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kernel / drivers / irqchip / Kconfig
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1# SPDX-License-Identifier: GPL-2.0-only 2menu "IRQ chip support" 3 4config IRQCHIP 5 def_bool y 6 depends on (OF_IRQ || ACPI_GENERIC_GSI) 7 8config ARM_GIC 9 bool 10 depends on OF 11 select IRQ_DOMAIN_HIERARCHY 12 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 13 14config ARM_GIC_PM 15 bool 16 depends on PM 17 select ARM_GIC 18 19config ARM_GIC_MAX_NR 20 int 21 depends on ARM_GIC 22 default 2 if ARCH_REALVIEW 23 default 1 24 25config ARM_GIC_V2M 26 bool 27 depends on PCI 28 select ARM_GIC 29 select IRQ_MSI_LIB 30 select PCI_MSI 31 select IRQ_MSI_IOMMU 32 33config GIC_NON_BANKED 34 bool 35 36config ARM_GIC_V3 37 bool 38 select IRQ_DOMAIN_HIERARCHY 39 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 40 select HAVE_ARM_SMCCC_DISCOVERY 41 select IRQ_MSI_IOMMU 42 43config ARM_GIC_ITS_PARENT 44 bool 45 46config ARM_GIC_V3_ITS 47 bool 48 select GENERIC_MSI_IRQ 49 select IRQ_MSI_LIB 50 select ARM_GIC_ITS_PARENT 51 default ARM_GIC_V3 52 select IRQ_MSI_IOMMU 53 54config ARM_GIC_V3_ITS_FSL_MC 55 bool 56 depends on ARM_GIC_V3_ITS 57 depends on FSL_MC_BUS 58 default ARM_GIC_V3_ITS 59 60config ARM_GIC_V5 61 bool 62 select IRQ_DOMAIN_HIERARCHY 63 select GENERIC_IRQ_EFFECTIVE_AFF_MASK 64 select GENERIC_MSI_IRQ 65 select IRQ_MSI_LIB 66 select ARM_GIC_ITS_PARENT 67 68config ARM_NVIC 69 bool 70 select IRQ_DOMAIN_HIERARCHY 71 select GENERIC_IRQ_CHIP 72 73config ARM_VIC 74 bool 75 select IRQ_DOMAIN 76 77config ARM_VIC_NR 78 int 79 default 4 if ARCH_S5PV210 80 default 2 81 depends on ARM_VIC 82 help 83 The maximum number of VICs available in the system, for 84 power management. 85 86config IRQ_MSI_LIB 87 bool 88 select GENERIC_MSI_IRQ 89 90config ARMADA_370_XP_IRQ 91 bool 92 select GENERIC_IRQ_CHIP 93 select PCI_MSI if PCI 94 select IRQ_MSI_LIB if PCI 95 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 96 97config ALPINE_MSI 98 bool 99 depends on PCI 100 select PCI_MSI 101 select IRQ_MSI_LIB 102 select GENERIC_IRQ_CHIP 103 104config AL_FIC 105 bool "Amazon's Annapurna Labs Fabric Interrupt Controller" 106 depends on OF 107 depends on HAS_IOMEM 108 select GENERIC_IRQ_CHIP 109 select IRQ_DOMAIN 110 help 111 Support Amazon's Annapurna Labs Fabric Interrupt Controller. 112 113config ATMEL_AIC_IRQ 114 bool 115 select GENERIC_IRQ_CHIP 116 select IRQ_DOMAIN 117 select SPARSE_IRQ 118 119config ATMEL_AIC5_IRQ 120 bool 121 select GENERIC_IRQ_CHIP 122 select IRQ_DOMAIN 123 select SPARSE_IRQ 124 125config I8259 126 bool 127 select IRQ_DOMAIN 128 129config BCM2712_MIP 130 tristate "Broadcom BCM2712 MSI-X Interrupt Peripheral support" 131 depends on ARCH_BRCMSTB || ARCH_BCM2835 || COMPILE_TEST 132 default m if ARCH_BRCMSTB || ARCH_BCM2835 133 depends on ARM_GIC 134 select GENERIC_IRQ_CHIP 135 select IRQ_DOMAIN_HIERARCHY 136 select GENERIC_MSI_IRQ 137 select IRQ_MSI_LIB 138 help 139 Enable support for the Broadcom BCM2712 MSI-X target peripheral 140 (MIP) needed by brcmstb PCIe to handle MSI-X interrupts on 141 Raspberry Pi 5. 142 143 If unsure say n. 144 145config BCM6345_L1_IRQ 146 bool 147 select GENERIC_IRQ_CHIP 148 select IRQ_DOMAIN 149 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 150 151config BCM7038_L1_IRQ 152 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver" 153 depends on ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST 154 default ARCH_BRCMSTB || BMIPS_GENERIC 155 select GENERIC_IRQ_CHIP 156 select IRQ_DOMAIN 157 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 158 159config BCM7120_L2_IRQ 160 tristate "Broadcom STB 7120-style L2 interrupt controller driver" 161 depends on ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST 162 default ARCH_BRCMSTB || BMIPS_GENERIC 163 select GENERIC_IRQ_CHIP 164 select IRQ_DOMAIN 165 166config BRCMSTB_L2_IRQ 167 tristate "Broadcom STB generic L2 interrupt controller driver" 168 depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST 169 default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC 170 select GENERIC_IRQ_CHIP 171 select IRQ_DOMAIN 172 173config DAVINCI_CP_INTC 174 bool 175 select GENERIC_IRQ_CHIP 176 select IRQ_DOMAIN 177 178config DW_APB_ICTL 179 bool 180 select GENERIC_IRQ_CHIP 181 select IRQ_DOMAIN_HIERARCHY 182 183config ECONET_EN751221_INTC 184 bool 185 select GENERIC_IRQ_CHIP 186 select IRQ_DOMAIN 187 188config FARADAY_FTINTC010 189 bool 190 select IRQ_DOMAIN 191 select SPARSE_IRQ 192 193config HISILICON_IRQ_MBIGEN 194 bool 195 select ARM_GIC_V3 196 select ARM_GIC_V3_ITS 197 198config IMGPDC_IRQ 199 bool 200 select GENERIC_IRQ_CHIP 201 select IRQ_DOMAIN 202 203config IXP4XX_IRQ 204 bool 205 select IRQ_DOMAIN 206 select SPARSE_IRQ 207 208config LAN966X_OIC 209 tristate "Microchip LAN966x OIC Support" 210 depends on MCHP_LAN966X_PCI || COMPILE_TEST 211 select GENERIC_IRQ_CHIP 212 select IRQ_DOMAIN 213 help 214 Enable support for the LAN966x Outbound Interrupt Controller. 215 This controller is present on the Microchip LAN966x PCI device and 216 maps the internal interrupts sources to PCIe interrupt. 217 218 To compile this driver as a module, choose M here: the module 219 will be called irq-lan966x-oic. 220 221config MADERA_IRQ 222 tristate 223 224config IRQ_MIPS_CPU 225 bool 226 select GENERIC_IRQ_CHIP 227 select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING 228 select IRQ_DOMAIN 229 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 230 231config CLPS711X_IRQCHIP 232 bool 233 depends on ARCH_CLPS711X 234 select IRQ_DOMAIN 235 select SPARSE_IRQ 236 default y 237 238config OMPIC 239 bool 240 241config OR1K_PIC 242 bool 243 select IRQ_DOMAIN 244 245config OMAP_IRQCHIP 246 bool 247 select GENERIC_IRQ_CHIP 248 select IRQ_DOMAIN 249 250config ORION_IRQCHIP 251 bool 252 select IRQ_DOMAIN 253 254config PIC32_EVIC 255 def_bool MACH_PIC32 || COMPILE_TEST 256 select GENERIC_IRQ_CHIP 257 select IRQ_DOMAIN 258 help 259 Enable support for the interrupt controller on the Microchip PIC32 260 family of platforms. 261 262config JCORE_AIC 263 bool "J-Core integrated AIC" if COMPILE_TEST 264 depends on OF 265 select IRQ_DOMAIN 266 help 267 Support for the J-Core integrated AIC. 268 269config RDA_INTC 270 bool 271 select IRQ_DOMAIN 272 273config RENESAS_INTC_IRQPIN 274 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST 275 select IRQ_DOMAIN 276 help 277 Enable support for the Renesas Interrupt Controller for external 278 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs. 279 280config RENESAS_IRQC 281 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST 282 select GENERIC_IRQ_CHIP 283 select IRQ_DOMAIN 284 help 285 Enable support for the Renesas Interrupt Controller for external 286 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs. 287 288config RENESAS_RZA1_IRQC 289 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST 290 select IRQ_DOMAIN_HIERARCHY 291 help 292 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up 293 to 8 external interrupts with configurable sense select. 294 295config RENESAS_RZG2L_IRQC 296 bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST 297 select GENERIC_IRQ_CHIP 298 select IRQ_DOMAIN_HIERARCHY 299 help 300 Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller 301 for external devices. 302 303config RENESAS_RZT2H_ICU 304 bool "Renesas RZ/{T2H,N2H} ICU support" if COMPILE_TEST 305 select GENERIC_IRQ_CHIP 306 select IRQ_DOMAIN_HIERARCHY 307 help 308 Enable support for the Renesas RZ/{T2H,N2H} Interrupt Controller 309 (ICU). 310 311config RENESAS_RZV2H_ICU 312 bool "Renesas RZ/V2H(P) ICU support" if COMPILE_TEST 313 select GENERIC_IRQ_CHIP 314 select IRQ_DOMAIN_HIERARCHY 315 help 316 Enable support for the Renesas RZ/V2H(P) Interrupt Control Unit (ICU) 317 318config SL28CPLD_INTC 319 bool "Kontron sl28cpld IRQ controller" 320 depends on MFD_SL28CPLD=y || COMPILE_TEST 321 select REGMAP_IRQ 322 help 323 Interrupt controller driver for the board management controller 324 found on the Kontron sl28 CPLD. 325 326config ST_IRQCHIP 327 bool 328 select REGMAP 329 select MFD_SYSCON 330 help 331 Enables SysCfg Controlled IRQs on STi based platforms. 332 333config SUN4I_INTC 334 bool 335 336config SUN6I_R_INTC 337 bool 338 select IRQ_DOMAIN_HIERARCHY 339 select IRQ_FASTEOI_HIERARCHY_HANDLERS 340 341config SUNXI_NMI_INTC 342 bool 343 select GENERIC_IRQ_CHIP 344 345config TB10X_IRQC 346 bool 347 select IRQ_DOMAIN 348 select GENERIC_IRQ_CHIP 349 350config TS4800_IRQ 351 tristate "TS-4800 IRQ controller" 352 select IRQ_DOMAIN 353 depends on HAS_IOMEM 354 depends on SOC_IMX51 || COMPILE_TEST 355 help 356 Support for the TS-4800 FPGA IRQ controller 357 358config VERSATILE_FPGA_IRQ 359 bool 360 select IRQ_DOMAIN 361 362config VERSATILE_FPGA_IRQ_NR 363 int 364 default 4 365 depends on VERSATILE_FPGA_IRQ 366 367config XTENSA_MX 368 bool 369 select IRQ_DOMAIN 370 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 371 372config XILINX_INTC 373 bool "Xilinx Interrupt Controller IP" 374 depends on OF_ADDRESS 375 select IRQ_DOMAIN 376 help 377 Support for the Xilinx Interrupt Controller IP core. 378 This is used as a primary controller with MicroBlaze and can also 379 be used as a secondary chained controller on other platforms. 380 381config IRQ_CROSSBAR 382 bool 383 help 384 Support for a CROSSBAR ip that precedes the main interrupt controller. 385 The primary irqchip invokes the crossbar's callback which inturn allocates 386 a free irq and configures the IP. Thus the peripheral interrupts are 387 routed to one of the free irqchip interrupt lines. 388 389config KEYSTONE_IRQ 390 tristate "Keystone 2 IRQ controller IP" 391 depends on ARCH_KEYSTONE 392 help 393 Support for Texas Instruments Keystone 2 IRQ controller IP which 394 is part of the Keystone 2 IPC mechanism 395 396config MIPS_GIC 397 bool 398 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 399 select GENERIC_IRQ_IPI if SMP 400 select IRQ_DOMAIN_HIERARCHY 401 select MIPS_CM 402 403config INGENIC_IRQ 404 bool 405 depends on MACH_INGENIC 406 default y 407 408config INGENIC_TCU_IRQ 409 bool "Ingenic JZ47xx TCU interrupt controller" 410 default MACH_INGENIC 411 depends on MIPS || COMPILE_TEST 412 select MFD_SYSCON 413 select GENERIC_IRQ_CHIP 414 help 415 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic 416 JZ47xx SoCs. 417 418 If unsure, say N. 419 420config IMX_GPCV2 421 bool 422 select IRQ_DOMAIN 423 help 424 Enables the wakeup IRQs for IMX platforms with GPCv2 block 425 426config IRQ_MXS 427 def_bool y if MACH_ASM9260 || ARCH_MXS 428 select IRQ_DOMAIN 429 select STMP_DEVICE 430 431config MSCC_OCELOT_IRQ 432 bool 433 select IRQ_DOMAIN 434 select GENERIC_IRQ_CHIP 435 436config MVEBU_GICP 437 select IRQ_MSI_LIB 438 bool 439 440config MVEBU_ICU 441 bool 442 443config MVEBU_ODMI 444 bool 445 select IRQ_MSI_LIB 446 select GENERIC_MSI_IRQ 447 448config MVEBU_PIC 449 bool 450 451config MVEBU_SEI 452 bool 453 454config LS_EXTIRQ 455 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 456 select MFD_SYSCON 457 458config LS_SCFG_MSI 459 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE 460 select IRQ_MSI_IOMMU 461 depends on PCI_MSI 462 select IRQ_MSI_LIB 463 464config STM32MP_EXTI 465 tristate "STM32MP extended interrupts and event controller" 466 depends on (ARCH_STM32 && !ARM_SINGLE_ARMV7M) || COMPILE_TEST 467 default ARCH_STM32 && !ARM_SINGLE_ARMV7M 468 select IRQ_DOMAIN_HIERARCHY 469 select GENERIC_IRQ_CHIP 470 help 471 Support STM32MP EXTI (extended interrupts and event) controller. 472 473config STM32_EXTI 474 bool 475 select IRQ_DOMAIN 476 select GENERIC_IRQ_CHIP 477 478config QCOM_IRQ_COMBINER 479 bool "QCOM IRQ combiner support" 480 depends on ARCH_QCOM && ACPI 481 select IRQ_DOMAIN_HIERARCHY 482 help 483 Say yes here to add support for the IRQ combiner devices embedded 484 in Qualcomm Technologies chips. 485 486config IRQ_UNIPHIER_AIDET 487 bool "UniPhier AIDET support" if COMPILE_TEST 488 depends on ARCH_UNIPHIER || COMPILE_TEST 489 default ARCH_UNIPHIER 490 select IRQ_DOMAIN_HIERARCHY 491 help 492 Support for the UniPhier AIDET (ARM Interrupt Detector). 493 494config MESON_IRQ_GPIO 495 tristate "Meson GPIO Interrupt Multiplexer" 496 depends on ARCH_MESON || COMPILE_TEST 497 default ARCH_MESON 498 select IRQ_DOMAIN_HIERARCHY 499 help 500 Support Meson SoC Family GPIO Interrupt Multiplexer 501 502config GOLDFISH_PIC 503 bool "Goldfish programmable interrupt controller" 504 depends on MIPS && (GOLDFISH || COMPILE_TEST) 505 select GENERIC_IRQ_CHIP 506 select IRQ_DOMAIN 507 help 508 Say yes here to enable Goldfish interrupt controller driver used 509 for Goldfish based virtual platforms. 510 511config QCOM_PDC 512 tristate "QCOM PDC" 513 depends on ARCH_QCOM 514 select IRQ_DOMAIN_HIERARCHY 515 help 516 Power Domain Controller driver to manage and configure wakeup 517 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 518 519config QCOM_MPM 520 tristate "QCOM MPM" 521 depends on ARCH_QCOM 522 depends on MAILBOX 523 select IRQ_DOMAIN_HIERARCHY 524 help 525 MSM Power Manager driver to manage and configure wakeup 526 IRQs for Qualcomm Technologies Inc (QTI) mobile chips. 527 528config CSKY_MPINTC 529 bool 530 depends on CSKY 531 help 532 Say yes here to enable C-SKY SMP interrupt controller driver used 533 for C-SKY SMP system. 534 In fact it's not mmio map in hardware and it uses ld/st to visit the 535 controller's register inside CPU. 536 537config CSKY_APB_INTC 538 bool "C-SKY APB Interrupt Controller" 539 depends on CSKY 540 help 541 Say yes here to enable C-SKY APB interrupt controller driver used 542 by C-SKY single core SOC system. It uses mmio map apb-bus to visit 543 the controller's register. 544 545config IMX_IRQSTEER 546 bool "i.MX IRQSTEER support" 547 depends on ARCH_MXC || ARCH_S32 || COMPILE_TEST 548 default y if ARCH_MXC || ARCH_S32 549 select IRQ_DOMAIN 550 help 551 Support for the i.MX and S32 IRQSTEER interrupt multiplexer/remapper. 552 553config IMX_INTMUX 554 bool "i.MX INTMUX support" if COMPILE_TEST 555 default y if ARCH_MXC 556 select IRQ_DOMAIN 557 help 558 Support for the i.MX INTMUX interrupt multiplexer. 559 560config IMX_MU_MSI 561 tristate "i.MX MU used as MSI controller" 562 depends on OF && HAS_IOMEM 563 depends on ARCH_MXC || COMPILE_TEST 564 depends on ARM || ARM64 565 default m if ARCH_MXC 566 select IRQ_DOMAIN 567 select IRQ_DOMAIN_HIERARCHY 568 select GENERIC_MSI_IRQ 569 select IRQ_MSI_LIB 570 help 571 Provide a driver for the i.MX Messaging Unit block used as a 572 CPU-to-CPU MSI controller. This requires a specially crafted DT 573 to make use of this driver. 574 575 If unsure, say N 576 577config LS1X_IRQ 578 bool "Loongson-1 Interrupt Controller" 579 depends on MACH_LOONGSON32 580 default y 581 select IRQ_DOMAIN 582 select GENERIC_IRQ_CHIP 583 help 584 Support for the Loongson-1 platform Interrupt Controller. 585 586config TI_SCI_INTR_IRQCHIP 587 tristate "TI SCI INTR Interrupt Controller" 588 depends on TI_SCI_PROTOCOL 589 depends on ARCH_K3 || COMPILE_TEST 590 select IRQ_DOMAIN_HIERARCHY 591 help 592 This enables the irqchip driver support for K3 Interrupt router 593 over TI System Control Interface available on some new TI's SoCs. 594 If you wish to use interrupt router irq resources managed by the 595 TI System Controller, say Y here. Otherwise, say N. 596 597config TI_SCI_INTA_IRQCHIP 598 tristate "TI SCI INTA Interrupt Controller" 599 depends on TI_SCI_PROTOCOL 600 depends on ARCH_K3 || (COMPILE_TEST && ARM64) 601 select IRQ_DOMAIN_HIERARCHY 602 select TI_SCI_INTA_MSI_DOMAIN 603 help 604 This enables the irqchip driver support for K3 Interrupt aggregator 605 over TI System Control Interface available on some new TI's SoCs. 606 If you wish to use interrupt aggregator irq resources managed by the 607 TI System Controller, say Y here. Otherwise, say N. 608 609config TI_PRUSS_INTC 610 tristate 611 depends on TI_PRUSS 612 default TI_PRUSS 613 select IRQ_DOMAIN 614 help 615 This enables support for the PRU-ICSS Local Interrupt Controller 616 present within a PRU-ICSS subsystem present on various TI SoCs. 617 The PRUSS INTC enables various interrupts to be routed to multiple 618 different processors within the SoC. 619 620config RISCV_INTC 621 bool 622 depends on RISCV 623 select IRQ_DOMAIN_HIERARCHY 624 625config RISCV_APLIC 626 bool 627 depends on RISCV 628 select IRQ_DOMAIN_HIERARCHY 629 630config RISCV_APLIC_MSI 631 bool 632 depends on RISCV_APLIC 633 select GENERIC_MSI_IRQ 634 default RISCV_APLIC 635 636config RISCV_IMSIC 637 bool 638 depends on RISCV 639 select IRQ_DOMAIN_HIERARCHY 640 select GENERIC_IRQ_MATRIX_ALLOCATOR 641 select GENERIC_MSI_IRQ 642 select IRQ_MSI_LIB 643 644config RISCV_RPMI_SYSMSI 645 bool 646 depends on RISCV && MAILBOX 647 select IRQ_DOMAIN_HIERARCHY 648 select GENERIC_MSI_IRQ 649 default RISCV 650 651config SIFIVE_PLIC 652 bool 653 depends on RISCV 654 select IRQ_DOMAIN_HIERARCHY 655 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 656 657config STARFIVE_JH8100_INTC 658 bool "StarFive JH8100 External Interrupt Controller" 659 depends on ARCH_STARFIVE || COMPILE_TEST 660 default ARCH_STARFIVE 661 select IRQ_DOMAIN_HIERARCHY 662 help 663 This enables support for the INTC chip found in StarFive JH8100 664 SoC. 665 666 If you don't know what to do here, say Y. 667 668config ACLINT_SSWI 669 bool "RISC-V ACLINT S-mode IPI Interrupt Controller" 670 depends on RISCV 671 depends on SMP 672 select IRQ_DOMAIN_HIERARCHY 673 select GENERIC_IRQ_IPI_MUX 674 help 675 This enables support for variants of the RISC-V ACLINT-SSWI device. 676 Supported variants are: 677 - T-HEAD, with compatible "thead,c900-aclint-sswi" 678 - MIPS P8700, with compatible "mips,p8700-aclint-sswi" 679 680 If you don't know what to do here, say Y. 681 682# Backwards compatibility so oldconfig does not drop it. 683config THEAD_C900_ACLINT_SSWI 684 bool 685 select ACLINT_SSWI 686 687config EXYNOS_IRQ_COMBINER 688 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST 689 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST 690 help 691 Say yes here to add support for the IRQ combiner devices embedded 692 in Samsung Exynos chips. 693 694config IRQ_LOONGARCH_CPU 695 bool 696 select GENERIC_IRQ_CHIP 697 select IRQ_DOMAIN 698 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP 699 select LOONGSON_HTVEC 700 select LOONGSON_LIOINTC 701 select LOONGSON_EIOINTC 702 select LOONGSON_PCH_PIC 703 select LOONGSON_PCH_MSI 704 select LOONGSON_PCH_LPC 705 help 706 Support for the LoongArch CPU Interrupt Controller. For details of 707 irq chip hierarchy on LoongArch platforms please read the document 708 Documentation/arch/loongarch/irq-chip-model.rst. 709 710config LOONGSON_LIOINTC 711 bool "Loongson Local I/O Interrupt Controller" 712 depends on MACH_LOONGSON64 || LOONGARCH 713 default y 714 select IRQ_DOMAIN 715 select GENERIC_IRQ_CHIP 716 help 717 Support for the Loongson Local I/O Interrupt Controller. 718 719config LOONGSON_EIOINTC 720 bool "Loongson Extend I/O Interrupt Controller" 721 depends on LOONGARCH 722 default MACH_LOONGSON64 723 select IRQ_DOMAIN_HIERARCHY 724 select GENERIC_IRQ_CHIP 725 help 726 Support for the Loongson3 Extend I/O Interrupt Vector Controller. 727 728config LOONGSON_HTPIC 729 bool "Loongson3 HyperTransport PIC Controller" 730 depends on MACH_LOONGSON64 && MIPS 731 default y 732 select IRQ_DOMAIN 733 select GENERIC_IRQ_CHIP 734 help 735 Support for the Loongson-3 HyperTransport PIC Controller. 736 737config LOONGSON_HTVEC 738 bool "Loongson HyperTransport Interrupt Vector Controller" 739 depends on MACH_LOONGSON64 || LOONGARCH 740 default MACH_LOONGSON64 741 select IRQ_DOMAIN_HIERARCHY 742 help 743 Support for the Loongson HyperTransport Interrupt Vector Controller. 744 745config LOONGSON_PCH_PIC 746 bool "Loongson PCH PIC Controller" 747 depends on MACH_LOONGSON64 || LOONGARCH 748 default MACH_LOONGSON64 749 select IRQ_DOMAIN_HIERARCHY 750 select IRQ_FASTEOI_HIERARCHY_HANDLERS 751 help 752 Support for the Loongson PCH PIC Controller. 753 754config LOONGSON_PCH_MSI 755 bool "Loongson PCH MSI Controller" 756 depends on MACH_LOONGSON64 || LOONGARCH 757 depends on PCI 758 default MACH_LOONGSON64 759 select IRQ_DOMAIN_HIERARCHY 760 select IRQ_MSI_LIB 761 select PCI_MSI 762 help 763 Support for the Loongson PCH MSI Controller. 764 765config LOONGSON_PCH_LPC 766 bool "Loongson PCH LPC Controller" 767 depends on MACH_LOONGSON64 || LOONGARCH 768 default MACH_LOONGSON64 769 select IRQ_DOMAIN_HIERARCHY 770 help 771 Support for the Loongson PCH LPC Controller. 772 773config MST_IRQ 774 bool "MStar Interrupt Controller" 775 depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST 776 default ARCH_MEDIATEK 777 select IRQ_DOMAIN 778 select IRQ_DOMAIN_HIERARCHY 779 help 780 Support MStar Interrupt Controller. 781 782config WPCM450_AIC 783 bool "Nuvoton WPCM450 Advanced Interrupt Controller" 784 depends on ARCH_WPCM450 785 help 786 Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC. 787 788config IRQ_IDT3243X 789 bool 790 select GENERIC_IRQ_CHIP 791 select IRQ_DOMAIN 792 793config APPLE_AIC 794 bool "Apple Interrupt Controller (AIC)" 795 depends on ARM64 796 depends on ARCH_APPLE || COMPILE_TEST 797 select GENERIC_IRQ_IPI_MUX 798 help 799 Support for the Apple Interrupt Controller found on Apple Silicon SoCs, 800 such as the M1. 801 802config MCHP_EIC 803 bool "Microchip External Interrupt Controller" 804 depends on ARCH_AT91 || COMPILE_TEST 805 select IRQ_DOMAIN 806 select IRQ_DOMAIN_HIERARCHY 807 help 808 Support for Microchip External Interrupt Controller. 809 810config SOPHGO_SG2042_MSI 811 bool "Sophgo SG2042 MSI Controller" 812 depends on ARCH_SOPHGO || COMPILE_TEST 813 depends on PCI 814 select IRQ_DOMAIN_HIERARCHY 815 select IRQ_MSI_LIB 816 select PCI_MSI 817 help 818 Support for the Sophgo SG2042 MSI Controller. 819 This on-chip interrupt controller enables MSI sources to be 820 routed to the primary PLIC controller on SoC. 821 822config SUNPLUS_SP7021_INTC 823 bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST 824 default SOC_SP7021 825 help 826 Support for the Sunplus SP7021 Interrupt Controller IP core. 827 SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a 828 chained controller, routing all interrupt source in P-Chip to 829 the primary controller on C-Chip. 830 831endmenu