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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Broadcom BCM7120 style Level 2 interrupt controller driver
4 *
5 * Copyright (C) 2014 Broadcom Corporation
6 */
7
8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
10#include <linux/init.h>
11#include <linux/slab.h>
12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/platform_device.h>
15#include <linux/of.h>
16#include <linux/of_irq.h>
17#include <linux/of_address.h>
18#include <linux/of_platform.h>
19#include <linux/interrupt.h>
20#include <linux/irq.h>
21#include <linux/io.h>
22#include <linux/irqdomain.h>
23#include <linux/reboot.h>
24#include <linux/bitops.h>
25#include <linux/irqchip.h>
26#include <linux/irqchip/chained_irq.h>
27
28/* Register offset in the L2 interrupt controller */
29#define IRQEN 0x00
30#define IRQSTAT 0x04
31
32#define MAX_WORDS 4
33#define MAX_MAPPINGS (MAX_WORDS * 2)
34#define IRQS_PER_WORD 32
35
36struct bcm7120_l1_intc_data {
37 struct bcm7120_l2_intc_data *b;
38 u32 irq_map_mask[MAX_WORDS];
39};
40
41struct bcm7120_l2_intc_data {
42 unsigned int n_words;
43 void __iomem *map_base[MAX_MAPPINGS];
44 void __iomem *pair_base[MAX_WORDS];
45 int en_offset[MAX_WORDS];
46 int stat_offset[MAX_WORDS];
47 struct irq_domain *domain;
48 bool can_wake;
49 u32 irq_fwd_mask[MAX_WORDS];
50 struct bcm7120_l1_intc_data *l1_data;
51 int num_parent_irqs;
52 const __be32 *map_mask_prop;
53};
54
55static void bcm7120_l2_intc_irq_handle(struct irq_desc *desc)
56{
57 struct bcm7120_l1_intc_data *data = irq_desc_get_handler_data(desc);
58 struct bcm7120_l2_intc_data *b = data->b;
59 struct irq_chip *chip = irq_desc_get_chip(desc);
60 unsigned int idx;
61
62 chained_irq_enter(chip, desc);
63
64 for (idx = 0; idx < b->n_words; idx++) {
65 int base = idx * IRQS_PER_WORD;
66 struct irq_chip_generic *gc;
67 unsigned long pending;
68 int hwirq;
69
70 gc = irq_get_domain_generic_chip(b->domain, base);
71 scoped_guard (raw_spinlock, &gc->lock) {
72 pending = irq_reg_readl(gc, b->stat_offset[idx]) & gc->mask_cache &
73 data->irq_map_mask[idx];
74 }
75
76 for_each_set_bit(hwirq, &pending, IRQS_PER_WORD)
77 generic_handle_domain_irq(b->domain, base + hwirq);
78 }
79
80 chained_irq_exit(chip, desc);
81}
82
83static void bcm7120_l2_intc_suspend(struct irq_chip_generic *gc)
84{
85 struct bcm7120_l2_intc_data *b = gc->private;
86 struct irq_chip_type *ct = gc->chip_types;
87
88 guard(raw_spinlock)(&gc->lock);
89 if (b->can_wake)
90 irq_reg_writel(gc, gc->mask_cache | gc->wake_active, ct->regs.mask);
91}
92
93static void bcm7120_l2_intc_resume(struct irq_chip_generic *gc)
94{
95 struct irq_chip_type *ct = gc->chip_types;
96
97 /* Restore the saved mask */
98 guard(raw_spinlock)(&gc->lock);
99 irq_reg_writel(gc, gc->mask_cache, ct->regs.mask);
100}
101
102static int bcm7120_l2_intc_init_one(struct device_node *dn,
103 struct bcm7120_l2_intc_data *data,
104 int irq, u32 *valid_mask)
105{
106 struct bcm7120_l1_intc_data *l1_data = &data->l1_data[irq];
107 int parent_irq;
108 unsigned int idx;
109
110 parent_irq = irq_of_parse_and_map(dn, irq);
111 if (!parent_irq) {
112 pr_err("failed to map interrupt %d\n", irq);
113 return -EINVAL;
114 }
115
116 /* For multiple parent IRQs with multiple words, this looks like:
117 * <irq0_w0 irq0_w1 irq1_w0 irq1_w1 ...>
118 *
119 * We need to associate a given parent interrupt with its corresponding
120 * map_mask in order to mask the status register with it because we
121 * have the same handler being called for multiple parent interrupts.
122 *
123 * This is typically something needed on BCM7xxx (STB chips).
124 */
125 for (idx = 0; idx < data->n_words; idx++) {
126 if (data->map_mask_prop) {
127 l1_data->irq_map_mask[idx] |=
128 be32_to_cpup(data->map_mask_prop +
129 irq * data->n_words + idx);
130 } else {
131 l1_data->irq_map_mask[idx] = 0xffffffff;
132 }
133 valid_mask[idx] |= l1_data->irq_map_mask[idx];
134 }
135
136 l1_data->b = data;
137
138 irq_set_chained_handler_and_data(parent_irq,
139 bcm7120_l2_intc_irq_handle, l1_data);
140 if (data->can_wake)
141 enable_irq_wake(parent_irq);
142
143 return 0;
144}
145
146static int bcm7120_l2_intc_iomap_7120(struct device_node *dn, struct bcm7120_l2_intc_data *data)
147{
148 int ret;
149
150 data->map_base[0] = of_iomap(dn, 0);
151 if (!data->map_base[0]) {
152 pr_err("unable to map registers\n");
153 return -ENOMEM;
154 }
155
156 data->pair_base[0] = data->map_base[0];
157 data->en_offset[0] = IRQEN;
158 data->stat_offset[0] = IRQSTAT;
159 data->n_words = 1;
160
161 ret = of_property_read_u32_array(dn, "brcm,int-fwd-mask",
162 data->irq_fwd_mask, data->n_words);
163 if (ret != 0 && ret != -EINVAL) {
164 /* property exists but has the wrong number of words */
165 pr_err("invalid brcm,int-fwd-mask property\n");
166 return -EINVAL;
167 }
168
169 data->map_mask_prop = of_get_property(dn, "brcm,int-map-mask", &ret);
170 if (!data->map_mask_prop ||
171 (ret != (sizeof(__be32) * data->num_parent_irqs * data->n_words))) {
172 pr_err("invalid brcm,int-map-mask property\n");
173 return -EINVAL;
174 }
175
176 return 0;
177}
178
179static int bcm7120_l2_intc_iomap_3380(struct device_node *dn, struct bcm7120_l2_intc_data *data)
180{
181 unsigned int gc_idx;
182
183 for (gc_idx = 0; gc_idx < MAX_WORDS; gc_idx++) {
184 unsigned int map_idx = gc_idx * 2;
185 void __iomem *en = of_iomap(dn, map_idx + 0);
186 void __iomem *stat = of_iomap(dn, map_idx + 1);
187 void __iomem *base = min(en, stat);
188
189 data->map_base[map_idx + 0] = en;
190 data->map_base[map_idx + 1] = stat;
191
192 if (!base)
193 break;
194
195 data->pair_base[gc_idx] = base;
196 data->en_offset[gc_idx] = en - base;
197 data->stat_offset[gc_idx] = stat - base;
198 }
199
200 if (!gc_idx) {
201 pr_err("unable to map registers\n");
202 return -EINVAL;
203 }
204
205 data->n_words = gc_idx;
206 return 0;
207}
208
209static int bcm7120_l2_intc_probe(struct platform_device *pdev, struct device_node *parent,
210 int (*iomap_regs_fn)(struct device_node *,
211 struct bcm7120_l2_intc_data *),
212 const char *intc_name)
213{
214 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
215 struct device_node *dn = pdev->dev.of_node;
216 struct bcm7120_l2_intc_data *data;
217 struct irq_chip_generic *gc;
218 struct irq_chip_type *ct;
219 int ret = 0;
220 unsigned int idx, irq, flags;
221 u32 valid_mask[MAX_WORDS] = { };
222
223 data = kzalloc_obj(*data);
224 if (!data)
225 return -ENOMEM;
226
227 data->num_parent_irqs = platform_irq_count(pdev);
228 if (data->num_parent_irqs <= 0) {
229 pr_err("invalid number of parent interrupts\n");
230 ret = -ENOMEM;
231 goto out_unmap;
232 }
233
234 data->l1_data = kzalloc_objs(*data->l1_data, data->num_parent_irqs);
235 if (!data->l1_data) {
236 ret = -ENOMEM;
237 goto out_free_l1_data;
238 }
239
240 ret = iomap_regs_fn(dn, data);
241 if (ret < 0)
242 goto out_free_l1_data;
243
244 data->can_wake = of_property_read_bool(dn, "brcm,irq-can-wake");
245
246 for (irq = 0; irq < data->num_parent_irqs; irq++) {
247 ret = bcm7120_l2_intc_init_one(dn, data, irq, valid_mask);
248 if (ret)
249 goto out_free_l1_data;
250 }
251
252 data->domain = irq_domain_create_linear(of_fwnode_handle(dn), IRQS_PER_WORD * data->n_words,
253 &irq_generic_chip_ops, NULL);
254 if (!data->domain) {
255 ret = -ENOMEM;
256 goto out_free_l1_data;
257 }
258
259 /* MIPS chips strapped for BE will automagically configure the
260 * peripheral registers for CPU-native byte order.
261 */
262 flags = IRQ_GC_INIT_MASK_CACHE;
263 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
264 flags |= IRQ_GC_BE_IO;
265
266 ret = irq_alloc_domain_generic_chips(data->domain, IRQS_PER_WORD, 1,
267 dn->full_name, handle_level_irq, clr,
268 IRQ_LEVEL, flags);
269 if (ret) {
270 pr_err("failed to allocate generic irq chip\n");
271 goto out_free_domain;
272 }
273
274 for (idx = 0; idx < data->n_words; idx++) {
275 irq = idx * IRQS_PER_WORD;
276 gc = irq_get_domain_generic_chip(data->domain, irq);
277
278 gc->unused = 0xffffffff & ~valid_mask[idx];
279 gc->private = data;
280 ct = gc->chip_types;
281
282 gc->reg_base = data->pair_base[idx];
283 ct->regs.mask = data->en_offset[idx];
284
285 /* gc->reg_base is defined and so is gc->writel */
286 irq_reg_writel(gc, data->irq_fwd_mask[idx],
287 data->en_offset[idx]);
288
289 ct->chip.irq_mask = irq_gc_mask_clr_bit;
290 ct->chip.irq_unmask = irq_gc_mask_set_bit;
291 ct->chip.irq_ack = irq_gc_noop;
292 gc->suspend = bcm7120_l2_intc_suspend;
293 gc->resume = bcm7120_l2_intc_resume;
294
295 /*
296 * Initialize mask-cache, in case we need it for
297 * saving/restoring fwd mask even w/o any child interrupts
298 * installed
299 */
300 gc->mask_cache = irq_reg_readl(gc, ct->regs.mask);
301
302 if (data->can_wake) {
303 /* This IRQ chip can wake the system, set all
304 * relevant child interrupts in wake_enabled mask
305 */
306 gc->wake_enabled = 0xffffffff;
307 gc->wake_enabled &= ~gc->unused;
308 ct->chip.irq_set_wake = irq_gc_set_wake;
309 }
310 }
311
312 pr_info("registered %s intc (%pOF, parent IRQ(s): %d)\n",
313 intc_name, dn, data->num_parent_irqs);
314
315 return 0;
316
317out_free_domain:
318 irq_domain_remove(data->domain);
319out_free_l1_data:
320 kfree(data->l1_data);
321out_unmap:
322 for (idx = 0; idx < MAX_MAPPINGS; idx++) {
323 if (data->map_base[idx])
324 iounmap(data->map_base[idx]);
325 }
326 kfree(data);
327 return ret;
328}
329
330static int bcm7120_l2_intc_probe_7120(struct platform_device *pdev, struct device_node *parent)
331{
332 return bcm7120_l2_intc_probe(pdev, parent, bcm7120_l2_intc_iomap_7120,
333 "BCM7120 L2");
334}
335
336static int bcm7120_l2_intc_probe_3380(struct platform_device *pdev, struct device_node *parent)
337{
338 return bcm7120_l2_intc_probe(pdev, parent, bcm7120_l2_intc_iomap_3380,
339 "BCM3380 L2");
340}
341
342IRQCHIP_PLATFORM_DRIVER_BEGIN(bcm7120_l2)
343IRQCHIP_MATCH("brcm,bcm7120-l2-intc", bcm7120_l2_intc_probe_7120)
344IRQCHIP_MATCH("brcm,bcm3380-l2-intc", bcm7120_l2_intc_probe_3380)
345IRQCHIP_PLATFORM_DRIVER_END(bcm7120_l2)
346MODULE_DESCRIPTION("Broadcom STB 7120-style L2 interrupt controller driver");
347MODULE_LICENSE("GPL v2");