Linux kernel mirror (for testing)
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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * linux/arch/arm/common/vic.c
4 *
5 * Copyright (C) 1999 - 2003 ARM Limited
6 * Copyright (C) 2000 Deep Blue Solutions Ltd
7 */
8
9#include <linux/export.h>
10#include <linux/init.h>
11#include <linux/list.h>
12#include <linux/io.h>
13#include <linux/irq.h>
14#include <linux/irqchip.h>
15#include <linux/irqchip/chained_irq.h>
16#include <linux/irqdomain.h>
17#include <linux/of.h>
18#include <linux/of_address.h>
19#include <linux/of_irq.h>
20#include <linux/syscore_ops.h>
21#include <linux/device.h>
22#include <linux/amba/bus.h>
23#include <linux/irqchip/arm-vic.h>
24
25#include <asm/exception.h>
26#include <asm/irq.h>
27
28#define VIC_IRQ_STATUS 0x00
29#define VIC_FIQ_STATUS 0x04
30#define VIC_RAW_STATUS 0x08
31#define VIC_INT_SELECT 0x0c /* 1 = FIQ, 0 = IRQ */
32#define VIC_INT_ENABLE 0x10 /* 1 = enable, 0 = disable */
33#define VIC_INT_ENABLE_CLEAR 0x14
34#define VIC_INT_SOFT 0x18
35#define VIC_INT_SOFT_CLEAR 0x1c
36#define VIC_PROTECT 0x20
37#define VIC_PL190_VECT_ADDR 0x30 /* PL190 only */
38#define VIC_PL190_DEF_VECT_ADDR 0x34 /* PL190 only */
39
40#define VIC_VECT_ADDR0 0x100 /* 0 to 15 (0..31 PL192) */
41#define VIC_VECT_CNTL0 0x200 /* 0 to 15 (0..31 PL192) */
42#define VIC_ITCR 0x300 /* VIC test control register */
43
44#define VIC_VECT_CNTL_ENABLE (1 << 5)
45
46#define VIC_PL192_VECT_ADDR 0xF00
47
48/**
49 * struct vic_device - VIC PM device
50 * @base: The register base for the VIC.
51 * @irq: The IRQ number for the base of the VIC.
52 * @valid_sources: A bitmask of valid interrupts
53 * @resume_sources: A bitmask of interrupts for resume.
54 * @resume_irqs: The IRQs enabled for resume.
55 * @int_select: Save for VIC_INT_SELECT.
56 * @int_enable: Save for VIC_INT_ENABLE.
57 * @soft_int: Save for VIC_INT_SOFT.
58 * @protect: Save for VIC_PROTECT.
59 * @domain: The IRQ domain for the VIC.
60 */
61struct vic_device {
62 void __iomem *base;
63 int irq;
64 u32 valid_sources;
65 u32 resume_sources;
66 u32 resume_irqs;
67 u32 int_select;
68 u32 int_enable;
69 u32 soft_int;
70 u32 protect;
71 struct irq_domain *domain;
72};
73
74/* we cannot allocate memory when VICs are initially registered */
75static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];
76
77static int vic_id;
78
79static void vic_handle_irq(struct pt_regs *regs);
80
81/**
82 * vic_init2 - common initialisation code
83 * @base: Base of the VIC.
84 *
85 * Common initialisation code for registration
86 * and resume.
87*/
88static void vic_init2(void __iomem *base)
89{
90 int i;
91
92 for (i = 0; i < 16; i++) {
93 void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
94 writel(VIC_VECT_CNTL_ENABLE | i, reg);
95 }
96
97 writel(32, base + VIC_PL190_DEF_VECT_ADDR);
98}
99
100#ifdef CONFIG_PM
101static void resume_one_vic(struct vic_device *vic)
102{
103 void __iomem *base = vic->base;
104
105 printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base);
106
107 /* re-initialise static settings */
108 vic_init2(base);
109
110 writel(vic->int_select, base + VIC_INT_SELECT);
111 writel(vic->protect, base + VIC_PROTECT);
112
113 /* set the enabled ints and then clear the non-enabled */
114 writel(vic->int_enable, base + VIC_INT_ENABLE);
115 writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR);
116
117 /* and the same for the soft-int register */
118
119 writel(vic->soft_int, base + VIC_INT_SOFT);
120 writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR);
121}
122
123static void vic_resume(void *data)
124{
125 int id;
126
127 for (id = vic_id - 1; id >= 0; id--)
128 resume_one_vic(vic_devices + id);
129}
130
131static void suspend_one_vic(struct vic_device *vic)
132{
133 void __iomem *base = vic->base;
134
135 printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base);
136
137 vic->int_select = readl(base + VIC_INT_SELECT);
138 vic->int_enable = readl(base + VIC_INT_ENABLE);
139 vic->soft_int = readl(base + VIC_INT_SOFT);
140 vic->protect = readl(base + VIC_PROTECT);
141
142 /* set the interrupts (if any) that are used for
143 * resuming the system */
144
145 writel(vic->resume_irqs, base + VIC_INT_ENABLE);
146 writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR);
147}
148
149static int vic_suspend(void *data)
150{
151 int id;
152
153 for (id = 0; id < vic_id; id++)
154 suspend_one_vic(vic_devices + id);
155
156 return 0;
157}
158
159static const struct syscore_ops vic_syscore_ops = {
160 .suspend = vic_suspend,
161 .resume = vic_resume,
162};
163
164static struct syscore vic_syscore = {
165 .ops = &vic_syscore_ops,
166};
167
168/**
169 * vic_pm_init - initcall to register VIC pm
170 *
171 * This is called via late_initcall() to register
172 * the resources for the VICs due to the early
173 * nature of the VIC's registration.
174*/
175static int __init vic_pm_init(void)
176{
177 if (vic_id > 0)
178 register_syscore(&vic_syscore);
179
180 return 0;
181}
182late_initcall(vic_pm_init);
183#endif /* CONFIG_PM */
184
185static struct irq_chip vic_chip;
186
187static int vic_irqdomain_map(struct irq_domain *d, unsigned int irq,
188 irq_hw_number_t hwirq)
189{
190 struct vic_device *v = d->host_data;
191
192 /* Skip invalid IRQs, only register handlers for the real ones */
193 if (!(v->valid_sources & (1 << hwirq)))
194 return -EPERM;
195 irq_set_chip_and_handler(irq, &vic_chip, handle_level_irq);
196 irq_set_chip_data(irq, v->base);
197 irq_set_probe(irq);
198 return 0;
199}
200
201/*
202 * Handle each interrupt in a single VIC. Returns non-zero if we've
203 * handled at least one interrupt. This reads the status register
204 * before handling each interrupt, which is necessary given that
205 * handle_IRQ may briefly re-enable interrupts for soft IRQ handling.
206 */
207static int handle_one_vic(struct vic_device *vic, struct pt_regs *regs)
208{
209 u32 stat, irq;
210 int handled = 0;
211
212 while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) {
213 irq = ffs(stat) - 1;
214 generic_handle_domain_irq(vic->domain, irq);
215 handled = 1;
216 }
217
218 return handled;
219}
220
221static void vic_handle_irq_cascaded(struct irq_desc *desc)
222{
223 u32 stat, hwirq;
224 struct irq_chip *host_chip = irq_desc_get_chip(desc);
225 struct vic_device *vic = irq_desc_get_handler_data(desc);
226
227 chained_irq_enter(host_chip, desc);
228
229 while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) {
230 hwirq = ffs(stat) - 1;
231 generic_handle_domain_irq(vic->domain, hwirq);
232 }
233
234 chained_irq_exit(host_chip, desc);
235}
236
237/*
238 * Keep iterating over all registered VIC's until there are no pending
239 * interrupts.
240 */
241static void __exception_irq_entry vic_handle_irq(struct pt_regs *regs)
242{
243 int i, handled;
244
245 do {
246 for (i = 0, handled = 0; i < vic_id; ++i)
247 handled |= handle_one_vic(&vic_devices[i], regs);
248 } while (handled);
249}
250
251static const struct irq_domain_ops vic_irqdomain_ops = {
252 .map = vic_irqdomain_map,
253 .xlate = irq_domain_xlate_onetwocell,
254};
255
256/**
257 * vic_register() - Register a VIC.
258 * @base: The base address of the VIC.
259 * @parent_irq: The parent IRQ if cascaded, else 0.
260 * @irq: The base IRQ for the VIC.
261 * @valid_sources: bitmask of valid interrupts
262 * @resume_sources: bitmask of interrupts allowed for resume sources.
263 * @node: The device tree node associated with the VIC.
264 *
265 * Register the VIC with the system device tree so that it can be notified
266 * of suspend and resume requests and ensure that the correct actions are
267 * taken to re-instate the settings on resume.
268 *
269 * This also configures the IRQ domain for the VIC.
270 */
271static void __init vic_register(void __iomem *base, unsigned int parent_irq,
272 unsigned int irq,
273 u32 valid_sources, u32 resume_sources,
274 struct device_node *node)
275{
276 struct vic_device *v;
277 int i;
278
279 if (vic_id >= ARRAY_SIZE(vic_devices)) {
280 printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
281 return;
282 }
283
284 v = &vic_devices[vic_id];
285 v->base = base;
286 v->valid_sources = valid_sources;
287 v->resume_sources = resume_sources;
288 set_handle_irq(vic_handle_irq);
289 vic_id++;
290
291 if (parent_irq) {
292 irq_set_chained_handler_and_data(parent_irq,
293 vic_handle_irq_cascaded, v);
294 }
295
296 v->domain = irq_domain_create_simple(of_fwnode_handle(node),
297 fls(valid_sources), irq,
298 &vic_irqdomain_ops, v);
299 /* create an IRQ mapping for each valid IRQ */
300 for (i = 0; i < fls(valid_sources); i++)
301 if (valid_sources & (1 << i))
302 irq_create_mapping(v->domain, i);
303 /* If no base IRQ was passed, figure out our allocated base */
304 if (irq)
305 v->irq = irq;
306 else
307 v->irq = irq_find_mapping(v->domain, 0);
308}
309
310static void vic_ack_irq(struct irq_data *d)
311{
312 void __iomem *base = irq_data_get_irq_chip_data(d);
313 unsigned int irq = d->hwirq;
314 writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
315 /* moreover, clear the soft-triggered, in case it was the reason */
316 writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
317}
318
319static void vic_mask_irq(struct irq_data *d)
320{
321 void __iomem *base = irq_data_get_irq_chip_data(d);
322 unsigned int irq = d->hwirq;
323 writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
324}
325
326static void vic_unmask_irq(struct irq_data *d)
327{
328 void __iomem *base = irq_data_get_irq_chip_data(d);
329 unsigned int irq = d->hwirq;
330 writel(1 << irq, base + VIC_INT_ENABLE);
331}
332
333#if defined(CONFIG_PM)
334static struct vic_device *vic_from_irq(unsigned int irq)
335{
336 struct vic_device *v = vic_devices;
337 unsigned int base_irq = irq & ~31;
338 int id;
339
340 for (id = 0; id < vic_id; id++, v++) {
341 if (v->irq == base_irq)
342 return v;
343 }
344
345 return NULL;
346}
347
348static int vic_set_wake(struct irq_data *d, unsigned int on)
349{
350 struct vic_device *v = vic_from_irq(d->irq);
351 unsigned int off = d->hwirq;
352 u32 bit = 1 << off;
353
354 if (!v)
355 return -EINVAL;
356
357 if (!(bit & v->resume_sources))
358 return -EINVAL;
359
360 if (on)
361 v->resume_irqs |= bit;
362 else
363 v->resume_irqs &= ~bit;
364
365 return 0;
366}
367#else
368#define vic_set_wake NULL
369#endif /* CONFIG_PM */
370
371static struct irq_chip vic_chip = {
372 .name = "VIC",
373 .irq_ack = vic_ack_irq,
374 .irq_mask = vic_mask_irq,
375 .irq_unmask = vic_unmask_irq,
376 .irq_set_wake = vic_set_wake,
377};
378
379static void __init vic_disable(void __iomem *base)
380{
381 writel(0, base + VIC_INT_SELECT);
382 writel(0, base + VIC_INT_ENABLE);
383 writel(~0, base + VIC_INT_ENABLE_CLEAR);
384 writel(0, base + VIC_ITCR);
385 writel(~0, base + VIC_INT_SOFT_CLEAR);
386}
387
388static void __init vic_clear_interrupts(void __iomem *base)
389{
390 unsigned int i;
391
392 writel(0, base + VIC_PL190_VECT_ADDR);
393 for (i = 0; i < 19; i++) {
394 unsigned int value;
395
396 value = readl(base + VIC_PL190_VECT_ADDR);
397 writel(value, base + VIC_PL190_VECT_ADDR);
398 }
399}
400
401/*
402 * The PL190 cell from ARM has been modified by ST to handle 64 interrupts.
403 * The original cell has 32 interrupts, while the modified one has 64,
404 * replicating two blocks 0x00..0x1f in 0x20..0x3f. In that case
405 * the probe function is called twice, with base set to offset 000
406 * and 020 within the page. We call this "second block".
407 */
408static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
409 u32 vic_sources, struct device_node *node)
410{
411 unsigned int i;
412 int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0;
413
414 /* Disable all interrupts initially. */
415 vic_disable(base);
416
417 /*
418 * Make sure we clear all existing interrupts. The vector registers
419 * in this cell are after the second block of general registers,
420 * so we can address them using standard offsets, but only from
421 * the second base address, which is 0x20 in the page
422 */
423 if (vic_2nd_block) {
424 vic_clear_interrupts(base);
425
426 /* ST has 16 vectors as well, but we don't enable them by now */
427 for (i = 0; i < 16; i++) {
428 void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
429 writel(0, reg);
430 }
431
432 writel(32, base + VIC_PL190_DEF_VECT_ADDR);
433 }
434
435 vic_register(base, 0, irq_start, vic_sources, 0, node);
436}
437
438static void __init __vic_init(void __iomem *base, int parent_irq, int irq_start,
439 u32 vic_sources, u32 resume_sources,
440 struct device_node *node)
441{
442 unsigned int i;
443 u32 cellid = 0;
444 enum amba_vendor vendor;
445
446 /* Identify which VIC cell this one is, by reading the ID */
447 for (i = 0; i < 4; i++) {
448 void __iomem *addr;
449 addr = (void __iomem *)((u32)base & PAGE_MASK) + 0xfe0 + (i * 4);
450 cellid |= (readl(addr) & 0xff) << (8 * i);
451 }
452 vendor = (cellid >> 12) & 0xff;
453 printk(KERN_INFO "VIC @%p: id 0x%08x, vendor 0x%02x\n",
454 base, cellid, vendor);
455
456 switch(vendor) {
457 case AMBA_VENDOR_ST:
458 vic_init_st(base, irq_start, vic_sources, node);
459 return;
460 default:
461 printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n");
462 fallthrough;
463 case AMBA_VENDOR_ARM:
464 break;
465 }
466
467 /* Disable all interrupts initially. */
468 vic_disable(base);
469
470 /* Make sure we clear all existing interrupts */
471 vic_clear_interrupts(base);
472
473 vic_init2(base);
474
475 vic_register(base, parent_irq, irq_start, vic_sources, resume_sources, node);
476}
477
478/**
479 * vic_init() - initialise a vectored interrupt controller
480 * @base: iomem base address
481 * @irq_start: starting interrupt number, must be muliple of 32
482 * @vic_sources: bitmask of interrupt sources to allow
483 * @resume_sources: bitmask of interrupt sources to allow for resume
484 */
485void __init vic_init(void __iomem *base, unsigned int irq_start,
486 u32 vic_sources, u32 resume_sources)
487{
488 __vic_init(base, 0, irq_start, vic_sources, resume_sources, NULL);
489}
490
491#ifdef CONFIG_OF
492static int __init vic_of_init(struct device_node *node,
493 struct device_node *parent)
494{
495 void __iomem *regs;
496 u32 interrupt_mask = ~0;
497 u32 wakeup_mask = ~0;
498 int parent_irq;
499
500 regs = of_iomap(node, 0);
501 if (WARN_ON(!regs))
502 return -EIO;
503
504 of_property_read_u32(node, "valid-mask", &interrupt_mask);
505 of_property_read_u32(node, "valid-wakeup-mask", &wakeup_mask);
506 parent_irq = of_irq_get(node, 0);
507 if (parent_irq < 0)
508 parent_irq = 0;
509
510 /*
511 * Passing 0 as first IRQ makes the simple domain allocate descriptors
512 */
513 __vic_init(regs, parent_irq, 0, interrupt_mask, wakeup_mask, node);
514
515 return 0;
516}
517IRQCHIP_DECLARE(arm_pl190_vic, "arm,pl190-vic", vic_of_init);
518IRQCHIP_DECLARE(arm_pl192_vic, "arm,pl192-vic", vic_of_init);
519IRQCHIP_DECLARE(arm_versatile_vic, "arm,versatile-vic", vic_of_init);
520#endif /* CONFIG OF */