Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1# SPDX-License-Identifier: GPL-2.0-only
2#
3# Memory devices
4#
5
6menuconfig MEMORY
7 bool "Memory Controller drivers"
8 help
9 This option allows to enable specific memory controller drivers,
10 useful mostly on embedded systems. These could be controllers
11 for DRAM (SDR, DDR), ROM, SRAM and others. The drivers features
12 vary from memory tuning and frequency scaling to enabling
13 access to attached peripherals through memory bus.
14
15if MEMORY
16
17config DDR
18 bool
19 help
20 Data from JEDEC specs for DDR SDRAM memories,
21 particularly the AC timing parameters and addressing
22 information. This data is useful for drivers handling
23 DDR SDRAM controllers.
24
25config ARM_PL172_MPMC
26 tristate "ARM PL172 MPMC driver"
27 depends on ARM_AMBA && OF
28 help
29 This selects the ARM PrimeCell PL172 MultiPort Memory Controller.
30 If you have an embedded system with an AMBA bus and a PL172
31 controller, say Y or M here.
32
33config ATMEL_EBI
34 bool "Atmel EBI driver"
35 default ARCH_AT91
36 depends on ARCH_AT91 || COMPILE_TEST
37 depends on OF
38 select MFD_SYSCON
39 select MFD_ATMEL_SMC
40 help
41 Driver for Atmel EBI controller.
42 Used to configure the EBI (external bus interface) when the device-
43 tree is used. This bus supports NANDs, external ethernet controller,
44 SRAMs, ATA devices, etc.
45
46config BRCMSTB_DPFE
47 tristate "Broadcom STB DPFE driver"
48 default ARCH_BRCMSTB
49 depends on ARCH_BRCMSTB || COMPILE_TEST
50 help
51 This driver provides access to the DPFE interface of Broadcom
52 STB SoCs. The firmware running on the DCPU inside the DDR PHY can
53 provide current information about the system's RAM, for instance
54 the DRAM refresh rate. This can be used as an indirect indicator
55 for the DRAM's temperature. Slower refresh rate means cooler RAM,
56 higher refresh rate means hotter RAM.
57
58config BRCMSTB_MEMC
59 tristate "Broadcom STB MEMC driver"
60 default ARCH_BRCMSTB
61 depends on ARCH_BRCMSTB || COMPILE_TEST
62 help
63 This driver provides a way to configure the Broadcom STB memory
64 controller and specifically control the Self Refresh Power Down
65 (SRPD) inactivity timeout.
66
67config TI_AEMIF
68 tristate "Texas Instruments AEMIF driver"
69 depends on ARCH_DAVINCI || ARCH_KEYSTONE || COMPILE_TEST
70 depends on OF
71 help
72 This driver is for the AEMIF module available in Texas Instruments
73 SoCs. AEMIF stands for Asynchronous External Memory Interface and
74 is intended to provide a glue-less interface to a variety of
75 asynchronuous memory devices like ASRAM, NOR and NAND memory. A total
76 of 256M bytes of any of these memories can be accessed at a given
77 time via four chip selects with 64M byte access per chip select.
78
79config TI_EMIF
80 tristate "Texas Instruments EMIF driver"
81 depends on ARCH_OMAP2PLUS || COMPILE_TEST
82 select DDR
83 help
84 This driver is for the EMIF module available in Texas Instruments
85 SoCs. EMIF is an SDRAM controller that, based on its revision,
86 supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
87 This driver takes care of only LPDDR2 memories presently. The
88 functions of the driver includes re-configuring AC timing
89 parameters and other settings during frequency, voltage and
90 temperature changes
91
92config OMAP_GPMC
93 tristate "Texas Instruments OMAP SoC GPMC driver"
94 depends on OF_ADDRESS
95 depends on ARCH_OMAP2PLUS || ARCH_KEYSTONE || ARCH_K3 || COMPILE_TEST
96 select GPIOLIB
97 help
98 This driver is for the General Purpose Memory Controller (GPMC)
99 present on Texas Instruments SoCs (e.g. OMAP2+). GPMC allows
100 interfacing to a variety of asynchronous as well as synchronous
101 memory drives like NOR, NAND, OneNAND, SRAM.
102
103config OMAP_GPMC_DEBUG
104 bool "Enable GPMC debug output and skip reset of GPMC during init"
105 depends on OMAP_GPMC
106 help
107 Enables verbose debugging mostly to decode the bootloader provided
108 timings. To preserve the bootloader provided timings, the reset
109 of GPMC is skipped during init. Enable this during development to
110 configure devices connected to the GPMC bus.
111
112 NOTE: In addition to matching the register setup with the bootloader
113 you also need to match the GPMC FCLK frequency used by the
114 bootloader or else the GPMC timings won't be identical with the
115 bootloader timings.
116
117config TI_EMIF_SRAM
118 tristate "Texas Instruments EMIF SRAM driver"
119 depends on SOC_AM33XX || SOC_AM43XX || (ARM && CPU_V7 && COMPILE_TEST)
120 depends on SRAM
121 help
122 This driver is for the EMIF module available on Texas Instruments
123 AM33XX and AM43XX SoCs and is required for PM. Certain parts of
124 the EMIF PM code must run from on-chip SRAM late in the suspend
125 sequence so this driver provides several relocatable PM functions
126 for the SoC PM code to use.
127
128config FPGA_DFL_EMIF
129 tristate "FPGA DFL EMIF Driver"
130 depends on FPGA_DFL && HAS_IOMEM
131 help
132 This driver is for the EMIF private feature implemented under
133 FPGA Device Feature List (DFL) framework. It is used to expose
134 memory interface status information as well as memory clearing
135 control.
136
137config MVEBU_DEVBUS
138 bool "Marvell EBU Device Bus Controller"
139 default PLAT_ORION
140 depends on PLAT_ORION || COMPILE_TEST
141 depends on OF
142 help
143 This driver is for the Device Bus controller available in some
144 Marvell EBU SoCs such as Discovery (mv78xx0), Orion (88f5xxx) and
145 Armada 370 and Armada XP. This controller allows to handle flash
146 devices such as NOR, NAND, SRAM, and FPGA.
147
148config FSL_CORENET_CF
149 tristate "Freescale CoreNet Error Reporting"
150 depends on FSL_SOC_BOOKE || COMPILE_TEST
151 help
152 Say Y for reporting of errors from the Freescale CoreNet
153 Coherency Fabric. Errors reported include accesses to
154 physical addresses that mapped by no local access window
155 (LAW) or an invalid LAW, as well as bad cache state that
156 represents a coherency violation.
157
158config FSL_IFC
159 bool "Freescale IFC driver"
160 depends on FSL_SOC || ARCH_LAYERSCAPE || SOC_LS1021A || COMPILE_TEST
161 depends on HAS_IOMEM
162
163config JZ4780_NEMC
164 bool "Ingenic JZ4780 SoC NEMC driver"
165 depends on MIPS || COMPILE_TEST
166 depends on HAS_IOMEM && OF
167 help
168 This driver is for the NAND/External Memory Controller (NEMC) in
169 the Ingenic JZ4780. This controller is used to handle external
170 memory devices such as NAND and SRAM.
171
172config MTK_SMI
173 tristate "MediaTek SoC Memory Controller driver" if COMPILE_TEST
174 depends on ARCH_MEDIATEK || COMPILE_TEST
175 help
176 This driver is for the Memory Controller module in MediaTek SoCs,
177 mainly help enable/disable iommu and control the power domain and
178 clocks for each local arbiter.
179
180config DA8XX_DDRCTL
181 bool "Texas Instruments da8xx DDR2/mDDR driver"
182 depends on ARCH_DAVINCI_DA8XX || COMPILE_TEST
183 help
184 This driver is for the DDR2/mDDR Memory Controller present on
185 Texas Instruments da8xx SoCs. It's used to tweak various memory
186 controller configuration options.
187
188config PL353_SMC
189 tristate "ARM PL35X Static Memory Controller(SMC) driver"
190 default ARM
191 depends on ARM || COMPILE_TEST
192 depends on ARM_AMBA
193 help
194 This driver is for the ARM PL351/PL353 Static Memory
195 Controller(SMC) module.
196
197config RENESAS_RPCIF
198 tristate "Renesas RPC-IF driver"
199 depends on ARCH_RENESAS || COMPILE_TEST
200 select REGMAP_MMIO
201 select RESET_CONTROLLER
202 help
203 This supports Renesas R-Car Gen3 or RZ/G2 RPC-IF which provides
204 either SPI host or HyperFlash. You'll have to select individual
205 components under the corresponding menu.
206
207config STM32_FMC2_EBI
208 tristate "Support for FMC2 External Bus Interface on STM32MP SoCs"
209 depends on ARCH_STM32 || COMPILE_TEST
210 select MFD_SYSCON
211 help
212 Select this option to enable the STM32 FMC2 External Bus Interface
213 controller. This driver configures the transactions with external
214 devices (like SRAM, ethernet adapters, FPGAs, LCD displays, ...) on
215 SOCs containing the FMC2 External Bus Interface.
216
217config STM32_OMM
218 tristate "STM32 Octo Memory Manager"
219 depends on SPI_STM32_OSPI || COMPILE_TEST
220 help
221 This driver manages the muxing between the 2 OSPI busses and
222 the 2 output ports. There are 4 possible muxing configurations:
223 - direct mode (no multiplexing): OSPI1 output is on port 1 and OSPI2
224 output is on port 2
225 - OSPI1 and OSPI2 are multiplexed over the same output port 1
226 - swapped mode (no multiplexing), OSPI1 output is on port 2,
227 OSPI2 output is on port 1
228 - OSPI1 and OSPI2 are multiplexed over the same output port 2
229 It also manages :
230 - the split of the memory area shared between the 2 OSPI instances.
231 - chip select selection override.
232 - the time between 2 transactions in multiplexed mode.
233
234source "drivers/memory/samsung/Kconfig"
235source "drivers/memory/tegra/Kconfig"
236
237endif