Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2/*
3 * Copyright (c) 2003-2022, Intel Corporation. All rights reserved.
4 * Intel Management Engine Interface (Intel MEI) Linux driver
5 */
6#ifndef _MEI_HW_MEI_REGS_H_
7#define _MEI_HW_MEI_REGS_H_
8
9/*
10 * MEI device IDs
11 */
12#define PCI_DEVICE_ID_INTEL_MEI_82946GZ 0x2974 /* 82946GZ/GL */
13#define PCI_DEVICE_ID_INTEL_MEI_82G35 0x2984 /* 82G35 Express */
14#define PCI_DEVICE_ID_INTEL_MEI_82Q965 0x2994 /* 82Q963/Q965 */
15#define PCI_DEVICE_ID_INTEL_MEI_82G965 0x29A4 /* 82P965/G965 */
16
17#define PCI_DEVICE_ID_INTEL_MEI_82GM965 0x2A04 /* Mobile PM965/GM965 */
18#define PCI_DEVICE_ID_INTEL_MEI_82GME965 0x2A14 /* Mobile GME965/GLE960 */
19
20#define PCI_DEVICE_ID_INTEL_MEI_ICH9_82Q35 0x29B4 /* 82Q35 Express */
21#define PCI_DEVICE_ID_INTEL_MEI_ICH9_82G33 0x29C4 /* 82G33/G31/P35/P31 Express */
22#define PCI_DEVICE_ID_INTEL_MEI_ICH9_82Q33 0x29D4 /* 82Q33 Express */
23#define PCI_DEVICE_ID_INTEL_MEI_ICH9_82X38 0x29E4 /* 82X38/X48 Express */
24#define PCI_DEVICE_ID_INTEL_MEI_ICH9_3200 0x29F4 /* 3200/3210 Server */
25
26#define PCI_DEVICE_ID_INTEL_MEI_ICH9_6 0x28B4 /* Bearlake */
27#define PCI_DEVICE_ID_INTEL_MEI_ICH9_7 0x28C4 /* Bearlake */
28#define PCI_DEVICE_ID_INTEL_MEI_ICH9_8 0x28D4 /* Bearlake */
29#define PCI_DEVICE_ID_INTEL_MEI_ICH9_9 0x28E4 /* Bearlake */
30#define PCI_DEVICE_ID_INTEL_MEI_ICH9_10 0x28F4 /* Bearlake */
31
32#define PCI_DEVICE_ID_INTEL_MEI_ICH9M_1 0x2A44 /* Cantiga */
33#define PCI_DEVICE_ID_INTEL_MEI_ICH9M_2 0x2A54 /* Cantiga */
34#define PCI_DEVICE_ID_INTEL_MEI_ICH9M_3 0x2A64 /* Cantiga */
35#define PCI_DEVICE_ID_INTEL_MEI_ICH9M_4 0x2A74 /* Cantiga */
36
37#define PCI_DEVICE_ID_INTEL_MEI_ICH10_1 0x2E04 /* Eaglelake */
38#define PCI_DEVICE_ID_INTEL_MEI_ICH10_2 0x2E14 /* Eaglelake */
39#define PCI_DEVICE_ID_INTEL_MEI_ICH10_3 0x2E24 /* Eaglelake */
40#define PCI_DEVICE_ID_INTEL_MEI_ICH10_4 0x2E34 /* Eaglelake */
41
42#define PCI_DEVICE_ID_INTEL_MEI_IBXPK_1 0x3B64 /* Calpella */
43#define PCI_DEVICE_ID_INTEL_MEI_IBXPK_2 0x3B65 /* Calpella */
44
45#define PCI_DEVICE_ID_INTEL_MEI_CPT_1 0x1C3A /* Couger Point */
46#define PCI_DEVICE_ID_INTEL_MEI_PBG_1 0x1D3A /* C600/X79 Patsburg */
47
48#define PCI_DEVICE_ID_INTEL_MEI_PPT_1 0x1E3A /* Panther Point */
49#define PCI_DEVICE_ID_INTEL_MEI_PPT_2 0x1CBA /* Panther Point */
50#define PCI_DEVICE_ID_INTEL_MEI_PPT_3 0x1DBA /* Panther Point */
51
52#define PCI_DEVICE_ID_INTEL_MEI_LPT_H 0x8C3A /* Lynx Point H */
53#define PCI_DEVICE_ID_INTEL_MEI_LPT_W 0x8D3A /* Lynx Point - Wellsburg */
54#define PCI_DEVICE_ID_INTEL_MEI_LPT_LP 0x9C3A /* Lynx Point LP */
55#define PCI_DEVICE_ID_INTEL_MEI_LPT_HR 0x8CBA /* Lynx Point H Refresh */
56
57#define PCI_DEVICE_ID_INTEL_MEI_WPT_LP 0x9CBA /* Wildcat Point LP */
58#define PCI_DEVICE_ID_INTEL_MEI_WPT_LP_2 0x9CBB /* Wildcat Point LP 2 */
59
60#define PCI_DEVICE_ID_INTEL_MEI_SPT 0x9D3A /* Sunrise Point */
61#define PCI_DEVICE_ID_INTEL_MEI_SPT_2 0x9D3B /* Sunrise Point 2 */
62#define PCI_DEVICE_ID_INTEL_MEI_SPT_3 0x9D3E /* Sunrise Point 3 (iToutch) */
63#define PCI_DEVICE_ID_INTEL_MEI_SPT_H 0xA13A /* Sunrise Point H */
64#define PCI_DEVICE_ID_INTEL_MEI_SPT_H_2 0xA13B /* Sunrise Point H 2 */
65
66#define PCI_DEVICE_ID_INTEL_MEI_LBG 0xA1BA /* Lewisburg (SPT) */
67
68#define PCI_DEVICE_ID_INTEL_MEI_BXT_M 0x1A9A /* Broxton M */
69#define PCI_DEVICE_ID_INTEL_MEI_APL_I 0x5A9A /* Apollo Lake I */
70
71#define PCI_DEVICE_ID_INTEL_MEI_DNV_IE 0x19E5 /* Denverton IE */
72
73#define PCI_DEVICE_ID_INTEL_MEI_GLK 0x319A /* Gemini Lake */
74
75#define PCI_DEVICE_ID_INTEL_MEI_KBP 0xA2BA /* Kaby Point */
76#define PCI_DEVICE_ID_INTEL_MEI_KBP_2 0xA2BB /* Kaby Point 2 */
77#define PCI_DEVICE_ID_INTEL_MEI_KBP_3 0xA2BE /* Kaby Point 3 (iTouch) */
78
79#define PCI_DEVICE_ID_INTEL_MEI_CNP_LP 0x9DE0 /* Cannon Point LP */
80#define PCI_DEVICE_ID_INTEL_MEI_CNP_LP_3 0x9DE4 /* Cannon Point LP 3 (iTouch) */
81#define PCI_DEVICE_ID_INTEL_MEI_CNP_H 0xA360 /* Cannon Point H */
82#define PCI_DEVICE_ID_INTEL_MEI_CNP_H_3 0xA364 /* Cannon Point H 3 (iTouch) */
83
84#define PCI_DEVICE_ID_INTEL_MEI_CMP_LP 0x02e0 /* Comet Point LP */
85#define PCI_DEVICE_ID_INTEL_MEI_CMP_LP_3 0x02e4 /* Comet Point LP 3 (iTouch) */
86
87#define PCI_DEVICE_ID_INTEL_MEI_CMP_V 0xA3BA /* Comet Point Lake V */
88
89#define PCI_DEVICE_ID_INTEL_MEI_CMP_H 0x06e0 /* Comet Lake H */
90#define PCI_DEVICE_ID_INTEL_MEI_CMP_H_3 0x06e4 /* Comet Lake H 3 (iTouch) */
91
92#define PCI_DEVICE_ID_INTEL_MEI_CDF 0x18D3 /* Cedar Fork */
93
94#define PCI_DEVICE_ID_INTEL_MEI_ICP_LP 0x34E0 /* Ice Lake Point LP */
95#define PCI_DEVICE_ID_INTEL_MEI_ICP_N 0x38E0 /* Ice Lake Point N */
96
97#define PCI_DEVICE_ID_INTEL_MEI_JSP_N 0x4DE0 /* Jasper Lake Point N */
98
99#define PCI_DEVICE_ID_INTEL_MEI_TGP_LP 0xA0E0 /* Tiger Lake Point LP */
100#define PCI_DEVICE_ID_INTEL_MEI_TGP_H 0x43E0 /* Tiger Lake Point H */
101
102#define PCI_DEVICE_ID_INTEL_MEI_MCC 0x4B70 /* Mule Creek Canyon (EHL) */
103#define PCI_DEVICE_ID_INTEL_MEI_MCC_4 0x4B75 /* Mule Creek Canyon 4 (EHL) */
104
105#define PCI_DEVICE_ID_INTEL_MEI_EBG 0x1BE0 /* Emmitsburg WS */
106
107#define PCI_DEVICE_ID_INTEL_MEI_ADP_S 0x7AE8 /* Alder Lake Point S */
108#define PCI_DEVICE_ID_INTEL_MEI_ADP_LP 0x7A60 /* Alder Lake Point LP */
109#define PCI_DEVICE_ID_INTEL_MEI_ADP_P 0x51E0 /* Alder Lake Point P */
110#define PCI_DEVICE_ID_INTEL_MEI_ADP_N 0x54E0 /* Alder Lake Point N */
111
112#define PCI_DEVICE_ID_INTEL_MEI_RPL_S 0x7A68 /* Raptor Lake Point S */
113
114#define PCI_DEVICE_ID_INTEL_MEI_MTL_M 0x7E70 /* Meteor Lake Point M */
115#define PCI_DEVICE_ID_INTEL_MEI_ARL_S 0x7F68 /* Arrow Lake Point S */
116#define PCI_DEVICE_ID_INTEL_MEI_ARL_H 0x7770 /* Arrow Lake Point H */
117
118#define PCI_DEVICE_ID_INTEL_MEI_LNL_M 0xA870 /* Lunar Lake Point M */
119
120#define PCI_DEVICE_ID_INTEL_MEI_PTL_H 0xE370 /* Panther Lake H */
121#define PCI_DEVICE_ID_INTEL_MEI_PTL_P 0xE470 /* Panther Lake P */
122
123#define PCI_DEVICE_ID_INTEL_MEI_WCL_P 0x4D70 /* Wildcat Lake P */
124
125#define PCI_DEVICE_ID_INTEL_MEI_NVL_S 0x6E68 /* Nova Lake Point S */
126#define PCI_DEVICE_ID_INTEL_MEI_NVL_H 0xD370 /* Nova Lake Point H */
127
128#define PCI_DEVICE_ID_INTEL_MEI_CRI 0x6766 /* Crescent Island */
129
130/*
131 * MEI HW Section
132 */
133
134/* Host Firmware Status Registers in PCI Config Space */
135#define PCI_CFG_HFS_1 0x40
136# define PCI_CFG_HFS_1_D0I3_MSK 0x80000000
137# define PCI_CFG_HFS_1_OPMODE_MSK 0xf0000 /* OP MODE Mask: SPS <= 4.0 */
138# define PCI_CFG_HFS_1_OPMODE_SPS 0xf0000 /* SPS SKU : SPS <= 4.0 */
139#define PCI_CFG_HFS_2 0x48
140# define PCI_CFG_HFS_2_D3_BLOCK BIT(7)
141# define PCI_CFG_HFS_2_PM_CMOFF_TO_CMX_ERROR 0x1000000 /* CMoff->CMx wake after an error */
142# define PCI_CFG_HFS_2_PM_CM_RESET_ERROR 0x5000000 /* CME reset due to exception */
143# define PCI_CFG_HFS_2_PM_EVENT_MASK 0xf000000
144#define PCI_CFG_HFS_3 0x60
145# define PCI_CFG_HFS_3_FW_SKU_MSK 0x00000070
146# define PCI_CFG_HFS_3_FW_SKU_IGN 0x00000000
147# define PCI_CFG_HFS_3_FW_SKU_SPS 0x00000060
148#define PCI_CFG_HFS_4 0x64
149#define PCI_CFG_HFS_5 0x68
150# define GSC_CFG_HFS_5_BOOT_TYPE_MSK 0x00000003
151# define GSC_CFG_HFS_5_BOOT_TYPE_PXP 3
152#define PCI_CFG_HFS_6 0x6C
153
154/* MEI registers */
155/* H_CB_WW - Host Circular Buffer (CB) Write Window register */
156#define H_CB_WW 0
157/* H_CSR - Host Control Status register */
158#define H_CSR 4
159/* ME_CB_RW - ME Circular Buffer Read Window register (read only) */
160#define ME_CB_RW 8
161/* ME_CSR_HA - ME Control Status Host Access register (read only) */
162#define ME_CSR_HA 0xC
163/* H_HGC_CSR - PGI register */
164#define H_HPG_CSR 0x10
165/* H_D0I3C - D0I3 Control */
166#define H_D0I3C 0x800
167
168#define H_GSC_EXT_OP_MEM_BASE_ADDR_LO_REG 0x100
169#define H_GSC_EXT_OP_MEM_BASE_ADDR_HI_REG 0x104
170#define H_GSC_EXT_OP_MEM_LIMIT_REG 0x108
171#define GSC_EXT_OP_MEM_VALID BIT(31)
172
173/* register bits of H_CSR (Host Control Status register) */
174/* Host Circular Buffer Depth - maximum number of 32-bit entries in CB */
175#define H_CBD 0xFF000000
176/* Host Circular Buffer Write Pointer */
177#define H_CBWP 0x00FF0000
178/* Host Circular Buffer Read Pointer */
179#define H_CBRP 0x0000FF00
180/* Host Reset */
181#define H_RST 0x00000010
182/* Host Ready */
183#define H_RDY 0x00000008
184/* Host Interrupt Generate */
185#define H_IG 0x00000004
186/* Host Interrupt Status */
187#define H_IS 0x00000002
188/* Host Interrupt Enable */
189#define H_IE 0x00000001
190/* Host D0I3 Interrupt Enable */
191#define H_D0I3C_IE 0x00000020
192/* Host D0I3 Interrupt Status */
193#define H_D0I3C_IS 0x00000040
194
195/* H_CSR masks */
196#define H_CSR_IE_MASK (H_IE | H_D0I3C_IE)
197#define H_CSR_IS_MASK (H_IS | H_D0I3C_IS)
198
199/* register bits of ME_CSR_HA (ME Control Status Host Access register) */
200/* ME CB (Circular Buffer) Depth HRA (Host Read Access) - host read only
201access to ME_CBD */
202#define ME_CBD_HRA 0xFF000000
203/* ME CB Write Pointer HRA - host read only access to ME_CBWP */
204#define ME_CBWP_HRA 0x00FF0000
205/* ME CB Read Pointer HRA - host read only access to ME_CBRP */
206#define ME_CBRP_HRA 0x0000FF00
207/* ME Power Gate Isolation Capability HRA - host ready only access */
208#define ME_PGIC_HRA 0x00000040
209/* ME Reset HRA - host read only access to ME_RST */
210#define ME_RST_HRA 0x00000010
211/* ME Ready HRA - host read only access to ME_RDY */
212#define ME_RDY_HRA 0x00000008
213/* ME Interrupt Generate HRA - host read only access to ME_IG */
214#define ME_IG_HRA 0x00000004
215/* ME Interrupt Status HRA - host read only access to ME_IS */
216#define ME_IS_HRA 0x00000002
217/* ME Interrupt Enable HRA - host read only access to ME_IE */
218#define ME_IE_HRA 0x00000001
219/* TRC control shadow register */
220#define ME_TRC 0x00000030
221
222/* H_HPG_CSR register bits */
223#define H_HPG_CSR_PGIHEXR 0x00000001
224#define H_HPG_CSR_PGI 0x00000002
225
226/* H_D0I3C register bits */
227#define H_D0I3C_CIP 0x00000001
228#define H_D0I3C_IR 0x00000002
229#define H_D0I3C_I3 0x00000004
230#define H_D0I3C_RR 0x00000008
231
232#endif /* _MEI_HW_MEI_REGS_H_ */