Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * NVM Express device driver
4 * Copyright (c) 2011-2014, Intel Corporation.
5 */
6
7#include <linux/acpi.h>
8#include <linux/async.h>
9#include <linux/blkdev.h>
10#include <linux/blk-mq-dma.h>
11#include <linux/blk-integrity.h>
12#include <linux/dmi.h>
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
16#include <linux/kstrtox.h>
17#include <linux/memremap.h>
18#include <linux/mm.h>
19#include <linux/module.h>
20#include <linux/mutex.h>
21#include <linux/nodemask.h>
22#include <linux/once.h>
23#include <linux/pci.h>
24#include <linux/suspend.h>
25#include <linux/t10-pi.h>
26#include <linux/types.h>
27#include <linux/io-64-nonatomic-lo-hi.h>
28#include <linux/io-64-nonatomic-hi-lo.h>
29#include <linux/sed-opal.h>
30
31#include "trace.h"
32#include "nvme.h"
33
34#define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
35#define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
36
37/* Optimisation for I/Os between 4k and 128k */
38#define NVME_SMALL_POOL_SIZE 256
39
40/*
41 * Arbitrary upper bound.
42 */
43#define NVME_MAX_BYTES SZ_8M
44#define NVME_MAX_NR_DESCRIPTORS 5
45
46/*
47 * For data SGLs we support a single descriptors worth of SGL entries.
48 * For PRPs, segments don't matter at all.
49 */
50#define NVME_MAX_SEGS \
51 (NVME_CTRL_PAGE_SIZE / sizeof(struct nvme_sgl_desc))
52
53/*
54 * For metadata SGLs, only the small descriptor is supported, and the first
55 * entry is the segment descriptor, which for the data pointer sits in the SQE.
56 */
57#define NVME_MAX_META_SEGS \
58 ((NVME_SMALL_POOL_SIZE / sizeof(struct nvme_sgl_desc)) - 1)
59
60/*
61 * The last entry is used to link to the next descriptor.
62 */
63#define PRPS_PER_PAGE \
64 (((NVME_CTRL_PAGE_SIZE / sizeof(__le64))) - 1)
65
66/*
67 * I/O could be non-aligned both at the beginning and end.
68 */
69#define MAX_PRP_RANGE \
70 (NVME_MAX_BYTES + 2 * (NVME_CTRL_PAGE_SIZE - 1))
71
72static_assert(MAX_PRP_RANGE / NVME_CTRL_PAGE_SIZE <=
73 (1 /* prp1 */ + NVME_MAX_NR_DESCRIPTORS * PRPS_PER_PAGE));
74
75struct quirk_entry {
76 u16 vendor_id;
77 u16 dev_id;
78 u32 enabled_quirks;
79 u32 disabled_quirks;
80};
81
82static int use_threaded_interrupts;
83module_param(use_threaded_interrupts, int, 0444);
84
85static bool use_cmb_sqes = true;
86module_param(use_cmb_sqes, bool, 0444);
87MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
88
89static unsigned int max_host_mem_size_mb = 128;
90module_param(max_host_mem_size_mb, uint, 0444);
91MODULE_PARM_DESC(max_host_mem_size_mb,
92 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
93
94static unsigned int sgl_threshold = SZ_32K;
95module_param(sgl_threshold, uint, 0644);
96MODULE_PARM_DESC(sgl_threshold,
97 "Use SGLs when average request segment size is larger or equal to "
98 "this size. Use 0 to disable SGLs.");
99
100#define NVME_PCI_MIN_QUEUE_SIZE 2
101#define NVME_PCI_MAX_QUEUE_SIZE 4095
102static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
103static const struct kernel_param_ops io_queue_depth_ops = {
104 .set = io_queue_depth_set,
105 .get = param_get_uint,
106};
107
108static unsigned int io_queue_depth = 1024;
109module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
110MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096");
111
112static struct quirk_entry *nvme_pci_quirk_list;
113static unsigned int nvme_pci_quirk_count;
114
115/* Helper to parse individual quirk names */
116static int nvme_parse_quirk_names(char *quirk_str, struct quirk_entry *entry)
117{
118 int i;
119 size_t field_len;
120 bool disabled, found;
121 char *p = quirk_str, *field;
122
123 while ((field = strsep(&p, ",")) && *field) {
124 disabled = false;
125 found = false;
126
127 if (*field == '^') {
128 /* Skip the '^' character */
129 disabled = true;
130 field++;
131 }
132
133 field_len = strlen(field);
134 for (i = 0; i < 32; i++) {
135 unsigned int bit = 1U << i;
136 char *q_name = nvme_quirk_name(bit);
137 size_t q_len = strlen(q_name);
138
139 if (!strcmp(q_name, "unknown"))
140 break;
141
142 if (!strcmp(q_name, field) &&
143 q_len == field_len) {
144 if (disabled)
145 entry->disabled_quirks |= bit;
146 else
147 entry->enabled_quirks |= bit;
148 found = true;
149 break;
150 }
151 }
152
153 if (!found) {
154 pr_err("nvme: unrecognized quirk %s\n", field);
155 return -EINVAL;
156 }
157 }
158 return 0;
159}
160
161/* Helper to parse a single VID:DID:quirk_names entry */
162static int nvme_parse_quirk_entry(char *s, struct quirk_entry *entry)
163{
164 char *field;
165
166 field = strsep(&s, ":");
167 if (!field || kstrtou16(field, 16, &entry->vendor_id))
168 return -EINVAL;
169
170 field = strsep(&s, ":");
171 if (!field || kstrtou16(field, 16, &entry->dev_id))
172 return -EINVAL;
173
174 field = strsep(&s, ":");
175 if (!field)
176 return -EINVAL;
177
178 return nvme_parse_quirk_names(field, entry);
179}
180
181static int quirks_param_set(const char *value, const struct kernel_param *kp)
182{
183 int count, err, i;
184 struct quirk_entry *qlist;
185 char *field, *val, *sep_ptr;
186
187 err = param_set_copystring(value, kp);
188 if (err)
189 return err;
190
191 val = kstrdup(value, GFP_KERNEL);
192 if (!val)
193 return -ENOMEM;
194
195 if (!*val)
196 goto out_free_val;
197
198 count = 1;
199 for (i = 0; val[i]; i++) {
200 if (val[i] == '-')
201 count++;
202 }
203
204 qlist = kcalloc(count, sizeof(*qlist), GFP_KERNEL);
205 if (!qlist) {
206 err = -ENOMEM;
207 goto out_free_val;
208 }
209
210 i = 0;
211 sep_ptr = val;
212 while ((field = strsep(&sep_ptr, "-"))) {
213 if (nvme_parse_quirk_entry(field, &qlist[i])) {
214 pr_err("nvme: failed to parse quirk string %s\n",
215 value);
216 goto out_free_qlist;
217 }
218
219 i++;
220 }
221
222 kfree(nvme_pci_quirk_list);
223 nvme_pci_quirk_count = count;
224 nvme_pci_quirk_list = qlist;
225 goto out_free_val;
226
227out_free_qlist:
228 kfree(qlist);
229out_free_val:
230 kfree(val);
231 return err;
232}
233
234static char quirks_param[128];
235static const struct kernel_param_ops quirks_param_ops = {
236 .set = quirks_param_set,
237 .get = param_get_string,
238};
239
240static struct kparam_string quirks_param_string = {
241 .maxlen = sizeof(quirks_param),
242 .string = quirks_param,
243};
244
245module_param_cb(quirks, &quirks_param_ops, &quirks_param_string, 0444);
246MODULE_PARM_DESC(quirks, "Enable/disable NVMe quirks by specifying "
247 "quirks=VID:DID:quirk_names");
248
249static int io_queue_count_set(const char *val, const struct kernel_param *kp)
250{
251 unsigned int n;
252 int ret;
253
254 ret = kstrtouint(val, 10, &n);
255 if (ret != 0 || n > blk_mq_num_possible_queues(0))
256 return -EINVAL;
257 return param_set_uint(val, kp);
258}
259
260static const struct kernel_param_ops io_queue_count_ops = {
261 .set = io_queue_count_set,
262 .get = param_get_uint,
263};
264
265static unsigned int write_queues;
266module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
267MODULE_PARM_DESC(write_queues,
268 "Number of queues to use for writes. If not set, reads and writes "
269 "will share a queue set.");
270
271static unsigned int poll_queues;
272module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
273MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
274
275static bool noacpi;
276module_param(noacpi, bool, 0444);
277MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
278
279struct nvme_dev;
280struct nvme_queue;
281
282static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
283static void nvme_delete_io_queues(struct nvme_dev *dev);
284static void nvme_update_attrs(struct nvme_dev *dev);
285
286struct nvme_descriptor_pools {
287 struct dma_pool *large;
288 struct dma_pool *small;
289};
290
291/*
292 * Represents an NVM Express device. Each nvme_dev is a PCI function.
293 */
294struct nvme_dev {
295 struct nvme_queue *queues;
296 struct blk_mq_tag_set tagset;
297 struct blk_mq_tag_set admin_tagset;
298 u32 __iomem *dbs;
299 struct device *dev;
300 unsigned online_queues;
301 unsigned max_qid;
302 unsigned io_queues[HCTX_MAX_TYPES];
303 unsigned int num_vecs;
304 u32 q_depth;
305 int io_sqes;
306 u32 db_stride;
307 void __iomem *bar;
308 unsigned long bar_mapped_size;
309 struct mutex shutdown_lock;
310 bool subsystem;
311 u64 cmb_size;
312 bool cmb_use_sqes;
313 u32 cmbsz;
314 u32 cmbloc;
315 struct nvme_ctrl ctrl;
316 u32 last_ps;
317 bool hmb;
318 struct sg_table *hmb_sgt;
319 mempool_t *dmavec_mempool;
320
321 /* shadow doorbell buffer support: */
322 __le32 *dbbuf_dbs;
323 dma_addr_t dbbuf_dbs_dma_addr;
324 __le32 *dbbuf_eis;
325 dma_addr_t dbbuf_eis_dma_addr;
326
327 /* host memory buffer support: */
328 u64 host_mem_size;
329 u32 nr_host_mem_descs;
330 u32 host_mem_descs_size;
331 dma_addr_t host_mem_descs_dma;
332 struct nvme_host_mem_buf_desc *host_mem_descs;
333 void **host_mem_desc_bufs;
334 unsigned int nr_allocated_queues;
335 unsigned int nr_write_queues;
336 unsigned int nr_poll_queues;
337 struct nvme_descriptor_pools descriptor_pools[];
338};
339
340static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
341{
342 return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE,
343 NVME_PCI_MAX_QUEUE_SIZE);
344}
345
346static inline unsigned int sq_idx(unsigned int qid, u32 stride)
347{
348 return qid * 2 * stride;
349}
350
351static inline unsigned int cq_idx(unsigned int qid, u32 stride)
352{
353 return (qid * 2 + 1) * stride;
354}
355
356static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
357{
358 return container_of(ctrl, struct nvme_dev, ctrl);
359}
360
361/*
362 * An NVM Express queue. Each device has at least two (one for admin
363 * commands and one for I/O commands).
364 */
365struct nvme_queue {
366 struct nvme_dev *dev;
367 struct nvme_descriptor_pools descriptor_pools;
368 spinlock_t sq_lock;
369 void *sq_cmds;
370 /* only used for poll queues: */
371 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
372 struct nvme_completion *cqes;
373 dma_addr_t sq_dma_addr;
374 dma_addr_t cq_dma_addr;
375 u32 __iomem *q_db;
376 u32 q_depth;
377 u16 cq_vector;
378 u16 sq_tail;
379 u16 last_sq_tail;
380 u16 cq_head;
381 u16 qid;
382 u8 cq_phase;
383 u8 sqes;
384 unsigned long flags;
385#define NVMEQ_ENABLED 0
386#define NVMEQ_SQ_CMB 1
387#define NVMEQ_DELETE_ERROR 2
388#define NVMEQ_POLLED 3
389 __le32 *dbbuf_sq_db;
390 __le32 *dbbuf_cq_db;
391 __le32 *dbbuf_sq_ei;
392 __le32 *dbbuf_cq_ei;
393 struct completion delete_done;
394};
395
396/* bits for iod->flags */
397enum nvme_iod_flags {
398 /* this command has been aborted by the timeout handler */
399 IOD_ABORTED = 1U << 0,
400
401 /* uses the small descriptor pool */
402 IOD_SMALL_DESCRIPTOR = 1U << 1,
403
404 /* single segment dma mapping */
405 IOD_SINGLE_SEGMENT = 1U << 2,
406
407 /* Data payload contains p2p memory */
408 IOD_DATA_P2P = 1U << 3,
409
410 /* Metadata contains p2p memory */
411 IOD_META_P2P = 1U << 4,
412
413 /* Data payload contains MMIO memory */
414 IOD_DATA_MMIO = 1U << 5,
415
416 /* Metadata contains MMIO memory */
417 IOD_META_MMIO = 1U << 6,
418
419 /* Metadata using non-coalesced MPTR */
420 IOD_SINGLE_META_SEGMENT = 1U << 7,
421};
422
423struct nvme_dma_vec {
424 dma_addr_t addr;
425 unsigned int len;
426};
427
428/*
429 * The nvme_iod describes the data in an I/O.
430 */
431struct nvme_iod {
432 struct nvme_request req;
433 struct nvme_command cmd;
434 u8 flags;
435 u8 nr_descriptors;
436
437 size_t total_len;
438 struct dma_iova_state dma_state;
439 void *descriptors[NVME_MAX_NR_DESCRIPTORS];
440 struct nvme_dma_vec *dma_vecs;
441 unsigned int nr_dma_vecs;
442
443 dma_addr_t meta_dma;
444 size_t meta_total_len;
445 struct dma_iova_state meta_dma_state;
446 struct nvme_sgl_desc *meta_descriptor;
447};
448
449static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
450{
451 return dev->nr_allocated_queues * 8 * dev->db_stride;
452}
453
454static void nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
455{
456 unsigned int mem_size = nvme_dbbuf_size(dev);
457
458 if (!(dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP))
459 return;
460
461 if (dev->dbbuf_dbs) {
462 /*
463 * Clear the dbbuf memory so the driver doesn't observe stale
464 * values from the previous instantiation.
465 */
466 memset(dev->dbbuf_dbs, 0, mem_size);
467 memset(dev->dbbuf_eis, 0, mem_size);
468 return;
469 }
470
471 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
472 &dev->dbbuf_dbs_dma_addr,
473 GFP_KERNEL);
474 if (!dev->dbbuf_dbs)
475 goto fail;
476 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
477 &dev->dbbuf_eis_dma_addr,
478 GFP_KERNEL);
479 if (!dev->dbbuf_eis)
480 goto fail_free_dbbuf_dbs;
481 return;
482
483fail_free_dbbuf_dbs:
484 dma_free_coherent(dev->dev, mem_size, dev->dbbuf_dbs,
485 dev->dbbuf_dbs_dma_addr);
486 dev->dbbuf_dbs = NULL;
487fail:
488 dev_warn(dev->dev, "unable to allocate dma for dbbuf\n");
489}
490
491static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
492{
493 unsigned int mem_size = nvme_dbbuf_size(dev);
494
495 if (dev->dbbuf_dbs) {
496 dma_free_coherent(dev->dev, mem_size,
497 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
498 dev->dbbuf_dbs = NULL;
499 }
500 if (dev->dbbuf_eis) {
501 dma_free_coherent(dev->dev, mem_size,
502 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
503 dev->dbbuf_eis = NULL;
504 }
505}
506
507static void nvme_dbbuf_init(struct nvme_dev *dev,
508 struct nvme_queue *nvmeq, int qid)
509{
510 if (!dev->dbbuf_dbs || !qid)
511 return;
512
513 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
514 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
515 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
516 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
517}
518
519static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
520{
521 if (!nvmeq->qid)
522 return;
523
524 nvmeq->dbbuf_sq_db = NULL;
525 nvmeq->dbbuf_cq_db = NULL;
526 nvmeq->dbbuf_sq_ei = NULL;
527 nvmeq->dbbuf_cq_ei = NULL;
528}
529
530static void nvme_dbbuf_set(struct nvme_dev *dev)
531{
532 struct nvme_command c = { };
533 unsigned int i;
534
535 if (!dev->dbbuf_dbs)
536 return;
537
538 c.dbbuf.opcode = nvme_admin_dbbuf;
539 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
540 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
541
542 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
543 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
544 /* Free memory and continue on */
545 nvme_dbbuf_dma_free(dev);
546
547 for (i = 1; i < dev->online_queues; i++)
548 nvme_dbbuf_free(&dev->queues[i]);
549 }
550}
551
552static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
553{
554 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
555}
556
557/* Update dbbuf and return true if an MMIO is required */
558static bool nvme_dbbuf_update_and_check_event(u16 value, __le32 *dbbuf_db,
559 volatile __le32 *dbbuf_ei)
560{
561 if (dbbuf_db) {
562 u16 old_value, event_idx;
563
564 /*
565 * Ensure that the queue is written before updating
566 * the doorbell in memory
567 */
568 wmb();
569
570 old_value = le32_to_cpu(*dbbuf_db);
571 *dbbuf_db = cpu_to_le32(value);
572
573 /*
574 * Ensure that the doorbell is updated before reading the event
575 * index from memory. The controller needs to provide similar
576 * ordering to ensure the event index is updated before reading
577 * the doorbell.
578 */
579 mb();
580
581 event_idx = le32_to_cpu(*dbbuf_ei);
582 if (!nvme_dbbuf_need_event(event_idx, value, old_value))
583 return false;
584 }
585
586 return true;
587}
588
589static struct nvme_descriptor_pools *
590nvme_setup_descriptor_pools(struct nvme_dev *dev, unsigned numa_node)
591{
592 struct nvme_descriptor_pools *pools = &dev->descriptor_pools[numa_node];
593 size_t small_align = NVME_SMALL_POOL_SIZE;
594
595 if (pools->small)
596 return pools; /* already initialized */
597
598 pools->large = dma_pool_create_node("nvme descriptor page", dev->dev,
599 NVME_CTRL_PAGE_SIZE, NVME_CTRL_PAGE_SIZE, 0, numa_node);
600 if (!pools->large)
601 return ERR_PTR(-ENOMEM);
602
603 if (dev->ctrl.quirks & NVME_QUIRK_DMAPOOL_ALIGN_512)
604 small_align = 512;
605
606 pools->small = dma_pool_create_node("nvme descriptor small", dev->dev,
607 NVME_SMALL_POOL_SIZE, small_align, 0, numa_node);
608 if (!pools->small) {
609 dma_pool_destroy(pools->large);
610 pools->large = NULL;
611 return ERR_PTR(-ENOMEM);
612 }
613
614 return pools;
615}
616
617static void nvme_release_descriptor_pools(struct nvme_dev *dev)
618{
619 unsigned i;
620
621 for (i = 0; i < nr_node_ids; i++) {
622 struct nvme_descriptor_pools *pools = &dev->descriptor_pools[i];
623
624 dma_pool_destroy(pools->large);
625 dma_pool_destroy(pools->small);
626 }
627}
628
629static int nvme_init_hctx_common(struct blk_mq_hw_ctx *hctx, void *data,
630 unsigned qid)
631{
632 struct nvme_dev *dev = to_nvme_dev(data);
633 struct nvme_queue *nvmeq = &dev->queues[qid];
634 struct nvme_descriptor_pools *pools;
635 struct blk_mq_tags *tags;
636
637 tags = qid ? dev->tagset.tags[qid - 1] : dev->admin_tagset.tags[0];
638 WARN_ON(tags != hctx->tags);
639 pools = nvme_setup_descriptor_pools(dev, hctx->numa_node);
640 if (IS_ERR(pools))
641 return PTR_ERR(pools);
642
643 nvmeq->descriptor_pools = *pools;
644 hctx->driver_data = nvmeq;
645 return 0;
646}
647
648static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
649 unsigned int hctx_idx)
650{
651 WARN_ON(hctx_idx != 0);
652 return nvme_init_hctx_common(hctx, data, 0);
653}
654
655static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
656 unsigned int hctx_idx)
657{
658 return nvme_init_hctx_common(hctx, data, hctx_idx + 1);
659}
660
661static int nvme_pci_init_request(struct blk_mq_tag_set *set,
662 struct request *req, unsigned int hctx_idx,
663 unsigned int numa_node)
664{
665 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
666
667 nvme_req(req)->ctrl = set->driver_data;
668 nvme_req(req)->cmd = &iod->cmd;
669 return 0;
670}
671
672static int queue_irq_offset(struct nvme_dev *dev)
673{
674 /* if we have more than 1 vec, admin queue offsets us by 1 */
675 if (dev->num_vecs > 1)
676 return 1;
677
678 return 0;
679}
680
681static void nvme_pci_map_queues(struct blk_mq_tag_set *set)
682{
683 struct nvme_dev *dev = to_nvme_dev(set->driver_data);
684 int i, qoff, offset;
685
686 offset = queue_irq_offset(dev);
687 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
688 struct blk_mq_queue_map *map = &set->map[i];
689
690 map->nr_queues = dev->io_queues[i];
691 if (!map->nr_queues) {
692 BUG_ON(i == HCTX_TYPE_DEFAULT);
693 continue;
694 }
695
696 /*
697 * The poll queue(s) doesn't have an IRQ (and hence IRQ
698 * affinity), so use the regular blk-mq cpu mapping
699 */
700 map->queue_offset = qoff;
701 if (i != HCTX_TYPE_POLL && offset)
702 blk_mq_map_hw_queues(map, dev->dev, offset);
703 else
704 blk_mq_map_queues(map);
705 qoff += map->nr_queues;
706 offset += map->nr_queues;
707 }
708}
709
710/*
711 * Write sq tail if we are asked to, or if the next command would wrap.
712 */
713static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
714{
715 if (!write_sq) {
716 u16 next_tail = nvmeq->sq_tail + 1;
717
718 if (next_tail == nvmeq->q_depth)
719 next_tail = 0;
720 if (next_tail != nvmeq->last_sq_tail)
721 return;
722 }
723
724 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
725 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
726 writel(nvmeq->sq_tail, nvmeq->q_db);
727 nvmeq->last_sq_tail = nvmeq->sq_tail;
728}
729
730static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq,
731 struct nvme_command *cmd)
732{
733 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
734 absolute_pointer(cmd), sizeof(*cmd));
735 if (++nvmeq->sq_tail == nvmeq->q_depth)
736 nvmeq->sq_tail = 0;
737}
738
739static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
740{
741 struct nvme_queue *nvmeq = hctx->driver_data;
742
743 spin_lock(&nvmeq->sq_lock);
744 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
745 nvme_write_sq_db(nvmeq, true);
746 spin_unlock(&nvmeq->sq_lock);
747}
748
749enum nvme_use_sgl {
750 SGL_UNSUPPORTED,
751 SGL_SUPPORTED,
752 SGL_FORCED,
753};
754
755static inline bool nvme_pci_metadata_use_sgls(struct request *req)
756{
757 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
758 struct nvme_dev *dev = nvmeq->dev;
759
760 if (!nvme_ctrl_meta_sgl_supported(&dev->ctrl))
761 return false;
762 return req->nr_integrity_segments > 1 ||
763 nvme_req(req)->flags & NVME_REQ_USERCMD;
764}
765
766static inline enum nvme_use_sgl nvme_pci_use_sgls(struct nvme_dev *dev,
767 struct request *req)
768{
769 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
770
771 if (nvmeq->qid && nvme_ctrl_sgl_supported(&dev->ctrl)) {
772 /*
773 * When the controller is capable of using SGL, there are
774 * several conditions that we force to use it:
775 *
776 * 1. A request containing page gaps within the controller's
777 * mask can not use the PRP format.
778 *
779 * 2. User commands use SGL because that lets the device
780 * validate the requested transfer lengths.
781 *
782 * 3. Multiple integrity segments must use SGL as that's the
783 * only way to describe such a command in NVMe.
784 */
785 if (req_phys_gap_mask(req) & (NVME_CTRL_PAGE_SIZE - 1) ||
786 nvme_req(req)->flags & NVME_REQ_USERCMD ||
787 req->nr_integrity_segments > 1)
788 return SGL_FORCED;
789 return SGL_SUPPORTED;
790 }
791
792 return SGL_UNSUPPORTED;
793}
794
795static unsigned int nvme_pci_avg_seg_size(struct request *req)
796{
797 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
798 unsigned int nseg;
799
800 if (blk_rq_dma_map_coalesce(&iod->dma_state))
801 nseg = 1;
802 else
803 nseg = blk_rq_nr_phys_segments(req);
804 return DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
805}
806
807static inline struct dma_pool *nvme_dma_pool(struct nvme_queue *nvmeq,
808 struct nvme_iod *iod)
809{
810 if (iod->flags & IOD_SMALL_DESCRIPTOR)
811 return nvmeq->descriptor_pools.small;
812 return nvmeq->descriptor_pools.large;
813}
814
815static inline bool nvme_pci_cmd_use_meta_sgl(struct nvme_command *cmd)
816{
817 return (cmd->common.flags & NVME_CMD_SGL_ALL) == NVME_CMD_SGL_METASEG;
818}
819
820static inline bool nvme_pci_cmd_use_sgl(struct nvme_command *cmd)
821{
822 return cmd->common.flags &
823 (NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG);
824}
825
826static inline dma_addr_t nvme_pci_first_desc_dma_addr(struct nvme_command *cmd)
827{
828 if (nvme_pci_cmd_use_sgl(cmd))
829 return le64_to_cpu(cmd->common.dptr.sgl.addr);
830 return le64_to_cpu(cmd->common.dptr.prp2);
831}
832
833static void nvme_free_descriptors(struct request *req)
834{
835 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
836 const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
837 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
838 dma_addr_t dma_addr = nvme_pci_first_desc_dma_addr(&iod->cmd);
839 int i;
840
841 if (iod->nr_descriptors == 1) {
842 dma_pool_free(nvme_dma_pool(nvmeq, iod), iod->descriptors[0],
843 dma_addr);
844 return;
845 }
846
847 for (i = 0; i < iod->nr_descriptors; i++) {
848 __le64 *prp_list = iod->descriptors[i];
849 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
850
851 dma_pool_free(nvmeq->descriptor_pools.large, prp_list,
852 dma_addr);
853 dma_addr = next_dma_addr;
854 }
855}
856
857static void nvme_free_prps(struct request *req, unsigned int attrs)
858{
859 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
860 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
861 unsigned int i;
862
863 for (i = 0; i < iod->nr_dma_vecs; i++)
864 dma_unmap_phys(nvmeq->dev->dev, iod->dma_vecs[i].addr,
865 iod->dma_vecs[i].len, rq_dma_dir(req), attrs);
866 mempool_free(iod->dma_vecs, nvmeq->dev->dmavec_mempool);
867}
868
869static void nvme_free_sgls(struct request *req, struct nvme_sgl_desc *sge,
870 struct nvme_sgl_desc *sg_list, unsigned int attrs)
871{
872 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
873 enum dma_data_direction dir = rq_dma_dir(req);
874 unsigned int len = le32_to_cpu(sge->length);
875 struct device *dma_dev = nvmeq->dev->dev;
876 unsigned int i;
877
878 if (sge->type == (NVME_SGL_FMT_DATA_DESC << 4)) {
879 dma_unmap_phys(dma_dev, le64_to_cpu(sge->addr), len, dir,
880 attrs);
881 return;
882 }
883
884 for (i = 0; i < len / sizeof(*sg_list); i++)
885 dma_unmap_phys(dma_dev, le64_to_cpu(sg_list[i].addr),
886 le32_to_cpu(sg_list[i].length), dir, attrs);
887}
888
889static void nvme_unmap_metadata(struct request *req)
890{
891 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
892 enum pci_p2pdma_map_type map = PCI_P2PDMA_MAP_NONE;
893 enum dma_data_direction dir = rq_dma_dir(req);
894 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
895 struct device *dma_dev = nvmeq->dev->dev;
896 struct nvme_sgl_desc *sge = iod->meta_descriptor;
897 unsigned int attrs = 0;
898
899 if (iod->flags & IOD_SINGLE_META_SEGMENT) {
900 dma_unmap_page(dma_dev, iod->meta_dma,
901 rq_integrity_vec(req).bv_len,
902 rq_dma_dir(req));
903 return;
904 }
905
906 if (iod->flags & IOD_META_P2P)
907 map = PCI_P2PDMA_MAP_BUS_ADDR;
908 else if (iod->flags & IOD_META_MMIO) {
909 map = PCI_P2PDMA_MAP_THRU_HOST_BRIDGE;
910 attrs |= DMA_ATTR_MMIO;
911 }
912
913 if (!blk_rq_dma_unmap(req, dma_dev, &iod->meta_dma_state,
914 iod->meta_total_len, map)) {
915 if (nvme_pci_cmd_use_meta_sgl(&iod->cmd))
916 nvme_free_sgls(req, sge, &sge[1], attrs);
917 else
918 dma_unmap_phys(dma_dev, iod->meta_dma,
919 iod->meta_total_len, dir, attrs);
920 }
921
922 if (iod->meta_descriptor)
923 dma_pool_free(nvmeq->descriptor_pools.small,
924 iod->meta_descriptor, iod->meta_dma);
925}
926
927static void nvme_unmap_data(struct request *req)
928{
929 enum pci_p2pdma_map_type map = PCI_P2PDMA_MAP_NONE;
930 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
931 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
932 struct device *dma_dev = nvmeq->dev->dev;
933 unsigned int attrs = 0;
934
935 if (iod->flags & IOD_SINGLE_SEGMENT) {
936 static_assert(offsetof(union nvme_data_ptr, prp1) ==
937 offsetof(union nvme_data_ptr, sgl.addr));
938 dma_unmap_page(dma_dev, le64_to_cpu(iod->cmd.common.dptr.prp1),
939 iod->total_len, rq_dma_dir(req));
940 return;
941 }
942
943 if (iod->flags & IOD_DATA_P2P)
944 map = PCI_P2PDMA_MAP_BUS_ADDR;
945 else if (iod->flags & IOD_DATA_MMIO) {
946 map = PCI_P2PDMA_MAP_THRU_HOST_BRIDGE;
947 attrs |= DMA_ATTR_MMIO;
948 }
949
950 if (!blk_rq_dma_unmap(req, dma_dev, &iod->dma_state, iod->total_len,
951 map)) {
952 if (nvme_pci_cmd_use_sgl(&iod->cmd))
953 nvme_free_sgls(req, &iod->cmd.common.dptr.sgl,
954 iod->descriptors[0], attrs);
955 else
956 nvme_free_prps(req, attrs);
957 }
958
959 if (iod->nr_descriptors)
960 nvme_free_descriptors(req);
961}
962
963static bool nvme_pci_prp_save_mapping(struct request *req,
964 struct device *dma_dev,
965 struct blk_dma_iter *iter)
966{
967 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
968
969 if (dma_use_iova(&iod->dma_state) || !dma_need_unmap(dma_dev))
970 return true;
971
972 if (!iod->nr_dma_vecs) {
973 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
974
975 iod->dma_vecs = mempool_alloc(nvmeq->dev->dmavec_mempool,
976 GFP_ATOMIC);
977 if (!iod->dma_vecs) {
978 iter->status = BLK_STS_RESOURCE;
979 return false;
980 }
981 }
982
983 iod->dma_vecs[iod->nr_dma_vecs].addr = iter->addr;
984 iod->dma_vecs[iod->nr_dma_vecs].len = iter->len;
985 iod->nr_dma_vecs++;
986 return true;
987}
988
989static bool nvme_pci_prp_iter_next(struct request *req, struct device *dma_dev,
990 struct blk_dma_iter *iter)
991{
992 if (iter->len)
993 return true;
994 if (!blk_rq_dma_map_iter_next(req, dma_dev, iter))
995 return false;
996 return nvme_pci_prp_save_mapping(req, dma_dev, iter);
997}
998
999static blk_status_t nvme_pci_setup_data_prp(struct request *req,
1000 struct blk_dma_iter *iter)
1001{
1002 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1003 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1004 unsigned int length = blk_rq_payload_bytes(req);
1005 dma_addr_t prp1_dma, prp2_dma = 0;
1006 unsigned int prp_len, i;
1007 __le64 *prp_list;
1008
1009 if (!nvme_pci_prp_save_mapping(req, nvmeq->dev->dev, iter))
1010 return iter->status;
1011
1012 /*
1013 * PRP1 always points to the start of the DMA transfers.
1014 *
1015 * This is the only PRP (except for the list entries) that could be
1016 * non-aligned.
1017 */
1018 prp1_dma = iter->addr;
1019 prp_len = min(length, NVME_CTRL_PAGE_SIZE -
1020 (iter->addr & (NVME_CTRL_PAGE_SIZE - 1)));
1021 iod->total_len += prp_len;
1022 iter->addr += prp_len;
1023 iter->len -= prp_len;
1024 length -= prp_len;
1025 if (!length)
1026 goto done;
1027
1028 if (!nvme_pci_prp_iter_next(req, nvmeq->dev->dev, iter)) {
1029 if (WARN_ON_ONCE(!iter->status))
1030 goto bad_sgl;
1031 goto done;
1032 }
1033
1034 /*
1035 * PRP2 is usually a list, but can point to data if all data to be
1036 * transferred fits into PRP1 + PRP2:
1037 */
1038 if (length <= NVME_CTRL_PAGE_SIZE) {
1039 prp2_dma = iter->addr;
1040 iod->total_len += length;
1041 goto done;
1042 }
1043
1044 if (DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE) <=
1045 NVME_SMALL_POOL_SIZE / sizeof(__le64))
1046 iod->flags |= IOD_SMALL_DESCRIPTOR;
1047
1048 prp_list = dma_pool_alloc(nvme_dma_pool(nvmeq, iod), GFP_ATOMIC,
1049 &prp2_dma);
1050 if (!prp_list) {
1051 iter->status = BLK_STS_RESOURCE;
1052 goto done;
1053 }
1054 iod->descriptors[iod->nr_descriptors++] = prp_list;
1055
1056 i = 0;
1057 for (;;) {
1058 prp_list[i++] = cpu_to_le64(iter->addr);
1059 prp_len = min(length, NVME_CTRL_PAGE_SIZE);
1060 if (WARN_ON_ONCE(iter->len < prp_len))
1061 goto bad_sgl;
1062
1063 iod->total_len += prp_len;
1064 iter->addr += prp_len;
1065 iter->len -= prp_len;
1066 length -= prp_len;
1067 if (!length)
1068 break;
1069
1070 if (!nvme_pci_prp_iter_next(req, nvmeq->dev->dev, iter)) {
1071 if (WARN_ON_ONCE(!iter->status))
1072 goto bad_sgl;
1073 goto done;
1074 }
1075
1076 /*
1077 * If we've filled the entire descriptor, allocate a new that is
1078 * pointed to be the last entry in the previous PRP list. To
1079 * accommodate for that move the last actual entry to the new
1080 * descriptor.
1081 */
1082 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
1083 __le64 *old_prp_list = prp_list;
1084 dma_addr_t prp_list_dma;
1085
1086 prp_list = dma_pool_alloc(nvmeq->descriptor_pools.large,
1087 GFP_ATOMIC, &prp_list_dma);
1088 if (!prp_list) {
1089 iter->status = BLK_STS_RESOURCE;
1090 goto done;
1091 }
1092 iod->descriptors[iod->nr_descriptors++] = prp_list;
1093
1094 prp_list[0] = old_prp_list[i - 1];
1095 old_prp_list[i - 1] = cpu_to_le64(prp_list_dma);
1096 i = 1;
1097 }
1098 }
1099
1100done:
1101 /*
1102 * nvme_unmap_data uses the DPT field in the SQE to tear down the
1103 * mapping, so initialize it even for failures.
1104 */
1105 iod->cmd.common.dptr.prp1 = cpu_to_le64(prp1_dma);
1106 iod->cmd.common.dptr.prp2 = cpu_to_le64(prp2_dma);
1107 if (unlikely(iter->status))
1108 nvme_unmap_data(req);
1109 return iter->status;
1110
1111bad_sgl:
1112 dev_err_once(nvmeq->dev->dev,
1113 "Incorrectly formed request for payload:%d nents:%d\n",
1114 blk_rq_payload_bytes(req), blk_rq_nr_phys_segments(req));
1115 return BLK_STS_IOERR;
1116}
1117
1118static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
1119 struct blk_dma_iter *iter)
1120{
1121 sge->addr = cpu_to_le64(iter->addr);
1122 sge->length = cpu_to_le32(iter->len);
1123 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
1124}
1125
1126static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
1127 dma_addr_t dma_addr, int entries)
1128{
1129 sge->addr = cpu_to_le64(dma_addr);
1130 sge->length = cpu_to_le32(entries * sizeof(*sge));
1131 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
1132}
1133
1134static blk_status_t nvme_pci_setup_data_sgl(struct request *req,
1135 struct blk_dma_iter *iter)
1136{
1137 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1138 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1139 unsigned int entries = blk_rq_nr_phys_segments(req);
1140 struct nvme_sgl_desc *sg_list;
1141 dma_addr_t sgl_dma;
1142 unsigned int mapped = 0;
1143
1144 /* set the transfer type as SGL */
1145 iod->cmd.common.flags = NVME_CMD_SGL_METABUF;
1146
1147 if (entries == 1 || blk_rq_dma_map_coalesce(&iod->dma_state)) {
1148 nvme_pci_sgl_set_data(&iod->cmd.common.dptr.sgl, iter);
1149 iod->total_len += iter->len;
1150 return BLK_STS_OK;
1151 }
1152
1153 if (entries <= NVME_SMALL_POOL_SIZE / sizeof(*sg_list))
1154 iod->flags |= IOD_SMALL_DESCRIPTOR;
1155
1156 sg_list = dma_pool_alloc(nvme_dma_pool(nvmeq, iod), GFP_ATOMIC,
1157 &sgl_dma);
1158 if (!sg_list)
1159 return BLK_STS_RESOURCE;
1160 iod->descriptors[iod->nr_descriptors++] = sg_list;
1161
1162 do {
1163 if (WARN_ON_ONCE(mapped == entries)) {
1164 iter->status = BLK_STS_IOERR;
1165 break;
1166 }
1167 nvme_pci_sgl_set_data(&sg_list[mapped++], iter);
1168 iod->total_len += iter->len;
1169 } while (blk_rq_dma_map_iter_next(req, nvmeq->dev->dev, iter));
1170
1171 nvme_pci_sgl_set_seg(&iod->cmd.common.dptr.sgl, sgl_dma, mapped);
1172 if (unlikely(iter->status))
1173 nvme_unmap_data(req);
1174 return iter->status;
1175}
1176
1177static blk_status_t nvme_pci_setup_data_simple(struct request *req,
1178 enum nvme_use_sgl use_sgl)
1179{
1180 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1181 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1182 struct bio_vec bv = req_bvec(req);
1183 unsigned int prp1_offset = bv.bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
1184 bool prp_possible = prp1_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2;
1185 dma_addr_t dma_addr;
1186
1187 if (!use_sgl && !prp_possible)
1188 return BLK_STS_AGAIN;
1189 if (is_pci_p2pdma_page(bv.bv_page))
1190 return BLK_STS_AGAIN;
1191
1192 dma_addr = dma_map_bvec(nvmeq->dev->dev, &bv, rq_dma_dir(req), 0);
1193 if (dma_mapping_error(nvmeq->dev->dev, dma_addr))
1194 return BLK_STS_RESOURCE;
1195 iod->total_len = bv.bv_len;
1196 iod->flags |= IOD_SINGLE_SEGMENT;
1197
1198 if (use_sgl == SGL_FORCED || !prp_possible) {
1199 iod->cmd.common.flags = NVME_CMD_SGL_METABUF;
1200 iod->cmd.common.dptr.sgl.addr = cpu_to_le64(dma_addr);
1201 iod->cmd.common.dptr.sgl.length = cpu_to_le32(bv.bv_len);
1202 iod->cmd.common.dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
1203 } else {
1204 unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - prp1_offset;
1205
1206 iod->cmd.common.dptr.prp1 = cpu_to_le64(dma_addr);
1207 iod->cmd.common.dptr.prp2 = 0;
1208 if (bv.bv_len > first_prp_len)
1209 iod->cmd.common.dptr.prp2 =
1210 cpu_to_le64(dma_addr + first_prp_len);
1211 }
1212
1213 return BLK_STS_OK;
1214}
1215
1216static blk_status_t nvme_map_data(struct request *req)
1217{
1218 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1219 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1220 struct nvme_dev *dev = nvmeq->dev;
1221 enum nvme_use_sgl use_sgl = nvme_pci_use_sgls(dev, req);
1222 struct blk_dma_iter iter;
1223 blk_status_t ret;
1224
1225 /*
1226 * Try to skip the DMA iterator for single segment requests, as that
1227 * significantly improves performances for small I/O sizes.
1228 */
1229 if (blk_rq_nr_phys_segments(req) == 1) {
1230 ret = nvme_pci_setup_data_simple(req, use_sgl);
1231 if (ret != BLK_STS_AGAIN)
1232 return ret;
1233 }
1234
1235 if (!blk_rq_dma_map_iter_start(req, dev->dev, &iod->dma_state, &iter))
1236 return iter.status;
1237
1238 switch (iter.p2pdma.map) {
1239 case PCI_P2PDMA_MAP_BUS_ADDR:
1240 iod->flags |= IOD_DATA_P2P;
1241 break;
1242 case PCI_P2PDMA_MAP_THRU_HOST_BRIDGE:
1243 iod->flags |= IOD_DATA_MMIO;
1244 break;
1245 case PCI_P2PDMA_MAP_NONE:
1246 break;
1247 default:
1248 return BLK_STS_RESOURCE;
1249 }
1250
1251 if (use_sgl == SGL_FORCED ||
1252 (use_sgl == SGL_SUPPORTED &&
1253 (sgl_threshold && nvme_pci_avg_seg_size(req) >= sgl_threshold)))
1254 return nvme_pci_setup_data_sgl(req, &iter);
1255 return nvme_pci_setup_data_prp(req, &iter);
1256}
1257
1258static blk_status_t nvme_pci_setup_meta_iter(struct request *req)
1259{
1260 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1261 unsigned int entries = req->nr_integrity_segments;
1262 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1263 struct nvme_dev *dev = nvmeq->dev;
1264 struct nvme_sgl_desc *sg_list;
1265 struct blk_dma_iter iter;
1266 dma_addr_t sgl_dma;
1267 int i = 0;
1268
1269 if (!blk_rq_integrity_dma_map_iter_start(req, dev->dev,
1270 &iod->meta_dma_state, &iter))
1271 return iter.status;
1272
1273 switch (iter.p2pdma.map) {
1274 case PCI_P2PDMA_MAP_BUS_ADDR:
1275 iod->flags |= IOD_META_P2P;
1276 break;
1277 case PCI_P2PDMA_MAP_THRU_HOST_BRIDGE:
1278 iod->flags |= IOD_META_MMIO;
1279 break;
1280 case PCI_P2PDMA_MAP_NONE:
1281 break;
1282 default:
1283 return BLK_STS_RESOURCE;
1284 }
1285
1286 if (blk_rq_dma_map_coalesce(&iod->meta_dma_state))
1287 entries = 1;
1288
1289 /*
1290 * The NVMe MPTR descriptor has an implicit length that the host and
1291 * device must agree on to avoid data/memory corruption. We trust the
1292 * kernel allocated correctly based on the format's parameters, so use
1293 * the more efficient MPTR to avoid extra dma pool allocations for the
1294 * SGL indirection.
1295 *
1296 * But for user commands, we don't necessarily know what they do, so
1297 * the driver can't validate the metadata buffer size. The SGL
1298 * descriptor provides an explicit length, so we're relying on that
1299 * mechanism to catch any misunderstandings between the application and
1300 * device.
1301 *
1302 * P2P DMA also needs to use the blk_dma_iter method, so mptr setup
1303 * leverages this routine when that happens.
1304 */
1305 if (!nvme_ctrl_meta_sgl_supported(&dev->ctrl) ||
1306 (entries == 1 && !(nvme_req(req)->flags & NVME_REQ_USERCMD))) {
1307 iod->cmd.common.metadata = cpu_to_le64(iter.addr);
1308 iod->meta_total_len = iter.len;
1309 iod->meta_dma = iter.addr;
1310 iod->meta_descriptor = NULL;
1311 return BLK_STS_OK;
1312 }
1313
1314 sg_list = dma_pool_alloc(nvmeq->descriptor_pools.small, GFP_ATOMIC,
1315 &sgl_dma);
1316 if (!sg_list)
1317 return BLK_STS_RESOURCE;
1318
1319 iod->meta_descriptor = sg_list;
1320 iod->meta_dma = sgl_dma;
1321 iod->cmd.common.flags = NVME_CMD_SGL_METASEG;
1322 iod->cmd.common.metadata = cpu_to_le64(sgl_dma);
1323 if (entries == 1) {
1324 iod->meta_total_len = iter.len;
1325 nvme_pci_sgl_set_data(sg_list, &iter);
1326 return BLK_STS_OK;
1327 }
1328
1329 sgl_dma += sizeof(*sg_list);
1330 do {
1331 nvme_pci_sgl_set_data(&sg_list[++i], &iter);
1332 iod->meta_total_len += iter.len;
1333 } while (blk_rq_integrity_dma_map_iter_next(req, dev->dev, &iter));
1334
1335 nvme_pci_sgl_set_seg(sg_list, sgl_dma, i);
1336 if (unlikely(iter.status))
1337 nvme_unmap_metadata(req);
1338 return iter.status;
1339}
1340
1341static blk_status_t nvme_pci_setup_meta_mptr(struct request *req)
1342{
1343 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1344 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1345 struct bio_vec bv = rq_integrity_vec(req);
1346
1347 if (is_pci_p2pdma_page(bv.bv_page))
1348 return nvme_pci_setup_meta_iter(req);
1349
1350 iod->meta_dma = dma_map_bvec(nvmeq->dev->dev, &bv, rq_dma_dir(req), 0);
1351 if (dma_mapping_error(nvmeq->dev->dev, iod->meta_dma))
1352 return BLK_STS_IOERR;
1353 iod->cmd.common.metadata = cpu_to_le64(iod->meta_dma);
1354 iod->flags |= IOD_SINGLE_META_SEGMENT;
1355 return BLK_STS_OK;
1356}
1357
1358static blk_status_t nvme_map_metadata(struct request *req)
1359{
1360 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1361
1362 if ((iod->cmd.common.flags & NVME_CMD_SGL_METABUF) &&
1363 nvme_pci_metadata_use_sgls(req))
1364 return nvme_pci_setup_meta_iter(req);
1365 return nvme_pci_setup_meta_mptr(req);
1366}
1367
1368static blk_status_t nvme_prep_rq(struct request *req)
1369{
1370 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1371 blk_status_t ret;
1372
1373 iod->flags = 0;
1374 iod->nr_descriptors = 0;
1375 iod->total_len = 0;
1376 iod->meta_total_len = 0;
1377 iod->nr_dma_vecs = 0;
1378
1379 ret = nvme_setup_cmd(req->q->queuedata, req);
1380 if (ret)
1381 return ret;
1382
1383 if (blk_rq_nr_phys_segments(req)) {
1384 ret = nvme_map_data(req);
1385 if (ret)
1386 goto out_free_cmd;
1387 }
1388
1389 if (blk_integrity_rq(req)) {
1390 ret = nvme_map_metadata(req);
1391 if (ret)
1392 goto out_unmap_data;
1393 }
1394
1395 nvme_start_request(req);
1396 return BLK_STS_OK;
1397out_unmap_data:
1398 if (blk_rq_nr_phys_segments(req))
1399 nvme_unmap_data(req);
1400out_free_cmd:
1401 nvme_cleanup_cmd(req);
1402 return ret;
1403}
1404
1405static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
1406 const struct blk_mq_queue_data *bd)
1407{
1408 struct nvme_queue *nvmeq = hctx->driver_data;
1409 struct nvme_dev *dev = nvmeq->dev;
1410 struct request *req = bd->rq;
1411 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1412 blk_status_t ret;
1413
1414 /*
1415 * We should not need to do this, but we're still using this to
1416 * ensure we can drain requests on a dying queue.
1417 */
1418 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
1419 return BLK_STS_IOERR;
1420
1421 if (unlikely(!nvme_check_ready(&dev->ctrl, req, true)))
1422 return nvme_fail_nonready_command(&dev->ctrl, req);
1423
1424 ret = nvme_prep_rq(req);
1425 if (unlikely(ret))
1426 return ret;
1427 spin_lock(&nvmeq->sq_lock);
1428 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
1429 nvme_write_sq_db(nvmeq, bd->last);
1430 spin_unlock(&nvmeq->sq_lock);
1431 return BLK_STS_OK;
1432}
1433
1434static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct rq_list *rqlist)
1435{
1436 struct request *req;
1437
1438 if (rq_list_empty(rqlist))
1439 return;
1440
1441 spin_lock(&nvmeq->sq_lock);
1442 while ((req = rq_list_pop(rqlist))) {
1443 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1444
1445 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
1446 }
1447 nvme_write_sq_db(nvmeq, true);
1448 spin_unlock(&nvmeq->sq_lock);
1449}
1450
1451static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req)
1452{
1453 /*
1454 * We should not need to do this, but we're still using this to
1455 * ensure we can drain requests on a dying queue.
1456 */
1457 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
1458 return false;
1459 if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true)))
1460 return false;
1461
1462 return nvme_prep_rq(req) == BLK_STS_OK;
1463}
1464
1465static void nvme_queue_rqs(struct rq_list *rqlist)
1466{
1467 struct rq_list submit_list = { };
1468 struct rq_list requeue_list = { };
1469 struct nvme_queue *nvmeq = NULL;
1470 struct request *req;
1471
1472 while ((req = rq_list_pop(rqlist))) {
1473 if (nvmeq && nvmeq != req->mq_hctx->driver_data)
1474 nvme_submit_cmds(nvmeq, &submit_list);
1475 nvmeq = req->mq_hctx->driver_data;
1476
1477 if (nvme_prep_rq_batch(nvmeq, req))
1478 rq_list_add_tail(&submit_list, req);
1479 else
1480 rq_list_add_tail(&requeue_list, req);
1481 }
1482
1483 if (nvmeq)
1484 nvme_submit_cmds(nvmeq, &submit_list);
1485 *rqlist = requeue_list;
1486}
1487
1488static __always_inline void nvme_pci_unmap_rq(struct request *req)
1489{
1490 if (blk_integrity_rq(req))
1491 nvme_unmap_metadata(req);
1492 if (blk_rq_nr_phys_segments(req))
1493 nvme_unmap_data(req);
1494}
1495
1496static void nvme_pci_complete_rq(struct request *req)
1497{
1498 nvme_pci_unmap_rq(req);
1499 nvme_complete_rq(req);
1500}
1501
1502static void nvme_pci_complete_batch(struct io_comp_batch *iob)
1503{
1504 nvme_complete_batch(iob, nvme_pci_unmap_rq);
1505}
1506
1507/* We read the CQE phase first to check if the rest of the entry is valid */
1508static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
1509{
1510 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
1511
1512 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
1513}
1514
1515static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
1516{
1517 u16 head = nvmeq->cq_head;
1518
1519 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
1520 nvmeq->dbbuf_cq_ei))
1521 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
1522}
1523
1524static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
1525{
1526 if (!nvmeq->qid)
1527 return nvmeq->dev->admin_tagset.tags[0];
1528 return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
1529}
1530
1531static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
1532 struct io_comp_batch *iob, u16 idx)
1533{
1534 struct nvme_completion *cqe = &nvmeq->cqes[idx];
1535 __u16 command_id = READ_ONCE(cqe->command_id);
1536 struct request *req;
1537
1538 /*
1539 * AEN requests are special as they don't time out and can
1540 * survive any kind of queue freeze and often don't respond to
1541 * aborts. We don't even bother to allocate a struct request
1542 * for them but rather special case them here.
1543 */
1544 if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
1545 nvme_complete_async_event(&nvmeq->dev->ctrl,
1546 cqe->status, &cqe->result);
1547 return;
1548 }
1549
1550 req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id);
1551 if (unlikely(!req)) {
1552 dev_warn(nvmeq->dev->ctrl.device,
1553 "invalid id %d completed on queue %d\n",
1554 command_id, le16_to_cpu(cqe->sq_id));
1555 return;
1556 }
1557
1558 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
1559 if (!nvme_try_complete_req(req, cqe->status, cqe->result) &&
1560 !blk_mq_add_to_batch(req, iob,
1561 nvme_req(req)->status != NVME_SC_SUCCESS,
1562 nvme_pci_complete_batch))
1563 nvme_pci_complete_rq(req);
1564}
1565
1566static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1567{
1568 u32 tmp = nvmeq->cq_head + 1;
1569
1570 if (tmp == nvmeq->q_depth) {
1571 nvmeq->cq_head = 0;
1572 nvmeq->cq_phase ^= 1;
1573 } else {
1574 nvmeq->cq_head = tmp;
1575 }
1576}
1577
1578static inline bool nvme_poll_cq(struct nvme_queue *nvmeq,
1579 struct io_comp_batch *iob)
1580{
1581 bool found = false;
1582
1583 while (nvme_cqe_pending(nvmeq)) {
1584 found = true;
1585 /*
1586 * load-load control dependency between phase and the rest of
1587 * the cqe requires a full read memory barrier
1588 */
1589 dma_rmb();
1590 nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head);
1591 nvme_update_cq_head(nvmeq);
1592 }
1593
1594 if (found)
1595 nvme_ring_cq_doorbell(nvmeq);
1596 return found;
1597}
1598
1599static irqreturn_t nvme_irq(int irq, void *data)
1600{
1601 struct nvme_queue *nvmeq = data;
1602 DEFINE_IO_COMP_BATCH(iob);
1603
1604 if (nvme_poll_cq(nvmeq, &iob)) {
1605 if (!rq_list_empty(&iob.req_list))
1606 nvme_pci_complete_batch(&iob);
1607 return IRQ_HANDLED;
1608 }
1609 return IRQ_NONE;
1610}
1611
1612static irqreturn_t nvme_irq_check(int irq, void *data)
1613{
1614 struct nvme_queue *nvmeq = data;
1615
1616 if (nvme_cqe_pending(nvmeq))
1617 return IRQ_WAKE_THREAD;
1618 return IRQ_NONE;
1619}
1620
1621/*
1622 * Poll for completions for any interrupt driven queue
1623 * Can be called from any context.
1624 */
1625static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
1626{
1627 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1628 int irq;
1629
1630 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
1631
1632 irq = pci_irq_vector(pdev, nvmeq->cq_vector);
1633 disable_irq(irq);
1634 spin_lock(&nvmeq->cq_poll_lock);
1635 nvme_poll_cq(nvmeq, NULL);
1636 spin_unlock(&nvmeq->cq_poll_lock);
1637 enable_irq(irq);
1638}
1639
1640static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob)
1641{
1642 struct nvme_queue *nvmeq = hctx->driver_data;
1643 bool found;
1644
1645 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags) ||
1646 !nvme_cqe_pending(nvmeq))
1647 return 0;
1648
1649 spin_lock(&nvmeq->cq_poll_lock);
1650 found = nvme_poll_cq(nvmeq, iob);
1651 spin_unlock(&nvmeq->cq_poll_lock);
1652
1653 return found;
1654}
1655
1656static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1657{
1658 struct nvme_dev *dev = to_nvme_dev(ctrl);
1659 struct nvme_queue *nvmeq = &dev->queues[0];
1660 struct nvme_command c = { };
1661
1662 c.common.opcode = nvme_admin_async_event;
1663 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1664
1665 spin_lock(&nvmeq->sq_lock);
1666 nvme_sq_copy_cmd(nvmeq, &c);
1667 nvme_write_sq_db(nvmeq, true);
1668 spin_unlock(&nvmeq->sq_lock);
1669}
1670
1671static int nvme_pci_subsystem_reset(struct nvme_ctrl *ctrl)
1672{
1673 struct nvme_dev *dev = to_nvme_dev(ctrl);
1674 int ret = 0;
1675
1676 /*
1677 * Taking the shutdown_lock ensures the BAR mapping is not being
1678 * altered by reset_work. Holding this lock before the RESETTING state
1679 * change, if successful, also ensures nvme_remove won't be able to
1680 * proceed to iounmap until we're done.
1681 */
1682 mutex_lock(&dev->shutdown_lock);
1683 if (!dev->bar_mapped_size) {
1684 ret = -ENODEV;
1685 goto unlock;
1686 }
1687
1688 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_RESETTING)) {
1689 ret = -EBUSY;
1690 goto unlock;
1691 }
1692
1693 writel(NVME_SUBSYS_RESET, dev->bar + NVME_REG_NSSR);
1694
1695 if (!nvme_change_ctrl_state(ctrl, NVME_CTRL_CONNECTING) ||
1696 !nvme_change_ctrl_state(ctrl, NVME_CTRL_LIVE))
1697 goto unlock;
1698
1699 /*
1700 * Read controller status to flush the previous write and trigger a
1701 * pcie read error.
1702 */
1703 readl(dev->bar + NVME_REG_CSTS);
1704unlock:
1705 mutex_unlock(&dev->shutdown_lock);
1706 return ret;
1707}
1708
1709static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1710{
1711 struct nvme_command c = { };
1712
1713 c.delete_queue.opcode = opcode;
1714 c.delete_queue.qid = cpu_to_le16(id);
1715
1716 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1717}
1718
1719static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1720 struct nvme_queue *nvmeq, s16 vector)
1721{
1722 struct nvme_command c = { };
1723 int flags = NVME_QUEUE_PHYS_CONTIG;
1724
1725 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
1726 flags |= NVME_CQ_IRQ_ENABLED;
1727
1728 /*
1729 * Note: we (ab)use the fact that the prp fields survive if no data
1730 * is attached to the request.
1731 */
1732 c.create_cq.opcode = nvme_admin_create_cq;
1733 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1734 c.create_cq.cqid = cpu_to_le16(qid);
1735 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1736 c.create_cq.cq_flags = cpu_to_le16(flags);
1737 c.create_cq.irq_vector = cpu_to_le16(vector);
1738
1739 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1740}
1741
1742static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1743 struct nvme_queue *nvmeq)
1744{
1745 struct nvme_ctrl *ctrl = &dev->ctrl;
1746 struct nvme_command c = { };
1747 int flags = NVME_QUEUE_PHYS_CONTIG;
1748
1749 /*
1750 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1751 * set. Since URGENT priority is zeroes, it makes all queues
1752 * URGENT.
1753 */
1754 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1755 flags |= NVME_SQ_PRIO_MEDIUM;
1756
1757 /*
1758 * Note: we (ab)use the fact that the prp fields survive if no data
1759 * is attached to the request.
1760 */
1761 c.create_sq.opcode = nvme_admin_create_sq;
1762 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1763 c.create_sq.sqid = cpu_to_le16(qid);
1764 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1765 c.create_sq.sq_flags = cpu_to_le16(flags);
1766 c.create_sq.cqid = cpu_to_le16(qid);
1767
1768 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1769}
1770
1771static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1772{
1773 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1774}
1775
1776static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1777{
1778 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1779}
1780
1781static enum rq_end_io_ret abort_endio(struct request *req, blk_status_t error,
1782 const struct io_comp_batch *iob)
1783{
1784 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1785
1786 dev_warn(nvmeq->dev->ctrl.device,
1787 "Abort status: 0x%x", nvme_req(req)->status);
1788 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1789 blk_mq_free_request(req);
1790 return RQ_END_IO_NONE;
1791}
1792
1793static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1794{
1795 /* If true, indicates loss of adapter communication, possibly by a
1796 * NVMe Subsystem reset.
1797 */
1798 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1799
1800 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1801 switch (nvme_ctrl_state(&dev->ctrl)) {
1802 case NVME_CTRL_RESETTING:
1803 case NVME_CTRL_CONNECTING:
1804 return false;
1805 default:
1806 break;
1807 }
1808
1809 /* We shouldn't reset unless the controller is on fatal error state
1810 * _or_ if we lost the communication with it.
1811 */
1812 if (!(csts & NVME_CSTS_CFS) && !nssro)
1813 return false;
1814
1815 return true;
1816}
1817
1818static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1819{
1820 /* Read a config register to help see what died. */
1821 u16 pci_status;
1822 int result;
1823
1824 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1825 &pci_status);
1826 if (result == PCIBIOS_SUCCESSFUL)
1827 dev_warn(dev->ctrl.device,
1828 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1829 csts, pci_status);
1830 else
1831 dev_warn(dev->ctrl.device,
1832 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1833 csts, result);
1834
1835 if (csts != ~0)
1836 return;
1837
1838 dev_warn(dev->ctrl.device,
1839 "Does your device have a faulty power saving mode enabled?\n");
1840 dev_warn(dev->ctrl.device,
1841 "Try \"nvme_core.default_ps_max_latency_us=0 pcie_aspm=off pcie_port_pm=off\" and report a bug\n");
1842}
1843
1844static enum blk_eh_timer_return nvme_timeout(struct request *req)
1845{
1846 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1847 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1848 struct nvme_dev *dev = nvmeq->dev;
1849 struct request *abort_req;
1850 struct nvme_command cmd = { };
1851 struct pci_dev *pdev = to_pci_dev(dev->dev);
1852 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1853 u8 opcode;
1854
1855 /*
1856 * Shutdown the device immediately if we see it is disconnected. This
1857 * unblocks PCIe error handling if the nvme driver is waiting in
1858 * error_resume for a device that has been removed. We can't unbind the
1859 * driver while the driver's error callback is waiting to complete, so
1860 * we're relying on a timeout to break that deadlock if a removal
1861 * occurs while reset work is running.
1862 */
1863 if (pci_dev_is_disconnected(pdev))
1864 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1865 if (nvme_state_terminal(&dev->ctrl))
1866 goto disable;
1867
1868 /* If PCI error recovery process is happening, we cannot reset or
1869 * the recovery mechanism will surely fail.
1870 */
1871 mb();
1872 if (pci_channel_offline(pdev))
1873 return BLK_EH_RESET_TIMER;
1874
1875 /*
1876 * Reset immediately if the controller is failed
1877 */
1878 if (nvme_should_reset(dev, csts)) {
1879 nvme_warn_reset(dev, csts);
1880 goto disable;
1881 }
1882
1883 /*
1884 * Did we miss an interrupt?
1885 */
1886 if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1887 nvme_poll(req->mq_hctx, NULL);
1888 else
1889 nvme_poll_irqdisable(nvmeq);
1890
1891 if (blk_mq_rq_state(req) != MQ_RQ_IN_FLIGHT) {
1892 dev_warn(dev->ctrl.device,
1893 "I/O tag %d (%04x) QID %d timeout, completion polled\n",
1894 req->tag, nvme_cid(req), nvmeq->qid);
1895 return BLK_EH_DONE;
1896 }
1897
1898 /*
1899 * Shutdown immediately if controller times out while starting. The
1900 * reset work will see the pci device disabled when it gets the forced
1901 * cancellation error. All outstanding requests are completed on
1902 * shutdown, so we return BLK_EH_DONE.
1903 */
1904 switch (nvme_ctrl_state(&dev->ctrl)) {
1905 case NVME_CTRL_CONNECTING:
1906 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1907 fallthrough;
1908 case NVME_CTRL_DELETING:
1909 dev_warn_ratelimited(dev->ctrl.device,
1910 "I/O tag %d (%04x) QID %d timeout, disable controller\n",
1911 req->tag, nvme_cid(req), nvmeq->qid);
1912 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1913 nvme_dev_disable(dev, true);
1914 return BLK_EH_DONE;
1915 case NVME_CTRL_RESETTING:
1916 return BLK_EH_RESET_TIMER;
1917 default:
1918 break;
1919 }
1920
1921 /*
1922 * Shutdown the controller immediately and schedule a reset if the
1923 * command was already aborted once before and still hasn't been
1924 * returned to the driver, or if this is the admin queue.
1925 */
1926 opcode = nvme_req(req)->cmd->common.opcode;
1927 if (!nvmeq->qid || (iod->flags & IOD_ABORTED)) {
1928 dev_warn(dev->ctrl.device,
1929 "I/O tag %d (%04x) opcode %#x (%s) QID %d timeout, reset controller\n",
1930 req->tag, nvme_cid(req), opcode,
1931 nvme_opcode_str(nvmeq->qid, opcode), nvmeq->qid);
1932 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1933 goto disable;
1934 }
1935
1936 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1937 atomic_inc(&dev->ctrl.abort_limit);
1938 return BLK_EH_RESET_TIMER;
1939 }
1940 iod->flags |= IOD_ABORTED;
1941
1942 cmd.abort.opcode = nvme_admin_abort_cmd;
1943 cmd.abort.cid = nvme_cid(req);
1944 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1945
1946 dev_warn(nvmeq->dev->ctrl.device,
1947 "I/O tag %d (%04x) opcode %#x (%s) QID %d timeout, aborting req_op:%s(%u) size:%u\n",
1948 req->tag, nvme_cid(req), opcode, nvme_get_opcode_str(opcode),
1949 nvmeq->qid, blk_op_str(req_op(req)), req_op(req),
1950 blk_rq_bytes(req));
1951
1952 abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd),
1953 BLK_MQ_REQ_NOWAIT);
1954 if (IS_ERR(abort_req)) {
1955 atomic_inc(&dev->ctrl.abort_limit);
1956 return BLK_EH_RESET_TIMER;
1957 }
1958 nvme_init_request(abort_req, &cmd);
1959
1960 abort_req->end_io = abort_endio;
1961 abort_req->end_io_data = NULL;
1962 blk_execute_rq_nowait(abort_req, false);
1963
1964 /*
1965 * The aborted req will be completed on receiving the abort req.
1966 * We enable the timer again. If hit twice, it'll cause a device reset,
1967 * as the device then is in a faulty state.
1968 */
1969 return BLK_EH_RESET_TIMER;
1970
1971disable:
1972 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING)) {
1973 if (nvme_state_terminal(&dev->ctrl))
1974 nvme_dev_disable(dev, true);
1975 return BLK_EH_DONE;
1976 }
1977
1978 nvme_dev_disable(dev, false);
1979 if (nvme_try_sched_reset(&dev->ctrl))
1980 nvme_unquiesce_io_queues(&dev->ctrl);
1981 return BLK_EH_DONE;
1982}
1983
1984static void nvme_free_queue(struct nvme_queue *nvmeq)
1985{
1986 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
1987 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1988 if (!nvmeq->sq_cmds)
1989 return;
1990
1991 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1992 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
1993 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1994 } else {
1995 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
1996 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1997 }
1998}
1999
2000static void nvme_free_queues(struct nvme_dev *dev, int lowest)
2001{
2002 int i;
2003
2004 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
2005 dev->ctrl.queue_count--;
2006 nvme_free_queue(&dev->queues[i]);
2007 }
2008}
2009
2010static void nvme_suspend_queue(struct nvme_dev *dev, unsigned int qid)
2011{
2012 struct nvme_queue *nvmeq = &dev->queues[qid];
2013
2014 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
2015 return;
2016
2017 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
2018 mb();
2019
2020 nvmeq->dev->online_queues--;
2021 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
2022 nvme_quiesce_admin_queue(&nvmeq->dev->ctrl);
2023 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
2024 pci_free_irq(to_pci_dev(dev->dev), nvmeq->cq_vector, nvmeq);
2025}
2026
2027static void nvme_suspend_io_queues(struct nvme_dev *dev)
2028{
2029 int i;
2030
2031 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
2032 nvme_suspend_queue(dev, i);
2033}
2034
2035/*
2036 * Called only on a device that has been disabled and after all other threads
2037 * that can check this device's completion queues have synced, except
2038 * nvme_poll(). This is the last chance for the driver to see a natural
2039 * completion before nvme_cancel_request() terminates all incomplete requests.
2040 */
2041static void nvme_reap_pending_cqes(struct nvme_dev *dev)
2042{
2043 int i;
2044
2045 for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
2046 spin_lock(&dev->queues[i].cq_poll_lock);
2047 nvme_poll_cq(&dev->queues[i], NULL);
2048 spin_unlock(&dev->queues[i].cq_poll_lock);
2049 }
2050}
2051
2052static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
2053 int entry_size)
2054{
2055 int q_depth = dev->q_depth;
2056 unsigned q_size_aligned = roundup(q_depth * entry_size,
2057 NVME_CTRL_PAGE_SIZE);
2058
2059 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
2060 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
2061
2062 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
2063 q_depth = div_u64(mem_per_q, entry_size);
2064
2065 /*
2066 * Ensure the reduced q_depth is above some threshold where it
2067 * would be better to map queues in system memory with the
2068 * original depth
2069 */
2070 if (q_depth < 64)
2071 return -ENOMEM;
2072 }
2073
2074 return q_depth;
2075}
2076
2077static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
2078 int qid)
2079{
2080 struct pci_dev *pdev = to_pci_dev(dev->dev);
2081
2082 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
2083 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
2084 if (nvmeq->sq_cmds) {
2085 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
2086 nvmeq->sq_cmds);
2087 if (nvmeq->sq_dma_addr) {
2088 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
2089 return 0;
2090 }
2091
2092 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
2093 }
2094 }
2095
2096 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
2097 &nvmeq->sq_dma_addr, GFP_KERNEL);
2098 if (!nvmeq->sq_cmds)
2099 return -ENOMEM;
2100 return 0;
2101}
2102
2103static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
2104{
2105 struct nvme_queue *nvmeq = &dev->queues[qid];
2106
2107 if (dev->ctrl.queue_count > qid)
2108 return 0;
2109
2110 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
2111 nvmeq->q_depth = depth;
2112 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
2113 &nvmeq->cq_dma_addr, GFP_KERNEL);
2114 if (!nvmeq->cqes)
2115 goto free_nvmeq;
2116
2117 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
2118 goto free_cqdma;
2119
2120 nvmeq->dev = dev;
2121 spin_lock_init(&nvmeq->sq_lock);
2122 spin_lock_init(&nvmeq->cq_poll_lock);
2123 nvmeq->cq_head = 0;
2124 nvmeq->cq_phase = 1;
2125 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
2126 nvmeq->qid = qid;
2127 dev->ctrl.queue_count++;
2128
2129 return 0;
2130
2131 free_cqdma:
2132 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
2133 nvmeq->cq_dma_addr);
2134 free_nvmeq:
2135 return -ENOMEM;
2136}
2137
2138static int queue_request_irq(struct nvme_queue *nvmeq)
2139{
2140 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
2141 int nr = nvmeq->dev->ctrl.instance;
2142
2143 if (use_threaded_interrupts) {
2144 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
2145 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
2146 } else {
2147 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
2148 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
2149 }
2150}
2151
2152static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
2153{
2154 struct nvme_dev *dev = nvmeq->dev;
2155
2156 nvmeq->sq_tail = 0;
2157 nvmeq->last_sq_tail = 0;
2158 nvmeq->cq_head = 0;
2159 nvmeq->cq_phase = 1;
2160 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
2161 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
2162 nvme_dbbuf_init(dev, nvmeq, qid);
2163 dev->online_queues++;
2164 wmb(); /* ensure the first interrupt sees the initialization */
2165}
2166
2167/*
2168 * Try getting shutdown_lock while setting up IO queues.
2169 */
2170static int nvme_setup_io_queues_trylock(struct nvme_dev *dev)
2171{
2172 /*
2173 * Give up if the lock is being held by nvme_dev_disable.
2174 */
2175 if (!mutex_trylock(&dev->shutdown_lock))
2176 return -ENODEV;
2177
2178 /*
2179 * Controller is in wrong state, fail early.
2180 */
2181 if (nvme_ctrl_state(&dev->ctrl) != NVME_CTRL_CONNECTING) {
2182 mutex_unlock(&dev->shutdown_lock);
2183 return -ENODEV;
2184 }
2185
2186 return 0;
2187}
2188
2189static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
2190{
2191 struct nvme_dev *dev = nvmeq->dev;
2192 int result;
2193 u16 vector = 0;
2194
2195 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
2196
2197 /*
2198 * A queue's vector matches the queue identifier unless the controller
2199 * has only one vector available.
2200 */
2201 if (!polled)
2202 vector = dev->num_vecs == 1 ? 0 : qid;
2203 else
2204 set_bit(NVMEQ_POLLED, &nvmeq->flags);
2205
2206 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
2207 if (result)
2208 return result;
2209
2210 result = adapter_alloc_sq(dev, qid, nvmeq);
2211 if (result < 0)
2212 return result;
2213 if (result)
2214 goto release_cq;
2215
2216 nvmeq->cq_vector = vector;
2217
2218 result = nvme_setup_io_queues_trylock(dev);
2219 if (result)
2220 return result;
2221 nvme_init_queue(nvmeq, qid);
2222 if (!polled) {
2223 result = queue_request_irq(nvmeq);
2224 if (result < 0)
2225 goto release_sq;
2226 }
2227
2228 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
2229 mutex_unlock(&dev->shutdown_lock);
2230 return result;
2231
2232release_sq:
2233 dev->online_queues--;
2234 mutex_unlock(&dev->shutdown_lock);
2235 adapter_delete_sq(dev, qid);
2236release_cq:
2237 adapter_delete_cq(dev, qid);
2238 return result;
2239}
2240
2241static const struct blk_mq_ops nvme_mq_admin_ops = {
2242 .queue_rq = nvme_queue_rq,
2243 .complete = nvme_pci_complete_rq,
2244 .commit_rqs = nvme_commit_rqs,
2245 .init_hctx = nvme_admin_init_hctx,
2246 .init_request = nvme_pci_init_request,
2247 .timeout = nvme_timeout,
2248};
2249
2250static const struct blk_mq_ops nvme_mq_ops = {
2251 .queue_rq = nvme_queue_rq,
2252 .queue_rqs = nvme_queue_rqs,
2253 .complete = nvme_pci_complete_rq,
2254 .commit_rqs = nvme_commit_rqs,
2255 .init_hctx = nvme_init_hctx,
2256 .init_request = nvme_pci_init_request,
2257 .map_queues = nvme_pci_map_queues,
2258 .timeout = nvme_timeout,
2259 .poll = nvme_poll,
2260};
2261
2262static void nvme_dev_remove_admin(struct nvme_dev *dev)
2263{
2264 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
2265 /*
2266 * If the controller was reset during removal, it's possible
2267 * user requests may be waiting on a stopped queue. Start the
2268 * queue to flush these to completion.
2269 */
2270 nvme_unquiesce_admin_queue(&dev->ctrl);
2271 nvme_remove_admin_tag_set(&dev->ctrl);
2272 }
2273}
2274
2275static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
2276{
2277 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
2278}
2279
2280static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
2281{
2282 struct pci_dev *pdev = to_pci_dev(dev->dev);
2283
2284 if (size <= dev->bar_mapped_size)
2285 return 0;
2286 if (size > pci_resource_len(pdev, 0))
2287 return -ENOMEM;
2288 if (dev->bar)
2289 iounmap(dev->bar);
2290 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
2291 if (!dev->bar) {
2292 dev->bar_mapped_size = 0;
2293 return -ENOMEM;
2294 }
2295 dev->bar_mapped_size = size;
2296 dev->dbs = dev->bar + NVME_REG_DBS;
2297
2298 return 0;
2299}
2300
2301static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
2302{
2303 int result;
2304 u32 aqa;
2305 struct nvme_queue *nvmeq;
2306
2307 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
2308 if (result < 0)
2309 return result;
2310
2311 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
2312 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
2313
2314 if (dev->subsystem &&
2315 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
2316 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
2317
2318 /*
2319 * If the device has been passed off to us in an enabled state, just
2320 * clear the enabled bit. The spec says we should set the 'shutdown
2321 * notification bits', but doing so may cause the device to complete
2322 * commands to the admin queue ... and we don't know what memory that
2323 * might be pointing at!
2324 */
2325 result = nvme_disable_ctrl(&dev->ctrl, false);
2326 if (result < 0) {
2327 struct pci_dev *pdev = to_pci_dev(dev->dev);
2328
2329 /*
2330 * The NVMe Controller Reset method did not get an expected
2331 * CSTS.RDY transition, so something with the device appears to
2332 * be stuck. Use the lower level and bigger hammer PCIe
2333 * Function Level Reset to attempt restoring the device to its
2334 * initial state, and try again.
2335 */
2336 result = pcie_reset_flr(pdev, false);
2337 if (result < 0)
2338 return result;
2339
2340 pci_restore_state(pdev);
2341 result = nvme_disable_ctrl(&dev->ctrl, false);
2342 if (result < 0)
2343 return result;
2344
2345 dev_info(dev->ctrl.device,
2346 "controller reset completed after pcie flr\n");
2347 }
2348
2349 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
2350 if (result)
2351 return result;
2352
2353 dev->ctrl.numa_node = dev_to_node(dev->dev);
2354
2355 nvmeq = &dev->queues[0];
2356 aqa = nvmeq->q_depth - 1;
2357 aqa |= aqa << 16;
2358
2359 writel(aqa, dev->bar + NVME_REG_AQA);
2360 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
2361 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
2362
2363 result = nvme_enable_ctrl(&dev->ctrl);
2364 if (result)
2365 return result;
2366
2367 nvmeq->cq_vector = 0;
2368 nvme_init_queue(nvmeq, 0);
2369 result = queue_request_irq(nvmeq);
2370 if (result) {
2371 dev->online_queues--;
2372 return result;
2373 }
2374
2375 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
2376 return result;
2377}
2378
2379static int nvme_create_io_queues(struct nvme_dev *dev)
2380{
2381 unsigned i, max, rw_queues;
2382 int ret = 0;
2383
2384 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
2385 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
2386 ret = -ENOMEM;
2387 break;
2388 }
2389 }
2390
2391 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
2392 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
2393 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
2394 dev->io_queues[HCTX_TYPE_READ];
2395 } else {
2396 rw_queues = max;
2397 }
2398
2399 for (i = dev->online_queues; i <= max; i++) {
2400 bool polled = i > rw_queues;
2401
2402 ret = nvme_create_queue(&dev->queues[i], i, polled);
2403 if (ret)
2404 break;
2405 }
2406
2407 /*
2408 * Ignore failing Create SQ/CQ commands, we can continue with less
2409 * than the desired amount of queues, and even a controller without
2410 * I/O queues can still be used to issue admin commands. This might
2411 * be useful to upgrade a buggy firmware for example.
2412 */
2413 return ret >= 0 ? 0 : ret;
2414}
2415
2416static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
2417{
2418 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
2419
2420 return 1ULL << (12 + 4 * szu);
2421}
2422
2423static u32 nvme_cmb_size(struct nvme_dev *dev)
2424{
2425 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
2426}
2427
2428static void nvme_map_cmb(struct nvme_dev *dev)
2429{
2430 u64 size, offset;
2431 resource_size_t bar_size;
2432 struct pci_dev *pdev = to_pci_dev(dev->dev);
2433 int bar;
2434
2435 if (dev->cmb_size)
2436 return;
2437
2438 if (NVME_CAP_CMBS(dev->ctrl.cap))
2439 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
2440
2441 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
2442 if (!dev->cmbsz)
2443 return;
2444 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
2445
2446 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
2447 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
2448 bar = NVME_CMB_BIR(dev->cmbloc);
2449 bar_size = pci_resource_len(pdev, bar);
2450
2451 if (offset > bar_size)
2452 return;
2453
2454 /*
2455 * Controllers may support a CMB size larger than their BAR, for
2456 * example, due to being behind a bridge. Reduce the CMB to the
2457 * reported size of the BAR
2458 */
2459 size = min(size, bar_size - offset);
2460
2461 if (!IS_ALIGNED(size, memremap_compat_align()) ||
2462 !IS_ALIGNED(pci_resource_start(pdev, bar),
2463 memremap_compat_align()))
2464 return;
2465
2466 /*
2467 * Tell the controller about the host side address mapping the CMB,
2468 * and enable CMB decoding for the NVMe 1.4+ scheme:
2469 */
2470 if (NVME_CAP_CMBS(dev->ctrl.cap)) {
2471 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
2472 (pci_bus_address(pdev, bar) + offset),
2473 dev->bar + NVME_REG_CMBMSC);
2474 }
2475
2476 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
2477 dev_warn(dev->ctrl.device,
2478 "failed to register the CMB\n");
2479 hi_lo_writeq(0, dev->bar + NVME_REG_CMBMSC);
2480 return;
2481 }
2482
2483 dev->cmb_size = size;
2484 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
2485
2486 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
2487 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
2488 pci_p2pmem_publish(pdev, true);
2489}
2490
2491static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
2492{
2493 u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
2494 u64 dma_addr = dev->host_mem_descs_dma;
2495 struct nvme_command c = { };
2496 int ret;
2497
2498 c.features.opcode = nvme_admin_set_features;
2499 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
2500 c.features.dword11 = cpu_to_le32(bits);
2501 c.features.dword12 = cpu_to_le32(host_mem_size);
2502 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
2503 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
2504 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
2505
2506 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
2507 if (ret) {
2508 dev_warn(dev->ctrl.device,
2509 "failed to set host mem (err %d, flags %#x).\n",
2510 ret, bits);
2511 } else
2512 dev->hmb = bits & NVME_HOST_MEM_ENABLE;
2513
2514 return ret;
2515}
2516
2517static void nvme_free_host_mem_multi(struct nvme_dev *dev)
2518{
2519 int i;
2520
2521 for (i = 0; i < dev->nr_host_mem_descs; i++) {
2522 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
2523 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
2524
2525 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
2526 le64_to_cpu(desc->addr),
2527 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
2528 }
2529
2530 kfree(dev->host_mem_desc_bufs);
2531 dev->host_mem_desc_bufs = NULL;
2532}
2533
2534static void nvme_free_host_mem(struct nvme_dev *dev)
2535{
2536 if (dev->hmb_sgt)
2537 dma_free_noncontiguous(dev->dev, dev->host_mem_size,
2538 dev->hmb_sgt, DMA_BIDIRECTIONAL);
2539 else
2540 nvme_free_host_mem_multi(dev);
2541
2542 dma_free_coherent(dev->dev, dev->host_mem_descs_size,
2543 dev->host_mem_descs, dev->host_mem_descs_dma);
2544 dev->host_mem_descs = NULL;
2545 dev->host_mem_descs_size = 0;
2546 dev->nr_host_mem_descs = 0;
2547}
2548
2549static int nvme_alloc_host_mem_single(struct nvme_dev *dev, u64 size)
2550{
2551 dev->hmb_sgt = dma_alloc_noncontiguous(dev->dev, size,
2552 DMA_BIDIRECTIONAL, GFP_KERNEL, 0);
2553 if (!dev->hmb_sgt)
2554 return -ENOMEM;
2555
2556 dev->host_mem_descs = dma_alloc_coherent(dev->dev,
2557 sizeof(*dev->host_mem_descs), &dev->host_mem_descs_dma,
2558 GFP_KERNEL);
2559 if (!dev->host_mem_descs) {
2560 dma_free_noncontiguous(dev->dev, size, dev->hmb_sgt,
2561 DMA_BIDIRECTIONAL);
2562 dev->hmb_sgt = NULL;
2563 return -ENOMEM;
2564 }
2565 dev->host_mem_size = size;
2566 dev->host_mem_descs_size = sizeof(*dev->host_mem_descs);
2567 dev->nr_host_mem_descs = 1;
2568
2569 dev->host_mem_descs[0].addr =
2570 cpu_to_le64(dev->hmb_sgt->sgl->dma_address);
2571 dev->host_mem_descs[0].size = cpu_to_le32(size / NVME_CTRL_PAGE_SIZE);
2572 return 0;
2573}
2574
2575static int nvme_alloc_host_mem_multi(struct nvme_dev *dev, u64 preferred,
2576 u32 chunk_size)
2577{
2578 struct nvme_host_mem_buf_desc *descs;
2579 u32 max_entries, len, descs_size;
2580 dma_addr_t descs_dma;
2581 int i = 0;
2582 void **bufs;
2583 u64 size, tmp;
2584
2585 tmp = (preferred + chunk_size - 1);
2586 do_div(tmp, chunk_size);
2587 max_entries = tmp;
2588
2589 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
2590 max_entries = dev->ctrl.hmmaxd;
2591
2592 descs_size = max_entries * sizeof(*descs);
2593 descs = dma_alloc_coherent(dev->dev, descs_size, &descs_dma,
2594 GFP_KERNEL);
2595 if (!descs)
2596 goto out;
2597
2598 bufs = kzalloc_objs(*bufs, max_entries);
2599 if (!bufs)
2600 goto out_free_descs;
2601
2602 for (size = 0; size < preferred && i < max_entries; size += len) {
2603 dma_addr_t dma_addr;
2604
2605 len = min_t(u64, chunk_size, preferred - size);
2606 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
2607 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
2608 if (!bufs[i])
2609 break;
2610
2611 descs[i].addr = cpu_to_le64(dma_addr);
2612 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
2613 i++;
2614 }
2615
2616 if (!size)
2617 goto out_free_bufs;
2618
2619 dev->nr_host_mem_descs = i;
2620 dev->host_mem_size = size;
2621 dev->host_mem_descs = descs;
2622 dev->host_mem_descs_dma = descs_dma;
2623 dev->host_mem_descs_size = descs_size;
2624 dev->host_mem_desc_bufs = bufs;
2625 return 0;
2626
2627out_free_bufs:
2628 kfree(bufs);
2629out_free_descs:
2630 dma_free_coherent(dev->dev, descs_size, descs, descs_dma);
2631out:
2632 dev->host_mem_descs = NULL;
2633 return -ENOMEM;
2634}
2635
2636static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
2637{
2638 unsigned long dma_merge_boundary = dma_get_merge_boundary(dev->dev);
2639 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
2640 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2641 u64 chunk_size;
2642
2643 /*
2644 * If there is an IOMMU that can merge pages, try a virtually
2645 * non-contiguous allocation for a single segment first.
2646 */
2647 if (dma_merge_boundary && (PAGE_SIZE & dma_merge_boundary) == 0) {
2648 if (!nvme_alloc_host_mem_single(dev, preferred))
2649 return 0;
2650 }
2651
2652 /* start big and work our way down */
2653 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
2654 if (!nvme_alloc_host_mem_multi(dev, preferred, chunk_size)) {
2655 if (!min || dev->host_mem_size >= min)
2656 return 0;
2657 nvme_free_host_mem(dev);
2658 }
2659 }
2660
2661 return -ENOMEM;
2662}
2663
2664static int nvme_setup_host_mem(struct nvme_dev *dev)
2665{
2666 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2667 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2668 u64 min = (u64)dev->ctrl.hmmin * 4096;
2669 u32 enable_bits = NVME_HOST_MEM_ENABLE;
2670 int ret;
2671
2672 if (!dev->ctrl.hmpre)
2673 return 0;
2674
2675 preferred = min(preferred, max);
2676 if (min > max) {
2677 dev_warn(dev->ctrl.device,
2678 "min host memory (%lld MiB) above limit (%d MiB).\n",
2679 min >> ilog2(SZ_1M), max_host_mem_size_mb);
2680 nvme_free_host_mem(dev);
2681 return 0;
2682 }
2683
2684 /*
2685 * If we already have a buffer allocated check if we can reuse it.
2686 */
2687 if (dev->host_mem_descs) {
2688 if (dev->host_mem_size >= min)
2689 enable_bits |= NVME_HOST_MEM_RETURN;
2690 else
2691 nvme_free_host_mem(dev);
2692 }
2693
2694 if (!dev->host_mem_descs) {
2695 if (nvme_alloc_host_mem(dev, min, preferred)) {
2696 dev_warn(dev->ctrl.device,
2697 "failed to allocate host memory buffer.\n");
2698 return 0; /* controller must work without HMB */
2699 }
2700
2701 dev_info(dev->ctrl.device,
2702 "allocated %lld MiB host memory buffer (%u segment%s).\n",
2703 dev->host_mem_size >> ilog2(SZ_1M),
2704 dev->nr_host_mem_descs,
2705 str_plural(dev->nr_host_mem_descs));
2706 }
2707
2708 ret = nvme_set_host_mem(dev, enable_bits);
2709 if (ret)
2710 nvme_free_host_mem(dev);
2711 return ret;
2712}
2713
2714static ssize_t cmb_show(struct device *dev, struct device_attribute *attr,
2715 char *buf)
2716{
2717 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2718
2719 return sysfs_emit(buf, "cmbloc : 0x%08x\ncmbsz : 0x%08x\n",
2720 ndev->cmbloc, ndev->cmbsz);
2721}
2722static DEVICE_ATTR_RO(cmb);
2723
2724static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr,
2725 char *buf)
2726{
2727 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2728
2729 return sysfs_emit(buf, "%u\n", ndev->cmbloc);
2730}
2731static DEVICE_ATTR_RO(cmbloc);
2732
2733static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr,
2734 char *buf)
2735{
2736 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2737
2738 return sysfs_emit(buf, "%u\n", ndev->cmbsz);
2739}
2740static DEVICE_ATTR_RO(cmbsz);
2741
2742static ssize_t hmb_show(struct device *dev, struct device_attribute *attr,
2743 char *buf)
2744{
2745 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2746
2747 return sysfs_emit(buf, "%d\n", ndev->hmb);
2748}
2749
2750static ssize_t hmb_store(struct device *dev, struct device_attribute *attr,
2751 const char *buf, size_t count)
2752{
2753 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2754 bool new;
2755 int ret;
2756
2757 if (kstrtobool(buf, &new) < 0)
2758 return -EINVAL;
2759
2760 if (new == ndev->hmb)
2761 return count;
2762
2763 if (new) {
2764 ret = nvme_setup_host_mem(ndev);
2765 } else {
2766 ret = nvme_set_host_mem(ndev, 0);
2767 if (!ret)
2768 nvme_free_host_mem(ndev);
2769 }
2770
2771 if (ret < 0)
2772 return ret;
2773
2774 return count;
2775}
2776static DEVICE_ATTR_RW(hmb);
2777
2778static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj,
2779 struct attribute *a, int n)
2780{
2781 struct nvme_ctrl *ctrl =
2782 dev_get_drvdata(container_of(kobj, struct device, kobj));
2783 struct nvme_dev *dev = to_nvme_dev(ctrl);
2784
2785 if (a == &dev_attr_cmb.attr ||
2786 a == &dev_attr_cmbloc.attr ||
2787 a == &dev_attr_cmbsz.attr) {
2788 if (!dev->cmbsz)
2789 return 0;
2790 }
2791 if (a == &dev_attr_hmb.attr && !ctrl->hmpre)
2792 return 0;
2793
2794 return a->mode;
2795}
2796
2797static struct attribute *nvme_pci_attrs[] = {
2798 &dev_attr_cmb.attr,
2799 &dev_attr_cmbloc.attr,
2800 &dev_attr_cmbsz.attr,
2801 &dev_attr_hmb.attr,
2802 NULL,
2803};
2804
2805static const struct attribute_group nvme_pci_dev_attrs_group = {
2806 .attrs = nvme_pci_attrs,
2807 .is_visible = nvme_pci_attrs_are_visible,
2808};
2809
2810static const struct attribute_group *nvme_pci_dev_attr_groups[] = {
2811 &nvme_dev_attrs_group,
2812 &nvme_pci_dev_attrs_group,
2813 NULL,
2814};
2815
2816static void nvme_update_attrs(struct nvme_dev *dev)
2817{
2818 sysfs_update_group(&dev->ctrl.device->kobj, &nvme_pci_dev_attrs_group);
2819}
2820
2821/*
2822 * nirqs is the number of interrupts available for write and read
2823 * queues. The core already reserved an interrupt for the admin queue.
2824 */
2825static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
2826{
2827 struct nvme_dev *dev = affd->priv;
2828 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
2829
2830 /*
2831 * If there is no interrupt available for queues, ensure that
2832 * the default queue is set to 1. The affinity set size is
2833 * also set to one, but the irq core ignores it for this case.
2834 *
2835 * If only one interrupt is available or 'write_queue' == 0, combine
2836 * write and read queues.
2837 *
2838 * If 'write_queues' > 0, ensure it leaves room for at least one read
2839 * queue.
2840 */
2841 if (!nrirqs) {
2842 nrirqs = 1;
2843 nr_read_queues = 0;
2844 } else if (nrirqs == 1 || !nr_write_queues) {
2845 nr_read_queues = 0;
2846 } else if (nr_write_queues >= nrirqs) {
2847 nr_read_queues = 1;
2848 } else {
2849 nr_read_queues = nrirqs - nr_write_queues;
2850 }
2851
2852 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2853 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2854 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2855 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2856 affd->nr_sets = nr_read_queues ? 2 : 1;
2857}
2858
2859static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
2860{
2861 struct pci_dev *pdev = to_pci_dev(dev->dev);
2862 struct irq_affinity affd = {
2863 .pre_vectors = 1,
2864 .calc_sets = nvme_calc_irq_sets,
2865 .priv = dev,
2866 };
2867 unsigned int irq_queues, poll_queues;
2868 unsigned int flags = PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY;
2869
2870 /*
2871 * Poll queues don't need interrupts, but we need at least one I/O queue
2872 * left over for non-polled I/O.
2873 */
2874 poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2875 dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
2876
2877 /*
2878 * Initialize for the single interrupt case, will be updated in
2879 * nvme_calc_irq_sets().
2880 */
2881 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2882 dev->io_queues[HCTX_TYPE_READ] = 0;
2883
2884 /*
2885 * We need interrupts for the admin queue and each non-polled I/O queue,
2886 * but some Apple controllers require all queues to use the first
2887 * vector.
2888 */
2889 irq_queues = 1;
2890 if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2891 irq_queues += (nr_io_queues - poll_queues);
2892 if (dev->ctrl.quirks & NVME_QUIRK_BROKEN_MSI)
2893 flags &= ~PCI_IRQ_MSI;
2894 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, flags,
2895 &affd);
2896}
2897
2898static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2899{
2900 /*
2901 * If tags are shared with admin queue (Apple bug), then
2902 * make sure we only use one IO queue.
2903 */
2904 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2905 return 1;
2906 return blk_mq_num_possible_queues(0) + dev->nr_write_queues +
2907 dev->nr_poll_queues;
2908}
2909
2910static int nvme_setup_io_queues(struct nvme_dev *dev)
2911{
2912 struct nvme_queue *adminq = &dev->queues[0];
2913 struct pci_dev *pdev = to_pci_dev(dev->dev);
2914 unsigned int nr_io_queues;
2915 unsigned long size;
2916 int result;
2917
2918 /*
2919 * Sample the module parameters once at reset time so that we have
2920 * stable values to work with.
2921 */
2922 dev->nr_write_queues = write_queues;
2923 dev->nr_poll_queues = poll_queues;
2924
2925 if (dev->ctrl.tagset) {
2926 /*
2927 * The set's maps are allocated only once at initialization
2928 * time. We can't add special queues later if their mq_map
2929 * wasn't preallocated.
2930 */
2931 if (dev->ctrl.tagset->nr_maps < 3)
2932 dev->nr_poll_queues = 0;
2933 if (dev->ctrl.tagset->nr_maps < 2)
2934 dev->nr_write_queues = 0;
2935 }
2936
2937 /*
2938 * The initial number of allocated queue slots may be too large if the
2939 * user reduced the special queue parameters. Cap the value to the
2940 * number we need for this round.
2941 */
2942 nr_io_queues = min(nvme_max_io_queues(dev),
2943 dev->nr_allocated_queues - 1);
2944 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2945 if (result < 0)
2946 return result;
2947
2948 if (nr_io_queues == 0)
2949 return 0;
2950
2951 /*
2952 * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions
2953 * from set to unset. If there is a window to it is truely freed,
2954 * pci_free_irq_vectors() jumping into this window will crash.
2955 * And take lock to avoid racing with pci_free_irq_vectors() in
2956 * nvme_dev_disable() path.
2957 */
2958 result = nvme_setup_io_queues_trylock(dev);
2959 if (result)
2960 return result;
2961 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2962 pci_free_irq(pdev, 0, adminq);
2963
2964 if (dev->cmb_use_sqes) {
2965 result = nvme_cmb_qdepth(dev, nr_io_queues,
2966 sizeof(struct nvme_command));
2967 if (result > 0) {
2968 dev->q_depth = result;
2969 dev->ctrl.sqsize = result - 1;
2970 } else {
2971 dev->cmb_use_sqes = false;
2972 }
2973 }
2974
2975 do {
2976 size = db_bar_size(dev, nr_io_queues);
2977 result = nvme_remap_bar(dev, size);
2978 if (!result)
2979 break;
2980 if (!--nr_io_queues) {
2981 result = -ENOMEM;
2982 goto out_unlock;
2983 }
2984 } while (1);
2985 adminq->q_db = dev->dbs;
2986
2987 retry:
2988 /* Deregister the admin queue's interrupt */
2989 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2990 pci_free_irq(pdev, 0, adminq);
2991
2992 /*
2993 * If we enable msix early due to not intx, disable it again before
2994 * setting up the full range we need.
2995 */
2996 pci_free_irq_vectors(pdev);
2997
2998 result = nvme_setup_irqs(dev, nr_io_queues);
2999 if (result <= 0) {
3000 result = -EIO;
3001 goto out_unlock;
3002 }
3003
3004 dev->num_vecs = result;
3005 result = max(result - 1, 1);
3006 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
3007
3008 /*
3009 * Should investigate if there's a performance win from allocating
3010 * more queues than interrupt vectors; it might allow the submission
3011 * path to scale better, even if the receive path is limited by the
3012 * number of interrupts.
3013 */
3014 result = queue_request_irq(adminq);
3015 if (result)
3016 goto out_unlock;
3017 set_bit(NVMEQ_ENABLED, &adminq->flags);
3018 mutex_unlock(&dev->shutdown_lock);
3019
3020 result = nvme_create_io_queues(dev);
3021 if (result || dev->online_queues < 2)
3022 return result;
3023
3024 if (dev->online_queues - 1 < dev->max_qid) {
3025 nr_io_queues = dev->online_queues - 1;
3026 nvme_delete_io_queues(dev);
3027 result = nvme_setup_io_queues_trylock(dev);
3028 if (result)
3029 return result;
3030 nvme_suspend_io_queues(dev);
3031 goto retry;
3032 }
3033 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
3034 dev->io_queues[HCTX_TYPE_DEFAULT],
3035 dev->io_queues[HCTX_TYPE_READ],
3036 dev->io_queues[HCTX_TYPE_POLL]);
3037 return 0;
3038out_unlock:
3039 mutex_unlock(&dev->shutdown_lock);
3040 return result;
3041}
3042
3043static enum rq_end_io_ret nvme_del_queue_end(struct request *req,
3044 blk_status_t error,
3045 const struct io_comp_batch *iob)
3046{
3047 struct nvme_queue *nvmeq = req->end_io_data;
3048
3049 blk_mq_free_request(req);
3050 complete(&nvmeq->delete_done);
3051 return RQ_END_IO_NONE;
3052}
3053
3054static enum rq_end_io_ret nvme_del_cq_end(struct request *req,
3055 blk_status_t error,
3056 const struct io_comp_batch *iob)
3057{
3058 struct nvme_queue *nvmeq = req->end_io_data;
3059
3060 if (error)
3061 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
3062
3063 return nvme_del_queue_end(req, error, iob);
3064}
3065
3066static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
3067{
3068 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
3069 struct request *req;
3070 struct nvme_command cmd = { };
3071
3072 cmd.delete_queue.opcode = opcode;
3073 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
3074
3075 req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT);
3076 if (IS_ERR(req))
3077 return PTR_ERR(req);
3078 nvme_init_request(req, &cmd);
3079
3080 if (opcode == nvme_admin_delete_cq)
3081 req->end_io = nvme_del_cq_end;
3082 else
3083 req->end_io = nvme_del_queue_end;
3084 req->end_io_data = nvmeq;
3085
3086 init_completion(&nvmeq->delete_done);
3087 blk_execute_rq_nowait(req, false);
3088 return 0;
3089}
3090
3091static bool __nvme_delete_io_queues(struct nvme_dev *dev, u8 opcode)
3092{
3093 int nr_queues = dev->online_queues - 1, sent = 0;
3094 unsigned long timeout;
3095
3096 retry:
3097 timeout = NVME_ADMIN_TIMEOUT;
3098 while (nr_queues > 0) {
3099 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
3100 break;
3101 nr_queues--;
3102 sent++;
3103 }
3104 while (sent) {
3105 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
3106
3107 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
3108 timeout);
3109 if (timeout == 0)
3110 return false;
3111
3112 sent--;
3113 if (nr_queues)
3114 goto retry;
3115 }
3116 return true;
3117}
3118
3119static void nvme_delete_io_queues(struct nvme_dev *dev)
3120{
3121 if (__nvme_delete_io_queues(dev, nvme_admin_delete_sq))
3122 __nvme_delete_io_queues(dev, nvme_admin_delete_cq);
3123}
3124
3125static unsigned int nvme_pci_nr_maps(struct nvme_dev *dev)
3126{
3127 if (dev->io_queues[HCTX_TYPE_POLL])
3128 return 3;
3129 if (dev->io_queues[HCTX_TYPE_READ])
3130 return 2;
3131 return 1;
3132}
3133
3134static bool nvme_pci_update_nr_queues(struct nvme_dev *dev)
3135{
3136 if (!dev->ctrl.tagset) {
3137 nvme_alloc_io_tag_set(&dev->ctrl, &dev->tagset, &nvme_mq_ops,
3138 nvme_pci_nr_maps(dev), sizeof(struct nvme_iod));
3139 return true;
3140 }
3141
3142 /* Give up if we are racing with nvme_dev_disable() */
3143 if (!mutex_trylock(&dev->shutdown_lock))
3144 return false;
3145
3146 /* Check if nvme_dev_disable() has been executed already */
3147 if (!dev->online_queues) {
3148 mutex_unlock(&dev->shutdown_lock);
3149 return false;
3150 }
3151
3152 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
3153 /* free previously allocated queues that are no longer usable */
3154 nvme_free_queues(dev, dev->online_queues);
3155 mutex_unlock(&dev->shutdown_lock);
3156 return true;
3157}
3158
3159static int nvme_pci_enable(struct nvme_dev *dev)
3160{
3161 int result = -ENOMEM;
3162 struct pci_dev *pdev = to_pci_dev(dev->dev);
3163 unsigned int flags = PCI_IRQ_ALL_TYPES;
3164
3165 if (pci_enable_device_mem(pdev))
3166 return result;
3167
3168 pci_set_master(pdev);
3169
3170 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
3171 dev_dbg(dev->ctrl.device, "reading CSTS register failed\n");
3172 result = -ENODEV;
3173 goto disable;
3174 }
3175
3176 /*
3177 * Some devices and/or platforms don't advertise or work with INTx
3178 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
3179 * adjust this later.
3180 */
3181 if (dev->ctrl.quirks & NVME_QUIRK_BROKEN_MSI)
3182 flags &= ~PCI_IRQ_MSI;
3183 result = pci_alloc_irq_vectors(pdev, 1, 1, flags);
3184 if (result < 0)
3185 goto disable;
3186
3187 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
3188
3189 dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
3190 io_queue_depth);
3191 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
3192 dev->dbs = dev->bar + 4096;
3193
3194 /*
3195 * Some Apple controllers require a non-standard SQE size.
3196 * Interestingly they also seem to ignore the CC:IOSQES register
3197 * so we don't bother updating it here.
3198 */
3199 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
3200 dev->io_sqes = 7;
3201 else
3202 dev->io_sqes = NVME_NVM_IOSQES;
3203
3204 if (dev->ctrl.quirks & NVME_QUIRK_QDEPTH_ONE) {
3205 dev->q_depth = 2;
3206 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
3207 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
3208 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
3209 dev->q_depth = 64;
3210 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
3211 "set queue depth=%u\n", dev->q_depth);
3212 }
3213
3214 /*
3215 * Controllers with the shared tags quirk need the IO queue to be
3216 * big enough so that we get 32 tags for the admin queue
3217 */
3218 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
3219 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
3220 dev->q_depth = NVME_AQ_DEPTH + 2;
3221 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
3222 dev->q_depth);
3223 }
3224 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
3225
3226 nvme_map_cmb(dev);
3227
3228 pci_save_state(pdev);
3229
3230 result = nvme_pci_configure_admin_queue(dev);
3231 if (result)
3232 goto free_irq;
3233 return result;
3234
3235 free_irq:
3236 pci_free_irq_vectors(pdev);
3237 disable:
3238 pci_disable_device(pdev);
3239 return result;
3240}
3241
3242static void nvme_dev_unmap(struct nvme_dev *dev)
3243{
3244 if (dev->bar)
3245 iounmap(dev->bar);
3246 pci_release_mem_regions(to_pci_dev(dev->dev));
3247}
3248
3249static bool nvme_pci_ctrl_is_dead(struct nvme_dev *dev)
3250{
3251 struct pci_dev *pdev = to_pci_dev(dev->dev);
3252 u32 csts;
3253
3254 if (!pci_is_enabled(pdev) || !pci_device_is_present(pdev))
3255 return true;
3256 if (pdev->error_state != pci_channel_io_normal)
3257 return true;
3258
3259 csts = readl(dev->bar + NVME_REG_CSTS);
3260 return (csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY);
3261}
3262
3263static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
3264{
3265 enum nvme_ctrl_state state = nvme_ctrl_state(&dev->ctrl);
3266 struct pci_dev *pdev = to_pci_dev(dev->dev);
3267 bool dead;
3268
3269 mutex_lock(&dev->shutdown_lock);
3270 dead = nvme_pci_ctrl_is_dead(dev);
3271 if (state == NVME_CTRL_LIVE || state == NVME_CTRL_RESETTING) {
3272 if (pci_is_enabled(pdev))
3273 nvme_start_freeze(&dev->ctrl);
3274 /*
3275 * Give the controller a chance to complete all entered requests
3276 * if doing a safe shutdown.
3277 */
3278 if (!dead && shutdown)
3279 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
3280 }
3281
3282 nvme_quiesce_io_queues(&dev->ctrl);
3283
3284 if (!dead && dev->ctrl.queue_count > 0) {
3285 nvme_delete_io_queues(dev);
3286 nvme_disable_ctrl(&dev->ctrl, shutdown);
3287 nvme_poll_irqdisable(&dev->queues[0]);
3288 }
3289 nvme_suspend_io_queues(dev);
3290 nvme_suspend_queue(dev, 0);
3291 pci_free_irq_vectors(pdev);
3292 if (pci_is_enabled(pdev))
3293 pci_disable_device(pdev);
3294 nvme_reap_pending_cqes(dev);
3295
3296 nvme_cancel_tagset(&dev->ctrl);
3297 nvme_cancel_admin_tagset(&dev->ctrl);
3298
3299 /*
3300 * The driver will not be starting up queues again if shutting down so
3301 * must flush all entered requests to their failed completion to avoid
3302 * deadlocking blk-mq hot-cpu notifier.
3303 */
3304 if (shutdown) {
3305 nvme_unquiesce_io_queues(&dev->ctrl);
3306 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
3307 nvme_unquiesce_admin_queue(&dev->ctrl);
3308 }
3309 mutex_unlock(&dev->shutdown_lock);
3310}
3311
3312static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
3313{
3314 if (!nvme_wait_reset(&dev->ctrl))
3315 return -EBUSY;
3316 nvme_dev_disable(dev, shutdown);
3317 return 0;
3318}
3319
3320static int nvme_pci_alloc_iod_mempool(struct nvme_dev *dev)
3321{
3322 size_t alloc_size = sizeof(struct nvme_dma_vec) * NVME_MAX_SEGS;
3323
3324 dev->dmavec_mempool = mempool_create_node(1,
3325 mempool_kmalloc, mempool_kfree,
3326 (void *)alloc_size, GFP_KERNEL,
3327 dev_to_node(dev->dev));
3328 if (!dev->dmavec_mempool)
3329 return -ENOMEM;
3330 return 0;
3331}
3332
3333static void nvme_free_tagset(struct nvme_dev *dev)
3334{
3335 if (dev->tagset.tags)
3336 nvme_remove_io_tag_set(&dev->ctrl);
3337 dev->ctrl.tagset = NULL;
3338}
3339
3340/* pairs with nvme_pci_alloc_dev */
3341static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
3342{
3343 struct nvme_dev *dev = to_nvme_dev(ctrl);
3344
3345 nvme_free_tagset(dev);
3346 put_device(dev->dev);
3347 kfree(dev->queues);
3348 kfree(dev);
3349}
3350
3351static void nvme_reset_work(struct work_struct *work)
3352{
3353 struct nvme_dev *dev =
3354 container_of(work, struct nvme_dev, ctrl.reset_work);
3355 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
3356 int result;
3357
3358 if (nvme_ctrl_state(&dev->ctrl) != NVME_CTRL_RESETTING) {
3359 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
3360 dev->ctrl.state);
3361 result = -ENODEV;
3362 goto out;
3363 }
3364
3365 /*
3366 * If we're called to reset a live controller first shut it down before
3367 * moving on.
3368 */
3369 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
3370 nvme_dev_disable(dev, false);
3371 nvme_sync_queues(&dev->ctrl);
3372
3373 mutex_lock(&dev->shutdown_lock);
3374 result = nvme_pci_enable(dev);
3375 if (result)
3376 goto out_unlock;
3377 nvme_unquiesce_admin_queue(&dev->ctrl);
3378 mutex_unlock(&dev->shutdown_lock);
3379
3380 /*
3381 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
3382 * initializing procedure here.
3383 */
3384 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
3385 dev_warn(dev->ctrl.device,
3386 "failed to mark controller CONNECTING\n");
3387 result = -EBUSY;
3388 goto out;
3389 }
3390
3391 result = nvme_init_ctrl_finish(&dev->ctrl, was_suspend);
3392 if (result)
3393 goto out;
3394
3395 if (nvme_ctrl_meta_sgl_supported(&dev->ctrl))
3396 dev->ctrl.max_integrity_segments = NVME_MAX_META_SEGS;
3397 else
3398 dev->ctrl.max_integrity_segments = 1;
3399
3400 nvme_dbbuf_dma_alloc(dev);
3401
3402 result = nvme_setup_host_mem(dev);
3403 if (result < 0)
3404 goto out;
3405
3406 nvme_update_attrs(dev);
3407
3408 result = nvme_setup_io_queues(dev);
3409 if (result)
3410 goto out;
3411
3412 /*
3413 * Freeze and update the number of I/O queues as those might have
3414 * changed. If there are no I/O queues left after this reset, keep the
3415 * controller around but remove all namespaces.
3416 */
3417 if (dev->online_queues > 1) {
3418 nvme_dbbuf_set(dev);
3419 nvme_unquiesce_io_queues(&dev->ctrl);
3420 nvme_wait_freeze(&dev->ctrl);
3421 if (!nvme_pci_update_nr_queues(dev))
3422 goto out;
3423 nvme_unfreeze(&dev->ctrl);
3424 } else {
3425 dev_warn(dev->ctrl.device, "IO queues lost\n");
3426 nvme_mark_namespaces_dead(&dev->ctrl);
3427 nvme_unquiesce_io_queues(&dev->ctrl);
3428 nvme_remove_namespaces(&dev->ctrl);
3429 nvme_free_tagset(dev);
3430 }
3431
3432 /*
3433 * If only admin queue live, keep it to do further investigation or
3434 * recovery.
3435 */
3436 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
3437 dev_warn(dev->ctrl.device,
3438 "failed to mark controller live state\n");
3439 result = -ENODEV;
3440 goto out;
3441 }
3442
3443 nvme_start_ctrl(&dev->ctrl);
3444 return;
3445
3446 out_unlock:
3447 mutex_unlock(&dev->shutdown_lock);
3448 out:
3449 /*
3450 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
3451 * may be holding this pci_dev's device lock.
3452 */
3453 dev_warn(dev->ctrl.device, "Disabling device after reset failure: %d\n",
3454 result);
3455 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
3456 nvme_dev_disable(dev, true);
3457 nvme_sync_queues(&dev->ctrl);
3458 nvme_mark_namespaces_dead(&dev->ctrl);
3459 nvme_unquiesce_io_queues(&dev->ctrl);
3460 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
3461}
3462
3463static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
3464{
3465 *val = readl(to_nvme_dev(ctrl)->bar + off);
3466 return 0;
3467}
3468
3469static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
3470{
3471 writel(val, to_nvme_dev(ctrl)->bar + off);
3472 return 0;
3473}
3474
3475static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
3476{
3477 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
3478 return 0;
3479}
3480
3481static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
3482{
3483 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
3484
3485 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
3486}
3487
3488static void nvme_pci_print_device_info(struct nvme_ctrl *ctrl)
3489{
3490 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
3491 struct nvme_subsystem *subsys = ctrl->subsys;
3492
3493 dev_err(ctrl->device,
3494 "VID:DID %04x:%04x model:%.*s firmware:%.*s\n",
3495 pdev->vendor, pdev->device,
3496 nvme_strlen(subsys->model, sizeof(subsys->model)),
3497 subsys->model, nvme_strlen(subsys->firmware_rev,
3498 sizeof(subsys->firmware_rev)),
3499 subsys->firmware_rev);
3500}
3501
3502static bool nvme_pci_supports_pci_p2pdma(struct nvme_ctrl *ctrl)
3503{
3504 struct nvme_dev *dev = to_nvme_dev(ctrl);
3505
3506 return dma_pci_p2pdma_supported(dev->dev);
3507}
3508
3509static unsigned long nvme_pci_get_virt_boundary(struct nvme_ctrl *ctrl,
3510 bool is_admin)
3511{
3512 if (!nvme_ctrl_sgl_supported(ctrl) || is_admin)
3513 return NVME_CTRL_PAGE_SIZE - 1;
3514 return 0;
3515}
3516
3517static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
3518 .name = "pcie",
3519 .module = THIS_MODULE,
3520 .flags = NVME_F_METADATA_SUPPORTED,
3521 .dev_attr_groups = nvme_pci_dev_attr_groups,
3522 .reg_read32 = nvme_pci_reg_read32,
3523 .reg_write32 = nvme_pci_reg_write32,
3524 .reg_read64 = nvme_pci_reg_read64,
3525 .free_ctrl = nvme_pci_free_ctrl,
3526 .submit_async_event = nvme_pci_submit_async_event,
3527 .subsystem_reset = nvme_pci_subsystem_reset,
3528 .get_address = nvme_pci_get_address,
3529 .print_device_info = nvme_pci_print_device_info,
3530 .supports_pci_p2pdma = nvme_pci_supports_pci_p2pdma,
3531 .get_virt_boundary = nvme_pci_get_virt_boundary,
3532};
3533
3534static int nvme_dev_map(struct nvme_dev *dev)
3535{
3536 struct pci_dev *pdev = to_pci_dev(dev->dev);
3537
3538 if (pci_request_mem_regions(pdev, "nvme"))
3539 return -ENODEV;
3540
3541 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
3542 goto release;
3543
3544 return 0;
3545 release:
3546 pci_release_mem_regions(pdev);
3547 return -ENODEV;
3548}
3549
3550static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
3551{
3552 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
3553 /*
3554 * Several Samsung devices seem to drop off the PCIe bus
3555 * randomly when APST is on and uses the deepest sleep state.
3556 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
3557 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
3558 * 950 PRO 256GB", but it seems to be restricted to two Dell
3559 * laptops.
3560 */
3561 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
3562 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
3563 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
3564 return NVME_QUIRK_NO_DEEPEST_PS;
3565 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
3566 /*
3567 * Samsung SSD 960 EVO drops off the PCIe bus after system
3568 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
3569 * within few minutes after bootup on a Coffee Lake board -
3570 * ASUS PRIME Z370-A
3571 */
3572 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
3573 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
3574 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
3575 return NVME_QUIRK_NO_APST;
3576 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
3577 pdev->device == 0xa808 || pdev->device == 0xa809)) ||
3578 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
3579 /*
3580 * Forcing to use host managed nvme power settings for
3581 * lowest idle power with quick resume latency on
3582 * Samsung and Toshiba SSDs based on suspend behavior
3583 * on Coffee Lake board for LENOVO C640
3584 */
3585 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
3586 dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
3587 return NVME_QUIRK_SIMPLE_SUSPEND;
3588 } else if (pdev->vendor == 0x2646 && (pdev->device == 0x2263 ||
3589 pdev->device == 0x500f)) {
3590 /*
3591 * Exclude some Kingston NV1 and A2000 devices from
3592 * NVME_QUIRK_SIMPLE_SUSPEND. Do a full suspend to save a
3593 * lot of energy with s2idle sleep on some TUXEDO platforms.
3594 */
3595 if (dmi_match(DMI_BOARD_NAME, "NS5X_NS7XAU") ||
3596 dmi_match(DMI_BOARD_NAME, "NS5x_7xAU") ||
3597 dmi_match(DMI_BOARD_NAME, "NS5x_7xPU") ||
3598 dmi_match(DMI_BOARD_NAME, "PH4PRX1_PH6PRX1"))
3599 return NVME_QUIRK_FORCE_NO_SIMPLE_SUSPEND;
3600 } else if (pdev->vendor == 0x144d && pdev->device == 0xa80d) {
3601 /*
3602 * Exclude Samsung 990 Evo from NVME_QUIRK_SIMPLE_SUSPEND
3603 * because of high power consumption (> 2 Watt) in s2idle
3604 * sleep. Only some boards with Intel CPU are affected.
3605 * (Note for testing: Samsung 990 Evo Plus has same PCI ID)
3606 */
3607 if (dmi_match(DMI_BOARD_NAME, "DN50Z-140HC-YD") ||
3608 dmi_match(DMI_BOARD_NAME, "GMxPXxx") ||
3609 dmi_match(DMI_BOARD_NAME, "GXxMRXx") ||
3610 dmi_match(DMI_BOARD_NAME, "NS5X_NS7XAU") ||
3611 dmi_match(DMI_BOARD_NAME, "PH4PG31") ||
3612 dmi_match(DMI_BOARD_NAME, "PH4PRX1_PH6PRX1") ||
3613 dmi_match(DMI_BOARD_NAME, "PH6PG01_PH6PG71"))
3614 return NVME_QUIRK_FORCE_NO_SIMPLE_SUSPEND;
3615 }
3616
3617 /*
3618 * NVMe SSD drops off the PCIe bus after system idle
3619 * for 10 hours on a Lenovo N60z board.
3620 */
3621 if (dmi_match(DMI_BOARD_NAME, "LXKT-ZXEG-N6"))
3622 return NVME_QUIRK_NO_APST;
3623
3624 return 0;
3625}
3626
3627static struct quirk_entry *detect_dynamic_quirks(struct pci_dev *pdev)
3628{
3629 int i;
3630
3631 for (i = 0; i < nvme_pci_quirk_count; i++)
3632 if (pdev->vendor == nvme_pci_quirk_list[i].vendor_id &&
3633 pdev->device == nvme_pci_quirk_list[i].dev_id)
3634 return &nvme_pci_quirk_list[i];
3635
3636 return NULL;
3637}
3638
3639static struct nvme_dev *nvme_pci_alloc_dev(struct pci_dev *pdev,
3640 const struct pci_device_id *id)
3641{
3642 unsigned long quirks = id->driver_data;
3643 int node = dev_to_node(&pdev->dev);
3644 struct nvme_dev *dev;
3645 struct quirk_entry *qentry;
3646 int ret = -ENOMEM;
3647
3648 dev = kzalloc_node(struct_size(dev, descriptor_pools, nr_node_ids),
3649 GFP_KERNEL, node);
3650 if (!dev)
3651 return ERR_PTR(-ENOMEM);
3652 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
3653 mutex_init(&dev->shutdown_lock);
3654
3655 dev->nr_write_queues = write_queues;
3656 dev->nr_poll_queues = poll_queues;
3657 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
3658 dev->queues = kcalloc_node(dev->nr_allocated_queues,
3659 sizeof(struct nvme_queue), GFP_KERNEL, node);
3660 if (!dev->queues)
3661 goto out_free_dev;
3662
3663 dev->dev = get_device(&pdev->dev);
3664
3665 quirks |= check_vendor_combination_bug(pdev);
3666 if (!noacpi &&
3667 !(quirks & NVME_QUIRK_FORCE_NO_SIMPLE_SUSPEND) &&
3668 acpi_storage_d3(&pdev->dev)) {
3669 /*
3670 * Some systems use a bios work around to ask for D3 on
3671 * platforms that support kernel managed suspend.
3672 */
3673 dev_info(&pdev->dev,
3674 "platform quirk: setting simple suspend\n");
3675 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
3676 }
3677 qentry = detect_dynamic_quirks(pdev);
3678 if (qentry) {
3679 quirks |= qentry->enabled_quirks;
3680 quirks &= ~qentry->disabled_quirks;
3681 }
3682 ret = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
3683 quirks);
3684 if (ret)
3685 goto out_put_device;
3686
3687 if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
3688 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(48));
3689 else
3690 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
3691 dma_set_min_align_mask(&pdev->dev, NVME_CTRL_PAGE_SIZE - 1);
3692 dma_set_max_seg_size(&pdev->dev, 0xffffffff);
3693
3694 /*
3695 * Limit the max command size to prevent iod->sg allocations going
3696 * over a single page.
3697 */
3698 dev->ctrl.max_hw_sectors = min_t(u32,
3699 NVME_MAX_BYTES >> SECTOR_SHIFT,
3700 dma_opt_mapping_size(&pdev->dev) >> 9);
3701 dev->ctrl.max_segments = NVME_MAX_SEGS;
3702 dev->ctrl.max_integrity_segments = 1;
3703 return dev;
3704
3705out_put_device:
3706 put_device(dev->dev);
3707 kfree(dev->queues);
3708out_free_dev:
3709 kfree(dev);
3710 return ERR_PTR(ret);
3711}
3712
3713static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3714{
3715 struct nvme_dev *dev;
3716 int result = -ENOMEM;
3717
3718 dev = nvme_pci_alloc_dev(pdev, id);
3719 if (IS_ERR(dev))
3720 return PTR_ERR(dev);
3721
3722 result = nvme_add_ctrl(&dev->ctrl);
3723 if (result)
3724 goto out_put_ctrl;
3725
3726 result = nvme_dev_map(dev);
3727 if (result)
3728 goto out_uninit_ctrl;
3729
3730 result = nvme_pci_alloc_iod_mempool(dev);
3731 if (result)
3732 goto out_dev_unmap;
3733
3734 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
3735
3736 result = nvme_pci_enable(dev);
3737 if (result)
3738 goto out_release_iod_mempool;
3739
3740 result = nvme_alloc_admin_tag_set(&dev->ctrl, &dev->admin_tagset,
3741 &nvme_mq_admin_ops, sizeof(struct nvme_iod));
3742 if (result)
3743 goto out_disable;
3744
3745 /*
3746 * Mark the controller as connecting before sending admin commands to
3747 * allow the timeout handler to do the right thing.
3748 */
3749 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
3750 dev_warn(dev->ctrl.device,
3751 "failed to mark controller CONNECTING\n");
3752 result = -EBUSY;
3753 goto out_disable;
3754 }
3755
3756 result = nvme_init_ctrl_finish(&dev->ctrl, false);
3757 if (result)
3758 goto out_disable;
3759
3760 if (nvme_ctrl_meta_sgl_supported(&dev->ctrl))
3761 dev->ctrl.max_integrity_segments = NVME_MAX_META_SEGS;
3762 else
3763 dev->ctrl.max_integrity_segments = 1;
3764
3765 nvme_dbbuf_dma_alloc(dev);
3766
3767 result = nvme_setup_host_mem(dev);
3768 if (result < 0)
3769 goto out_disable;
3770
3771 nvme_update_attrs(dev);
3772
3773 result = nvme_setup_io_queues(dev);
3774 if (result)
3775 goto out_disable;
3776
3777 if (dev->online_queues > 1) {
3778 nvme_alloc_io_tag_set(&dev->ctrl, &dev->tagset, &nvme_mq_ops,
3779 nvme_pci_nr_maps(dev), sizeof(struct nvme_iod));
3780 nvme_dbbuf_set(dev);
3781 }
3782
3783 if (!dev->ctrl.tagset)
3784 dev_warn(dev->ctrl.device, "IO queues not created\n");
3785
3786 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
3787 dev_warn(dev->ctrl.device,
3788 "failed to mark controller live state\n");
3789 result = -ENODEV;
3790 goto out_disable;
3791 }
3792
3793 pci_set_drvdata(pdev, dev);
3794
3795 nvme_start_ctrl(&dev->ctrl);
3796 nvme_put_ctrl(&dev->ctrl);
3797 flush_work(&dev->ctrl.scan_work);
3798 return 0;
3799
3800out_disable:
3801 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
3802 nvme_dev_disable(dev, true);
3803 nvme_free_host_mem(dev);
3804 nvme_dev_remove_admin(dev);
3805 nvme_dbbuf_dma_free(dev);
3806 nvme_free_queues(dev, 0);
3807out_release_iod_mempool:
3808 mempool_destroy(dev->dmavec_mempool);
3809out_dev_unmap:
3810 nvme_dev_unmap(dev);
3811out_uninit_ctrl:
3812 nvme_uninit_ctrl(&dev->ctrl);
3813out_put_ctrl:
3814 nvme_put_ctrl(&dev->ctrl);
3815 dev_err_probe(&pdev->dev, result, "probe failed\n");
3816 return result;
3817}
3818
3819static void nvme_reset_prepare(struct pci_dev *pdev)
3820{
3821 struct nvme_dev *dev = pci_get_drvdata(pdev);
3822
3823 /*
3824 * We don't need to check the return value from waiting for the reset
3825 * state as pci_dev device lock is held, making it impossible to race
3826 * with ->remove().
3827 */
3828 nvme_disable_prepare_reset(dev, false);
3829 nvme_sync_queues(&dev->ctrl);
3830}
3831
3832static void nvme_reset_done(struct pci_dev *pdev)
3833{
3834 struct nvme_dev *dev = pci_get_drvdata(pdev);
3835
3836 if (!nvme_try_sched_reset(&dev->ctrl))
3837 flush_work(&dev->ctrl.reset_work);
3838}
3839
3840static void nvme_shutdown(struct pci_dev *pdev)
3841{
3842 struct nvme_dev *dev = pci_get_drvdata(pdev);
3843
3844 nvme_disable_prepare_reset(dev, true);
3845}
3846
3847/*
3848 * The driver's remove may be called on a device in a partially initialized
3849 * state. This function must not have any dependencies on the device state in
3850 * order to proceed.
3851 */
3852static void nvme_remove(struct pci_dev *pdev)
3853{
3854 struct nvme_dev *dev = pci_get_drvdata(pdev);
3855
3856 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
3857 pci_set_drvdata(pdev, NULL);
3858
3859 if (!pci_device_is_present(pdev)) {
3860 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
3861 nvme_dev_disable(dev, true);
3862 }
3863
3864 flush_work(&dev->ctrl.reset_work);
3865 nvme_stop_ctrl(&dev->ctrl);
3866 nvme_remove_namespaces(&dev->ctrl);
3867 nvme_dev_disable(dev, true);
3868 nvme_free_host_mem(dev);
3869 nvme_dev_remove_admin(dev);
3870 nvme_dbbuf_dma_free(dev);
3871 nvme_free_queues(dev, 0);
3872 mempool_destroy(dev->dmavec_mempool);
3873 nvme_release_descriptor_pools(dev);
3874 nvme_dev_unmap(dev);
3875 nvme_uninit_ctrl(&dev->ctrl);
3876}
3877
3878#ifdef CONFIG_PM_SLEEP
3879static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3880{
3881 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3882}
3883
3884static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3885{
3886 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3887}
3888
3889static int nvme_resume(struct device *dev)
3890{
3891 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3892 struct nvme_ctrl *ctrl = &ndev->ctrl;
3893
3894 if (ndev->last_ps == U32_MAX ||
3895 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
3896 goto reset;
3897 if (ctrl->hmpre && nvme_setup_host_mem(ndev))
3898 goto reset;
3899
3900 return 0;
3901reset:
3902 return nvme_try_sched_reset(ctrl);
3903}
3904
3905static int nvme_suspend(struct device *dev)
3906{
3907 struct pci_dev *pdev = to_pci_dev(dev);
3908 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3909 struct nvme_ctrl *ctrl = &ndev->ctrl;
3910 int ret = -EBUSY;
3911
3912 ndev->last_ps = U32_MAX;
3913
3914 /*
3915 * The platform does not remove power for a kernel managed suspend so
3916 * use host managed nvme power settings for lowest idle power if
3917 * possible. This should have quicker resume latency than a full device
3918 * shutdown. But if the firmware is involved after the suspend or the
3919 * device does not support any non-default power states, shut down the
3920 * device fully.
3921 *
3922 * If ASPM is not enabled for the device, shut down the device and allow
3923 * the PCI bus layer to put it into D3 in order to take the PCIe link
3924 * down, so as to allow the platform to achieve its minimum low-power
3925 * state (which may not be possible if the link is up).
3926 */
3927 if (pm_suspend_via_firmware() || !ctrl->npss ||
3928 !pcie_aspm_enabled(pdev) ||
3929 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3930 return nvme_disable_prepare_reset(ndev, true);
3931
3932 nvme_start_freeze(ctrl);
3933 nvme_wait_freeze(ctrl);
3934 nvme_sync_queues(ctrl);
3935
3936 if (nvme_ctrl_state(ctrl) != NVME_CTRL_LIVE)
3937 goto unfreeze;
3938
3939 /*
3940 * Host memory access may not be successful in a system suspend state,
3941 * but the specification allows the controller to access memory in a
3942 * non-operational power state.
3943 */
3944 if (ndev->hmb) {
3945 ret = nvme_set_host_mem(ndev, 0);
3946 if (ret < 0)
3947 goto unfreeze;
3948 }
3949
3950 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3951 if (ret < 0)
3952 goto unfreeze;
3953
3954 /*
3955 * A saved state prevents pci pm from generically controlling the
3956 * device's power. If we're using protocol specific settings, we don't
3957 * want pci interfering.
3958 */
3959 pci_save_state(pdev);
3960
3961 ret = nvme_set_power_state(ctrl, ctrl->npss);
3962 if (ret < 0)
3963 goto unfreeze;
3964
3965 if (ret) {
3966 /* discard the saved state */
3967 pci_load_saved_state(pdev, NULL);
3968
3969 /*
3970 * Clearing npss forces a controller reset on resume. The
3971 * correct value will be rediscovered then.
3972 */
3973 ret = nvme_disable_prepare_reset(ndev, true);
3974 ctrl->npss = 0;
3975 }
3976unfreeze:
3977 nvme_unfreeze(ctrl);
3978 return ret;
3979}
3980
3981static int nvme_simple_suspend(struct device *dev)
3982{
3983 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3984
3985 return nvme_disable_prepare_reset(ndev, true);
3986}
3987
3988static int nvme_simple_resume(struct device *dev)
3989{
3990 struct pci_dev *pdev = to_pci_dev(dev);
3991 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3992
3993 return nvme_try_sched_reset(&ndev->ctrl);
3994}
3995
3996static const struct dev_pm_ops nvme_dev_pm_ops = {
3997 .suspend = nvme_suspend,
3998 .resume = nvme_resume,
3999 .freeze = nvme_simple_suspend,
4000 .thaw = nvme_simple_resume,
4001 .poweroff = nvme_simple_suspend,
4002 .restore = nvme_simple_resume,
4003};
4004#endif /* CONFIG_PM_SLEEP */
4005
4006static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
4007 pci_channel_state_t state)
4008{
4009 struct nvme_dev *dev = pci_get_drvdata(pdev);
4010
4011 /*
4012 * A frozen channel requires a reset. When detected, this method will
4013 * shutdown the controller to quiesce. The controller will be restarted
4014 * after the slot reset through driver's slot_reset callback.
4015 */
4016 switch (state) {
4017 case pci_channel_io_normal:
4018 return PCI_ERS_RESULT_CAN_RECOVER;
4019 case pci_channel_io_frozen:
4020 dev_warn(dev->ctrl.device,
4021 "frozen state error detected, reset controller\n");
4022 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING)) {
4023 nvme_dev_disable(dev, true);
4024 return PCI_ERS_RESULT_DISCONNECT;
4025 }
4026 nvme_dev_disable(dev, false);
4027 return PCI_ERS_RESULT_NEED_RESET;
4028 case pci_channel_io_perm_failure:
4029 dev_warn(dev->ctrl.device,
4030 "failure state error detected, request disconnect\n");
4031 return PCI_ERS_RESULT_DISCONNECT;
4032 }
4033 return PCI_ERS_RESULT_NEED_RESET;
4034}
4035
4036static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
4037{
4038 struct nvme_dev *dev = pci_get_drvdata(pdev);
4039
4040 dev_info(dev->ctrl.device, "restart after slot reset\n");
4041 pci_restore_state(pdev);
4042 if (nvme_try_sched_reset(&dev->ctrl))
4043 nvme_unquiesce_io_queues(&dev->ctrl);
4044 return PCI_ERS_RESULT_RECOVERED;
4045}
4046
4047static void nvme_error_resume(struct pci_dev *pdev)
4048{
4049 struct nvme_dev *dev = pci_get_drvdata(pdev);
4050
4051 flush_work(&dev->ctrl.reset_work);
4052}
4053
4054static const struct pci_error_handlers nvme_err_handler = {
4055 .error_detected = nvme_error_detected,
4056 .slot_reset = nvme_slot_reset,
4057 .resume = nvme_error_resume,
4058 .reset_prepare = nvme_reset_prepare,
4059 .reset_done = nvme_reset_done,
4060};
4061
4062static const struct pci_device_id nvme_id_table[] = {
4063 { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */
4064 .driver_data = NVME_QUIRK_STRIPE_SIZE |
4065 NVME_QUIRK_DEALLOCATE_ZEROES, },
4066 { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */
4067 .driver_data = NVME_QUIRK_STRIPE_SIZE |
4068 NVME_QUIRK_DEALLOCATE_ZEROES, },
4069 { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */
4070 .driver_data = NVME_QUIRK_STRIPE_SIZE |
4071 NVME_QUIRK_IGNORE_DEV_SUBNQN |
4072 NVME_QUIRK_BOGUS_NID, },
4073 { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */
4074 .driver_data = NVME_QUIRK_STRIPE_SIZE, },
4075 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
4076 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
4077 NVME_QUIRK_MEDIUM_PRIO_SQ |
4078 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
4079 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
4080 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
4081 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
4082 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
4083 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
4084 NVME_QUIRK_DISABLE_WRITE_ZEROES |
4085 NVME_QUIRK_BOGUS_NID, },
4086 { PCI_VDEVICE(REDHAT, 0x0010), /* Qemu emulated controller */
4087 .driver_data = NVME_QUIRK_BOGUS_NID, },
4088 { PCI_DEVICE(0x1217, 0x8760), /* O2 Micro 64GB Steam Deck */
4089 .driver_data = NVME_QUIRK_DMAPOOL_ALIGN_512, },
4090 { PCI_DEVICE(0x126f, 0x1001), /* Silicon Motion generic */
4091 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
4092 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
4093 { PCI_DEVICE(0x126f, 0x2262), /* Silicon Motion generic */
4094 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
4095 NVME_QUIRK_BOGUS_NID, },
4096 { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */
4097 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
4098 NVME_QUIRK_BOGUS_NID, },
4099 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
4100 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
4101 NVME_QUIRK_NO_NS_DESC_LIST, },
4102 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
4103 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
4104 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
4105 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
4106 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
4107 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
4108 { PCI_DEVICE(0x1c5f, 0x0555), /* Memblaze Pblaze5 adapter */
4109 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST, },
4110 { PCI_DEVICE(0x144d, 0xa808), /* Samsung PM981/983 */
4111 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
4112 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
4113 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
4114 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
4115 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
4116 NVME_QUIRK_DISABLE_WRITE_ZEROES|
4117 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
4118 { PCI_DEVICE(0x15b7, 0x5008), /* Sandisk SN530 */
4119 .driver_data = NVME_QUIRK_BROKEN_MSI },
4120 { PCI_DEVICE(0x15b7, 0x5009), /* Sandisk SN550 */
4121 .driver_data = NVME_QUIRK_BROKEN_MSI |
4122 NVME_QUIRK_NO_DEEPEST_PS },
4123 { PCI_DEVICE(0x1987, 0x5012), /* Phison E12 */
4124 .driver_data = NVME_QUIRK_BOGUS_NID, },
4125 { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */
4126 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
4127 NVME_QUIRK_BOGUS_NID, },
4128 { PCI_DEVICE(0x1987, 0x5019), /* phison E19 */
4129 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
4130 { PCI_DEVICE(0x1987, 0x5021), /* Phison E21 */
4131 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
4132 { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */
4133 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
4134 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
4135 { PCI_DEVICE(0x1cc1, 0x33f8), /* ADATA IM2P33F8ABR1 1 TB */
4136 .driver_data = NVME_QUIRK_BOGUS_NID, },
4137 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
4138 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
4139 NVME_QUIRK_BOGUS_NID, },
4140 { PCI_DEVICE(0x10ec, 0x5763), /* ADATA SX6000PNP */
4141 .driver_data = NVME_QUIRK_BOGUS_NID, },
4142 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
4143 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
4144 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
4145 { PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */
4146 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN },
4147 { PCI_DEVICE(0x1344, 0x6001), /* Micron Nitro NVMe */
4148 .driver_data = NVME_QUIRK_BOGUS_NID, },
4149 { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */
4150 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
4151 { PCI_DEVICE(0x1c5c, 0x174a), /* SK Hynix P31 SSD */
4152 .driver_data = NVME_QUIRK_BOGUS_NID, },
4153 { PCI_DEVICE(0x1c5c, 0x1D59), /* SK Hynix BC901 */
4154 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
4155 { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */
4156 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
4157 { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */
4158 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
4159 { PCI_DEVICE(0x144d, 0xa80b), /* Samsung PM9B1 256G and 512G */
4160 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES |
4161 NVME_QUIRK_BOGUS_NID, },
4162 { PCI_DEVICE(0x144d, 0xa809), /* Samsung MZALQ256HBJD 256G */
4163 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
4164 { PCI_DEVICE(0x144d, 0xa802), /* Samsung SM953 */
4165 .driver_data = NVME_QUIRK_BOGUS_NID, },
4166 { PCI_DEVICE(0x1cc4, 0x6303), /* UMIS RPJTJ512MGE1QDY 512G */
4167 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
4168 { PCI_DEVICE(0x1cc4, 0x6302), /* UMIS RPJTJ256MGE1QDY 256G */
4169 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
4170 { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */
4171 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
4172 { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */
4173 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
4174 { PCI_DEVICE(0x2646, 0x5013), /* Kingston KC3000, Kingston FURY Renegade */
4175 .driver_data = NVME_QUIRK_NO_SECONDARY_TEMP_THRESH, },
4176 { PCI_DEVICE(0x2646, 0x5018), /* KINGSTON OM8SFP4xxxxP OS21012 NVMe SSD */
4177 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
4178 { PCI_DEVICE(0x2646, 0x5016), /* KINGSTON OM3PGP4xxxxP OS21011 NVMe SSD */
4179 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
4180 { PCI_DEVICE(0x2646, 0x501A), /* KINGSTON OM8PGP4xxxxP OS21005 NVMe SSD */
4181 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
4182 { PCI_DEVICE(0x2646, 0x501B), /* KINGSTON OM8PGP4xxxxQ OS21005 NVMe SSD */
4183 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
4184 { PCI_DEVICE(0x2646, 0x501E), /* KINGSTON OM3PGP4xxxxQ OS21011 NVMe SSD */
4185 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
4186 { PCI_DEVICE(0x2646, 0x502F), /* KINGSTON OM3SGP4xxxxK NVMe SSD */
4187 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
4188 { PCI_DEVICE(0x1f40, 0x1202), /* Netac Technologies Co. NV3000 NVMe SSD */
4189 .driver_data = NVME_QUIRK_BOGUS_NID, },
4190 { PCI_DEVICE(0x1f40, 0x5236), /* Netac Technologies Co. NV7000 NVMe SSD */
4191 .driver_data = NVME_QUIRK_BOGUS_NID, },
4192 { PCI_DEVICE(0x1e4B, 0x1001), /* MAXIO MAP1001 */
4193 .driver_data = NVME_QUIRK_BOGUS_NID, },
4194 { PCI_DEVICE(0x1e4B, 0x1002), /* MAXIO MAP1002 */
4195 .driver_data = NVME_QUIRK_BOGUS_NID, },
4196 { PCI_DEVICE(0x1e4B, 0x1202), /* MAXIO MAP1202 */
4197 .driver_data = NVME_QUIRK_BOGUS_NID, },
4198 { PCI_DEVICE(0x1e4B, 0x1602), /* MAXIO MAP1602 */
4199 .driver_data = NVME_QUIRK_BOGUS_NID, },
4200 { PCI_DEVICE(0x1cc1, 0x5350), /* ADATA XPG GAMMIX S50 */
4201 .driver_data = NVME_QUIRK_BOGUS_NID, },
4202 { PCI_DEVICE(0x1dbe, 0x5216), /* Acer/INNOGRIT FA100/5216 NVMe SSD */
4203 .driver_data = NVME_QUIRK_BOGUS_NID, },
4204 { PCI_DEVICE(0x1dbe, 0x5236), /* ADATA XPG GAMMIX S70 */
4205 .driver_data = NVME_QUIRK_BOGUS_NID, },
4206 { PCI_DEVICE(0x1e49, 0x0021), /* ZHITAI TiPro5000 NVMe SSD */
4207 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
4208 { PCI_DEVICE(0x1e49, 0x0041), /* ZHITAI TiPro7000 NVMe SSD */
4209 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
4210 { PCI_DEVICE(0x1fa0, 0x2283), /* Wodposit WPBSNM8-256GTP */
4211 .driver_data = NVME_QUIRK_NO_SECONDARY_TEMP_THRESH, },
4212 { PCI_DEVICE(0x025e, 0xf1ac), /* SOLIDIGM P44 pro SSDPFKKW020X7 */
4213 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
4214 { PCI_DEVICE(0xc0a9, 0x540a), /* Crucial P2 */
4215 .driver_data = NVME_QUIRK_BOGUS_NID, },
4216 { PCI_DEVICE(0x1d97, 0x2263), /* Lexar NM610 */
4217 .driver_data = NVME_QUIRK_BOGUS_NID, },
4218 { PCI_DEVICE(0x1d97, 0x1d97), /* Lexar NM620 */
4219 .driver_data = NVME_QUIRK_BOGUS_NID, },
4220 { PCI_DEVICE(0x1d97, 0x2269), /* Lexar NM760 */
4221 .driver_data = NVME_QUIRK_BOGUS_NID |
4222 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
4223 { PCI_DEVICE(0x10ec, 0x5763), /* TEAMGROUP T-FORCE CARDEA ZERO Z330 SSD */
4224 .driver_data = NVME_QUIRK_BOGUS_NID, },
4225 { PCI_DEVICE(0x1e4b, 0x1602), /* HS-SSD-FUTURE 2048G */
4226 .driver_data = NVME_QUIRK_BOGUS_NID, },
4227 { PCI_DEVICE(0x10ec, 0x5765), /* TEAMGROUP MP33 2TB SSD */
4228 .driver_data = NVME_QUIRK_BOGUS_NID, },
4229 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
4230 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
4231 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
4232 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
4233 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
4234 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
4235 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
4236 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
4237 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
4238 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
4239 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
4240 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
4241 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
4242 /*
4243 * Fix for the Apple controller found in the MacBook8,1 and
4244 * some MacBook7,1 to avoid controller resets and data loss.
4245 */
4246 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
4247 NVME_QUIRK_QDEPTH_ONE },
4248 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
4249 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
4250 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
4251 NVME_QUIRK_128_BYTES_SQES |
4252 NVME_QUIRK_SHARED_TAGS |
4253 NVME_QUIRK_SKIP_CID_GEN |
4254 NVME_QUIRK_IDENTIFY_CNS },
4255 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
4256 { 0, }
4257};
4258MODULE_DEVICE_TABLE(pci, nvme_id_table);
4259
4260static struct pci_driver nvme_driver = {
4261 .name = "nvme",
4262 .id_table = nvme_id_table,
4263 .probe = nvme_probe,
4264 .remove = nvme_remove,
4265 .shutdown = nvme_shutdown,
4266 .driver = {
4267 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
4268#ifdef CONFIG_PM_SLEEP
4269 .pm = &nvme_dev_pm_ops,
4270#endif
4271 },
4272 .sriov_configure = pci_sriov_configure_simple,
4273 .err_handler = &nvme_err_handler,
4274};
4275
4276static int __init nvme_init(void)
4277{
4278 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
4279 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
4280 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
4281 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
4282
4283 return pci_register_driver(&nvme_driver);
4284}
4285
4286static void __exit nvme_exit(void)
4287{
4288 kfree(nvme_pci_quirk_list);
4289 pci_unregister_driver(&nvme_driver);
4290 flush_workqueue(nvme_wq);
4291}
4292
4293MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
4294MODULE_LICENSE("GPL");
4295MODULE_VERSION("1.0");
4296MODULE_DESCRIPTION("NVMe host PCIe transport driver");
4297module_init(nvme_init);
4298module_exit(nvme_exit);