Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * ARMv8 PMUv3 Performance Events handling code.
4 *
5 * Copyright (C) 2012 ARM Limited
6 * Author: Will Deacon <will.deacon@arm.com>
7 *
8 * This code is based heavily on the ARMv7 perf event code.
9 */
10
11#include <asm/irq_regs.h>
12#include <asm/perf_event.h>
13#include <asm/virt.h>
14
15#include <clocksource/arm_arch_timer.h>
16
17#include <linux/acpi.h>
18#include <linux/bitfield.h>
19#include <linux/clocksource.h>
20#include <linux/of.h>
21#include <linux/perf/arm_pmu.h>
22#include <linux/perf/arm_pmuv3.h>
23#include <linux/platform_device.h>
24#include <linux/sched_clock.h>
25#include <linux/smp.h>
26#include <linux/nmi.h>
27
28#include "arm_brbe.h"
29
30/* ARMv8 Cortex-A53 specific event types. */
31#define ARMV8_A53_PERFCTR_PREF_LINEFILL 0xC2
32
33/* ARMv8 Cavium ThunderX specific event types. */
34#define ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST 0xE9
35#define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS 0xEA
36#define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS 0xEB
37#define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS 0xEC
38#define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS 0xED
39
40/*
41 * ARMv8 Architectural defined events, not all of these may
42 * be supported on any given implementation. Unsupported events will
43 * be disabled at run-time based on the PMCEID registers.
44 */
45static const unsigned armv8_pmuv3_perf_map[PERF_COUNT_HW_MAX] = {
46 PERF_MAP_ALL_UNSUPPORTED,
47 [PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
48 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
49 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
50 [PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
51 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
52 [PERF_COUNT_HW_BUS_CYCLES] = ARMV8_PMUV3_PERFCTR_BUS_CYCLES,
53 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV8_PMUV3_PERFCTR_STALL_FRONTEND,
54 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV8_PMUV3_PERFCTR_STALL_BACKEND,
55};
56
57static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
58 [PERF_COUNT_HW_CACHE_OP_MAX]
59 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
60 PERF_CACHE_MAP_ALL_UNSUPPORTED,
61
62 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
63 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
64
65 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
66 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
67
68 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL,
69 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB,
70
71 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
72 [C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB,
73
74 [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD,
75 [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_LL_CACHE_RD,
76
77 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
78 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
79};
80
81static const unsigned armv8_a53_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
82 [PERF_COUNT_HW_CACHE_OP_MAX]
83 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
84 PERF_CACHE_MAP_ALL_UNSUPPORTED,
85
86 [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_A53_PERFCTR_PREF_LINEFILL,
87
88 [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
89 [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
90};
91
92static const unsigned armv8_a57_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
93 [PERF_COUNT_HW_CACHE_OP_MAX]
94 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
95 PERF_CACHE_MAP_ALL_UNSUPPORTED,
96
97 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
98 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
99 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
100 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR,
101
102 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
103 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
104
105 [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
106 [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
107};
108
109static const unsigned armv8_a73_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
110 [PERF_COUNT_HW_CACHE_OP_MAX]
111 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
112 PERF_CACHE_MAP_ALL_UNSUPPORTED,
113
114 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
115 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
116};
117
118static const unsigned armv8_thunder_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
119 [PERF_COUNT_HW_CACHE_OP_MAX]
120 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
121 PERF_CACHE_MAP_ALL_UNSUPPORTED,
122
123 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
124 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
125 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
126 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST,
127 [C(L1D)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS,
128 [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS,
129
130 [C(L1I)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS,
131 [C(L1I)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS,
132
133 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD,
134 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
135 [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR,
136 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
137};
138
139static const unsigned armv8_vulcan_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
140 [PERF_COUNT_HW_CACHE_OP_MAX]
141 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
142 PERF_CACHE_MAP_ALL_UNSUPPORTED,
143
144 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
145 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
146 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
147 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR,
148
149 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD,
150 [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR,
151 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
152 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
153
154 [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
155 [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
156};
157
158static ssize_t
159armv8pmu_events_sysfs_show(struct device *dev,
160 struct device_attribute *attr, char *page)
161{
162 struct perf_pmu_events_attr *pmu_attr;
163
164 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
165
166 return sprintf(page, "event=0x%04llx\n", pmu_attr->id);
167}
168
169#define ARMV8_EVENT_ATTR(name, config) \
170 PMU_EVENT_ATTR_ID(name, armv8pmu_events_sysfs_show, config)
171
172static struct attribute *armv8_pmuv3_event_attrs[] = {
173 /*
174 * Don't expose the sw_incr event in /sys. It's not usable as writes to
175 * PMSWINC_EL0 will trap as PMUSERENR.{SW,EN}=={0,0} and event rotation
176 * means we don't have a fixed event<->counter relationship regardless.
177 */
178 ARMV8_EVENT_ATTR(l1i_cache_refill, ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL),
179 ARMV8_EVENT_ATTR(l1i_tlb_refill, ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL),
180 ARMV8_EVENT_ATTR(l1d_cache_refill, ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL),
181 ARMV8_EVENT_ATTR(l1d_cache, ARMV8_PMUV3_PERFCTR_L1D_CACHE),
182 ARMV8_EVENT_ATTR(l1d_tlb_refill, ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL),
183 ARMV8_EVENT_ATTR(ld_retired, ARMV8_PMUV3_PERFCTR_LD_RETIRED),
184 ARMV8_EVENT_ATTR(st_retired, ARMV8_PMUV3_PERFCTR_ST_RETIRED),
185 ARMV8_EVENT_ATTR(inst_retired, ARMV8_PMUV3_PERFCTR_INST_RETIRED),
186 ARMV8_EVENT_ATTR(exc_taken, ARMV8_PMUV3_PERFCTR_EXC_TAKEN),
187 ARMV8_EVENT_ATTR(exc_return, ARMV8_PMUV3_PERFCTR_EXC_RETURN),
188 ARMV8_EVENT_ATTR(cid_write_retired, ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED),
189 ARMV8_EVENT_ATTR(pc_write_retired, ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED),
190 ARMV8_EVENT_ATTR(br_immed_retired, ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED),
191 ARMV8_EVENT_ATTR(br_return_retired, ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED),
192 ARMV8_EVENT_ATTR(unaligned_ldst_retired, ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED),
193 ARMV8_EVENT_ATTR(br_mis_pred, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED),
194 ARMV8_EVENT_ATTR(cpu_cycles, ARMV8_PMUV3_PERFCTR_CPU_CYCLES),
195 ARMV8_EVENT_ATTR(br_pred, ARMV8_PMUV3_PERFCTR_BR_PRED),
196 ARMV8_EVENT_ATTR(mem_access, ARMV8_PMUV3_PERFCTR_MEM_ACCESS),
197 ARMV8_EVENT_ATTR(l1i_cache, ARMV8_PMUV3_PERFCTR_L1I_CACHE),
198 ARMV8_EVENT_ATTR(l1d_cache_wb, ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB),
199 ARMV8_EVENT_ATTR(l2d_cache, ARMV8_PMUV3_PERFCTR_L2D_CACHE),
200 ARMV8_EVENT_ATTR(l2d_cache_refill, ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL),
201 ARMV8_EVENT_ATTR(l2d_cache_wb, ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB),
202 ARMV8_EVENT_ATTR(bus_access, ARMV8_PMUV3_PERFCTR_BUS_ACCESS),
203 ARMV8_EVENT_ATTR(memory_error, ARMV8_PMUV3_PERFCTR_MEMORY_ERROR),
204 ARMV8_EVENT_ATTR(inst_spec, ARMV8_PMUV3_PERFCTR_INST_SPEC),
205 ARMV8_EVENT_ATTR(ttbr_write_retired, ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED),
206 ARMV8_EVENT_ATTR(bus_cycles, ARMV8_PMUV3_PERFCTR_BUS_CYCLES),
207 /* Don't expose the chain event in /sys, since it's useless in isolation */
208 ARMV8_EVENT_ATTR(l1d_cache_allocate, ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE),
209 ARMV8_EVENT_ATTR(l2d_cache_allocate, ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE),
210 ARMV8_EVENT_ATTR(br_retired, ARMV8_PMUV3_PERFCTR_BR_RETIRED),
211 ARMV8_EVENT_ATTR(br_mis_pred_retired, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED),
212 ARMV8_EVENT_ATTR(stall_frontend, ARMV8_PMUV3_PERFCTR_STALL_FRONTEND),
213 ARMV8_EVENT_ATTR(stall_backend, ARMV8_PMUV3_PERFCTR_STALL_BACKEND),
214 ARMV8_EVENT_ATTR(l1d_tlb, ARMV8_PMUV3_PERFCTR_L1D_TLB),
215 ARMV8_EVENT_ATTR(l1i_tlb, ARMV8_PMUV3_PERFCTR_L1I_TLB),
216 ARMV8_EVENT_ATTR(l2i_cache, ARMV8_PMUV3_PERFCTR_L2I_CACHE),
217 ARMV8_EVENT_ATTR(l2i_cache_refill, ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL),
218 ARMV8_EVENT_ATTR(l3d_cache_allocate, ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE),
219 ARMV8_EVENT_ATTR(l3d_cache_refill, ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL),
220 ARMV8_EVENT_ATTR(l3d_cache, ARMV8_PMUV3_PERFCTR_L3D_CACHE),
221 ARMV8_EVENT_ATTR(l3d_cache_wb, ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB),
222 ARMV8_EVENT_ATTR(l2d_tlb_refill, ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL),
223 ARMV8_EVENT_ATTR(l2i_tlb_refill, ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL),
224 ARMV8_EVENT_ATTR(l2d_tlb, ARMV8_PMUV3_PERFCTR_L2D_TLB),
225 ARMV8_EVENT_ATTR(l2i_tlb, ARMV8_PMUV3_PERFCTR_L2I_TLB),
226 ARMV8_EVENT_ATTR(remote_access, ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS),
227 ARMV8_EVENT_ATTR(ll_cache, ARMV8_PMUV3_PERFCTR_LL_CACHE),
228 ARMV8_EVENT_ATTR(ll_cache_miss, ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS),
229 ARMV8_EVENT_ATTR(dtlb_walk, ARMV8_PMUV3_PERFCTR_DTLB_WALK),
230 ARMV8_EVENT_ATTR(itlb_walk, ARMV8_PMUV3_PERFCTR_ITLB_WALK),
231 ARMV8_EVENT_ATTR(ll_cache_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_RD),
232 ARMV8_EVENT_ATTR(ll_cache_miss_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD),
233 ARMV8_EVENT_ATTR(remote_access_rd, ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD),
234 ARMV8_EVENT_ATTR(l1d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD),
235 ARMV8_EVENT_ATTR(op_retired, ARMV8_PMUV3_PERFCTR_OP_RETIRED),
236 ARMV8_EVENT_ATTR(op_spec, ARMV8_PMUV3_PERFCTR_OP_SPEC),
237 ARMV8_EVENT_ATTR(stall, ARMV8_PMUV3_PERFCTR_STALL),
238 ARMV8_EVENT_ATTR(stall_slot_backend, ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND),
239 ARMV8_EVENT_ATTR(stall_slot_frontend, ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND),
240 ARMV8_EVENT_ATTR(stall_slot, ARMV8_PMUV3_PERFCTR_STALL_SLOT),
241 ARMV8_EVENT_ATTR(sample_pop, ARMV8_SPE_PERFCTR_SAMPLE_POP),
242 ARMV8_EVENT_ATTR(sample_feed, ARMV8_SPE_PERFCTR_SAMPLE_FEED),
243 ARMV8_EVENT_ATTR(sample_filtrate, ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE),
244 ARMV8_EVENT_ATTR(sample_collision, ARMV8_SPE_PERFCTR_SAMPLE_COLLISION),
245 ARMV8_EVENT_ATTR(cnt_cycles, ARMV8_AMU_PERFCTR_CNT_CYCLES),
246 ARMV8_EVENT_ATTR(stall_backend_mem, ARMV8_AMU_PERFCTR_STALL_BACKEND_MEM),
247 ARMV8_EVENT_ATTR(l1i_cache_lmiss, ARMV8_PMUV3_PERFCTR_L1I_CACHE_LMISS),
248 ARMV8_EVENT_ATTR(l2d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L2D_CACHE_LMISS_RD),
249 ARMV8_EVENT_ATTR(l2i_cache_lmiss, ARMV8_PMUV3_PERFCTR_L2I_CACHE_LMISS),
250 ARMV8_EVENT_ATTR(l3d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L3D_CACHE_LMISS_RD),
251 ARMV8_EVENT_ATTR(trb_wrap, ARMV8_PMUV3_PERFCTR_TRB_WRAP),
252 ARMV8_EVENT_ATTR(trb_trig, ARMV8_PMUV3_PERFCTR_TRB_TRIG),
253 ARMV8_EVENT_ATTR(trcextout0, ARMV8_PMUV3_PERFCTR_TRCEXTOUT0),
254 ARMV8_EVENT_ATTR(trcextout1, ARMV8_PMUV3_PERFCTR_TRCEXTOUT1),
255 ARMV8_EVENT_ATTR(trcextout2, ARMV8_PMUV3_PERFCTR_TRCEXTOUT2),
256 ARMV8_EVENT_ATTR(trcextout3, ARMV8_PMUV3_PERFCTR_TRCEXTOUT3),
257 ARMV8_EVENT_ATTR(cti_trigout4, ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT4),
258 ARMV8_EVENT_ATTR(cti_trigout5, ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT5),
259 ARMV8_EVENT_ATTR(cti_trigout6, ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT6),
260 ARMV8_EVENT_ATTR(cti_trigout7, ARMV8_PMUV3_PERFCTR_CTI_TRIGOUT7),
261 ARMV8_EVENT_ATTR(ldst_align_lat, ARMV8_PMUV3_PERFCTR_LDST_ALIGN_LAT),
262 ARMV8_EVENT_ATTR(ld_align_lat, ARMV8_PMUV3_PERFCTR_LD_ALIGN_LAT),
263 ARMV8_EVENT_ATTR(st_align_lat, ARMV8_PMUV3_PERFCTR_ST_ALIGN_LAT),
264 ARMV8_EVENT_ATTR(mem_access_checked, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED),
265 ARMV8_EVENT_ATTR(mem_access_checked_rd, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_RD),
266 ARMV8_EVENT_ATTR(mem_access_checked_wr, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_WR),
267 NULL,
268};
269
270static umode_t
271armv8pmu_event_attr_is_visible(struct kobject *kobj,
272 struct attribute *attr, int unused)
273{
274 struct device *dev = kobj_to_dev(kobj);
275 struct pmu *pmu = dev_get_drvdata(dev);
276 struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
277 struct perf_pmu_events_attr *pmu_attr;
278
279 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr);
280
281 if (pmu_attr->id < ARMV8_PMUV3_MAX_COMMON_EVENTS &&
282 test_bit(pmu_attr->id, cpu_pmu->pmceid_bitmap))
283 return attr->mode;
284
285 if (pmu_attr->id >= ARMV8_PMUV3_EXT_COMMON_EVENT_BASE) {
286 u64 id = pmu_attr->id - ARMV8_PMUV3_EXT_COMMON_EVENT_BASE;
287
288 if (id < ARMV8_PMUV3_MAX_COMMON_EVENTS &&
289 test_bit(id, cpu_pmu->pmceid_ext_bitmap))
290 return attr->mode;
291 }
292
293 return 0;
294}
295
296static const struct attribute_group armv8_pmuv3_events_attr_group = {
297 .name = "events",
298 .attrs = armv8_pmuv3_event_attrs,
299 .is_visible = armv8pmu_event_attr_is_visible,
300};
301
302/* User ABI */
303#define ATTR_CFG_FLD_event_CFG config
304#define ATTR_CFG_FLD_event_LO 0
305#define ATTR_CFG_FLD_event_HI 15
306#define ATTR_CFG_FLD_long_CFG config1
307#define ATTR_CFG_FLD_long_LO 0
308#define ATTR_CFG_FLD_long_HI 0
309#define ATTR_CFG_FLD_rdpmc_CFG config1
310#define ATTR_CFG_FLD_rdpmc_LO 1
311#define ATTR_CFG_FLD_rdpmc_HI 1
312#define ATTR_CFG_FLD_threshold_count_CFG config1 /* PMEVTYPER.TC[0] */
313#define ATTR_CFG_FLD_threshold_count_LO 2
314#define ATTR_CFG_FLD_threshold_count_HI 2
315#define ATTR_CFG_FLD_threshold_compare_CFG config1 /* PMEVTYPER.TC[2:1] */
316#define ATTR_CFG_FLD_threshold_compare_LO 3
317#define ATTR_CFG_FLD_threshold_compare_HI 4
318#define ATTR_CFG_FLD_threshold_CFG config1 /* PMEVTYPER.TH */
319#define ATTR_CFG_FLD_threshold_LO 5
320#define ATTR_CFG_FLD_threshold_HI 16
321
322GEN_PMU_FORMAT_ATTR(event);
323GEN_PMU_FORMAT_ATTR(long);
324GEN_PMU_FORMAT_ATTR(rdpmc);
325GEN_PMU_FORMAT_ATTR(threshold_count);
326GEN_PMU_FORMAT_ATTR(threshold_compare);
327GEN_PMU_FORMAT_ATTR(threshold);
328
329static int sysctl_perf_user_access __read_mostly;
330
331static bool armv8pmu_event_is_64bit(struct perf_event *event)
332{
333 return ATTR_CFG_GET_FLD(&event->attr, long);
334}
335
336static bool armv8pmu_event_want_user_access(struct perf_event *event)
337{
338 return ATTR_CFG_GET_FLD(&event->attr, rdpmc);
339}
340
341static u32 armv8pmu_event_get_threshold(struct perf_event_attr *attr)
342{
343 return ATTR_CFG_GET_FLD(attr, threshold);
344}
345
346static u8 armv8pmu_event_threshold_control(struct perf_event_attr *attr)
347{
348 u8 th_compare = ATTR_CFG_GET_FLD(attr, threshold_compare);
349 u8 th_count = ATTR_CFG_GET_FLD(attr, threshold_count);
350
351 /*
352 * The count bit is always the bottom bit of the full control field, and
353 * the comparison is the upper two bits, but it's not explicitly
354 * labelled in the Arm ARM. For the Perf interface we split it into two
355 * fields, so reconstruct it here.
356 */
357 return (th_compare << 1) | th_count;
358}
359
360static struct attribute *armv8_pmuv3_format_attrs[] = {
361 &format_attr_event.attr,
362 &format_attr_long.attr,
363 &format_attr_rdpmc.attr,
364 &format_attr_threshold.attr,
365 &format_attr_threshold_compare.attr,
366 &format_attr_threshold_count.attr,
367 NULL,
368};
369
370static const struct attribute_group armv8_pmuv3_format_attr_group = {
371 .name = "format",
372 .attrs = armv8_pmuv3_format_attrs,
373};
374
375static ssize_t slots_show(struct device *dev, struct device_attribute *attr,
376 char *page)
377{
378 struct pmu *pmu = dev_get_drvdata(dev);
379 struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
380 u32 slots = FIELD_GET(ARMV8_PMU_SLOTS, cpu_pmu->reg_pmmir);
381
382 return sysfs_emit(page, "0x%08x\n", slots);
383}
384
385static DEVICE_ATTR_RO(slots);
386
387static ssize_t bus_slots_show(struct device *dev, struct device_attribute *attr,
388 char *page)
389{
390 struct pmu *pmu = dev_get_drvdata(dev);
391 struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
392 u32 bus_slots = FIELD_GET(ARMV8_PMU_BUS_SLOTS, cpu_pmu->reg_pmmir);
393
394 return sysfs_emit(page, "0x%08x\n", bus_slots);
395}
396
397static DEVICE_ATTR_RO(bus_slots);
398
399static ssize_t bus_width_show(struct device *dev, struct device_attribute *attr,
400 char *page)
401{
402 struct pmu *pmu = dev_get_drvdata(dev);
403 struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
404 u32 bus_width = FIELD_GET(ARMV8_PMU_BUS_WIDTH, cpu_pmu->reg_pmmir);
405 u32 val = 0;
406
407 /* Encoded as Log2(number of bytes), plus one */
408 if (bus_width > 2 && bus_width < 13)
409 val = 1 << (bus_width - 1);
410
411 return sysfs_emit(page, "0x%08x\n", val);
412}
413
414static DEVICE_ATTR_RO(bus_width);
415
416static u32 threshold_max(struct arm_pmu *cpu_pmu)
417{
418 /*
419 * PMMIR.THWIDTH is readable and non-zero on aarch32, but it would be
420 * impossible to write the threshold in the upper 32 bits of PMEVTYPER.
421 */
422 if (IS_ENABLED(CONFIG_ARM))
423 return 0;
424
425 /*
426 * The largest value that can be written to PMEVTYPER<n>_EL0.TH is
427 * (2 ^ PMMIR.THWIDTH) - 1.
428 */
429 return (1 << FIELD_GET(ARMV8_PMU_THWIDTH, cpu_pmu->reg_pmmir)) - 1;
430}
431
432static ssize_t threshold_max_show(struct device *dev,
433 struct device_attribute *attr, char *page)
434{
435 struct pmu *pmu = dev_get_drvdata(dev);
436 struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
437
438 return sysfs_emit(page, "0x%08x\n", threshold_max(cpu_pmu));
439}
440
441static DEVICE_ATTR_RO(threshold_max);
442
443static ssize_t branches_show(struct device *dev,
444 struct device_attribute *attr, char *page)
445{
446 struct pmu *pmu = dev_get_drvdata(dev);
447 struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
448
449 return sysfs_emit(page, "%d\n", brbe_num_branch_records(cpu_pmu));
450}
451
452static DEVICE_ATTR_RO(branches);
453
454static struct attribute *armv8_pmuv3_caps_attrs[] = {
455 &dev_attr_branches.attr,
456 &dev_attr_slots.attr,
457 &dev_attr_bus_slots.attr,
458 &dev_attr_bus_width.attr,
459 &dev_attr_threshold_max.attr,
460 NULL,
461};
462
463static umode_t caps_is_visible(struct kobject *kobj, struct attribute *attr, int i)
464{
465 struct device *dev = kobj_to_dev(kobj);
466 struct pmu *pmu = dev_get_drvdata(dev);
467 struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
468
469 if (i == 0)
470 return brbe_num_branch_records(cpu_pmu) ? attr->mode : 0;
471
472 return attr->mode;
473}
474
475static const struct attribute_group armv8_pmuv3_caps_attr_group = {
476 .name = "caps",
477 .attrs = armv8_pmuv3_caps_attrs,
478 .is_visible = caps_is_visible,
479};
480
481/*
482 * We unconditionally enable ARMv8.5-PMU long event counter support
483 * (64-bit events) where supported. Indicate if this arm_pmu has long
484 * event counter support.
485 *
486 * On AArch32, long counters make no sense (you can't access the top
487 * bits), so we only enable this on AArch64.
488 */
489static bool armv8pmu_has_long_event(struct arm_pmu *cpu_pmu)
490{
491 return (IS_ENABLED(CONFIG_ARM64) && is_pmuv3p5(cpu_pmu->pmuver));
492}
493
494static bool armv8pmu_event_has_user_read(struct perf_event *event)
495{
496 return event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT;
497}
498
499/*
500 * We must chain two programmable counters for 64 bit events,
501 * except when we have allocated the 64bit cycle counter (for CPU
502 * cycles event) or when user space counter access is enabled.
503 */
504static bool armv8pmu_event_is_chained(struct perf_event *event)
505{
506 int idx = event->hw.idx;
507 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
508
509 return !armv8pmu_event_has_user_read(event) &&
510 armv8pmu_event_is_64bit(event) &&
511 !armv8pmu_has_long_event(cpu_pmu) &&
512 (idx < ARMV8_PMU_MAX_GENERAL_COUNTERS);
513}
514
515/*
516 * ARMv8 low level PMU access
517 */
518static u64 armv8pmu_pmcr_read(void)
519{
520 return read_pmcr();
521}
522
523static void armv8pmu_pmcr_write(u64 val)
524{
525 val &= ARMV8_PMU_PMCR_MASK;
526 isb();
527 write_pmcr(val);
528}
529
530static int armv8pmu_has_overflowed(u64 pmovsr)
531{
532 return !!(pmovsr & ARMV8_PMU_OVERFLOWED_MASK);
533}
534
535static int armv8pmu_counter_has_overflowed(u64 pmnc, int idx)
536{
537 return !!(pmnc & BIT(idx));
538}
539
540static u64 armv8pmu_read_evcntr(int idx)
541{
542 return read_pmevcntrn(idx);
543}
544
545static u64 armv8pmu_read_hw_counter(struct perf_event *event)
546{
547 int idx = event->hw.idx;
548 u64 val = armv8pmu_read_evcntr(idx);
549
550 if (armv8pmu_event_is_chained(event))
551 val = (val << 32) | armv8pmu_read_evcntr(idx - 1);
552 return val;
553}
554
555/*
556 * The cycle counter is always a 64-bit counter. When ARMV8_PMU_PMCR_LP
557 * is set the event counters also become 64-bit counters. Unless the
558 * user has requested a long counter (attr.config1) then we want to
559 * interrupt upon 32-bit overflow - we achieve this by applying a bias.
560 */
561static bool armv8pmu_event_needs_bias(struct perf_event *event)
562{
563 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
564 struct hw_perf_event *hwc = &event->hw;
565 int idx = hwc->idx;
566
567 if (armv8pmu_event_is_64bit(event))
568 return false;
569
570 if (armv8pmu_has_long_event(cpu_pmu) ||
571 idx >= ARMV8_PMU_MAX_GENERAL_COUNTERS)
572 return true;
573
574 return false;
575}
576
577static u64 armv8pmu_bias_long_counter(struct perf_event *event, u64 value)
578{
579 if (armv8pmu_event_needs_bias(event))
580 value |= GENMASK_ULL(63, 32);
581
582 return value;
583}
584
585static u64 armv8pmu_unbias_long_counter(struct perf_event *event, u64 value)
586{
587 if (armv8pmu_event_needs_bias(event))
588 value &= ~GENMASK_ULL(63, 32);
589
590 return value;
591}
592
593static u64 armv8pmu_read_counter(struct perf_event *event)
594{
595 struct hw_perf_event *hwc = &event->hw;
596 int idx = hwc->idx;
597 u64 value;
598
599 if (idx == ARMV8_PMU_CYCLE_IDX)
600 value = read_pmccntr();
601 else if (idx == ARMV8_PMU_INSTR_IDX)
602 value = read_pmicntr();
603 else
604 value = armv8pmu_read_hw_counter(event);
605
606 return armv8pmu_unbias_long_counter(event, value);
607}
608
609static void armv8pmu_write_evcntr(int idx, u64 value)
610{
611 write_pmevcntrn(idx, value);
612}
613
614static void armv8pmu_write_hw_counter(struct perf_event *event,
615 u64 value)
616{
617 int idx = event->hw.idx;
618
619 if (armv8pmu_event_is_chained(event)) {
620 armv8pmu_write_evcntr(idx, upper_32_bits(value));
621 armv8pmu_write_evcntr(idx - 1, lower_32_bits(value));
622 } else {
623 armv8pmu_write_evcntr(idx, value);
624 }
625}
626
627static void armv8pmu_write_counter(struct perf_event *event, u64 value)
628{
629 struct hw_perf_event *hwc = &event->hw;
630 int idx = hwc->idx;
631
632 value = armv8pmu_bias_long_counter(event, value);
633
634 if (idx == ARMV8_PMU_CYCLE_IDX)
635 write_pmccntr(value);
636 else if (idx == ARMV8_PMU_INSTR_IDX)
637 write_pmicntr(value);
638 else
639 armv8pmu_write_hw_counter(event, value);
640}
641
642static void armv8pmu_write_evtype(int idx, unsigned long val)
643{
644 unsigned long mask = ARMV8_PMU_EVTYPE_EVENT |
645 ARMV8_PMU_INCLUDE_EL2 |
646 ARMV8_PMU_EXCLUDE_EL0 |
647 ARMV8_PMU_EXCLUDE_EL1;
648
649 if (IS_ENABLED(CONFIG_ARM64))
650 mask |= ARMV8_PMU_EVTYPE_TC | ARMV8_PMU_EVTYPE_TH;
651
652 val &= mask;
653 write_pmevtypern(idx, val);
654}
655
656static void armv8pmu_write_event_type(struct perf_event *event)
657{
658 struct hw_perf_event *hwc = &event->hw;
659 int idx = hwc->idx;
660
661 /*
662 * For chained events, the low counter is programmed to count
663 * the event of interest and the high counter is programmed
664 * with CHAIN event code with filters set to count at all ELs.
665 */
666 if (armv8pmu_event_is_chained(event)) {
667 u32 chain_evt = ARMV8_PMUV3_PERFCTR_CHAIN |
668 ARMV8_PMU_INCLUDE_EL2;
669
670 armv8pmu_write_evtype(idx - 1, hwc->config_base);
671 armv8pmu_write_evtype(idx, chain_evt);
672 } else {
673 if (idx == ARMV8_PMU_CYCLE_IDX)
674 write_pmccfiltr(hwc->config_base);
675 else if (idx == ARMV8_PMU_INSTR_IDX)
676 write_pmicfiltr(hwc->config_base);
677 else
678 armv8pmu_write_evtype(idx, hwc->config_base);
679 }
680}
681
682static u64 armv8pmu_event_cnten_mask(struct perf_event *event)
683{
684 int counter = event->hw.idx;
685 u64 mask = BIT(counter);
686
687 if (armv8pmu_event_is_chained(event))
688 mask |= BIT(counter - 1);
689 return mask;
690}
691
692static void armv8pmu_enable_counter(u64 mask)
693{
694 /*
695 * Make sure event configuration register writes are visible before we
696 * enable the counter.
697 * */
698 isb();
699 write_pmcntenset(mask);
700}
701
702static void armv8pmu_enable_event_counter(struct perf_event *event)
703{
704 struct perf_event_attr *attr = &event->attr;
705 u64 mask = armv8pmu_event_cnten_mask(event);
706
707 kvm_set_pmu_events(mask, attr);
708
709 /* We rely on the hypervisor switch code to enable guest counters */
710 if (!kvm_pmu_counter_deferred(attr))
711 armv8pmu_enable_counter(mask);
712}
713
714static void armv8pmu_disable_counter(u64 mask)
715{
716 write_pmcntenclr(mask);
717 /*
718 * Make sure the effects of disabling the counter are visible before we
719 * start configuring the event.
720 */
721 isb();
722}
723
724static void armv8pmu_disable_event_counter(struct perf_event *event)
725{
726 struct perf_event_attr *attr = &event->attr;
727 u64 mask = armv8pmu_event_cnten_mask(event);
728
729 kvm_clr_pmu_events(mask);
730
731 /* We rely on the hypervisor switch code to disable guest counters */
732 if (!kvm_pmu_counter_deferred(attr))
733 armv8pmu_disable_counter(mask);
734}
735
736static void armv8pmu_enable_intens(u64 mask)
737{
738 write_pmintenset(mask);
739}
740
741static void armv8pmu_enable_event_irq(struct perf_event *event)
742{
743 armv8pmu_enable_intens(BIT(event->hw.idx));
744}
745
746static void armv8pmu_disable_intens(u64 mask)
747{
748 write_pmintenclr(mask);
749 isb();
750 /* Clear the overflow flag in case an interrupt is pending. */
751 write_pmovsclr(mask);
752 isb();
753}
754
755static void armv8pmu_disable_event_irq(struct perf_event *event)
756{
757 armv8pmu_disable_intens(BIT(event->hw.idx));
758}
759
760static u64 armv8pmu_getreset_flags(void)
761{
762 u64 value;
763
764 /* Read */
765 value = read_pmovsclr();
766
767 /* Write to clear flags */
768 value &= ARMV8_PMU_OVERFLOWED_MASK;
769 write_pmovsclr(value);
770
771 return value;
772}
773
774static void update_pmuserenr(u64 val)
775{
776 lockdep_assert_irqs_disabled();
777
778 /*
779 * The current PMUSERENR_EL0 value might be the value for the guest.
780 * If that's the case, have KVM keep tracking of the register value
781 * for the host EL0 so that KVM can restore it before returning to
782 * the host EL0. Otherwise, update the register now.
783 */
784 if (kvm_set_pmuserenr(val))
785 return;
786
787 write_pmuserenr(val);
788}
789
790static void armv8pmu_disable_user_access(void)
791{
792 update_pmuserenr(0);
793}
794
795static void armv8pmu_enable_user_access(struct arm_pmu *cpu_pmu)
796{
797 int i;
798 struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);
799
800 if (is_pmuv3p9(cpu_pmu->pmuver)) {
801 u64 mask = 0;
802 for_each_set_bit(i, cpuc->used_mask, ARMPMU_MAX_HWEVENTS) {
803 if (armv8pmu_event_has_user_read(cpuc->events[i]))
804 mask |= BIT(i);
805 }
806 write_pmuacr(mask);
807 } else {
808 /* Clear any unused counters to avoid leaking their contents */
809 for_each_andnot_bit(i, cpu_pmu->cntr_mask, cpuc->used_mask,
810 ARMPMU_MAX_HWEVENTS) {
811 if (i == ARMV8_PMU_CYCLE_IDX)
812 write_pmccntr(0);
813 else if (i == ARMV8_PMU_INSTR_IDX)
814 write_pmicntr(0);
815 else
816 armv8pmu_write_evcntr(i, 0);
817 }
818 }
819
820 update_pmuserenr(ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_UEN);
821}
822
823static void armv8pmu_enable_event(struct perf_event *event)
824{
825 armv8pmu_write_event_type(event);
826 armv8pmu_enable_event_irq(event);
827 armv8pmu_enable_event_counter(event);
828}
829
830static void armv8pmu_disable_event(struct perf_event *event)
831{
832 armv8pmu_disable_event_counter(event);
833 armv8pmu_disable_event_irq(event);
834}
835
836static void armv8pmu_start(struct arm_pmu *cpu_pmu)
837{
838 struct perf_event_context *ctx;
839 struct pmu_hw_events *hw_events = this_cpu_ptr(cpu_pmu->hw_events);
840 int nr_user = 0;
841
842 ctx = perf_cpu_task_ctx();
843 if (ctx)
844 nr_user = ctx->nr_user;
845
846 if (sysctl_perf_user_access && nr_user)
847 armv8pmu_enable_user_access(cpu_pmu);
848 else
849 armv8pmu_disable_user_access();
850
851 kvm_vcpu_pmu_resync_el0();
852
853 if (hw_events->branch_users)
854 brbe_enable(cpu_pmu);
855
856 /* Enable all counters */
857 armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMU_PMCR_E);
858}
859
860static void armv8pmu_stop(struct arm_pmu *cpu_pmu)
861{
862 struct pmu_hw_events *hw_events = this_cpu_ptr(cpu_pmu->hw_events);
863
864 if (hw_events->branch_users)
865 brbe_disable();
866
867 /* Disable all counters */
868 armv8pmu_pmcr_write(armv8pmu_pmcr_read() & ~ARMV8_PMU_PMCR_E);
869}
870
871static void read_branch_records(struct pmu_hw_events *cpuc,
872 struct perf_event *event,
873 struct perf_sample_data *data)
874{
875 struct perf_branch_stack *branch_stack = cpuc->branch_stack;
876
877 brbe_read_filtered_entries(branch_stack, event);
878 perf_sample_save_brstack(data, event, branch_stack, NULL);
879}
880
881static irqreturn_t armv8pmu_handle_irq(struct arm_pmu *cpu_pmu)
882{
883 u64 pmovsr;
884 struct perf_sample_data data;
885 struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);
886 struct pt_regs *regs;
887 int idx;
888
889 /*
890 * Get and reset the IRQ flags
891 */
892 pmovsr = armv8pmu_getreset_flags();
893
894 /*
895 * Did an overflow occur?
896 */
897 if (!armv8pmu_has_overflowed(pmovsr))
898 return IRQ_NONE;
899
900 /*
901 * Handle the counter(s) overflow(s)
902 */
903 regs = get_irq_regs();
904
905 /*
906 * Stop the PMU while processing the counter overflows
907 * to prevent skews in group events.
908 */
909 armv8pmu_stop(cpu_pmu);
910 for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMPMU_MAX_HWEVENTS) {
911 struct perf_event *event = cpuc->events[idx];
912 struct hw_perf_event *hwc;
913
914 /* Ignore if we don't have an event. */
915 if (!event)
916 continue;
917
918 /*
919 * We have a single interrupt for all counters. Check that
920 * each counter has overflowed before we process it.
921 */
922 if (!armv8pmu_counter_has_overflowed(pmovsr, idx))
923 continue;
924
925 hwc = &event->hw;
926 armpmu_event_update(event);
927 perf_sample_data_init(&data, 0, hwc->last_period);
928 if (!armpmu_event_set_period(event))
929 continue;
930
931 if (has_branch_stack(event))
932 read_branch_records(cpuc, event, &data);
933
934 /*
935 * Perf event overflow will queue the processing of the event as
936 * an irq_work which will be taken care of in the handling of
937 * IPI_IRQ_WORK.
938 */
939 perf_event_overflow(event, &data, regs);
940 }
941 armv8pmu_start(cpu_pmu);
942
943 return IRQ_HANDLED;
944}
945
946static int armv8pmu_get_single_idx(struct pmu_hw_events *cpuc,
947 struct arm_pmu *cpu_pmu)
948{
949 int idx;
950
951 for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMV8_PMU_MAX_GENERAL_COUNTERS) {
952 if (!test_and_set_bit(idx, cpuc->used_mask))
953 return idx;
954 }
955 return -EAGAIN;
956}
957
958static int armv8pmu_get_chain_idx(struct pmu_hw_events *cpuc,
959 struct arm_pmu *cpu_pmu)
960{
961 int idx;
962
963 /*
964 * Chaining requires two consecutive event counters, where
965 * the lower idx must be even.
966 */
967 for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMV8_PMU_MAX_GENERAL_COUNTERS) {
968 if (!(idx & 0x1))
969 continue;
970 if (!test_and_set_bit(idx, cpuc->used_mask)) {
971 /* Check if the preceding even counter is available */
972 if (!test_and_set_bit(idx - 1, cpuc->used_mask))
973 return idx;
974 /* Release the Odd counter */
975 clear_bit(idx, cpuc->used_mask);
976 }
977 }
978 return -EAGAIN;
979}
980
981static bool armv8pmu_can_use_pmccntr(struct pmu_hw_events *cpuc,
982 struct perf_event *event)
983{
984 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
985 struct hw_perf_event *hwc = &event->hw;
986 unsigned long evtype = hwc->config_base & ARMV8_PMU_EVTYPE_EVENT;
987
988 if (evtype != ARMV8_PMUV3_PERFCTR_CPU_CYCLES)
989 return false;
990
991 /*
992 * A CPU_CYCLES event with threshold counting cannot use PMCCNTR_EL0
993 * since it lacks threshold support.
994 */
995 if (armv8pmu_event_get_threshold(&event->attr))
996 return false;
997
998 /*
999 * PMCCNTR_EL0 is not affected by BRBE controls like BRBCR_ELx.FZP.
1000 * So don't use it for branch events.
1001 */
1002 if (has_branch_stack(event))
1003 return false;
1004
1005 /*
1006 * The PMCCNTR_EL0 increments from the processor clock rather than
1007 * the PE clock (ARM DDI0487 L.b D13.1.3) which means it'll continue
1008 * counting on a WFI PE if one of its SMT sibling is not idle on a
1009 * multi-threaded implementation. So don't use it on SMT cores.
1010 */
1011 if (cpu_pmu->has_smt)
1012 return false;
1013
1014 return true;
1015}
1016
1017static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc,
1018 struct perf_event *event)
1019{
1020 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
1021 struct hw_perf_event *hwc = &event->hw;
1022 unsigned long evtype = hwc->config_base & ARMV8_PMU_EVTYPE_EVENT;
1023
1024 /* Always prefer to place a cycle counter into the cycle counter. */
1025 if (armv8pmu_can_use_pmccntr(cpuc, event)) {
1026 if (!test_and_set_bit(ARMV8_PMU_CYCLE_IDX, cpuc->used_mask))
1027 return ARMV8_PMU_CYCLE_IDX;
1028 else if (armv8pmu_event_is_64bit(event) &&
1029 armv8pmu_event_want_user_access(event) &&
1030 !armv8pmu_has_long_event(cpu_pmu))
1031 return -EAGAIN;
1032 }
1033
1034 /*
1035 * Always prefer to place a instruction counter into the instruction counter,
1036 * but don't expose the instruction counter to userspace access as userspace
1037 * may not know how to handle it.
1038 */
1039 if ((evtype == ARMV8_PMUV3_PERFCTR_INST_RETIRED) &&
1040 !armv8pmu_event_get_threshold(&event->attr) &&
1041 test_bit(ARMV8_PMU_INSTR_IDX, cpu_pmu->cntr_mask) &&
1042 !armv8pmu_event_want_user_access(event)) {
1043 if (!test_and_set_bit(ARMV8_PMU_INSTR_IDX, cpuc->used_mask))
1044 return ARMV8_PMU_INSTR_IDX;
1045 }
1046
1047 /*
1048 * Otherwise use events counters
1049 */
1050 if (armv8pmu_event_is_chained(event))
1051 return armv8pmu_get_chain_idx(cpuc, cpu_pmu);
1052 else
1053 return armv8pmu_get_single_idx(cpuc, cpu_pmu);
1054}
1055
1056static void armv8pmu_clear_event_idx(struct pmu_hw_events *cpuc,
1057 struct perf_event *event)
1058{
1059 int idx = event->hw.idx;
1060
1061 clear_bit(idx, cpuc->used_mask);
1062 if (armv8pmu_event_is_chained(event))
1063 clear_bit(idx - 1, cpuc->used_mask);
1064}
1065
1066static int armv8pmu_user_event_idx(struct perf_event *event)
1067{
1068 if (!sysctl_perf_user_access || !armv8pmu_event_has_user_read(event))
1069 return 0;
1070
1071 return event->hw.idx + 1;
1072}
1073
1074static void armv8pmu_sched_task(struct perf_event_pmu_context *pmu_ctx,
1075 struct task_struct *task, bool sched_in)
1076{
1077 struct arm_pmu *armpmu = to_arm_pmu(pmu_ctx->pmu);
1078 struct pmu_hw_events *hw_events = this_cpu_ptr(armpmu->hw_events);
1079
1080 if (!hw_events->branch_users)
1081 return;
1082
1083 if (sched_in)
1084 brbe_invalidate();
1085}
1086
1087/*
1088 * Add an event filter to a given event.
1089 */
1090static int armv8pmu_set_event_filter(struct hw_perf_event *event,
1091 struct perf_event_attr *attr)
1092{
1093 unsigned long config_base = 0;
1094 struct perf_event *perf_event = container_of(attr, struct perf_event,
1095 attr);
1096 struct arm_pmu *cpu_pmu = to_arm_pmu(perf_event->pmu);
1097 u32 th;
1098
1099 if (attr->exclude_idle) {
1100 pr_debug("ARM performance counters do not support mode exclusion\n");
1101 return -EOPNOTSUPP;
1102 }
1103
1104 if (has_branch_stack(perf_event)) {
1105 if (!brbe_num_branch_records(cpu_pmu) || !brbe_branch_attr_valid(perf_event))
1106 return -EOPNOTSUPP;
1107
1108 perf_event->attach_state |= PERF_ATTACH_SCHED_CB;
1109 }
1110
1111 /*
1112 * If we're running in hyp mode, then we *are* the hypervisor.
1113 * Therefore we ignore exclude_hv in this configuration, since
1114 * there's no hypervisor to sample anyway. This is consistent
1115 * with other architectures (x86 and Power).
1116 */
1117 if (is_kernel_in_hyp_mode()) {
1118 if (!attr->exclude_kernel && !attr->exclude_host)
1119 config_base |= ARMV8_PMU_INCLUDE_EL2;
1120 if (attr->exclude_guest)
1121 config_base |= ARMV8_PMU_EXCLUDE_EL1;
1122 if (attr->exclude_host)
1123 config_base |= ARMV8_PMU_EXCLUDE_EL0;
1124 } else {
1125 if (!attr->exclude_hv && !attr->exclude_host)
1126 config_base |= ARMV8_PMU_INCLUDE_EL2;
1127 }
1128
1129 /*
1130 * Filter out !VHE kernels and guest kernels
1131 */
1132 if (attr->exclude_kernel)
1133 config_base |= ARMV8_PMU_EXCLUDE_EL1;
1134
1135 if (attr->exclude_user)
1136 config_base |= ARMV8_PMU_EXCLUDE_EL0;
1137
1138 /*
1139 * If FEAT_PMUv3_TH isn't implemented, then THWIDTH (threshold_max) will
1140 * be 0 and will also trigger this check, preventing it from being used.
1141 */
1142 th = armv8pmu_event_get_threshold(attr);
1143 if (th > threshold_max(cpu_pmu)) {
1144 pr_debug("PMU event threshold exceeds max value\n");
1145 return -EINVAL;
1146 }
1147
1148 if (th) {
1149 config_base |= FIELD_PREP(ARMV8_PMU_EVTYPE_TH, th);
1150 config_base |= FIELD_PREP(ARMV8_PMU_EVTYPE_TC,
1151 armv8pmu_event_threshold_control(attr));
1152 }
1153
1154 /*
1155 * Install the filter into config_base as this is used to
1156 * construct the event type.
1157 */
1158 event->config_base = config_base;
1159
1160 return 0;
1161}
1162
1163static void armv8pmu_reset(void *info)
1164{
1165 struct arm_pmu *cpu_pmu = (struct arm_pmu *)info;
1166 u64 pmcr, mask;
1167
1168 bitmap_to_arr64(&mask, cpu_pmu->cntr_mask, ARMPMU_MAX_HWEVENTS);
1169
1170 /* The counter and interrupt enable registers are unknown at reset. */
1171 armv8pmu_disable_counter(mask);
1172 armv8pmu_disable_intens(mask);
1173
1174 /* Clear the counters we flip at guest entry/exit */
1175 kvm_clr_pmu_events(mask);
1176
1177 if (brbe_num_branch_records(cpu_pmu)) {
1178 brbe_disable();
1179 brbe_invalidate();
1180 }
1181
1182 /*
1183 * Initialize & Reset PMNC. Request overflow interrupt for
1184 * 64 bit cycle counter but cheat in armv8pmu_write_counter().
1185 */
1186 pmcr = ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C | ARMV8_PMU_PMCR_LC;
1187
1188 /* Enable long event counter support where available */
1189 if (armv8pmu_has_long_event(cpu_pmu))
1190 pmcr |= ARMV8_PMU_PMCR_LP;
1191
1192 armv8pmu_pmcr_write(pmcr);
1193}
1194
1195static int __armv8_pmuv3_map_event_id(struct arm_pmu *armpmu,
1196 struct perf_event *event)
1197{
1198 if (event->attr.type == PERF_TYPE_HARDWARE &&
1199 event->attr.config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) {
1200
1201 if (test_bit(ARMV8_PMUV3_PERFCTR_BR_RETIRED,
1202 armpmu->pmceid_bitmap))
1203 return ARMV8_PMUV3_PERFCTR_BR_RETIRED;
1204
1205 if (test_bit(ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED,
1206 armpmu->pmceid_bitmap))
1207 return ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED;
1208
1209 return HW_OP_UNSUPPORTED;
1210 }
1211
1212 return armpmu_map_event(event, &armv8_pmuv3_perf_map,
1213 &armv8_pmuv3_perf_cache_map,
1214 ARMV8_PMU_EVTYPE_EVENT);
1215}
1216
1217static int __armv8_pmuv3_map_event(struct perf_event *event,
1218 const unsigned (*extra_event_map)
1219 [PERF_COUNT_HW_MAX],
1220 const unsigned (*extra_cache_map)
1221 [PERF_COUNT_HW_CACHE_MAX]
1222 [PERF_COUNT_HW_CACHE_OP_MAX]
1223 [PERF_COUNT_HW_CACHE_RESULT_MAX])
1224{
1225 int hw_event_id;
1226 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
1227
1228 hw_event_id = __armv8_pmuv3_map_event_id(armpmu, event);
1229
1230 /*
1231 * CHAIN events only work when paired with an adjacent counter, and it
1232 * never makes sense for a user to open one in isolation, as they'll be
1233 * rotated arbitrarily.
1234 */
1235 if (hw_event_id == ARMV8_PMUV3_PERFCTR_CHAIN)
1236 return -EINVAL;
1237
1238 if (armv8pmu_event_is_64bit(event))
1239 event->hw.flags |= ARMPMU_EVT_64BIT;
1240
1241 /*
1242 * User events must be allocated into a single counter, and so
1243 * must not be chained.
1244 *
1245 * Most 64-bit events require long counter support, but 64-bit
1246 * CPU_CYCLES events can be placed into the dedicated cycle
1247 * counter when this is free.
1248 */
1249 if (armv8pmu_event_want_user_access(event)) {
1250 if (!(event->attach_state & PERF_ATTACH_TASK))
1251 return -EINVAL;
1252 if (armv8pmu_event_is_64bit(event) &&
1253 (hw_event_id != ARMV8_PMUV3_PERFCTR_CPU_CYCLES) &&
1254 !armv8pmu_has_long_event(armpmu))
1255 return -EOPNOTSUPP;
1256
1257 event->hw.flags |= PERF_EVENT_FLAG_USER_READ_CNT;
1258 }
1259
1260 /* Only expose micro/arch events supported by this PMU */
1261 if ((hw_event_id > 0) && (hw_event_id < ARMV8_PMUV3_MAX_COMMON_EVENTS)
1262 && test_bit(hw_event_id, armpmu->pmceid_bitmap)) {
1263 return hw_event_id;
1264 }
1265
1266 return armpmu_map_event(event, extra_event_map, extra_cache_map,
1267 ARMV8_PMU_EVTYPE_EVENT);
1268}
1269
1270static int armv8_pmuv3_map_event(struct perf_event *event)
1271{
1272 return __armv8_pmuv3_map_event(event, NULL, NULL);
1273}
1274
1275static int armv8_a53_map_event(struct perf_event *event)
1276{
1277 return __armv8_pmuv3_map_event(event, NULL, &armv8_a53_perf_cache_map);
1278}
1279
1280static int armv8_a57_map_event(struct perf_event *event)
1281{
1282 return __armv8_pmuv3_map_event(event, NULL, &armv8_a57_perf_cache_map);
1283}
1284
1285static int armv8_a73_map_event(struct perf_event *event)
1286{
1287 return __armv8_pmuv3_map_event(event, NULL, &armv8_a73_perf_cache_map);
1288}
1289
1290static int armv8_thunder_map_event(struct perf_event *event)
1291{
1292 return __armv8_pmuv3_map_event(event, NULL,
1293 &armv8_thunder_perf_cache_map);
1294}
1295
1296static int armv8_vulcan_map_event(struct perf_event *event)
1297{
1298 return __armv8_pmuv3_map_event(event, NULL,
1299 &armv8_vulcan_perf_cache_map);
1300}
1301
1302struct armv8pmu_probe_info {
1303 struct arm_pmu *pmu;
1304 bool present;
1305};
1306
1307static void __armv8pmu_probe_pmu(void *info)
1308{
1309 struct armv8pmu_probe_info *probe = info;
1310 struct arm_pmu *cpu_pmu = probe->pmu;
1311 u64 pmceid_raw[2];
1312 u32 pmceid[2];
1313 int pmuver;
1314
1315 pmuver = read_pmuver();
1316 if (!pmuv3_implemented(pmuver))
1317 return;
1318
1319 cpu_pmu->pmuver = pmuver;
1320 probe->present = true;
1321
1322 /* Read the nb of CNTx counters supported from PMNC */
1323 bitmap_set(cpu_pmu->cntr_mask,
1324 0, FIELD_GET(ARMV8_PMU_PMCR_N, armv8pmu_pmcr_read()));
1325
1326 /* Add the CPU cycles counter */
1327 set_bit(ARMV8_PMU_CYCLE_IDX, cpu_pmu->cntr_mask);
1328
1329 /* Add the CPU instructions counter */
1330 if (pmuv3_has_icntr())
1331 set_bit(ARMV8_PMU_INSTR_IDX, cpu_pmu->cntr_mask);
1332
1333 pmceid[0] = pmceid_raw[0] = read_pmceid0();
1334 pmceid[1] = pmceid_raw[1] = read_pmceid1();
1335
1336 bitmap_from_arr32(cpu_pmu->pmceid_bitmap,
1337 pmceid, ARMV8_PMUV3_MAX_COMMON_EVENTS);
1338
1339 pmceid[0] = pmceid_raw[0] >> 32;
1340 pmceid[1] = pmceid_raw[1] >> 32;
1341
1342 bitmap_from_arr32(cpu_pmu->pmceid_ext_bitmap,
1343 pmceid, ARMV8_PMUV3_MAX_COMMON_EVENTS);
1344
1345 /* store PMMIR register for sysfs */
1346 if (is_pmuv3p4(pmuver))
1347 cpu_pmu->reg_pmmir = read_pmmir();
1348 else
1349 cpu_pmu->reg_pmmir = 0;
1350
1351 brbe_probe(cpu_pmu);
1352}
1353
1354static int branch_records_alloc(struct arm_pmu *armpmu)
1355{
1356 size_t size = struct_size_t(struct perf_branch_stack, entries,
1357 brbe_num_branch_records(armpmu));
1358 int cpu;
1359
1360 for_each_cpu(cpu, &armpmu->supported_cpus) {
1361 struct pmu_hw_events *events_cpu;
1362
1363 events_cpu = per_cpu_ptr(armpmu->hw_events, cpu);
1364 events_cpu->branch_stack = kmalloc(size, GFP_KERNEL);
1365 if (!events_cpu->branch_stack)
1366 return -ENOMEM;
1367 }
1368 return 0;
1369}
1370
1371static int armv8pmu_probe_pmu(struct arm_pmu *cpu_pmu)
1372{
1373 struct armv8pmu_probe_info probe = {
1374 .pmu = cpu_pmu,
1375 .present = false,
1376 };
1377 int ret;
1378
1379 ret = smp_call_function_any(&cpu_pmu->supported_cpus,
1380 __armv8pmu_probe_pmu,
1381 &probe, 1);
1382 if (ret)
1383 return ret;
1384
1385 if (!probe.present)
1386 return -ENODEV;
1387
1388 if (brbe_num_branch_records(cpu_pmu)) {
1389 ret = branch_records_alloc(cpu_pmu);
1390 if (ret)
1391 return ret;
1392 }
1393 return 0;
1394}
1395
1396static void armv8pmu_disable_user_access_ipi(void *unused)
1397{
1398 armv8pmu_disable_user_access();
1399}
1400
1401static int armv8pmu_proc_user_access_handler(const struct ctl_table *table, int write,
1402 void *buffer, size_t *lenp, loff_t *ppos)
1403{
1404 int ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos);
1405 if (ret || !write || sysctl_perf_user_access)
1406 return ret;
1407
1408 on_each_cpu(armv8pmu_disable_user_access_ipi, NULL, 1);
1409 return 0;
1410}
1411
1412static const struct ctl_table armv8_pmu_sysctl_table[] = {
1413 {
1414 .procname = "perf_user_access",
1415 .data = &sysctl_perf_user_access,
1416 .maxlen = sizeof(unsigned int),
1417 .mode = 0644,
1418 .proc_handler = armv8pmu_proc_user_access_handler,
1419 .extra1 = SYSCTL_ZERO,
1420 .extra2 = SYSCTL_ONE,
1421 },
1422};
1423
1424static void armv8_pmu_register_sysctl_table(void)
1425{
1426 static u32 tbl_registered = 0;
1427
1428 if (!cmpxchg_relaxed(&tbl_registered, 0, 1))
1429 register_sysctl("kernel", armv8_pmu_sysctl_table);
1430}
1431
1432static int armv8_pmu_init(struct arm_pmu *cpu_pmu, char *name,
1433 int (*map_event)(struct perf_event *event))
1434{
1435 int ret = armv8pmu_probe_pmu(cpu_pmu);
1436 if (ret)
1437 return ret;
1438
1439 cpu_pmu->handle_irq = armv8pmu_handle_irq;
1440 cpu_pmu->enable = armv8pmu_enable_event;
1441 cpu_pmu->disable = armv8pmu_disable_event;
1442 cpu_pmu->read_counter = armv8pmu_read_counter;
1443 cpu_pmu->write_counter = armv8pmu_write_counter;
1444 cpu_pmu->get_event_idx = armv8pmu_get_event_idx;
1445 cpu_pmu->clear_event_idx = armv8pmu_clear_event_idx;
1446 cpu_pmu->start = armv8pmu_start;
1447 cpu_pmu->stop = armv8pmu_stop;
1448 cpu_pmu->reset = armv8pmu_reset;
1449 cpu_pmu->set_event_filter = armv8pmu_set_event_filter;
1450
1451 cpu_pmu->pmu.event_idx = armv8pmu_user_event_idx;
1452 if (brbe_num_branch_records(cpu_pmu))
1453 cpu_pmu->pmu.sched_task = armv8pmu_sched_task;
1454
1455 cpu_pmu->name = name;
1456 cpu_pmu->map_event = map_event;
1457 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = &armv8_pmuv3_events_attr_group;
1458 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = &armv8_pmuv3_format_attr_group;
1459 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_CAPS] = &armv8_pmuv3_caps_attr_group;
1460 armv8_pmu_register_sysctl_table();
1461 return 0;
1462}
1463
1464#define PMUV3_INIT_SIMPLE(name) \
1465static int name##_pmu_init(struct arm_pmu *cpu_pmu) \
1466{ \
1467 return armv8_pmu_init(cpu_pmu, #name, armv8_pmuv3_map_event); \
1468}
1469
1470#define PMUV3_INIT_MAP_EVENT(name, map_event) \
1471static int name##_pmu_init(struct arm_pmu *cpu_pmu) \
1472{ \
1473 return armv8_pmu_init(cpu_pmu, #name, map_event); \
1474}
1475
1476PMUV3_INIT_SIMPLE(armv8_pmuv3)
1477
1478PMUV3_INIT_SIMPLE(armv8_c1_nano)
1479PMUV3_INIT_SIMPLE(armv8_c1_premium)
1480PMUV3_INIT_SIMPLE(armv8_c1_pro)
1481PMUV3_INIT_SIMPLE(armv8_c1_ultra)
1482PMUV3_INIT_SIMPLE(armv8_cortex_a34)
1483PMUV3_INIT_SIMPLE(armv8_cortex_a55)
1484PMUV3_INIT_SIMPLE(armv8_cortex_a65)
1485PMUV3_INIT_SIMPLE(armv8_cortex_a75)
1486PMUV3_INIT_SIMPLE(armv8_cortex_a76)
1487PMUV3_INIT_SIMPLE(armv8_cortex_a77)
1488PMUV3_INIT_SIMPLE(armv8_cortex_a78)
1489PMUV3_INIT_SIMPLE(armv9_cortex_a320)
1490PMUV3_INIT_SIMPLE(armv9_cortex_a510)
1491PMUV3_INIT_SIMPLE(armv9_cortex_a520)
1492PMUV3_INIT_SIMPLE(armv9_cortex_a520ae)
1493PMUV3_INIT_SIMPLE(armv9_cortex_a710)
1494PMUV3_INIT_SIMPLE(armv9_cortex_a715)
1495PMUV3_INIT_SIMPLE(armv9_cortex_a720)
1496PMUV3_INIT_SIMPLE(armv9_cortex_a720ae)
1497PMUV3_INIT_SIMPLE(armv9_cortex_a725)
1498PMUV3_INIT_SIMPLE(armv8_cortex_x1)
1499PMUV3_INIT_SIMPLE(armv9_cortex_x2)
1500PMUV3_INIT_SIMPLE(armv9_cortex_x3)
1501PMUV3_INIT_SIMPLE(armv9_cortex_x4)
1502PMUV3_INIT_SIMPLE(armv9_cortex_x925)
1503PMUV3_INIT_SIMPLE(armv8_neoverse_e1)
1504PMUV3_INIT_SIMPLE(armv8_neoverse_n1)
1505PMUV3_INIT_SIMPLE(armv9_neoverse_n2)
1506PMUV3_INIT_SIMPLE(armv9_neoverse_n3)
1507PMUV3_INIT_SIMPLE(armv8_neoverse_v1)
1508PMUV3_INIT_SIMPLE(armv8_neoverse_v2)
1509PMUV3_INIT_SIMPLE(armv8_neoverse_v3)
1510PMUV3_INIT_SIMPLE(armv8_neoverse_v3ae)
1511PMUV3_INIT_SIMPLE(armv8_rainier)
1512
1513PMUV3_INIT_SIMPLE(armv8_nvidia_carmel)
1514PMUV3_INIT_SIMPLE(armv8_nvidia_denver)
1515
1516PMUV3_INIT_SIMPLE(armv8_samsung_mongoose)
1517
1518PMUV3_INIT_MAP_EVENT(armv8_cortex_a35, armv8_a53_map_event)
1519PMUV3_INIT_MAP_EVENT(armv8_cortex_a53, armv8_a53_map_event)
1520PMUV3_INIT_MAP_EVENT(armv8_cortex_a57, armv8_a57_map_event)
1521PMUV3_INIT_MAP_EVENT(armv8_cortex_a72, armv8_a57_map_event)
1522PMUV3_INIT_MAP_EVENT(armv8_cortex_a73, armv8_a73_map_event)
1523PMUV3_INIT_MAP_EVENT(armv8_cavium_thunder, armv8_thunder_map_event)
1524PMUV3_INIT_MAP_EVENT(armv8_brcm_vulcan, armv8_vulcan_map_event)
1525
1526static const struct of_device_id armv8_pmu_of_device_ids[] = {
1527 {.compatible = "arm,armv8-pmuv3", .data = armv8_pmuv3_pmu_init},
1528 {.compatible = "arm,c1-nano-pmu", .data = armv8_c1_nano_pmu_init},
1529 {.compatible = "arm,c1-premium-pmu", .data = armv8_c1_premium_pmu_init},
1530 {.compatible = "arm,c1-pro-pmu", .data = armv8_c1_pro_pmu_init},
1531 {.compatible = "arm,c1-ultra-pmu", .data = armv8_c1_ultra_pmu_init},
1532 {.compatible = "arm,cortex-a34-pmu", .data = armv8_cortex_a34_pmu_init},
1533 {.compatible = "arm,cortex-a35-pmu", .data = armv8_cortex_a35_pmu_init},
1534 {.compatible = "arm,cortex-a53-pmu", .data = armv8_cortex_a53_pmu_init},
1535 {.compatible = "arm,cortex-a55-pmu", .data = armv8_cortex_a55_pmu_init},
1536 {.compatible = "arm,cortex-a57-pmu", .data = armv8_cortex_a57_pmu_init},
1537 {.compatible = "arm,cortex-a65-pmu", .data = armv8_cortex_a65_pmu_init},
1538 {.compatible = "arm,cortex-a72-pmu", .data = armv8_cortex_a72_pmu_init},
1539 {.compatible = "arm,cortex-a73-pmu", .data = armv8_cortex_a73_pmu_init},
1540 {.compatible = "arm,cortex-a75-pmu", .data = armv8_cortex_a75_pmu_init},
1541 {.compatible = "arm,cortex-a76-pmu", .data = armv8_cortex_a76_pmu_init},
1542 {.compatible = "arm,cortex-a77-pmu", .data = armv8_cortex_a77_pmu_init},
1543 {.compatible = "arm,cortex-a78-pmu", .data = armv8_cortex_a78_pmu_init},
1544 {.compatible = "arm,cortex-a320-pmu", .data = armv9_cortex_a320_pmu_init},
1545 {.compatible = "arm,cortex-a510-pmu", .data = armv9_cortex_a510_pmu_init},
1546 {.compatible = "arm,cortex-a520-pmu", .data = armv9_cortex_a520_pmu_init},
1547 {.compatible = "arm,cortex-a520ae-pmu", .data = armv9_cortex_a520ae_pmu_init},
1548 {.compatible = "arm,cortex-a710-pmu", .data = armv9_cortex_a710_pmu_init},
1549 {.compatible = "arm,cortex-a715-pmu", .data = armv9_cortex_a715_pmu_init},
1550 {.compatible = "arm,cortex-a720-pmu", .data = armv9_cortex_a720_pmu_init},
1551 {.compatible = "arm,cortex-a720ae-pmu", .data = armv9_cortex_a720ae_pmu_init},
1552 {.compatible = "arm,cortex-a725-pmu", .data = armv9_cortex_a725_pmu_init},
1553 {.compatible = "arm,cortex-x1-pmu", .data = armv8_cortex_x1_pmu_init},
1554 {.compatible = "arm,cortex-x2-pmu", .data = armv9_cortex_x2_pmu_init},
1555 {.compatible = "arm,cortex-x3-pmu", .data = armv9_cortex_x3_pmu_init},
1556 {.compatible = "arm,cortex-x4-pmu", .data = armv9_cortex_x4_pmu_init},
1557 {.compatible = "arm,cortex-x925-pmu", .data = armv9_cortex_x925_pmu_init},
1558 {.compatible = "arm,neoverse-e1-pmu", .data = armv8_neoverse_e1_pmu_init},
1559 {.compatible = "arm,neoverse-n1-pmu", .data = armv8_neoverse_n1_pmu_init},
1560 {.compatible = "arm,neoverse-n2-pmu", .data = armv9_neoverse_n2_pmu_init},
1561 {.compatible = "arm,neoverse-n3-pmu", .data = armv9_neoverse_n3_pmu_init},
1562 {.compatible = "arm,neoverse-v1-pmu", .data = armv8_neoverse_v1_pmu_init},
1563 {.compatible = "arm,neoverse-v2-pmu", .data = armv8_neoverse_v2_pmu_init},
1564 {.compatible = "arm,neoverse-v3-pmu", .data = armv8_neoverse_v3_pmu_init},
1565 {.compatible = "arm,neoverse-v3ae-pmu", .data = armv8_neoverse_v3ae_pmu_init},
1566 {.compatible = "arm,rainier-pmu", .data = armv8_rainier_pmu_init},
1567 {.compatible = "cavium,thunder-pmu", .data = armv8_cavium_thunder_pmu_init},
1568 {.compatible = "brcm,vulcan-pmu", .data = armv8_brcm_vulcan_pmu_init},
1569 {.compatible = "nvidia,carmel-pmu", .data = armv8_nvidia_carmel_pmu_init},
1570 {.compatible = "nvidia,denver-pmu", .data = armv8_nvidia_denver_pmu_init},
1571 {.compatible = "samsung,mongoose-pmu", .data = armv8_samsung_mongoose_pmu_init},
1572 {},
1573};
1574
1575static int armv8_pmu_device_probe(struct platform_device *pdev)
1576{
1577 return arm_pmu_device_probe(pdev, armv8_pmu_of_device_ids, NULL);
1578}
1579
1580static struct platform_driver armv8_pmu_driver = {
1581 .driver = {
1582 .name = ARMV8_PMU_PDEV_NAME,
1583 .of_match_table = armv8_pmu_of_device_ids,
1584 .suppress_bind_attrs = true,
1585 },
1586 .probe = armv8_pmu_device_probe,
1587};
1588
1589static int __init armv8_pmu_driver_init(void)
1590{
1591 int ret;
1592
1593 if (acpi_disabled)
1594 ret = platform_driver_register(&armv8_pmu_driver);
1595 else
1596 ret = arm_pmu_acpi_probe(armv8_pmuv3_pmu_init);
1597
1598 if (!ret)
1599 lockup_detector_retry_init();
1600
1601 return ret;
1602}
1603device_initcall(armv8_pmu_driver_init)
1604
1605void arch_perf_update_userpage(struct perf_event *event,
1606 struct perf_event_mmap_page *userpg, u64 now)
1607{
1608 struct clock_read_data *rd;
1609 unsigned int seq;
1610 u64 ns;
1611
1612 userpg->cap_user_time = 0;
1613 userpg->cap_user_time_zero = 0;
1614 userpg->cap_user_time_short = 0;
1615 userpg->cap_user_rdpmc = armv8pmu_event_has_user_read(event);
1616
1617 if (userpg->cap_user_rdpmc) {
1618 if (event->hw.flags & ARMPMU_EVT_64BIT)
1619 userpg->pmc_width = 64;
1620 else
1621 userpg->pmc_width = 32;
1622 }
1623
1624 do {
1625 rd = sched_clock_read_begin(&seq);
1626
1627 if (rd->read_sched_clock != arch_timer_read_counter)
1628 return;
1629
1630 userpg->time_mult = rd->mult;
1631 userpg->time_shift = rd->shift;
1632 userpg->time_zero = rd->epoch_ns;
1633 userpg->time_cycles = rd->epoch_cyc;
1634 userpg->time_mask = rd->sched_clock_mask;
1635
1636 /*
1637 * Subtract the cycle base, such that software that
1638 * doesn't know about cap_user_time_short still 'works'
1639 * assuming no wraps.
1640 */
1641 ns = mul_u64_u32_shr(rd->epoch_cyc, rd->mult, rd->shift);
1642 userpg->time_zero -= ns;
1643
1644 } while (sched_clock_read_retry(seq));
1645
1646 userpg->time_offset = userpg->time_zero - now;
1647
1648 /*
1649 * time_shift is not expected to be greater than 31 due to
1650 * the original published conversion algorithm shifting a
1651 * 32-bit value (now specifies a 64-bit value) - refer
1652 * perf_event_mmap_page documentation in perf_event.h.
1653 */
1654 if (userpg->time_shift == 32) {
1655 userpg->time_shift = 31;
1656 userpg->time_mult >>= 1;
1657 }
1658
1659 /*
1660 * Internal timekeeping for enabled/running/stopped times
1661 * is always computed with the sched_clock.
1662 */
1663 userpg->cap_user_time = 1;
1664 userpg->cap_user_time_zero = 1;
1665 userpg->cap_user_time_short = 1;
1666}