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1/* SPDX-License-Identifier: GPL-2.0-only */
2
3#ifndef __SOC_MEDIATEK_MT8167_PM_DOMAINS_H
4#define __SOC_MEDIATEK_MT8167_PM_DOMAINS_H
5
6#include "mtk-pm-domains.h"
7#include <dt-bindings/power/mt8167-power.h>
8
9#define MT8167_PWR_STATUS_MFG_2D BIT(24)
10#define MT8167_PWR_STATUS_MFG_ASYNC BIT(25)
11
12/*
13 * MT8167 power domain support
14 */
15static enum scpsys_bus_prot_block scpsys_bus_prot_blocks_mt8167[] = {
16 BUS_PROT_BLOCK_INFRA
17};
18
19static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = {
20 [MT8167_POWER_DOMAIN_MM] = {
21 .name = "mm",
22 .sta_mask = PWR_STATUS_DISP,
23 .ctl_offs = SPM_DIS_PWR_CON,
24 .pwr_sta_offs = SPM_PWR_STATUS,
25 .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
26 .sram_pdn_bits = GENMASK(11, 8),
27 .sram_pdn_ack_bits = GENMASK(12, 12),
28 .bp_cfg = {
29 BUS_PROT_INFRA_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MM_EMI |
30 MT8167_TOP_AXI_PROT_EN_MCU_MM),
31 },
32 .caps = MTK_SCPD_ACTIVE_WAKEUP,
33 },
34 [MT8167_POWER_DOMAIN_VDEC] = {
35 .name = "vdec",
36 .sta_mask = PWR_STATUS_VDEC,
37 .ctl_offs = SPM_VDE_PWR_CON,
38 .pwr_sta_offs = SPM_PWR_STATUS,
39 .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
40 .sram_pdn_bits = GENMASK(8, 8),
41 .sram_pdn_ack_bits = GENMASK(12, 12),
42 .caps = MTK_SCPD_ACTIVE_WAKEUP,
43 },
44 [MT8167_POWER_DOMAIN_ISP] = {
45 .name = "isp",
46 .sta_mask = PWR_STATUS_ISP,
47 .ctl_offs = SPM_ISP_PWR_CON,
48 .pwr_sta_offs = SPM_PWR_STATUS,
49 .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
50 .sram_pdn_bits = GENMASK(11, 8),
51 .sram_pdn_ack_bits = GENMASK(13, 12),
52 .caps = MTK_SCPD_ACTIVE_WAKEUP,
53 },
54 [MT8167_POWER_DOMAIN_MFG_ASYNC] = {
55 .name = "mfg_async",
56 .sta_mask = MT8167_PWR_STATUS_MFG_ASYNC,
57 .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
58 .pwr_sta_offs = SPM_PWR_STATUS,
59 .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
60 .sram_pdn_bits = 0,
61 .sram_pdn_ack_bits = 0,
62 .bp_cfg = {
63 BUS_PROT_INFRA_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MCU_MFG |
64 MT8167_TOP_AXI_PROT_EN_MFG_EMI),
65 },
66 },
67 [MT8167_POWER_DOMAIN_MFG_2D] = {
68 .name = "mfg_2d",
69 .sta_mask = MT8167_PWR_STATUS_MFG_2D,
70 .ctl_offs = SPM_MFG_2D_PWR_CON,
71 .pwr_sta_offs = SPM_PWR_STATUS,
72 .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
73 .sram_pdn_bits = GENMASK(11, 8),
74 .sram_pdn_ack_bits = GENMASK(15, 12),
75 },
76 [MT8167_POWER_DOMAIN_MFG] = {
77 .name = "mfg",
78 .sta_mask = PWR_STATUS_MFG,
79 .ctl_offs = SPM_MFG_PWR_CON,
80 .pwr_sta_offs = SPM_PWR_STATUS,
81 .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
82 .sram_pdn_bits = GENMASK(11, 8),
83 .sram_pdn_ack_bits = GENMASK(15, 12),
84 },
85 [MT8167_POWER_DOMAIN_CONN] = {
86 .name = "conn",
87 .sta_mask = PWR_STATUS_CONN,
88 .ctl_offs = SPM_CONN_PWR_CON,
89 .pwr_sta_offs = SPM_PWR_STATUS,
90 .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
91 .sram_pdn_bits = GENMASK(8, 8),
92 .sram_pdn_ack_bits = 0,
93 .caps = MTK_SCPD_ACTIVE_WAKEUP,
94 .bp_cfg = {
95 BUS_PROT_INFRA_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_CONN_EMI |
96 MT8167_TOP_AXI_PROT_EN_CONN_MCU |
97 MT8167_TOP_AXI_PROT_EN_MCU_CONN),
98 },
99 },
100};
101
102static const struct scpsys_soc_data mt8167_scpsys_data = {
103 .domains_data = scpsys_domain_data_mt8167,
104 .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8167),
105 .bus_prot_blocks = scpsys_bus_prot_blocks_mt8167,
106 .num_bus_prot_blocks = ARRAY_SIZE(scpsys_bus_prot_blocks_mt8167),
107};
108
109#endif /* __SOC_MEDIATEK_MT8167_PM_DOMAINS_H */
110