Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
1/*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
3 * Fibre Channel Host Bus Adapters. *
4 * Copyright (C) 2017-2026 Broadcom. All Rights Reserved. The term *
5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. *
6 * Copyright (C) 2004-2016 Emulex. All rights reserved. *
7 * EMULEX and SLI are trademarks of Emulex. *
8 * www.broadcom.com *
9 * *
10 * This program is free software; you can redistribute it and/or *
11 * modify it under the terms of version 2 of the GNU General *
12 * Public License as published by the Free Software Foundation. *
13 * This program is distributed in the hope that it will be useful. *
14 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
15 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
16 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
17 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
18 * TO BE LEGALLY INVALID. See the GNU General Public License for *
19 * more details, a copy of which can be found in the file COPYING *
20 * included with this package. *
21 *******************************************************************/
22
23#define FDMI_DID 0xfffffaU
24#define NameServer_DID 0xfffffcU
25#define Fabric_Cntl_DID 0xfffffdU
26#define Fabric_DID 0xfffffeU
27#define Bcast_DID 0xffffffU
28#define Mask_DID 0xffffffU
29#define CT_DID_MASK 0xffff00U
30#define Fabric_DID_MASK 0xfff000U
31#define WELL_KNOWN_DID_MASK 0xfffff0U
32
33#define PT2PT_LocalID 1
34#define PT2PT_RemoteID 2
35
36#define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */
37#define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */
38#define FF_DEF_RATOV 10 /* Default RA_TOV (10s) */
39#define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */
40
41#define LPFC_BUF_RING0 64 /* Number of buffers to post to RING
42 0 */
43
44#define FCELSSIZE 1024 /* maximum ELS transfer size */
45
46#define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */
47#define LPFC_EXTRA_RING 1 /* ring 1 for other protocols */
48#define LPFC_ELS_RING 2 /* ring 2 for ELS commands */
49
50#define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */
51#define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */
52#define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 extra command ring entries */
53#define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 extra response ring entries */
54#define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */
55#define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */
56#define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */
57#define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */
58#define SLI2_IOCB_CMD_R3_ENTRIES 0
59#define SLI2_IOCB_RSP_R3_ENTRIES 0
60#define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
61#define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
62
63#define SLI2_IOCB_CMD_SIZE 32
64#define SLI2_IOCB_RSP_SIZE 32
65#define SLI3_IOCB_CMD_SIZE 128
66#define SLI3_IOCB_RSP_SIZE 64
67
68#define LPFC_UNREG_ALL_RPIS_VPORT 0xffff
69#define LPFC_UNREG_ALL_DFLT_RPIS 0xffffffff
70
71/* vendor ID used in SCSI netlink calls */
72#define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX)
73
74#define FW_REV_STR_SIZE 32
75/* Common Transport structures and definitions */
76
77union CtRevisionId {
78 /* Structure is in Big Endian format */
79 struct {
80 uint32_t Revision:8;
81 uint32_t InId:24;
82 } bits;
83 uint32_t word;
84};
85
86union CtCommandResponse {
87 /* Structure is in Big Endian format */
88 struct {
89 __be16 CmdRsp;
90 __be16 Size;
91 } bits;
92 uint32_t word;
93};
94
95/* FC4 Feature bits for RFF_ID */
96#define FC4_FEATURE_TARGET 0x1
97#define FC4_FEATURE_INIT 0x2
98#define FC4_FEATURE_NVME_DISC 0x4
99
100enum rft_word0 {
101 RFT_FCP_REG = (0x1 << 8),
102};
103
104enum rft_word1 {
105 RFT_NVME_REG = (0x1 << 8),
106};
107
108enum rft_word3 {
109 RFT_APP_SERV_REG = (0x1 << 0),
110};
111
112struct lpfc_sli_ct_request {
113 /* Structure is in Big Endian format */
114 union CtRevisionId RevisionId;
115 uint8_t FsType;
116 uint8_t FsSubType;
117 uint8_t Options;
118 uint8_t Rsrvd1;
119 union CtCommandResponse CommandResponse;
120 uint8_t Rsrvd2;
121 uint8_t ReasonCode;
122 uint8_t Explanation;
123 uint8_t VendorUnique;
124#define LPFC_CT_PREAMBLE 20 /* Size of CTReq + 4 up to here */
125
126 union {
127 __be32 PortID;
128 struct gid {
129 uint8_t PortType; /* for GID_PT requests */
130#define GID_PT_N_PORT 1
131 uint8_t DomainScope;
132 uint8_t AreaScope;
133 uint8_t Fc4Type; /* for GID_FT requests */
134 } gid;
135 struct gid_ff {
136 uint8_t Flags;
137 uint8_t DomainScope;
138 uint8_t AreaScope;
139 uint8_t rsvd1;
140 uint8_t rsvd2;
141 uint8_t rsvd3;
142 uint8_t Fc4FBits;
143 uint8_t Fc4Type;
144 } gid_ff;
145 struct rft {
146 __be32 port_id; /* For RFT_ID requests */
147
148 __be32 fcp_reg; /* rsvd 31:9, fcp_reg 8, rsvd 7:0 */
149 __be32 nvme_reg; /* rsvd 31:9, nvme_reg 8, rsvd 7:0 */
150 __be32 word2;
151 __be32 app_serv_reg; /* rsvd 31:1, app_serv_reg 0 */
152 __be32 word[4];
153 } rft;
154 struct rnn {
155 uint32_t PortId; /* For RNN_ID requests */
156 uint8_t wwnn[8];
157 } rnn;
158 struct rsnn { /* For RSNN_ID requests */
159 uint8_t wwnn[8];
160 uint8_t len;
161 uint8_t symbname[255];
162 } rsnn;
163 struct da_id { /* For DA_ID requests */
164 uint32_t port_id;
165 } da_id;
166 struct rspn { /* For RSPN_ID requests */
167 uint32_t PortId;
168 uint8_t len;
169 uint8_t symbname[255];
170 } rspn;
171 struct rspni { /* For RSPNI_PNI requests */
172 __be64 pni;
173 u8 len;
174 u8 symbname[255];
175 } rspni;
176 struct gff {
177 uint32_t PortId;
178 } gff;
179 struct gff_acc {
180 uint8_t fbits[128];
181 } gff_acc;
182 struct gft {
183 uint32_t PortId;
184 } gft;
185 struct gft_acc {
186 uint32_t fc4_types[8];
187 } gft_acc;
188#define FCP_TYPE_FEATURE_OFFSET 7
189 struct rff {
190 uint32_t PortId;
191 uint8_t reserved[2];
192 uint8_t fbits;
193 uint8_t type_code; /* type=8 for FCP */
194 } rff;
195 } un;
196};
197
198#define LPFC_MAX_CT_SIZE (60 * 4096)
199
200#define SLI_CT_REVISION 1
201#define GID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
202 sizeof(struct gid))
203#define GIDFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
204 sizeof(struct gid_ff))
205#define GFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
206 sizeof(struct gff))
207#define GFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
208 sizeof(struct gft))
209#define RFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
210 sizeof(struct rft))
211#define RFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
212 sizeof(struct rff))
213#define RNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
214 sizeof(struct rnn))
215#define RSNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
216 sizeof(struct rsnn))
217#define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
218 sizeof(struct da_id))
219#define RSPN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
220 sizeof(struct rspn))
221#define RSPNI_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
222 sizeof(struct rspni))
223
224/*
225 * FsType Definitions
226 */
227
228#define SLI_CT_MANAGEMENT_SERVICE 0xFA
229#define SLI_CT_TIME_SERVICE 0xFB
230#define SLI_CT_DIRECTORY_SERVICE 0xFC
231#define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD
232
233/*
234 * Directory Service Subtypes
235 */
236
237#define SLI_CT_DIRECTORY_NAME_SERVER 0x02
238
239/*
240 * Response Codes
241 */
242
243#define SLI_CT_RESPONSE_FS_RJT 0x8001
244#define SLI_CT_RESPONSE_FS_ACC 0x8002
245
246/*
247 * Reason Codes
248 */
249
250#define SLI_CT_NO_ADDITIONAL_EXPL 0x0
251#define SLI_CT_INVALID_COMMAND 0x01
252#define SLI_CT_INVALID_VERSION 0x02
253#define SLI_CT_LOGICAL_ERROR 0x03
254#define SLI_CT_INVALID_IU_SIZE 0x04
255#define SLI_CT_LOGICAL_BUSY 0x05
256#define SLI_CT_PROTOCOL_ERROR 0x07
257#define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09
258#define SLI_CT_REQ_NOT_SUPPORTED 0x0b
259#define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10
260#define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11
261#define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12
262#define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13
263#define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20
264#define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21
265#define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22
266#define SLI_CT_VENDOR_UNIQUE 0xff
267
268/*
269 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations
270 */
271
272#define SLI_CT_NO_PORT_ID 0x01
273#define SLI_CT_NO_PORT_NAME 0x02
274#define SLI_CT_NO_NODE_NAME 0x03
275#define SLI_CT_NO_CLASS_OF_SERVICE 0x04
276#define SLI_CT_NO_IP_ADDRESS 0x05
277#define SLI_CT_NO_IPA 0x06
278#define SLI_CT_NO_FC4_TYPES 0x07
279#define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08
280#define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09
281#define SLI_CT_NO_PORT_TYPE 0x0A
282#define SLI_CT_ACCESS_DENIED 0x10
283#define SLI_CT_INVALID_PORT_ID 0x11
284#define SLI_CT_DATABASE_EMPTY 0x12
285#define SLI_CT_APP_ID_NOT_AVAILABLE 0x40
286
287/*
288 * Name Server Command Codes
289 */
290
291#define SLI_CTNS_GA_NXT 0x0100
292#define SLI_CTNS_GPN_ID 0x0112
293#define SLI_CTNS_GNN_ID 0x0113
294#define SLI_CTNS_GCS_ID 0x0114
295#define SLI_CTNS_GFT_ID 0x0117
296#define SLI_CTNS_GSPN_ID 0x0118
297#define SLI_CTNS_GPT_ID 0x011A
298#define SLI_CTNS_GFF_ID 0x011F
299#define SLI_CTNS_GID_PN 0x0121
300#define SLI_CTNS_GID_NN 0x0131
301#define SLI_CTNS_GIP_NN 0x0135
302#define SLI_CTNS_GIPA_NN 0x0136
303#define SLI_CTNS_GSNN_NN 0x0139
304#define SLI_CTNS_GNN_IP 0x0153
305#define SLI_CTNS_GIPA_IP 0x0156
306#define SLI_CTNS_GID_FT 0x0171
307#define SLI_CTNS_GID_FF 0x01F1
308#define SLI_CTNS_GID_PT 0x01A1
309#define SLI_CTNS_RPN_ID 0x0212
310#define SLI_CTNS_RNN_ID 0x0213
311#define SLI_CTNS_RCS_ID 0x0214
312#define SLI_CTNS_RFT_ID 0x0217
313#define SLI_CTNS_RSPN_ID 0x0218
314#define SLI_CTNS_RPT_ID 0x021A
315#define SLI_CTNS_RFF_ID 0x021F
316#define SLI_CTNS_RIP_NN 0x0235
317#define SLI_CTNS_RIPA_NN 0x0236
318#define SLI_CTNS_RSNN_NN 0x0239
319#define SLI_CTNS_RSPNI_PNI 0x0240
320#define SLI_CTNS_DA_ID 0x0300
321
322/*
323 * Port Types
324 */
325
326#define SLI_CTPT_N_PORT 0x01
327#define SLI_CTPT_NL_PORT 0x02
328#define SLI_CTPT_FNL_PORT 0x03
329#define SLI_CTPT_IP 0x04
330#define SLI_CTPT_FCP 0x08
331#define SLI_CTPT_NVME 0x28
332#define SLI_CTPT_NX_PORT 0x7F
333#define SLI_CTPT_F_PORT 0x81
334#define SLI_CTPT_FL_PORT 0x82
335#define SLI_CTPT_E_PORT 0x84
336
337#define SLI_CT_LAST_ENTRY 0x80000000
338
339/* Fibre Channel Service Parameter definitions */
340
341#define FC_PH_4_0 6 /* FC-PH version 4.0 */
342#define FC_PH_4_1 7 /* FC-PH version 4.1 */
343#define FC_PH_4_2 8 /* FC-PH version 4.2 */
344#define FC_PH_4_3 9 /* FC-PH version 4.3 */
345
346#define FC_PH_LOW 8 /* Lowest supported FC-PH version */
347#define FC_PH_HIGH 9 /* Highest supported FC-PH version */
348#define FC_PH3 0x20 /* FC-PH-3 version */
349
350#define FF_FRAME_SIZE 2048
351
352struct lpfc_name {
353 union {
354 struct {
355#ifdef __BIG_ENDIAN_BITFIELD
356 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
357 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
358 8:11 of IEEE ext */
359#else /* __LITTLE_ENDIAN_BITFIELD */
360 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
361 8:11 of IEEE ext */
362 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
363#endif
364
365#define NAME_IEEE 0x1 /* IEEE name - nameType */
366#define NAME_IEEE_EXT 0x2 /* IEEE extended name */
367#define NAME_FC_TYPE 0x3 /* FC native name type */
368#define NAME_IP_TYPE 0x4 /* IP address */
369#define NAME_CCITT_TYPE 0xC
370#define NAME_CCITT_GR_TYPE 0xE
371 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE
372 extended Lsb */
373 uint8_t IEEE[6]; /* FC IEEE address */
374 } s;
375 uint8_t wwn[8];
376 uint64_t name __packed __aligned(4);
377 __be64 wwn_be __packed __aligned(4);
378 } u;
379};
380
381struct csp {
382 uint8_t fcphHigh; /* FC Word 0, byte 0 */
383 uint8_t fcphLow;
384 uint8_t bbCreditMsb;
385 uint8_t bbCreditLsb; /* FC Word 0, byte 3 */
386
387/*
388 * Word 1 Bit 31 in common service parameter is overloaded.
389 * Word 1 Bit 31 in FLOGI request is multiple NPort request
390 * Word 1 Bit 31 in FLOGI response is clean address bit
391 */
392#define clean_address_bit request_multiple_Nport /* Word 1, bit 31 */
393/*
394 * Word 1 Bit 30 in common service parameter is overloaded.
395 * Word 1 Bit 30 in FLOGI request is Virtual Fabrics
396 * Word 1 Bit 30 in PLOGI request is random offset
397 */
398#define virtual_fabric_support randomOffset /* Word 1, bit 30 */
399/*
400 * Word 1 Bit 29 in common service parameter is overloaded.
401 * Word 1 Bit 29 in FLOGI response is multiple NPort assignment
402 * Word 1 Bit 29 in FLOGI/PLOGI request is Valid Vendor Version Level
403 */
404#define valid_vendor_ver_level response_multiple_NPort /* Word 1, bit 29 */
405#ifdef __BIG_ENDIAN_BITFIELD
406 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
407 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
408 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
409 uint16_t fPort:1; /* FC Word 1, bit 28 */
410 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
411 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
412 uint16_t multicast:1; /* FC Word 1, bit 25 */
413 uint16_t app_hdr_support:1; /* FC Word 1, bit 24 */
414
415 uint16_t priority_tagging:1; /* FC Word 1, bit 23 */
416 uint16_t simplex:1; /* FC Word 1, bit 22 */
417 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
418 uint16_t dhd:1; /* FC Word 1, bit 18 */
419 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
420 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
421#else /* __LITTLE_ENDIAN_BITFIELD */
422 uint16_t app_hdr_support:1; /* FC Word 1, bit 24 */
423 uint16_t multicast:1; /* FC Word 1, bit 25 */
424 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
425 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
426 uint16_t fPort:1; /* FC Word 1, bit 28 */
427 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
428 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
429 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
430
431 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
432 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
433 uint16_t dhd:1; /* FC Word 1, bit 18 */
434 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
435 uint16_t simplex:1; /* FC Word 1, bit 22 */
436 uint16_t priority_tagging:1; /* FC Word 1, bit 23 */
437#endif
438
439 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */
440 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */
441 union {
442 struct {
443 uint8_t word2Reserved1; /* FC Word 2 byte 0 */
444
445 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */
446 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */
447
448 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */
449 } nPort;
450 uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */
451 } w2;
452
453 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */
454};
455
456struct class_parms {
457#ifdef __BIG_ENDIAN_BITFIELD
458 uint8_t classValid:1; /* FC Word 0, bit 31 */
459 uint8_t intermix:1; /* FC Word 0, bit 30 */
460 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
461 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
462 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
463 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
464#else /* __LITTLE_ENDIAN_BITFIELD */
465 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
466 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
467 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
468 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
469 uint8_t intermix:1; /* FC Word 0, bit 30 */
470 uint8_t classValid:1; /* FC Word 0, bit 31 */
471
472#endif
473
474 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */
475
476#ifdef __BIG_ENDIAN_BITFIELD
477 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
478 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
479 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
480 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
481 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
482#else /* __LITTLE_ENDIAN_BITFIELD */
483 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
484 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
485 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
486 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
487 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
488#endif
489
490 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */
491
492#ifdef __BIG_ENDIAN_BITFIELD
493 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
494 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
495 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
496 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
497 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
498 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
499#else /* __LITTLE_ENDIAN_BITFIELD */
500 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
501 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
502 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
503 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
504 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
505 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
506#endif
507
508 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */
509 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */
510 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */
511
512 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */
513 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */
514 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */
515 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */
516
517 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */
518 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */
519 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */
520 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */
521};
522
523enum aux_parm_flags {
524 AUX_PARM_PNI_VALID = 0x20, /* FC Word 0, bit 29 */
525 AUX_PARM_DATA_VALID = 0x40, /* FC Word 0, bit 30 */
526};
527
528struct aux_parm {
529 u8 flags; /* FC Word 0, bit 31:24 */
530 u8 ext_feat[3]; /* FC Word 0, bit 23:0 */
531
532 __be64 pni; /* FC Word 1 and 2, platform name identifier */
533
534 __be16 rsvd; /* FC Word 3, bit 31:16 */
535 __be16 npiv_cnt; /* FC Word 3, bit 15:0 */
536} __packed;
537
538struct serv_parm { /* Structure is in Big Endian format */
539 struct csp cmn;
540 struct lpfc_name portName;
541 struct lpfc_name nodeName;
542 struct class_parms cls1;
543 struct class_parms cls2;
544 struct class_parms cls3;
545 struct aux_parm aux;
546 union {
547 uint8_t vendorVersion[16];
548 struct {
549 uint32_t vid;
550#define LPFC_VV_EMLX_ID 0x454d4c58 /* EMLX */
551 uint32_t flags;
552#define LPFC_VV_SUPPRESS_RSP 1
553 } vv;
554 } un;
555};
556
557/*
558 * Virtual Fabric Tagging Header
559 */
560struct fc_vft_header {
561 uint32_t word0;
562#define fc_vft_hdr_r_ctl_SHIFT 24
563#define fc_vft_hdr_r_ctl_MASK 0xFF
564#define fc_vft_hdr_r_ctl_WORD word0
565#define fc_vft_hdr_ver_SHIFT 22
566#define fc_vft_hdr_ver_MASK 0x3
567#define fc_vft_hdr_ver_WORD word0
568#define fc_vft_hdr_type_SHIFT 18
569#define fc_vft_hdr_type_MASK 0xF
570#define fc_vft_hdr_type_WORD word0
571#define fc_vft_hdr_e_SHIFT 16
572#define fc_vft_hdr_e_MASK 0x1
573#define fc_vft_hdr_e_WORD word0
574#define fc_vft_hdr_priority_SHIFT 13
575#define fc_vft_hdr_priority_MASK 0x7
576#define fc_vft_hdr_priority_WORD word0
577#define fc_vft_hdr_vf_id_SHIFT 1
578#define fc_vft_hdr_vf_id_MASK 0xFFF
579#define fc_vft_hdr_vf_id_WORD word0
580 uint32_t word1;
581#define fc_vft_hdr_hopct_SHIFT 24
582#define fc_vft_hdr_hopct_MASK 0xFF
583#define fc_vft_hdr_hopct_WORD word1
584};
585
586#include <uapi/scsi/fc/fc_els.h>
587
588/*
589 * Application Header
590 */
591struct fc_app_header {
592 uint32_t dst_app_id;
593 uint32_t src_app_id;
594#define LOOPBACK_SRC_APPID 0x4321
595 uint32_t word2;
596 uint32_t word3;
597};
598
599/*
600 * dfctl optional header definition
601 */
602enum lpfc_fc_dfctl {
603 LPFC_FC_NO_DEVICE_HEADER,
604 LPFC_FC_16B_DEVICE_HEADER,
605 LPFC_FC_32B_DEVICE_HEADER,
606 LPFC_FC_64B_DEVICE_HEADER,
607};
608
609/*
610 * Extended Link Service LS_COMMAND codes (Payload Word 0)
611 */
612#ifdef __BIG_ENDIAN_BITFIELD
613#define ELS_CMD_MASK 0xffff0000
614#define ELS_RSP_MASK 0xff000000
615#define ELS_CMD_LS_RJT 0x01000000
616#define ELS_CMD_ACC 0x02000000
617#define ELS_CMD_PLOGI 0x03000000
618#define ELS_CMD_FLOGI 0x04000000
619#define ELS_CMD_LOGO 0x05000000
620#define ELS_CMD_ABTX 0x06000000
621#define ELS_CMD_RCS 0x07000000
622#define ELS_CMD_RES 0x08000000
623#define ELS_CMD_RSS 0x09000000
624#define ELS_CMD_RSI 0x0A000000
625#define ELS_CMD_ESTS 0x0B000000
626#define ELS_CMD_ESTC 0x0C000000
627#define ELS_CMD_ADVC 0x0D000000
628#define ELS_CMD_RTV 0x0E000000
629#define ELS_CMD_RLS 0x0F000000
630#define ELS_CMD_ECHO 0x10000000
631#define ELS_CMD_TEST 0x11000000
632#define ELS_CMD_RRQ 0x12000000
633#define ELS_CMD_REC 0x13000000
634#define ELS_CMD_RDP 0x18000000
635#define ELS_CMD_RDF 0x19000000
636#define ELS_CMD_PRLI 0x20100014
637#define ELS_CMD_NVMEPRLI 0x20140018
638#define ELS_CMD_PRLO 0x21100014
639#define ELS_CMD_PRLO_ACC 0x02100014
640#define ELS_CMD_PDISC 0x50000000
641#define ELS_CMD_FDISC 0x51000000
642#define ELS_CMD_ADISC 0x52000000
643#define ELS_CMD_FARP 0x54000000
644#define ELS_CMD_FARPR 0x55000000
645#define ELS_CMD_RPL 0x57000000
646#define ELS_CMD_FAN 0x60000000
647#define ELS_CMD_RSCN 0x61040000
648#define ELS_CMD_RSCN_XMT 0x61040008
649#define ELS_CMD_SCR 0x62000000
650#define ELS_CMD_RNID 0x78000000
651#define ELS_CMD_LIRR 0x7A000000
652#define ELS_CMD_LCB 0x81000000
653#define ELS_CMD_FPIN 0x16000000
654#define ELS_CMD_EDC 0x17000000
655#define ELS_CMD_QFPA 0xB0000000
656#define ELS_CMD_UVEM 0xB1000000
657#else /* __LITTLE_ENDIAN_BITFIELD */
658#define ELS_CMD_MASK 0xffff
659#define ELS_RSP_MASK 0xff
660#define ELS_CMD_LS_RJT 0x01
661#define ELS_CMD_ACC 0x02
662#define ELS_CMD_PLOGI 0x03
663#define ELS_CMD_FLOGI 0x04
664#define ELS_CMD_LOGO 0x05
665#define ELS_CMD_ABTX 0x06
666#define ELS_CMD_RCS 0x07
667#define ELS_CMD_RES 0x08
668#define ELS_CMD_RSS 0x09
669#define ELS_CMD_RSI 0x0A
670#define ELS_CMD_ESTS 0x0B
671#define ELS_CMD_ESTC 0x0C
672#define ELS_CMD_ADVC 0x0D
673#define ELS_CMD_RTV 0x0E
674#define ELS_CMD_RLS 0x0F
675#define ELS_CMD_ECHO 0x10
676#define ELS_CMD_TEST 0x11
677#define ELS_CMD_RRQ 0x12
678#define ELS_CMD_REC 0x13
679#define ELS_CMD_RDP 0x18
680#define ELS_CMD_RDF 0x19
681#define ELS_CMD_PRLI 0x14001020
682#define ELS_CMD_NVMEPRLI 0x18001420
683#define ELS_CMD_PRLO 0x14001021
684#define ELS_CMD_PRLO_ACC 0x14001002
685#define ELS_CMD_PDISC 0x50
686#define ELS_CMD_FDISC 0x51
687#define ELS_CMD_ADISC 0x52
688#define ELS_CMD_FARP 0x54
689#define ELS_CMD_FARPR 0x55
690#define ELS_CMD_RPL 0x57
691#define ELS_CMD_FAN 0x60
692#define ELS_CMD_RSCN 0x0461
693#define ELS_CMD_RSCN_XMT 0x08000461
694#define ELS_CMD_SCR 0x62
695#define ELS_CMD_RNID 0x78
696#define ELS_CMD_LIRR 0x7A
697#define ELS_CMD_LCB 0x81
698#define ELS_CMD_FPIN ELS_FPIN
699#define ELS_CMD_EDC ELS_EDC
700#define ELS_CMD_QFPA 0xB0
701#define ELS_CMD_UVEM 0xB1
702#endif
703
704/*
705 * LS_RJT Payload Definition
706 */
707
708struct ls_rjt { /* Structure is in Big Endian format */
709 union {
710 __be32 ls_rjt_error_be;
711 uint32_t lsRjtError;
712 struct {
713 uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */
714
715 uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */
716 /* LS_RJT reason codes */
717#define LSRJT_INVALID_CMD 0x01
718#define LSRJT_LOGICAL_ERR 0x03
719#define LSRJT_LOGICAL_BSY 0x05
720#define LSRJT_PROTOCOL_ERR 0x07
721#define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */
722#define LSRJT_CMD_UNSUPPORTED 0x0B
723#define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */
724
725 uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */
726 /* LS_RJT reason explanation */
727#define LSEXP_NOTHING_MORE 0x00
728#define LSEXP_SPARM_OPTIONS 0x01
729#define LSEXP_SPARM_ICTL 0x03
730#define LSEXP_SPARM_RCTL 0x05
731#define LSEXP_SPARM_RCV_SIZE 0x07
732#define LSEXP_SPARM_CONCUR_SEQ 0x09
733#define LSEXP_SPARM_CREDIT 0x0B
734#define LSEXP_INVALID_PNAME 0x0D
735#define LSEXP_INVALID_NNAME 0x0E
736#define LSEXP_INVALID_CSP 0x0F
737#define LSEXP_INVALID_ASSOC_HDR 0x11
738#define LSEXP_ASSOC_HDR_REQ 0x13
739#define LSEXP_INVALID_O_SID 0x15
740#define LSEXP_INVALID_OX_RX 0x17
741#define LSEXP_CMD_IN_PROGRESS 0x19
742#define LSEXP_PORT_LOGIN_REQ 0x1E
743#define LSEXP_INVALID_NPORT_ID 0x1F
744#define LSEXP_INVALID_SEQ_ID 0x21
745#define LSEXP_INVALID_XCHG 0x23
746#define LSEXP_INACTIVE_XCHG 0x25
747#define LSEXP_RQ_REQUIRED 0x27
748#define LSEXP_OUT_OF_RESOURCE 0x29
749#define LSEXP_CANT_GIVE_DATA 0x2A
750#define LSEXP_REQ_UNSUPPORTED 0x2C
751#define LSEXP_AUTH_REQ 0x48
752#define LSEXP_NO_RSRC_ASSIGN 0x52
753 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */
754 } b;
755 } un;
756};
757
758/*
759 * N_Port Login (FLOGO/PLOGO Request) Payload Definition
760 */
761
762typedef struct _LOGO { /* Structure is in Big Endian format */
763 union {
764 uint32_t nPortId32; /* Access nPortId as a word */
765 struct {
766 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */
767 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */
768 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */
769 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */
770 } b;
771 } un;
772 struct lpfc_name portName; /* N_port name field */
773} LOGO;
774
775/*
776 * FCP Login (PRLI Request / ACC) Payload Definition
777 */
778
779#define PRLX_PAGE_LEN 0x10
780#define TPRLO_PAGE_LEN 0x14
781
782typedef struct _PRLI { /* Structure is in Big Endian format */
783 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */
784
785#define PRLI_FCP_TYPE 0x08
786#define PRLI_NVME_TYPE 0x28
787 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
788
789#ifdef __BIG_ENDIAN_BITFIELD
790 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
791 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
792 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
793
794 /* ACC = imagePairEstablished */
795 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
796 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
797#else /* __LITTLE_ENDIAN_BITFIELD */
798 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
799 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
800 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
801 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
802 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
803 /* ACC = imagePairEstablished */
804#endif
805
806#define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */
807#define PRLI_NO_RESOURCES 0x2
808#define PRLI_INIT_INCOMPLETE 0x3
809#define PRLI_NO_SUCH_PA 0x4
810#define PRLI_PREDEF_CONFIG 0x5
811#define PRLI_PARTIAL_SUCCESS 0x6
812#define PRLI_INVALID_PAGE_CNT 0x7
813#define PRLI_INV_SRV_PARM 0x8
814
815 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
816
817 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
818
819 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
820
821 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */
822 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */
823
824#ifdef __BIG_ENDIAN_BITFIELD
825 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
826 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
827 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
828 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
829 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
830 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
831 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
832 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
833 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
834 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
835 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
836 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
837 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
838 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
839 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
840 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
841#else /* __LITTLE_ENDIAN_BITFIELD */
842 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
843 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
844 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
845 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
846 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
847 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
848 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
849 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
850 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
851 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
852 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
853 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
854 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
855 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
856 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
857 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
858#endif
859} PRLI;
860
861/*
862 * FCP Logout (PRLO Request / ACC) Payload Definition
863 */
864
865typedef struct _PRLO { /* Structure is in Big Endian format */
866 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */
867
868#define PRLO_FCP_TYPE 0x08
869 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
870
871#ifdef __BIG_ENDIAN_BITFIELD
872 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
873 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
874 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
875 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
876#else /* __LITTLE_ENDIAN_BITFIELD */
877 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
878 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
879 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
880 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
881#endif
882
883#define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */
884#define PRLO_NO_SUCH_IMAGE 0x4
885#define PRLO_INVALID_PAGE_CNT 0x7
886
887 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
888
889 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
890
891 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
892
893 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */
894} PRLO;
895
896typedef struct _ADISC { /* Structure is in Big Endian format */
897 uint32_t hardAL_PA;
898 struct lpfc_name portName;
899 struct lpfc_name nodeName;
900 uint32_t DID;
901} ADISC;
902
903typedef struct _FARP { /* Structure is in Big Endian format */
904 uint32_t Mflags:8;
905 uint32_t Odid:24;
906#define FARP_NO_ACTION 0 /* FARP information enclosed, no
907 action */
908#define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */
909#define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */
910#define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */
911#define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not
912 supported */
913#define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not
914 supported */
915 uint32_t Rflags:8;
916 uint32_t Rdid:24;
917#define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */
918#define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */
919 struct lpfc_name OportName;
920 struct lpfc_name OnodeName;
921 struct lpfc_name RportName;
922 struct lpfc_name RnodeName;
923 uint8_t Oipaddr[16];
924 uint8_t Ripaddr[16];
925} FARP;
926
927typedef struct _FAN { /* Structure is in Big Endian format */
928 uint32_t Fdid;
929 struct lpfc_name FportName;
930 struct lpfc_name FnodeName;
931} FAN;
932
933typedef struct _SCR { /* Structure is in Big Endian format */
934 uint8_t resvd1;
935 uint8_t resvd2;
936 uint8_t resvd3;
937 uint8_t Function;
938#define SCR_FUNC_FABRIC 0x01
939#define SCR_FUNC_NPORT 0x02
940#define SCR_FUNC_FULL 0x03
941#define SCR_CLEAR 0xff
942} SCR;
943
944typedef struct _RNID_TOP_DISC {
945 struct lpfc_name portName;
946 uint8_t resvd[8];
947 uint32_t unitType;
948#define RNID_HBA 0x7
949#define RNID_HOST 0xa
950#define RNID_DRIVER 0xd
951 uint32_t physPort;
952 uint32_t attachedNodes;
953 uint16_t ipVersion;
954#define RNID_IPV4 0x1
955#define RNID_IPV6 0x2
956 uint16_t UDPport;
957 uint8_t ipAddr[16];
958 uint16_t resvd1;
959 uint16_t flags;
960#define RNID_TD_SUPPORT 0x1
961#define RNID_LP_VALID 0x2
962} RNID_TOP_DISC;
963
964typedef struct _RNID { /* Structure is in Big Endian format */
965 uint8_t Format;
966#define RNID_TOPOLOGY_DISC 0xdf
967 uint8_t CommonLen;
968 uint8_t resvd1;
969 uint8_t SpecificLen;
970 struct lpfc_name portName;
971 struct lpfc_name nodeName;
972 union {
973 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */
974 } un;
975} RNID;
976
977struct RLS { /* Structure is in Big Endian format */
978 uint32_t rls;
979#define rls_rsvd_SHIFT 24
980#define rls_rsvd_MASK 0x000000ff
981#define rls_rsvd_WORD rls
982#define rls_did_SHIFT 0
983#define rls_did_MASK 0x00ffffff
984#define rls_did_WORD rls
985};
986
987struct RLS_RSP { /* Structure is in Big Endian format */
988 uint32_t linkFailureCnt;
989 uint32_t lossSyncCnt;
990 uint32_t lossSignalCnt;
991 uint32_t primSeqErrCnt;
992 uint32_t invalidXmitWord;
993 uint32_t crcCnt;
994};
995
996struct RRQ { /* Structure is in Big Endian format */
997 uint32_t rrq;
998#define rrq_rsvd_SHIFT 24
999#define rrq_rsvd_MASK 0x000000ff
1000#define rrq_rsvd_WORD rrq
1001#define rrq_did_SHIFT 0
1002#define rrq_did_MASK 0x00ffffff
1003#define rrq_did_WORD rrq
1004 uint32_t rrq_exchg;
1005#define rrq_oxid_SHIFT 16
1006#define rrq_oxid_MASK 0xffff
1007#define rrq_oxid_WORD rrq_exchg
1008#define rrq_rxid_SHIFT 0
1009#define rrq_rxid_MASK 0xffff
1010#define rrq_rxid_WORD rrq_exchg
1011};
1012
1013#define LPFC_MAX_VFN_PER_PFN 255 /* Maximum VFs allowed per ARI */
1014#define LPFC_DEF_VFN_PER_PFN 0 /* Default VFs due to platform limitation*/
1015
1016struct RTV_RSP { /* Structure is in Big Endian format */
1017 uint32_t ratov;
1018 uint32_t edtov;
1019 uint32_t qtov;
1020#define qtov_rsvd0_SHIFT 28
1021#define qtov_rsvd0_MASK 0x0000000f
1022#define qtov_rsvd0_WORD qtov /* reserved */
1023#define qtov_edtovres_SHIFT 27
1024#define qtov_edtovres_MASK 0x00000001
1025#define qtov_edtovres_WORD qtov /* E_D_TOV Resolution */
1026#define qtov__rsvd1_SHIFT 19
1027#define qtov_rsvd1_MASK 0x0000003f
1028#define qtov_rsvd1_WORD qtov /* reserved */
1029#define qtov_rttov_SHIFT 18
1030#define qtov_rttov_MASK 0x00000001
1031#define qtov_rttov_WORD qtov /* R_T_TOV value */
1032#define qtov_rsvd2_SHIFT 0
1033#define qtov_rsvd2_MASK 0x0003ffff
1034#define qtov_rsvd2_WORD qtov /* reserved */
1035};
1036
1037
1038typedef struct _RPL { /* Structure is in Big Endian format */
1039 uint32_t maxsize;
1040 uint32_t index;
1041} RPL;
1042
1043typedef struct _PORT_NUM_BLK {
1044 uint32_t portNum;
1045 uint32_t portID;
1046 struct lpfc_name portName;
1047} PORT_NUM_BLK;
1048
1049typedef struct _RPL_RSP { /* Structure is in Big Endian format */
1050 uint32_t listLen;
1051 uint32_t index;
1052 PORT_NUM_BLK port_num_blk;
1053} RPL_RSP;
1054
1055/* This is used for RSCN command */
1056typedef struct _D_ID { /* Structure is in Big Endian format */
1057 union {
1058 uint32_t word;
1059 struct {
1060#ifdef __BIG_ENDIAN_BITFIELD
1061 uint8_t resv;
1062 uint8_t domain;
1063 uint8_t area;
1064 uint8_t id;
1065#else /* __LITTLE_ENDIAN_BITFIELD */
1066 uint8_t id;
1067 uint8_t area;
1068 uint8_t domain;
1069 uint8_t resv;
1070#endif
1071 } b;
1072 } un;
1073} D_ID;
1074
1075#define RSCN_ADDRESS_FORMAT_PORT 0x0
1076#define RSCN_ADDRESS_FORMAT_AREA 0x1
1077#define RSCN_ADDRESS_FORMAT_DOMAIN 0x2
1078#define RSCN_ADDRESS_FORMAT_FABRIC 0x3
1079#define RSCN_ADDRESS_FORMAT_MASK 0x3
1080
1081/*
1082 * Structure to define all ELS Payload types
1083 */
1084
1085typedef struct _ELS_PKT { /* Structure is in Big Endian format */
1086 uint8_t elsCode; /* FC Word 0, bit 24:31 */
1087 uint8_t elsByte1;
1088 uint8_t elsByte2;
1089 uint8_t elsByte3;
1090 union {
1091 struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */
1092 struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */
1093 LOGO logo; /* Payload for PLOGO/FLOGO/ACC */
1094 PRLI prli; /* Payload for PRLI/ACC */
1095 PRLO prlo; /* Payload for PRLO/ACC */
1096 ADISC adisc; /* Payload for ADISC/ACC */
1097 FARP farp; /* Payload for FARP/ACC */
1098 FAN fan; /* Payload for FAN */
1099 SCR scr; /* Payload for SCR/ACC */
1100 RNID rnid; /* Payload for RNID */
1101 uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */
1102 } un;
1103} ELS_PKT;
1104
1105/*
1106 * Link Cable Beacon (LCB) ELS Frame
1107 */
1108
1109struct fc_lcb_request_frame {
1110 uint32_t lcb_command; /* ELS command opcode (0x81) */
1111 uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */
1112#define LPFC_LCB_ON 0x1
1113#define LPFC_LCB_OFF 0x2
1114 uint8_t reserved[2];
1115 uint8_t capability; /* LCB Payload Word 1, bit 0:7 */
1116 uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */
1117#define LPFC_LCB_GREEN 0x1
1118#define LPFC_LCB_AMBER 0x2
1119 uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */
1120#define LCB_CAPABILITY_DURATION 1
1121#define BEACON_VERSION_V1 1
1122#define BEACON_VERSION_V0 0
1123 uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */
1124};
1125
1126/*
1127 * Link Cable Beacon (LCB) ELS Response Frame
1128 */
1129struct fc_lcb_res_frame {
1130 uint32_t lcb_ls_acc; /* Acceptance of LCB request (0x02) */
1131 uint8_t lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */
1132 uint8_t reserved[2];
1133 uint8_t capability; /* LCB Payload Word 1, bit 0:7 */
1134 uint8_t lcb_type; /* LCB Payload Word 2, bit 24:31 */
1135 uint8_t lcb_frequency; /* LCB Payload Word 2, bit 16:23 */
1136 uint16_t lcb_duration; /* LCB Payload Word 2, bit 15:0 */
1137};
1138
1139/*
1140 * Read Diagnostic Parameters (RDP) ELS frame.
1141 */
1142#define SFF_PG0_IDENT_SFP 0x3
1143
1144#define SFP_FLAG_PT_OPTICAL 0x0
1145#define SFP_FLAG_PT_SWLASER 0x01
1146#define SFP_FLAG_PT_LWLASER_LC1310 0x02
1147#define SFP_FLAG_PT_LWLASER_LL1550 0x03
1148#define SFP_FLAG_PT_MASK 0x0F
1149#define SFP_FLAG_PT_SHIFT 0
1150
1151#define SFP_FLAG_IS_OPTICAL_PORT 0x01
1152#define SFP_FLAG_IS_OPTICAL_MASK 0x010
1153#define SFP_FLAG_IS_OPTICAL_SHIFT 4
1154
1155#define SFP_FLAG_IS_DESC_VALID 0x01
1156#define SFP_FLAG_IS_DESC_VALID_MASK 0x020
1157#define SFP_FLAG_IS_DESC_VALID_SHIFT 5
1158
1159#define SFP_FLAG_CT_UNKNOWN 0x0
1160#define SFP_FLAG_CT_SFP_PLUS 0x01
1161#define SFP_FLAG_CT_MASK 0x3C
1162#define SFP_FLAG_CT_SHIFT 6
1163
1164struct fc_rdp_port_name_info {
1165 uint8_t wwnn[8];
1166 uint8_t wwpn[8];
1167};
1168
1169
1170/*
1171 * Link Error Status Block Structure (FC-FS-3) for RDP
1172 * This similar to RPS ELS
1173 */
1174struct fc_link_status {
1175 uint32_t link_failure_cnt;
1176 uint32_t loss_of_synch_cnt;
1177 uint32_t loss_of_signal_cnt;
1178 uint32_t primitive_seq_proto_err;
1179 uint32_t invalid_trans_word;
1180 uint32_t invalid_crc_cnt;
1181
1182};
1183
1184#define RDP_PORT_NAMES_DESC_TAG 0x00010003
1185struct fc_rdp_port_name_desc {
1186 uint32_t tag; /* 0001 0003h */
1187 uint32_t length; /* set to size of payload struct */
1188 struct fc_rdp_port_name_info port_names;
1189};
1190
1191
1192struct fc_rdp_fec_info {
1193 uint32_t CorrectedBlocks;
1194 uint32_t UncorrectableBlocks;
1195};
1196
1197#define RDP_FEC_DESC_TAG 0x00010005
1198struct fc_fec_rdp_desc {
1199 uint32_t tag;
1200 uint32_t length;
1201 struct fc_rdp_fec_info info;
1202};
1203
1204struct fc_rdp_link_error_status_payload_info {
1205 struct fc_link_status link_status; /* 24 bytes */
1206 uint32_t port_type; /* bits 31-30 only */
1207};
1208
1209#define RDP_LINK_ERROR_STATUS_DESC_TAG 0x00010002
1210struct fc_rdp_link_error_status_desc {
1211 uint32_t tag; /* 0001 0002h */
1212 uint32_t length; /* set to size of payload struct */
1213 struct fc_rdp_link_error_status_payload_info info;
1214};
1215
1216#define VN_PT_PHY_UNKNOWN 0x00
1217#define VN_PT_PHY_PF_PORT 0x01
1218#define VN_PT_PHY_ETH_MAC 0x10
1219#define VN_PT_PHY_SHIFT 30
1220
1221#define RDP_PS_1GB 0x8000
1222#define RDP_PS_2GB 0x4000
1223#define RDP_PS_4GB 0x2000
1224#define RDP_PS_10GB 0x1000
1225#define RDP_PS_8GB 0x0800
1226#define RDP_PS_16GB 0x0400
1227#define RDP_PS_32GB 0x0200
1228#define RDP_PS_64GB 0x0100
1229#define RDP_PS_128GB 0x0080
1230#define RDP_PS_256GB 0x0040
1231
1232#define RDP_CAP_USER_CONFIGURED 0x0002
1233#define RDP_CAP_UNKNOWN 0x0001
1234#define RDP_PS_UNKNOWN 0x0002
1235#define RDP_PS_NOT_ESTABLISHED 0x0001
1236
1237struct fc_rdp_port_speed {
1238 uint16_t capabilities;
1239 uint16_t speed;
1240};
1241
1242struct fc_rdp_port_speed_info {
1243 struct fc_rdp_port_speed port_speed;
1244};
1245
1246#define RDP_PORT_SPEED_DESC_TAG 0x00010001
1247struct fc_rdp_port_speed_desc {
1248 uint32_t tag; /* 00010001h */
1249 uint32_t length; /* set to size of payload struct */
1250 struct fc_rdp_port_speed_info info;
1251};
1252
1253#define RDP_NPORT_ID_SIZE 4
1254#define RDP_N_PORT_DESC_TAG 0x00000003
1255struct fc_rdp_nport_desc {
1256 uint32_t tag; /* 0000 0003h, big endian */
1257 uint32_t length; /* size of RDP_N_PORT_ID struct */
1258 uint32_t nport_id : 12;
1259 uint32_t reserved : 8;
1260};
1261
1262
1263struct fc_rdp_link_service_info {
1264 uint32_t els_req; /* Request payload word 0 value.*/
1265};
1266
1267#define RDP_LINK_SERVICE_DESC_TAG 0x00000001
1268struct fc_rdp_link_service_desc {
1269 uint32_t tag; /* Descriptor tag 1 */
1270 uint32_t length; /* set to size of payload struct. */
1271 struct fc_rdp_link_service_info payload;
1272 /* must be ELS req Word 0(0x18) */
1273};
1274
1275struct fc_rdp_sfp_info {
1276 uint16_t temperature;
1277 uint16_t vcc;
1278 uint16_t tx_bias;
1279 uint16_t tx_power;
1280 uint16_t rx_power;
1281 uint16_t flags;
1282};
1283
1284#define RDP_SFP_DESC_TAG 0x00010000
1285struct fc_rdp_sfp_desc {
1286 uint32_t tag;
1287 uint32_t length; /* set to size of sfp_info struct */
1288 struct fc_rdp_sfp_info sfp_info;
1289};
1290
1291/* Buffer Credit Descriptor */
1292struct fc_rdp_bbc_info {
1293 uint32_t port_bbc; /* FC_Port buffer-to-buffer credit */
1294 uint32_t attached_port_bbc;
1295 uint32_t rtt; /* Round trip time */
1296};
1297#define RDP_BBC_DESC_TAG 0x00010006
1298struct fc_rdp_bbc_desc {
1299 uint32_t tag;
1300 uint32_t length;
1301 struct fc_rdp_bbc_info bbc_info;
1302};
1303
1304/* Optical Element Type Transgression Flags */
1305#define RDP_OET_LOW_WARNING 0x1
1306#define RDP_OET_HIGH_WARNING 0x2
1307#define RDP_OET_LOW_ALARM 0x4
1308#define RDP_OET_HIGH_ALARM 0x8
1309
1310#define RDP_OED_TEMPERATURE 0x1
1311#define RDP_OED_VOLTAGE 0x2
1312#define RDP_OED_TXBIAS 0x3
1313#define RDP_OED_TXPOWER 0x4
1314#define RDP_OED_RXPOWER 0x5
1315
1316#define RDP_OED_TYPE_SHIFT 28
1317/* Optical Element Data descriptor */
1318struct fc_rdp_oed_info {
1319 uint16_t hi_alarm;
1320 uint16_t lo_alarm;
1321 uint16_t hi_warning;
1322 uint16_t lo_warning;
1323 uint32_t function_flags;
1324};
1325#define RDP_OED_DESC_TAG 0x00010007
1326struct fc_rdp_oed_sfp_desc {
1327 uint32_t tag;
1328 uint32_t length;
1329 struct fc_rdp_oed_info oed_info;
1330};
1331
1332/* Optical Product Data descriptor */
1333struct fc_rdp_opd_sfp_info {
1334 uint8_t vendor_name[16];
1335 uint8_t model_number[16];
1336 uint8_t serial_number[16];
1337 uint8_t revision[4];
1338 uint8_t date[8];
1339};
1340
1341#define RDP_OPD_DESC_TAG 0x00010008
1342struct fc_rdp_opd_sfp_desc {
1343 uint32_t tag;
1344 uint32_t length;
1345 struct fc_rdp_opd_sfp_info opd_info;
1346};
1347
1348struct fc_rdp_req_frame {
1349 uint32_t rdp_command; /* ELS command opcode (0x18)*/
1350 uint32_t rdp_des_length; /* RDP Payload Word 1 */
1351 struct fc_rdp_nport_desc nport_id_desc; /* RDP Payload Word 2 - 4 */
1352};
1353
1354
1355struct fc_rdp_res_frame {
1356 uint32_t reply_sequence; /* FC word0 LS_ACC or LS_RJT */
1357 uint32_t length; /* FC Word 1 */
1358 struct fc_rdp_link_service_desc link_service_desc; /* Word 2 -4 */
1359 struct fc_rdp_sfp_desc sfp_desc; /* Word 5 -9 */
1360 struct fc_rdp_port_speed_desc portspeed_desc; /* Word 10 -12 */
1361 struct fc_rdp_link_error_status_desc link_error_desc; /* Word 13 -21 */
1362 struct fc_rdp_port_name_desc diag_port_names_desc; /* Word 22 -27 */
1363 struct fc_rdp_port_name_desc attached_port_names_desc;/* Word 28 -33 */
1364 struct fc_fec_rdp_desc fec_desc; /* FC word 34-37*/
1365 struct fc_rdp_bbc_desc bbc_desc; /* FC Word 38-42*/
1366 struct fc_rdp_oed_sfp_desc oed_temp_desc; /* FC Word 43-47*/
1367 struct fc_rdp_oed_sfp_desc oed_voltage_desc; /* FC word 48-52*/
1368 struct fc_rdp_oed_sfp_desc oed_txbias_desc; /* FC word 53-57*/
1369 struct fc_rdp_oed_sfp_desc oed_txpower_desc; /* FC word 58-62*/
1370 struct fc_rdp_oed_sfp_desc oed_rxpower_desc; /* FC word 63-67*/
1371 struct fc_rdp_opd_sfp_desc opd_desc; /* FC word 68-84*/
1372};
1373
1374
1375/* UVEM */
1376
1377#define LPFC_UVEM_SIZE 60
1378#define LPFC_UVEM_VEM_ID_DESC_SIZE 16
1379#define LPFC_UVEM_VE_MAP_DESC_SIZE 20
1380
1381#define VEM_ID_DESC_TAG 0x0001000A
1382struct lpfc_vem_id_desc {
1383 uint32_t tag;
1384 uint32_t length;
1385 uint8_t vem_id[16];
1386};
1387
1388#define LPFC_QFPA_SIZE 4
1389
1390#define INSTANTIATED_VE_DESC_TAG 0x0001000B
1391struct instantiated_ve_desc {
1392 uint32_t tag;
1393 uint32_t length;
1394 uint8_t global_vem_id[16];
1395 uint32_t word6;
1396#define lpfc_instantiated_local_id_SHIFT 0
1397#define lpfc_instantiated_local_id_MASK 0x000000ff
1398#define lpfc_instantiated_local_id_WORD word6
1399#define lpfc_instantiated_nport_id_SHIFT 8
1400#define lpfc_instantiated_nport_id_MASK 0x00ffffff
1401#define lpfc_instantiated_nport_id_WORD word6
1402};
1403
1404#define DEINSTANTIATED_VE_DESC_TAG 0x0001000C
1405struct deinstantiated_ve_desc {
1406 uint32_t tag;
1407 uint32_t length;
1408 uint8_t global_vem_id[16];
1409 uint32_t word6;
1410#define lpfc_deinstantiated_nport_id_SHIFT 0
1411#define lpfc_deinstantiated_nport_id_MASK 0x000000ff
1412#define lpfc_deinstantiated_nport_id_WORD word6
1413#define lpfc_deinstantiated_local_id_SHIFT 24
1414#define lpfc_deinstantiated_local_id_MASK 0x00ffffff
1415#define lpfc_deinstantiated_local_id_WORD word6
1416};
1417
1418/* Query Fabric Priority Allocation Response */
1419#define LPFC_PRIORITY_RANGE_DESC_SIZE 12
1420
1421struct priority_range_desc {
1422 uint32_t tag;
1423 uint32_t length;
1424 uint8_t lo_range;
1425 uint8_t hi_range;
1426 uint8_t qos_priority;
1427 uint8_t local_ve_id;
1428};
1429
1430struct fc_qfpa_res {
1431 uint32_t reply_sequence; /* LS_ACC or LS_RJT */
1432 uint32_t length; /* FC Word 1 */
1433 struct priority_range_desc desc[1];
1434};
1435
1436/* Application Server command code */
1437/* VMID */
1438
1439#define SLI_CT_APP_SEV_Subtypes 0x20 /* Application Server subtype */
1440
1441#define SLI_CTAS_GAPPIA_ENT 0x0100 /* Get Application Identifier */
1442#define SLI_CTAS_GALLAPPIA 0x0101 /* Get All Application Identifier */
1443#define SLI_CTAS_GALLAPPIA_ID 0x0102 /* Get All Application Identifier */
1444 /* for Nport */
1445#define SLI_CTAS_GAPPIA_IDAPP 0x0103 /* Get Application Identifier */
1446 /* for Nport */
1447#define SLI_CTAS_RAPP_IDENT 0x0200 /* Register Application Identifier */
1448#define SLI_CTAS_DAPP_IDENT 0x0300 /* Deregister Application */
1449 /* Identifier */
1450#define SLI_CTAS_DALLAPP_ID 0x0301 /* Deregister All Application */
1451 /* Identifier */
1452
1453struct entity_id_object {
1454 uint8_t entity_id_len;
1455 uint8_t entity_id[255]; /* VM UUID */
1456};
1457
1458struct app_id_object {
1459 __be32 port_id;
1460 __be32 app_id;
1461 struct entity_id_object obj;
1462};
1463
1464struct lpfc_vmid_rapp_ident_list {
1465 __be32 no_of_objects;
1466 struct entity_id_object obj[];
1467};
1468
1469struct lpfc_vmid_dapp_ident_list {
1470 __be32 no_of_objects;
1471 struct entity_id_object obj[];
1472};
1473
1474#define GALLAPPIA_ID_LAST 0x80
1475struct lpfc_vmid_gallapp_ident_list {
1476 uint8_t control;
1477 uint8_t reserved[3];
1478 struct app_id_object app_id;
1479};
1480
1481#define RAPP_IDENT_OFFSET (offsetof(struct lpfc_sli_ct_request, un) + 4)
1482#define DAPP_IDENT_OFFSET (offsetof(struct lpfc_sli_ct_request, un) + 4)
1483#define GALLAPPIA_ID_SIZE (offsetof(struct lpfc_sli_ct_request, un) + 4)
1484#define DALLAPP_ID_SIZE (offsetof(struct lpfc_sli_ct_request, un) + 4)
1485
1486/******** FDMI ********/
1487
1488/* lpfc_sli_ct_request defines the CT_IU preamble for FDMI commands */
1489#define SLI_CT_FDMI_Subtypes 0x10 /* Management Service Subtype */
1490
1491/* Definitions for HBA / Port attribute entries */
1492
1493/* Attribute Entry Structures */
1494
1495struct lpfc_fdmi_attr_u32 {
1496 __be16 type;
1497 __be16 len;
1498 __be32 value_u32;
1499};
1500
1501struct lpfc_fdmi_attr_wwn {
1502 __be16 type;
1503 __be16 len;
1504
1505 /* Keep as u8[8] instead of __be64 to avoid accidental zero padding
1506 * by compiler
1507 */
1508 u8 name[8];
1509};
1510
1511struct lpfc_fdmi_attr_fullwwn {
1512 __be16 type;
1513 __be16 len;
1514
1515 /* Keep as u8[8] instead of __be64 to avoid accidental zero padding
1516 * by compiler
1517 */
1518 u8 nname[8];
1519 u8 pname[8];
1520};
1521
1522struct lpfc_fdmi_attr_fc4types {
1523 __be16 type;
1524 __be16 len;
1525 u8 value_types[32];
1526};
1527
1528struct lpfc_fdmi_attr_string {
1529 __be16 type;
1530 __be16 len;
1531 char value_string[256];
1532};
1533
1534/* Maximum FDMI attribute length is Type+Len (4 bytes) + 256 byte string */
1535#define FDMI_MAX_ATTRLEN sizeof(struct lpfc_fdmi_attr_string)
1536
1537/*
1538 * HBA Attribute Block
1539 */
1540struct lpfc_fdmi_attr_block {
1541 uint32_t EntryCnt; /* Number of HBA attribute entries */
1542 /* Variable Length Attribute Entry TLV's follow */
1543};
1544
1545/*
1546 * Port Entry
1547 */
1548struct lpfc_fdmi_port_entry {
1549 struct lpfc_name PortName;
1550};
1551
1552/*
1553 * HBA Identifier
1554 */
1555struct lpfc_fdmi_hba_ident {
1556 struct lpfc_name PortName;
1557};
1558
1559/*
1560 * Registered Port List Format
1561 */
1562struct lpfc_fdmi_reg_port_list {
1563 __be32 EntryCnt;
1564 struct lpfc_fdmi_port_entry pe;
1565};
1566
1567/*
1568 * Register HBA(RHBA)
1569 */
1570struct lpfc_fdmi_reg_hba {
1571 struct lpfc_fdmi_hba_ident hi;
1572 struct lpfc_fdmi_reg_port_list rpl;
1573};
1574
1575/******** MI MIB ********/
1576#define SLI_CT_MIB_Subtypes 0x11
1577
1578/*
1579 * Register HBA Attributes (RHAT)
1580 */
1581struct lpfc_fdmi_reg_hbaattr {
1582 struct lpfc_name HBA_PortName;
1583 struct lpfc_fdmi_attr_block ab;
1584};
1585
1586/*
1587 * Register Port Attributes (RPA)
1588 */
1589struct lpfc_fdmi_reg_portattr {
1590 struct lpfc_name PortName;
1591 struct lpfc_fdmi_attr_block ab;
1592};
1593
1594/*
1595 * HBA MAnagement Operations Command Codes
1596 */
1597#define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */
1598#define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */
1599#define SLI_MGMT_GRPL 0x102 /* Get registered Port list */
1600#define SLI_MGMT_GPAT 0x110 /* Get Port attributes */
1601#define SLI_MGMT_GPAS 0x120 /* Get Port Statistics */
1602#define SLI_MGMT_RHBA 0x200 /* Register HBA */
1603#define SLI_MGMT_RHAT 0x201 /* Register HBA attributes */
1604#define SLI_MGMT_RPRT 0x210 /* Register Port */
1605#define SLI_MGMT_RPA 0x211 /* Register Port attributes */
1606#define SLI_MGMT_DHBA 0x300 /* De-register HBA */
1607#define SLI_MGMT_DHAT 0x301 /* De-register HBA attributes */
1608#define SLI_MGMT_DPRT 0x310 /* De-register Port */
1609#define SLI_MGMT_DPA 0x311 /* De-register Port attributes */
1610
1611#define LPFC_FDMI_MAX_RETRY 3 /* Max retries for a FDMI command */
1612
1613/*
1614 * HBA Attribute Types
1615 */
1616#define RHBA_NODENAME 0x1 /* 8 byte WWNN */
1617#define RHBA_MANUFACTURER 0x2 /* 4 to 64 byte ASCII string */
1618#define RHBA_SERIAL_NUMBER 0x3 /* 4 to 64 byte ASCII string */
1619#define RHBA_MODEL 0x4 /* 4 to 256 byte ASCII string */
1620#define RHBA_MODEL_DESCRIPTION 0x5 /* 4 to 256 byte ASCII string */
1621#define RHBA_HARDWARE_VERSION 0x6 /* 4 to 256 byte ASCII string */
1622#define RHBA_DRIVER_VERSION 0x7 /* 4 to 256 byte ASCII string */
1623#define RHBA_OPTION_ROM_VERSION 0x8 /* 4 to 256 byte ASCII string */
1624#define RHBA_FIRMWARE_VERSION 0x9 /* 4 to 256 byte ASCII string */
1625#define RHBA_OS_NAME_VERSION 0xa /* 4 to 256 byte ASCII string */
1626#define RHBA_MAX_CT_PAYLOAD_LEN 0xb /* 32-bit unsigned int */
1627#define RHBA_SYM_NODENAME 0xc /* 4 to 256 byte ASCII string */
1628#define RHBA_VENDOR_INFO 0xd /* 32-bit unsigned int */
1629#define RHBA_NUM_PORTS 0xe /* 32-bit unsigned int */
1630#define RHBA_FABRIC_WWNN 0xf /* 8 byte WWNN */
1631#define RHBA_BIOS_VERSION 0x10 /* 4 to 256 byte ASCII string */
1632#define RHBA_BIOS_STATE 0x11 /* 32-bit unsigned int */
1633#define RHBA_VENDOR_ID 0xe0 /* 8 byte ASCII string */
1634
1635/* Bit mask for all individual HBA attributes */
1636#define LPFC_FDMI_HBA_ATTR_wwnn 0x00000001
1637#define LPFC_FDMI_HBA_ATTR_manufacturer 0x00000002
1638#define LPFC_FDMI_HBA_ATTR_sn 0x00000004
1639#define LPFC_FDMI_HBA_ATTR_model 0x00000008
1640#define LPFC_FDMI_HBA_ATTR_description 0x00000010
1641#define LPFC_FDMI_HBA_ATTR_hdw_ver 0x00000020
1642#define LPFC_FDMI_HBA_ATTR_drvr_ver 0x00000040
1643#define LPFC_FDMI_HBA_ATTR_rom_ver 0x00000080
1644#define LPFC_FDMI_HBA_ATTR_fmw_ver 0x00000100
1645#define LPFC_FDMI_HBA_ATTR_os_ver 0x00000200
1646#define LPFC_FDMI_HBA_ATTR_ct_len 0x00000400
1647#define LPFC_FDMI_HBA_ATTR_symbolic_name 0x00000800
1648#define LPFC_FDMI_HBA_ATTR_vendor_info 0x00001000 /* Not used */
1649#define LPFC_FDMI_HBA_ATTR_num_ports 0x00002000
1650#define LPFC_FDMI_HBA_ATTR_fabric_wwnn 0x00004000
1651#define LPFC_FDMI_HBA_ATTR_bios_ver 0x00008000
1652#define LPFC_FDMI_HBA_ATTR_bios_state 0x00010000 /* Not used */
1653#define LPFC_FDMI_HBA_ATTR_vendor_id 0x00020000
1654
1655/* Bit mask for FDMI-1 defined HBA attributes */
1656#define LPFC_FDMI1_HBA_ATTR 0x000007ff
1657
1658/* Bit mask for FDMI-2 defined HBA attributes */
1659/* Skip vendor_info and bios_state */
1660#define LPFC_FDMI2_HBA_ATTR 0x0002efff
1661
1662/*
1663 * Port Attribute Types
1664 */
1665#define RPRT_SUPPORTED_FC4_TYPES 0x1 /* 32 byte binary array */
1666#define RPRT_SUPPORTED_SPEED 0x2 /* 32-bit unsigned int */
1667#define RPRT_PORT_SPEED 0x3 /* 32-bit unsigned int */
1668#define RPRT_MAX_FRAME_SIZE 0x4 /* 32-bit unsigned int */
1669#define RPRT_OS_DEVICE_NAME 0x5 /* 4 to 256 byte ASCII string */
1670#define RPRT_HOST_NAME 0x6 /* 4 to 256 byte ASCII string */
1671#define RPRT_NODENAME 0x7 /* 8 byte WWNN */
1672#define RPRT_PORTNAME 0x8 /* 8 byte WWPN */
1673#define RPRT_SYM_PORTNAME 0x9 /* 4 to 256 byte ASCII string */
1674#define RPRT_PORT_TYPE 0xa /* 32-bit unsigned int */
1675#define RPRT_SUPPORTED_CLASS 0xb /* 32-bit unsigned int */
1676#define RPRT_FABRICNAME 0xc /* 8 byte Fabric WWPN */
1677#define RPRT_ACTIVE_FC4_TYPES 0xd /* 32 byte binary array */
1678#define RPRT_PORT_STATE 0x101 /* 32-bit unsigned int */
1679#define RPRT_DISC_PORT 0x102 /* 32-bit unsigned int */
1680#define RPRT_PORT_ID 0x103 /* 32-bit unsigned int */
1681#define RPRT_VENDOR_MI 0xf047 /* vendor ascii string */
1682#define RPRT_SMART_SERVICE 0xf100 /* 4 to 256 byte ASCII string */
1683#define RPRT_SMART_GUID 0xf101 /* 8 byte WWNN + 8 byte WWPN */
1684#define RPRT_SMART_VERSION 0xf102 /* 4 to 256 byte ASCII string */
1685#define RPRT_SMART_MODEL 0xf103 /* 4 to 256 byte ASCII string */
1686#define RPRT_SMART_PORT_INFO 0xf104 /* 32-bit unsigned int */
1687#define RPRT_SMART_QOS 0xf105 /* 32-bit unsigned int */
1688#define RPRT_SMART_SECURITY 0xf106 /* 32-bit unsigned int */
1689
1690/* Bit mask for all individual PORT attributes */
1691#define LPFC_FDMI_PORT_ATTR_fc4type 0x00000001
1692#define LPFC_FDMI_PORT_ATTR_support_speed 0x00000002
1693#define LPFC_FDMI_PORT_ATTR_speed 0x00000004
1694#define LPFC_FDMI_PORT_ATTR_max_frame 0x00000008
1695#define LPFC_FDMI_PORT_ATTR_os_devname 0x00000010
1696#define LPFC_FDMI_PORT_ATTR_host_name 0x00000020
1697#define LPFC_FDMI_PORT_ATTR_wwnn 0x00000040
1698#define LPFC_FDMI_PORT_ATTR_wwpn 0x00000080
1699#define LPFC_FDMI_PORT_ATTR_symbolic_name 0x00000100
1700#define LPFC_FDMI_PORT_ATTR_port_type 0x00000200
1701#define LPFC_FDMI_PORT_ATTR_class 0x00000400
1702#define LPFC_FDMI_PORT_ATTR_fabric_wwpn 0x00000800
1703#define LPFC_FDMI_PORT_ATTR_port_state 0x00001000
1704#define LPFC_FDMI_PORT_ATTR_active_fc4type 0x00002000
1705#define LPFC_FDMI_PORT_ATTR_num_disc 0x00004000
1706#define LPFC_FDMI_PORT_ATTR_nportid 0x00008000
1707#define LPFC_FDMI_SMART_ATTR_service 0x00010000 /* Vendor specific */
1708#define LPFC_FDMI_SMART_ATTR_guid 0x00020000 /* Vendor specific */
1709#define LPFC_FDMI_SMART_ATTR_version 0x00040000 /* Vendor specific */
1710#define LPFC_FDMI_SMART_ATTR_model 0x00080000 /* Vendor specific */
1711#define LPFC_FDMI_SMART_ATTR_port_info 0x00100000 /* Vendor specific */
1712#define LPFC_FDMI_SMART_ATTR_qos 0x00200000 /* Vendor specific */
1713#define LPFC_FDMI_SMART_ATTR_security 0x00400000 /* Vendor specific */
1714#define LPFC_FDMI_VENDOR_ATTR_mi 0x00800000 /* Vendor specific */
1715
1716/* Bit mask for FDMI-1 defined PORT attributes */
1717#define LPFC_FDMI1_PORT_ATTR 0x0000003f
1718
1719/* Bit mask for FDMI-2 defined PORT attributes */
1720#define LPFC_FDMI2_PORT_ATTR 0x0000ffff
1721
1722/* Bit mask for Smart SAN defined PORT attributes */
1723#define LPFC_FDMI2_SMART_ATTR 0x007fffff
1724
1725/* Defines for PORT port state attribute */
1726#define LPFC_FDMI_PORTSTATE_UNKNOWN 1
1727#define LPFC_FDMI_PORTSTATE_ONLINE 2
1728
1729/* Defines for PORT port type attribute */
1730#define LPFC_FDMI_PORTTYPE_UNKNOWN 0
1731#define LPFC_FDMI_PORTTYPE_NPORT 1
1732#define LPFC_FDMI_PORTTYPE_NLPORT 2
1733
1734/*
1735 * Begin HBA configuration parameters.
1736 * The PCI configuration register BAR assignments are:
1737 * BAR0, offset 0x10 - SLIM base memory address
1738 * BAR1, offset 0x14 - SLIM base memory high address
1739 * BAR2, offset 0x18 - REGISTER base memory address
1740 * BAR3, offset 0x1c - REGISTER base memory high address
1741 * BAR4, offset 0x20 - BIU I/O registers
1742 * BAR5, offset 0x24 - REGISTER base io high address
1743 */
1744
1745/* Number of rings currently used and available. */
1746#define MAX_SLI3_CONFIGURED_RINGS 3
1747#define MAX_SLI3_RINGS 4
1748
1749/* IOCB / Mailbox is owned by FireFly */
1750#define OWN_CHIP 1
1751
1752/* IOCB / Mailbox is owned by Host */
1753#define OWN_HOST 0
1754
1755/* Number of 4-byte words in an IOCB. */
1756#define IOCB_WORD_SZ 8
1757
1758/* network headers for Dfctl field */
1759#define FC_NET_HDR 0x20
1760
1761/* Start FireFly Register definitions */
1762#define PCI_VENDOR_ID_EMULEX 0x10df
1763#define PCI_DEVICE_ID_FIREFLY 0x1ae5
1764#define PCI_DEVICE_ID_PROTEUS_VF 0xe100
1765#define PCI_DEVICE_ID_BALIUS 0xe131
1766#define PCI_DEVICE_ID_PROTEUS_PF 0xe180
1767#define PCI_DEVICE_ID_LANCER_FC 0xe200
1768#define PCI_DEVICE_ID_LANCER_FC_VF 0xe208
1769#define PCI_DEVICE_ID_LANCER_FCOE 0xe260
1770#define PCI_DEVICE_ID_LANCER_FCOE_VF 0xe268
1771#define PCI_DEVICE_ID_LANCER_G6_FC 0xe300
1772#define PCI_DEVICE_ID_LANCER_G7_FC 0xf400
1773#define PCI_DEVICE_ID_LANCER_G7P_FC 0xf500
1774#define PCI_DEVICE_ID_LANCER_G8_FC 0xd300
1775#define PCI_DEVICE_ID_SAT_SMB 0xf011
1776#define PCI_DEVICE_ID_SAT_MID 0xf015
1777#define PCI_DEVICE_ID_RFLY 0xf095
1778#define PCI_DEVICE_ID_PFLY 0xf098
1779#define PCI_DEVICE_ID_LP101 0xf0a1
1780#define PCI_DEVICE_ID_TFLY 0xf0a5
1781#define PCI_DEVICE_ID_BSMB 0xf0d1
1782#define PCI_DEVICE_ID_BMID 0xf0d5
1783#define PCI_DEVICE_ID_ZSMB 0xf0e1
1784#define PCI_DEVICE_ID_ZMID 0xf0e5
1785#define PCI_DEVICE_ID_NEPTUNE 0xf0f5
1786#define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6
1787#define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7
1788#define PCI_DEVICE_ID_SAT 0xf100
1789#define PCI_DEVICE_ID_SAT_SCSP 0xf111
1790#define PCI_DEVICE_ID_SAT_DCSP 0xf112
1791#define PCI_DEVICE_ID_FALCON 0xf180
1792#define PCI_DEVICE_ID_SUPERFLY 0xf700
1793#define PCI_DEVICE_ID_DRAGONFLY 0xf800
1794#define PCI_DEVICE_ID_CENTAUR 0xf900
1795#define PCI_DEVICE_ID_PEGASUS 0xf980
1796#define PCI_DEVICE_ID_THOR 0xfa00
1797#define PCI_DEVICE_ID_VIPER 0xfb00
1798#define PCI_DEVICE_ID_LP10000S 0xfc00
1799#define PCI_DEVICE_ID_LP11000S 0xfc10
1800#define PCI_DEVICE_ID_LPE11000S 0xfc20
1801#define PCI_DEVICE_ID_SAT_S 0xfc40
1802#define PCI_DEVICE_ID_PROTEUS_S 0xfc50
1803#define PCI_DEVICE_ID_HELIOS 0xfd00
1804#define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11
1805#define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12
1806#define PCI_DEVICE_ID_ZEPHYR 0xfe00
1807#define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11
1808#define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12
1809#define PCI_VENDOR_ID_SERVERENGINE 0x19a2
1810#define PCI_DEVICE_ID_TIGERSHARK 0x0704
1811#define PCI_DEVICE_ID_TOMCAT 0x0714
1812#define PCI_DEVICE_ID_SKYHAWK 0x0724
1813#define PCI_DEVICE_ID_SKYHAWK_VF 0x072c
1814#define PCI_VENDOR_ID_ATTO 0x117c
1815#define PCI_DEVICE_ID_CLRY_16XE 0x0064
1816#define PCI_DEVICE_ID_CLRY_161E 0x0063
1817#define PCI_DEVICE_ID_CLRY_162E 0x0064
1818#define PCI_DEVICE_ID_CLRY_164E 0x0065
1819#define PCI_DEVICE_ID_CLRY_16XP 0x0094
1820#define PCI_DEVICE_ID_CLRY_161P 0x00a0
1821#define PCI_DEVICE_ID_CLRY_162P 0x0094
1822#define PCI_DEVICE_ID_CLRY_164P 0x00a1
1823#define PCI_DEVICE_ID_CLRY_32XE 0x0094
1824#define PCI_DEVICE_ID_CLRY_321E 0x00a2
1825#define PCI_DEVICE_ID_CLRY_322E 0x00a3
1826#define PCI_DEVICE_ID_CLRY_324E 0x00ac
1827#define PCI_DEVICE_ID_CLRY_32XP 0x00bb
1828#define PCI_DEVICE_ID_CLRY_321P 0x00bc
1829#define PCI_DEVICE_ID_CLRY_322P 0x00bd
1830#define PCI_DEVICE_ID_CLRY_324P 0x00be
1831#define PCI_DEVICE_ID_TLFC_2 0x0064
1832#define PCI_DEVICE_ID_TLFC_2XX2 0x4064
1833#define PCI_DEVICE_ID_TLFC_3 0x0094
1834#define PCI_DEVICE_ID_TLFC_3162 0x40a6
1835#define PCI_DEVICE_ID_TLFC_3322 0x40a7
1836
1837#define JEDEC_ID_ADDRESS 0x0080001c
1838#define FIREFLY_JEDEC_ID 0x1ACC
1839#define SUPERFLY_JEDEC_ID 0x0020
1840#define DRAGONFLY_JEDEC_ID 0x0021
1841#define DRAGONFLY_V2_JEDEC_ID 0x0025
1842#define CENTAUR_2G_JEDEC_ID 0x0026
1843#define CENTAUR_1G_JEDEC_ID 0x0028
1844#define PEGASUS_ORION_JEDEC_ID 0x0036
1845#define PEGASUS_JEDEC_ID 0x0038
1846#define THOR_JEDEC_ID 0x0012
1847#define HELIOS_JEDEC_ID 0x0364
1848#define ZEPHYR_JEDEC_ID 0x0577
1849#define VIPER_JEDEC_ID 0x4838
1850#define SATURN_JEDEC_ID 0x1004
1851
1852#define JEDEC_ID_MASK 0x0FFFF000
1853#define JEDEC_ID_SHIFT 12
1854#define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT)
1855
1856typedef struct { /* FireFly BIU registers */
1857 uint32_t hostAtt; /* See definitions for Host Attention
1858 register */
1859 uint32_t chipAtt; /* See definitions for Chip Attention
1860 register */
1861 uint32_t hostStatus; /* See definitions for Host Status register */
1862 uint32_t hostControl; /* See definitions for Host Control register */
1863 uint32_t buiConfig; /* See definitions for BIU configuration
1864 register */
1865} FF_REGS;
1866
1867/* IO Register size in bytes */
1868#define FF_REG_AREA_SIZE 256
1869
1870/* Host Attention Register */
1871
1872#define HA_REG_OFFSET 0 /* Byte offset from register base address */
1873
1874#define HA_R0RE_REQ 0x00000001 /* Bit 0 */
1875#define HA_R0CE_RSP 0x00000002 /* Bit 1 */
1876#define HA_R0ATT 0x00000008 /* Bit 3 */
1877#define HA_R1RE_REQ 0x00000010 /* Bit 4 */
1878#define HA_R1CE_RSP 0x00000020 /* Bit 5 */
1879#define HA_R1ATT 0x00000080 /* Bit 7 */
1880#define HA_R2RE_REQ 0x00000100 /* Bit 8 */
1881#define HA_R2CE_RSP 0x00000200 /* Bit 9 */
1882#define HA_R2ATT 0x00000800 /* Bit 11 */
1883#define HA_R3RE_REQ 0x00001000 /* Bit 12 */
1884#define HA_R3CE_RSP 0x00002000 /* Bit 13 */
1885#define HA_R3ATT 0x00008000 /* Bit 15 */
1886#define HA_LATT 0x20000000 /* Bit 29 */
1887#define HA_MBATT 0x40000000 /* Bit 30 */
1888#define HA_ERATT 0x80000000 /* Bit 31 */
1889
1890#define HA_RXRE_REQ 0x00000001 /* Bit 0 */
1891#define HA_RXCE_RSP 0x00000002 /* Bit 1 */
1892#define HA_RXATT 0x00000008 /* Bit 3 */
1893#define HA_RXMASK 0x0000000f
1894
1895#define HA_R0_CLR_MSK (HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT)
1896#define HA_R1_CLR_MSK (HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT)
1897#define HA_R2_CLR_MSK (HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT)
1898#define HA_R3_CLR_MSK (HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT)
1899
1900#define HA_R0_POS 3
1901#define HA_R1_POS 7
1902#define HA_R2_POS 11
1903#define HA_R3_POS 15
1904#define HA_LE_POS 29
1905#define HA_MB_POS 30
1906#define HA_ER_POS 31
1907/* Chip Attention Register */
1908
1909#define CA_REG_OFFSET 4 /* Byte offset from register base address */
1910
1911#define CA_R0CE_REQ 0x00000001 /* Bit 0 */
1912#define CA_R0RE_RSP 0x00000002 /* Bit 1 */
1913#define CA_R0ATT 0x00000008 /* Bit 3 */
1914#define CA_R1CE_REQ 0x00000010 /* Bit 4 */
1915#define CA_R1RE_RSP 0x00000020 /* Bit 5 */
1916#define CA_R1ATT 0x00000080 /* Bit 7 */
1917#define CA_R2CE_REQ 0x00000100 /* Bit 8 */
1918#define CA_R2RE_RSP 0x00000200 /* Bit 9 */
1919#define CA_R2ATT 0x00000800 /* Bit 11 */
1920#define CA_R3CE_REQ 0x00001000 /* Bit 12 */
1921#define CA_R3RE_RSP 0x00002000 /* Bit 13 */
1922#define CA_R3ATT 0x00008000 /* Bit 15 */
1923#define CA_MBATT 0x40000000 /* Bit 30 */
1924
1925/* Host Status Register */
1926
1927#define HS_REG_OFFSET 8 /* Byte offset from register base address */
1928
1929#define HS_MBRDY 0x00400000 /* Bit 22 */
1930#define HS_FFRDY 0x00800000 /* Bit 23 */
1931#define HS_FFER8 0x01000000 /* Bit 24 */
1932#define HS_FFER7 0x02000000 /* Bit 25 */
1933#define HS_FFER6 0x04000000 /* Bit 26 */
1934#define HS_FFER5 0x08000000 /* Bit 27 */
1935#define HS_FFER4 0x10000000 /* Bit 28 */
1936#define HS_FFER3 0x20000000 /* Bit 29 */
1937#define HS_FFER2 0x40000000 /* Bit 30 */
1938#define HS_FFER1 0x80000000 /* Bit 31 */
1939#define HS_CRIT_TEMP 0x00000100 /* Bit 8 */
1940#define HS_FFERM 0xFF000100 /* Mask for error bits 31:24 and 8 */
1941#define UNPLUG_ERR 0x00000001 /* Indicate pci hot unplug */
1942/* Host Control Register */
1943
1944#define HC_REG_OFFSET 12 /* Byte offset from register base address */
1945
1946#define HC_MBINT_ENA 0x00000001 /* Bit 0 */
1947#define HC_R0INT_ENA 0x00000002 /* Bit 1 */
1948#define HC_R1INT_ENA 0x00000004 /* Bit 2 */
1949#define HC_R2INT_ENA 0x00000008 /* Bit 3 */
1950#define HC_R3INT_ENA 0x00000010 /* Bit 4 */
1951#define HC_INITHBI 0x02000000 /* Bit 25 */
1952#define HC_INITMB 0x04000000 /* Bit 26 */
1953#define HC_INITFF 0x08000000 /* Bit 27 */
1954#define HC_LAINT_ENA 0x20000000 /* Bit 29 */
1955#define HC_ERINT_ENA 0x80000000 /* Bit 31 */
1956
1957/* Message Signaled Interrupt eXtension (MSI-X) message identifiers */
1958#define MSIX_DFLT_ID 0
1959#define MSIX_RNG0_ID 0
1960#define MSIX_RNG1_ID 1
1961#define MSIX_RNG2_ID 2
1962#define MSIX_RNG3_ID 3
1963
1964#define MSIX_LINK_ID 4
1965#define MSIX_MBOX_ID 5
1966
1967#define MSIX_SPARE0_ID 6
1968#define MSIX_SPARE1_ID 7
1969
1970/* Mailbox Commands */
1971#define MBX_SHUTDOWN 0x00 /* terminate testing */
1972#define MBX_LOAD_SM 0x01
1973#define MBX_READ_NV 0x02
1974#define MBX_WRITE_NV 0x03
1975#define MBX_RUN_BIU_DIAG 0x04
1976#define MBX_INIT_LINK 0x05
1977#define MBX_DOWN_LINK 0x06
1978#define MBX_CONFIG_LINK 0x07
1979#define MBX_CONFIG_RING 0x09
1980#define MBX_RESET_RING 0x0A
1981#define MBX_READ_CONFIG 0x0B
1982#define MBX_READ_RCONFIG 0x0C
1983#define MBX_READ_SPARM 0x0D
1984#define MBX_READ_STATUS 0x0E
1985#define MBX_READ_RPI 0x0F
1986#define MBX_READ_XRI 0x10
1987#define MBX_READ_REV 0x11
1988#define MBX_READ_LNK_STAT 0x12
1989#define MBX_REG_LOGIN 0x13
1990#define MBX_UNREG_LOGIN 0x14
1991#define MBX_CLEAR_LA 0x16
1992#define MBX_DUMP_MEMORY 0x17
1993#define MBX_DUMP_CONTEXT 0x18
1994#define MBX_RUN_DIAGS 0x19
1995#define MBX_RESTART 0x1A
1996#define MBX_UPDATE_CFG 0x1B
1997#define MBX_DOWN_LOAD 0x1C
1998#define MBX_DEL_LD_ENTRY 0x1D
1999#define MBX_RUN_PROGRAM 0x1E
2000#define MBX_SET_MASK 0x20
2001#define MBX_SET_VARIABLE 0x21
2002#define MBX_UNREG_D_ID 0x23
2003#define MBX_KILL_BOARD 0x24
2004#define MBX_CONFIG_FARP 0x25
2005#define MBX_BEACON 0x2A
2006#define MBX_CONFIG_MSI 0x30
2007#define MBX_HEARTBEAT 0x31
2008#define MBX_WRITE_VPARMS 0x32
2009#define MBX_ASYNCEVT_ENABLE 0x33
2010#define MBX_READ_EVENT_LOG_STATUS 0x37
2011#define MBX_READ_EVENT_LOG 0x38
2012#define MBX_WRITE_EVENT_LOG 0x39
2013
2014#define MBX_PORT_CAPABILITIES 0x3B
2015#define MBX_PORT_IOV_CONTROL 0x3C
2016
2017#define MBX_CONFIG_HBQ 0x7C
2018#define MBX_LOAD_AREA 0x81
2019#define MBX_RUN_BIU_DIAG64 0x84
2020#define MBX_CONFIG_PORT 0x88
2021#define MBX_READ_SPARM64 0x8D
2022#define MBX_READ_RPI64 0x8F
2023#define MBX_REG_LOGIN64 0x93
2024#define MBX_READ_TOPOLOGY 0x95
2025#define MBX_REG_VPI 0x96
2026#define MBX_UNREG_VPI 0x97
2027
2028#define MBX_WRITE_WWN 0x98
2029#define MBX_SET_DEBUG 0x99
2030#define MBX_LOAD_EXP_ROM 0x9C
2031#define MBX_SLI4_CONFIG 0x9B
2032#define MBX_SLI4_REQ_FTRS 0x9D
2033#define MBX_MAX_CMDS 0x9E
2034#define MBX_RESUME_RPI 0x9E
2035#define MBX_SLI2_CMD_MASK 0x80
2036#define MBX_REG_VFI 0x9F
2037#define MBX_REG_FCFI 0xA0
2038#define MBX_UNREG_VFI 0xA1
2039#define MBX_UNREG_FCFI 0xA2
2040#define MBX_INIT_VFI 0xA3
2041#define MBX_INIT_VPI 0xA4
2042#define MBX_ACCESS_VDATA 0xA5
2043#define MBX_REG_FCFI_MRQ 0xAF
2044
2045#define MBX_AUTH_PORT 0xF8
2046#define MBX_SECURITY_MGMT 0xF9
2047
2048/* IOCB Commands */
2049
2050#define CMD_RCV_SEQUENCE_CX 0x01
2051#define CMD_XMIT_SEQUENCE_CR 0x02
2052#define CMD_XMIT_SEQUENCE_CX 0x03
2053#define CMD_XMIT_BCAST_CN 0x04
2054#define CMD_XMIT_BCAST_CX 0x05
2055#define CMD_QUE_RING_BUF_CN 0x06
2056#define CMD_QUE_XRI_BUF_CX 0x07
2057#define CMD_IOCB_CONTINUE_CN 0x08
2058#define CMD_RET_XRI_BUF_CX 0x09
2059#define CMD_ELS_REQUEST_CR 0x0A
2060#define CMD_ELS_REQUEST_CX 0x0B
2061#define CMD_RCV_ELS_REQ_CX 0x0D
2062#define CMD_ABORT_XRI_CN 0x0E
2063#define CMD_ABORT_XRI_CX 0x0F
2064#define CMD_CLOSE_XRI_CN 0x10
2065#define CMD_CLOSE_XRI_CX 0x11
2066#define CMD_CREATE_XRI_CR 0x12
2067#define CMD_CREATE_XRI_CX 0x13
2068#define CMD_GET_RPI_CN 0x14
2069#define CMD_XMIT_ELS_RSP_CX 0x15
2070#define CMD_GET_RPI_CR 0x16
2071#define CMD_XRI_ABORTED_CX 0x17
2072#define CMD_FCP_IWRITE_CR 0x18
2073#define CMD_FCP_IWRITE_CX 0x19
2074#define CMD_FCP_IREAD_CR 0x1A
2075#define CMD_FCP_IREAD_CX 0x1B
2076#define CMD_FCP_ICMND_CR 0x1C
2077#define CMD_FCP_ICMND_CX 0x1D
2078#define CMD_FCP_TSEND_CX 0x1F
2079#define CMD_FCP_TRECEIVE_CX 0x21
2080#define CMD_FCP_TRSP_CX 0x23
2081#define CMD_FCP_AUTO_TRSP_CX 0x29
2082
2083#define CMD_ADAPTER_MSG 0x20
2084#define CMD_ADAPTER_DUMP 0x22
2085
2086/* SLI_2 IOCB Command Set */
2087
2088#define CMD_ASYNC_STATUS 0x7C
2089#define CMD_RCV_SEQUENCE64_CX 0x81
2090#define CMD_XMIT_SEQUENCE64_CR 0x82
2091#define CMD_XMIT_SEQUENCE64_CX 0x83
2092#define CMD_XMIT_BCAST64_CN 0x84
2093#define CMD_XMIT_BCAST64_CX 0x85
2094#define CMD_QUE_RING_BUF64_CN 0x86
2095#define CMD_QUE_XRI_BUF64_CX 0x87
2096#define CMD_IOCB_CONTINUE64_CN 0x88
2097#define CMD_RET_XRI_BUF64_CX 0x89
2098#define CMD_ELS_REQUEST64_CR 0x8A
2099#define CMD_ELS_REQUEST64_CX 0x8B
2100#define CMD_ABORT_MXRI64_CN 0x8C
2101#define CMD_RCV_ELS_REQ64_CX 0x8D
2102#define CMD_XMIT_ELS_RSP64_CX 0x95
2103#define CMD_XMIT_BLS_RSP64_CX 0x97
2104#define CMD_FCP_IWRITE64_CR 0x98
2105#define CMD_FCP_IWRITE64_CX 0x99
2106#define CMD_FCP_IREAD64_CR 0x9A
2107#define CMD_FCP_IREAD64_CX 0x9B
2108#define CMD_FCP_ICMND64_CR 0x9C
2109#define CMD_FCP_ICMND64_CX 0x9D
2110#define CMD_FCP_TSEND64_CX 0x9F
2111#define CMD_FCP_TRECEIVE64_CX 0xA1
2112#define CMD_FCP_TRSP64_CX 0xA3
2113
2114#define CMD_QUE_XRI64_CX 0xB3
2115#define CMD_IOCB_RCV_SEQ64_CX 0xB5
2116#define CMD_IOCB_RCV_ELS64_CX 0xB7
2117#define CMD_IOCB_RET_XRI64_CX 0xB9
2118#define CMD_IOCB_RCV_CONT64_CX 0xBB
2119
2120#define CMD_GEN_REQUEST64_CR 0xC2
2121#define CMD_GEN_REQUEST64_CX 0xC3
2122
2123/* Unhandled SLI-3 Commands */
2124#define CMD_IOCB_XMIT_MSEQ64_CR 0xB0
2125#define CMD_IOCB_XMIT_MSEQ64_CX 0xB1
2126#define CMD_IOCB_RCV_SEQ_LIST64_CX 0xC1
2127#define CMD_IOCB_RCV_ELS_LIST64_CX 0xCD
2128#define CMD_IOCB_CLOSE_EXTENDED_CN 0xB6
2129#define CMD_IOCB_ABORT_EXTENDED_CN 0xBA
2130#define CMD_IOCB_RET_HBQE64_CN 0xCA
2131#define CMD_IOCB_FCP_IBIDIR64_CR 0xAC
2132#define CMD_IOCB_FCP_IBIDIR64_CX 0xAD
2133#define CMD_IOCB_FCP_ITASKMGT64_CX 0xAF
2134#define CMD_IOCB_LOGENTRY_CN 0x94
2135#define CMD_IOCB_LOGENTRY_ASYNC_CN 0x96
2136
2137/* Data Security SLI Commands */
2138#define DSSCMD_IWRITE64_CR 0xF8
2139#define DSSCMD_IWRITE64_CX 0xF9
2140#define DSSCMD_IREAD64_CR 0xFA
2141#define DSSCMD_IREAD64_CX 0xFB
2142
2143#define CMD_MAX_IOCB_CMD 0xFB
2144#define CMD_IOCB_MASK 0xff
2145
2146#define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG
2147 iocb */
2148#define LPFC_MAX_ADPTMSG 32 /* max msg data */
2149/*
2150 * Define Status
2151 */
2152#define MBX_SUCCESS 0
2153#define MBXERR_NUM_RINGS 1
2154#define MBXERR_NUM_IOCBS 2
2155#define MBXERR_IOCBS_EXCEEDED 3
2156#define MBXERR_BAD_RING_NUMBER 4
2157#define MBXERR_MASK_ENTRIES_RANGE 5
2158#define MBXERR_MASKS_EXCEEDED 6
2159#define MBXERR_BAD_PROFILE 7
2160#define MBXERR_BAD_DEF_CLASS 8
2161#define MBXERR_BAD_MAX_RESPONDER 9
2162#define MBXERR_BAD_MAX_ORIGINATOR 10
2163#define MBXERR_RPI_REGISTERED 11
2164#define MBXERR_RPI_FULL 12
2165#define MBXERR_NO_RESOURCES 13
2166#define MBXERR_BAD_RCV_LENGTH 14
2167#define MBXERR_DMA_ERROR 15
2168#define MBXERR_ERROR 16
2169#define MBXERR_LINK_DOWN 0x33
2170#define MBXERR_SEC_NO_PERMISSION 0xF02
2171#define MBX_NOT_FINISHED 255
2172
2173#define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */
2174#define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */
2175
2176#define TEMPERATURE_OFFSET 0xB0 /* Slim offset for critical temperature event */
2177
2178/*
2179 * return code Fail
2180 */
2181#define FAILURE 1
2182
2183/*
2184 * Begin Structure Definitions for Mailbox Commands
2185 */
2186
2187typedef struct {
2188#ifdef __BIG_ENDIAN_BITFIELD
2189 uint8_t tval;
2190 uint8_t tmask;
2191 uint8_t rval;
2192 uint8_t rmask;
2193#else /* __LITTLE_ENDIAN_BITFIELD */
2194 uint8_t rmask;
2195 uint8_t rval;
2196 uint8_t tmask;
2197 uint8_t tval;
2198#endif
2199} RR_REG;
2200
2201struct ulp_bde {
2202 uint32_t bdeAddress;
2203#ifdef __BIG_ENDIAN_BITFIELD
2204 uint32_t bdeReserved:4;
2205 uint32_t bdeAddrHigh:4;
2206 uint32_t bdeSize:24;
2207#else /* __LITTLE_ENDIAN_BITFIELD */
2208 uint32_t bdeSize:24;
2209 uint32_t bdeAddrHigh:4;
2210 uint32_t bdeReserved:4;
2211#endif
2212};
2213
2214typedef struct ULP_BDL { /* SLI-2 */
2215#ifdef __BIG_ENDIAN_BITFIELD
2216 uint32_t bdeFlags:8; /* BDL Flags */
2217 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
2218#else /* __LITTLE_ENDIAN_BITFIELD */
2219 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
2220 uint32_t bdeFlags:8; /* BDL Flags */
2221#endif
2222
2223 uint32_t addrLow; /* Address 0:31 */
2224 uint32_t addrHigh; /* Address 32:63 */
2225 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */
2226} ULP_BDL;
2227
2228/*
2229 * BlockGuard Definitions
2230 */
2231
2232enum lpfc_protgrp_type {
2233 LPFC_PG_TYPE_INVALID = 0, /* used to indicate errors */
2234 LPFC_PG_TYPE_NO_DIF, /* no DIF data pointed to by prot grp */
2235 LPFC_PG_TYPE_EMBD_DIF, /* DIF is embedded (inline) with data */
2236 LPFC_PG_TYPE_DIF_BUF /* DIF has its own scatter/gather list */
2237};
2238
2239/* PDE Descriptors */
2240#define LPFC_PDE5_DESCRIPTOR 0x85
2241#define LPFC_PDE6_DESCRIPTOR 0x86
2242#define LPFC_PDE7_DESCRIPTOR 0x87
2243
2244/* BlockGuard Opcodes */
2245#define BG_OP_IN_NODIF_OUT_CRC 0x0
2246#define BG_OP_IN_CRC_OUT_NODIF 0x1
2247#define BG_OP_IN_NODIF_OUT_CSUM 0x2
2248#define BG_OP_IN_CSUM_OUT_NODIF 0x3
2249#define BG_OP_IN_CRC_OUT_CRC 0x4
2250#define BG_OP_IN_CSUM_OUT_CSUM 0x5
2251#define BG_OP_IN_CRC_OUT_CSUM 0x6
2252#define BG_OP_IN_CSUM_OUT_CRC 0x7
2253#define BG_OP_RAW_MODE 0x8
2254
2255struct lpfc_pde5 {
2256 uint32_t word0;
2257#define pde5_type_SHIFT 24
2258#define pde5_type_MASK 0x000000ff
2259#define pde5_type_WORD word0
2260#define pde5_rsvd0_SHIFT 0
2261#define pde5_rsvd0_MASK 0x00ffffff
2262#define pde5_rsvd0_WORD word0
2263 uint32_t reftag; /* Reference Tag Value */
2264 uint32_t reftagtr; /* Reference Tag Translation Value */
2265};
2266
2267struct lpfc_pde6 {
2268 uint32_t word0;
2269#define pde6_type_SHIFT 24
2270#define pde6_type_MASK 0x000000ff
2271#define pde6_type_WORD word0
2272#define pde6_rsvd0_SHIFT 0
2273#define pde6_rsvd0_MASK 0x00ffffff
2274#define pde6_rsvd0_WORD word0
2275 uint32_t word1;
2276#define pde6_rsvd1_SHIFT 26
2277#define pde6_rsvd1_MASK 0x0000003f
2278#define pde6_rsvd1_WORD word1
2279#define pde6_na_SHIFT 25
2280#define pde6_na_MASK 0x00000001
2281#define pde6_na_WORD word1
2282#define pde6_rsvd2_SHIFT 16
2283#define pde6_rsvd2_MASK 0x000001FF
2284#define pde6_rsvd2_WORD word1
2285#define pde6_apptagtr_SHIFT 0
2286#define pde6_apptagtr_MASK 0x0000ffff
2287#define pde6_apptagtr_WORD word1
2288 uint32_t word2;
2289#define pde6_optx_SHIFT 28
2290#define pde6_optx_MASK 0x0000000f
2291#define pde6_optx_WORD word2
2292#define pde6_oprx_SHIFT 24
2293#define pde6_oprx_MASK 0x0000000f
2294#define pde6_oprx_WORD word2
2295#define pde6_nr_SHIFT 23
2296#define pde6_nr_MASK 0x00000001
2297#define pde6_nr_WORD word2
2298#define pde6_ce_SHIFT 22
2299#define pde6_ce_MASK 0x00000001
2300#define pde6_ce_WORD word2
2301#define pde6_re_SHIFT 21
2302#define pde6_re_MASK 0x00000001
2303#define pde6_re_WORD word2
2304#define pde6_ae_SHIFT 20
2305#define pde6_ae_MASK 0x00000001
2306#define pde6_ae_WORD word2
2307#define pde6_ai_SHIFT 19
2308#define pde6_ai_MASK 0x00000001
2309#define pde6_ai_WORD word2
2310#define pde6_bs_SHIFT 16
2311#define pde6_bs_MASK 0x00000007
2312#define pde6_bs_WORD word2
2313#define pde6_apptagval_SHIFT 0
2314#define pde6_apptagval_MASK 0x0000ffff
2315#define pde6_apptagval_WORD word2
2316};
2317
2318struct lpfc_pde7 {
2319 uint32_t word0;
2320#define pde7_type_SHIFT 24
2321#define pde7_type_MASK 0x000000ff
2322#define pde7_type_WORD word0
2323#define pde7_rsvd0_SHIFT 0
2324#define pde7_rsvd0_MASK 0x00ffffff
2325#define pde7_rsvd0_WORD word0
2326 uint32_t addrHigh;
2327 uint32_t addrLow;
2328};
2329
2330/* Structure for MB Command LOAD_SM and DOWN_LOAD */
2331
2332typedef struct {
2333#ifdef __BIG_ENDIAN_BITFIELD
2334 uint32_t rsvd2:25;
2335 uint32_t acknowledgment:1;
2336 uint32_t version:1;
2337 uint32_t erase_or_prog:1;
2338 uint32_t update_flash:1;
2339 uint32_t update_ram:1;
2340 uint32_t method:1;
2341 uint32_t load_cmplt:1;
2342#else /* __LITTLE_ENDIAN_BITFIELD */
2343 uint32_t load_cmplt:1;
2344 uint32_t method:1;
2345 uint32_t update_ram:1;
2346 uint32_t update_flash:1;
2347 uint32_t erase_or_prog:1;
2348 uint32_t version:1;
2349 uint32_t acknowledgment:1;
2350 uint32_t rsvd2:25;
2351#endif
2352
2353 uint32_t dl_to_adr_low;
2354 uint32_t dl_to_adr_high;
2355 uint32_t dl_len;
2356 union {
2357 uint32_t dl_from_mbx_offset;
2358 struct ulp_bde dl_from_bde;
2359 struct ulp_bde64 dl_from_bde64;
2360 } un;
2361
2362} LOAD_SM_VAR;
2363
2364/* Structure for MB Command READ_NVPARM (02) */
2365
2366typedef struct {
2367 uint32_t rsvd1[3]; /* Read as all one's */
2368 uint32_t rsvd2; /* Read as all zero's */
2369 uint32_t portname[2]; /* N_PORT name */
2370 uint32_t nodename[2]; /* NODE name */
2371
2372#ifdef __BIG_ENDIAN_BITFIELD
2373 uint32_t pref_DID:24;
2374 uint32_t hardAL_PA:8;
2375#else /* __LITTLE_ENDIAN_BITFIELD */
2376 uint32_t hardAL_PA:8;
2377 uint32_t pref_DID:24;
2378#endif
2379
2380 uint32_t rsvd3[21]; /* Read as all one's */
2381} READ_NV_VAR;
2382
2383/* Structure for MB Command WRITE_NVPARMS (03) */
2384
2385typedef struct {
2386 uint32_t rsvd1[3]; /* Must be all one's */
2387 uint32_t rsvd2; /* Must be all zero's */
2388 uint32_t portname[2]; /* N_PORT name */
2389 uint32_t nodename[2]; /* NODE name */
2390
2391#ifdef __BIG_ENDIAN_BITFIELD
2392 uint32_t pref_DID:24;
2393 uint32_t hardAL_PA:8;
2394#else /* __LITTLE_ENDIAN_BITFIELD */
2395 uint32_t hardAL_PA:8;
2396 uint32_t pref_DID:24;
2397#endif
2398
2399 uint32_t rsvd3[21]; /* Must be all one's */
2400} WRITE_NV_VAR;
2401
2402/* Structure for MB Command RUN_BIU_DIAG (04) */
2403/* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
2404
2405typedef struct {
2406 uint32_t rsvd1;
2407 union {
2408 struct {
2409 struct ulp_bde xmit_bde;
2410 struct ulp_bde rcv_bde;
2411 } s1;
2412 struct {
2413 struct ulp_bde64 xmit_bde64;
2414 struct ulp_bde64 rcv_bde64;
2415 } s2;
2416 } un;
2417} BIU_DIAG_VAR;
2418
2419/* Structure for MB command READ_EVENT_LOG (0x38) */
2420struct READ_EVENT_LOG_VAR {
2421 uint32_t word1;
2422#define lpfc_event_log_SHIFT 29
2423#define lpfc_event_log_MASK 0x00000001
2424#define lpfc_event_log_WORD word1
2425#define USE_MAILBOX_RESPONSE 1
2426 uint32_t offset;
2427 struct ulp_bde64 rcv_bde64;
2428};
2429
2430/* Structure for MB Command INIT_LINK (05) */
2431
2432typedef struct {
2433#ifdef __BIG_ENDIAN_BITFIELD
2434 uint32_t rsvd1:24;
2435 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
2436#else /* __LITTLE_ENDIAN_BITFIELD */
2437 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
2438 uint32_t rsvd1:24;
2439#endif
2440
2441#ifdef __BIG_ENDIAN_BITFIELD
2442 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
2443 uint8_t rsvd2;
2444 uint16_t link_flags;
2445#else /* __LITTLE_ENDIAN_BITFIELD */
2446 uint16_t link_flags;
2447 uint8_t rsvd2;
2448 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
2449#endif
2450
2451#define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */
2452#define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */
2453#define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */
2454#define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */
2455#define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */
2456#define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */
2457#define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */
2458
2459#define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */
2460#define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */
2461#define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */
2462
2463 uint32_t link_speed;
2464#define LINK_SPEED_AUTO 0x0 /* Auto selection */
2465#define LINK_SPEED_1G 0x1 /* 1 Gigabaud */
2466#define LINK_SPEED_2G 0x2 /* 2 Gigabaud */
2467#define LINK_SPEED_4G 0x4 /* 4 Gigabaud */
2468#define LINK_SPEED_8G 0x8 /* 8 Gigabaud */
2469#define LINK_SPEED_10G 0x10 /* 10 Gigabaud */
2470#define LINK_SPEED_16G 0x11 /* 16 Gigabaud */
2471#define LINK_SPEED_32G 0x14 /* 32 Gigabaud */
2472#define LINK_SPEED_64G 0x17 /* 64 Gigabaud */
2473#define LINK_SPEED_128G 0x1A /* 128 Gigabaud */
2474#define LINK_SPEED_256G 0x1D /* 256 Gigabaud */
2475
2476} INIT_LINK_VAR;
2477
2478/* Structure for MB Command DOWN_LINK (06) */
2479
2480typedef struct {
2481 uint32_t rsvd1;
2482} DOWN_LINK_VAR;
2483
2484/* Structure for MB Command CONFIG_LINK (07) */
2485
2486typedef struct {
2487#ifdef __BIG_ENDIAN_BITFIELD
2488 uint32_t cr:1;
2489 uint32_t ci:1;
2490 uint32_t cr_delay:6;
2491 uint32_t cr_count:8;
2492 uint32_t rsvd1:8;
2493 uint32_t MaxBBC:8;
2494#else /* __LITTLE_ENDIAN_BITFIELD */
2495 uint32_t MaxBBC:8;
2496 uint32_t rsvd1:8;
2497 uint32_t cr_count:8;
2498 uint32_t cr_delay:6;
2499 uint32_t ci:1;
2500 uint32_t cr:1;
2501#endif
2502
2503 uint32_t myId;
2504 uint32_t rsvd2;
2505 uint32_t edtov;
2506 uint32_t arbtov;
2507 uint32_t ratov;
2508 uint32_t rttov;
2509 uint32_t altov;
2510 uint32_t crtov;
2511
2512#ifdef __BIG_ENDIAN_BITFIELD
2513 uint32_t rsvd4:19;
2514 uint32_t cscn:1;
2515 uint32_t bbscn:4;
2516 uint32_t rsvd3:8;
2517#else /* __LITTLE_ENDIAN_BITFIELD */
2518 uint32_t rsvd3:8;
2519 uint32_t bbscn:4;
2520 uint32_t cscn:1;
2521 uint32_t rsvd4:19;
2522#endif
2523
2524#ifdef __BIG_ENDIAN_BITFIELD
2525 uint32_t rrq_enable:1;
2526 uint32_t rrq_immed:1;
2527 uint32_t rsvd5:29;
2528 uint32_t ack0_enable:1;
2529#else /* __LITTLE_ENDIAN_BITFIELD */
2530 uint32_t ack0_enable:1;
2531 uint32_t rsvd5:29;
2532 uint32_t rrq_immed:1;
2533 uint32_t rrq_enable:1;
2534#endif
2535} CONFIG_LINK;
2536
2537/* Structure for MB Command PART_SLIM (08)
2538 * will be removed since SLI1 is no longer supported!
2539 */
2540typedef struct {
2541#ifdef __BIG_ENDIAN_BITFIELD
2542 uint16_t offCiocb;
2543 uint16_t numCiocb;
2544 uint16_t offRiocb;
2545 uint16_t numRiocb;
2546#else /* __LITTLE_ENDIAN_BITFIELD */
2547 uint16_t numCiocb;
2548 uint16_t offCiocb;
2549 uint16_t numRiocb;
2550 uint16_t offRiocb;
2551#endif
2552} RING_DEF;
2553
2554typedef struct {
2555#ifdef __BIG_ENDIAN_BITFIELD
2556 uint32_t unused1:24;
2557 uint32_t numRing:8;
2558#else /* __LITTLE_ENDIAN_BITFIELD */
2559 uint32_t numRing:8;
2560 uint32_t unused1:24;
2561#endif
2562
2563 RING_DEF ringdef[4];
2564 uint32_t hbainit;
2565} PART_SLIM_VAR;
2566
2567/* Structure for MB Command CONFIG_RING (09) */
2568
2569typedef struct {
2570#ifdef __BIG_ENDIAN_BITFIELD
2571 uint32_t unused2:6;
2572 uint32_t recvSeq:1;
2573 uint32_t recvNotify:1;
2574 uint32_t numMask:8;
2575 uint32_t profile:8;
2576 uint32_t unused1:4;
2577 uint32_t ring:4;
2578#else /* __LITTLE_ENDIAN_BITFIELD */
2579 uint32_t ring:4;
2580 uint32_t unused1:4;
2581 uint32_t profile:8;
2582 uint32_t numMask:8;
2583 uint32_t recvNotify:1;
2584 uint32_t recvSeq:1;
2585 uint32_t unused2:6;
2586#endif
2587
2588#ifdef __BIG_ENDIAN_BITFIELD
2589 uint16_t maxRespXchg;
2590 uint16_t maxOrigXchg;
2591#else /* __LITTLE_ENDIAN_BITFIELD */
2592 uint16_t maxOrigXchg;
2593 uint16_t maxRespXchg;
2594#endif
2595
2596 RR_REG rrRegs[6];
2597} CONFIG_RING_VAR;
2598
2599/* Structure for MB Command RESET_RING (10) */
2600
2601typedef struct {
2602 uint32_t ring_no;
2603} RESET_RING_VAR;
2604
2605/* Structure for MB Command READ_CONFIG (11) */
2606
2607typedef struct {
2608#ifdef __BIG_ENDIAN_BITFIELD
2609 uint32_t cr:1;
2610 uint32_t ci:1;
2611 uint32_t cr_delay:6;
2612 uint32_t cr_count:8;
2613 uint32_t InitBBC:8;
2614 uint32_t MaxBBC:8;
2615#else /* __LITTLE_ENDIAN_BITFIELD */
2616 uint32_t MaxBBC:8;
2617 uint32_t InitBBC:8;
2618 uint32_t cr_count:8;
2619 uint32_t cr_delay:6;
2620 uint32_t ci:1;
2621 uint32_t cr:1;
2622#endif
2623
2624#ifdef __BIG_ENDIAN_BITFIELD
2625 uint32_t topology:8;
2626 uint32_t myDid:24;
2627#else /* __LITTLE_ENDIAN_BITFIELD */
2628 uint32_t myDid:24;
2629 uint32_t topology:8;
2630#endif
2631
2632 /* Defines for topology (defined previously) */
2633#ifdef __BIG_ENDIAN_BITFIELD
2634 uint32_t AR:1;
2635 uint32_t IR:1;
2636 uint32_t rsvd1:29;
2637 uint32_t ack0:1;
2638#else /* __LITTLE_ENDIAN_BITFIELD */
2639 uint32_t ack0:1;
2640 uint32_t rsvd1:29;
2641 uint32_t IR:1;
2642 uint32_t AR:1;
2643#endif
2644
2645 uint32_t edtov;
2646 uint32_t arbtov;
2647 uint32_t ratov;
2648 uint32_t rttov;
2649 uint32_t altov;
2650 uint32_t lmt;
2651#define LMT_RESERVED 0x000 /* Not used */
2652#define LMT_1Gb 0x004
2653#define LMT_2Gb 0x008
2654#define LMT_4Gb 0x040
2655#define LMT_8Gb 0x080
2656#define LMT_10Gb 0x100
2657#define LMT_16Gb 0x200
2658#define LMT_32Gb 0x400
2659#define LMT_64Gb 0x800
2660#define LMT_128Gb 0x1000
2661#define LMT_256Gb 0x2000
2662 uint32_t rsvd2;
2663 uint32_t rsvd3;
2664 uint32_t max_xri;
2665 uint32_t max_iocb;
2666 uint32_t max_rpi;
2667 uint32_t avail_xri;
2668 uint32_t avail_iocb;
2669 uint32_t avail_rpi;
2670 uint32_t max_vpi;
2671 uint32_t rsvd4;
2672 uint32_t rsvd5;
2673 uint32_t avail_vpi;
2674} READ_CONFIG_VAR;
2675
2676/* Structure for MB Command READ_RCONFIG (12) */
2677
2678typedef struct {
2679#ifdef __BIG_ENDIAN_BITFIELD
2680 uint32_t rsvd2:7;
2681 uint32_t recvNotify:1;
2682 uint32_t numMask:8;
2683 uint32_t profile:8;
2684 uint32_t rsvd1:4;
2685 uint32_t ring:4;
2686#else /* __LITTLE_ENDIAN_BITFIELD */
2687 uint32_t ring:4;
2688 uint32_t rsvd1:4;
2689 uint32_t profile:8;
2690 uint32_t numMask:8;
2691 uint32_t recvNotify:1;
2692 uint32_t rsvd2:7;
2693#endif
2694
2695#ifdef __BIG_ENDIAN_BITFIELD
2696 uint16_t maxResp;
2697 uint16_t maxOrig;
2698#else /* __LITTLE_ENDIAN_BITFIELD */
2699 uint16_t maxOrig;
2700 uint16_t maxResp;
2701#endif
2702
2703 RR_REG rrRegs[6];
2704
2705#ifdef __BIG_ENDIAN_BITFIELD
2706 uint16_t cmdRingOffset;
2707 uint16_t cmdEntryCnt;
2708 uint16_t rspRingOffset;
2709 uint16_t rspEntryCnt;
2710 uint16_t nextCmdOffset;
2711 uint16_t rsvd3;
2712 uint16_t nextRspOffset;
2713 uint16_t rsvd4;
2714#else /* __LITTLE_ENDIAN_BITFIELD */
2715 uint16_t cmdEntryCnt;
2716 uint16_t cmdRingOffset;
2717 uint16_t rspEntryCnt;
2718 uint16_t rspRingOffset;
2719 uint16_t rsvd3;
2720 uint16_t nextCmdOffset;
2721 uint16_t rsvd4;
2722 uint16_t nextRspOffset;
2723#endif
2724} READ_RCONF_VAR;
2725
2726/* Structure for MB Command READ_SPARM (13) */
2727/* Structure for MB Command READ_SPARM64 (0x8D) */
2728
2729typedef struct {
2730 uint32_t rsvd1;
2731 uint32_t rsvd2;
2732 union {
2733 struct ulp_bde sp; /* This BDE points to struct serv_parm
2734 structure */
2735 struct ulp_bde64 sp64;
2736 } un;
2737#ifdef __BIG_ENDIAN_BITFIELD
2738 uint16_t rsvd3;
2739 uint16_t vpi;
2740#else /* __LITTLE_ENDIAN_BITFIELD */
2741 uint16_t vpi;
2742 uint16_t rsvd3;
2743#endif
2744} READ_SPARM_VAR;
2745
2746/* Structure for MB Command READ_STATUS (14) */
2747enum read_status_word1 {
2748 RD_ST_CC = 0x01,
2749 RD_ST_XKB = 0x80,
2750};
2751
2752enum read_status_word17 {
2753 RD_ST_XMIT_XKB_MASK = 0x3fffff,
2754};
2755
2756enum read_status_word18 {
2757 RD_ST_RCV_XKB_MASK = 0x3fffff,
2758};
2759
2760typedef struct {
2761 u8 clear_counters; /* rsvd 7:1, cc 0 */
2762 u8 rsvd5;
2763 u8 rsvd6;
2764 u8 xkb; /* xkb 7, rsvd 6:0 */
2765
2766 u32 rsvd8;
2767
2768 uint32_t xmitByteCnt;
2769 uint32_t rcvByteCnt;
2770 uint32_t xmitFrameCnt;
2771 uint32_t rcvFrameCnt;
2772 uint32_t xmitSeqCnt;
2773 uint32_t rcvSeqCnt;
2774 uint32_t totalOrigExchanges;
2775 uint32_t totalRespExchanges;
2776 uint32_t rcvPbsyCnt;
2777 uint32_t rcvFbsyCnt;
2778
2779 u32 drop_frame_no_rq;
2780 u32 empty_rq;
2781 u32 drop_frame_no_xri;
2782 u32 empty_xri;
2783
2784 u32 xmit_xkb; /* rsvd 31:22, xmit_xkb 21:0 */
2785 u32 rcv_xkb; /* rsvd 31:22, rcv_xkb 21:0 */
2786} READ_STATUS_VAR;
2787
2788/* Structure for MB Command READ_RPI (15) */
2789/* Structure for MB Command READ_RPI64 (0x8F) */
2790
2791typedef struct {
2792#ifdef __BIG_ENDIAN_BITFIELD
2793 uint16_t nextRpi;
2794 uint16_t reqRpi;
2795 uint32_t rsvd2:8;
2796 uint32_t DID:24;
2797#else /* __LITTLE_ENDIAN_BITFIELD */
2798 uint16_t reqRpi;
2799 uint16_t nextRpi;
2800 uint32_t DID:24;
2801 uint32_t rsvd2:8;
2802#endif
2803
2804 union {
2805 struct ulp_bde sp;
2806 struct ulp_bde64 sp64;
2807 } un;
2808
2809} READ_RPI_VAR;
2810
2811/* Structure for MB Command READ_XRI (16) */
2812
2813typedef struct {
2814#ifdef __BIG_ENDIAN_BITFIELD
2815 uint16_t nextXri;
2816 uint16_t reqXri;
2817 uint16_t rsvd1;
2818 uint16_t rpi;
2819 uint32_t rsvd2:8;
2820 uint32_t DID:24;
2821 uint32_t rsvd3:8;
2822 uint32_t SID:24;
2823 uint32_t rsvd4;
2824 uint8_t seqId;
2825 uint8_t rsvd5;
2826 uint16_t seqCount;
2827 uint16_t oxId;
2828 uint16_t rxId;
2829 uint32_t rsvd6:30;
2830 uint32_t si:1;
2831 uint32_t exchOrig:1;
2832#else /* __LITTLE_ENDIAN_BITFIELD */
2833 uint16_t reqXri;
2834 uint16_t nextXri;
2835 uint16_t rpi;
2836 uint16_t rsvd1;
2837 uint32_t DID:24;
2838 uint32_t rsvd2:8;
2839 uint32_t SID:24;
2840 uint32_t rsvd3:8;
2841 uint32_t rsvd4;
2842 uint16_t seqCount;
2843 uint8_t rsvd5;
2844 uint8_t seqId;
2845 uint16_t rxId;
2846 uint16_t oxId;
2847 uint32_t exchOrig:1;
2848 uint32_t si:1;
2849 uint32_t rsvd6:30;
2850#endif
2851} READ_XRI_VAR;
2852
2853/* Structure for MB Command READ_REV (17) */
2854
2855typedef struct {
2856#ifdef __BIG_ENDIAN_BITFIELD
2857 uint32_t cv:1;
2858 uint32_t rr:1;
2859 uint32_t rsvd2:2;
2860 uint32_t v3req:1;
2861 uint32_t v3rsp:1;
2862 uint32_t rsvd1:25;
2863 uint32_t rv:1;
2864#else /* __LITTLE_ENDIAN_BITFIELD */
2865 uint32_t rv:1;
2866 uint32_t rsvd1:25;
2867 uint32_t v3rsp:1;
2868 uint32_t v3req:1;
2869 uint32_t rsvd2:2;
2870 uint32_t rr:1;
2871 uint32_t cv:1;
2872#endif
2873
2874 uint32_t biuRev;
2875 uint32_t smRev;
2876 union {
2877 uint32_t smFwRev;
2878 struct {
2879#ifdef __BIG_ENDIAN_BITFIELD
2880 uint8_t ProgType;
2881 uint8_t ProgId;
2882 uint16_t ProgVer:4;
2883 uint16_t ProgRev:4;
2884 uint16_t ProgFixLvl:2;
2885 uint16_t ProgDistType:2;
2886 uint16_t DistCnt:4;
2887#else /* __LITTLE_ENDIAN_BITFIELD */
2888 uint16_t DistCnt:4;
2889 uint16_t ProgDistType:2;
2890 uint16_t ProgFixLvl:2;
2891 uint16_t ProgRev:4;
2892 uint16_t ProgVer:4;
2893 uint8_t ProgId;
2894 uint8_t ProgType;
2895#endif
2896
2897 } b;
2898 } un;
2899 uint32_t endecRev;
2900#ifdef __BIG_ENDIAN_BITFIELD
2901 uint8_t feaLevelHigh;
2902 uint8_t feaLevelLow;
2903 uint8_t fcphHigh;
2904 uint8_t fcphLow;
2905#else /* __LITTLE_ENDIAN_BITFIELD */
2906 uint8_t fcphLow;
2907 uint8_t fcphHigh;
2908 uint8_t feaLevelLow;
2909 uint8_t feaLevelHigh;
2910#endif
2911
2912 uint32_t postKernRev;
2913 uint32_t opFwRev;
2914 uint8_t opFwName[16];
2915 uint32_t sli1FwRev;
2916 uint8_t sli1FwName[16];
2917 uint32_t sli2FwRev;
2918 uint8_t sli2FwName[16];
2919 uint32_t sli3Feat;
2920 uint32_t RandomData[6];
2921} READ_REV_VAR;
2922
2923/* Structure for MB Command READ_LINK_STAT (18) */
2924
2925typedef struct {
2926 uint32_t word0;
2927
2928#define lpfc_read_link_stat_rec_SHIFT 0
2929#define lpfc_read_link_stat_rec_MASK 0x1
2930#define lpfc_read_link_stat_rec_WORD word0
2931
2932#define lpfc_read_link_stat_gec_SHIFT 1
2933#define lpfc_read_link_stat_gec_MASK 0x1
2934#define lpfc_read_link_stat_gec_WORD word0
2935
2936#define lpfc_read_link_stat_w02oftow23of_SHIFT 2
2937#define lpfc_read_link_stat_w02oftow23of_MASK 0x3FFFFF
2938#define lpfc_read_link_stat_w02oftow23of_WORD word0
2939
2940#define lpfc_read_link_stat_rsvd_SHIFT 24
2941#define lpfc_read_link_stat_rsvd_MASK 0x1F
2942#define lpfc_read_link_stat_rsvd_WORD word0
2943
2944#define lpfc_read_link_stat_gec2_SHIFT 29
2945#define lpfc_read_link_stat_gec2_MASK 0x1
2946#define lpfc_read_link_stat_gec2_WORD word0
2947
2948#define lpfc_read_link_stat_clrc_SHIFT 30
2949#define lpfc_read_link_stat_clrc_MASK 0x1
2950#define lpfc_read_link_stat_clrc_WORD word0
2951
2952#define lpfc_read_link_stat_clof_SHIFT 31
2953#define lpfc_read_link_stat_clof_MASK 0x1
2954#define lpfc_read_link_stat_clof_WORD word0
2955
2956 uint32_t linkFailureCnt;
2957 uint32_t lossSyncCnt;
2958 uint32_t lossSignalCnt;
2959 uint32_t primSeqErrCnt;
2960 uint32_t invalidXmitWord;
2961 uint32_t crcCnt;
2962 uint32_t primSeqTimeout;
2963 uint32_t elasticOverrun;
2964 uint32_t arbTimeout;
2965 uint32_t advRecBufCredit;
2966 uint32_t curRecBufCredit;
2967 uint32_t advTransBufCredit;
2968 uint32_t curTransBufCredit;
2969 uint32_t recEofCount;
2970 uint32_t recEofdtiCount;
2971 uint32_t recEofniCount;
2972 uint32_t recSofcount;
2973 uint32_t rsvd1;
2974 uint32_t rsvd2;
2975 uint32_t recDrpXriCount;
2976 uint32_t fecCorrBlkCount;
2977 uint32_t fecUncorrBlkCount;
2978} READ_LNK_VAR;
2979
2980/* Structure for MB Command REG_LOGIN (19) */
2981/* Structure for MB Command REG_LOGIN64 (0x93) */
2982
2983typedef struct {
2984#ifdef __BIG_ENDIAN_BITFIELD
2985 uint16_t rsvd1;
2986 uint16_t rpi;
2987 uint32_t rsvd2:8;
2988 uint32_t did:24;
2989#else /* __LITTLE_ENDIAN_BITFIELD */
2990 uint16_t rpi;
2991 uint16_t rsvd1;
2992 uint32_t did:24;
2993 uint32_t rsvd2:8;
2994#endif
2995
2996 union {
2997 struct ulp_bde sp;
2998 struct ulp_bde64 sp64;
2999 } un;
3000
3001#ifdef __BIG_ENDIAN_BITFIELD
3002 uint16_t rsvd6;
3003 uint16_t vpi;
3004#else /* __LITTLE_ENDIAN_BITFIELD */
3005 uint16_t vpi;
3006 uint16_t rsvd6;
3007#endif
3008
3009} REG_LOGIN_VAR;
3010
3011/* Word 30 contents for REG_LOGIN */
3012typedef union {
3013 struct {
3014#ifdef __BIG_ENDIAN_BITFIELD
3015 uint16_t rsvd1:12;
3016 uint16_t wd30_class:4;
3017 uint16_t xri;
3018#else /* __LITTLE_ENDIAN_BITFIELD */
3019 uint16_t xri;
3020 uint16_t wd30_class:4;
3021 uint16_t rsvd1:12;
3022#endif
3023 } f;
3024 uint32_t word;
3025} REG_WD30;
3026
3027/* Structure for MB Command UNREG_LOGIN (20) */
3028
3029typedef struct {
3030#ifdef __BIG_ENDIAN_BITFIELD
3031 uint16_t rsvd1;
3032 uint16_t rpi;
3033 uint32_t rsvd2;
3034 uint32_t rsvd3;
3035 uint32_t rsvd4;
3036 uint32_t rsvd5;
3037 uint16_t rsvd6;
3038 uint16_t vpi;
3039#else /* __LITTLE_ENDIAN_BITFIELD */
3040 uint16_t rpi;
3041 uint16_t rsvd1;
3042 uint32_t rsvd2;
3043 uint32_t rsvd3;
3044 uint32_t rsvd4;
3045 uint32_t rsvd5;
3046 uint16_t vpi;
3047 uint16_t rsvd6;
3048#endif
3049} UNREG_LOGIN_VAR;
3050
3051/* Structure for MB Command REG_VPI (0x96) */
3052typedef struct {
3053#ifdef __BIG_ENDIAN_BITFIELD
3054 uint32_t rsvd1;
3055 uint32_t rsvd2:7;
3056 uint32_t upd:1;
3057 uint32_t sid:24;
3058 uint32_t wwn[2];
3059 uint32_t rsvd5;
3060 uint16_t vfi;
3061 uint16_t vpi;
3062#else /* __LITTLE_ENDIAN */
3063 uint32_t rsvd1;
3064 uint32_t sid:24;
3065 uint32_t upd:1;
3066 uint32_t rsvd2:7;
3067 uint32_t wwn[2];
3068 uint32_t rsvd5;
3069 uint16_t vpi;
3070 uint16_t vfi;
3071#endif
3072} REG_VPI_VAR;
3073
3074/* Structure for MB Command UNREG_VPI (0x97) */
3075typedef struct {
3076 uint32_t rsvd1;
3077#ifdef __BIG_ENDIAN_BITFIELD
3078 uint16_t rsvd2;
3079 uint16_t sli4_vpi;
3080#else /* __LITTLE_ENDIAN */
3081 uint16_t sli4_vpi;
3082 uint16_t rsvd2;
3083#endif
3084 uint32_t rsvd3;
3085 uint32_t rsvd4;
3086 uint32_t rsvd5;
3087#ifdef __BIG_ENDIAN_BITFIELD
3088 uint16_t rsvd6;
3089 uint16_t vpi;
3090#else /* __LITTLE_ENDIAN */
3091 uint16_t vpi;
3092 uint16_t rsvd6;
3093#endif
3094} UNREG_VPI_VAR;
3095
3096/* Structure for MB Command UNREG_D_ID (0x23) */
3097
3098typedef struct {
3099 uint32_t did;
3100 uint32_t rsvd2;
3101 uint32_t rsvd3;
3102 uint32_t rsvd4;
3103 uint32_t rsvd5;
3104#ifdef __BIG_ENDIAN_BITFIELD
3105 uint16_t rsvd6;
3106 uint16_t vpi;
3107#else
3108 uint16_t vpi;
3109 uint16_t rsvd6;
3110#endif
3111} UNREG_D_ID_VAR;
3112
3113/* Structure for MB Command READ_TOPOLOGY (0x95) */
3114struct lpfc_mbx_read_top {
3115 uint32_t eventTag; /* Event tag */
3116 uint32_t word2;
3117#define lpfc_mbx_read_top_fa_SHIFT 12
3118#define lpfc_mbx_read_top_fa_MASK 0x00000001
3119#define lpfc_mbx_read_top_fa_WORD word2
3120#define lpfc_mbx_read_top_mm_SHIFT 11
3121#define lpfc_mbx_read_top_mm_MASK 0x00000001
3122#define lpfc_mbx_read_top_mm_WORD word2
3123#define lpfc_mbx_read_top_pb_SHIFT 9
3124#define lpfc_mbx_read_top_pb_MASK 0X00000001
3125#define lpfc_mbx_read_top_pb_WORD word2
3126#define lpfc_mbx_read_top_il_SHIFT 8
3127#define lpfc_mbx_read_top_il_MASK 0x00000001
3128#define lpfc_mbx_read_top_il_WORD word2
3129#define lpfc_mbx_read_top_att_type_SHIFT 0
3130#define lpfc_mbx_read_top_att_type_MASK 0x000000FF
3131#define lpfc_mbx_read_top_att_type_WORD word2
3132#define LPFC_ATT_RESERVED 0x00 /* Reserved - attType */
3133#define LPFC_ATT_LINK_UP 0x01 /* Link is up */
3134#define LPFC_ATT_LINK_DOWN 0x02 /* Link is down */
3135#define LPFC_ATT_UNEXP_WWPN 0x06 /* Link is down Unexpected WWWPN */
3136 uint32_t word3;
3137#define lpfc_mbx_read_top_alpa_granted_SHIFT 24
3138#define lpfc_mbx_read_top_alpa_granted_MASK 0x000000FF
3139#define lpfc_mbx_read_top_alpa_granted_WORD word3
3140#define lpfc_mbx_read_top_lip_alps_SHIFT 16
3141#define lpfc_mbx_read_top_lip_alps_MASK 0x000000FF
3142#define lpfc_mbx_read_top_lip_alps_WORD word3
3143#define lpfc_mbx_read_top_lip_type_SHIFT 8
3144#define lpfc_mbx_read_top_lip_type_MASK 0x000000FF
3145#define lpfc_mbx_read_top_lip_type_WORD word3
3146#define lpfc_mbx_read_top_topology_SHIFT 0
3147#define lpfc_mbx_read_top_topology_MASK 0x000000FF
3148#define lpfc_mbx_read_top_topology_WORD word3
3149#define LPFC_TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */
3150#define LPFC_TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */
3151 /* store the LILP AL_PA position map into */
3152 struct ulp_bde64 lilpBde64;
3153#define LPFC_ALPA_MAP_SIZE 128
3154 uint32_t word7;
3155#define lpfc_mbx_read_top_ld_lu_SHIFT 31
3156#define lpfc_mbx_read_top_ld_lu_MASK 0x00000001
3157#define lpfc_mbx_read_top_ld_lu_WORD word7
3158#define lpfc_mbx_read_top_ld_tf_SHIFT 30
3159#define lpfc_mbx_read_top_ld_tf_MASK 0x00000001
3160#define lpfc_mbx_read_top_ld_tf_WORD word7
3161#define lpfc_mbx_read_top_ld_link_spd_SHIFT 8
3162#define lpfc_mbx_read_top_ld_link_spd_MASK 0x000000FF
3163#define lpfc_mbx_read_top_ld_link_spd_WORD word7
3164#define lpfc_mbx_read_top_ld_nl_port_SHIFT 4
3165#define lpfc_mbx_read_top_ld_nl_port_MASK 0x0000000F
3166#define lpfc_mbx_read_top_ld_nl_port_WORD word7
3167#define lpfc_mbx_read_top_ld_tx_SHIFT 2
3168#define lpfc_mbx_read_top_ld_tx_MASK 0x00000003
3169#define lpfc_mbx_read_top_ld_tx_WORD word7
3170#define lpfc_mbx_read_top_ld_rx_SHIFT 0
3171#define lpfc_mbx_read_top_ld_rx_MASK 0x00000003
3172#define lpfc_mbx_read_top_ld_rx_WORD word7
3173 uint32_t word8;
3174#define lpfc_mbx_read_top_lu_SHIFT 31
3175#define lpfc_mbx_read_top_lu_MASK 0x00000001
3176#define lpfc_mbx_read_top_lu_WORD word8
3177#define lpfc_mbx_read_top_tf_SHIFT 30
3178#define lpfc_mbx_read_top_tf_MASK 0x00000001
3179#define lpfc_mbx_read_top_tf_WORD word8
3180#define lpfc_mbx_read_top_link_spd_SHIFT 8
3181#define lpfc_mbx_read_top_link_spd_MASK 0x000000FF
3182#define lpfc_mbx_read_top_link_spd_WORD word8
3183#define lpfc_mbx_read_top_nl_port_SHIFT 4
3184#define lpfc_mbx_read_top_nl_port_MASK 0x0000000F
3185#define lpfc_mbx_read_top_nl_port_WORD word8
3186#define lpfc_mbx_read_top_tx_SHIFT 2
3187#define lpfc_mbx_read_top_tx_MASK 0x00000003
3188#define lpfc_mbx_read_top_tx_WORD word8
3189#define lpfc_mbx_read_top_rx_SHIFT 0
3190#define lpfc_mbx_read_top_rx_MASK 0x00000003
3191#define lpfc_mbx_read_top_rx_WORD word8
3192#define LPFC_LINK_SPEED_UNKNOWN 0x0
3193#define LPFC_LINK_SPEED_1GHZ 0x04
3194#define LPFC_LINK_SPEED_2GHZ 0x08
3195#define LPFC_LINK_SPEED_4GHZ 0x10
3196#define LPFC_LINK_SPEED_8GHZ 0x20
3197#define LPFC_LINK_SPEED_10GHZ 0x40
3198#define LPFC_LINK_SPEED_16GHZ 0x80
3199#define LPFC_LINK_SPEED_32GHZ 0x90
3200#define LPFC_LINK_SPEED_64GHZ 0xA0
3201#define LPFC_LINK_SPEED_128GHZ 0xB0
3202#define LPFC_LINK_SPEED_256GHZ 0xC0
3203};
3204
3205/* Structure for MB Command CLEAR_LA (22) */
3206
3207typedef struct {
3208 uint32_t eventTag; /* Event tag */
3209 uint32_t rsvd1;
3210} CLEAR_LA_VAR;
3211
3212/* Structure for MB Command DUMP */
3213
3214typedef struct {
3215#ifdef __BIG_ENDIAN_BITFIELD
3216 uint32_t rsvd:25;
3217 uint32_t ra:1;
3218 uint32_t co:1;
3219 uint32_t cv:1;
3220 uint32_t type:4;
3221 uint32_t entry_index:16;
3222 uint32_t region_id:16;
3223#else /* __LITTLE_ENDIAN_BITFIELD */
3224 uint32_t type:4;
3225 uint32_t cv:1;
3226 uint32_t co:1;
3227 uint32_t ra:1;
3228 uint32_t rsvd:25;
3229 uint32_t region_id:16;
3230 uint32_t entry_index:16;
3231#endif
3232
3233 uint32_t sli4_length;
3234 uint32_t word_cnt;
3235 uint32_t resp_offset;
3236} DUMP_VAR;
3237
3238#define DMP_MEM_REG 0x1
3239#define DMP_NV_PARAMS 0x2
3240#define DMP_LMSD 0x3 /* Link Module Serial Data */
3241#define DMP_WELL_KNOWN 0x4
3242
3243#define DMP_REGION_VPD 0xe
3244#define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */
3245#define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */
3246#define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */
3247
3248#define DMP_REGION_VPORT 0x16 /* VPort info region */
3249#define DMP_VPORT_REGION_SIZE 0x200
3250#define DMP_MBOX_OFFSET_WORD 0x5
3251
3252#define DMP_REGION_23 0x17 /* fcoe param and port state region */
3253#define DMP_RGN23_SIZE 0x400
3254
3255#define WAKE_UP_PARMS_REGION_ID 4
3256#define WAKE_UP_PARMS_WORD_SIZE 15
3257
3258struct vport_rec {
3259 uint8_t wwpn[8];
3260 uint8_t wwnn[8];
3261};
3262
3263#define VPORT_INFO_SIG 0x32324752
3264#define VPORT_INFO_REV_MASK 0xff
3265#define VPORT_INFO_REV 0x1
3266#define MAX_STATIC_VPORT_COUNT 16
3267struct static_vport_info {
3268 uint32_t signature;
3269 uint32_t rev;
3270 struct vport_rec vport_list[MAX_STATIC_VPORT_COUNT];
3271 uint32_t resvd[66];
3272};
3273
3274/* Option rom version structure */
3275struct prog_id {
3276#ifdef __BIG_ENDIAN_BITFIELD
3277 uint8_t type;
3278 uint8_t id;
3279 uint32_t ver:4; /* Major Version */
3280 uint32_t rev:4; /* Revision */
3281 uint32_t lev:2; /* Level */
3282 uint32_t dist:2; /* Dist Type */
3283 uint32_t num:4; /* number after dist type */
3284#else /* __LITTLE_ENDIAN_BITFIELD */
3285 uint32_t num:4; /* number after dist type */
3286 uint32_t dist:2; /* Dist Type */
3287 uint32_t lev:2; /* Level */
3288 uint32_t rev:4; /* Revision */
3289 uint32_t ver:4; /* Major Version */
3290 uint8_t id;
3291 uint8_t type;
3292#endif
3293};
3294
3295/* Structure for MB Command UPDATE_CFG (0x1B) */
3296
3297struct update_cfg_var {
3298#ifdef __BIG_ENDIAN_BITFIELD
3299 uint32_t rsvd2:16;
3300 uint32_t type:8;
3301 uint32_t rsvd:1;
3302 uint32_t ra:1;
3303 uint32_t co:1;
3304 uint32_t cv:1;
3305 uint32_t req:4;
3306 uint32_t entry_length:16;
3307 uint32_t region_id:16;
3308#else /* __LITTLE_ENDIAN_BITFIELD */
3309 uint32_t req:4;
3310 uint32_t cv:1;
3311 uint32_t co:1;
3312 uint32_t ra:1;
3313 uint32_t rsvd:1;
3314 uint32_t type:8;
3315 uint32_t rsvd2:16;
3316 uint32_t region_id:16;
3317 uint32_t entry_length:16;
3318#endif
3319
3320 uint32_t resp_info;
3321 uint32_t byte_cnt;
3322 uint32_t data_offset;
3323};
3324
3325struct hbq_mask {
3326#ifdef __BIG_ENDIAN_BITFIELD
3327 uint8_t tmatch;
3328 uint8_t tmask;
3329 uint8_t rctlmatch;
3330 uint8_t rctlmask;
3331#else /* __LITTLE_ENDIAN */
3332 uint8_t rctlmask;
3333 uint8_t rctlmatch;
3334 uint8_t tmask;
3335 uint8_t tmatch;
3336#endif
3337};
3338
3339
3340/* Structure for MB Command CONFIG_HBQ (7c) */
3341
3342struct config_hbq_var {
3343#ifdef __BIG_ENDIAN_BITFIELD
3344 uint32_t rsvd1 :7;
3345 uint32_t recvNotify :1; /* Receive Notification */
3346 uint32_t numMask :8; /* # Mask Entries */
3347 uint32_t profile :8; /* Selection Profile */
3348 uint32_t rsvd2 :8;
3349#else /* __LITTLE_ENDIAN */
3350 uint32_t rsvd2 :8;
3351 uint32_t profile :8; /* Selection Profile */
3352 uint32_t numMask :8; /* # Mask Entries */
3353 uint32_t recvNotify :1; /* Receive Notification */
3354 uint32_t rsvd1 :7;
3355#endif
3356
3357#ifdef __BIG_ENDIAN_BITFIELD
3358 uint32_t hbqId :16;
3359 uint32_t rsvd3 :12;
3360 uint32_t ringMask :4;
3361#else /* __LITTLE_ENDIAN */
3362 uint32_t ringMask :4;
3363 uint32_t rsvd3 :12;
3364 uint32_t hbqId :16;
3365#endif
3366
3367#ifdef __BIG_ENDIAN_BITFIELD
3368 uint32_t entry_count :16;
3369 uint32_t rsvd4 :8;
3370 uint32_t headerLen :8;
3371#else /* __LITTLE_ENDIAN */
3372 uint32_t headerLen :8;
3373 uint32_t rsvd4 :8;
3374 uint32_t entry_count :16;
3375#endif
3376
3377 uint32_t hbqaddrLow;
3378 uint32_t hbqaddrHigh;
3379
3380#ifdef __BIG_ENDIAN_BITFIELD
3381 uint32_t rsvd5 :31;
3382 uint32_t logEntry :1;
3383#else /* __LITTLE_ENDIAN */
3384 uint32_t logEntry :1;
3385 uint32_t rsvd5 :31;
3386#endif
3387
3388 uint32_t rsvd6; /* w7 */
3389 uint32_t rsvd7; /* w8 */
3390 uint32_t rsvd8; /* w9 */
3391
3392 struct hbq_mask hbqMasks[6];
3393
3394
3395 union {
3396 uint32_t allprofiles[12];
3397
3398 struct {
3399 #ifdef __BIG_ENDIAN_BITFIELD
3400 uint32_t seqlenoff :16;
3401 uint32_t maxlen :16;
3402 #else /* __LITTLE_ENDIAN */
3403 uint32_t maxlen :16;
3404 uint32_t seqlenoff :16;
3405 #endif
3406 #ifdef __BIG_ENDIAN_BITFIELD
3407 uint32_t rsvd1 :28;
3408 uint32_t seqlenbcnt :4;
3409 #else /* __LITTLE_ENDIAN */
3410 uint32_t seqlenbcnt :4;
3411 uint32_t rsvd1 :28;
3412 #endif
3413 uint32_t rsvd[10];
3414 } profile2;
3415
3416 struct {
3417 #ifdef __BIG_ENDIAN_BITFIELD
3418 uint32_t seqlenoff :16;
3419 uint32_t maxlen :16;
3420 #else /* __LITTLE_ENDIAN */
3421 uint32_t maxlen :16;
3422 uint32_t seqlenoff :16;
3423 #endif
3424 #ifdef __BIG_ENDIAN_BITFIELD
3425 uint32_t cmdcodeoff :28;
3426 uint32_t rsvd1 :12;
3427 uint32_t seqlenbcnt :4;
3428 #else /* __LITTLE_ENDIAN */
3429 uint32_t seqlenbcnt :4;
3430 uint32_t rsvd1 :12;
3431 uint32_t cmdcodeoff :28;
3432 #endif
3433 uint32_t cmdmatch[8];
3434
3435 uint32_t rsvd[2];
3436 } profile3;
3437
3438 struct {
3439 #ifdef __BIG_ENDIAN_BITFIELD
3440 uint32_t seqlenoff :16;
3441 uint32_t maxlen :16;
3442 #else /* __LITTLE_ENDIAN */
3443 uint32_t maxlen :16;
3444 uint32_t seqlenoff :16;
3445 #endif
3446 #ifdef __BIG_ENDIAN_BITFIELD
3447 uint32_t cmdcodeoff :28;
3448 uint32_t rsvd1 :12;
3449 uint32_t seqlenbcnt :4;
3450 #else /* __LITTLE_ENDIAN */
3451 uint32_t seqlenbcnt :4;
3452 uint32_t rsvd1 :12;
3453 uint32_t cmdcodeoff :28;
3454 #endif
3455 uint32_t cmdmatch[8];
3456
3457 uint32_t rsvd[2];
3458 } profile5;
3459
3460 } profiles;
3461
3462};
3463
3464
3465
3466/* Structure for MB Command CONFIG_PORT (0x88) */
3467typedef struct {
3468#ifdef __BIG_ENDIAN_BITFIELD
3469 uint32_t cBE : 1;
3470 uint32_t cET : 1;
3471 uint32_t cHpcb : 1;
3472 uint32_t cMA : 1;
3473 uint32_t sli_mode : 4;
3474 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
3475 * config block */
3476#else /* __LITTLE_ENDIAN */
3477 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
3478 * config block */
3479 uint32_t sli_mode : 4;
3480 uint32_t cMA : 1;
3481 uint32_t cHpcb : 1;
3482 uint32_t cET : 1;
3483 uint32_t cBE : 1;
3484#endif
3485
3486 uint32_t pcbLow; /* bit 31:0 of memory based port config block */
3487 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */
3488 uint32_t hbainit[5];
3489#ifdef __BIG_ENDIAN_BITFIELD
3490 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */
3491 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */
3492#else /* __LITTLE_ENDIAN */
3493 uint32_t rsvd : 31; /* least significant 31 bits of word 9 */
3494 uint32_t hps : 1; /* bit 31 word9 Host Pointer in slim */
3495#endif
3496
3497#ifdef __BIG_ENDIAN_BITFIELD
3498 uint32_t rsvd1 : 20; /* Reserved */
3499 uint32_t casabt : 1; /* Configure async abts status notice */
3500 uint32_t rsvd2 : 2; /* Reserved */
3501 uint32_t cbg : 1; /* Configure BlockGuard */
3502 uint32_t cmv : 1; /* Configure Max VPIs */
3503 uint32_t ccrp : 1; /* Config Command Ring Polling */
3504 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
3505 uint32_t chbs : 1; /* Cofigure Host Backing store */
3506 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
3507 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
3508 uint32_t cmx : 1; /* Configure Max XRIs */
3509 uint32_t cmr : 1; /* Configure Max RPIs */
3510#else /* __LITTLE_ENDIAN */
3511 uint32_t cmr : 1; /* Configure Max RPIs */
3512 uint32_t cmx : 1; /* Configure Max XRIs */
3513 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
3514 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
3515 uint32_t chbs : 1; /* Cofigure Host Backing store */
3516 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
3517 uint32_t ccrp : 1; /* Config Command Ring Polling */
3518 uint32_t cmv : 1; /* Configure Max VPIs */
3519 uint32_t cbg : 1; /* Configure BlockGuard */
3520 uint32_t rsvd2 : 2; /* Reserved */
3521 uint32_t casabt : 1; /* Configure async abts status notice */
3522 uint32_t rsvd1 : 20; /* Reserved */
3523#endif
3524#ifdef __BIG_ENDIAN_BITFIELD
3525 uint32_t rsvd3 : 20; /* Reserved */
3526 uint32_t gasabt : 1; /* Grant async abts status notice */
3527 uint32_t rsvd4 : 2; /* Reserved */
3528 uint32_t gbg : 1; /* Grant BlockGuard */
3529 uint32_t gmv : 1; /* Grant Max VPIs */
3530 uint32_t gcrp : 1; /* Grant Command Ring Polling */
3531 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
3532 uint32_t ghbs : 1; /* Grant Host Backing Store */
3533 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
3534 uint32_t gerbm : 1; /* Grant ERBM Request */
3535 uint32_t gmx : 1; /* Grant Max XRIs */
3536 uint32_t gmr : 1; /* Grant Max RPIs */
3537#else /* __LITTLE_ENDIAN */
3538 uint32_t gmr : 1; /* Grant Max RPIs */
3539 uint32_t gmx : 1; /* Grant Max XRIs */
3540 uint32_t gerbm : 1; /* Grant ERBM Request */
3541 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
3542 uint32_t ghbs : 1; /* Grant Host Backing Store */
3543 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
3544 uint32_t gcrp : 1; /* Grant Command Ring Polling */
3545 uint32_t gmv : 1; /* Grant Max VPIs */
3546 uint32_t gbg : 1; /* Grant BlockGuard */
3547 uint32_t rsvd4 : 2; /* Reserved */
3548 uint32_t gasabt : 1; /* Grant async abts status notice */
3549 uint32_t rsvd3 : 20; /* Reserved */
3550#endif
3551
3552#ifdef __BIG_ENDIAN_BITFIELD
3553 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
3554 uint32_t max_xri : 16; /* Max XRIs Port should configure */
3555#else /* __LITTLE_ENDIAN */
3556 uint32_t max_xri : 16; /* Max XRIs Port should configure */
3557 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
3558#endif
3559
3560#ifdef __BIG_ENDIAN_BITFIELD
3561 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
3562 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */
3563#else /* __LITTLE_ENDIAN */
3564 uint32_t rsvd5 : 16; /* Max HBQs Host expect to configure */
3565 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
3566#endif
3567
3568 uint32_t rsvd6; /* Reserved */
3569
3570#ifdef __BIG_ENDIAN_BITFIELD
3571 uint32_t rsvd7 : 16;
3572 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
3573#else /* __LITTLE_ENDIAN */
3574 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
3575 uint32_t rsvd7 : 16;
3576#endif
3577
3578} CONFIG_PORT_VAR;
3579
3580/* Structure for MB Command CONFIG_MSI (0x30) */
3581struct config_msi_var {
3582#ifdef __BIG_ENDIAN_BITFIELD
3583 uint32_t dfltMsgNum:8; /* Default message number */
3584 uint32_t rsvd1:11; /* Reserved */
3585 uint32_t NID:5; /* Number of secondary attention IDs */
3586 uint32_t rsvd2:5; /* Reserved */
3587 uint32_t dfltPresent:1; /* Default message number present */
3588 uint32_t addFlag:1; /* Add association flag */
3589 uint32_t reportFlag:1; /* Report association flag */
3590#else /* __LITTLE_ENDIAN_BITFIELD */
3591 uint32_t reportFlag:1; /* Report association flag */
3592 uint32_t addFlag:1; /* Add association flag */
3593 uint32_t dfltPresent:1; /* Default message number present */
3594 uint32_t rsvd2:5; /* Reserved */
3595 uint32_t NID:5; /* Number of secondary attention IDs */
3596 uint32_t rsvd1:11; /* Reserved */
3597 uint32_t dfltMsgNum:8; /* Default message number */
3598#endif
3599 uint32_t attentionConditions[2];
3600 uint8_t attentionId[16];
3601 uint8_t messageNumberByHA[64];
3602 uint8_t messageNumberByID[16];
3603 uint32_t autoClearHA[2];
3604#ifdef __BIG_ENDIAN_BITFIELD
3605 uint32_t rsvd3:16;
3606 uint32_t autoClearID:16;
3607#else /* __LITTLE_ENDIAN_BITFIELD */
3608 uint32_t autoClearID:16;
3609 uint32_t rsvd3:16;
3610#endif
3611 uint32_t rsvd4;
3612};
3613
3614/* SLI-2 Port Control Block */
3615
3616/* SLIM POINTER */
3617#define SLIMOFF 0x30 /* WORD */
3618
3619typedef struct _SLI2_RDSC {
3620 uint32_t cmdEntries;
3621 uint32_t cmdAddrLow;
3622 uint32_t cmdAddrHigh;
3623
3624 uint32_t rspEntries;
3625 uint32_t rspAddrLow;
3626 uint32_t rspAddrHigh;
3627} SLI2_RDSC;
3628
3629typedef struct _PCB {
3630#ifdef __BIG_ENDIAN_BITFIELD
3631 uint32_t type:8;
3632#define TYPE_NATIVE_SLI2 0x01
3633 uint32_t feature:8;
3634#define FEATURE_INITIAL_SLI2 0x01
3635 uint32_t rsvd:12;
3636 uint32_t maxRing:4;
3637#else /* __LITTLE_ENDIAN_BITFIELD */
3638 uint32_t maxRing:4;
3639 uint32_t rsvd:12;
3640 uint32_t feature:8;
3641#define FEATURE_INITIAL_SLI2 0x01
3642 uint32_t type:8;
3643#define TYPE_NATIVE_SLI2 0x01
3644#endif
3645
3646 uint32_t mailBoxSize;
3647 uint32_t mbAddrLow;
3648 uint32_t mbAddrHigh;
3649
3650 uint32_t hgpAddrLow;
3651 uint32_t hgpAddrHigh;
3652
3653 uint32_t pgpAddrLow;
3654 uint32_t pgpAddrHigh;
3655 SLI2_RDSC rdsc[MAX_SLI3_RINGS];
3656} PCB_t;
3657
3658/* NEW_FEATURE */
3659typedef struct {
3660#ifdef __BIG_ENDIAN_BITFIELD
3661 uint32_t rsvd0:27;
3662 uint32_t discardFarp:1;
3663 uint32_t IPEnable:1;
3664 uint32_t nodeName:1;
3665 uint32_t portName:1;
3666 uint32_t filterEnable:1;
3667#else /* __LITTLE_ENDIAN_BITFIELD */
3668 uint32_t filterEnable:1;
3669 uint32_t portName:1;
3670 uint32_t nodeName:1;
3671 uint32_t IPEnable:1;
3672 uint32_t discardFarp:1;
3673 uint32_t rsvd:27;
3674#endif
3675
3676 uint8_t portname[8]; /* Used to be struct lpfc_name */
3677 uint8_t nodename[8];
3678 uint32_t rsvd1;
3679 uint32_t rsvd2;
3680 uint32_t rsvd3;
3681 uint32_t IPAddress;
3682} CONFIG_FARP_VAR;
3683
3684/* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */
3685
3686typedef struct {
3687#ifdef __BIG_ENDIAN_BITFIELD
3688 uint32_t rsvd:30;
3689 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
3690#else /* __LITTLE_ENDIAN */
3691 uint32_t ring:2; /* Ring for ASYNC_EVENT iocb Bits 0-1*/
3692 uint32_t rsvd:30;
3693#endif
3694} ASYNCEVT_ENABLE_VAR;
3695
3696/* Union of all Mailbox Command types */
3697#define MAILBOX_CMD_WSIZE 32
3698#define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t))
3699/* ext_wsize times 4 bytes should not be greater than max xmit size */
3700#define MAILBOX_EXT_WSIZE 512
3701#define MAILBOX_EXT_SIZE (MAILBOX_EXT_WSIZE * sizeof(uint32_t))
3702#define MAILBOX_HBA_EXT_OFFSET 0x100
3703/* max mbox xmit size is a page size for sysfs IO operations */
3704#define MAILBOX_SYSFS_MAX 4096
3705
3706typedef union {
3707 uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/
3708 * feature/max ring number
3709 */
3710 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */
3711 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */
3712 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */
3713 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */
3714 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */
3715 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */
3716 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */
3717 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */
3718 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */
3719 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */
3720 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */
3721 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */
3722 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */
3723 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */
3724 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */
3725 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */
3726 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */
3727 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */
3728 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */
3729 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */
3730 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */
3731 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */
3732 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */
3733 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP)
3734 * NEW_FEATURE
3735 */
3736 struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ) */
3737 struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/
3738 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */
3739 struct lpfc_mbx_read_top varReadTop; /* cmd = 0x95 (READ_TOPOLOGY) */
3740 REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */
3741 UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */
3742 ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */
3743 struct READ_EVENT_LOG_VAR varRdEventLog; /* cmd = 0x38
3744 * (READ_EVENT_LOG)
3745 */
3746 struct config_msi_var varCfgMSI;/* cmd = x30 (CONFIG_MSI) */
3747} MAILVARIANTS;
3748
3749/*
3750 * SLI-2 specific structures
3751 */
3752
3753struct lpfc_hgp {
3754 __le32 cmdPutInx;
3755 __le32 rspGetInx;
3756};
3757
3758struct lpfc_pgp {
3759 __le32 cmdGetInx;
3760 __le32 rspPutInx;
3761};
3762
3763struct sli2_desc {
3764 uint32_t unused1[16];
3765 struct lpfc_hgp host[MAX_SLI3_RINGS];
3766 struct lpfc_pgp port[MAX_SLI3_RINGS];
3767};
3768
3769struct sli3_desc {
3770 struct lpfc_hgp host[MAX_SLI3_RINGS];
3771 uint32_t reserved[8];
3772 uint32_t hbq_put[16];
3773};
3774
3775struct sli3_pgp {
3776 struct lpfc_pgp port[MAX_SLI3_RINGS];
3777 uint32_t hbq_get[16];
3778};
3779
3780union sli_var {
3781 struct sli2_desc s2;
3782 struct sli3_desc s3;
3783 struct sli3_pgp s3_pgp;
3784};
3785
3786typedef struct {
3787 struct_group_tagged(MAILBOX_word0, bits,
3788 union {
3789 struct {
3790#ifdef __BIG_ENDIAN_BITFIELD
3791 uint16_t mbxStatus;
3792 uint8_t mbxCommand;
3793 uint8_t mbxReserved:6;
3794 uint8_t mbxHc:1;
3795 uint8_t mbxOwner:1; /* Low order bit first word */
3796#else /* __LITTLE_ENDIAN_BITFIELD */
3797 uint8_t mbxOwner:1; /* Low order bit first word */
3798 uint8_t mbxHc:1;
3799 uint8_t mbxReserved:6;
3800 uint8_t mbxCommand;
3801 uint16_t mbxStatus;
3802#endif
3803 };
3804 u32 word0;
3805 };
3806 );
3807
3808 MAILVARIANTS un;
3809 union sli_var us;
3810} MAILBOX_t;
3811
3812/*
3813 * Begin Structure Definitions for IOCB Commands
3814 */
3815
3816typedef struct {
3817#ifdef __BIG_ENDIAN_BITFIELD
3818 uint8_t statAction;
3819 uint8_t statRsn;
3820 uint8_t statBaExp;
3821 uint8_t statLocalError;
3822#else /* __LITTLE_ENDIAN_BITFIELD */
3823 uint8_t statLocalError;
3824 uint8_t statBaExp;
3825 uint8_t statRsn;
3826 uint8_t statAction;
3827#endif
3828 /* statRsn P/F_RJT reason codes */
3829#define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */
3830#define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */
3831#define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */
3832#define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */
3833#define RJT_UNSUP_CLASS 0x05 /* Class not supported */
3834#define RJT_DELIM_ERR 0x06 /* Delimiter usage error */
3835#define RJT_UNSUP_TYPE 0x07 /* Type not supported */
3836#define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */
3837#define RJT_BAD_RCTL 0x09 /* R_CTL invalid */
3838#define RJT_BAD_FCTL 0x0A /* F_CTL invalid */
3839#define RJT_BAD_OXID 0x0B /* OX_ID invalid */
3840#define RJT_BAD_RXID 0x0C /* RX_ID invalid */
3841#define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */
3842#define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */
3843#define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */
3844#define RJT_BAD_PARM 0x10 /* Param. field invalid */
3845#define RJT_XCHG_ERR 0x11 /* Exchange error */
3846#define RJT_PROT_ERR 0x12 /* Protocol error */
3847#define RJT_BAD_LENGTH 0x13 /* Invalid Length */
3848#define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */
3849#define RJT_LOGIN_REQUIRED 0x16 /* Login required */
3850#define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */
3851#define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */
3852#define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */
3853#define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */
3854#define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */
3855
3856#define IOERR_SUCCESS 0x00 /* statLocalError */
3857#define IOERR_MISSING_CONTINUE 0x01
3858#define IOERR_SEQUENCE_TIMEOUT 0x02
3859#define IOERR_INTERNAL_ERROR 0x03
3860#define IOERR_INVALID_RPI 0x04
3861#define IOERR_NO_XRI 0x05
3862#define IOERR_ILLEGAL_COMMAND 0x06
3863#define IOERR_XCHG_DROPPED 0x07
3864#define IOERR_ILLEGAL_FIELD 0x08
3865#define IOERR_RPI_SUSPENDED 0x09
3866#define IOERR_TOO_MANY_BUFFERS 0x0A
3867#define IOERR_RCV_BUFFER_WAITING 0x0B
3868#define IOERR_NO_CONNECTION 0x0C
3869#define IOERR_TX_DMA_FAILED 0x0D
3870#define IOERR_RX_DMA_FAILED 0x0E
3871#define IOERR_ILLEGAL_FRAME 0x0F
3872#define IOERR_EXTRA_DATA 0x10
3873#define IOERR_NO_RESOURCES 0x11
3874#define IOERR_RESERVED 0x12
3875#define IOERR_ILLEGAL_LENGTH 0x13
3876#define IOERR_UNSUPPORTED_FEATURE 0x14
3877#define IOERR_ABORT_IN_PROGRESS 0x15
3878#define IOERR_ABORT_REQUESTED 0x16
3879#define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17
3880#define IOERR_LOOP_OPEN_FAILURE 0x18
3881#define IOERR_RING_RESET 0x19
3882#define IOERR_LINK_DOWN 0x1A
3883#define IOERR_CORRUPTED_DATA 0x1B
3884#define IOERR_CORRUPTED_RPI 0x1C
3885#define IOERR_OUT_OF_ORDER_DATA 0x1D
3886#define IOERR_OUT_OF_ORDER_ACK 0x1E
3887#define IOERR_DUP_FRAME 0x1F
3888#define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */
3889#define IOERR_BAD_HOST_ADDRESS 0x21
3890#define IOERR_RCV_HDRBUF_WAITING 0x22
3891#define IOERR_MISSING_HDR_BUFFER 0x23
3892#define IOERR_MSEQ_CHAIN_CORRUPTED 0x24
3893#define IOERR_ABORTMULT_REQUESTED 0x25
3894#define IOERR_BUFFER_SHORTAGE 0x28
3895#define IOERR_DEFAULT 0x29
3896#define IOERR_CNT 0x2A
3897#define IOERR_SLER_FAILURE 0x46
3898#define IOERR_SLER_CMD_RCV_FAILURE 0x47
3899#define IOERR_SLER_REC_RJT_ERR 0x48
3900#define IOERR_SLER_REC_SRR_RETRY_ERR 0x49
3901#define IOERR_SLER_SRR_RJT_ERR 0x4A
3902#define IOERR_SLER_RRQ_RJT_ERR 0x4C
3903#define IOERR_SLER_RRQ_RETRY_ERR 0x4D
3904#define IOERR_SLER_ABTS_ERR 0x4E
3905#define IOERR_ELXSEC_KEY_UNWRAP_ERROR 0xF0
3906#define IOERR_ELXSEC_KEY_UNWRAP_COMPARE_ERROR 0xF1
3907#define IOERR_ELXSEC_CRYPTO_ERROR 0xF2
3908#define IOERR_ELXSEC_CRYPTO_COMPARE_ERROR 0xF3
3909#define IOERR_DRVR_MASK 0x100
3910#define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */
3911#define IOERR_SLI_BRESET 0x102
3912#define IOERR_SLI_ABORTED 0x103
3913#define IOERR_PARAM_MASK 0x1ff
3914} PARM_ERR;
3915
3916typedef union {
3917 struct {
3918#ifdef __BIG_ENDIAN_BITFIELD
3919 uint8_t Rctl; /* R_CTL field */
3920 uint8_t Type; /* TYPE field */
3921 uint8_t Dfctl; /* DF_CTL field */
3922 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
3923#else /* __LITTLE_ENDIAN_BITFIELD */
3924 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
3925 uint8_t Dfctl; /* DF_CTL field */
3926 uint8_t Type; /* TYPE field */
3927 uint8_t Rctl; /* R_CTL field */
3928#endif
3929
3930#define BC 0x02 /* Broadcast Received - Fctl */
3931#define SI 0x04 /* Sequence Initiative */
3932#define LA 0x08 /* Ignore Link Attention state */
3933#define LS 0x80 /* Last Sequence */
3934 } hcsw;
3935 uint32_t reserved;
3936} WORD5;
3937
3938/* IOCB Command template for a generic response */
3939typedef struct {
3940 uint32_t reserved[4];
3941 PARM_ERR perr;
3942} GENERIC_RSP;
3943
3944/* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */
3945typedef struct {
3946 struct ulp_bde xrsqbde[2];
3947 uint32_t xrsqRo; /* Starting Relative Offset */
3948 WORD5 w5; /* Header control/status word */
3949} XR_SEQ_FIELDS;
3950
3951/* IOCB Command template for ELS_REQUEST */
3952typedef struct {
3953 struct ulp_bde elsReq;
3954 struct ulp_bde elsRsp;
3955
3956#ifdef __BIG_ENDIAN_BITFIELD
3957 uint32_t word4Rsvd:7;
3958 uint32_t fl:1;
3959 uint32_t myID:24;
3960 uint32_t word5Rsvd:8;
3961 uint32_t remoteID:24;
3962#else /* __LITTLE_ENDIAN_BITFIELD */
3963 uint32_t myID:24;
3964 uint32_t fl:1;
3965 uint32_t word4Rsvd:7;
3966 uint32_t remoteID:24;
3967 uint32_t word5Rsvd:8;
3968#endif
3969} ELS_REQUEST;
3970
3971/* IOCB Command template for RCV_ELS_REQ */
3972typedef struct {
3973 struct ulp_bde elsReq[2];
3974 uint32_t parmRo;
3975
3976#ifdef __BIG_ENDIAN_BITFIELD
3977 uint32_t word5Rsvd:8;
3978 uint32_t remoteID:24;
3979#else /* __LITTLE_ENDIAN_BITFIELD */
3980 uint32_t remoteID:24;
3981 uint32_t word5Rsvd:8;
3982#endif
3983} RCV_ELS_REQ;
3984
3985/* IOCB Command template for ABORT / CLOSE_XRI */
3986typedef struct {
3987 uint32_t rsvd[3];
3988 uint32_t abortType;
3989#define ABORT_TYPE_ABTX 0x00000000
3990#define ABORT_TYPE_ABTS 0x00000001
3991 uint32_t parm;
3992#ifdef __BIG_ENDIAN_BITFIELD
3993 uint16_t abortContextTag; /* ulpContext from command to abort/close */
3994 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
3995#else /* __LITTLE_ENDIAN_BITFIELD */
3996 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
3997 uint16_t abortContextTag; /* ulpContext from command to abort/close */
3998#endif
3999} AC_XRI;
4000
4001/* IOCB Command template for ABORT_MXRI64 */
4002typedef struct {
4003 uint32_t rsvd[3];
4004 uint32_t abortType;
4005 uint32_t parm;
4006 uint32_t iotag32;
4007} A_MXRI64;
4008
4009/* IOCB Command template for GET_RPI */
4010typedef struct {
4011 uint32_t rsvd[4];
4012 uint32_t parmRo;
4013#ifdef __BIG_ENDIAN_BITFIELD
4014 uint32_t word5Rsvd:8;
4015 uint32_t remoteID:24;
4016#else /* __LITTLE_ENDIAN_BITFIELD */
4017 uint32_t remoteID:24;
4018 uint32_t word5Rsvd:8;
4019#endif
4020} GET_RPI;
4021
4022/* IOCB Command template for all FCP Initiator commands */
4023typedef struct {
4024 struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */
4025 struct ulp_bde fcpi_rsp; /* Rcv buffer */
4026 uint32_t fcpi_parm;
4027 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
4028} FCPI_FIELDS;
4029
4030/* IOCB Command template for all FCP Target commands */
4031typedef struct {
4032 struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */
4033 uint32_t fcpt_Offset;
4034 uint32_t fcpt_Length; /* transfer ready for IWRITE */
4035} FCPT_FIELDS;
4036
4037/* SLI-2 IOCB structure definitions */
4038
4039/* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */
4040typedef struct {
4041 ULP_BDL bdl;
4042 uint32_t xrsqRo; /* Starting Relative Offset */
4043 WORD5 w5; /* Header control/status word */
4044} XMT_SEQ_FIELDS64;
4045
4046/* This word is remote ports D_ID for XMIT_ELS_RSP64 */
4047#define xmit_els_remoteID xrsqRo
4048
4049/* IOCB Command template for 64 bit RCV_SEQUENCE64 */
4050typedef struct {
4051 struct ulp_bde64 rcvBde;
4052 uint32_t rsvd1;
4053 uint32_t xrsqRo; /* Starting Relative Offset */
4054 WORD5 w5; /* Header control/status word */
4055} RCV_SEQ_FIELDS64;
4056
4057/* IOCB Command template for ELS_REQUEST64 */
4058typedef struct {
4059 ULP_BDL bdl;
4060#ifdef __BIG_ENDIAN_BITFIELD
4061 uint32_t word4Rsvd:7;
4062 uint32_t fl:1;
4063 uint32_t myID:24;
4064 uint32_t word5Rsvd:8;
4065 uint32_t remoteID:24;
4066#else /* __LITTLE_ENDIAN_BITFIELD */
4067 uint32_t myID:24;
4068 uint32_t fl:1;
4069 uint32_t word4Rsvd:7;
4070 uint32_t remoteID:24;
4071 uint32_t word5Rsvd:8;
4072#endif
4073} ELS_REQUEST64;
4074
4075/* IOCB Command template for GEN_REQUEST64 */
4076typedef struct {
4077 ULP_BDL bdl;
4078 uint32_t xrsqRo; /* Starting Relative Offset */
4079 WORD5 w5; /* Header control/status word */
4080} GEN_REQUEST64;
4081
4082/* IOCB Command template for RCV_ELS_REQ64 */
4083typedef struct {
4084 struct ulp_bde64 elsReq;
4085 uint32_t rcvd1;
4086 uint32_t parmRo;
4087
4088#ifdef __BIG_ENDIAN_BITFIELD
4089 uint32_t word5Rsvd:8;
4090 uint32_t remoteID:24;
4091#else /* __LITTLE_ENDIAN_BITFIELD */
4092 uint32_t remoteID:24;
4093 uint32_t word5Rsvd:8;
4094#endif
4095} RCV_ELS_REQ64;
4096
4097/* IOCB Command template for RCV_SEQ64 */
4098struct rcv_seq64 {
4099 struct ulp_bde64 elsReq;
4100 uint32_t hbq_1;
4101 uint32_t parmRo;
4102#ifdef __BIG_ENDIAN_BITFIELD
4103 uint32_t rctl:8;
4104 uint32_t type:8;
4105 uint32_t dfctl:8;
4106 uint32_t ls:1;
4107 uint32_t fs:1;
4108 uint32_t rsvd2:3;
4109 uint32_t si:1;
4110 uint32_t bc:1;
4111 uint32_t rsvd3:1;
4112#else /* __LITTLE_ENDIAN_BITFIELD */
4113 uint32_t rsvd3:1;
4114 uint32_t bc:1;
4115 uint32_t si:1;
4116 uint32_t rsvd2:3;
4117 uint32_t fs:1;
4118 uint32_t ls:1;
4119 uint32_t dfctl:8;
4120 uint32_t type:8;
4121 uint32_t rctl:8;
4122#endif
4123};
4124
4125/* IOCB Command template for all 64 bit FCP Initiator commands */
4126typedef struct {
4127 ULP_BDL bdl;
4128 uint32_t fcpi_parm;
4129 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
4130} FCPI_FIELDS64;
4131
4132/* IOCB Command template for all 64 bit FCP Target commands */
4133typedef struct {
4134 ULP_BDL bdl;
4135 uint32_t fcpt_Offset;
4136 uint32_t fcpt_Length; /* transfer ready for IWRITE */
4137} FCPT_FIELDS64;
4138
4139/* IOCB Command template for Async Status iocb commands */
4140typedef struct {
4141 uint32_t rsvd[4];
4142 uint32_t param;
4143#ifdef __BIG_ENDIAN_BITFIELD
4144 uint16_t evt_code; /* High order bits word 5 */
4145 uint16_t sub_ctxt_tag; /* Low order bits word 5 */
4146#else /* __LITTLE_ENDIAN_BITFIELD */
4147 uint16_t sub_ctxt_tag; /* High order bits word 5 */
4148 uint16_t evt_code; /* Low order bits word 5 */
4149#endif
4150} ASYNCSTAT_FIELDS;
4151#define ASYNC_TEMP_WARN 0x100
4152#define ASYNC_TEMP_SAFE 0x101
4153#define ASYNC_STATUS_CN 0x102
4154
4155/* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7)
4156 or CMD_IOCB_RCV_SEQ64_CX (0xB5) */
4157
4158struct rcv_sli3 {
4159#ifdef __BIG_ENDIAN_BITFIELD
4160 uint16_t ox_id;
4161 uint16_t seq_cnt;
4162
4163 uint16_t vpi;
4164 uint16_t word9Rsvd;
4165#else /* __LITTLE_ENDIAN */
4166 uint16_t seq_cnt;
4167 uint16_t ox_id;
4168
4169 uint16_t word9Rsvd;
4170 uint16_t vpi;
4171#endif
4172 uint32_t word10Rsvd;
4173 uint32_t acc_len; /* accumulated length */
4174 struct ulp_bde64 bde2;
4175};
4176
4177/* Structure used for a single HBQ entry */
4178struct lpfc_hbq_entry {
4179 struct ulp_bde64 bde;
4180 uint32_t buffer_tag;
4181};
4182
4183/* IOCB Command template for QUE_XRI64_CX (0xB3) command */
4184typedef struct {
4185 struct lpfc_hbq_entry buff;
4186 uint32_t rsvd;
4187 uint32_t rsvd1;
4188} QUE_XRI64_CX_FIELDS;
4189
4190struct que_xri64cx_ext_fields {
4191 uint32_t iotag64_low;
4192 uint32_t iotag64_high;
4193 uint32_t ebde_count;
4194 uint32_t rsvd;
4195 struct lpfc_hbq_entry buff[5];
4196};
4197
4198struct sli3_bg_fields {
4199 uint32_t filler[6]; /* word 8-13 in IOCB */
4200 uint32_t bghm; /* word 14 - BlockGuard High Water Mark */
4201/* Bitfields for bgstat (BlockGuard Status - word 15 of IOCB) */
4202#define BGS_BIDIR_BG_PROF_MASK 0xff000000
4203#define BGS_BIDIR_BG_PROF_SHIFT 24
4204#define BGS_BIDIR_ERR_COND_FLAGS_MASK 0x003f0000
4205#define BGS_BIDIR_ERR_COND_SHIFT 16
4206#define BGS_BG_PROFILE_MASK 0x0000ff00
4207#define BGS_BG_PROFILE_SHIFT 8
4208#define BGS_INVALID_PROF_MASK 0x00000020
4209#define BGS_INVALID_PROF_SHIFT 5
4210#define BGS_UNINIT_DIF_BLOCK_MASK 0x00000010
4211#define BGS_UNINIT_DIF_BLOCK_SHIFT 4
4212#define BGS_HI_WATER_MARK_PRESENT_MASK 0x00000008
4213#define BGS_HI_WATER_MARK_PRESENT_SHIFT 3
4214#define BGS_REFTAG_ERR_MASK 0x00000004
4215#define BGS_REFTAG_ERR_SHIFT 2
4216#define BGS_APPTAG_ERR_MASK 0x00000002
4217#define BGS_APPTAG_ERR_SHIFT 1
4218#define BGS_GUARD_ERR_MASK 0x00000001
4219#define BGS_GUARD_ERR_SHIFT 0
4220 uint32_t bgstat; /* word 15 - BlockGuard Status */
4221};
4222
4223static inline uint32_t
4224lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat)
4225{
4226 return (bgstat & BGS_BIDIR_BG_PROF_MASK) >>
4227 BGS_BIDIR_BG_PROF_SHIFT;
4228}
4229
4230static inline uint32_t
4231lpfc_bgs_get_bidir_err_cond(uint32_t bgstat)
4232{
4233 return (bgstat & BGS_BIDIR_ERR_COND_FLAGS_MASK) >>
4234 BGS_BIDIR_ERR_COND_SHIFT;
4235}
4236
4237static inline uint32_t
4238lpfc_bgs_get_bg_prof(uint32_t bgstat)
4239{
4240 return (bgstat & BGS_BG_PROFILE_MASK) >>
4241 BGS_BG_PROFILE_SHIFT;
4242}
4243
4244static inline uint32_t
4245lpfc_bgs_get_invalid_prof(uint32_t bgstat)
4246{
4247 return (bgstat & BGS_INVALID_PROF_MASK) >>
4248 BGS_INVALID_PROF_SHIFT;
4249}
4250
4251static inline uint32_t
4252lpfc_bgs_get_uninit_dif_block(uint32_t bgstat)
4253{
4254 return (bgstat & BGS_UNINIT_DIF_BLOCK_MASK) >>
4255 BGS_UNINIT_DIF_BLOCK_SHIFT;
4256}
4257
4258static inline uint32_t
4259lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat)
4260{
4261 return (bgstat & BGS_HI_WATER_MARK_PRESENT_MASK) >>
4262 BGS_HI_WATER_MARK_PRESENT_SHIFT;
4263}
4264
4265static inline uint32_t
4266lpfc_bgs_get_reftag_err(uint32_t bgstat)
4267{
4268 return (bgstat & BGS_REFTAG_ERR_MASK) >>
4269 BGS_REFTAG_ERR_SHIFT;
4270}
4271
4272static inline uint32_t
4273lpfc_bgs_get_apptag_err(uint32_t bgstat)
4274{
4275 return (bgstat & BGS_APPTAG_ERR_MASK) >>
4276 BGS_APPTAG_ERR_SHIFT;
4277}
4278
4279static inline uint32_t
4280lpfc_bgs_get_guard_err(uint32_t bgstat)
4281{
4282 return (bgstat & BGS_GUARD_ERR_MASK) >>
4283 BGS_GUARD_ERR_SHIFT;
4284}
4285
4286#define LPFC_EXT_DATA_BDE_COUNT 3
4287struct fcp_irw_ext {
4288 uint32_t io_tag64_low;
4289 uint32_t io_tag64_high;
4290#ifdef __BIG_ENDIAN_BITFIELD
4291 uint8_t reserved1;
4292 uint8_t reserved2;
4293 uint8_t reserved3;
4294 uint8_t ebde_count;
4295#else /* __LITTLE_ENDIAN */
4296 uint8_t ebde_count;
4297 uint8_t reserved3;
4298 uint8_t reserved2;
4299 uint8_t reserved1;
4300#endif
4301 uint32_t reserved4;
4302 struct ulp_bde64 rbde; /* response bde */
4303 struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT]; /* data BDE or BPL */
4304 uint8_t icd[32]; /* immediate command data (32 bytes) */
4305};
4306
4307typedef struct _IOCB { /* IOCB structure */
4308 union {
4309 GENERIC_RSP grsp; /* Generic response */
4310 XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */
4311 struct ulp_bde cont[3]; /* up to 3 continuation bdes */
4312 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */
4313 AC_XRI acxri; /* ABORT / CLOSE_XRI template */
4314 A_MXRI64 amxri; /* abort multiple xri command overlay */
4315 GET_RPI getrpi; /* GET_RPI template */
4316 FCPI_FIELDS fcpi; /* FCP Initiator template */
4317 FCPT_FIELDS fcpt; /* FCP target template */
4318
4319 /* SLI-2 structures */
4320
4321 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation
4322 * bde_64s */
4323 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */
4324 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */
4325 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */
4326 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */
4327 FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */
4328 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */
4329 ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */
4330 QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */
4331 struct rcv_seq64 rcvseq64; /* RCV_SEQ64 and RCV_CONT64 */
4332 struct sli4_bls_rsp bls_rsp; /* UNSOL ABTS BLS_RSP params */
4333 uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */
4334 } un;
4335 union {
4336 struct {
4337#ifdef __BIG_ENDIAN_BITFIELD
4338 uint16_t ulpContext; /* High order bits word 6 */
4339 uint16_t ulpIoTag; /* Low order bits word 6 */
4340#else /* __LITTLE_ENDIAN_BITFIELD */
4341 uint16_t ulpIoTag; /* Low order bits word 6 */
4342 uint16_t ulpContext; /* High order bits word 6 */
4343#endif
4344 } t1;
4345 struct {
4346#ifdef __BIG_ENDIAN_BITFIELD
4347 uint16_t ulpContext; /* High order bits word 6 */
4348 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
4349 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
4350#else /* __LITTLE_ENDIAN_BITFIELD */
4351 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
4352 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
4353 uint16_t ulpContext; /* High order bits word 6 */
4354#endif
4355 } t2;
4356 } un1;
4357#define ulpContext un1.t1.ulpContext
4358#define ulpIoTag un1.t1.ulpIoTag
4359#define ulpIoTag0 un1.t2.ulpIoTag0
4360
4361#ifdef __BIG_ENDIAN_BITFIELD
4362 uint32_t ulpTimeout:8;
4363 uint32_t ulpXS:1;
4364 uint32_t ulpFCP2Rcvy:1;
4365 uint32_t ulpPU:2;
4366 uint32_t ulpIr:1;
4367 uint32_t ulpClass:3;
4368 uint32_t ulpCommand:8;
4369 uint32_t ulpStatus:4;
4370 uint32_t ulpBdeCount:2;
4371 uint32_t ulpLe:1;
4372 uint32_t ulpOwner:1; /* Low order bit word 7 */
4373#else /* __LITTLE_ENDIAN_BITFIELD */
4374 uint32_t ulpOwner:1; /* Low order bit word 7 */
4375 uint32_t ulpLe:1;
4376 uint32_t ulpBdeCount:2;
4377 uint32_t ulpStatus:4;
4378 uint32_t ulpCommand:8;
4379 uint32_t ulpClass:3;
4380 uint32_t ulpIr:1;
4381 uint32_t ulpPU:2;
4382 uint32_t ulpFCP2Rcvy:1;
4383 uint32_t ulpXS:1;
4384 uint32_t ulpTimeout:8;
4385#endif
4386
4387 union {
4388 struct rcv_sli3 rcvsli3; /* words 8 - 15 */
4389
4390 /* words 8-31 used for que_xri_cx iocb */
4391 struct que_xri64cx_ext_fields que_xri64cx_ext_words;
4392 struct fcp_irw_ext fcp_ext;
4393 uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */
4394
4395 /* words 8-15 for BlockGuard */
4396 struct sli3_bg_fields sli3_bg;
4397 } unsli3;
4398
4399#define ulpCt_h ulpXS
4400#define ulpCt_l ulpFCP2Rcvy
4401
4402#define IOCB_FCP 1 /* IOCB is used for FCP ELS cmds-ulpRsvByte */
4403#define IOCB_IP 2 /* IOCB is used for IP ELS cmds */
4404#define PARM_UNUSED 0 /* PU field (Word 4) not used */
4405#define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */
4406#define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */
4407#define PARM_NPIV_DID 3
4408#define CLASS1 0 /* Class 1 */
4409#define CLASS2 1 /* Class 2 */
4410#define CLASS3 2 /* Class 3 */
4411#define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */
4412
4413#define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */
4414#define IOSTAT_FCP_RSP_ERROR 0x1
4415#define IOSTAT_REMOTE_STOP 0x2
4416#define IOSTAT_LOCAL_REJECT 0x3
4417#define IOSTAT_NPORT_RJT 0x4
4418#define IOSTAT_FABRIC_RJT 0x5
4419#define IOSTAT_NPORT_BSY 0x6
4420#define IOSTAT_FABRIC_BSY 0x7
4421#define IOSTAT_INTERMED_RSP 0x8
4422#define IOSTAT_LS_RJT 0x9
4423#define IOSTAT_BA_RJT 0xA
4424#define IOSTAT_RSVD1 0xB
4425#define IOSTAT_RSVD2 0xC
4426#define IOSTAT_RSVD3 0xD
4427#define IOSTAT_RSVD4 0xE
4428#define IOSTAT_NEED_BUFFER 0xF
4429#define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */
4430#define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */
4431#define IOSTAT_CNT 0x11
4432
4433} IOCB_t;
4434
4435
4436#define SLI1_SLIM_SIZE (4 * 1024)
4437
4438/* Up to 498 IOCBs will fit into 16k
4439 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384
4440 */
4441#define SLI2_SLIM_SIZE (64 * 1024)
4442
4443/* Maximum IOCBs that will fit in SLI2 slim */
4444#define MAX_SLI2_IOCB 498
4445#define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \
4446 (sizeof(MAILBOX_t) + sizeof(PCB_t) + \
4447 sizeof(uint32_t) * MAILBOX_EXT_WSIZE))
4448
4449/* HBQ entries are 4 words each = 4k */
4450#define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \
4451 lpfc_sli_hbq_count())
4452
4453struct lpfc_sli2_slim {
4454 MAILBOX_t mbx;
4455 uint32_t mbx_ext_words[MAILBOX_EXT_WSIZE];
4456 PCB_t pcb;
4457 IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE];
4458};
4459
4460/*
4461 * This function checks PCI device to allow special handling for LC HBAs.
4462 *
4463 * Parameters:
4464 * device : struct pci_dev 's device field
4465 *
4466 * return 1 => TRUE
4467 * 0 => FALSE
4468 */
4469static inline int
4470lpfc_is_LC_HBA(unsigned short device)
4471{
4472 if ((device == PCI_DEVICE_ID_TFLY) ||
4473 (device == PCI_DEVICE_ID_PFLY) ||
4474 (device == PCI_DEVICE_ID_LP101) ||
4475 (device == PCI_DEVICE_ID_BMID) ||
4476 (device == PCI_DEVICE_ID_BSMB) ||
4477 (device == PCI_DEVICE_ID_ZMID) ||
4478 (device == PCI_DEVICE_ID_ZSMB) ||
4479 (device == PCI_DEVICE_ID_SAT_MID) ||
4480 (device == PCI_DEVICE_ID_SAT_SMB) ||
4481 (device == PCI_DEVICE_ID_RFLY))
4482 return 1;
4483 else
4484 return 0;
4485}
4486
4487#define BPL_ALIGN_SZ 8 /* 8 byte alignment for bpl and mbufs */