Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
3 * Fibre Channel Host Bus Adapters. *
4 * Copyright (C) 2017-2026 Broadcom. All Rights Reserved. The term *
5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. *
6 * Copyright (C) 2009-2016 Emulex. All rights reserved. *
7 * EMULEX and SLI are trademarks of Emulex. *
8 * www.broadcom.com *
9 * *
10 * This program is free software; you can redistribute it and/or *
11 * modify it under the terms of version 2 of the GNU General *
12 * Public License as published by the Free Software Foundation. *
13 * This program is distributed in the hope that it will be useful. *
14 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
15 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
16 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
17 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
18 * TO BE LEGALLY INVALID. See the GNU General Public License for *
19 * more details, a copy of which can be found in the file COPYING *
20 * included with this package. *
21 *******************************************************************/
22
23#include <uapi/scsi/fc/fc_fs.h>
24#include <uapi/scsi/fc/fc_els.h>
25
26/* Macros to deal with bit fields. Each bit field must have 3 #defines
27 * associated with it (_SHIFT, _MASK, and _WORD).
28 * EG. For a bit field that is in the 7th bit of the "field4" field of a
29 * structure and is 2 bits in size the following #defines must exist:
30 * struct temp {
31 * uint32_t field1;
32 * uint32_t field2;
33 * uint32_t field3;
34 * uint32_t field4;
35 * #define example_bit_field_SHIFT 7
36 * #define example_bit_field_MASK 0x03
37 * #define example_bit_field_WORD field4
38 * uint32_t field5;
39 * };
40 * Then the macros below may be used to get or set the value of that field.
41 * EG. To get the value of the bit field from the above example:
42 * struct temp t1;
43 * value = bf_get(example_bit_field, &t1);
44 * And then to set that bit field:
45 * bf_set(example_bit_field, &t1, 2);
46 * Or clear that bit field:
47 * bf_set(example_bit_field, &t1, 0);
48 */
49#define bf_get_be32(name, ptr) \
50 ((be32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK)
51#define bf_get_le32(name, ptr) \
52 ((le32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK)
53#define bf_get(name, ptr) \
54 (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK)
55#define bf_set_le32(name, ptr, value) \
56 ((ptr)->name##_WORD = cpu_to_le32(((((value) & \
57 name##_MASK) << name##_SHIFT) | (le32_to_cpu((ptr)->name##_WORD) & \
58 ~(name##_MASK << name##_SHIFT)))))
59#define bf_set(name, ptr, value) \
60 ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \
61 ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT))))
62
63#define get_wqe_reqtag(x) (((x)->wqe.words[9] >> 0) & 0xFFFF)
64#define get_wqe_tmo(x) (((x)->wqe.words[7] >> 24) & 0x00FF)
65
66#define get_job_ulpword(x, y) ((x)->iocb.un.ulpWord[y])
67
68#define set_job_ulpstatus(x, y) bf_set(lpfc_wcqe_c_status, &(x)->wcqe_cmpl, y)
69#define set_job_ulpword4(x, y) ((&(x)->wcqe_cmpl)->parameter = y)
70
71struct dma_address {
72 uint32_t addr_lo;
73 uint32_t addr_hi;
74};
75
76struct lpfc_sli_intf {
77 uint32_t word0;
78#define lpfc_sli_intf_valid_SHIFT 29
79#define lpfc_sli_intf_valid_MASK 0x00000007
80#define lpfc_sli_intf_valid_WORD word0
81#define LPFC_SLI_INTF_VALID 6
82#define lpfc_sli_intf_sli_hint2_SHIFT 24
83#define lpfc_sli_intf_sli_hint2_MASK 0x0000001F
84#define lpfc_sli_intf_sli_hint2_WORD word0
85#define LPFC_SLI_INTF_SLI_HINT2_NONE 0
86#define lpfc_sli_intf_sli_hint1_SHIFT 16
87#define lpfc_sli_intf_sli_hint1_MASK 0x000000FF
88#define lpfc_sli_intf_sli_hint1_WORD word0
89#define LPFC_SLI_INTF_SLI_HINT1_NONE 0
90#define LPFC_SLI_INTF_SLI_HINT1_1 1
91#define LPFC_SLI_INTF_SLI_HINT1_2 2
92#define lpfc_sli_intf_if_type_SHIFT 12
93#define lpfc_sli_intf_if_type_MASK 0x0000000F
94#define lpfc_sli_intf_if_type_WORD word0
95#define LPFC_SLI_INTF_IF_TYPE_0 0
96#define LPFC_SLI_INTF_IF_TYPE_1 1
97#define LPFC_SLI_INTF_IF_TYPE_2 2
98#define LPFC_SLI_INTF_IF_TYPE_6 6
99#define lpfc_sli_intf_sli_family_SHIFT 8
100#define lpfc_sli_intf_sli_family_MASK 0x0000000F
101#define lpfc_sli_intf_sli_family_WORD word0
102#define LPFC_SLI_INTF_FAMILY_BE2 0x0
103#define LPFC_SLI_INTF_ASIC_ID 0x1 /* Refer to ASIC_ID register */
104#define LPFC_SLI_INTF_FAMILY_BE3 0x3
105#define LPFC_SLI_INTF_FAMILY_LNCR_A0 0xa
106#define LPFC_SLI_INTF_FAMILY_LNCR_B0 0xb
107#define LPFC_SLI_INTF_FAMILY_G6 0xc
108#define LPFC_SLI_INTF_FAMILY_G7 0xd
109#define LPFC_SLI_INTF_FAMILY_G7P 0xe
110#define lpfc_sli_intf_slirev_SHIFT 4
111#define lpfc_sli_intf_slirev_MASK 0x0000000F
112#define lpfc_sli_intf_slirev_WORD word0
113#define LPFC_SLI_INTF_REV_SLI3 3
114#define LPFC_SLI_INTF_REV_SLI4 4
115#define lpfc_sli_intf_func_type_SHIFT 0
116#define lpfc_sli_intf_func_type_MASK 0x00000001
117#define lpfc_sli_intf_func_type_WORD word0
118#define LPFC_SLI_INTF_IF_TYPE_PHYS 0
119#define LPFC_SLI_INTF_IF_TYPE_VIRT 1
120};
121
122struct lpfc_asic_id {
123 u32 word0;
124#define lpfc_asic_id_gen_num_SHIFT 8
125#define lpfc_asic_id_gen_num_MASK 0x000000FF
126#define lpfc_asic_id_gen_num_WORD word0
127#define LPFC_SLI_INTF_FAMILY_G8 0x10
128#define lpfc_asic_id_rev_num_SHIFT 0
129#define lpfc_asic_id_rev_num_MASK 0x000000FF
130#define lpfc_asic_id_rev_num_WORD word0
131};
132
133#define LPFC_SLI4_MBX_EMBED true
134#define LPFC_SLI4_MBX_NEMBED false
135
136#define LPFC_SLI4_MB_WORD_COUNT 64
137#define LPFC_MAX_MQ_PAGE 8
138#define LPFC_MAX_WQ_PAGE_V0 4
139#define LPFC_MAX_WQ_PAGE 8
140#define LPFC_MAX_RQ_PAGE 8
141#define LPFC_MAX_CQ_PAGE 4
142#define LPFC_MAX_EQ_PAGE 8
143
144#define LPFC_VIR_FUNC_MAX 32 /* Maximum number of virtual functions */
145#define LPFC_PCI_FUNC_MAX 5 /* Maximum number of PCI functions */
146#define LPFC_VFR_PAGE_SIZE 0x1000 /* 4KB BAR2 per-VF register page size */
147
148/* Define SLI4 Alignment requirements. */
149#define LPFC_ALIGN_16_BYTE 16
150#define LPFC_ALIGN_64_BYTE 64
151#define SLI4_PAGE_SIZE 4096
152
153/* Define SLI4 specific definitions. */
154#define LPFC_MQ_CQE_BYTE_OFFSET 256
155#define LPFC_MBX_CMD_HDR_LENGTH 16
156#define LPFC_MBX_ERROR_RANGE 0x4000
157#define LPFC_BMBX_BIT1_ADDR_HI 0x2
158#define LPFC_BMBX_BIT1_ADDR_LO 0
159#define LPFC_RPI_HDR_COUNT 64
160#define LPFC_HDR_TEMPLATE_SIZE 4096
161#define LPFC_RPI_ALLOC_ERROR 0xFFFF
162#define LPFC_FCF_RECORD_WD_CNT 132
163#define LPFC_ENTIRE_FCF_DATABASE 0
164#define LPFC_DFLT_FCF_INDEX 0
165
166/* Virtual function numbers */
167#define LPFC_VF0 0
168#define LPFC_VF1 1
169#define LPFC_VF2 2
170#define LPFC_VF3 3
171#define LPFC_VF4 4
172#define LPFC_VF5 5
173#define LPFC_VF6 6
174#define LPFC_VF7 7
175#define LPFC_VF8 8
176#define LPFC_VF9 9
177#define LPFC_VF10 10
178#define LPFC_VF11 11
179#define LPFC_VF12 12
180#define LPFC_VF13 13
181#define LPFC_VF14 14
182#define LPFC_VF15 15
183#define LPFC_VF16 16
184#define LPFC_VF17 17
185#define LPFC_VF18 18
186#define LPFC_VF19 19
187#define LPFC_VF20 20
188#define LPFC_VF21 21
189#define LPFC_VF22 22
190#define LPFC_VF23 23
191#define LPFC_VF24 24
192#define LPFC_VF25 25
193#define LPFC_VF26 26
194#define LPFC_VF27 27
195#define LPFC_VF28 28
196#define LPFC_VF29 29
197#define LPFC_VF30 30
198#define LPFC_VF31 31
199
200/* PCI function numbers */
201#define LPFC_PCI_FUNC0 0
202#define LPFC_PCI_FUNC1 1
203#define LPFC_PCI_FUNC2 2
204#define LPFC_PCI_FUNC3 3
205#define LPFC_PCI_FUNC4 4
206
207/* SLI4 interface type-2 PDEV_CTL register */
208#define LPFC_CTL_PDEV_CTL_OFFSET 0x414
209#define LPFC_CTL_PDEV_CTL_DRST 0x00000001
210#define LPFC_CTL_PDEV_CTL_FRST 0x00000002
211#define LPFC_CTL_PDEV_CTL_DD 0x00000004
212#define LPFC_CTL_PDEV_CTL_LC 0x00000008
213#define LPFC_CTL_PDEV_CTL_FRL_ALL 0x00
214#define LPFC_CTL_PDEV_CTL_FRL_FC_FCOE 0x10
215#define LPFC_CTL_PDEV_CTL_FRL_NIC 0x20
216#define LPFC_CTL_PDEV_CTL_DDL_RAS 0x1000000
217
218#define LPFC_FW_DUMP_REQUEST (LPFC_CTL_PDEV_CTL_DD | LPFC_CTL_PDEV_CTL_FRST)
219
220/* Active interrupt test count */
221#define LPFC_ACT_INTR_CNT 4
222
223/* Algrithmns for scheduling FCP commands to WQs */
224#define LPFC_FCP_SCHED_BY_HDWQ 0
225#define LPFC_FCP_SCHED_BY_CPU 1
226
227/* Algrithmns for NameServer Query after RSCN */
228#define LPFC_NS_QUERY_GID_FT 0
229#define LPFC_NS_QUERY_GID_PT 1
230
231/* Delay Multiplier constant */
232#define LPFC_DMULT_CONST 651042
233#define LPFC_DMULT_MAX 1023
234
235/* Configuration of Interrupts / sec for entire HBA port */
236#define LPFC_MIN_IMAX 5000
237#define LPFC_MAX_IMAX 5000000
238#define LPFC_DEF_IMAX 0
239
240#define LPFC_MAX_AUTO_EQ_DELAY 120
241#define LPFC_EQ_DELAY_STEP 15
242#define LPFC_EQD_ISR_TRIGGER 20000
243/* 1s intervals */
244#define LPFC_EQ_DELAY_MSECS 1000
245
246#define LPFC_MIN_CPU_MAP 0
247#define LPFC_MAX_CPU_MAP 1
248#define LPFC_HBA_CPU_MAP 1
249
250/* PORT_CAPABILITIES constants. */
251#define LPFC_MAX_SUPPORTED_PAGES 8
252
253enum ulp_bde64_word3 {
254 ULP_BDE64_SIZE_MASK = 0xffffff,
255
256 ULP_BDE64_TYPE_SHIFT = 24,
257 ULP_BDE64_TYPE_MASK = (0xff << ULP_BDE64_TYPE_SHIFT),
258
259 /* BDE (Host_resident) */
260 ULP_BDE64_TYPE_BDE_64 = (0x00 << ULP_BDE64_TYPE_SHIFT),
261 /* Immediate Data BDE */
262 ULP_BDE64_TYPE_BDE_IMMED = (0x01 << ULP_BDE64_TYPE_SHIFT),
263 /* BDE (Port-resident) */
264 ULP_BDE64_TYPE_BDE_64P = (0x02 << ULP_BDE64_TYPE_SHIFT),
265 /* Input BDE (Host-resident) */
266 ULP_BDE64_TYPE_BDE_64I = (0x08 << ULP_BDE64_TYPE_SHIFT),
267 /* Input BDE (Port-resident) */
268 ULP_BDE64_TYPE_BDE_64IP = (0x0A << ULP_BDE64_TYPE_SHIFT),
269 /* BLP (Host-resident) */
270 ULP_BDE64_TYPE_BLP_64 = (0x40 << ULP_BDE64_TYPE_SHIFT),
271 /* BLP (Port-resident) */
272 ULP_BDE64_TYPE_BLP_64P = (0x42 << ULP_BDE64_TYPE_SHIFT),
273};
274
275struct ulp_bde64_le {
276 __le32 type_size; /* type 31:24, size 23:0 */
277 __le32 addr_low;
278 __le32 addr_high;
279};
280
281struct ulp_bde64 {
282 union ULP_BDE_TUS {
283 uint32_t w;
284 struct {
285#ifdef __BIG_ENDIAN_BITFIELD
286 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED
287 VALUE !! */
288 uint32_t bdeSize:24; /* Size of buffer (in bytes) */
289#else /* __LITTLE_ENDIAN_BITFIELD */
290 uint32_t bdeSize:24; /* Size of buffer (in bytes) */
291 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED
292 VALUE !! */
293#endif
294#define BUFF_TYPE_BDE_64 0x00 /* BDE (Host_resident) */
295#define BUFF_TYPE_BDE_IMMED 0x01 /* Immediate Data BDE */
296#define BUFF_TYPE_BDE_64P 0x02 /* BDE (Port-resident) */
297#define BUFF_TYPE_BDE_64I 0x08 /* Input BDE (Host-resident) */
298#define BUFF_TYPE_BDE_64IP 0x0A /* Input BDE (Port-resident) */
299#define BUFF_TYPE_BLP_64 0x40 /* BLP (Host-resident) */
300#define BUFF_TYPE_BLP_64P 0x42 /* BLP (Port-resident) */
301 } f;
302 } tus;
303 uint32_t addrLow;
304 uint32_t addrHigh;
305};
306
307/* Maximun size of immediate data that can fit into a 128 byte WQE */
308#define LPFC_MAX_BDE_IMM_SIZE 64
309
310struct lpfc_sli4_flags {
311 uint32_t word0;
312#define lpfc_idx_rsrc_rdy_SHIFT 0
313#define lpfc_idx_rsrc_rdy_MASK 0x00000001
314#define lpfc_idx_rsrc_rdy_WORD word0
315#define LPFC_IDX_RSRC_RDY 1
316#define lpfc_rpi_rsrc_rdy_SHIFT 1
317#define lpfc_rpi_rsrc_rdy_MASK 0x00000001
318#define lpfc_rpi_rsrc_rdy_WORD word0
319#define LPFC_RPI_RSRC_RDY 1
320#define lpfc_vpi_rsrc_rdy_SHIFT 2
321#define lpfc_vpi_rsrc_rdy_MASK 0x00000001
322#define lpfc_vpi_rsrc_rdy_WORD word0
323#define LPFC_VPI_RSRC_RDY 1
324#define lpfc_vfi_rsrc_rdy_SHIFT 3
325#define lpfc_vfi_rsrc_rdy_MASK 0x00000001
326#define lpfc_vfi_rsrc_rdy_WORD word0
327#define LPFC_VFI_RSRC_RDY 1
328#define lpfc_ftr_ashdr_SHIFT 4
329#define lpfc_ftr_ashdr_MASK 0x00000001
330#define lpfc_ftr_ashdr_WORD word0
331};
332
333struct sli4_bls_rsp {
334 uint32_t word0_rsvd; /* Word0 must be reserved */
335 uint32_t word1;
336#define lpfc_abts_orig_SHIFT 0
337#define lpfc_abts_orig_MASK 0x00000001
338#define lpfc_abts_orig_WORD word1
339#define LPFC_ABTS_UNSOL_RSP 1
340#define LPFC_ABTS_UNSOL_INT 0
341 uint32_t word2;
342#define lpfc_abts_rxid_SHIFT 0
343#define lpfc_abts_rxid_MASK 0x0000FFFF
344#define lpfc_abts_rxid_WORD word2
345#define lpfc_abts_oxid_SHIFT 16
346#define lpfc_abts_oxid_MASK 0x0000FFFF
347#define lpfc_abts_oxid_WORD word2
348 uint32_t word3;
349#define lpfc_vndr_code_SHIFT 0
350#define lpfc_vndr_code_MASK 0x000000FF
351#define lpfc_vndr_code_WORD word3
352#define lpfc_rsn_expln_SHIFT 8
353#define lpfc_rsn_expln_MASK 0x000000FF
354#define lpfc_rsn_expln_WORD word3
355#define lpfc_rsn_code_SHIFT 16
356#define lpfc_rsn_code_MASK 0x000000FF
357#define lpfc_rsn_code_WORD word3
358
359 uint32_t word4;
360 uint32_t word5_rsvd; /* Word5 must be reserved */
361};
362
363/* event queue entry structure */
364struct lpfc_eqe {
365 uint32_t word0;
366#define lpfc_eqe_resource_id_SHIFT 16
367#define lpfc_eqe_resource_id_MASK 0x0000FFFF
368#define lpfc_eqe_resource_id_WORD word0
369#define lpfc_eqe_minor_code_SHIFT 4
370#define lpfc_eqe_minor_code_MASK 0x00000FFF
371#define lpfc_eqe_minor_code_WORD word0
372#define lpfc_eqe_major_code_SHIFT 1
373#define lpfc_eqe_major_code_MASK 0x00000007
374#define lpfc_eqe_major_code_WORD word0
375#define lpfc_eqe_valid_SHIFT 0
376#define lpfc_eqe_valid_MASK 0x00000001
377#define lpfc_eqe_valid_WORD word0
378};
379
380/* completion queue entry structure (common fields for all cqe types) */
381struct lpfc_cqe {
382 uint32_t reserved0;
383 uint32_t reserved1;
384 uint32_t reserved2;
385 uint32_t word3;
386#define lpfc_cqe_valid_SHIFT 31
387#define lpfc_cqe_valid_MASK 0x00000001
388#define lpfc_cqe_valid_WORD word3
389#define lpfc_cqe_code_SHIFT 16
390#define lpfc_cqe_code_MASK 0x000000FF
391#define lpfc_cqe_code_WORD word3
392};
393
394/* Completion Queue Entry Status Codes */
395#define CQE_STATUS_SUCCESS 0x0
396#define CQE_STATUS_FCP_RSP_FAILURE 0x1
397#define CQE_STATUS_REMOTE_STOP 0x2
398#define CQE_STATUS_LOCAL_REJECT 0x3
399#define CQE_STATUS_NPORT_RJT 0x4
400#define CQE_STATUS_FABRIC_RJT 0x5
401#define CQE_STATUS_NPORT_BSY 0x6
402#define CQE_STATUS_FABRIC_BSY 0x7
403#define CQE_STATUS_INTERMED_RSP 0x8
404#define CQE_STATUS_LS_RJT 0x9
405#define CQE_STATUS_CMD_REJECT 0xb
406#define CQE_STATUS_FCP_TGT_LENCHECK 0xc
407#define CQE_STATUS_NEED_BUFF_ENTRY 0xf
408#define CQE_STATUS_DI_ERROR 0x16
409
410/* Status returned by hardware (valid only if status = CQE_STATUS_SUCCESS). */
411#define CQE_HW_STATUS_NO_ERR 0x0
412#define CQE_HW_STATUS_UNDERRUN 0x1
413#define CQE_HW_STATUS_OVERRUN 0x2
414
415/* Completion Queue Entry Codes */
416#define CQE_CODE_COMPL_WQE 0x1
417#define CQE_CODE_RELEASE_WQE 0x2
418#define CQE_CODE_RECEIVE 0x4
419#define CQE_CODE_XRI_ABORTED 0x5
420#define CQE_CODE_RECEIVE_V1 0x9
421#define CQE_CODE_NVME_ERSP 0xd
422
423/*
424 * Define mask value for xri_aborted and wcqe completed CQE extended status.
425 * Currently, extended status is limited to 9 bits (0x0 -> 0x103) .
426 */
427#define WCQE_PARAM_MASK 0x1FF
428
429/* completion queue entry for wqe completions */
430struct lpfc_wcqe_complete {
431 uint32_t word0;
432#define lpfc_wcqe_c_request_tag_SHIFT 16
433#define lpfc_wcqe_c_request_tag_MASK 0x0000FFFF
434#define lpfc_wcqe_c_request_tag_WORD word0
435#define lpfc_wcqe_c_status_SHIFT 8
436#define lpfc_wcqe_c_status_MASK 0x000000FF
437#define lpfc_wcqe_c_status_WORD word0
438#define lpfc_wcqe_c_hw_status_SHIFT 0
439#define lpfc_wcqe_c_hw_status_MASK 0x000000FF
440#define lpfc_wcqe_c_hw_status_WORD word0
441#define lpfc_wcqe_c_ersp0_SHIFT 0
442#define lpfc_wcqe_c_ersp0_MASK 0x0000FFFF
443#define lpfc_wcqe_c_ersp0_WORD word0
444 uint32_t total_data_placed;
445#define lpfc_wcqe_c_cmf_cg_SHIFT 31
446#define lpfc_wcqe_c_cmf_cg_MASK 0x00000001
447#define lpfc_wcqe_c_cmf_cg_WORD total_data_placed
448#define lpfc_wcqe_c_cmf_bw_SHIFT 0
449#define lpfc_wcqe_c_cmf_bw_MASK 0x0FFFFFFF
450#define lpfc_wcqe_c_cmf_bw_WORD total_data_placed
451 uint32_t parameter;
452#define lpfc_wcqe_c_enc_SHIFT 31
453#define lpfc_wcqe_c_enc_MASK 0x00000001
454#define lpfc_wcqe_c_enc_WORD parameter
455#define lpfc_wcqe_c_enc_lvl_SHIFT 30
456#define lpfc_wcqe_c_enc_lvl_MASK 0x00000001
457#define lpfc_wcqe_c_enc_lvl_WORD parameter
458#define lpfc_wcqe_c_bg_edir_SHIFT 5
459#define lpfc_wcqe_c_bg_edir_MASK 0x00000001
460#define lpfc_wcqe_c_bg_edir_WORD parameter
461#define lpfc_wcqe_c_bg_tdpv_SHIFT 3
462#define lpfc_wcqe_c_bg_tdpv_MASK 0x00000001
463#define lpfc_wcqe_c_bg_tdpv_WORD parameter
464#define lpfc_wcqe_c_bg_re_SHIFT 2
465#define lpfc_wcqe_c_bg_re_MASK 0x00000001
466#define lpfc_wcqe_c_bg_re_WORD parameter
467#define lpfc_wcqe_c_bg_ae_SHIFT 1
468#define lpfc_wcqe_c_bg_ae_MASK 0x00000001
469#define lpfc_wcqe_c_bg_ae_WORD parameter
470#define lpfc_wcqe_c_bg_ge_SHIFT 0
471#define lpfc_wcqe_c_bg_ge_MASK 0x00000001
472#define lpfc_wcqe_c_bg_ge_WORD parameter
473 uint32_t word3;
474#define lpfc_wcqe_c_valid_SHIFT lpfc_cqe_valid_SHIFT
475#define lpfc_wcqe_c_valid_MASK lpfc_cqe_valid_MASK
476#define lpfc_wcqe_c_valid_WORD lpfc_cqe_valid_WORD
477#define lpfc_wcqe_c_xb_SHIFT 28
478#define lpfc_wcqe_c_xb_MASK 0x00000001
479#define lpfc_wcqe_c_xb_WORD word3
480#define lpfc_wcqe_c_pv_SHIFT 27
481#define lpfc_wcqe_c_pv_MASK 0x00000001
482#define lpfc_wcqe_c_pv_WORD word3
483#define lpfc_wcqe_c_priority_SHIFT 24
484#define lpfc_wcqe_c_priority_MASK 0x00000007
485#define lpfc_wcqe_c_priority_WORD word3
486#define lpfc_wcqe_c_code_SHIFT lpfc_cqe_code_SHIFT
487#define lpfc_wcqe_c_code_MASK lpfc_cqe_code_MASK
488#define lpfc_wcqe_c_code_WORD lpfc_cqe_code_WORD
489#define lpfc_wcqe_c_sqhead_SHIFT 0
490#define lpfc_wcqe_c_sqhead_MASK 0x0000FFFF
491#define lpfc_wcqe_c_sqhead_WORD word3
492};
493
494/* completion queue entry for wqe release */
495struct lpfc_wcqe_release {
496 uint32_t reserved0;
497 uint32_t reserved1;
498 uint32_t word2;
499#define lpfc_wcqe_r_wq_id_SHIFT 16
500#define lpfc_wcqe_r_wq_id_MASK 0x0000FFFF
501#define lpfc_wcqe_r_wq_id_WORD word2
502#define lpfc_wcqe_r_wqe_index_SHIFT 0
503#define lpfc_wcqe_r_wqe_index_MASK 0x0000FFFF
504#define lpfc_wcqe_r_wqe_index_WORD word2
505 uint32_t word3;
506#define lpfc_wcqe_r_valid_SHIFT lpfc_cqe_valid_SHIFT
507#define lpfc_wcqe_r_valid_MASK lpfc_cqe_valid_MASK
508#define lpfc_wcqe_r_valid_WORD lpfc_cqe_valid_WORD
509#define lpfc_wcqe_r_code_SHIFT lpfc_cqe_code_SHIFT
510#define lpfc_wcqe_r_code_MASK lpfc_cqe_code_MASK
511#define lpfc_wcqe_r_code_WORD lpfc_cqe_code_WORD
512};
513
514struct sli4_wcqe_xri_aborted {
515 uint32_t word0;
516#define lpfc_wcqe_xa_status_SHIFT 8
517#define lpfc_wcqe_xa_status_MASK 0x000000FF
518#define lpfc_wcqe_xa_status_WORD word0
519 uint32_t parameter;
520 uint32_t word2;
521#define lpfc_wcqe_xa_remote_xid_SHIFT 16
522#define lpfc_wcqe_xa_remote_xid_MASK 0x0000FFFF
523#define lpfc_wcqe_xa_remote_xid_WORD word2
524#define lpfc_wcqe_xa_xri_SHIFT 0
525#define lpfc_wcqe_xa_xri_MASK 0x0000FFFF
526#define lpfc_wcqe_xa_xri_WORD word2
527 uint32_t word3;
528#define lpfc_wcqe_xa_valid_SHIFT lpfc_cqe_valid_SHIFT
529#define lpfc_wcqe_xa_valid_MASK lpfc_cqe_valid_MASK
530#define lpfc_wcqe_xa_valid_WORD lpfc_cqe_valid_WORD
531#define lpfc_wcqe_xa_ia_SHIFT 30
532#define lpfc_wcqe_xa_ia_MASK 0x00000001
533#define lpfc_wcqe_xa_ia_WORD word3
534#define CQE_XRI_ABORTED_IA_REMOTE 0
535#define CQE_XRI_ABORTED_IA_LOCAL 1
536#define lpfc_wcqe_xa_br_SHIFT 29
537#define lpfc_wcqe_xa_br_MASK 0x00000001
538#define lpfc_wcqe_xa_br_WORD word3
539#define CQE_XRI_ABORTED_BR_BA_ACC 0
540#define CQE_XRI_ABORTED_BR_BA_RJT 1
541#define lpfc_wcqe_xa_eo_SHIFT 28
542#define lpfc_wcqe_xa_eo_MASK 0x00000001
543#define lpfc_wcqe_xa_eo_WORD word3
544#define CQE_XRI_ABORTED_EO_REMOTE 0
545#define CQE_XRI_ABORTED_EO_LOCAL 1
546#define lpfc_wcqe_xa_code_SHIFT lpfc_cqe_code_SHIFT
547#define lpfc_wcqe_xa_code_MASK lpfc_cqe_code_MASK
548#define lpfc_wcqe_xa_code_WORD lpfc_cqe_code_WORD
549};
550
551/* completion queue entry structure for rqe completion */
552struct lpfc_rcqe {
553 uint32_t word0;
554#define lpfc_rcqe_iv_SHIFT 31
555#define lpfc_rcqe_iv_MASK 0x00000001
556#define lpfc_rcqe_iv_WORD word0
557#define lpfc_rcqe_status_SHIFT 8
558#define lpfc_rcqe_status_MASK 0x000000FF
559#define lpfc_rcqe_status_WORD word0
560#define FC_STATUS_RQ_SUCCESS 0x10 /* Async receive successful */
561#define FC_STATUS_RQ_BUF_LEN_EXCEEDED 0x11 /* payload truncated */
562#define FC_STATUS_INSUFF_BUF_NEED_BUF 0x12 /* Insufficient buffers */
563#define FC_STATUS_INSUFF_BUF_FRM_DISC 0x13 /* Frame Discard */
564#define FC_STATUS_RQ_DMA_FAILURE 0x14 /* DMA failure */
565 uint32_t word1;
566#define lpfc_rcqe_fcf_id_v1_SHIFT 0
567#define lpfc_rcqe_fcf_id_v1_MASK 0x0000003F
568#define lpfc_rcqe_fcf_id_v1_WORD word1
569 uint32_t word2;
570#define lpfc_rcqe_length_SHIFT 16
571#define lpfc_rcqe_length_MASK 0x0000FFFF
572#define lpfc_rcqe_length_WORD word2
573#define lpfc_rcqe_rq_id_SHIFT 6
574#define lpfc_rcqe_rq_id_MASK 0x000003FF
575#define lpfc_rcqe_rq_id_WORD word2
576#define lpfc_rcqe_fcf_id_SHIFT 0
577#define lpfc_rcqe_fcf_id_MASK 0x0000003F
578#define lpfc_rcqe_fcf_id_WORD word2
579#define lpfc_rcqe_rq_id_v1_SHIFT 0
580#define lpfc_rcqe_rq_id_v1_MASK 0x0000FFFF
581#define lpfc_rcqe_rq_id_v1_WORD word2
582 uint32_t word3;
583#define lpfc_rcqe_valid_SHIFT lpfc_cqe_valid_SHIFT
584#define lpfc_rcqe_valid_MASK lpfc_cqe_valid_MASK
585#define lpfc_rcqe_valid_WORD lpfc_cqe_valid_WORD
586#define lpfc_rcqe_port_SHIFT 30
587#define lpfc_rcqe_port_MASK 0x00000001
588#define lpfc_rcqe_port_WORD word3
589#define lpfc_rcqe_hdr_length_SHIFT 24
590#define lpfc_rcqe_hdr_length_MASK 0x0000001F
591#define lpfc_rcqe_hdr_length_WORD word3
592#define lpfc_rcqe_code_SHIFT lpfc_cqe_code_SHIFT
593#define lpfc_rcqe_code_MASK lpfc_cqe_code_MASK
594#define lpfc_rcqe_code_WORD lpfc_cqe_code_WORD
595#define lpfc_rcqe_eof_SHIFT 8
596#define lpfc_rcqe_eof_MASK 0x000000FF
597#define lpfc_rcqe_eof_WORD word3
598#define FCOE_EOFn 0x41
599#define FCOE_EOFt 0x42
600#define FCOE_EOFni 0x49
601#define FCOE_EOFa 0x50
602#define lpfc_rcqe_sof_SHIFT 0
603#define lpfc_rcqe_sof_MASK 0x000000FF
604#define lpfc_rcqe_sof_WORD word3
605#define FCOE_SOFi2 0x2d
606#define FCOE_SOFi3 0x2e
607#define FCOE_SOFn2 0x35
608#define FCOE_SOFn3 0x36
609};
610
611struct lpfc_rqe {
612 uint32_t address_hi;
613 uint32_t address_lo;
614};
615
616/* buffer descriptors */
617struct lpfc_bde4 {
618 uint32_t addr_hi;
619 uint32_t addr_lo;
620 uint32_t word2;
621#define lpfc_bde4_last_SHIFT 31
622#define lpfc_bde4_last_MASK 0x00000001
623#define lpfc_bde4_last_WORD word2
624#define lpfc_bde4_sge_offset_SHIFT 0
625#define lpfc_bde4_sge_offset_MASK 0x000003FF
626#define lpfc_bde4_sge_offset_WORD word2
627 uint32_t word3;
628#define lpfc_bde4_length_SHIFT 0
629#define lpfc_bde4_length_MASK 0x000000FF
630#define lpfc_bde4_length_WORD word3
631};
632
633struct lpfc_register {
634 uint32_t word0;
635};
636
637#define LPFC_PORT_SEM_UE_RECOVERABLE 0xE000
638#define LPFC_PORT_SEM_MASK 0xF000
639
640/* The following are config space register offsets */
641#define LPFC_ASIC_ID_OFFSET 0x0308
642
643/* The following BAR0 Registers apply to SLI4 if_type 0 UCNAs. */
644#define LPFC_UERR_STATUS_HI 0x00A4
645#define LPFC_UERR_STATUS_LO 0x00A0
646#define LPFC_UE_MASK_HI 0x00AC
647#define LPFC_UE_MASK_LO 0x00A8
648
649/* The following BAR0 register sets are defined for if_type 0 and 2 UCNAs. */
650#define LPFC_SLI_INTF 0x0058
651
652#define LPFC_CTL_PORT_SEM_OFFSET 0x400
653#define lpfc_port_smphr_perr_SHIFT 31
654#define lpfc_port_smphr_perr_MASK 0x1
655#define lpfc_port_smphr_perr_WORD word0
656#define lpfc_port_smphr_sfi_SHIFT 30
657#define lpfc_port_smphr_sfi_MASK 0x1
658#define lpfc_port_smphr_sfi_WORD word0
659#define lpfc_port_smphr_nip_SHIFT 29
660#define lpfc_port_smphr_nip_MASK 0x1
661#define lpfc_port_smphr_nip_WORD word0
662#define lpfc_port_smphr_ipc_SHIFT 28
663#define lpfc_port_smphr_ipc_MASK 0x1
664#define lpfc_port_smphr_ipc_WORD word0
665#define lpfc_port_smphr_scr1_SHIFT 27
666#define lpfc_port_smphr_scr1_MASK 0x1
667#define lpfc_port_smphr_scr1_WORD word0
668#define lpfc_port_smphr_scr2_SHIFT 26
669#define lpfc_port_smphr_scr2_MASK 0x1
670#define lpfc_port_smphr_scr2_WORD word0
671#define lpfc_port_smphr_host_scratch_SHIFT 16
672#define lpfc_port_smphr_host_scratch_MASK 0xFF
673#define lpfc_port_smphr_host_scratch_WORD word0
674#define lpfc_port_smphr_port_status_SHIFT 0
675#define lpfc_port_smphr_port_status_MASK 0xFFFF
676#define lpfc_port_smphr_port_status_WORD word0
677
678#define LPFC_POST_STAGE_POWER_ON_RESET 0x0000
679#define LPFC_POST_STAGE_AWAITING_HOST_RDY 0x0001
680#define LPFC_POST_STAGE_HOST_RDY 0x0002
681#define LPFC_POST_STAGE_BE_RESET 0x0003
682#define LPFC_POST_STAGE_SEEPROM_CS_START 0x0100
683#define LPFC_POST_STAGE_SEEPROM_CS_DONE 0x0101
684#define LPFC_POST_STAGE_DDR_CONFIG_START 0x0200
685#define LPFC_POST_STAGE_DDR_CONFIG_DONE 0x0201
686#define LPFC_POST_STAGE_DDR_CALIBRATE_START 0x0300
687#define LPFC_POST_STAGE_DDR_CALIBRATE_DONE 0x0301
688#define LPFC_POST_STAGE_DDR_TEST_START 0x0400
689#define LPFC_POST_STAGE_DDR_TEST_DONE 0x0401
690#define LPFC_POST_STAGE_REDBOOT_INIT_START 0x0600
691#define LPFC_POST_STAGE_REDBOOT_INIT_DONE 0x0601
692#define LPFC_POST_STAGE_FW_IMAGE_LOAD_START 0x0700
693#define LPFC_POST_STAGE_FW_IMAGE_LOAD_DONE 0x0701
694#define LPFC_POST_STAGE_ARMFW_START 0x0800
695#define LPFC_POST_STAGE_DHCP_QUERY_START 0x0900
696#define LPFC_POST_STAGE_DHCP_QUERY_DONE 0x0901
697#define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_START 0x0A00
698#define LPFC_POST_STAGE_BOOT_TARGET_DISCOVERY_DONE 0x0A01
699#define LPFC_POST_STAGE_RC_OPTION_SET 0x0B00
700#define LPFC_POST_STAGE_SWITCH_LINK 0x0B01
701#define LPFC_POST_STAGE_SEND_ICDS_MESSAGE 0x0B02
702#define LPFC_POST_STAGE_PERFROM_TFTP 0x0B03
703#define LPFC_POST_STAGE_PARSE_XML 0x0B04
704#define LPFC_POST_STAGE_DOWNLOAD_IMAGE 0x0B05
705#define LPFC_POST_STAGE_FLASH_IMAGE 0x0B06
706#define LPFC_POST_STAGE_RC_DONE 0x0B07
707#define LPFC_POST_STAGE_REBOOT_SYSTEM 0x0B08
708#define LPFC_POST_STAGE_MAC_ADDRESS 0x0C00
709#define LPFC_POST_STAGE_PORT_READY 0xC000
710#define LPFC_POST_STAGE_PORT_UE 0xF000
711
712#define LPFC_CTL_PORT_STA_OFFSET 0x404
713#define lpfc_sliport_status_err_SHIFT 31
714#define lpfc_sliport_status_err_MASK 0x1
715#define lpfc_sliport_status_err_WORD word0
716#define lpfc_sliport_status_end_SHIFT 30
717#define lpfc_sliport_status_end_MASK 0x1
718#define lpfc_sliport_status_end_WORD word0
719#define lpfc_sliport_status_oti_SHIFT 29
720#define lpfc_sliport_status_oti_MASK 0x1
721#define lpfc_sliport_status_oti_WORD word0
722#define lpfc_sliport_status_dip_SHIFT 25
723#define lpfc_sliport_status_dip_MASK 0x1
724#define lpfc_sliport_status_dip_WORD word0
725#define lpfc_sliport_status_rn_SHIFT 24
726#define lpfc_sliport_status_rn_MASK 0x1
727#define lpfc_sliport_status_rn_WORD word0
728#define lpfc_sliport_status_rdy_SHIFT 23
729#define lpfc_sliport_status_rdy_MASK 0x1
730#define lpfc_sliport_status_rdy_WORD word0
731#define lpfc_sliport_status_pldv_SHIFT 0
732#define lpfc_sliport_status_pldv_MASK 0x1
733#define lpfc_sliport_status_pldv_WORD word0
734#define CFG_PLD 0x3C
735#define MAX_IF_TYPE_2_RESETS 6
736
737#define LPFC_CTL_PORT_CTL_OFFSET 0x408
738#define lpfc_sliport_ctrl_end_SHIFT 30
739#define lpfc_sliport_ctrl_end_MASK 0x1
740#define lpfc_sliport_ctrl_end_WORD word0
741#define LPFC_SLIPORT_LITTLE_ENDIAN 0
742#define LPFC_SLIPORT_BIG_ENDIAN 1
743#define lpfc_sliport_ctrl_ip_SHIFT 27
744#define lpfc_sliport_ctrl_ip_MASK 0x1
745#define lpfc_sliport_ctrl_ip_WORD word0
746#define LPFC_SLIPORT_INIT_PORT 1
747
748#define LPFC_CTL_PORT_ER1_OFFSET 0x40C
749#define LPFC_CTL_PORT_ER2_OFFSET 0x410
750
751#define LPFC_CTL_PORT_EQ_DELAY_OFFSET 0x418
752#define lpfc_sliport_eqdelay_delay_SHIFT 16
753#define lpfc_sliport_eqdelay_delay_MASK 0xffff
754#define lpfc_sliport_eqdelay_delay_WORD word0
755#define lpfc_sliport_eqdelay_id_SHIFT 0
756#define lpfc_sliport_eqdelay_id_MASK 0xfff
757#define lpfc_sliport_eqdelay_id_WORD word0
758#define LPFC_SEC_TO_USEC 1000000
759#define LPFC_SEC_TO_MSEC 1000
760#define LPFC_MSECS_TO_SECS(msecs) ((msecs) / 1000)
761
762/* The following Registers apply to SLI4 if_type 0 UCNAs. They typically
763 * reside in BAR 2.
764 */
765#define LPFC_SLIPORT_IF0_SMPHR 0x00AC
766
767#define LPFC_IMR_MASK_ALL 0xFFFFFFFF
768#define LPFC_ISCR_CLEAR_ALL 0xFFFFFFFF
769
770#define LPFC_HST_ISR0 0x0C18
771#define LPFC_HST_ISR1 0x0C1C
772#define LPFC_HST_ISR2 0x0C20
773#define LPFC_HST_ISR3 0x0C24
774#define LPFC_HST_ISR4 0x0C28
775
776#define LPFC_HST_IMR0 0x0C48
777#define LPFC_HST_IMR1 0x0C4C
778#define LPFC_HST_IMR2 0x0C50
779#define LPFC_HST_IMR3 0x0C54
780#define LPFC_HST_IMR4 0x0C58
781
782#define LPFC_HST_ISCR0 0x0C78
783#define LPFC_HST_ISCR1 0x0C7C
784#define LPFC_HST_ISCR2 0x0C80
785#define LPFC_HST_ISCR3 0x0C84
786#define LPFC_HST_ISCR4 0x0C88
787
788#define LPFC_SLI4_INTR0 BIT0
789#define LPFC_SLI4_INTR1 BIT1
790#define LPFC_SLI4_INTR2 BIT2
791#define LPFC_SLI4_INTR3 BIT3
792#define LPFC_SLI4_INTR4 BIT4
793#define LPFC_SLI4_INTR5 BIT5
794#define LPFC_SLI4_INTR6 BIT6
795#define LPFC_SLI4_INTR7 BIT7
796#define LPFC_SLI4_INTR8 BIT8
797#define LPFC_SLI4_INTR9 BIT9
798#define LPFC_SLI4_INTR10 BIT10
799#define LPFC_SLI4_INTR11 BIT11
800#define LPFC_SLI4_INTR12 BIT12
801#define LPFC_SLI4_INTR13 BIT13
802#define LPFC_SLI4_INTR14 BIT14
803#define LPFC_SLI4_INTR15 BIT15
804#define LPFC_SLI4_INTR16 BIT16
805#define LPFC_SLI4_INTR17 BIT17
806#define LPFC_SLI4_INTR18 BIT18
807#define LPFC_SLI4_INTR19 BIT19
808#define LPFC_SLI4_INTR20 BIT20
809#define LPFC_SLI4_INTR21 BIT21
810#define LPFC_SLI4_INTR22 BIT22
811#define LPFC_SLI4_INTR23 BIT23
812#define LPFC_SLI4_INTR24 BIT24
813#define LPFC_SLI4_INTR25 BIT25
814#define LPFC_SLI4_INTR26 BIT26
815#define LPFC_SLI4_INTR27 BIT27
816#define LPFC_SLI4_INTR28 BIT28
817#define LPFC_SLI4_INTR29 BIT29
818#define LPFC_SLI4_INTR30 BIT30
819#define LPFC_SLI4_INTR31 BIT31
820
821/*
822 * The Doorbell registers defined here exist in different BAR
823 * register sets depending on the UCNA Port's reported if_type
824 * value. For UCNA ports running SLI4 and if_type 0, they reside in
825 * BAR4. For UCNA ports running SLI4 and if_type 2, they reside in
826 * BAR0. For FC ports running SLI4 and if_type 6, they reside in
827 * BAR2. The offsets and base address are different, so the driver
828 * has to compute the register addresses accordingly
829 */
830#define LPFC_ULP0_RQ_DOORBELL 0x00A0
831#define LPFC_ULP1_RQ_DOORBELL 0x00C0
832#define LPFC_IF6_RQ_DOORBELL 0x0080
833#define lpfc_rq_db_list_fm_num_posted_SHIFT 24
834#define lpfc_rq_db_list_fm_num_posted_MASK 0x00FF
835#define lpfc_rq_db_list_fm_num_posted_WORD word0
836#define lpfc_rq_db_list_fm_index_SHIFT 16
837#define lpfc_rq_db_list_fm_index_MASK 0x00FF
838#define lpfc_rq_db_list_fm_index_WORD word0
839#define lpfc_rq_db_list_fm_id_SHIFT 0
840#define lpfc_rq_db_list_fm_id_MASK 0xFFFF
841#define lpfc_rq_db_list_fm_id_WORD word0
842#define lpfc_rq_db_ring_fm_num_posted_SHIFT 16
843#define lpfc_rq_db_ring_fm_num_posted_MASK 0x3FFF
844#define lpfc_rq_db_ring_fm_num_posted_WORD word0
845#define lpfc_rq_db_ring_fm_id_SHIFT 0
846#define lpfc_rq_db_ring_fm_id_MASK 0xFFFF
847#define lpfc_rq_db_ring_fm_id_WORD word0
848
849#define LPFC_ULP0_WQ_DOORBELL 0x0040
850#define LPFC_ULP1_WQ_DOORBELL 0x0060
851#define lpfc_wq_db_list_fm_num_posted_SHIFT 24
852#define lpfc_wq_db_list_fm_num_posted_MASK 0x00FF
853#define lpfc_wq_db_list_fm_num_posted_WORD word0
854#define lpfc_wq_db_list_fm_index_SHIFT 16
855#define lpfc_wq_db_list_fm_index_MASK 0x00FF
856#define lpfc_wq_db_list_fm_index_WORD word0
857#define lpfc_wq_db_list_fm_id_SHIFT 0
858#define lpfc_wq_db_list_fm_id_MASK 0xFFFF
859#define lpfc_wq_db_list_fm_id_WORD word0
860#define lpfc_wq_db_ring_fm_num_posted_SHIFT 16
861#define lpfc_wq_db_ring_fm_num_posted_MASK 0x3FFF
862#define lpfc_wq_db_ring_fm_num_posted_WORD word0
863#define lpfc_wq_db_ring_fm_id_SHIFT 0
864#define lpfc_wq_db_ring_fm_id_MASK 0xFFFF
865#define lpfc_wq_db_ring_fm_id_WORD word0
866
867#define LPFC_IF6_WQ_DOORBELL 0x0040
868#define lpfc_if6_wq_db_list_fm_num_posted_SHIFT 24
869#define lpfc_if6_wq_db_list_fm_num_posted_MASK 0x00FF
870#define lpfc_if6_wq_db_list_fm_num_posted_WORD word0
871#define lpfc_if6_wq_db_list_fm_dpp_SHIFT 23
872#define lpfc_if6_wq_db_list_fm_dpp_MASK 0x0001
873#define lpfc_if6_wq_db_list_fm_dpp_WORD word0
874#define lpfc_if6_wq_db_list_fm_dpp_id_SHIFT 16
875#define lpfc_if6_wq_db_list_fm_dpp_id_MASK 0x001F
876#define lpfc_if6_wq_db_list_fm_dpp_id_WORD word0
877#define lpfc_if6_wq_db_list_fm_id_SHIFT 0
878#define lpfc_if6_wq_db_list_fm_id_MASK 0xFFFF
879#define lpfc_if6_wq_db_list_fm_id_WORD word0
880
881#define LPFC_EQCQ_DOORBELL 0x0120
882#define lpfc_eqcq_doorbell_se_SHIFT 31
883#define lpfc_eqcq_doorbell_se_MASK 0x0001
884#define lpfc_eqcq_doorbell_se_WORD word0
885#define LPFC_EQCQ_SOLICIT_ENABLE_OFF 0
886#define LPFC_EQCQ_SOLICIT_ENABLE_ON 1
887#define lpfc_eqcq_doorbell_arm_SHIFT 29
888#define lpfc_eqcq_doorbell_arm_MASK 0x0001
889#define lpfc_eqcq_doorbell_arm_WORD word0
890#define lpfc_eqcq_doorbell_num_released_SHIFT 16
891#define lpfc_eqcq_doorbell_num_released_MASK 0x1FFF
892#define lpfc_eqcq_doorbell_num_released_WORD word0
893#define lpfc_eqcq_doorbell_qt_SHIFT 10
894#define lpfc_eqcq_doorbell_qt_MASK 0x0001
895#define lpfc_eqcq_doorbell_qt_WORD word0
896#define LPFC_QUEUE_TYPE_COMPLETION 0
897#define LPFC_QUEUE_TYPE_EVENT 1
898#define lpfc_eqcq_doorbell_eqci_SHIFT 9
899#define lpfc_eqcq_doorbell_eqci_MASK 0x0001
900#define lpfc_eqcq_doorbell_eqci_WORD word0
901#define lpfc_eqcq_doorbell_cqid_lo_SHIFT 0
902#define lpfc_eqcq_doorbell_cqid_lo_MASK 0x03FF
903#define lpfc_eqcq_doorbell_cqid_lo_WORD word0
904#define lpfc_eqcq_doorbell_cqid_hi_SHIFT 11
905#define lpfc_eqcq_doorbell_cqid_hi_MASK 0x001F
906#define lpfc_eqcq_doorbell_cqid_hi_WORD word0
907#define lpfc_eqcq_doorbell_eqid_lo_SHIFT 0
908#define lpfc_eqcq_doorbell_eqid_lo_MASK 0x01FF
909#define lpfc_eqcq_doorbell_eqid_lo_WORD word0
910#define lpfc_eqcq_doorbell_eqid_hi_SHIFT 11
911#define lpfc_eqcq_doorbell_eqid_hi_MASK 0x001F
912#define lpfc_eqcq_doorbell_eqid_hi_WORD word0
913#define LPFC_CQID_HI_FIELD_SHIFT 10
914#define LPFC_EQID_HI_FIELD_SHIFT 9
915
916#define LPFC_IF6_CQ_DOORBELL 0x00C0
917#define lpfc_if6_cq_doorbell_se_SHIFT 31
918#define lpfc_if6_cq_doorbell_se_MASK 0x0001
919#define lpfc_if6_cq_doorbell_se_WORD word0
920#define LPFC_IF6_CQ_SOLICIT_ENABLE_OFF 0
921#define LPFC_IF6_CQ_SOLICIT_ENABLE_ON 1
922#define lpfc_if6_cq_doorbell_arm_SHIFT 29
923#define lpfc_if6_cq_doorbell_arm_MASK 0x0001
924#define lpfc_if6_cq_doorbell_arm_WORD word0
925#define lpfc_if6_cq_doorbell_num_released_SHIFT 16
926#define lpfc_if6_cq_doorbell_num_released_MASK 0x1FFF
927#define lpfc_if6_cq_doorbell_num_released_WORD word0
928#define lpfc_if6_cq_doorbell_cqid_SHIFT 0
929#define lpfc_if6_cq_doorbell_cqid_MASK 0xFFFF
930#define lpfc_if6_cq_doorbell_cqid_WORD word0
931
932#define LPFC_IF6_EQ_DOORBELL 0x0120
933#define lpfc_if6_eq_doorbell_io_SHIFT 31
934#define lpfc_if6_eq_doorbell_io_MASK 0x0001
935#define lpfc_if6_eq_doorbell_io_WORD word0
936#define LPFC_IF6_EQ_INTR_OVERRIDE_OFF 0
937#define LPFC_IF6_EQ_INTR_OVERRIDE_ON 1
938#define lpfc_if6_eq_doorbell_arm_SHIFT 29
939#define lpfc_if6_eq_doorbell_arm_MASK 0x0001
940#define lpfc_if6_eq_doorbell_arm_WORD word0
941#define lpfc_if6_eq_doorbell_num_released_SHIFT 16
942#define lpfc_if6_eq_doorbell_num_released_MASK 0x1FFF
943#define lpfc_if6_eq_doorbell_num_released_WORD word0
944#define lpfc_if6_eq_doorbell_eqid_SHIFT 0
945#define lpfc_if6_eq_doorbell_eqid_MASK 0x0FFF
946#define lpfc_if6_eq_doorbell_eqid_WORD word0
947
948#define LPFC_BMBX 0x0160
949#define lpfc_bmbx_addr_SHIFT 2
950#define lpfc_bmbx_addr_MASK 0x3FFFFFFF
951#define lpfc_bmbx_addr_WORD word0
952#define lpfc_bmbx_hi_SHIFT 1
953#define lpfc_bmbx_hi_MASK 0x0001
954#define lpfc_bmbx_hi_WORD word0
955#define lpfc_bmbx_rdy_SHIFT 0
956#define lpfc_bmbx_rdy_MASK 0x0001
957#define lpfc_bmbx_rdy_WORD word0
958
959#define LPFC_MQ_DOORBELL 0x0140
960#define LPFC_IF6_MQ_DOORBELL 0x0160
961#define lpfc_mq_doorbell_num_posted_SHIFT 16
962#define lpfc_mq_doorbell_num_posted_MASK 0x3FFF
963#define lpfc_mq_doorbell_num_posted_WORD word0
964#define lpfc_mq_doorbell_id_SHIFT 0
965#define lpfc_mq_doorbell_id_MASK 0xFFFF
966#define lpfc_mq_doorbell_id_WORD word0
967
968struct lpfc_sli4_cfg_mhdr {
969 uint32_t word1;
970#define lpfc_mbox_hdr_emb_SHIFT 0
971#define lpfc_mbox_hdr_emb_MASK 0x00000001
972#define lpfc_mbox_hdr_emb_WORD word1
973#define lpfc_mbox_hdr_sge_cnt_SHIFT 3
974#define lpfc_mbox_hdr_sge_cnt_MASK 0x0000001F
975#define lpfc_mbox_hdr_sge_cnt_WORD word1
976 uint32_t payload_length;
977 uint32_t tag_lo;
978 uint32_t tag_hi;
979 uint32_t reserved5;
980};
981
982union lpfc_sli4_cfg_shdr {
983 struct {
984 uint32_t word6;
985#define lpfc_mbox_hdr_opcode_SHIFT 0
986#define lpfc_mbox_hdr_opcode_MASK 0x000000FF
987#define lpfc_mbox_hdr_opcode_WORD word6
988#define lpfc_mbox_hdr_subsystem_SHIFT 8
989#define lpfc_mbox_hdr_subsystem_MASK 0x000000FF
990#define lpfc_mbox_hdr_subsystem_WORD word6
991#define lpfc_mbox_hdr_port_number_SHIFT 16
992#define lpfc_mbox_hdr_port_number_MASK 0x000000FF
993#define lpfc_mbox_hdr_port_number_WORD word6
994#define lpfc_mbox_hdr_domain_SHIFT 24
995#define lpfc_mbox_hdr_domain_MASK 0x000000FF
996#define lpfc_mbox_hdr_domain_WORD word6
997 uint32_t timeout;
998 uint32_t request_length;
999 uint32_t word9;
1000#define lpfc_mbox_hdr_version_SHIFT 0
1001#define lpfc_mbox_hdr_version_MASK 0x000000FF
1002#define lpfc_mbox_hdr_version_WORD word9
1003#define lpfc_mbox_hdr_pf_num_SHIFT 16
1004#define lpfc_mbox_hdr_pf_num_MASK 0x000000FF
1005#define lpfc_mbox_hdr_pf_num_WORD word9
1006#define lpfc_mbox_hdr_vh_num_SHIFT 24
1007#define lpfc_mbox_hdr_vh_num_MASK 0x000000FF
1008#define lpfc_mbox_hdr_vh_num_WORD word9
1009#define LPFC_Q_CREATE_VERSION_2 2
1010#define LPFC_Q_CREATE_VERSION_1 1
1011#define LPFC_Q_CREATE_VERSION_0 0
1012#define LPFC_OPCODE_VERSION_0 0
1013#define LPFC_OPCODE_VERSION_1 1
1014 } request;
1015 struct {
1016 uint32_t word6;
1017#define lpfc_mbox_hdr_opcode_SHIFT 0
1018#define lpfc_mbox_hdr_opcode_MASK 0x000000FF
1019#define lpfc_mbox_hdr_opcode_WORD word6
1020#define lpfc_mbox_hdr_subsystem_SHIFT 8
1021#define lpfc_mbox_hdr_subsystem_MASK 0x000000FF
1022#define lpfc_mbox_hdr_subsystem_WORD word6
1023#define lpfc_mbox_hdr_domain_SHIFT 24
1024#define lpfc_mbox_hdr_domain_MASK 0x000000FF
1025#define lpfc_mbox_hdr_domain_WORD word6
1026 uint32_t word7;
1027#define lpfc_mbox_hdr_status_SHIFT 0
1028#define lpfc_mbox_hdr_status_MASK 0x000000FF
1029#define lpfc_mbox_hdr_status_WORD word7
1030#define lpfc_mbox_hdr_add_status_SHIFT 8
1031#define lpfc_mbox_hdr_add_status_MASK 0x000000FF
1032#define lpfc_mbox_hdr_add_status_WORD word7
1033#define LPFC_ADD_STATUS_INCOMPAT_OBJ 0xA2
1034#define lpfc_mbox_hdr_add_status_2_SHIFT 16
1035#define lpfc_mbox_hdr_add_status_2_MASK 0x000000FF
1036#define lpfc_mbox_hdr_add_status_2_WORD word7
1037#define LPFC_ADD_STATUS_2_INCOMPAT_FLASH 0x01
1038#define LPFC_ADD_STATUS_2_INCORRECT_ASIC 0x02
1039 uint32_t response_length;
1040 uint32_t actual_response_length;
1041 } response;
1042};
1043
1044/* Mailbox Header structures.
1045 * struct mbox_header is defined for first generation SLI4_CFG mailbox
1046 * calls deployed for BE-based ports.
1047 *
1048 * struct sli4_mbox_header is defined for second generation SLI4
1049 * ports that don't deploy the SLI4_CFG mechanism.
1050 */
1051struct mbox_header {
1052 struct lpfc_sli4_cfg_mhdr cfg_mhdr;
1053 union lpfc_sli4_cfg_shdr cfg_shdr;
1054};
1055
1056#define LPFC_EXTENT_LOCAL 0
1057#define LPFC_TIMEOUT_DEFAULT 0
1058#define LPFC_EXTENT_VERSION_DEFAULT 0
1059
1060/* Subsystem Definitions */
1061#define LPFC_MBOX_SUBSYSTEM_NA 0x0
1062#define LPFC_MBOX_SUBSYSTEM_COMMON 0x1
1063#define LPFC_MBOX_SUBSYSTEM_LOWLEVEL 0xB
1064#define LPFC_MBOX_SUBSYSTEM_FCOE 0xC
1065
1066/* Device Specific Definitions */
1067
1068/* The HOST ENDIAN defines are in Big Endian format. */
1069#define HOST_ENDIAN_LOW_WORD0 0xFF3412FF
1070#define HOST_ENDIAN_HIGH_WORD1 0xFF7856FF
1071
1072/* Common Opcodes */
1073#define LPFC_MBOX_OPCODE_NA 0x00
1074#define LPFC_MBOX_OPCODE_CQ_CREATE 0x0C
1075#define LPFC_MBOX_OPCODE_EQ_CREATE 0x0D
1076#define LPFC_MBOX_OPCODE_MQ_CREATE 0x15
1077#define LPFC_MBOX_OPCODE_GET_CNTL_ATTRIBUTES 0x20
1078#define LPFC_MBOX_OPCODE_NOP 0x21
1079#define LPFC_MBOX_OPCODE_MODIFY_EQ_DELAY 0x29
1080#define LPFC_MBOX_OPCODE_MQ_DESTROY 0x35
1081#define LPFC_MBOX_OPCODE_CQ_DESTROY 0x36
1082#define LPFC_MBOX_OPCODE_EQ_DESTROY 0x37
1083#define LPFC_MBOX_OPCODE_QUERY_FW_CFG 0x3A
1084#define LPFC_MBOX_OPCODE_FUNCTION_RESET 0x3D
1085#define LPFC_MBOX_OPCODE_SET_PHYSICAL_LINK_CONFIG 0x3E
1086#define LPFC_MBOX_OPCODE_SET_BOOT_CONFIG 0x43
1087#define LPFC_MBOX_OPCODE_SET_BEACON_CONFIG 0x45
1088#define LPFC_MBOX_OPCODE_GET_BEACON_CONFIG 0x46
1089#define LPFC_MBOX_OPCODE_GET_PORT_NAME 0x4D
1090#define LPFC_MBOX_OPCODE_MQ_CREATE_EXT 0x5A
1091#define LPFC_MBOX_OPCODE_GET_VPD_DATA 0x5B
1092#define LPFC_MBOX_OPCODE_SET_HOST_DATA 0x5D
1093#define LPFC_MBOX_OPCODE_SEND_ACTIVATION 0x73
1094#define LPFC_MBOX_OPCODE_RESET_LICENSES 0x74
1095#define LPFC_MBOX_OPCODE_REG_CONGESTION_BUF 0x8E
1096#define LPFC_MBOX_OPCODE_GET_RSRC_EXTENT_INFO 0x9A
1097#define LPFC_MBOX_OPCODE_GET_ALLOC_RSRC_EXTENT 0x9B
1098#define LPFC_MBOX_OPCODE_ALLOC_RSRC_EXTENT 0x9C
1099#define LPFC_MBOX_OPCODE_DEALLOC_RSRC_EXTENT 0x9D
1100#define LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG 0xA0
1101#define LPFC_MBOX_OPCODE_GET_PROFILE_CAPACITIES 0xA1
1102#define LPFC_MBOX_OPCODE_GET_PROFILE_CONFIG 0xA4
1103#define LPFC_MBOX_OPCODE_SET_PROFILE_CONFIG 0xA5
1104#define LPFC_MBOX_OPCODE_GET_PROFILE_LIST 0xA6
1105#define LPFC_MBOX_OPCODE_SET_ACT_PROFILE 0xA8
1106#define LPFC_MBOX_OPCODE_GET_FACTORY_PROFILE_CONFIG 0xA9
1107#define LPFC_MBOX_OPCODE_READ_OBJECT 0xAB
1108#define LPFC_MBOX_OPCODE_WRITE_OBJECT 0xAC
1109#define LPFC_MBOX_OPCODE_READ_OBJECT_LIST 0xAD
1110#define LPFC_MBOX_OPCODE_DELETE_OBJECT 0xAE
1111#define LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS 0xB5
1112#define LPFC_MBOX_OPCODE_SET_FEATURES 0xBF
1113
1114/* FCoE Opcodes */
1115#define LPFC_MBOX_OPCODE_FCOE_WQ_CREATE 0x01
1116#define LPFC_MBOX_OPCODE_FCOE_WQ_DESTROY 0x02
1117#define LPFC_MBOX_OPCODE_FCOE_POST_SGL_PAGES 0x03
1118#define LPFC_MBOX_OPCODE_FCOE_REMOVE_SGL_PAGES 0x04
1119#define LPFC_MBOX_OPCODE_FCOE_RQ_CREATE 0x05
1120#define LPFC_MBOX_OPCODE_FCOE_RQ_DESTROY 0x06
1121#define LPFC_MBOX_OPCODE_FCOE_READ_FCF_TABLE 0x08
1122#define LPFC_MBOX_OPCODE_FCOE_ADD_FCF 0x09
1123#define LPFC_MBOX_OPCODE_FCOE_DELETE_FCF 0x0A
1124#define LPFC_MBOX_OPCODE_FCOE_POST_HDR_TEMPLATE 0x0B
1125#define LPFC_MBOX_OPCODE_FCOE_REDISCOVER_FCF 0x10
1126#define LPFC_MBOX_OPCODE_FCOE_CQ_CREATE_SET 0x1D
1127#define LPFC_MBOX_OPCODE_FCOE_SET_FCLINK_SETTINGS 0x21
1128#define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_STATE 0x22
1129#define LPFC_MBOX_OPCODE_FCOE_LINK_DIAG_LOOPBACK 0x23
1130#define LPFC_MBOX_OPCODE_FCOE_FC_SET_TRUNK_MODE 0x42
1131
1132/* Low level Opcodes */
1133#define LPFC_MBOX_OPCODE_SET_DIAG_LOG_OPTION 0x37
1134
1135/* Mailbox command structures */
1136struct eq_context {
1137 uint32_t word0;
1138#define lpfc_eq_context_size_SHIFT 31
1139#define lpfc_eq_context_size_MASK 0x00000001
1140#define lpfc_eq_context_size_WORD word0
1141#define LPFC_EQE_SIZE_4 0x0
1142#define LPFC_EQE_SIZE_16 0x1
1143#define lpfc_eq_context_valid_SHIFT 29
1144#define lpfc_eq_context_valid_MASK 0x00000001
1145#define lpfc_eq_context_valid_WORD word0
1146#define lpfc_eq_context_autovalid_SHIFT 28
1147#define lpfc_eq_context_autovalid_MASK 0x00000001
1148#define lpfc_eq_context_autovalid_WORD word0
1149 uint32_t word1;
1150#define lpfc_eq_context_count_SHIFT 26
1151#define lpfc_eq_context_count_MASK 0x00000003
1152#define lpfc_eq_context_count_WORD word1
1153#define LPFC_EQ_CNT_256 0x0
1154#define LPFC_EQ_CNT_512 0x1
1155#define LPFC_EQ_CNT_1024 0x2
1156#define LPFC_EQ_CNT_2048 0x3
1157#define LPFC_EQ_CNT_4096 0x4
1158 uint32_t word2;
1159#define lpfc_eq_context_delay_multi_SHIFT 13
1160#define lpfc_eq_context_delay_multi_MASK 0x000003FF
1161#define lpfc_eq_context_delay_multi_WORD word2
1162 uint32_t reserved3;
1163};
1164
1165struct eq_delay_info {
1166 uint32_t eq_id;
1167 uint32_t phase;
1168 uint32_t delay_multi;
1169};
1170#define LPFC_MAX_EQ_DELAY_EQID_CNT 8
1171
1172struct sgl_page_pairs {
1173 uint32_t sgl_pg0_addr_lo;
1174 uint32_t sgl_pg0_addr_hi;
1175 uint32_t sgl_pg1_addr_lo;
1176 uint32_t sgl_pg1_addr_hi;
1177};
1178
1179struct lpfc_mbx_post_sgl_pages {
1180 struct mbox_header header;
1181 uint32_t word0;
1182#define lpfc_post_sgl_pages_xri_SHIFT 0
1183#define lpfc_post_sgl_pages_xri_MASK 0x0000FFFF
1184#define lpfc_post_sgl_pages_xri_WORD word0
1185#define lpfc_post_sgl_pages_xricnt_SHIFT 16
1186#define lpfc_post_sgl_pages_xricnt_MASK 0x0000FFFF
1187#define lpfc_post_sgl_pages_xricnt_WORD word0
1188 struct sgl_page_pairs sgl_pg_pairs[1];
1189};
1190
1191/* word0 of page-1 struct shares the same SHIFT/MASK/WORD defines as above */
1192struct lpfc_mbx_post_uembed_sgl_page1 {
1193 union lpfc_sli4_cfg_shdr cfg_shdr;
1194 uint32_t word0;
1195 struct sgl_page_pairs sgl_pg_pairs;
1196};
1197
1198struct lpfc_mbx_sge {
1199 uint32_t pa_lo;
1200 uint32_t pa_hi;
1201 uint32_t length;
1202};
1203
1204struct lpfc_mbx_host_buf {
1205 uint32_t length;
1206 uint32_t pa_lo;
1207 uint32_t pa_hi;
1208};
1209
1210struct lpfc_mbx_nembed_cmd {
1211 struct lpfc_sli4_cfg_mhdr cfg_mhdr;
1212#define LPFC_SLI4_MBX_SGE_MAX_PAGES 19
1213 struct lpfc_mbx_sge sge[LPFC_SLI4_MBX_SGE_MAX_PAGES];
1214};
1215
1216struct lpfc_mbx_nembed_sge_virt {
1217 void *addr[LPFC_SLI4_MBX_SGE_MAX_PAGES];
1218};
1219
1220#define LPFC_MBX_OBJECT_NAME_LEN_DW 26
1221struct lpfc_mbx_read_object { /* Version 0 */
1222 struct mbox_header header;
1223 union {
1224 struct {
1225 uint32_t word0;
1226#define lpfc_mbx_rd_object_rlen_SHIFT 0
1227#define lpfc_mbx_rd_object_rlen_MASK 0x00FFFFFF
1228#define lpfc_mbx_rd_object_rlen_WORD word0
1229 uint32_t rd_object_offset;
1230 __le32 rd_object_name[LPFC_MBX_OBJECT_NAME_LEN_DW];
1231#define LPFC_OBJ_NAME_SZ 104 /* 26 x sizeof(uint32_t) is 104. */
1232 uint32_t rd_object_cnt;
1233 struct lpfc_mbx_host_buf rd_object_hbuf[4];
1234 } request;
1235 struct {
1236 uint32_t rd_object_actual_rlen;
1237 uint32_t word1;
1238#define lpfc_mbx_rd_object_eof_SHIFT 31
1239#define lpfc_mbx_rd_object_eof_MASK 0x1
1240#define lpfc_mbx_rd_object_eof_WORD word1
1241 } response;
1242 } u;
1243};
1244
1245struct lpfc_mbx_eq_create {
1246 struct mbox_header header;
1247 union {
1248 struct {
1249 uint32_t word0;
1250#define lpfc_mbx_eq_create_num_pages_SHIFT 0
1251#define lpfc_mbx_eq_create_num_pages_MASK 0x0000FFFF
1252#define lpfc_mbx_eq_create_num_pages_WORD word0
1253 struct eq_context context;
1254 struct dma_address page[LPFC_MAX_EQ_PAGE];
1255 } request;
1256 struct {
1257 uint32_t word0;
1258#define lpfc_mbx_eq_create_q_id_SHIFT 0
1259#define lpfc_mbx_eq_create_q_id_MASK 0x0000FFFF
1260#define lpfc_mbx_eq_create_q_id_WORD word0
1261 } response;
1262 } u;
1263};
1264
1265struct lpfc_mbx_modify_eq_delay {
1266 struct mbox_header header;
1267 union {
1268 struct {
1269 uint32_t num_eq;
1270 struct eq_delay_info eq[LPFC_MAX_EQ_DELAY_EQID_CNT];
1271 } request;
1272 struct {
1273 uint32_t word0;
1274 } response;
1275 } u;
1276};
1277
1278struct lpfc_mbx_eq_destroy {
1279 struct mbox_header header;
1280 union {
1281 struct {
1282 uint32_t word0;
1283#define lpfc_mbx_eq_destroy_q_id_SHIFT 0
1284#define lpfc_mbx_eq_destroy_q_id_MASK 0x0000FFFF
1285#define lpfc_mbx_eq_destroy_q_id_WORD word0
1286 } request;
1287 struct {
1288 uint32_t word0;
1289 } response;
1290 } u;
1291};
1292
1293struct lpfc_mbx_nop {
1294 struct mbox_header header;
1295 uint32_t context[2];
1296};
1297
1298
1299
1300struct lpfc_mbx_set_ras_fwlog {
1301 struct mbox_header header;
1302 union {
1303 struct {
1304 uint32_t word4;
1305#define lpfc_fwlog_enable_SHIFT 0
1306#define lpfc_fwlog_enable_MASK 0x00000001
1307#define lpfc_fwlog_enable_WORD word4
1308#define lpfc_fwlog_loglvl_SHIFT 8
1309#define lpfc_fwlog_loglvl_MASK 0x0000000F
1310#define lpfc_fwlog_loglvl_WORD word4
1311#define lpfc_fwlog_ra_SHIFT 15
1312#define lpfc_fwlog_ra_WORD 0x00000008
1313#define lpfc_fwlog_buffcnt_SHIFT 16
1314#define lpfc_fwlog_buffcnt_MASK 0x000000FF
1315#define lpfc_fwlog_buffcnt_WORD word4
1316#define lpfc_fwlog_buffsz_SHIFT 24
1317#define lpfc_fwlog_buffsz_MASK 0x000000FF
1318#define lpfc_fwlog_buffsz_WORD word4
1319 uint32_t word5;
1320#define lpfc_fwlog_acqe_SHIFT 0
1321#define lpfc_fwlog_acqe_MASK 0x0000FFFF
1322#define lpfc_fwlog_acqe_WORD word5
1323#define lpfc_fwlog_cqid_SHIFT 16
1324#define lpfc_fwlog_cqid_MASK 0x0000FFFF
1325#define lpfc_fwlog_cqid_WORD word5
1326#define LPFC_MAX_FWLOG_PAGE 16
1327 struct dma_address lwpd;
1328 struct dma_address buff_fwlog[LPFC_MAX_FWLOG_PAGE];
1329 } request;
1330 struct {
1331 uint32_t word0;
1332 } response;
1333 } u;
1334};
1335
1336
1337struct cq_context {
1338 uint32_t word0;
1339#define lpfc_cq_context_event_SHIFT 31
1340#define lpfc_cq_context_event_MASK 0x00000001
1341#define lpfc_cq_context_event_WORD word0
1342#define lpfc_cq_context_valid_SHIFT 29
1343#define lpfc_cq_context_valid_MASK 0x00000001
1344#define lpfc_cq_context_valid_WORD word0
1345#define lpfc_cq_context_count_SHIFT 27
1346#define lpfc_cq_context_count_MASK 0x00000003
1347#define lpfc_cq_context_count_WORD word0
1348#define LPFC_CQ_CNT_256 0x0
1349#define LPFC_CQ_CNT_512 0x1
1350#define LPFC_CQ_CNT_1024 0x2
1351#define LPFC_CQ_CNT_WORD7 0x3
1352#define lpfc_cq_context_cqe_sz_SHIFT 25
1353#define lpfc_cq_context_cqe_sz_MASK 0x00000003
1354#define lpfc_cq_context_cqe_sz_WORD word0
1355#define lpfc_cq_context_autovalid_SHIFT 15
1356#define lpfc_cq_context_autovalid_MASK 0x00000001
1357#define lpfc_cq_context_autovalid_WORD word0
1358 uint32_t word1;
1359#define lpfc_cq_eq_id_SHIFT 22 /* Version 0 Only */
1360#define lpfc_cq_eq_id_MASK 0x000000FF
1361#define lpfc_cq_eq_id_WORD word1
1362#define lpfc_cq_eq_id_2_SHIFT 0 /* Version 2 Only */
1363#define lpfc_cq_eq_id_2_MASK 0x0000FFFF
1364#define lpfc_cq_eq_id_2_WORD word1
1365 uint32_t lpfc_cq_context_count; /* Version 2 Only */
1366 uint32_t reserved1;
1367};
1368
1369struct lpfc_mbx_cq_create {
1370 struct mbox_header header;
1371 union {
1372 struct {
1373 uint32_t word0;
1374#define lpfc_mbx_cq_create_page_size_SHIFT 16 /* Version 2 Only */
1375#define lpfc_mbx_cq_create_page_size_MASK 0x000000FF
1376#define lpfc_mbx_cq_create_page_size_WORD word0
1377#define lpfc_mbx_cq_create_num_pages_SHIFT 0
1378#define lpfc_mbx_cq_create_num_pages_MASK 0x0000FFFF
1379#define lpfc_mbx_cq_create_num_pages_WORD word0
1380 struct cq_context context;
1381 struct dma_address page[LPFC_MAX_CQ_PAGE];
1382 } request;
1383 struct {
1384 uint32_t word0;
1385#define lpfc_mbx_cq_create_q_id_SHIFT 0
1386#define lpfc_mbx_cq_create_q_id_MASK 0x0000FFFF
1387#define lpfc_mbx_cq_create_q_id_WORD word0
1388 } response;
1389 } u;
1390};
1391
1392struct lpfc_mbx_cq_create_set {
1393 union lpfc_sli4_cfg_shdr cfg_shdr;
1394 union {
1395 struct {
1396 uint32_t word0;
1397#define lpfc_mbx_cq_create_set_page_size_SHIFT 16 /* Version 2 Only */
1398#define lpfc_mbx_cq_create_set_page_size_MASK 0x000000FF
1399#define lpfc_mbx_cq_create_set_page_size_WORD word0
1400#define lpfc_mbx_cq_create_set_num_pages_SHIFT 0
1401#define lpfc_mbx_cq_create_set_num_pages_MASK 0x0000FFFF
1402#define lpfc_mbx_cq_create_set_num_pages_WORD word0
1403 uint32_t word1;
1404#define lpfc_mbx_cq_create_set_evt_SHIFT 31
1405#define lpfc_mbx_cq_create_set_evt_MASK 0x00000001
1406#define lpfc_mbx_cq_create_set_evt_WORD word1
1407#define lpfc_mbx_cq_create_set_valid_SHIFT 29
1408#define lpfc_mbx_cq_create_set_valid_MASK 0x00000001
1409#define lpfc_mbx_cq_create_set_valid_WORD word1
1410#define lpfc_mbx_cq_create_set_cqecnt_SHIFT 27
1411#define lpfc_mbx_cq_create_set_cqecnt_MASK 0x00000003
1412#define lpfc_mbx_cq_create_set_cqecnt_WORD word1
1413#define lpfc_mbx_cq_create_set_cqe_size_SHIFT 25
1414#define lpfc_mbx_cq_create_set_cqe_size_MASK 0x00000003
1415#define lpfc_mbx_cq_create_set_cqe_size_WORD word1
1416#define lpfc_mbx_cq_create_set_autovalid_SHIFT 15
1417#define lpfc_mbx_cq_create_set_autovalid_MASK 0x0000001
1418#define lpfc_mbx_cq_create_set_autovalid_WORD word1
1419#define lpfc_mbx_cq_create_set_nodelay_SHIFT 14
1420#define lpfc_mbx_cq_create_set_nodelay_MASK 0x00000001
1421#define lpfc_mbx_cq_create_set_nodelay_WORD word1
1422#define lpfc_mbx_cq_create_set_clswm_SHIFT 12
1423#define lpfc_mbx_cq_create_set_clswm_MASK 0x00000003
1424#define lpfc_mbx_cq_create_set_clswm_WORD word1
1425#define lpfc_mbx_cq_create_set_cqe_cnt_hi_SHIFT 0
1426#define lpfc_mbx_cq_create_set_cqe_cnt_hi_MASK 0x0000001F
1427#define lpfc_mbx_cq_create_set_cqe_cnt_hi_WORD word1
1428 uint32_t word2;
1429#define lpfc_mbx_cq_create_set_arm_SHIFT 31
1430#define lpfc_mbx_cq_create_set_arm_MASK 0x00000001
1431#define lpfc_mbx_cq_create_set_arm_WORD word2
1432#define lpfc_mbx_cq_create_set_cqe_cnt_lo_SHIFT 16
1433#define lpfc_mbx_cq_create_set_cqe_cnt_lo_MASK 0x00007FFF
1434#define lpfc_mbx_cq_create_set_cqe_cnt_lo_WORD word2
1435#define lpfc_mbx_cq_create_set_num_cq_SHIFT 0
1436#define lpfc_mbx_cq_create_set_num_cq_MASK 0x0000FFFF
1437#define lpfc_mbx_cq_create_set_num_cq_WORD word2
1438 uint32_t word3;
1439#define lpfc_mbx_cq_create_set_eq_id1_SHIFT 16
1440#define lpfc_mbx_cq_create_set_eq_id1_MASK 0x0000FFFF
1441#define lpfc_mbx_cq_create_set_eq_id1_WORD word3
1442#define lpfc_mbx_cq_create_set_eq_id0_SHIFT 0
1443#define lpfc_mbx_cq_create_set_eq_id0_MASK 0x0000FFFF
1444#define lpfc_mbx_cq_create_set_eq_id0_WORD word3
1445 uint32_t word4;
1446#define lpfc_mbx_cq_create_set_eq_id3_SHIFT 16
1447#define lpfc_mbx_cq_create_set_eq_id3_MASK 0x0000FFFF
1448#define lpfc_mbx_cq_create_set_eq_id3_WORD word4
1449#define lpfc_mbx_cq_create_set_eq_id2_SHIFT 0
1450#define lpfc_mbx_cq_create_set_eq_id2_MASK 0x0000FFFF
1451#define lpfc_mbx_cq_create_set_eq_id2_WORD word4
1452 uint32_t word5;
1453#define lpfc_mbx_cq_create_set_eq_id5_SHIFT 16
1454#define lpfc_mbx_cq_create_set_eq_id5_MASK 0x0000FFFF
1455#define lpfc_mbx_cq_create_set_eq_id5_WORD word5
1456#define lpfc_mbx_cq_create_set_eq_id4_SHIFT 0
1457#define lpfc_mbx_cq_create_set_eq_id4_MASK 0x0000FFFF
1458#define lpfc_mbx_cq_create_set_eq_id4_WORD word5
1459 uint32_t word6;
1460#define lpfc_mbx_cq_create_set_eq_id7_SHIFT 16
1461#define lpfc_mbx_cq_create_set_eq_id7_MASK 0x0000FFFF
1462#define lpfc_mbx_cq_create_set_eq_id7_WORD word6
1463#define lpfc_mbx_cq_create_set_eq_id6_SHIFT 0
1464#define lpfc_mbx_cq_create_set_eq_id6_MASK 0x0000FFFF
1465#define lpfc_mbx_cq_create_set_eq_id6_WORD word6
1466 uint32_t word7;
1467#define lpfc_mbx_cq_create_set_eq_id9_SHIFT 16
1468#define lpfc_mbx_cq_create_set_eq_id9_MASK 0x0000FFFF
1469#define lpfc_mbx_cq_create_set_eq_id9_WORD word7
1470#define lpfc_mbx_cq_create_set_eq_id8_SHIFT 0
1471#define lpfc_mbx_cq_create_set_eq_id8_MASK 0x0000FFFF
1472#define lpfc_mbx_cq_create_set_eq_id8_WORD word7
1473 uint32_t word8;
1474#define lpfc_mbx_cq_create_set_eq_id11_SHIFT 16
1475#define lpfc_mbx_cq_create_set_eq_id11_MASK 0x0000FFFF
1476#define lpfc_mbx_cq_create_set_eq_id11_WORD word8
1477#define lpfc_mbx_cq_create_set_eq_id10_SHIFT 0
1478#define lpfc_mbx_cq_create_set_eq_id10_MASK 0x0000FFFF
1479#define lpfc_mbx_cq_create_set_eq_id10_WORD word8
1480 uint32_t word9;
1481#define lpfc_mbx_cq_create_set_eq_id13_SHIFT 16
1482#define lpfc_mbx_cq_create_set_eq_id13_MASK 0x0000FFFF
1483#define lpfc_mbx_cq_create_set_eq_id13_WORD word9
1484#define lpfc_mbx_cq_create_set_eq_id12_SHIFT 0
1485#define lpfc_mbx_cq_create_set_eq_id12_MASK 0x0000FFFF
1486#define lpfc_mbx_cq_create_set_eq_id12_WORD word9
1487 uint32_t word10;
1488#define lpfc_mbx_cq_create_set_eq_id15_SHIFT 16
1489#define lpfc_mbx_cq_create_set_eq_id15_MASK 0x0000FFFF
1490#define lpfc_mbx_cq_create_set_eq_id15_WORD word10
1491#define lpfc_mbx_cq_create_set_eq_id14_SHIFT 0
1492#define lpfc_mbx_cq_create_set_eq_id14_MASK 0x0000FFFF
1493#define lpfc_mbx_cq_create_set_eq_id14_WORD word10
1494 struct dma_address page[1];
1495 } request;
1496 struct {
1497 uint32_t word0;
1498#define lpfc_mbx_cq_create_set_num_alloc_SHIFT 16
1499#define lpfc_mbx_cq_create_set_num_alloc_MASK 0x0000FFFF
1500#define lpfc_mbx_cq_create_set_num_alloc_WORD word0
1501#define lpfc_mbx_cq_create_set_base_id_SHIFT 0
1502#define lpfc_mbx_cq_create_set_base_id_MASK 0x0000FFFF
1503#define lpfc_mbx_cq_create_set_base_id_WORD word0
1504 } response;
1505 } u;
1506};
1507
1508struct lpfc_mbx_cq_destroy {
1509 struct mbox_header header;
1510 union {
1511 struct {
1512 uint32_t word0;
1513#define lpfc_mbx_cq_destroy_q_id_SHIFT 0
1514#define lpfc_mbx_cq_destroy_q_id_MASK 0x0000FFFF
1515#define lpfc_mbx_cq_destroy_q_id_WORD word0
1516 } request;
1517 struct {
1518 uint32_t word0;
1519 } response;
1520 } u;
1521};
1522
1523struct wq_context {
1524 uint32_t reserved0;
1525 uint32_t reserved1;
1526 uint32_t reserved2;
1527 uint32_t reserved3;
1528};
1529
1530struct lpfc_mbx_wq_create {
1531 struct mbox_header header;
1532 union {
1533 struct { /* Version 0 Request */
1534 uint32_t word0;
1535#define lpfc_mbx_wq_create_num_pages_SHIFT 0
1536#define lpfc_mbx_wq_create_num_pages_MASK 0x000000FF
1537#define lpfc_mbx_wq_create_num_pages_WORD word0
1538#define lpfc_mbx_wq_create_dua_SHIFT 8
1539#define lpfc_mbx_wq_create_dua_MASK 0x00000001
1540#define lpfc_mbx_wq_create_dua_WORD word0
1541#define lpfc_mbx_wq_create_cq_id_SHIFT 16
1542#define lpfc_mbx_wq_create_cq_id_MASK 0x0000FFFF
1543#define lpfc_mbx_wq_create_cq_id_WORD word0
1544 struct dma_address page[LPFC_MAX_WQ_PAGE_V0];
1545 uint32_t word9;
1546#define lpfc_mbx_wq_create_bua_SHIFT 0
1547#define lpfc_mbx_wq_create_bua_MASK 0x00000001
1548#define lpfc_mbx_wq_create_bua_WORD word9
1549#define lpfc_mbx_wq_create_ulp_num_SHIFT 8
1550#define lpfc_mbx_wq_create_ulp_num_MASK 0x000000FF
1551#define lpfc_mbx_wq_create_ulp_num_WORD word9
1552 } request;
1553 struct { /* Version 1 Request */
1554 uint32_t word0; /* Word 0 is the same as in v0 */
1555 uint32_t word1;
1556#define lpfc_mbx_wq_create_page_size_SHIFT 0
1557#define lpfc_mbx_wq_create_page_size_MASK 0x000000FF
1558#define lpfc_mbx_wq_create_page_size_WORD word1
1559#define LPFC_WQ_PAGE_SIZE_4096 0x1
1560#define lpfc_mbx_wq_create_dpp_req_SHIFT 15
1561#define lpfc_mbx_wq_create_dpp_req_MASK 0x00000001
1562#define lpfc_mbx_wq_create_dpp_req_WORD word1
1563#define lpfc_mbx_wq_create_doe_SHIFT 14
1564#define lpfc_mbx_wq_create_doe_MASK 0x00000001
1565#define lpfc_mbx_wq_create_doe_WORD word1
1566#define lpfc_mbx_wq_create_toe_SHIFT 13
1567#define lpfc_mbx_wq_create_toe_MASK 0x00000001
1568#define lpfc_mbx_wq_create_toe_WORD word1
1569#define lpfc_mbx_wq_create_wqe_size_SHIFT 8
1570#define lpfc_mbx_wq_create_wqe_size_MASK 0x0000000F
1571#define lpfc_mbx_wq_create_wqe_size_WORD word1
1572#define LPFC_WQ_WQE_SIZE_64 0x5
1573#define LPFC_WQ_WQE_SIZE_128 0x6
1574#define lpfc_mbx_wq_create_wqe_count_SHIFT 16
1575#define lpfc_mbx_wq_create_wqe_count_MASK 0x0000FFFF
1576#define lpfc_mbx_wq_create_wqe_count_WORD word1
1577 uint32_t word2;
1578 struct dma_address page[LPFC_MAX_WQ_PAGE-1];
1579 } request_1;
1580 struct {
1581 uint32_t word0;
1582#define lpfc_mbx_wq_create_q_id_SHIFT 0
1583#define lpfc_mbx_wq_create_q_id_MASK 0x0000FFFF
1584#define lpfc_mbx_wq_create_q_id_WORD word0
1585 uint32_t doorbell_offset;
1586 uint32_t word2;
1587#define lpfc_mbx_wq_create_bar_set_SHIFT 0
1588#define lpfc_mbx_wq_create_bar_set_MASK 0x0000FFFF
1589#define lpfc_mbx_wq_create_bar_set_WORD word2
1590#define WQ_PCI_BAR_0_AND_1 0x00
1591#define WQ_PCI_BAR_2_AND_3 0x01
1592#define WQ_PCI_BAR_4_AND_5 0x02
1593#define lpfc_mbx_wq_create_db_format_SHIFT 16
1594#define lpfc_mbx_wq_create_db_format_MASK 0x0000FFFF
1595#define lpfc_mbx_wq_create_db_format_WORD word2
1596 } response;
1597 struct {
1598 uint32_t word0;
1599#define lpfc_mbx_wq_create_dpp_rsp_SHIFT 31
1600#define lpfc_mbx_wq_create_dpp_rsp_MASK 0x00000001
1601#define lpfc_mbx_wq_create_dpp_rsp_WORD word0
1602#define lpfc_mbx_wq_create_v1_q_id_SHIFT 0
1603#define lpfc_mbx_wq_create_v1_q_id_MASK 0x0000FFFF
1604#define lpfc_mbx_wq_create_v1_q_id_WORD word0
1605 uint32_t word1;
1606#define lpfc_mbx_wq_create_v1_bar_set_SHIFT 0
1607#define lpfc_mbx_wq_create_v1_bar_set_MASK 0x0000000F
1608#define lpfc_mbx_wq_create_v1_bar_set_WORD word1
1609 uint32_t doorbell_offset;
1610 uint32_t word3;
1611#define lpfc_mbx_wq_create_dpp_id_SHIFT 16
1612#define lpfc_mbx_wq_create_dpp_id_MASK 0x0000001F
1613#define lpfc_mbx_wq_create_dpp_id_WORD word3
1614#define lpfc_mbx_wq_create_dpp_bar_SHIFT 0
1615#define lpfc_mbx_wq_create_dpp_bar_MASK 0x0000000F
1616#define lpfc_mbx_wq_create_dpp_bar_WORD word3
1617 uint32_t dpp_offset;
1618 } response_1;
1619 } u;
1620};
1621
1622struct lpfc_mbx_wq_destroy {
1623 struct mbox_header header;
1624 union {
1625 struct {
1626 uint32_t word0;
1627#define lpfc_mbx_wq_destroy_q_id_SHIFT 0
1628#define lpfc_mbx_wq_destroy_q_id_MASK 0x0000FFFF
1629#define lpfc_mbx_wq_destroy_q_id_WORD word0
1630 } request;
1631 struct {
1632 uint32_t word0;
1633 } response;
1634 } u;
1635};
1636
1637#define LPFC_HDR_BUF_SIZE 128
1638#define LPFC_DATA_BUF_SIZE 2048
1639#define LPFC_NVMET_DATA_BUF_SIZE 128
1640struct rq_context {
1641 uint32_t word0;
1642#define lpfc_rq_context_rqe_count_SHIFT 16 /* Version 0 Only */
1643#define lpfc_rq_context_rqe_count_MASK 0x0000000F
1644#define lpfc_rq_context_rqe_count_WORD word0
1645#define LPFC_RQ_RING_SIZE_512 9 /* 512 entries */
1646#define LPFC_RQ_RING_SIZE_1024 10 /* 1024 entries */
1647#define LPFC_RQ_RING_SIZE_2048 11 /* 2048 entries */
1648#define LPFC_RQ_RING_SIZE_4096 12 /* 4096 entries */
1649#define lpfc_rq_context_rqe_count_1_SHIFT 16 /* Version 1-2 Only */
1650#define lpfc_rq_context_rqe_count_1_MASK 0x0000FFFF
1651#define lpfc_rq_context_rqe_count_1_WORD word0
1652#define lpfc_rq_context_rqe_size_SHIFT 8 /* Version 1-2 Only */
1653#define lpfc_rq_context_rqe_size_MASK 0x0000000F
1654#define lpfc_rq_context_rqe_size_WORD word0
1655#define LPFC_RQE_SIZE_8 2
1656#define LPFC_RQE_SIZE_16 3
1657#define LPFC_RQE_SIZE_32 4
1658#define LPFC_RQE_SIZE_64 5
1659#define LPFC_RQE_SIZE_128 6
1660#define lpfc_rq_context_page_size_SHIFT 0 /* Version 1 Only */
1661#define lpfc_rq_context_page_size_MASK 0x000000FF
1662#define lpfc_rq_context_page_size_WORD word0
1663#define LPFC_RQ_PAGE_SIZE_4096 0x1
1664 uint32_t word1;
1665#define lpfc_rq_context_data_size_SHIFT 16 /* Version 2 Only */
1666#define lpfc_rq_context_data_size_MASK 0x0000FFFF
1667#define lpfc_rq_context_data_size_WORD word1
1668#define lpfc_rq_context_hdr_size_SHIFT 0 /* Version 2 Only */
1669#define lpfc_rq_context_hdr_size_MASK 0x0000FFFF
1670#define lpfc_rq_context_hdr_size_WORD word1
1671 uint32_t word2;
1672#define lpfc_rq_context_cq_id_SHIFT 16
1673#define lpfc_rq_context_cq_id_MASK 0x0000FFFF
1674#define lpfc_rq_context_cq_id_WORD word2
1675#define lpfc_rq_context_buf_size_SHIFT 0
1676#define lpfc_rq_context_buf_size_MASK 0x0000FFFF
1677#define lpfc_rq_context_buf_size_WORD word2
1678#define lpfc_rq_context_base_cq_SHIFT 0 /* Version 2 Only */
1679#define lpfc_rq_context_base_cq_MASK 0x0000FFFF
1680#define lpfc_rq_context_base_cq_WORD word2
1681 uint32_t buffer_size; /* Version 1 Only */
1682};
1683
1684struct lpfc_mbx_rq_create {
1685 struct mbox_header header;
1686 union {
1687 struct {
1688 uint32_t word0;
1689#define lpfc_mbx_rq_create_num_pages_SHIFT 0
1690#define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF
1691#define lpfc_mbx_rq_create_num_pages_WORD word0
1692#define lpfc_mbx_rq_create_dua_SHIFT 16
1693#define lpfc_mbx_rq_create_dua_MASK 0x00000001
1694#define lpfc_mbx_rq_create_dua_WORD word0
1695#define lpfc_mbx_rq_create_bqu_SHIFT 17
1696#define lpfc_mbx_rq_create_bqu_MASK 0x00000001
1697#define lpfc_mbx_rq_create_bqu_WORD word0
1698#define lpfc_mbx_rq_create_ulp_num_SHIFT 24
1699#define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF
1700#define lpfc_mbx_rq_create_ulp_num_WORD word0
1701 struct rq_context context;
1702 struct dma_address page[LPFC_MAX_RQ_PAGE];
1703 } request;
1704 struct {
1705 uint32_t word0;
1706#define lpfc_mbx_rq_create_q_cnt_v2_SHIFT 16
1707#define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF
1708#define lpfc_mbx_rq_create_q_cnt_v2_WORD word0
1709#define lpfc_mbx_rq_create_q_id_SHIFT 0
1710#define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF
1711#define lpfc_mbx_rq_create_q_id_WORD word0
1712 uint32_t doorbell_offset;
1713 uint32_t word2;
1714#define lpfc_mbx_rq_create_bar_set_SHIFT 0
1715#define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF
1716#define lpfc_mbx_rq_create_bar_set_WORD word2
1717#define lpfc_mbx_rq_create_db_format_SHIFT 16
1718#define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF
1719#define lpfc_mbx_rq_create_db_format_WORD word2
1720 } response;
1721 } u;
1722};
1723
1724struct lpfc_mbx_rq_create_v2 {
1725 union lpfc_sli4_cfg_shdr cfg_shdr;
1726 union {
1727 struct {
1728 uint32_t word0;
1729#define lpfc_mbx_rq_create_num_pages_SHIFT 0
1730#define lpfc_mbx_rq_create_num_pages_MASK 0x0000FFFF
1731#define lpfc_mbx_rq_create_num_pages_WORD word0
1732#define lpfc_mbx_rq_create_rq_cnt_SHIFT 16
1733#define lpfc_mbx_rq_create_rq_cnt_MASK 0x000000FF
1734#define lpfc_mbx_rq_create_rq_cnt_WORD word0
1735#define lpfc_mbx_rq_create_dua_SHIFT 16
1736#define lpfc_mbx_rq_create_dua_MASK 0x00000001
1737#define lpfc_mbx_rq_create_dua_WORD word0
1738#define lpfc_mbx_rq_create_bqu_SHIFT 17
1739#define lpfc_mbx_rq_create_bqu_MASK 0x00000001
1740#define lpfc_mbx_rq_create_bqu_WORD word0
1741#define lpfc_mbx_rq_create_ulp_num_SHIFT 24
1742#define lpfc_mbx_rq_create_ulp_num_MASK 0x000000FF
1743#define lpfc_mbx_rq_create_ulp_num_WORD word0
1744#define lpfc_mbx_rq_create_dim_SHIFT 29
1745#define lpfc_mbx_rq_create_dim_MASK 0x00000001
1746#define lpfc_mbx_rq_create_dim_WORD word0
1747#define lpfc_mbx_rq_create_dfd_SHIFT 30
1748#define lpfc_mbx_rq_create_dfd_MASK 0x00000001
1749#define lpfc_mbx_rq_create_dfd_WORD word0
1750#define lpfc_mbx_rq_create_dnb_SHIFT 31
1751#define lpfc_mbx_rq_create_dnb_MASK 0x00000001
1752#define lpfc_mbx_rq_create_dnb_WORD word0
1753 struct rq_context context;
1754 struct dma_address page[1];
1755 } request;
1756 struct {
1757 uint32_t word0;
1758#define lpfc_mbx_rq_create_q_cnt_v2_SHIFT 16
1759#define lpfc_mbx_rq_create_q_cnt_v2_MASK 0x0000FFFF
1760#define lpfc_mbx_rq_create_q_cnt_v2_WORD word0
1761#define lpfc_mbx_rq_create_q_id_SHIFT 0
1762#define lpfc_mbx_rq_create_q_id_MASK 0x0000FFFF
1763#define lpfc_mbx_rq_create_q_id_WORD word0
1764 uint32_t doorbell_offset;
1765 uint32_t word2;
1766#define lpfc_mbx_rq_create_bar_set_SHIFT 0
1767#define lpfc_mbx_rq_create_bar_set_MASK 0x0000FFFF
1768#define lpfc_mbx_rq_create_bar_set_WORD word2
1769#define lpfc_mbx_rq_create_db_format_SHIFT 16
1770#define lpfc_mbx_rq_create_db_format_MASK 0x0000FFFF
1771#define lpfc_mbx_rq_create_db_format_WORD word2
1772 } response;
1773 } u;
1774};
1775
1776struct lpfc_mbx_rq_destroy {
1777 struct mbox_header header;
1778 union {
1779 struct {
1780 uint32_t word0;
1781#define lpfc_mbx_rq_destroy_q_id_SHIFT 0
1782#define lpfc_mbx_rq_destroy_q_id_MASK 0x0000FFFF
1783#define lpfc_mbx_rq_destroy_q_id_WORD word0
1784 } request;
1785 struct {
1786 uint32_t word0;
1787 } response;
1788 } u;
1789};
1790
1791struct mq_context {
1792 uint32_t word0;
1793#define lpfc_mq_context_cq_id_SHIFT 22 /* Version 0 Only */
1794#define lpfc_mq_context_cq_id_MASK 0x000003FF
1795#define lpfc_mq_context_cq_id_WORD word0
1796#define lpfc_mq_context_ring_size_SHIFT 16
1797#define lpfc_mq_context_ring_size_MASK 0x0000000F
1798#define lpfc_mq_context_ring_size_WORD word0
1799#define LPFC_MQ_RING_SIZE_16 0x5
1800#define LPFC_MQ_RING_SIZE_32 0x6
1801#define LPFC_MQ_RING_SIZE_64 0x7
1802#define LPFC_MQ_RING_SIZE_128 0x8
1803 uint32_t word1;
1804#define lpfc_mq_context_valid_SHIFT 31
1805#define lpfc_mq_context_valid_MASK 0x00000001
1806#define lpfc_mq_context_valid_WORD word1
1807 uint32_t reserved2;
1808 uint32_t reserved3;
1809};
1810
1811struct lpfc_mbx_mq_create {
1812 struct mbox_header header;
1813 union {
1814 struct {
1815 uint32_t word0;
1816#define lpfc_mbx_mq_create_num_pages_SHIFT 0
1817#define lpfc_mbx_mq_create_num_pages_MASK 0x0000FFFF
1818#define lpfc_mbx_mq_create_num_pages_WORD word0
1819 struct mq_context context;
1820 struct dma_address page[LPFC_MAX_MQ_PAGE];
1821 } request;
1822 struct {
1823 uint32_t word0;
1824#define lpfc_mbx_mq_create_q_id_SHIFT 0
1825#define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF
1826#define lpfc_mbx_mq_create_q_id_WORD word0
1827 } response;
1828 } u;
1829};
1830
1831struct lpfc_mbx_mq_create_ext {
1832 struct mbox_header header;
1833 union {
1834 struct {
1835 uint32_t word0;
1836#define lpfc_mbx_mq_create_ext_num_pages_SHIFT 0
1837#define lpfc_mbx_mq_create_ext_num_pages_MASK 0x0000FFFF
1838#define lpfc_mbx_mq_create_ext_num_pages_WORD word0
1839#define lpfc_mbx_mq_create_ext_cq_id_SHIFT 16 /* Version 1 Only */
1840#define lpfc_mbx_mq_create_ext_cq_id_MASK 0x0000FFFF
1841#define lpfc_mbx_mq_create_ext_cq_id_WORD word0
1842 uint32_t async_evt_bmap;
1843#define lpfc_mbx_mq_create_ext_async_evt_link_SHIFT LPFC_TRAILER_CODE_LINK
1844#define lpfc_mbx_mq_create_ext_async_evt_link_MASK 0x00000001
1845#define lpfc_mbx_mq_create_ext_async_evt_link_WORD async_evt_bmap
1846#define LPFC_EVT_CODE_LINK_NO_LINK 0x0
1847#define LPFC_EVT_CODE_LINK_10_MBIT 0x1
1848#define LPFC_EVT_CODE_LINK_100_MBIT 0x2
1849#define LPFC_EVT_CODE_LINK_1_GBIT 0x3
1850#define LPFC_EVT_CODE_LINK_10_GBIT 0x4
1851#define lpfc_mbx_mq_create_ext_async_evt_fip_SHIFT LPFC_TRAILER_CODE_FCOE
1852#define lpfc_mbx_mq_create_ext_async_evt_fip_MASK 0x00000001
1853#define lpfc_mbx_mq_create_ext_async_evt_fip_WORD async_evt_bmap
1854#define lpfc_mbx_mq_create_ext_async_evt_group5_SHIFT LPFC_TRAILER_CODE_GRP5
1855#define lpfc_mbx_mq_create_ext_async_evt_group5_MASK 0x00000001
1856#define lpfc_mbx_mq_create_ext_async_evt_group5_WORD async_evt_bmap
1857#define lpfc_mbx_mq_create_ext_async_evt_fc_SHIFT LPFC_TRAILER_CODE_FC
1858#define lpfc_mbx_mq_create_ext_async_evt_fc_MASK 0x00000001
1859#define lpfc_mbx_mq_create_ext_async_evt_fc_WORD async_evt_bmap
1860#define LPFC_EVT_CODE_FC_NO_LINK 0x0
1861#define LPFC_EVT_CODE_FC_1_GBAUD 0x1
1862#define LPFC_EVT_CODE_FC_2_GBAUD 0x2
1863#define LPFC_EVT_CODE_FC_4_GBAUD 0x4
1864#define LPFC_EVT_CODE_FC_8_GBAUD 0x8
1865#define LPFC_EVT_CODE_FC_10_GBAUD 0xA
1866#define LPFC_EVT_CODE_FC_16_GBAUD 0x10
1867#define lpfc_mbx_mq_create_ext_async_evt_sli_SHIFT LPFC_TRAILER_CODE_SLI
1868#define lpfc_mbx_mq_create_ext_async_evt_sli_MASK 0x00000001
1869#define lpfc_mbx_mq_create_ext_async_evt_sli_WORD async_evt_bmap
1870 struct mq_context context;
1871 struct dma_address page[LPFC_MAX_MQ_PAGE];
1872 } request;
1873 struct {
1874 uint32_t word0;
1875#define lpfc_mbx_mq_create_q_id_SHIFT 0
1876#define lpfc_mbx_mq_create_q_id_MASK 0x0000FFFF
1877#define lpfc_mbx_mq_create_q_id_WORD word0
1878 } response;
1879 } u;
1880#define LPFC_ASYNC_EVENT_LINK_STATE 0x2
1881#define LPFC_ASYNC_EVENT_FCF_STATE 0x4
1882#define LPFC_ASYNC_EVENT_GROUP5 0x20
1883};
1884
1885struct lpfc_mbx_mq_destroy {
1886 struct mbox_header header;
1887 union {
1888 struct {
1889 uint32_t word0;
1890#define lpfc_mbx_mq_destroy_q_id_SHIFT 0
1891#define lpfc_mbx_mq_destroy_q_id_MASK 0x0000FFFF
1892#define lpfc_mbx_mq_destroy_q_id_WORD word0
1893 } request;
1894 struct {
1895 uint32_t word0;
1896 } response;
1897 } u;
1898};
1899
1900/* Start Gen 2 SLI4 Mailbox definitions: */
1901
1902/* Define allocate-ready Gen 2 SLI4 FCoE Resource Extent Types. */
1903#define LPFC_RSC_TYPE_FCOE_VFI 0x20
1904#define LPFC_RSC_TYPE_FCOE_VPI 0x21
1905#define LPFC_RSC_TYPE_FCOE_RPI 0x22
1906#define LPFC_RSC_TYPE_FCOE_XRI 0x23
1907
1908struct lpfc_mbx_get_rsrc_extent_info {
1909 struct mbox_header header;
1910 union {
1911 struct {
1912 uint32_t word4;
1913#define lpfc_mbx_get_rsrc_extent_info_type_SHIFT 0
1914#define lpfc_mbx_get_rsrc_extent_info_type_MASK 0x0000FFFF
1915#define lpfc_mbx_get_rsrc_extent_info_type_WORD word4
1916 } req;
1917 struct {
1918 uint32_t word4;
1919#define lpfc_mbx_get_rsrc_extent_info_cnt_SHIFT 0
1920#define lpfc_mbx_get_rsrc_extent_info_cnt_MASK 0x0000FFFF
1921#define lpfc_mbx_get_rsrc_extent_info_cnt_WORD word4
1922#define lpfc_mbx_get_rsrc_extent_info_size_SHIFT 16
1923#define lpfc_mbx_get_rsrc_extent_info_size_MASK 0x0000FFFF
1924#define lpfc_mbx_get_rsrc_extent_info_size_WORD word4
1925 } rsp;
1926 } u;
1927};
1928
1929struct lpfc_mbx_query_fw_config {
1930 struct mbox_header header;
1931 struct {
1932 uint32_t config_number;
1933#define LPFC_FC_FCOE 0x00000007
1934 uint32_t asic_revision;
1935 uint32_t physical_port;
1936 uint32_t function_mode;
1937#define LPFC_FC_INI_MODE 0x00000040
1938#define LPFC_FC_TGT_MODE 0x00000080
1939#define LPFC_DUA_MODE 0x00000800
1940 uint32_t oper_mode;
1941 uint32_t rsvd9[2];
1942 uint32_t wqid_base;
1943 uint32_t wqid_tot;
1944 uint32_t rqid_base;
1945 uint32_t rqid_tot;
1946 uint32_t rsvd15[19];
1947 uint32_t function_capabilities;
1948 uint32_t cqid_base;
1949 uint32_t cqid_tot;
1950 uint32_t eqid_base;
1951 uint32_t eqid_tot;
1952 uint32_t rsvd39[4];
1953 } rsp;
1954};
1955
1956struct lpfc_mbx_set_beacon_config {
1957 struct mbox_header header;
1958 uint32_t word4;
1959#define lpfc_mbx_set_beacon_port_num_SHIFT 0
1960#define lpfc_mbx_set_beacon_port_num_MASK 0x0000003F
1961#define lpfc_mbx_set_beacon_port_num_WORD word4
1962#define lpfc_mbx_set_beacon_port_type_SHIFT 6
1963#define lpfc_mbx_set_beacon_port_type_MASK 0x00000003
1964#define lpfc_mbx_set_beacon_port_type_WORD word4
1965#define lpfc_mbx_set_beacon_state_SHIFT 8
1966#define lpfc_mbx_set_beacon_state_MASK 0x000000FF
1967#define lpfc_mbx_set_beacon_state_WORD word4
1968#define lpfc_mbx_set_beacon_duration_SHIFT 16
1969#define lpfc_mbx_set_beacon_duration_MASK 0x000000FF
1970#define lpfc_mbx_set_beacon_duration_WORD word4
1971
1972/* COMMON_SET_BEACON_CONFIG_V1 */
1973#define lpfc_mbx_set_beacon_duration_v1_SHIFT 16
1974#define lpfc_mbx_set_beacon_duration_v1_MASK 0x0000FFFF
1975#define lpfc_mbx_set_beacon_duration_v1_WORD word4
1976 uint32_t word5; /* RESERVED */
1977};
1978
1979struct lpfc_id_range {
1980 uint32_t word5;
1981#define lpfc_mbx_rsrc_id_word4_0_SHIFT 0
1982#define lpfc_mbx_rsrc_id_word4_0_MASK 0x0000FFFF
1983#define lpfc_mbx_rsrc_id_word4_0_WORD word5
1984#define lpfc_mbx_rsrc_id_word4_1_SHIFT 16
1985#define lpfc_mbx_rsrc_id_word4_1_MASK 0x0000FFFF
1986#define lpfc_mbx_rsrc_id_word4_1_WORD word5
1987};
1988
1989struct lpfc_mbx_set_link_diag_state {
1990 struct mbox_header header;
1991 union {
1992 struct {
1993 uint32_t word0;
1994#define lpfc_mbx_set_diag_state_diag_SHIFT 0
1995#define lpfc_mbx_set_diag_state_diag_MASK 0x00000001
1996#define lpfc_mbx_set_diag_state_diag_WORD word0
1997#define lpfc_mbx_set_diag_state_diag_bit_valid_SHIFT 2
1998#define lpfc_mbx_set_diag_state_diag_bit_valid_MASK 0x00000001
1999#define lpfc_mbx_set_diag_state_diag_bit_valid_WORD word0
2000#define LPFC_DIAG_STATE_DIAG_BIT_VALID_NO_CHANGE 0
2001#define LPFC_DIAG_STATE_DIAG_BIT_VALID_CHANGE 1
2002#define lpfc_mbx_set_diag_state_link_num_SHIFT 16
2003#define lpfc_mbx_set_diag_state_link_num_MASK 0x0000003F
2004#define lpfc_mbx_set_diag_state_link_num_WORD word0
2005#define lpfc_mbx_set_diag_state_link_type_SHIFT 22
2006#define lpfc_mbx_set_diag_state_link_type_MASK 0x00000003
2007#define lpfc_mbx_set_diag_state_link_type_WORD word0
2008 } req;
2009 struct {
2010 uint32_t word0;
2011 } rsp;
2012 } u;
2013};
2014
2015struct lpfc_mbx_set_link_diag_loopback {
2016 struct mbox_header header;
2017 union {
2018 struct {
2019 uint32_t word0;
2020#define lpfc_mbx_set_diag_lpbk_type_SHIFT 0
2021#define lpfc_mbx_set_diag_lpbk_type_MASK 0x00000003
2022#define lpfc_mbx_set_diag_lpbk_type_WORD word0
2023#define LPFC_DIAG_LOOPBACK_TYPE_DISABLE 0x0
2024#define LPFC_DIAG_LOOPBACK_TYPE_INTERNAL 0x1
2025#define LPFC_DIAG_LOOPBACK_TYPE_SERDES 0x2
2026#define LPFC_DIAG_LOOPBACK_TYPE_EXTERNAL_TRUNKED 0x3
2027#define lpfc_mbx_set_diag_lpbk_link_num_SHIFT 16
2028#define lpfc_mbx_set_diag_lpbk_link_num_MASK 0x0000003F
2029#define lpfc_mbx_set_diag_lpbk_link_num_WORD word0
2030#define lpfc_mbx_set_diag_lpbk_link_type_SHIFT 22
2031#define lpfc_mbx_set_diag_lpbk_link_type_MASK 0x00000003
2032#define lpfc_mbx_set_diag_lpbk_link_type_WORD word0
2033 } req;
2034 struct {
2035 uint32_t word0;
2036 } rsp;
2037 } u;
2038};
2039
2040struct lpfc_mbx_run_link_diag_test {
2041 struct mbox_header header;
2042 union {
2043 struct {
2044 uint32_t word0;
2045#define lpfc_mbx_run_diag_test_link_num_SHIFT 16
2046#define lpfc_mbx_run_diag_test_link_num_MASK 0x0000003F
2047#define lpfc_mbx_run_diag_test_link_num_WORD word0
2048#define lpfc_mbx_run_diag_test_link_type_SHIFT 22
2049#define lpfc_mbx_run_diag_test_link_type_MASK 0x00000003
2050#define lpfc_mbx_run_diag_test_link_type_WORD word0
2051 uint32_t word1;
2052#define lpfc_mbx_run_diag_test_test_id_SHIFT 0
2053#define lpfc_mbx_run_diag_test_test_id_MASK 0x0000FFFF
2054#define lpfc_mbx_run_diag_test_test_id_WORD word1
2055#define lpfc_mbx_run_diag_test_loops_SHIFT 16
2056#define lpfc_mbx_run_diag_test_loops_MASK 0x0000FFFF
2057#define lpfc_mbx_run_diag_test_loops_WORD word1
2058 uint32_t word2;
2059#define lpfc_mbx_run_diag_test_test_ver_SHIFT 0
2060#define lpfc_mbx_run_diag_test_test_ver_MASK 0x0000FFFF
2061#define lpfc_mbx_run_diag_test_test_ver_WORD word2
2062#define lpfc_mbx_run_diag_test_err_act_SHIFT 16
2063#define lpfc_mbx_run_diag_test_err_act_MASK 0x000000FF
2064#define lpfc_mbx_run_diag_test_err_act_WORD word2
2065 } req;
2066 struct {
2067 uint32_t word0;
2068 } rsp;
2069 } u;
2070};
2071
2072/*
2073 * struct lpfc_mbx_alloc_rsrc_extents:
2074 * A mbox is generically 256 bytes long. An SLI4_CONFIG mailbox requires
2075 * 6 words of header + 4 words of shared subcommand header +
2076 * 1 words of Extent-Opcode-specific header = 11 words or 44 bytes total.
2077 *
2078 * An embedded version of SLI4_CONFIG therefore has 256 - 44 = 212 bytes
2079 * for extents payload.
2080 *
2081 * 212/2 (bytes per extent) = 106 extents.
2082 * 106/2 (extents per word) = 53 words.
2083 * lpfc_id_range id is statically size to 53.
2084 *
2085 * This mailbox definition is used for ALLOC or GET_ALLOCATED
2086 * extent ranges. For ALLOC, the type and cnt are required.
2087 * For GET_ALLOCATED, only the type is required.
2088 */
2089struct lpfc_mbx_alloc_rsrc_extents {
2090 struct mbox_header header;
2091 union {
2092 struct {
2093 uint32_t word4;
2094#define lpfc_mbx_alloc_rsrc_extents_type_SHIFT 0
2095#define lpfc_mbx_alloc_rsrc_extents_type_MASK 0x0000FFFF
2096#define lpfc_mbx_alloc_rsrc_extents_type_WORD word4
2097#define lpfc_mbx_alloc_rsrc_extents_cnt_SHIFT 16
2098#define lpfc_mbx_alloc_rsrc_extents_cnt_MASK 0x0000FFFF
2099#define lpfc_mbx_alloc_rsrc_extents_cnt_WORD word4
2100 } req;
2101 struct {
2102 uint32_t word4;
2103#define lpfc_mbx_rsrc_cnt_SHIFT 0
2104#define lpfc_mbx_rsrc_cnt_MASK 0x0000FFFF
2105#define lpfc_mbx_rsrc_cnt_WORD word4
2106 struct lpfc_id_range id[53];
2107 } rsp;
2108 } u;
2109};
2110
2111/*
2112 * This is the non-embedded version of ALLOC or GET RSRC_EXTENTS. Word4 in this
2113 * structure shares the same SHIFT/MASK/WORD defines provided in the
2114 * mbx_alloc_rsrc_extents and mbx_get_alloc_rsrc_extents, word4, provided in
2115 * the structures defined above. This non-embedded structure provides for the
2116 * maximum number of extents supported by the port.
2117 */
2118struct lpfc_mbx_nembed_rsrc_extent {
2119 union lpfc_sli4_cfg_shdr cfg_shdr;
2120 uint32_t word4;
2121 struct lpfc_id_range id;
2122};
2123
2124struct lpfc_mbx_dealloc_rsrc_extents {
2125 struct mbox_header header;
2126 struct {
2127 uint32_t word4;
2128#define lpfc_mbx_dealloc_rsrc_extents_type_SHIFT 0
2129#define lpfc_mbx_dealloc_rsrc_extents_type_MASK 0x0000FFFF
2130#define lpfc_mbx_dealloc_rsrc_extents_type_WORD word4
2131 } req;
2132
2133};
2134
2135/* Start SLI4 FCoE specific mbox structures. */
2136
2137struct lpfc_mbx_post_hdr_tmpl {
2138 struct mbox_header header;
2139 uint32_t word10;
2140#define lpfc_mbx_post_hdr_tmpl_rpi_offset_SHIFT 0
2141#define lpfc_mbx_post_hdr_tmpl_rpi_offset_MASK 0x0000FFFF
2142#define lpfc_mbx_post_hdr_tmpl_rpi_offset_WORD word10
2143#define lpfc_mbx_post_hdr_tmpl_page_cnt_SHIFT 16
2144#define lpfc_mbx_post_hdr_tmpl_page_cnt_MASK 0x0000FFFF
2145#define lpfc_mbx_post_hdr_tmpl_page_cnt_WORD word10
2146 uint32_t rpi_paddr_lo;
2147 uint32_t rpi_paddr_hi;
2148};
2149
2150struct sli4_sge { /* SLI-4 */
2151 uint32_t addr_hi;
2152 uint32_t addr_lo;
2153
2154 uint32_t word2;
2155#define lpfc_sli4_sge_offset_SHIFT 0
2156#define lpfc_sli4_sge_offset_MASK 0x07FFFFFF
2157#define lpfc_sli4_sge_offset_WORD word2
2158#define lpfc_sli4_sge_type_SHIFT 27
2159#define lpfc_sli4_sge_type_MASK 0x0000000F
2160#define lpfc_sli4_sge_type_WORD word2
2161#define LPFC_SGE_TYPE_DATA 0x0
2162#define LPFC_SGE_TYPE_DIF 0x4
2163#define LPFC_SGE_TYPE_LSP 0x5
2164#define LPFC_SGE_TYPE_PEDIF 0x6
2165#define LPFC_SGE_TYPE_PESEED 0x7
2166#define LPFC_SGE_TYPE_DISEED 0x8
2167#define LPFC_SGE_TYPE_ENC 0x9
2168#define LPFC_SGE_TYPE_ATM 0xA
2169#define LPFC_SGE_TYPE_SKIP 0xC
2170#define lpfc_sli4_sge_last_SHIFT 31 /* Last SEG in the SGL sets it */
2171#define lpfc_sli4_sge_last_MASK 0x00000001
2172#define lpfc_sli4_sge_last_WORD word2
2173 uint32_t sge_len;
2174};
2175
2176struct sli4_sge_le {
2177 __le32 addr_hi;
2178 __le32 addr_lo;
2179
2180 __le32 word2;
2181 __le32 sge_len;
2182};
2183
2184struct sli4_hybrid_sgl {
2185 struct list_head list_node;
2186 struct sli4_sge *dma_sgl;
2187 dma_addr_t dma_phys_sgl;
2188};
2189
2190struct fcp_cmd_rsp_buf {
2191 struct list_head list_node;
2192
2193 /* for storing cmd/rsp dma alloc'ed virt_addr */
2194 struct fcp_cmnd *fcp_cmnd;
2195 struct fcp_rsp *fcp_rsp;
2196
2197 /* for storing this cmd/rsp's dma mapped phys addr from per CPU pool */
2198 dma_addr_t fcp_cmd_rsp_dma_handle;
2199};
2200
2201struct sli4_sge_diseed { /* SLI-4 */
2202 uint32_t ref_tag;
2203 uint32_t ref_tag_tran;
2204
2205 uint32_t word2;
2206#define lpfc_sli4_sge_dif_apptran_SHIFT 0
2207#define lpfc_sli4_sge_dif_apptran_MASK 0x0000FFFF
2208#define lpfc_sli4_sge_dif_apptran_WORD word2
2209#define lpfc_sli4_sge_dif_af_SHIFT 24
2210#define lpfc_sli4_sge_dif_af_MASK 0x00000001
2211#define lpfc_sli4_sge_dif_af_WORD word2
2212#define lpfc_sli4_sge_dif_na_SHIFT 25
2213#define lpfc_sli4_sge_dif_na_MASK 0x00000001
2214#define lpfc_sli4_sge_dif_na_WORD word2
2215#define lpfc_sli4_sge_dif_hi_SHIFT 26
2216#define lpfc_sli4_sge_dif_hi_MASK 0x00000001
2217#define lpfc_sli4_sge_dif_hi_WORD word2
2218#define lpfc_sli4_sge_dif_type_SHIFT 27
2219#define lpfc_sli4_sge_dif_type_MASK 0x0000000F
2220#define lpfc_sli4_sge_dif_type_WORD word2
2221#define lpfc_sli4_sge_dif_last_SHIFT 31 /* Last SEG in the SGL sets it */
2222#define lpfc_sli4_sge_dif_last_MASK 0x00000001
2223#define lpfc_sli4_sge_dif_last_WORD word2
2224 uint32_t word3;
2225#define lpfc_sli4_sge_dif_apptag_SHIFT 0
2226#define lpfc_sli4_sge_dif_apptag_MASK 0x0000FFFF
2227#define lpfc_sli4_sge_dif_apptag_WORD word3
2228#define lpfc_sli4_sge_dif_bs_SHIFT 16
2229#define lpfc_sli4_sge_dif_bs_MASK 0x00000007
2230#define lpfc_sli4_sge_dif_bs_WORD word3
2231#define lpfc_sli4_sge_dif_ai_SHIFT 19
2232#define lpfc_sli4_sge_dif_ai_MASK 0x00000001
2233#define lpfc_sli4_sge_dif_ai_WORD word3
2234#define lpfc_sli4_sge_dif_me_SHIFT 20
2235#define lpfc_sli4_sge_dif_me_MASK 0x00000001
2236#define lpfc_sli4_sge_dif_me_WORD word3
2237#define lpfc_sli4_sge_dif_re_SHIFT 21
2238#define lpfc_sli4_sge_dif_re_MASK 0x00000001
2239#define lpfc_sli4_sge_dif_re_WORD word3
2240#define lpfc_sli4_sge_dif_ce_SHIFT 22
2241#define lpfc_sli4_sge_dif_ce_MASK 0x00000001
2242#define lpfc_sli4_sge_dif_ce_WORD word3
2243#define lpfc_sli4_sge_dif_nr_SHIFT 23
2244#define lpfc_sli4_sge_dif_nr_MASK 0x00000001
2245#define lpfc_sli4_sge_dif_nr_WORD word3
2246#define lpfc_sli4_sge_dif_oprx_SHIFT 24
2247#define lpfc_sli4_sge_dif_oprx_MASK 0x0000000F
2248#define lpfc_sli4_sge_dif_oprx_WORD word3
2249#define lpfc_sli4_sge_dif_optx_SHIFT 28
2250#define lpfc_sli4_sge_dif_optx_MASK 0x0000000F
2251#define lpfc_sli4_sge_dif_optx_WORD word3
2252/* optx and oprx use BG_OP_IN defines in lpfc_hw.h */
2253};
2254
2255struct fcf_record {
2256 uint32_t max_rcv_size;
2257 uint32_t fka_adv_period;
2258 uint32_t fip_priority;
2259 uint32_t word3;
2260#define lpfc_fcf_record_mac_0_SHIFT 0
2261#define lpfc_fcf_record_mac_0_MASK 0x000000FF
2262#define lpfc_fcf_record_mac_0_WORD word3
2263#define lpfc_fcf_record_mac_1_SHIFT 8
2264#define lpfc_fcf_record_mac_1_MASK 0x000000FF
2265#define lpfc_fcf_record_mac_1_WORD word3
2266#define lpfc_fcf_record_mac_2_SHIFT 16
2267#define lpfc_fcf_record_mac_2_MASK 0x000000FF
2268#define lpfc_fcf_record_mac_2_WORD word3
2269#define lpfc_fcf_record_mac_3_SHIFT 24
2270#define lpfc_fcf_record_mac_3_MASK 0x000000FF
2271#define lpfc_fcf_record_mac_3_WORD word3
2272 uint32_t word4;
2273#define lpfc_fcf_record_mac_4_SHIFT 0
2274#define lpfc_fcf_record_mac_4_MASK 0x000000FF
2275#define lpfc_fcf_record_mac_4_WORD word4
2276#define lpfc_fcf_record_mac_5_SHIFT 8
2277#define lpfc_fcf_record_mac_5_MASK 0x000000FF
2278#define lpfc_fcf_record_mac_5_WORD word4
2279#define lpfc_fcf_record_fcf_avail_SHIFT 16
2280#define lpfc_fcf_record_fcf_avail_MASK 0x000000FF
2281#define lpfc_fcf_record_fcf_avail_WORD word4
2282#define lpfc_fcf_record_mac_addr_prov_SHIFT 24
2283#define lpfc_fcf_record_mac_addr_prov_MASK 0x000000FF
2284#define lpfc_fcf_record_mac_addr_prov_WORD word4
2285#define LPFC_FCF_FPMA 1 /* Fabric Provided MAC Address */
2286#define LPFC_FCF_SPMA 2 /* Server Provided MAC Address */
2287 uint32_t word5;
2288#define lpfc_fcf_record_fab_name_0_SHIFT 0
2289#define lpfc_fcf_record_fab_name_0_MASK 0x000000FF
2290#define lpfc_fcf_record_fab_name_0_WORD word5
2291#define lpfc_fcf_record_fab_name_1_SHIFT 8
2292#define lpfc_fcf_record_fab_name_1_MASK 0x000000FF
2293#define lpfc_fcf_record_fab_name_1_WORD word5
2294#define lpfc_fcf_record_fab_name_2_SHIFT 16
2295#define lpfc_fcf_record_fab_name_2_MASK 0x000000FF
2296#define lpfc_fcf_record_fab_name_2_WORD word5
2297#define lpfc_fcf_record_fab_name_3_SHIFT 24
2298#define lpfc_fcf_record_fab_name_3_MASK 0x000000FF
2299#define lpfc_fcf_record_fab_name_3_WORD word5
2300 uint32_t word6;
2301#define lpfc_fcf_record_fab_name_4_SHIFT 0
2302#define lpfc_fcf_record_fab_name_4_MASK 0x000000FF
2303#define lpfc_fcf_record_fab_name_4_WORD word6
2304#define lpfc_fcf_record_fab_name_5_SHIFT 8
2305#define lpfc_fcf_record_fab_name_5_MASK 0x000000FF
2306#define lpfc_fcf_record_fab_name_5_WORD word6
2307#define lpfc_fcf_record_fab_name_6_SHIFT 16
2308#define lpfc_fcf_record_fab_name_6_MASK 0x000000FF
2309#define lpfc_fcf_record_fab_name_6_WORD word6
2310#define lpfc_fcf_record_fab_name_7_SHIFT 24
2311#define lpfc_fcf_record_fab_name_7_MASK 0x000000FF
2312#define lpfc_fcf_record_fab_name_7_WORD word6
2313 uint32_t word7;
2314#define lpfc_fcf_record_fc_map_0_SHIFT 0
2315#define lpfc_fcf_record_fc_map_0_MASK 0x000000FF
2316#define lpfc_fcf_record_fc_map_0_WORD word7
2317#define lpfc_fcf_record_fc_map_1_SHIFT 8
2318#define lpfc_fcf_record_fc_map_1_MASK 0x000000FF
2319#define lpfc_fcf_record_fc_map_1_WORD word7
2320#define lpfc_fcf_record_fc_map_2_SHIFT 16
2321#define lpfc_fcf_record_fc_map_2_MASK 0x000000FF
2322#define lpfc_fcf_record_fc_map_2_WORD word7
2323#define lpfc_fcf_record_fcf_valid_SHIFT 24
2324#define lpfc_fcf_record_fcf_valid_MASK 0x00000001
2325#define lpfc_fcf_record_fcf_valid_WORD word7
2326#define lpfc_fcf_record_fcf_fc_SHIFT 25
2327#define lpfc_fcf_record_fcf_fc_MASK 0x00000001
2328#define lpfc_fcf_record_fcf_fc_WORD word7
2329#define lpfc_fcf_record_fcf_sol_SHIFT 31
2330#define lpfc_fcf_record_fcf_sol_MASK 0x00000001
2331#define lpfc_fcf_record_fcf_sol_WORD word7
2332 uint32_t word8;
2333#define lpfc_fcf_record_fcf_index_SHIFT 0
2334#define lpfc_fcf_record_fcf_index_MASK 0x0000FFFF
2335#define lpfc_fcf_record_fcf_index_WORD word8
2336#define lpfc_fcf_record_fcf_state_SHIFT 16
2337#define lpfc_fcf_record_fcf_state_MASK 0x0000FFFF
2338#define lpfc_fcf_record_fcf_state_WORD word8
2339 uint8_t vlan_bitmap[512];
2340 uint32_t word137;
2341#define lpfc_fcf_record_switch_name_0_SHIFT 0
2342#define lpfc_fcf_record_switch_name_0_MASK 0x000000FF
2343#define lpfc_fcf_record_switch_name_0_WORD word137
2344#define lpfc_fcf_record_switch_name_1_SHIFT 8
2345#define lpfc_fcf_record_switch_name_1_MASK 0x000000FF
2346#define lpfc_fcf_record_switch_name_1_WORD word137
2347#define lpfc_fcf_record_switch_name_2_SHIFT 16
2348#define lpfc_fcf_record_switch_name_2_MASK 0x000000FF
2349#define lpfc_fcf_record_switch_name_2_WORD word137
2350#define lpfc_fcf_record_switch_name_3_SHIFT 24
2351#define lpfc_fcf_record_switch_name_3_MASK 0x000000FF
2352#define lpfc_fcf_record_switch_name_3_WORD word137
2353 uint32_t word138;
2354#define lpfc_fcf_record_switch_name_4_SHIFT 0
2355#define lpfc_fcf_record_switch_name_4_MASK 0x000000FF
2356#define lpfc_fcf_record_switch_name_4_WORD word138
2357#define lpfc_fcf_record_switch_name_5_SHIFT 8
2358#define lpfc_fcf_record_switch_name_5_MASK 0x000000FF
2359#define lpfc_fcf_record_switch_name_5_WORD word138
2360#define lpfc_fcf_record_switch_name_6_SHIFT 16
2361#define lpfc_fcf_record_switch_name_6_MASK 0x000000FF
2362#define lpfc_fcf_record_switch_name_6_WORD word138
2363#define lpfc_fcf_record_switch_name_7_SHIFT 24
2364#define lpfc_fcf_record_switch_name_7_MASK 0x000000FF
2365#define lpfc_fcf_record_switch_name_7_WORD word138
2366};
2367
2368struct lpfc_mbx_read_fcf_tbl {
2369 union lpfc_sli4_cfg_shdr cfg_shdr;
2370 union {
2371 struct {
2372 uint32_t word10;
2373#define lpfc_mbx_read_fcf_tbl_indx_SHIFT 0
2374#define lpfc_mbx_read_fcf_tbl_indx_MASK 0x0000FFFF
2375#define lpfc_mbx_read_fcf_tbl_indx_WORD word10
2376 } request;
2377 struct {
2378 uint32_t eventag;
2379 } response;
2380 } u;
2381 uint32_t word11;
2382#define lpfc_mbx_read_fcf_tbl_nxt_vindx_SHIFT 0
2383#define lpfc_mbx_read_fcf_tbl_nxt_vindx_MASK 0x0000FFFF
2384#define lpfc_mbx_read_fcf_tbl_nxt_vindx_WORD word11
2385};
2386
2387struct lpfc_mbx_add_fcf_tbl_entry {
2388 union lpfc_sli4_cfg_shdr cfg_shdr;
2389 uint32_t word10;
2390#define lpfc_mbx_add_fcf_tbl_fcfi_SHIFT 0
2391#define lpfc_mbx_add_fcf_tbl_fcfi_MASK 0x0000FFFF
2392#define lpfc_mbx_add_fcf_tbl_fcfi_WORD word10
2393 struct lpfc_mbx_sge fcf_sge;
2394};
2395
2396struct lpfc_mbx_del_fcf_tbl_entry {
2397 struct mbox_header header;
2398 uint32_t word10;
2399#define lpfc_mbx_del_fcf_tbl_count_SHIFT 0
2400#define lpfc_mbx_del_fcf_tbl_count_MASK 0x0000FFFF
2401#define lpfc_mbx_del_fcf_tbl_count_WORD word10
2402#define lpfc_mbx_del_fcf_tbl_index_SHIFT 16
2403#define lpfc_mbx_del_fcf_tbl_index_MASK 0x0000FFFF
2404#define lpfc_mbx_del_fcf_tbl_index_WORD word10
2405};
2406
2407struct lpfc_mbx_redisc_fcf_tbl {
2408 struct mbox_header header;
2409 uint32_t word10;
2410#define lpfc_mbx_redisc_fcf_count_SHIFT 0
2411#define lpfc_mbx_redisc_fcf_count_MASK 0x0000FFFF
2412#define lpfc_mbx_redisc_fcf_count_WORD word10
2413 uint32_t resvd;
2414 uint32_t word12;
2415#define lpfc_mbx_redisc_fcf_index_SHIFT 0
2416#define lpfc_mbx_redisc_fcf_index_MASK 0x0000FFFF
2417#define lpfc_mbx_redisc_fcf_index_WORD word12
2418};
2419
2420/* Status field for embedded SLI_CONFIG mailbox command */
2421#define STATUS_SUCCESS 0x0
2422#define STATUS_FAILED 0x1
2423#define STATUS_ILLEGAL_REQUEST 0x2
2424#define STATUS_ILLEGAL_FIELD 0x3
2425#define STATUS_INSUFFICIENT_BUFFER 0x4
2426#define STATUS_UNAUTHORIZED_REQUEST 0x5
2427#define STATUS_FLASHROM_SAVE_FAILED 0x17
2428#define STATUS_FLASHROM_RESTORE_FAILED 0x18
2429#define STATUS_ICCBINDEX_ALLOC_FAILED 0x1a
2430#define STATUS_IOCTLHANDLE_ALLOC_FAILED 0x1b
2431#define STATUS_INVALID_PHY_ADDR_FROM_OSM 0x1c
2432#define STATUS_INVALID_PHY_ADDR_LEN_FROM_OSM 0x1d
2433#define STATUS_ASSERT_FAILED 0x1e
2434#define STATUS_INVALID_SESSION 0x1f
2435#define STATUS_INVALID_CONNECTION 0x20
2436#define STATUS_BTL_PATH_EXCEEDS_OSM_LIMIT 0x21
2437#define STATUS_BTL_NO_FREE_SLOT_PATH 0x24
2438#define STATUS_BTL_NO_FREE_SLOT_TGTID 0x25
2439#define STATUS_OSM_DEVSLOT_NOT_FOUND 0x26
2440#define STATUS_FLASHROM_READ_FAILED 0x27
2441#define STATUS_POLL_IOCTL_TIMEOUT 0x28
2442#define STATUS_ERROR_ACITMAIN 0x2a
2443#define STATUS_REBOOT_REQUIRED 0x2c
2444#define STATUS_FCF_IN_USE 0x3a
2445#define STATUS_FCF_TABLE_EMPTY 0x43
2446
2447/*
2448 * Additional status field for embedded SLI_CONFIG mailbox
2449 * command.
2450 */
2451#define ADD_STATUS_OPERATION_ALREADY_ACTIVE 0x67
2452#define ADD_STATUS_FW_NOT_SUPPORTED 0xEB
2453#define ADD_STATUS_INVALID_REQUEST 0x4B
2454#define ADD_STATUS_INVALID_OBJECT_NAME 0xA0
2455#define ADD_STATUS_FW_DOWNLOAD_HW_DISABLED 0x58
2456
2457struct lpfc_mbx_sli4_config {
2458 struct mbox_header header;
2459};
2460
2461struct lpfc_mbx_init_vfi {
2462 uint32_t word1;
2463#define lpfc_init_vfi_vr_SHIFT 31
2464#define lpfc_init_vfi_vr_MASK 0x00000001
2465#define lpfc_init_vfi_vr_WORD word1
2466#define lpfc_init_vfi_vt_SHIFT 30
2467#define lpfc_init_vfi_vt_MASK 0x00000001
2468#define lpfc_init_vfi_vt_WORD word1
2469#define lpfc_init_vfi_vf_SHIFT 29
2470#define lpfc_init_vfi_vf_MASK 0x00000001
2471#define lpfc_init_vfi_vf_WORD word1
2472#define lpfc_init_vfi_vp_SHIFT 28
2473#define lpfc_init_vfi_vp_MASK 0x00000001
2474#define lpfc_init_vfi_vp_WORD word1
2475#define lpfc_init_vfi_vfi_SHIFT 0
2476#define lpfc_init_vfi_vfi_MASK 0x0000FFFF
2477#define lpfc_init_vfi_vfi_WORD word1
2478 uint32_t word2;
2479#define lpfc_init_vfi_vpi_SHIFT 16
2480#define lpfc_init_vfi_vpi_MASK 0x0000FFFF
2481#define lpfc_init_vfi_vpi_WORD word2
2482#define lpfc_init_vfi_fcfi_SHIFT 0
2483#define lpfc_init_vfi_fcfi_MASK 0x0000FFFF
2484#define lpfc_init_vfi_fcfi_WORD word2
2485 uint32_t word3;
2486#define lpfc_init_vfi_pri_SHIFT 13
2487#define lpfc_init_vfi_pri_MASK 0x00000007
2488#define lpfc_init_vfi_pri_WORD word3
2489#define lpfc_init_vfi_vf_id_SHIFT 1
2490#define lpfc_init_vfi_vf_id_MASK 0x00000FFF
2491#define lpfc_init_vfi_vf_id_WORD word3
2492 uint32_t word4;
2493#define lpfc_init_vfi_hop_count_SHIFT 24
2494#define lpfc_init_vfi_hop_count_MASK 0x000000FF
2495#define lpfc_init_vfi_hop_count_WORD word4
2496};
2497#define MBX_VFI_IN_USE 0x9F02
2498
2499
2500struct lpfc_mbx_reg_vfi {
2501 uint32_t word1;
2502#define lpfc_reg_vfi_upd_SHIFT 29
2503#define lpfc_reg_vfi_upd_MASK 0x00000001
2504#define lpfc_reg_vfi_upd_WORD word1
2505#define lpfc_reg_vfi_vp_SHIFT 28
2506#define lpfc_reg_vfi_vp_MASK 0x00000001
2507#define lpfc_reg_vfi_vp_WORD word1
2508#define lpfc_reg_vfi_vfi_SHIFT 0
2509#define lpfc_reg_vfi_vfi_MASK 0x0000FFFF
2510#define lpfc_reg_vfi_vfi_WORD word1
2511 uint32_t word2;
2512#define lpfc_reg_vfi_vpi_SHIFT 16
2513#define lpfc_reg_vfi_vpi_MASK 0x0000FFFF
2514#define lpfc_reg_vfi_vpi_WORD word2
2515#define lpfc_reg_vfi_fcfi_SHIFT 0
2516#define lpfc_reg_vfi_fcfi_MASK 0x0000FFFF
2517#define lpfc_reg_vfi_fcfi_WORD word2
2518 uint32_t wwn[2];
2519 struct ulp_bde64 bde;
2520 uint32_t e_d_tov;
2521 uint32_t r_a_tov;
2522 uint32_t word10;
2523#define lpfc_reg_vfi_nport_id_SHIFT 0
2524#define lpfc_reg_vfi_nport_id_MASK 0x00FFFFFF
2525#define lpfc_reg_vfi_nport_id_WORD word10
2526#define lpfc_reg_vfi_bbcr_SHIFT 27
2527#define lpfc_reg_vfi_bbcr_MASK 0x00000001
2528#define lpfc_reg_vfi_bbcr_WORD word10
2529#define lpfc_reg_vfi_bbscn_SHIFT 28
2530#define lpfc_reg_vfi_bbscn_MASK 0x0000000F
2531#define lpfc_reg_vfi_bbscn_WORD word10
2532};
2533
2534struct lpfc_mbx_init_vpi {
2535 uint32_t word1;
2536#define lpfc_init_vpi_vfi_SHIFT 16
2537#define lpfc_init_vpi_vfi_MASK 0x0000FFFF
2538#define lpfc_init_vpi_vfi_WORD word1
2539#define lpfc_init_vpi_vpi_SHIFT 0
2540#define lpfc_init_vpi_vpi_MASK 0x0000FFFF
2541#define lpfc_init_vpi_vpi_WORD word1
2542};
2543
2544struct lpfc_mbx_read_vpi {
2545 uint32_t word1_rsvd;
2546 uint32_t word2;
2547#define lpfc_mbx_read_vpi_vnportid_SHIFT 0
2548#define lpfc_mbx_read_vpi_vnportid_MASK 0x00FFFFFF
2549#define lpfc_mbx_read_vpi_vnportid_WORD word2
2550 uint32_t word3_rsvd;
2551 uint32_t word4;
2552#define lpfc_mbx_read_vpi_acq_alpa_SHIFT 0
2553#define lpfc_mbx_read_vpi_acq_alpa_MASK 0x000000FF
2554#define lpfc_mbx_read_vpi_acq_alpa_WORD word4
2555#define lpfc_mbx_read_vpi_pb_SHIFT 15
2556#define lpfc_mbx_read_vpi_pb_MASK 0x00000001
2557#define lpfc_mbx_read_vpi_pb_WORD word4
2558#define lpfc_mbx_read_vpi_spec_alpa_SHIFT 16
2559#define lpfc_mbx_read_vpi_spec_alpa_MASK 0x000000FF
2560#define lpfc_mbx_read_vpi_spec_alpa_WORD word4
2561#define lpfc_mbx_read_vpi_ns_SHIFT 30
2562#define lpfc_mbx_read_vpi_ns_MASK 0x00000001
2563#define lpfc_mbx_read_vpi_ns_WORD word4
2564#define lpfc_mbx_read_vpi_hl_SHIFT 31
2565#define lpfc_mbx_read_vpi_hl_MASK 0x00000001
2566#define lpfc_mbx_read_vpi_hl_WORD word4
2567 uint32_t word5_rsvd;
2568 uint32_t word6;
2569#define lpfc_mbx_read_vpi_vpi_SHIFT 0
2570#define lpfc_mbx_read_vpi_vpi_MASK 0x0000FFFF
2571#define lpfc_mbx_read_vpi_vpi_WORD word6
2572 uint32_t word7;
2573#define lpfc_mbx_read_vpi_mac_0_SHIFT 0
2574#define lpfc_mbx_read_vpi_mac_0_MASK 0x000000FF
2575#define lpfc_mbx_read_vpi_mac_0_WORD word7
2576#define lpfc_mbx_read_vpi_mac_1_SHIFT 8
2577#define lpfc_mbx_read_vpi_mac_1_MASK 0x000000FF
2578#define lpfc_mbx_read_vpi_mac_1_WORD word7
2579#define lpfc_mbx_read_vpi_mac_2_SHIFT 16
2580#define lpfc_mbx_read_vpi_mac_2_MASK 0x000000FF
2581#define lpfc_mbx_read_vpi_mac_2_WORD word7
2582#define lpfc_mbx_read_vpi_mac_3_SHIFT 24
2583#define lpfc_mbx_read_vpi_mac_3_MASK 0x000000FF
2584#define lpfc_mbx_read_vpi_mac_3_WORD word7
2585 uint32_t word8;
2586#define lpfc_mbx_read_vpi_mac_4_SHIFT 0
2587#define lpfc_mbx_read_vpi_mac_4_MASK 0x000000FF
2588#define lpfc_mbx_read_vpi_mac_4_WORD word8
2589#define lpfc_mbx_read_vpi_mac_5_SHIFT 8
2590#define lpfc_mbx_read_vpi_mac_5_MASK 0x000000FF
2591#define lpfc_mbx_read_vpi_mac_5_WORD word8
2592#define lpfc_mbx_read_vpi_vlan_tag_SHIFT 16
2593#define lpfc_mbx_read_vpi_vlan_tag_MASK 0x00000FFF
2594#define lpfc_mbx_read_vpi_vlan_tag_WORD word8
2595#define lpfc_mbx_read_vpi_vv_SHIFT 28
2596#define lpfc_mbx_read_vpi_vv_MASK 0x0000001
2597#define lpfc_mbx_read_vpi_vv_WORD word8
2598};
2599
2600struct lpfc_mbx_unreg_vfi {
2601 uint32_t word1_rsvd;
2602 uint32_t word2;
2603#define lpfc_unreg_vfi_vfi_SHIFT 0
2604#define lpfc_unreg_vfi_vfi_MASK 0x0000FFFF
2605#define lpfc_unreg_vfi_vfi_WORD word2
2606};
2607
2608struct lpfc_mbx_resume_rpi {
2609 uint32_t word1;
2610#define lpfc_resume_rpi_index_SHIFT 0
2611#define lpfc_resume_rpi_index_MASK 0x0000FFFF
2612#define lpfc_resume_rpi_index_WORD word1
2613#define lpfc_resume_rpi_ii_SHIFT 30
2614#define lpfc_resume_rpi_ii_MASK 0x00000003
2615#define lpfc_resume_rpi_ii_WORD word1
2616#define RESUME_INDEX_RPI 0
2617#define RESUME_INDEX_VPI 1
2618#define RESUME_INDEX_VFI 2
2619#define RESUME_INDEX_FCFI 3
2620 uint32_t event_tag;
2621};
2622
2623#define REG_FCF_INVALID_QID 0xFFFF
2624struct lpfc_mbx_reg_fcfi {
2625 uint32_t word1;
2626#define lpfc_reg_fcfi_info_index_SHIFT 0
2627#define lpfc_reg_fcfi_info_index_MASK 0x0000FFFF
2628#define lpfc_reg_fcfi_info_index_WORD word1
2629#define lpfc_reg_fcfi_fcfi_SHIFT 16
2630#define lpfc_reg_fcfi_fcfi_MASK 0x0000FFFF
2631#define lpfc_reg_fcfi_fcfi_WORD word1
2632 uint32_t word2;
2633#define lpfc_reg_fcfi_rq_id1_SHIFT 0
2634#define lpfc_reg_fcfi_rq_id1_MASK 0x0000FFFF
2635#define lpfc_reg_fcfi_rq_id1_WORD word2
2636#define lpfc_reg_fcfi_rq_id0_SHIFT 16
2637#define lpfc_reg_fcfi_rq_id0_MASK 0x0000FFFF
2638#define lpfc_reg_fcfi_rq_id0_WORD word2
2639 uint32_t word3;
2640#define lpfc_reg_fcfi_rq_id3_SHIFT 0
2641#define lpfc_reg_fcfi_rq_id3_MASK 0x0000FFFF
2642#define lpfc_reg_fcfi_rq_id3_WORD word3
2643#define lpfc_reg_fcfi_rq_id2_SHIFT 16
2644#define lpfc_reg_fcfi_rq_id2_MASK 0x0000FFFF
2645#define lpfc_reg_fcfi_rq_id2_WORD word3
2646 uint32_t word4;
2647#define lpfc_reg_fcfi_type_match0_SHIFT 24
2648#define lpfc_reg_fcfi_type_match0_MASK 0x000000FF
2649#define lpfc_reg_fcfi_type_match0_WORD word4
2650#define lpfc_reg_fcfi_type_mask0_SHIFT 16
2651#define lpfc_reg_fcfi_type_mask0_MASK 0x000000FF
2652#define lpfc_reg_fcfi_type_mask0_WORD word4
2653#define lpfc_reg_fcfi_rctl_match0_SHIFT 8
2654#define lpfc_reg_fcfi_rctl_match0_MASK 0x000000FF
2655#define lpfc_reg_fcfi_rctl_match0_WORD word4
2656#define lpfc_reg_fcfi_rctl_mask0_SHIFT 0
2657#define lpfc_reg_fcfi_rctl_mask0_MASK 0x000000FF
2658#define lpfc_reg_fcfi_rctl_mask0_WORD word4
2659 uint32_t word5;
2660#define lpfc_reg_fcfi_type_match1_SHIFT 24
2661#define lpfc_reg_fcfi_type_match1_MASK 0x000000FF
2662#define lpfc_reg_fcfi_type_match1_WORD word5
2663#define lpfc_reg_fcfi_type_mask1_SHIFT 16
2664#define lpfc_reg_fcfi_type_mask1_MASK 0x000000FF
2665#define lpfc_reg_fcfi_type_mask1_WORD word5
2666#define lpfc_reg_fcfi_rctl_match1_SHIFT 8
2667#define lpfc_reg_fcfi_rctl_match1_MASK 0x000000FF
2668#define lpfc_reg_fcfi_rctl_match1_WORD word5
2669#define lpfc_reg_fcfi_rctl_mask1_SHIFT 0
2670#define lpfc_reg_fcfi_rctl_mask1_MASK 0x000000FF
2671#define lpfc_reg_fcfi_rctl_mask1_WORD word5
2672 uint32_t word6;
2673#define lpfc_reg_fcfi_type_match2_SHIFT 24
2674#define lpfc_reg_fcfi_type_match2_MASK 0x000000FF
2675#define lpfc_reg_fcfi_type_match2_WORD word6
2676#define lpfc_reg_fcfi_type_mask2_SHIFT 16
2677#define lpfc_reg_fcfi_type_mask2_MASK 0x000000FF
2678#define lpfc_reg_fcfi_type_mask2_WORD word6
2679#define lpfc_reg_fcfi_rctl_match2_SHIFT 8
2680#define lpfc_reg_fcfi_rctl_match2_MASK 0x000000FF
2681#define lpfc_reg_fcfi_rctl_match2_WORD word6
2682#define lpfc_reg_fcfi_rctl_mask2_SHIFT 0
2683#define lpfc_reg_fcfi_rctl_mask2_MASK 0x000000FF
2684#define lpfc_reg_fcfi_rctl_mask2_WORD word6
2685 uint32_t word7;
2686#define lpfc_reg_fcfi_type_match3_SHIFT 24
2687#define lpfc_reg_fcfi_type_match3_MASK 0x000000FF
2688#define lpfc_reg_fcfi_type_match3_WORD word7
2689#define lpfc_reg_fcfi_type_mask3_SHIFT 16
2690#define lpfc_reg_fcfi_type_mask3_MASK 0x000000FF
2691#define lpfc_reg_fcfi_type_mask3_WORD word7
2692#define lpfc_reg_fcfi_rctl_match3_SHIFT 8
2693#define lpfc_reg_fcfi_rctl_match3_MASK 0x000000FF
2694#define lpfc_reg_fcfi_rctl_match3_WORD word7
2695#define lpfc_reg_fcfi_rctl_mask3_SHIFT 0
2696#define lpfc_reg_fcfi_rctl_mask3_MASK 0x000000FF
2697#define lpfc_reg_fcfi_rctl_mask3_WORD word7
2698 uint32_t word8;
2699#define lpfc_reg_fcfi_mam_SHIFT 13
2700#define lpfc_reg_fcfi_mam_MASK 0x00000003
2701#define lpfc_reg_fcfi_mam_WORD word8
2702#define LPFC_MAM_BOTH 0 /* Both SPMA and FPMA */
2703#define LPFC_MAM_SPMA 1 /* Server Provided MAC Address */
2704#define LPFC_MAM_FPMA 2 /* Fabric Provided MAC Address */
2705#define lpfc_reg_fcfi_vv_SHIFT 12
2706#define lpfc_reg_fcfi_vv_MASK 0x00000001
2707#define lpfc_reg_fcfi_vv_WORD word8
2708#define lpfc_reg_fcfi_vlan_tag_SHIFT 0
2709#define lpfc_reg_fcfi_vlan_tag_MASK 0x00000FFF
2710#define lpfc_reg_fcfi_vlan_tag_WORD word8
2711};
2712
2713struct lpfc_mbx_reg_fcfi_mrq {
2714 uint32_t word1;
2715#define lpfc_reg_fcfi_mrq_info_index_SHIFT 0
2716#define lpfc_reg_fcfi_mrq_info_index_MASK 0x0000FFFF
2717#define lpfc_reg_fcfi_mrq_info_index_WORD word1
2718#define lpfc_reg_fcfi_mrq_fcfi_SHIFT 16
2719#define lpfc_reg_fcfi_mrq_fcfi_MASK 0x0000FFFF
2720#define lpfc_reg_fcfi_mrq_fcfi_WORD word1
2721 uint32_t word2;
2722#define lpfc_reg_fcfi_mrq_rq_id1_SHIFT 0
2723#define lpfc_reg_fcfi_mrq_rq_id1_MASK 0x0000FFFF
2724#define lpfc_reg_fcfi_mrq_rq_id1_WORD word2
2725#define lpfc_reg_fcfi_mrq_rq_id0_SHIFT 16
2726#define lpfc_reg_fcfi_mrq_rq_id0_MASK 0x0000FFFF
2727#define lpfc_reg_fcfi_mrq_rq_id0_WORD word2
2728 uint32_t word3;
2729#define lpfc_reg_fcfi_mrq_rq_id3_SHIFT 0
2730#define lpfc_reg_fcfi_mrq_rq_id3_MASK 0x0000FFFF
2731#define lpfc_reg_fcfi_mrq_rq_id3_WORD word3
2732#define lpfc_reg_fcfi_mrq_rq_id2_SHIFT 16
2733#define lpfc_reg_fcfi_mrq_rq_id2_MASK 0x0000FFFF
2734#define lpfc_reg_fcfi_mrq_rq_id2_WORD word3
2735 uint32_t word4;
2736#define lpfc_reg_fcfi_mrq_type_match0_SHIFT 24
2737#define lpfc_reg_fcfi_mrq_type_match0_MASK 0x000000FF
2738#define lpfc_reg_fcfi_mrq_type_match0_WORD word4
2739#define lpfc_reg_fcfi_mrq_type_mask0_SHIFT 16
2740#define lpfc_reg_fcfi_mrq_type_mask0_MASK 0x000000FF
2741#define lpfc_reg_fcfi_mrq_type_mask0_WORD word4
2742#define lpfc_reg_fcfi_mrq_rctl_match0_SHIFT 8
2743#define lpfc_reg_fcfi_mrq_rctl_match0_MASK 0x000000FF
2744#define lpfc_reg_fcfi_mrq_rctl_match0_WORD word4
2745#define lpfc_reg_fcfi_mrq_rctl_mask0_SHIFT 0
2746#define lpfc_reg_fcfi_mrq_rctl_mask0_MASK 0x000000FF
2747#define lpfc_reg_fcfi_mrq_rctl_mask0_WORD word4
2748 uint32_t word5;
2749#define lpfc_reg_fcfi_mrq_type_match1_SHIFT 24
2750#define lpfc_reg_fcfi_mrq_type_match1_MASK 0x000000FF
2751#define lpfc_reg_fcfi_mrq_type_match1_WORD word5
2752#define lpfc_reg_fcfi_mrq_type_mask1_SHIFT 16
2753#define lpfc_reg_fcfi_mrq_type_mask1_MASK 0x000000FF
2754#define lpfc_reg_fcfi_mrq_type_mask1_WORD word5
2755#define lpfc_reg_fcfi_mrq_rctl_match1_SHIFT 8
2756#define lpfc_reg_fcfi_mrq_rctl_match1_MASK 0x000000FF
2757#define lpfc_reg_fcfi_mrq_rctl_match1_WORD word5
2758#define lpfc_reg_fcfi_mrq_rctl_mask1_SHIFT 0
2759#define lpfc_reg_fcfi_mrq_rctl_mask1_MASK 0x000000FF
2760#define lpfc_reg_fcfi_mrq_rctl_mask1_WORD word5
2761 uint32_t word6;
2762#define lpfc_reg_fcfi_mrq_type_match2_SHIFT 24
2763#define lpfc_reg_fcfi_mrq_type_match2_MASK 0x000000FF
2764#define lpfc_reg_fcfi_mrq_type_match2_WORD word6
2765#define lpfc_reg_fcfi_mrq_type_mask2_SHIFT 16
2766#define lpfc_reg_fcfi_mrq_type_mask2_MASK 0x000000FF
2767#define lpfc_reg_fcfi_mrq_type_mask2_WORD word6
2768#define lpfc_reg_fcfi_mrq_rctl_match2_SHIFT 8
2769#define lpfc_reg_fcfi_mrq_rctl_match2_MASK 0x000000FF
2770#define lpfc_reg_fcfi_mrq_rctl_match2_WORD word6
2771#define lpfc_reg_fcfi_mrq_rctl_mask2_SHIFT 0
2772#define lpfc_reg_fcfi_mrq_rctl_mask2_MASK 0x000000FF
2773#define lpfc_reg_fcfi_mrq_rctl_mask2_WORD word6
2774 uint32_t word7;
2775#define lpfc_reg_fcfi_mrq_type_match3_SHIFT 24
2776#define lpfc_reg_fcfi_mrq_type_match3_MASK 0x000000FF
2777#define lpfc_reg_fcfi_mrq_type_match3_WORD word7
2778#define lpfc_reg_fcfi_mrq_type_mask3_SHIFT 16
2779#define lpfc_reg_fcfi_mrq_type_mask3_MASK 0x000000FF
2780#define lpfc_reg_fcfi_mrq_type_mask3_WORD word7
2781#define lpfc_reg_fcfi_mrq_rctl_match3_SHIFT 8
2782#define lpfc_reg_fcfi_mrq_rctl_match3_MASK 0x000000FF
2783#define lpfc_reg_fcfi_mrq_rctl_match3_WORD word7
2784#define lpfc_reg_fcfi_mrq_rctl_mask3_SHIFT 0
2785#define lpfc_reg_fcfi_mrq_rctl_mask3_MASK 0x000000FF
2786#define lpfc_reg_fcfi_mrq_rctl_mask3_WORD word7
2787 uint32_t word8;
2788#define lpfc_reg_fcfi_mrq_ptc7_SHIFT 31
2789#define lpfc_reg_fcfi_mrq_ptc7_MASK 0x00000001
2790#define lpfc_reg_fcfi_mrq_ptc7_WORD word8
2791#define lpfc_reg_fcfi_mrq_ptc6_SHIFT 30
2792#define lpfc_reg_fcfi_mrq_ptc6_MASK 0x00000001
2793#define lpfc_reg_fcfi_mrq_ptc6_WORD word8
2794#define lpfc_reg_fcfi_mrq_ptc5_SHIFT 29
2795#define lpfc_reg_fcfi_mrq_ptc5_MASK 0x00000001
2796#define lpfc_reg_fcfi_mrq_ptc5_WORD word8
2797#define lpfc_reg_fcfi_mrq_ptc4_SHIFT 28
2798#define lpfc_reg_fcfi_mrq_ptc4_MASK 0x00000001
2799#define lpfc_reg_fcfi_mrq_ptc4_WORD word8
2800#define lpfc_reg_fcfi_mrq_ptc3_SHIFT 27
2801#define lpfc_reg_fcfi_mrq_ptc3_MASK 0x00000001
2802#define lpfc_reg_fcfi_mrq_ptc3_WORD word8
2803#define lpfc_reg_fcfi_mrq_ptc2_SHIFT 26
2804#define lpfc_reg_fcfi_mrq_ptc2_MASK 0x00000001
2805#define lpfc_reg_fcfi_mrq_ptc2_WORD word8
2806#define lpfc_reg_fcfi_mrq_ptc1_SHIFT 25
2807#define lpfc_reg_fcfi_mrq_ptc1_MASK 0x00000001
2808#define lpfc_reg_fcfi_mrq_ptc1_WORD word8
2809#define lpfc_reg_fcfi_mrq_ptc0_SHIFT 24
2810#define lpfc_reg_fcfi_mrq_ptc0_MASK 0x00000001
2811#define lpfc_reg_fcfi_mrq_ptc0_WORD word8
2812#define lpfc_reg_fcfi_mrq_pt7_SHIFT 23
2813#define lpfc_reg_fcfi_mrq_pt7_MASK 0x00000001
2814#define lpfc_reg_fcfi_mrq_pt7_WORD word8
2815#define lpfc_reg_fcfi_mrq_pt6_SHIFT 22
2816#define lpfc_reg_fcfi_mrq_pt6_MASK 0x00000001
2817#define lpfc_reg_fcfi_mrq_pt6_WORD word8
2818#define lpfc_reg_fcfi_mrq_pt5_SHIFT 21
2819#define lpfc_reg_fcfi_mrq_pt5_MASK 0x00000001
2820#define lpfc_reg_fcfi_mrq_pt5_WORD word8
2821#define lpfc_reg_fcfi_mrq_pt4_SHIFT 20
2822#define lpfc_reg_fcfi_mrq_pt4_MASK 0x00000001
2823#define lpfc_reg_fcfi_mrq_pt4_WORD word8
2824#define lpfc_reg_fcfi_mrq_pt3_SHIFT 19
2825#define lpfc_reg_fcfi_mrq_pt3_MASK 0x00000001
2826#define lpfc_reg_fcfi_mrq_pt3_WORD word8
2827#define lpfc_reg_fcfi_mrq_pt2_SHIFT 18
2828#define lpfc_reg_fcfi_mrq_pt2_MASK 0x00000001
2829#define lpfc_reg_fcfi_mrq_pt2_WORD word8
2830#define lpfc_reg_fcfi_mrq_pt1_SHIFT 17
2831#define lpfc_reg_fcfi_mrq_pt1_MASK 0x00000001
2832#define lpfc_reg_fcfi_mrq_pt1_WORD word8
2833#define lpfc_reg_fcfi_mrq_pt0_SHIFT 16
2834#define lpfc_reg_fcfi_mrq_pt0_MASK 0x00000001
2835#define lpfc_reg_fcfi_mrq_pt0_WORD word8
2836#define lpfc_reg_fcfi_mrq_xmv_SHIFT 15
2837#define lpfc_reg_fcfi_mrq_xmv_MASK 0x00000001
2838#define lpfc_reg_fcfi_mrq_xmv_WORD word8
2839#define lpfc_reg_fcfi_mrq_mode_SHIFT 13
2840#define lpfc_reg_fcfi_mrq_mode_MASK 0x00000001
2841#define lpfc_reg_fcfi_mrq_mode_WORD word8
2842#define lpfc_reg_fcfi_mrq_vv_SHIFT 12
2843#define lpfc_reg_fcfi_mrq_vv_MASK 0x00000001
2844#define lpfc_reg_fcfi_mrq_vv_WORD word8
2845#define lpfc_reg_fcfi_mrq_vlan_tag_SHIFT 0
2846#define lpfc_reg_fcfi_mrq_vlan_tag_MASK 0x00000FFF
2847#define lpfc_reg_fcfi_mrq_vlan_tag_WORD word8
2848 uint32_t word9;
2849#define lpfc_reg_fcfi_mrq_policy_SHIFT 12
2850#define lpfc_reg_fcfi_mrq_policy_MASK 0x0000000F
2851#define lpfc_reg_fcfi_mrq_policy_WORD word9
2852#define lpfc_reg_fcfi_mrq_filter_SHIFT 8
2853#define lpfc_reg_fcfi_mrq_filter_MASK 0x0000000F
2854#define lpfc_reg_fcfi_mrq_filter_WORD word9
2855#define lpfc_reg_fcfi_mrq_npairs_SHIFT 0
2856#define lpfc_reg_fcfi_mrq_npairs_MASK 0x000000FF
2857#define lpfc_reg_fcfi_mrq_npairs_WORD word9
2858 uint32_t word10;
2859 uint32_t word11;
2860 uint32_t word12;
2861 uint32_t word13;
2862 uint32_t word14;
2863 uint32_t word15;
2864 uint32_t word16;
2865};
2866
2867struct lpfc_mbx_unreg_fcfi {
2868 uint32_t word1_rsv;
2869 uint32_t word2;
2870#define lpfc_unreg_fcfi_SHIFT 0
2871#define lpfc_unreg_fcfi_MASK 0x0000FFFF
2872#define lpfc_unreg_fcfi_WORD word2
2873};
2874
2875struct lpfc_mbx_read_rev {
2876 uint32_t word1;
2877#define lpfc_mbx_rd_rev_sli_lvl_SHIFT 16
2878#define lpfc_mbx_rd_rev_sli_lvl_MASK 0x0000000F
2879#define lpfc_mbx_rd_rev_sli_lvl_WORD word1
2880#define lpfc_mbx_rd_rev_fcoe_SHIFT 20
2881#define lpfc_mbx_rd_rev_fcoe_MASK 0x00000001
2882#define lpfc_mbx_rd_rev_fcoe_WORD word1
2883#define lpfc_mbx_rd_rev_cee_ver_SHIFT 21
2884#define lpfc_mbx_rd_rev_cee_ver_MASK 0x00000003
2885#define lpfc_mbx_rd_rev_cee_ver_WORD word1
2886#define LPFC_PREDCBX_CEE_MODE 0
2887#define LPFC_DCBX_CEE_MODE 1
2888#define lpfc_mbx_rd_rev_vpd_SHIFT 29
2889#define lpfc_mbx_rd_rev_vpd_MASK 0x00000001
2890#define lpfc_mbx_rd_rev_vpd_WORD word1
2891 uint32_t first_hw_rev;
2892#define LPFC_G7_ASIC_1 0xd
2893 uint32_t second_hw_rev;
2894 uint32_t word4_rsvd;
2895 uint32_t third_hw_rev;
2896 uint32_t word6;
2897#define lpfc_mbx_rd_rev_fcph_low_SHIFT 0
2898#define lpfc_mbx_rd_rev_fcph_low_MASK 0x000000FF
2899#define lpfc_mbx_rd_rev_fcph_low_WORD word6
2900#define lpfc_mbx_rd_rev_fcph_high_SHIFT 8
2901#define lpfc_mbx_rd_rev_fcph_high_MASK 0x000000FF
2902#define lpfc_mbx_rd_rev_fcph_high_WORD word6
2903#define lpfc_mbx_rd_rev_ftr_lvl_low_SHIFT 16
2904#define lpfc_mbx_rd_rev_ftr_lvl_low_MASK 0x000000FF
2905#define lpfc_mbx_rd_rev_ftr_lvl_low_WORD word6
2906#define lpfc_mbx_rd_rev_ftr_lvl_high_SHIFT 24
2907#define lpfc_mbx_rd_rev_ftr_lvl_high_MASK 0x000000FF
2908#define lpfc_mbx_rd_rev_ftr_lvl_high_WORD word6
2909 uint32_t word7_rsvd;
2910 uint32_t fw_id_rev;
2911 uint8_t fw_name[16];
2912 uint32_t ulp_fw_id_rev;
2913 uint8_t ulp_fw_name[16];
2914 uint32_t word18_47_rsvd[30];
2915 uint32_t word48;
2916#define lpfc_mbx_rd_rev_avail_len_SHIFT 0
2917#define lpfc_mbx_rd_rev_avail_len_MASK 0x00FFFFFF
2918#define lpfc_mbx_rd_rev_avail_len_WORD word48
2919 uint32_t vpd_paddr_low;
2920 uint32_t vpd_paddr_high;
2921 uint32_t avail_vpd_len;
2922 uint32_t rsvd_52_63[12];
2923};
2924
2925struct lpfc_mbx_read_config {
2926 uint32_t word1;
2927#define lpfc_mbx_rd_conf_extnts_inuse_SHIFT 31
2928#define lpfc_mbx_rd_conf_extnts_inuse_MASK 0x00000001
2929#define lpfc_mbx_rd_conf_extnts_inuse_WORD word1
2930#define lpfc_mbx_rd_conf_fawwpn_SHIFT 30
2931#define lpfc_mbx_rd_conf_fawwpn_MASK 0x00000001
2932#define lpfc_mbx_rd_conf_fawwpn_WORD word1
2933#define lpfc_mbx_rd_conf_wcs_SHIFT 28 /* warning signaling */
2934#define lpfc_mbx_rd_conf_wcs_MASK 0x00000001
2935#define lpfc_mbx_rd_conf_wcs_WORD word1
2936#define lpfc_mbx_rd_conf_acs_SHIFT 27 /* alarm signaling */
2937#define lpfc_mbx_rd_conf_acs_MASK 0x00000001
2938#define lpfc_mbx_rd_conf_acs_WORD word1
2939 uint32_t word2;
2940#define lpfc_mbx_rd_conf_lnk_numb_SHIFT 0
2941#define lpfc_mbx_rd_conf_lnk_numb_MASK 0x0000003F
2942#define lpfc_mbx_rd_conf_lnk_numb_WORD word2
2943#define lpfc_mbx_rd_conf_lnk_type_SHIFT 6
2944#define lpfc_mbx_rd_conf_lnk_type_MASK 0x00000003
2945#define lpfc_mbx_rd_conf_lnk_type_WORD word2
2946#define LPFC_LNK_TYPE_GE 0
2947#define LPFC_LNK_TYPE_FC 1
2948#define lpfc_mbx_rd_conf_lnk_ldv_SHIFT 8
2949#define lpfc_mbx_rd_conf_lnk_ldv_MASK 0x00000001
2950#define lpfc_mbx_rd_conf_lnk_ldv_WORD word2
2951#define lpfc_mbx_rd_conf_trunk_SHIFT 12
2952#define lpfc_mbx_rd_conf_trunk_MASK 0x0000000F
2953#define lpfc_mbx_rd_conf_trunk_WORD word2
2954#define lpfc_mbx_rd_conf_pt_SHIFT 20
2955#define lpfc_mbx_rd_conf_pt_MASK 0x00000003
2956#define lpfc_mbx_rd_conf_pt_WORD word2
2957#define lpfc_mbx_rd_conf_tf_SHIFT 22
2958#define lpfc_mbx_rd_conf_tf_MASK 0x00000001
2959#define lpfc_mbx_rd_conf_tf_WORD word2
2960#define lpfc_mbx_rd_conf_ptv_SHIFT 23
2961#define lpfc_mbx_rd_conf_ptv_MASK 0x00000001
2962#define lpfc_mbx_rd_conf_ptv_WORD word2
2963#define lpfc_mbx_rd_conf_topology_SHIFT 24
2964#define lpfc_mbx_rd_conf_topology_MASK 0x000000FF
2965#define lpfc_mbx_rd_conf_topology_WORD word2
2966 uint32_t word3;
2967#define lpfc_mbx_rd_conf_fedif_SHIFT 6
2968#define lpfc_mbx_rd_conf_fedif_MASK 0x00000001
2969#define lpfc_mbx_rd_conf_fedif_WORD word3
2970 uint32_t word4;
2971#define lpfc_mbx_rd_conf_e_d_tov_SHIFT 0
2972#define lpfc_mbx_rd_conf_e_d_tov_MASK 0x0000FFFF
2973#define lpfc_mbx_rd_conf_e_d_tov_WORD word4
2974 uint32_t rsvd_5;
2975 uint32_t word6;
2976#define lpfc_mbx_rd_conf_r_a_tov_SHIFT 0
2977#define lpfc_mbx_rd_conf_r_a_tov_MASK 0x0000FFFF
2978#define lpfc_mbx_rd_conf_r_a_tov_WORD word6
2979#define lpfc_mbx_rd_conf_link_speed_SHIFT 16
2980#define lpfc_mbx_rd_conf_link_speed_MASK 0x0000FFFF
2981#define lpfc_mbx_rd_conf_link_speed_WORD word6
2982 uint32_t rsvd_7;
2983 uint32_t word8;
2984#define lpfc_mbx_rd_conf_bbscn_min_SHIFT 0
2985#define lpfc_mbx_rd_conf_bbscn_min_MASK 0x0000000F
2986#define lpfc_mbx_rd_conf_bbscn_min_WORD word8
2987#define lpfc_mbx_rd_conf_bbscn_max_SHIFT 4
2988#define lpfc_mbx_rd_conf_bbscn_max_MASK 0x0000000F
2989#define lpfc_mbx_rd_conf_bbscn_max_WORD word8
2990#define lpfc_mbx_rd_conf_bbscn_def_SHIFT 8
2991#define lpfc_mbx_rd_conf_bbscn_def_MASK 0x0000000F
2992#define lpfc_mbx_rd_conf_bbscn_def_WORD word8
2993 uint32_t word9;
2994#define lpfc_mbx_rd_conf_lmt_SHIFT 0
2995#define lpfc_mbx_rd_conf_lmt_MASK 0x0000FFFF
2996#define lpfc_mbx_rd_conf_lmt_WORD word9
2997 uint32_t rsvd_10;
2998 uint32_t rsvd_11;
2999 uint32_t word12;
3000#define lpfc_mbx_rd_conf_xri_base_SHIFT 0
3001#define lpfc_mbx_rd_conf_xri_base_MASK 0x0000FFFF
3002#define lpfc_mbx_rd_conf_xri_base_WORD word12
3003#define lpfc_mbx_rd_conf_xri_count_SHIFT 16
3004#define lpfc_mbx_rd_conf_xri_count_MASK 0x0000FFFF
3005#define lpfc_mbx_rd_conf_xri_count_WORD word12
3006 uint32_t word13;
3007#define lpfc_mbx_rd_conf_rpi_base_SHIFT 0
3008#define lpfc_mbx_rd_conf_rpi_base_MASK 0x0000FFFF
3009#define lpfc_mbx_rd_conf_rpi_base_WORD word13
3010#define lpfc_mbx_rd_conf_rpi_count_SHIFT 16
3011#define lpfc_mbx_rd_conf_rpi_count_MASK 0x0000FFFF
3012#define lpfc_mbx_rd_conf_rpi_count_WORD word13
3013 uint32_t word14;
3014#define lpfc_mbx_rd_conf_vpi_base_SHIFT 0
3015#define lpfc_mbx_rd_conf_vpi_base_MASK 0x0000FFFF
3016#define lpfc_mbx_rd_conf_vpi_base_WORD word14
3017#define lpfc_mbx_rd_conf_vpi_count_SHIFT 16
3018#define lpfc_mbx_rd_conf_vpi_count_MASK 0x0000FFFF
3019#define lpfc_mbx_rd_conf_vpi_count_WORD word14
3020 uint32_t word15;
3021#define lpfc_mbx_rd_conf_vfi_base_SHIFT 0
3022#define lpfc_mbx_rd_conf_vfi_base_MASK 0x0000FFFF
3023#define lpfc_mbx_rd_conf_vfi_base_WORD word15
3024#define lpfc_mbx_rd_conf_vfi_count_SHIFT 16
3025#define lpfc_mbx_rd_conf_vfi_count_MASK 0x0000FFFF
3026#define lpfc_mbx_rd_conf_vfi_count_WORD word15
3027 uint32_t word16;
3028#define lpfc_mbx_rd_conf_fcfi_count_SHIFT 16
3029#define lpfc_mbx_rd_conf_fcfi_count_MASK 0x0000FFFF
3030#define lpfc_mbx_rd_conf_fcfi_count_WORD word16
3031 uint32_t word17;
3032#define lpfc_mbx_rd_conf_rq_count_SHIFT 0
3033#define lpfc_mbx_rd_conf_rq_count_MASK 0x0000FFFF
3034#define lpfc_mbx_rd_conf_rq_count_WORD word17
3035#define lpfc_mbx_rd_conf_eq_count_SHIFT 16
3036#define lpfc_mbx_rd_conf_eq_count_MASK 0x0000FFFF
3037#define lpfc_mbx_rd_conf_eq_count_WORD word17
3038 uint32_t word18;
3039#define lpfc_mbx_rd_conf_wq_count_SHIFT 0
3040#define lpfc_mbx_rd_conf_wq_count_MASK 0x0000FFFF
3041#define lpfc_mbx_rd_conf_wq_count_WORD word18
3042#define lpfc_mbx_rd_conf_cq_count_SHIFT 16
3043#define lpfc_mbx_rd_conf_cq_count_MASK 0x0000FFFF
3044#define lpfc_mbx_rd_conf_cq_count_WORD word18
3045};
3046
3047struct lpfc_mbx_request_features {
3048 uint32_t word1;
3049#define lpfc_mbx_rq_ftr_qry_SHIFT 0
3050#define lpfc_mbx_rq_ftr_qry_MASK 0x00000001
3051#define lpfc_mbx_rq_ftr_qry_WORD word1
3052 uint32_t word2;
3053#define lpfc_mbx_rq_ftr_rq_iaab_SHIFT 0
3054#define lpfc_mbx_rq_ftr_rq_iaab_MASK 0x00000001
3055#define lpfc_mbx_rq_ftr_rq_iaab_WORD word2
3056#define lpfc_mbx_rq_ftr_rq_npiv_SHIFT 1
3057#define lpfc_mbx_rq_ftr_rq_npiv_MASK 0x00000001
3058#define lpfc_mbx_rq_ftr_rq_npiv_WORD word2
3059#define lpfc_mbx_rq_ftr_rq_dif_SHIFT 2
3060#define lpfc_mbx_rq_ftr_rq_dif_MASK 0x00000001
3061#define lpfc_mbx_rq_ftr_rq_dif_WORD word2
3062#define lpfc_mbx_rq_ftr_rq_vf_SHIFT 3
3063#define lpfc_mbx_rq_ftr_rq_vf_MASK 0x00000001
3064#define lpfc_mbx_rq_ftr_rq_vf_WORD word2
3065#define lpfc_mbx_rq_ftr_rq_fcpi_SHIFT 4
3066#define lpfc_mbx_rq_ftr_rq_fcpi_MASK 0x00000001
3067#define lpfc_mbx_rq_ftr_rq_fcpi_WORD word2
3068#define lpfc_mbx_rq_ftr_rq_fcpt_SHIFT 5
3069#define lpfc_mbx_rq_ftr_rq_fcpt_MASK 0x00000001
3070#define lpfc_mbx_rq_ftr_rq_fcpt_WORD word2
3071#define lpfc_mbx_rq_ftr_rq_fcpc_SHIFT 6
3072#define lpfc_mbx_rq_ftr_rq_fcpc_MASK 0x00000001
3073#define lpfc_mbx_rq_ftr_rq_fcpc_WORD word2
3074#define lpfc_mbx_rq_ftr_rq_ifip_SHIFT 7
3075#define lpfc_mbx_rq_ftr_rq_ifip_MASK 0x00000001
3076#define lpfc_mbx_rq_ftr_rq_ifip_WORD word2
3077#define lpfc_mbx_rq_ftr_rq_iaar_SHIFT 9
3078#define lpfc_mbx_rq_ftr_rq_iaar_MASK 0x00000001
3079#define lpfc_mbx_rq_ftr_rq_iaar_WORD word2
3080#define lpfc_mbx_rq_ftr_rq_mrqp_SHIFT 16
3081#define lpfc_mbx_rq_ftr_rq_mrqp_MASK 0x00000001
3082#define lpfc_mbx_rq_ftr_rq_mrqp_WORD word2
3083#define lpfc_mbx_rq_ftr_rq_ashdr_SHIFT 17
3084#define lpfc_mbx_rq_ftr_rq_ashdr_MASK 0x00000001
3085#define lpfc_mbx_rq_ftr_rq_ashdr_WORD word2
3086 uint32_t word3;
3087#define lpfc_mbx_rq_ftr_rsp_iaab_SHIFT 0
3088#define lpfc_mbx_rq_ftr_rsp_iaab_MASK 0x00000001
3089#define lpfc_mbx_rq_ftr_rsp_iaab_WORD word3
3090#define lpfc_mbx_rq_ftr_rsp_npiv_SHIFT 1
3091#define lpfc_mbx_rq_ftr_rsp_npiv_MASK 0x00000001
3092#define lpfc_mbx_rq_ftr_rsp_npiv_WORD word3
3093#define lpfc_mbx_rq_ftr_rsp_dif_SHIFT 2
3094#define lpfc_mbx_rq_ftr_rsp_dif_MASK 0x00000001
3095#define lpfc_mbx_rq_ftr_rsp_dif_WORD word3
3096#define lpfc_mbx_rq_ftr_rsp_vf_SHIFT 3
3097#define lpfc_mbx_rq_ftr_rsp_vf__MASK 0x00000001
3098#define lpfc_mbx_rq_ftr_rsp_vf_WORD word3
3099#define lpfc_mbx_rq_ftr_rsp_fcpi_SHIFT 4
3100#define lpfc_mbx_rq_ftr_rsp_fcpi_MASK 0x00000001
3101#define lpfc_mbx_rq_ftr_rsp_fcpi_WORD word3
3102#define lpfc_mbx_rq_ftr_rsp_fcpt_SHIFT 5
3103#define lpfc_mbx_rq_ftr_rsp_fcpt_MASK 0x00000001
3104#define lpfc_mbx_rq_ftr_rsp_fcpt_WORD word3
3105#define lpfc_mbx_rq_ftr_rsp_fcpc_SHIFT 6
3106#define lpfc_mbx_rq_ftr_rsp_fcpc_MASK 0x00000001
3107#define lpfc_mbx_rq_ftr_rsp_fcpc_WORD word3
3108#define lpfc_mbx_rq_ftr_rsp_ifip_SHIFT 7
3109#define lpfc_mbx_rq_ftr_rsp_ifip_MASK 0x00000001
3110#define lpfc_mbx_rq_ftr_rsp_ifip_WORD word3
3111#define lpfc_mbx_rq_ftr_rsp_mrqp_SHIFT 16
3112#define lpfc_mbx_rq_ftr_rsp_mrqp_MASK 0x00000001
3113#define lpfc_mbx_rq_ftr_rsp_mrqp_WORD word3
3114#define lpfc_mbx_rq_ftr_rsp_ashdr_SHIFT 17
3115#define lpfc_mbx_rq_ftr_rsp_ashdr_MASK 0x00000001
3116#define lpfc_mbx_rq_ftr_rsp_ashdr_WORD word3
3117};
3118
3119struct lpfc_mbx_memory_dump_type3 {
3120 uint32_t word1;
3121#define lpfc_mbx_memory_dump_type3_type_SHIFT 0
3122#define lpfc_mbx_memory_dump_type3_type_MASK 0x0000000f
3123#define lpfc_mbx_memory_dump_type3_type_WORD word1
3124#define lpfc_mbx_memory_dump_type3_link_SHIFT 24
3125#define lpfc_mbx_memory_dump_type3_link_MASK 0x000000ff
3126#define lpfc_mbx_memory_dump_type3_link_WORD word1
3127 uint32_t word2;
3128#define lpfc_mbx_memory_dump_type3_page_no_SHIFT 0
3129#define lpfc_mbx_memory_dump_type3_page_no_MASK 0x0000ffff
3130#define lpfc_mbx_memory_dump_type3_page_no_WORD word2
3131#define lpfc_mbx_memory_dump_type3_offset_SHIFT 16
3132#define lpfc_mbx_memory_dump_type3_offset_MASK 0x0000ffff
3133#define lpfc_mbx_memory_dump_type3_offset_WORD word2
3134 uint32_t word3;
3135#define lpfc_mbx_memory_dump_type3_length_SHIFT 0
3136#define lpfc_mbx_memory_dump_type3_length_MASK 0x00ffffff
3137#define lpfc_mbx_memory_dump_type3_length_WORD word3
3138 uint32_t addr_lo;
3139 uint32_t addr_hi;
3140 uint32_t return_len;
3141};
3142
3143#define DMP_PAGE_A0 0xa0
3144#define DMP_PAGE_A2 0xa2
3145#define DMP_SFF_PAGE_A0_SIZE 256
3146#define DMP_SFF_PAGE_A2_SIZE 256
3147
3148#define SFP_WAVELENGTH_LC1310 1310
3149#define SFP_WAVELENGTH_LL1550 1550
3150
3151
3152/*
3153 * * SFF-8472 TABLE 3.4
3154 * */
3155#define SFF_PG0_CONNECTOR_UNKNOWN 0x00 /* Unknown */
3156#define SFF_PG0_CONNECTOR_SC 0x01 /* SC */
3157#define SFF_PG0_CONNECTOR_FC_COPPER1 0x02 /* FC style 1 copper connector */
3158#define SFF_PG0_CONNECTOR_FC_COPPER2 0x03 /* FC style 2 copper connector */
3159#define SFF_PG0_CONNECTOR_BNC 0x04 /* BNC / TNC */
3160#define SFF_PG0_CONNECTOR__FC_COAX 0x05 /* FC coaxial headers */
3161#define SFF_PG0_CONNECTOR_FIBERJACK 0x06 /* FiberJack */
3162#define SFF_PG0_CONNECTOR_LC 0x07 /* LC */
3163#define SFF_PG0_CONNECTOR_MT 0x08 /* MT - RJ */
3164#define SFF_PG0_CONNECTOR_MU 0x09 /* MU */
3165#define SFF_PG0_CONNECTOR_SF 0x0A /* SG */
3166#define SFF_PG0_CONNECTOR_OPTICAL_PIGTAIL 0x0B /* Optical pigtail */
3167#define SFF_PG0_CONNECTOR_OPTICAL_PARALLEL 0x0C /* MPO Parallel Optic */
3168#define SFF_PG0_CONNECTOR_HSSDC_II 0x20 /* HSSDC II */
3169#define SFF_PG0_CONNECTOR_COPPER_PIGTAIL 0x21 /* Copper pigtail */
3170#define SFF_PG0_CONNECTOR_RJ45 0x22 /* RJ45 */
3171
3172/* SFF-8472 Table 3.1 Diagnostics: Data Fields Address/Page A0 */
3173
3174#define SSF_IDENTIFIER 0
3175#define SSF_EXT_IDENTIFIER 1
3176#define SSF_CONNECTOR 2
3177#define SSF_TRANSCEIVER_CODE_B0 3
3178#define SSF_TRANSCEIVER_CODE_B1 4
3179#define SSF_TRANSCEIVER_CODE_B2 5
3180#define SSF_TRANSCEIVER_CODE_B3 6
3181#define SSF_TRANSCEIVER_CODE_B4 7
3182#define SSF_TRANSCEIVER_CODE_B5 8
3183#define SSF_TRANSCEIVER_CODE_B6 9
3184#define SSF_TRANSCEIVER_CODE_B7 10
3185#define SSF_ENCODING 11
3186#define SSF_BR_NOMINAL 12
3187#define SSF_RATE_IDENTIFIER 13
3188#define SSF_LENGTH_9UM_KM 14
3189#define SSF_LENGTH_9UM 15
3190#define SSF_LENGTH_50UM_OM2 16
3191#define SSF_LENGTH_62UM_OM1 17
3192#define SFF_LENGTH_COPPER 18
3193#define SSF_LENGTH_50UM_OM3 19
3194#define SSF_VENDOR_NAME 20
3195#define SSF_TRANSCEIVER2 36
3196#define SSF_VENDOR_OUI 37
3197#define SSF_VENDOR_PN 40
3198#define SSF_VENDOR_REV 56
3199#define SSF_WAVELENGTH_B1 60
3200#define SSF_WAVELENGTH_B0 61
3201#define SSF_CC_BASE 63
3202#define SSF_OPTIONS_B1 64
3203#define SSF_OPTIONS_B0 65
3204#define SSF_BR_MAX 66
3205#define SSF_BR_MIN 67
3206#define SSF_VENDOR_SN 68
3207#define SSF_DATE_CODE 84
3208#define SSF_MONITORING_TYPEDIAGNOSTIC 92
3209#define SSF_ENHANCED_OPTIONS 93
3210#define SFF_8472_COMPLIANCE 94
3211#define SSF_CC_EXT 95
3212#define SSF_A0_VENDOR_SPECIFIC 96
3213
3214/* SFF-8472 Table 3.1a Diagnostics: Data Fields Address/Page A2 */
3215
3216#define SSF_TEMP_HIGH_ALARM 0
3217#define SSF_TEMP_LOW_ALARM 2
3218#define SSF_TEMP_HIGH_WARNING 4
3219#define SSF_TEMP_LOW_WARNING 6
3220#define SSF_VOLTAGE_HIGH_ALARM 8
3221#define SSF_VOLTAGE_LOW_ALARM 10
3222#define SSF_VOLTAGE_HIGH_WARNING 12
3223#define SSF_VOLTAGE_LOW_WARNING 14
3224#define SSF_BIAS_HIGH_ALARM 16
3225#define SSF_BIAS_LOW_ALARM 18
3226#define SSF_BIAS_HIGH_WARNING 20
3227#define SSF_BIAS_LOW_WARNING 22
3228#define SSF_TXPOWER_HIGH_ALARM 24
3229#define SSF_TXPOWER_LOW_ALARM 26
3230#define SSF_TXPOWER_HIGH_WARNING 28
3231#define SSF_TXPOWER_LOW_WARNING 30
3232#define SSF_RXPOWER_HIGH_ALARM 32
3233#define SSF_RXPOWER_LOW_ALARM 34
3234#define SSF_RXPOWER_HIGH_WARNING 36
3235#define SSF_RXPOWER_LOW_WARNING 38
3236#define SSF_EXT_CAL_CONSTANTS 56
3237#define SSF_CC_DMI 95
3238#define SFF_TEMPERATURE_B1 96
3239#define SFF_TEMPERATURE_B0 97
3240#define SFF_VCC_B1 98
3241#define SFF_VCC_B0 99
3242#define SFF_TX_BIAS_CURRENT_B1 100
3243#define SFF_TX_BIAS_CURRENT_B0 101
3244#define SFF_TXPOWER_B1 102
3245#define SFF_TXPOWER_B0 103
3246#define SFF_RXPOWER_B1 104
3247#define SFF_RXPOWER_B0 105
3248#define SSF_STATUS_CONTROL 110
3249#define SSF_ALARM_FLAGS 112
3250#define SSF_WARNING_FLAGS 116
3251#define SSF_EXT_TATUS_CONTROL_B1 118
3252#define SSF_EXT_TATUS_CONTROL_B0 119
3253#define SSF_A2_VENDOR_SPECIFIC 120
3254#define SSF_USER_EEPROM 128
3255#define SSF_VENDOR_CONTROL 148
3256
3257
3258/*
3259 * Tranceiver codes Fibre Channel SFF-8472
3260 * Table 3.5.
3261 */
3262
3263struct sff_trasnceiver_codes_byte0 {
3264 uint8_t inifiband:4;
3265 uint8_t teng_ethernet:4;
3266};
3267
3268struct sff_trasnceiver_codes_byte1 {
3269 uint8_t sonet:6;
3270 uint8_t escon:2;
3271};
3272
3273struct sff_trasnceiver_codes_byte2 {
3274 uint8_t soNet:8;
3275};
3276
3277struct sff_trasnceiver_codes_byte3 {
3278 uint8_t ethernet:8;
3279};
3280
3281struct sff_trasnceiver_codes_byte4 {
3282 uint8_t fc_el_lo:1;
3283 uint8_t fc_lw_laser:1;
3284 uint8_t fc_sw_laser:1;
3285 uint8_t fc_md_distance:1;
3286 uint8_t fc_lg_distance:1;
3287 uint8_t fc_int_distance:1;
3288 uint8_t fc_short_distance:1;
3289 uint8_t fc_vld_distance:1;
3290};
3291
3292struct sff_trasnceiver_codes_byte5 {
3293 uint8_t reserved1:1;
3294 uint8_t reserved2:1;
3295 uint8_t fc_sfp_active:1; /* Active cable */
3296 uint8_t fc_sfp_passive:1; /* Passive cable */
3297 uint8_t fc_lw_laser:1; /* Longwave laser */
3298 uint8_t fc_sw_laser_sl:1;
3299 uint8_t fc_sw_laser_sn:1;
3300 uint8_t fc_el_hi:1; /* Electrical enclosure high bit */
3301};
3302
3303struct sff_trasnceiver_codes_byte6 {
3304 uint8_t fc_tm_sm:1; /* Single Mode */
3305 uint8_t reserved:1;
3306 uint8_t fc_tm_m6:1; /* Multimode, 62.5um (M6) */
3307 uint8_t fc_tm_tv:1; /* Video Coax (TV) */
3308 uint8_t fc_tm_mi:1; /* Miniature Coax (MI) */
3309 uint8_t fc_tm_tp:1; /* Twisted Pair (TP) */
3310 uint8_t fc_tm_tw:1; /* Twin Axial Pair */
3311};
3312
3313struct sff_trasnceiver_codes_byte7 {
3314 uint8_t fc_sp_100MB:1; /* 100 MB/sec */
3315 uint8_t speed_chk_ecc:1;
3316 uint8_t fc_sp_200mb:1; /* 200 MB/sec */
3317 uint8_t fc_sp_3200MB:1; /* 3200 MB/sec */
3318 uint8_t fc_sp_400MB:1; /* 400 MB/sec */
3319 uint8_t fc_sp_1600MB:1; /* 1600 MB/sec */
3320 uint8_t fc_sp_800MB:1; /* 800 MB/sec */
3321 uint8_t fc_sp_1200MB:1; /* 1200 MB/sec */
3322};
3323
3324/* User writable non-volatile memory, SFF-8472 Table 3.20 */
3325struct user_eeprom {
3326 uint8_t vendor_name[16];
3327 uint8_t vendor_oui[3];
3328 uint8_t vendor_pn[816];
3329 uint8_t vendor_rev[4];
3330 uint8_t vendor_sn[16];
3331 uint8_t datecode[6];
3332 uint8_t lot_code[2];
3333 uint8_t reserved191[57];
3334};
3335
3336#define SLI4_PAGE_ALIGN(addr) (((addr)+((SLI4_PAGE_SIZE)-1)) \
3337 &(~((SLI4_PAGE_SIZE)-1)))
3338
3339struct lpfc_sli4_parameters {
3340 uint32_t word0;
3341#define cfg_prot_type_SHIFT 0
3342#define cfg_prot_type_MASK 0x000000FF
3343#define cfg_prot_type_WORD word0
3344 uint32_t word1;
3345#define cfg_ft_SHIFT 0
3346#define cfg_ft_MASK 0x00000001
3347#define cfg_ft_WORD word1
3348#define cfg_sli_rev_SHIFT 4
3349#define cfg_sli_rev_MASK 0x0000000f
3350#define cfg_sli_rev_WORD word1
3351#define cfg_sli_family_SHIFT 8
3352#define cfg_sli_family_MASK 0x0000000f
3353#define cfg_sli_family_WORD word1
3354#define cfg_if_type_SHIFT 12
3355#define cfg_if_type_MASK 0x0000000f
3356#define cfg_if_type_WORD word1
3357#define cfg_sli_hint_1_SHIFT 16
3358#define cfg_sli_hint_1_MASK 0x000000ff
3359#define cfg_sli_hint_1_WORD word1
3360#define cfg_sli_hint_2_SHIFT 24
3361#define cfg_sli_hint_2_MASK 0x0000001f
3362#define cfg_sli_hint_2_WORD word1
3363 uint32_t word2;
3364#define cfg_eqav_SHIFT 31
3365#define cfg_eqav_MASK 0x00000001
3366#define cfg_eqav_WORD word2
3367 uint32_t word3;
3368 uint32_t word4;
3369#define cfg_cqv_SHIFT 14
3370#define cfg_cqv_MASK 0x00000003
3371#define cfg_cqv_WORD word4
3372#define cfg_cqpsize_SHIFT 16
3373#define cfg_cqpsize_MASK 0x000000ff
3374#define cfg_cqpsize_WORD word4
3375#define cfg_cqav_SHIFT 31
3376#define cfg_cqav_MASK 0x00000001
3377#define cfg_cqav_WORD word4
3378 uint32_t word5;
3379 uint32_t word6;
3380#define cfg_mqv_SHIFT 14
3381#define cfg_mqv_MASK 0x00000003
3382#define cfg_mqv_WORD word6
3383 uint32_t word7;
3384 uint32_t word8;
3385#define cfg_wqpcnt_SHIFT 0
3386#define cfg_wqpcnt_MASK 0x0000000f
3387#define cfg_wqpcnt_WORD word8
3388#define cfg_wqsize_SHIFT 8
3389#define cfg_wqsize_MASK 0x0000000f
3390#define cfg_wqsize_WORD word8
3391#define cfg_wqv_SHIFT 14
3392#define cfg_wqv_MASK 0x00000003
3393#define cfg_wqv_WORD word8
3394#define cfg_wqpsize_SHIFT 16
3395#define cfg_wqpsize_MASK 0x000000ff
3396#define cfg_wqpsize_WORD word8
3397 uint32_t word9;
3398 uint32_t word10;
3399#define cfg_rqv_SHIFT 14
3400#define cfg_rqv_MASK 0x00000003
3401#define cfg_rqv_WORD word10
3402 uint32_t word11;
3403#define cfg_rq_db_window_SHIFT 28
3404#define cfg_rq_db_window_MASK 0x0000000f
3405#define cfg_rq_db_window_WORD word11
3406 uint32_t word12;
3407#define cfg_fcoe_SHIFT 0
3408#define cfg_fcoe_MASK 0x00000001
3409#define cfg_fcoe_WORD word12
3410#define cfg_ext_SHIFT 1
3411#define cfg_ext_MASK 0x00000001
3412#define cfg_ext_WORD word12
3413#define cfg_hdrr_SHIFT 2
3414#define cfg_hdrr_MASK 0x00000001
3415#define cfg_hdrr_WORD word12
3416#define cfg_phwq_SHIFT 15
3417#define cfg_phwq_MASK 0x00000001
3418#define cfg_phwq_WORD word12
3419#define cfg_oas_SHIFT 25
3420#define cfg_oas_MASK 0x00000001
3421#define cfg_oas_WORD word12
3422#define cfg_loopbk_scope_SHIFT 28
3423#define cfg_loopbk_scope_MASK 0x0000000f
3424#define cfg_loopbk_scope_WORD word12
3425 uint32_t sge_supp_len;
3426 uint32_t word14;
3427#define cfg_sgl_page_cnt_SHIFT 0
3428#define cfg_sgl_page_cnt_MASK 0x0000000f
3429#define cfg_sgl_page_cnt_WORD word14
3430#define cfg_sgl_page_size_SHIFT 8
3431#define cfg_sgl_page_size_MASK 0x000000ff
3432#define cfg_sgl_page_size_WORD word14
3433#define cfg_sgl_pp_align_SHIFT 16
3434#define cfg_sgl_pp_align_MASK 0x000000ff
3435#define cfg_sgl_pp_align_WORD word14
3436 uint32_t word15;
3437 uint32_t word16;
3438 uint32_t word17;
3439 uint32_t word18;
3440 uint32_t word19;
3441#define cfg_ext_embed_cb_SHIFT 0
3442#define cfg_ext_embed_cb_MASK 0x00000001
3443#define cfg_ext_embed_cb_WORD word19
3444#define cfg_mds_diags_SHIFT 1
3445#define cfg_mds_diags_MASK 0x00000001
3446#define cfg_mds_diags_WORD word19
3447#define cfg_nvme_SHIFT 3
3448#define cfg_nvme_MASK 0x00000001
3449#define cfg_nvme_WORD word19
3450#define cfg_xib_SHIFT 4
3451#define cfg_xib_MASK 0x00000001
3452#define cfg_xib_WORD word19
3453#define cfg_xpsgl_SHIFT 6
3454#define cfg_xpsgl_MASK 0x00000001
3455#define cfg_xpsgl_WORD word19
3456#define cfg_eqdr_SHIFT 8
3457#define cfg_eqdr_MASK 0x00000001
3458#define cfg_eqdr_WORD word19
3459#define cfg_nosr_SHIFT 9
3460#define cfg_nosr_MASK 0x00000001
3461#define cfg_nosr_WORD word19
3462#define cfg_bv1s_SHIFT 10
3463#define cfg_bv1s_MASK 0x00000001
3464#define cfg_bv1s_WORD word19
3465
3466#define cfg_nsler_SHIFT 12
3467#define cfg_nsler_MASK 0x00000001
3468#define cfg_nsler_WORD word19
3469#define cfg_pvl_SHIFT 13
3470#define cfg_pvl_MASK 0x00000001
3471#define cfg_pvl_WORD word19
3472
3473 uint32_t word20;
3474#define cfg_max_tow_xri_SHIFT 0
3475#define cfg_max_tow_xri_MASK 0x0000ffff
3476#define cfg_max_tow_xri_WORD word20
3477
3478 uint32_t word21;
3479#define cfg_mi_ver_SHIFT 0
3480#define cfg_mi_ver_MASK 0x0000ffff
3481#define cfg_mi_ver_WORD word21
3482#define cfg_cmf_SHIFT 24
3483#define cfg_cmf_MASK 0x000000ff
3484#define cfg_cmf_WORD word21
3485
3486 uint32_t mib_size;
3487 uint32_t word23; /* RESERVED */
3488
3489 uint32_t word24;
3490#define cfg_frag_field_offset_SHIFT 0
3491#define cfg_frag_field_offset_MASK 0x0000ffff
3492#define cfg_frag_field_offset_WORD word24
3493
3494#define cfg_frag_field_size_SHIFT 16
3495#define cfg_frag_field_size_MASK 0x0000ffff
3496#define cfg_frag_field_size_WORD word24
3497
3498 uint32_t word25;
3499#define cfg_sgl_field_offset_SHIFT 0
3500#define cfg_sgl_field_offset_MASK 0x0000ffff
3501#define cfg_sgl_field_offset_WORD word25
3502
3503#define cfg_sgl_field_size_SHIFT 16
3504#define cfg_sgl_field_size_MASK 0x0000ffff
3505#define cfg_sgl_field_size_WORD word25
3506
3507 uint32_t word26; /* Chain SGE initial value LOW */
3508 uint32_t word27; /* Chain SGE initial value HIGH */
3509#define LPFC_NODELAY_MAX_IO 32
3510};
3511
3512#define LPFC_SET_UE_RECOVERY 0x10
3513#define LPFC_SET_MDS_DIAGS 0x12
3514#define LPFC_SET_DUAL_DUMP 0x1e
3515#define LPFC_SET_CGN_SIGNAL 0x1f
3516#define LPFC_SET_ENABLE_MI 0x21
3517#define LPFC_SET_LD_SIGNAL 0x23
3518#define LPFC_SET_ENABLE_CMF 0x24
3519struct lpfc_mbx_set_feature {
3520 struct mbox_header header;
3521 uint32_t feature;
3522 uint32_t param_len;
3523 uint32_t word6;
3524#define lpfc_mbx_set_feature_UER_SHIFT 0
3525#define lpfc_mbx_set_feature_UER_MASK 0x00000001
3526#define lpfc_mbx_set_feature_UER_WORD word6
3527#define lpfc_mbx_set_feature_mds_SHIFT 2
3528#define lpfc_mbx_set_feature_mds_MASK 0x00000001
3529#define lpfc_mbx_set_feature_mds_WORD word6
3530#define lpfc_mbx_set_feature_mds_deep_loopbk_SHIFT 1
3531#define lpfc_mbx_set_feature_mds_deep_loopbk_MASK 0x00000001
3532#define lpfc_mbx_set_feature_mds_deep_loopbk_WORD word6
3533#define lpfc_mbx_set_feature_CGN_warn_freq_SHIFT 0
3534#define lpfc_mbx_set_feature_CGN_warn_freq_MASK 0x0000ffff
3535#define lpfc_mbx_set_feature_CGN_warn_freq_WORD word6
3536#define lpfc_mbx_set_feature_dd_SHIFT 0
3537#define lpfc_mbx_set_feature_dd_MASK 0x00000001
3538#define lpfc_mbx_set_feature_dd_WORD word6
3539#define lpfc_mbx_set_feature_ddquery_SHIFT 1
3540#define lpfc_mbx_set_feature_ddquery_MASK 0x00000001
3541#define lpfc_mbx_set_feature_ddquery_WORD word6
3542#define LPFC_DISABLE_DUAL_DUMP 0
3543#define LPFC_ENABLE_DUAL_DUMP 1
3544#define LPFC_QUERY_OP_DUAL_DUMP 2
3545#define lpfc_mbx_set_feature_cmf_SHIFT 0
3546#define lpfc_mbx_set_feature_cmf_MASK 0x00000001
3547#define lpfc_mbx_set_feature_cmf_WORD word6
3548#define lpfc_mbx_set_feature_lds_qry_SHIFT 0
3549#define lpfc_mbx_set_feature_lds_qry_MASK 0x00000001
3550#define lpfc_mbx_set_feature_lds_qry_WORD word6
3551#define LPFC_QUERY_LDS_OP 1
3552#define lpfc_mbx_set_feature_mi_SHIFT 0
3553#define lpfc_mbx_set_feature_mi_MASK 0x0000ffff
3554#define lpfc_mbx_set_feature_mi_WORD word6
3555#define lpfc_mbx_set_feature_milunq_SHIFT 16
3556#define lpfc_mbx_set_feature_milunq_MASK 0x0000ffff
3557#define lpfc_mbx_set_feature_milunq_WORD word6
3558 u32 word7;
3559#define lpfc_mbx_set_feature_UERP_SHIFT 0
3560#define lpfc_mbx_set_feature_UERP_MASK 0x0000ffff
3561#define lpfc_mbx_set_feature_UERP_WORD word7
3562#define lpfc_mbx_set_feature_UESR_SHIFT 16
3563#define lpfc_mbx_set_feature_UESR_MASK 0x0000ffff
3564#define lpfc_mbx_set_feature_UESR_WORD word7
3565#define lpfc_mbx_set_feature_CGN_alarm_freq_SHIFT 0
3566#define lpfc_mbx_set_feature_CGN_alarm_freq_MASK 0x0000ffff
3567#define lpfc_mbx_set_feature_CGN_alarm_freq_WORD word7
3568 u32 word8;
3569#define lpfc_mbx_set_feature_CGN_acqe_freq_SHIFT 0
3570#define lpfc_mbx_set_feature_CGN_acqe_freq_MASK 0x000000ff
3571#define lpfc_mbx_set_feature_CGN_acqe_freq_WORD word8
3572 u32 word9;
3573 u32 word10;
3574};
3575
3576
3577#define LPFC_SET_HOST_OS_DRIVER_VERSION 0x2
3578#define LPFC_SET_HOST_DATE_TIME 0x4
3579
3580struct lpfc_mbx_set_host_date_time {
3581 uint32_t word6;
3582#define lpfc_mbx_set_host_month_WORD word6
3583#define lpfc_mbx_set_host_month_SHIFT 16
3584#define lpfc_mbx_set_host_month_MASK 0xFF
3585#define lpfc_mbx_set_host_day_WORD word6
3586#define lpfc_mbx_set_host_day_SHIFT 8
3587#define lpfc_mbx_set_host_day_MASK 0xFF
3588#define lpfc_mbx_set_host_year_WORD word6
3589#define lpfc_mbx_set_host_year_SHIFT 0
3590#define lpfc_mbx_set_host_year_MASK 0xFF
3591 uint32_t word7;
3592#define lpfc_mbx_set_host_hour_WORD word7
3593#define lpfc_mbx_set_host_hour_SHIFT 16
3594#define lpfc_mbx_set_host_hour_MASK 0xFF
3595#define lpfc_mbx_set_host_min_WORD word7
3596#define lpfc_mbx_set_host_min_SHIFT 8
3597#define lpfc_mbx_set_host_min_MASK 0xFF
3598#define lpfc_mbx_set_host_sec_WORD word7
3599#define lpfc_mbx_set_host_sec_SHIFT 0
3600#define lpfc_mbx_set_host_sec_MASK 0xFF
3601};
3602
3603struct lpfc_mbx_set_host_data {
3604#define LPFC_HOST_OS_DRIVER_VERSION_SIZE 48
3605 struct mbox_header header;
3606 uint32_t param_id;
3607 uint32_t param_len;
3608 union {
3609 uint8_t data[LPFC_HOST_OS_DRIVER_VERSION_SIZE];
3610 struct lpfc_mbx_set_host_date_time tm;
3611 } un;
3612};
3613
3614struct lpfc_mbx_set_trunk_mode {
3615 struct mbox_header header;
3616 uint32_t word0;
3617#define lpfc_mbx_set_trunk_mode_WORD word0
3618#define lpfc_mbx_set_trunk_mode_SHIFT 0
3619#define lpfc_mbx_set_trunk_mode_MASK 0xFF
3620 uint32_t word1;
3621 uint32_t word2;
3622};
3623
3624struct lpfc_mbx_get_sli4_parameters {
3625 struct mbox_header header;
3626 struct lpfc_sli4_parameters sli4_parameters;
3627};
3628
3629struct lpfc_mbx_reg_congestion_buf {
3630 struct mbox_header header;
3631 uint32_t word0;
3632#define lpfc_mbx_reg_cgn_buf_type_WORD word0
3633#define lpfc_mbx_reg_cgn_buf_type_SHIFT 0
3634#define lpfc_mbx_reg_cgn_buf_type_MASK 0xFF
3635#define lpfc_mbx_reg_cgn_buf_cnt_WORD word0
3636#define lpfc_mbx_reg_cgn_buf_cnt_SHIFT 16
3637#define lpfc_mbx_reg_cgn_buf_cnt_MASK 0xFF
3638 uint32_t word1;
3639 uint32_t length;
3640 uint32_t addr_lo;
3641 uint32_t addr_hi;
3642};
3643
3644struct lpfc_rscr_desc_generic {
3645#define LPFC_RSRC_DESC_WSIZE 22
3646 uint32_t desc[LPFC_RSRC_DESC_WSIZE];
3647};
3648
3649struct lpfc_rsrc_desc_pcie {
3650 uint32_t word0;
3651#define lpfc_rsrc_desc_pcie_type_SHIFT 0
3652#define lpfc_rsrc_desc_pcie_type_MASK 0x000000ff
3653#define lpfc_rsrc_desc_pcie_type_WORD word0
3654#define LPFC_RSRC_DESC_TYPE_PCIE 0x40
3655#define lpfc_rsrc_desc_pcie_length_SHIFT 8
3656#define lpfc_rsrc_desc_pcie_length_MASK 0x000000ff
3657#define lpfc_rsrc_desc_pcie_length_WORD word0
3658 uint32_t word1;
3659#define lpfc_rsrc_desc_pcie_pfnum_SHIFT 0
3660#define lpfc_rsrc_desc_pcie_pfnum_MASK 0x000000ff
3661#define lpfc_rsrc_desc_pcie_pfnum_WORD word1
3662 uint32_t reserved;
3663 uint32_t word3;
3664#define lpfc_rsrc_desc_pcie_sriov_sta_SHIFT 0
3665#define lpfc_rsrc_desc_pcie_sriov_sta_MASK 0x000000ff
3666#define lpfc_rsrc_desc_pcie_sriov_sta_WORD word3
3667#define lpfc_rsrc_desc_pcie_pf_sta_SHIFT 8
3668#define lpfc_rsrc_desc_pcie_pf_sta_MASK 0x000000ff
3669#define lpfc_rsrc_desc_pcie_pf_sta_WORD word3
3670#define lpfc_rsrc_desc_pcie_pf_type_SHIFT 16
3671#define lpfc_rsrc_desc_pcie_pf_type_MASK 0x000000ff
3672#define lpfc_rsrc_desc_pcie_pf_type_WORD word3
3673 uint32_t word4;
3674#define lpfc_rsrc_desc_pcie_nr_virtfn_SHIFT 0
3675#define lpfc_rsrc_desc_pcie_nr_virtfn_MASK 0x0000ffff
3676#define lpfc_rsrc_desc_pcie_nr_virtfn_WORD word4
3677};
3678
3679struct lpfc_rsrc_desc_fcfcoe {
3680 uint32_t word0;
3681#define lpfc_rsrc_desc_fcfcoe_type_SHIFT 0
3682#define lpfc_rsrc_desc_fcfcoe_type_MASK 0x000000ff
3683#define lpfc_rsrc_desc_fcfcoe_type_WORD word0
3684#define LPFC_RSRC_DESC_TYPE_FCFCOE 0x43
3685#define lpfc_rsrc_desc_fcfcoe_length_SHIFT 8
3686#define lpfc_rsrc_desc_fcfcoe_length_MASK 0x000000ff
3687#define lpfc_rsrc_desc_fcfcoe_length_WORD word0
3688#define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_RSVD 0
3689#define LPFC_RSRC_DESC_TYPE_FCFCOE_V0_LENGTH 72
3690#define LPFC_RSRC_DESC_TYPE_FCFCOE_V1_LENGTH 88
3691 uint32_t word1;
3692#define lpfc_rsrc_desc_fcfcoe_vfnum_SHIFT 0
3693#define lpfc_rsrc_desc_fcfcoe_vfnum_MASK 0x000000ff
3694#define lpfc_rsrc_desc_fcfcoe_vfnum_WORD word1
3695#define lpfc_rsrc_desc_fcfcoe_pfnum_SHIFT 16
3696#define lpfc_rsrc_desc_fcfcoe_pfnum_MASK 0x000007ff
3697#define lpfc_rsrc_desc_fcfcoe_pfnum_WORD word1
3698 uint32_t word2;
3699#define lpfc_rsrc_desc_fcfcoe_rpi_cnt_SHIFT 0
3700#define lpfc_rsrc_desc_fcfcoe_rpi_cnt_MASK 0x0000ffff
3701#define lpfc_rsrc_desc_fcfcoe_rpi_cnt_WORD word2
3702#define lpfc_rsrc_desc_fcfcoe_xri_cnt_SHIFT 16
3703#define lpfc_rsrc_desc_fcfcoe_xri_cnt_MASK 0x0000ffff
3704#define lpfc_rsrc_desc_fcfcoe_xri_cnt_WORD word2
3705 uint32_t word3;
3706#define lpfc_rsrc_desc_fcfcoe_wq_cnt_SHIFT 0
3707#define lpfc_rsrc_desc_fcfcoe_wq_cnt_MASK 0x0000ffff
3708#define lpfc_rsrc_desc_fcfcoe_wq_cnt_WORD word3
3709#define lpfc_rsrc_desc_fcfcoe_rq_cnt_SHIFT 16
3710#define lpfc_rsrc_desc_fcfcoe_rq_cnt_MASK 0x0000ffff
3711#define lpfc_rsrc_desc_fcfcoe_rq_cnt_WORD word3
3712 uint32_t word4;
3713#define lpfc_rsrc_desc_fcfcoe_cq_cnt_SHIFT 0
3714#define lpfc_rsrc_desc_fcfcoe_cq_cnt_MASK 0x0000ffff
3715#define lpfc_rsrc_desc_fcfcoe_cq_cnt_WORD word4
3716#define lpfc_rsrc_desc_fcfcoe_vpi_cnt_SHIFT 16
3717#define lpfc_rsrc_desc_fcfcoe_vpi_cnt_MASK 0x0000ffff
3718#define lpfc_rsrc_desc_fcfcoe_vpi_cnt_WORD word4
3719 uint32_t word5;
3720#define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_SHIFT 0
3721#define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_MASK 0x0000ffff
3722#define lpfc_rsrc_desc_fcfcoe_fcfi_cnt_WORD word5
3723#define lpfc_rsrc_desc_fcfcoe_vfi_cnt_SHIFT 16
3724#define lpfc_rsrc_desc_fcfcoe_vfi_cnt_MASK 0x0000ffff
3725#define lpfc_rsrc_desc_fcfcoe_vfi_cnt_WORD word5
3726 uint32_t word6;
3727 uint32_t word7;
3728 uint32_t word8;
3729 uint32_t word9;
3730 uint32_t word10;
3731 uint32_t word11;
3732 uint32_t word12;
3733 uint32_t word13;
3734#define lpfc_rsrc_desc_fcfcoe_lnk_nr_SHIFT 0
3735#define lpfc_rsrc_desc_fcfcoe_lnk_nr_MASK 0x0000003f
3736#define lpfc_rsrc_desc_fcfcoe_lnk_nr_WORD word13
3737#define lpfc_rsrc_desc_fcfcoe_lnk_tp_SHIFT 6
3738#define lpfc_rsrc_desc_fcfcoe_lnk_tp_MASK 0x00000003
3739#define lpfc_rsrc_desc_fcfcoe_lnk_tp_WORD word13
3740#define lpfc_rsrc_desc_fcfcoe_lmc_SHIFT 8
3741#define lpfc_rsrc_desc_fcfcoe_lmc_MASK 0x00000001
3742#define lpfc_rsrc_desc_fcfcoe_lmc_WORD word13
3743#define lpfc_rsrc_desc_fcfcoe_lld_SHIFT 9
3744#define lpfc_rsrc_desc_fcfcoe_lld_MASK 0x00000001
3745#define lpfc_rsrc_desc_fcfcoe_lld_WORD word13
3746#define lpfc_rsrc_desc_fcfcoe_eq_cnt_SHIFT 16
3747#define lpfc_rsrc_desc_fcfcoe_eq_cnt_MASK 0x0000ffff
3748#define lpfc_rsrc_desc_fcfcoe_eq_cnt_WORD word13
3749/* extended FC/FCoE Resource Descriptor when length = 88 bytes */
3750 uint32_t bw_min;
3751 uint32_t bw_max;
3752 uint32_t iops_min;
3753 uint32_t iops_max;
3754 uint32_t reserved[4];
3755};
3756
3757struct lpfc_func_cfg {
3758#define LPFC_RSRC_DESC_MAX_NUM 2
3759 uint32_t rsrc_desc_count;
3760 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM];
3761};
3762
3763struct lpfc_mbx_get_func_cfg {
3764 struct mbox_header header;
3765#define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0
3766#define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1
3767#define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2
3768 struct lpfc_func_cfg func_cfg;
3769};
3770
3771struct lpfc_prof_cfg {
3772#define LPFC_RSRC_DESC_MAX_NUM 2
3773 uint32_t rsrc_desc_count;
3774 struct lpfc_rscr_desc_generic desc[LPFC_RSRC_DESC_MAX_NUM];
3775};
3776
3777struct lpfc_mbx_get_prof_cfg {
3778 struct mbox_header header;
3779#define LPFC_CFG_TYPE_PERSISTENT_OVERRIDE 0x0
3780#define LPFC_CFG_TYPE_FACTURY_DEFAULT 0x1
3781#define LPFC_CFG_TYPE_CURRENT_ACTIVE 0x2
3782 union {
3783 struct {
3784 uint32_t word10;
3785#define lpfc_mbx_get_prof_cfg_prof_id_SHIFT 0
3786#define lpfc_mbx_get_prof_cfg_prof_id_MASK 0x000000ff
3787#define lpfc_mbx_get_prof_cfg_prof_id_WORD word10
3788#define lpfc_mbx_get_prof_cfg_prof_tp_SHIFT 8
3789#define lpfc_mbx_get_prof_cfg_prof_tp_MASK 0x00000003
3790#define lpfc_mbx_get_prof_cfg_prof_tp_WORD word10
3791 } request;
3792 struct {
3793 struct lpfc_prof_cfg prof_cfg;
3794 } response;
3795 } u;
3796};
3797
3798struct lpfc_controller_attribute {
3799 uint32_t version_string[8];
3800 uint32_t manufacturer_name[8];
3801 uint32_t rsvd16;
3802 uint32_t word17;
3803#define lpfc_cntl_attr_flash_id_SHIFT 16
3804#define lpfc_cntl_attr_flash_id_MASK 0x000000ff
3805#define lpfc_cntl_attr_flash_id_WORD word17
3806#define lpfc_cntl_attr_boot_enable_SHIFT 24
3807#define lpfc_cntl_attr_boot_enable_MASK 0x00000001
3808#define lpfc_cntl_attr_boot_enable_WORD word17
3809 uint32_t rsvd18[2];
3810 uint32_t ncsi_ver_str[3];
3811 uint32_t rsvd23;
3812 uint32_t model_number[8];
3813 uint32_t description[16];
3814 uint32_t serial_number[8];
3815 uint32_t ipl_name[5];
3816 uint32_t rsvd61[3];
3817 uint32_t fw_ver_str[8];
3818 uint32_t bios_ver_str[8];
3819 uint32_t redboot_ver_str[8];
3820 uint32_t driver_ver_str[8];
3821 uint32_t flash_fw_ver_str[8];
3822 uint32_t functionality;
3823 uint32_t word105;
3824#define lpfc_cntl_attr_asic_rev_SHIFT 16
3825#define lpfc_cntl_attr_asic_rev_MASK 0x000000ff
3826#define lpfc_cntl_attr_asic_rev_WORD word105
3827 uint32_t rsvd106[3];
3828 uint32_t word109;
3829#define lpfc_cntl_attr_hba_port_cnt_SHIFT 24
3830#define lpfc_cntl_attr_hba_port_cnt_MASK 0x000000ff
3831#define lpfc_cntl_attr_hba_port_cnt_WORD word109
3832 uint32_t rsvd110;
3833 uint32_t word111;
3834#define lpfc_cntl_attr_hba_status_SHIFT 8
3835#define lpfc_cntl_attr_hba_status_MASK 0x000000ff
3836#define lpfc_cntl_attr_hba_status_WORD word111
3837#define lpfc_cntl_attr_lnk_numb_SHIFT 24
3838#define lpfc_cntl_attr_lnk_numb_MASK 0x0000003f
3839#define lpfc_cntl_attr_lnk_numb_WORD word111
3840#define lpfc_cntl_attr_lnk_type_SHIFT 30
3841#define lpfc_cntl_attr_lnk_type_MASK 0x00000003
3842#define lpfc_cntl_attr_lnk_type_WORD word111
3843 uint32_t rsvd112[9];
3844 uint32_t word121;
3845#define lpfc_cntl_attr_asic_gen_SHIFT 8
3846#define lpfc_cntl_attr_asic_gen_MASK 0x000000ff
3847#define lpfc_cntl_attr_asic_gen_WORD word121
3848 uint32_t rsvd122[3];
3849 uint32_t word125;
3850#define lpfc_cntl_attr_pci_vendor_id_SHIFT 0
3851#define lpfc_cntl_attr_pci_vendor_id_MASK 0x0000ffff
3852#define lpfc_cntl_attr_pci_vendor_id_WORD word125
3853#define lpfc_cntl_attr_pci_device_id_SHIFT 16
3854#define lpfc_cntl_attr_pci_device_id_MASK 0x0000ffff
3855#define lpfc_cntl_attr_pci_device_id_WORD word125
3856 uint32_t word126;
3857#define lpfc_cntl_attr_pci_subvdr_id_SHIFT 0
3858#define lpfc_cntl_attr_pci_subvdr_id_MASK 0x0000ffff
3859#define lpfc_cntl_attr_pci_subvdr_id_WORD word126
3860#define lpfc_cntl_attr_pci_subsys_id_SHIFT 16
3861#define lpfc_cntl_attr_pci_subsys_id_MASK 0x0000ffff
3862#define lpfc_cntl_attr_pci_subsys_id_WORD word126
3863 uint32_t word127;
3864#define lpfc_cntl_attr_pci_bus_num_SHIFT 0
3865#define lpfc_cntl_attr_pci_bus_num_MASK 0x000000ff
3866#define lpfc_cntl_attr_pci_bus_num_WORD word127
3867#define lpfc_cntl_attr_pci_dev_num_SHIFT 8
3868#define lpfc_cntl_attr_pci_dev_num_MASK 0x000000ff
3869#define lpfc_cntl_attr_pci_dev_num_WORD word127
3870#define lpfc_cntl_attr_pci_fnc_num_SHIFT 16
3871#define lpfc_cntl_attr_pci_fnc_num_MASK 0x000000ff
3872#define lpfc_cntl_attr_pci_fnc_num_WORD word127
3873 uint32_t rsvd128[7];
3874};
3875
3876struct lpfc_mbx_get_cntl_attributes {
3877 union lpfc_sli4_cfg_shdr cfg_shdr;
3878 struct lpfc_controller_attribute cntl_attr;
3879};
3880
3881struct lpfc_mbx_get_port_name {
3882 struct mbox_header header;
3883 union {
3884 struct {
3885 uint32_t word4;
3886#define lpfc_mbx_get_port_name_lnk_type_SHIFT 0
3887#define lpfc_mbx_get_port_name_lnk_type_MASK 0x00000003
3888#define lpfc_mbx_get_port_name_lnk_type_WORD word4
3889 } request;
3890 struct {
3891 uint32_t word4;
3892#define lpfc_mbx_get_port_name_name0_SHIFT 0
3893#define lpfc_mbx_get_port_name_name0_MASK 0x000000FF
3894#define lpfc_mbx_get_port_name_name0_WORD word4
3895#define lpfc_mbx_get_port_name_name1_SHIFT 8
3896#define lpfc_mbx_get_port_name_name1_MASK 0x000000FF
3897#define lpfc_mbx_get_port_name_name1_WORD word4
3898#define lpfc_mbx_get_port_name_name2_SHIFT 16
3899#define lpfc_mbx_get_port_name_name2_MASK 0x000000FF
3900#define lpfc_mbx_get_port_name_name2_WORD word4
3901#define lpfc_mbx_get_port_name_name3_SHIFT 24
3902#define lpfc_mbx_get_port_name_name3_MASK 0x000000FF
3903#define lpfc_mbx_get_port_name_name3_WORD word4
3904#define LPFC_LINK_NUMBER_0 0
3905#define LPFC_LINK_NUMBER_1 1
3906#define LPFC_LINK_NUMBER_2 2
3907#define LPFC_LINK_NUMBER_3 3
3908 } response;
3909 } u;
3910};
3911
3912/* Mailbox Completion Queue Error Messages */
3913#define MB_CQE_STATUS_SUCCESS 0x0
3914#define MB_CQE_STATUS_INSUFFICIENT_PRIVILEGES 0x1
3915#define MB_CQE_STATUS_INVALID_PARAMETER 0x2
3916#define MB_CQE_STATUS_INSUFFICIENT_RESOURCES 0x3
3917#define MB_CEQ_STATUS_QUEUE_FLUSHING 0x4
3918#define MB_CQE_STATUS_DMA_FAILED 0x5
3919
3920
3921#define LPFC_MBX_WR_CONFIG_MAX_BDE 1
3922struct lpfc_mbx_wr_object {
3923 struct mbox_header header;
3924 union {
3925 struct {
3926 uint32_t word4;
3927#define lpfc_wr_object_eof_SHIFT 31
3928#define lpfc_wr_object_eof_MASK 0x00000001
3929#define lpfc_wr_object_eof_WORD word4
3930#define lpfc_wr_object_eas_SHIFT 29
3931#define lpfc_wr_object_eas_MASK 0x00000001
3932#define lpfc_wr_object_eas_WORD word4
3933#define lpfc_wr_object_write_length_SHIFT 0
3934#define lpfc_wr_object_write_length_MASK 0x00FFFFFF
3935#define lpfc_wr_object_write_length_WORD word4
3936 uint32_t write_offset;
3937 uint32_t object_name[LPFC_MBX_OBJECT_NAME_LEN_DW];
3938 uint32_t bde_count;
3939 struct ulp_bde64 bde[LPFC_MBX_WR_CONFIG_MAX_BDE];
3940 } request;
3941 struct {
3942 uint32_t actual_write_length;
3943 uint32_t word5;
3944#define lpfc_wr_object_change_status_SHIFT 0
3945#define lpfc_wr_object_change_status_MASK 0x000000FF
3946#define lpfc_wr_object_change_status_WORD word5
3947#define LPFC_CHANGE_STATUS_NO_RESET_NEEDED 0x00
3948#define LPFC_CHANGE_STATUS_PHYS_DEV_RESET 0x01
3949#define LPFC_CHANGE_STATUS_FW_RESET 0x02
3950#define LPFC_CHANGE_STATUS_PORT_MIGRATION 0x04
3951#define LPFC_CHANGE_STATUS_PCI_RESET 0x05
3952#define lpfc_wr_object_csf_SHIFT 8
3953#define lpfc_wr_object_csf_MASK 0x00000001
3954#define lpfc_wr_object_csf_WORD word5
3955 } response;
3956 } u;
3957};
3958
3959/* mailbox queue entry structure */
3960struct lpfc_mqe {
3961 uint32_t word0;
3962#define lpfc_mqe_status_SHIFT 16
3963#define lpfc_mqe_status_MASK 0x0000FFFF
3964#define lpfc_mqe_status_WORD word0
3965#define lpfc_mqe_command_SHIFT 8
3966#define lpfc_mqe_command_MASK 0x000000FF
3967#define lpfc_mqe_command_WORD word0
3968 union {
3969 uint32_t mb_words[LPFC_SLI4_MB_WORD_COUNT - 1];
3970 /* sli4 mailbox commands */
3971 struct lpfc_mbx_sli4_config sli4_config;
3972 struct lpfc_mbx_init_vfi init_vfi;
3973 struct lpfc_mbx_reg_vfi reg_vfi;
3974 struct lpfc_mbx_reg_vfi unreg_vfi;
3975 struct lpfc_mbx_init_vpi init_vpi;
3976 struct lpfc_mbx_resume_rpi resume_rpi;
3977 struct lpfc_mbx_read_fcf_tbl read_fcf_tbl;
3978 struct lpfc_mbx_add_fcf_tbl_entry add_fcf_entry;
3979 struct lpfc_mbx_del_fcf_tbl_entry del_fcf_entry;
3980 struct lpfc_mbx_redisc_fcf_tbl redisc_fcf_tbl;
3981 struct lpfc_mbx_reg_fcfi reg_fcfi;
3982 struct lpfc_mbx_reg_fcfi_mrq reg_fcfi_mrq;
3983 struct lpfc_mbx_unreg_fcfi unreg_fcfi;
3984 struct lpfc_mbx_mq_create mq_create;
3985 struct lpfc_mbx_mq_create_ext mq_create_ext;
3986 struct lpfc_mbx_read_object read_object;
3987 struct lpfc_mbx_eq_create eq_create;
3988 struct lpfc_mbx_modify_eq_delay eq_delay;
3989 struct lpfc_mbx_cq_create cq_create;
3990 struct lpfc_mbx_cq_create_set cq_create_set;
3991 struct lpfc_mbx_wq_create wq_create;
3992 struct lpfc_mbx_rq_create rq_create;
3993 struct lpfc_mbx_rq_create_v2 rq_create_v2;
3994 struct lpfc_mbx_mq_destroy mq_destroy;
3995 struct lpfc_mbx_eq_destroy eq_destroy;
3996 struct lpfc_mbx_cq_destroy cq_destroy;
3997 struct lpfc_mbx_wq_destroy wq_destroy;
3998 struct lpfc_mbx_rq_destroy rq_destroy;
3999 struct lpfc_mbx_get_rsrc_extent_info rsrc_extent_info;
4000 struct lpfc_mbx_alloc_rsrc_extents alloc_rsrc_extents;
4001 struct lpfc_mbx_dealloc_rsrc_extents dealloc_rsrc_extents;
4002 struct lpfc_mbx_post_sgl_pages post_sgl_pages;
4003 struct lpfc_mbx_nembed_cmd nembed_cmd;
4004 struct lpfc_mbx_read_rev read_rev;
4005 struct lpfc_mbx_read_vpi read_vpi;
4006 struct lpfc_mbx_read_config rd_config;
4007 struct lpfc_mbx_request_features req_ftrs;
4008 struct lpfc_mbx_post_hdr_tmpl hdr_tmpl;
4009 struct lpfc_mbx_query_fw_config query_fw_cfg;
4010 struct lpfc_mbx_set_beacon_config beacon_config;
4011 struct lpfc_mbx_get_sli4_parameters get_sli4_parameters;
4012 struct lpfc_mbx_reg_congestion_buf reg_congestion_buf;
4013 struct lpfc_mbx_set_link_diag_state link_diag_state;
4014 struct lpfc_mbx_set_link_diag_loopback link_diag_loopback;
4015 struct lpfc_mbx_run_link_diag_test link_diag_test;
4016 struct lpfc_mbx_get_func_cfg get_func_cfg;
4017 struct lpfc_mbx_get_prof_cfg get_prof_cfg;
4018 struct lpfc_mbx_wr_object wr_object;
4019 struct lpfc_mbx_get_port_name get_port_name;
4020 struct lpfc_mbx_set_feature set_feature;
4021 struct lpfc_mbx_memory_dump_type3 mem_dump_type3;
4022 struct lpfc_mbx_set_host_data set_host_data;
4023 struct lpfc_mbx_set_trunk_mode set_trunk_mode;
4024 struct lpfc_mbx_nop nop;
4025 struct lpfc_mbx_set_ras_fwlog ras_fwlog;
4026 } un;
4027};
4028
4029struct lpfc_mcqe {
4030 uint32_t word0;
4031#define lpfc_mcqe_status_SHIFT 0
4032#define lpfc_mcqe_status_MASK 0x0000FFFF
4033#define lpfc_mcqe_status_WORD word0
4034#define lpfc_mcqe_ext_status_SHIFT 16
4035#define lpfc_mcqe_ext_status_MASK 0x0000FFFF
4036#define lpfc_mcqe_ext_status_WORD word0
4037 uint32_t mcqe_tag0;
4038 uint32_t mcqe_tag1;
4039 uint32_t trailer;
4040#define lpfc_trailer_valid_SHIFT 31
4041#define lpfc_trailer_valid_MASK 0x00000001
4042#define lpfc_trailer_valid_WORD trailer
4043#define lpfc_trailer_async_SHIFT 30
4044#define lpfc_trailer_async_MASK 0x00000001
4045#define lpfc_trailer_async_WORD trailer
4046#define lpfc_trailer_hpi_SHIFT 29
4047#define lpfc_trailer_hpi_MASK 0x00000001
4048#define lpfc_trailer_hpi_WORD trailer
4049#define lpfc_trailer_completed_SHIFT 28
4050#define lpfc_trailer_completed_MASK 0x00000001
4051#define lpfc_trailer_completed_WORD trailer
4052#define lpfc_trailer_consumed_SHIFT 27
4053#define lpfc_trailer_consumed_MASK 0x00000001
4054#define lpfc_trailer_consumed_WORD trailer
4055#define lpfc_trailer_type_SHIFT 16
4056#define lpfc_trailer_type_MASK 0x000000FF
4057#define lpfc_trailer_type_WORD trailer
4058#define lpfc_trailer_code_SHIFT 8
4059#define lpfc_trailer_code_MASK 0x000000FF
4060#define lpfc_trailer_code_WORD trailer
4061#define LPFC_TRAILER_CODE_LINK 0x1
4062#define LPFC_TRAILER_CODE_FCOE 0x2
4063#define LPFC_TRAILER_CODE_DCBX 0x3
4064#define LPFC_TRAILER_CODE_GRP5 0x5
4065#define LPFC_TRAILER_CODE_FC 0x10
4066#define LPFC_TRAILER_CODE_SLI 0x11
4067};
4068
4069struct lpfc_acqe_link {
4070 uint32_t word0;
4071#define lpfc_acqe_link_speed_SHIFT 24
4072#define lpfc_acqe_link_speed_MASK 0x000000FF
4073#define lpfc_acqe_link_speed_WORD word0
4074#define LPFC_ASYNC_LINK_SPEED_ZERO 0x0
4075#define LPFC_ASYNC_LINK_SPEED_10MBPS 0x1
4076#define LPFC_ASYNC_LINK_SPEED_100MBPS 0x2
4077#define LPFC_ASYNC_LINK_SPEED_1GBPS 0x3
4078#define LPFC_ASYNC_LINK_SPEED_10GBPS 0x4
4079#define LPFC_ASYNC_LINK_SPEED_20GBPS 0x5
4080#define LPFC_ASYNC_LINK_SPEED_25GBPS 0x6
4081#define LPFC_ASYNC_LINK_SPEED_40GBPS 0x7
4082#define LPFC_ASYNC_LINK_SPEED_100GBPS 0x8
4083#define lpfc_acqe_link_duplex_SHIFT 16
4084#define lpfc_acqe_link_duplex_MASK 0x000000FF
4085#define lpfc_acqe_link_duplex_WORD word0
4086#define LPFC_ASYNC_LINK_DUPLEX_NONE 0x0
4087#define LPFC_ASYNC_LINK_DUPLEX_HALF 0x1
4088#define LPFC_ASYNC_LINK_DUPLEX_FULL 0x2
4089#define lpfc_acqe_link_status_SHIFT 8
4090#define lpfc_acqe_link_status_MASK 0x000000FF
4091#define lpfc_acqe_link_status_WORD word0
4092#define LPFC_ASYNC_LINK_STATUS_DOWN 0x0
4093#define LPFC_ASYNC_LINK_STATUS_UP 0x1
4094#define LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN 0x2
4095#define LPFC_ASYNC_LINK_STATUS_LOGICAL_UP 0x3
4096#define lpfc_acqe_link_type_SHIFT 6
4097#define lpfc_acqe_link_type_MASK 0x00000003
4098#define lpfc_acqe_link_type_WORD word0
4099#define lpfc_acqe_link_number_SHIFT 0
4100#define lpfc_acqe_link_number_MASK 0x0000003F
4101#define lpfc_acqe_link_number_WORD word0
4102 uint32_t word1;
4103#define lpfc_acqe_link_fault_SHIFT 0
4104#define lpfc_acqe_link_fault_MASK 0x000000FF
4105#define lpfc_acqe_link_fault_WORD word1
4106#define LPFC_ASYNC_LINK_FAULT_NONE 0x0
4107#define LPFC_ASYNC_LINK_FAULT_LOCAL 0x1
4108#define LPFC_ASYNC_LINK_FAULT_REMOTE 0x2
4109#define LPFC_ASYNC_LINK_FAULT_LR_LRR 0x3
4110#define lpfc_acqe_logical_link_speed_SHIFT 16
4111#define lpfc_acqe_logical_link_speed_MASK 0x0000FFFF
4112#define lpfc_acqe_logical_link_speed_WORD word1
4113 uint32_t event_tag;
4114 uint32_t trailer;
4115#define LPFC_LINK_EVENT_TYPE_PHYSICAL 0x0
4116#define LPFC_LINK_EVENT_TYPE_VIRTUAL 0x1
4117};
4118
4119struct lpfc_acqe_fip {
4120 uint32_t index;
4121 uint32_t word1;
4122#define lpfc_acqe_fip_fcf_count_SHIFT 0
4123#define lpfc_acqe_fip_fcf_count_MASK 0x0000FFFF
4124#define lpfc_acqe_fip_fcf_count_WORD word1
4125#define lpfc_acqe_fip_event_type_SHIFT 16
4126#define lpfc_acqe_fip_event_type_MASK 0x0000FFFF
4127#define lpfc_acqe_fip_event_type_WORD word1
4128 uint32_t event_tag;
4129 uint32_t trailer;
4130#define LPFC_FIP_EVENT_TYPE_NEW_FCF 0x1
4131#define LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL 0x2
4132#define LPFC_FIP_EVENT_TYPE_FCF_DEAD 0x3
4133#define LPFC_FIP_EVENT_TYPE_CVL 0x4
4134#define LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD 0x5
4135};
4136
4137struct lpfc_acqe_dcbx {
4138 uint32_t tlv_ttl;
4139 uint32_t reserved;
4140 uint32_t event_tag;
4141 uint32_t trailer;
4142};
4143
4144struct lpfc_acqe_grp5 {
4145 uint32_t word0;
4146#define lpfc_acqe_grp5_type_SHIFT 6
4147#define lpfc_acqe_grp5_type_MASK 0x00000003
4148#define lpfc_acqe_grp5_type_WORD word0
4149#define lpfc_acqe_grp5_number_SHIFT 0
4150#define lpfc_acqe_grp5_number_MASK 0x0000003F
4151#define lpfc_acqe_grp5_number_WORD word0
4152 uint32_t word1;
4153#define lpfc_acqe_grp5_llink_spd_SHIFT 16
4154#define lpfc_acqe_grp5_llink_spd_MASK 0x0000FFFF
4155#define lpfc_acqe_grp5_llink_spd_WORD word1
4156 uint32_t event_tag;
4157 uint32_t trailer;
4158};
4159
4160extern const char *const trunk_errmsg[];
4161
4162struct lpfc_acqe_fc_la {
4163 uint32_t word0;
4164#define lpfc_acqe_fc_la_speed_SHIFT 24
4165#define lpfc_acqe_fc_la_speed_MASK 0x000000FF
4166#define lpfc_acqe_fc_la_speed_WORD word0
4167#define LPFC_FC_LA_SPEED_UNKNOWN 0x0
4168#define LPFC_FC_LA_SPEED_1G 0x1
4169#define LPFC_FC_LA_SPEED_2G 0x2
4170#define LPFC_FC_LA_SPEED_4G 0x4
4171#define LPFC_FC_LA_SPEED_8G 0x8
4172#define LPFC_FC_LA_SPEED_10G 0xA
4173#define LPFC_FC_LA_SPEED_16G 0x10
4174#define LPFC_FC_LA_SPEED_32G 0x20
4175#define LPFC_FC_LA_SPEED_64G 0x21
4176#define LPFC_FC_LA_SPEED_128G 0x22
4177#define LPFC_FC_LA_SPEED_256G 0x23
4178#define lpfc_acqe_fc_la_topology_SHIFT 16
4179#define lpfc_acqe_fc_la_topology_MASK 0x000000FF
4180#define lpfc_acqe_fc_la_topology_WORD word0
4181#define LPFC_FC_LA_TOP_UNKOWN 0x0
4182#define LPFC_FC_LA_TOP_P2P 0x1
4183#define LPFC_FC_LA_TOP_FCAL 0x2
4184#define LPFC_FC_LA_TOP_INTERNAL_LOOP 0x3
4185#define LPFC_FC_LA_TOP_SERDES_LOOP 0x4
4186#define lpfc_acqe_fc_la_att_type_SHIFT 8
4187#define lpfc_acqe_fc_la_att_type_MASK 0x000000FF
4188#define lpfc_acqe_fc_la_att_type_WORD word0
4189#define LPFC_FC_LA_TYPE_LINK_UP 0x1
4190#define LPFC_FC_LA_TYPE_LINK_DOWN 0x2
4191#define LPFC_FC_LA_TYPE_NO_HARD_ALPA 0x3
4192#define LPFC_FC_LA_TYPE_MDS_LINK_DOWN 0x4
4193#define LPFC_FC_LA_TYPE_MDS_LOOPBACK 0x5
4194#define LPFC_FC_LA_TYPE_UNEXP_WWPN 0x6
4195#define LPFC_FC_LA_TYPE_TRUNKING_EVENT 0x7
4196#define LPFC_FC_LA_TYPE_ACTIVATE_FAIL 0x8
4197#define LPFC_FC_LA_TYPE_LINK_RESET_PRTCL_EVT 0x9
4198#define lpfc_acqe_fc_la_port_type_SHIFT 6
4199#define lpfc_acqe_fc_la_port_type_MASK 0x00000003
4200#define lpfc_acqe_fc_la_port_type_WORD word0
4201#define LPFC_LINK_TYPE_ETHERNET 0x0
4202#define LPFC_LINK_TYPE_FC 0x1
4203#define lpfc_acqe_fc_la_port_number_SHIFT 0
4204#define lpfc_acqe_fc_la_port_number_MASK 0x0000003F
4205#define lpfc_acqe_fc_la_port_number_WORD word0
4206
4207/* Attention Type is 0x07 (Trunking Event) word0 */
4208#define lpfc_acqe_fc_la_trunk_link_status_port0_SHIFT 16
4209#define lpfc_acqe_fc_la_trunk_link_status_port0_MASK 0x0000001
4210#define lpfc_acqe_fc_la_trunk_link_status_port0_WORD word0
4211#define lpfc_acqe_fc_la_trunk_link_status_port1_SHIFT 17
4212#define lpfc_acqe_fc_la_trunk_link_status_port1_MASK 0x0000001
4213#define lpfc_acqe_fc_la_trunk_link_status_port1_WORD word0
4214#define lpfc_acqe_fc_la_trunk_link_status_port2_SHIFT 18
4215#define lpfc_acqe_fc_la_trunk_link_status_port2_MASK 0x0000001
4216#define lpfc_acqe_fc_la_trunk_link_status_port2_WORD word0
4217#define lpfc_acqe_fc_la_trunk_link_status_port3_SHIFT 19
4218#define lpfc_acqe_fc_la_trunk_link_status_port3_MASK 0x0000001
4219#define lpfc_acqe_fc_la_trunk_link_status_port3_WORD word0
4220#define lpfc_acqe_fc_la_trunk_config_port0_SHIFT 20
4221#define lpfc_acqe_fc_la_trunk_config_port0_MASK 0x0000001
4222#define lpfc_acqe_fc_la_trunk_config_port0_WORD word0
4223#define lpfc_acqe_fc_la_trunk_config_port1_SHIFT 21
4224#define lpfc_acqe_fc_la_trunk_config_port1_MASK 0x0000001
4225#define lpfc_acqe_fc_la_trunk_config_port1_WORD word0
4226#define lpfc_acqe_fc_la_trunk_config_port2_SHIFT 22
4227#define lpfc_acqe_fc_la_trunk_config_port2_MASK 0x0000001
4228#define lpfc_acqe_fc_la_trunk_config_port2_WORD word0
4229#define lpfc_acqe_fc_la_trunk_config_port3_SHIFT 23
4230#define lpfc_acqe_fc_la_trunk_config_port3_MASK 0x0000001
4231#define lpfc_acqe_fc_la_trunk_config_port3_WORD word0
4232 uint32_t word1;
4233#define lpfc_acqe_fc_la_llink_spd_SHIFT 16
4234#define lpfc_acqe_fc_la_llink_spd_MASK 0x0000FFFF
4235#define lpfc_acqe_fc_la_llink_spd_WORD word1
4236#define lpfc_acqe_fc_la_fault_SHIFT 0
4237#define lpfc_acqe_fc_la_fault_MASK 0x000000FF
4238#define lpfc_acqe_fc_la_fault_WORD word1
4239#define lpfc_acqe_fc_la_link_status_SHIFT 8
4240#define lpfc_acqe_fc_la_link_status_MASK 0x0000007F
4241#define lpfc_acqe_fc_la_link_status_WORD word1
4242#define lpfc_acqe_fc_la_trunk_fault_SHIFT 0
4243#define lpfc_acqe_fc_la_trunk_fault_MASK 0x0000000F
4244#define lpfc_acqe_fc_la_trunk_fault_WORD word1
4245#define lpfc_acqe_fc_la_trunk_linkmask_SHIFT 4
4246#define lpfc_acqe_fc_la_trunk_linkmask_MASK 0x000000F
4247#define lpfc_acqe_fc_la_trunk_linkmask_WORD word1
4248#define LPFC_FC_LA_FAULT_NONE 0x0
4249#define LPFC_FC_LA_FAULT_LOCAL 0x1
4250#define LPFC_FC_LA_FAULT_REMOTE 0x2
4251 uint32_t event_tag;
4252 uint32_t trailer;
4253#define LPFC_FC_LA_EVENT_TYPE_FC_LINK 0x1
4254#define LPFC_FC_LA_EVENT_TYPE_SHARED_LINK 0x2
4255};
4256
4257struct lpfc_acqe_misconfigured_event {
4258 struct {
4259 uint32_t word0;
4260#define lpfc_sli_misconfigured_port0_state_SHIFT 0
4261#define lpfc_sli_misconfigured_port0_state_MASK 0x000000FF
4262#define lpfc_sli_misconfigured_port0_state_WORD word0
4263#define lpfc_sli_misconfigured_port1_state_SHIFT 8
4264#define lpfc_sli_misconfigured_port1_state_MASK 0x000000FF
4265#define lpfc_sli_misconfigured_port1_state_WORD word0
4266#define lpfc_sli_misconfigured_port2_state_SHIFT 16
4267#define lpfc_sli_misconfigured_port2_state_MASK 0x000000FF
4268#define lpfc_sli_misconfigured_port2_state_WORD word0
4269#define lpfc_sli_misconfigured_port3_state_SHIFT 24
4270#define lpfc_sli_misconfigured_port3_state_MASK 0x000000FF
4271#define lpfc_sli_misconfigured_port3_state_WORD word0
4272 uint32_t word1;
4273#define lpfc_sli_misconfigured_port0_op_SHIFT 0
4274#define lpfc_sli_misconfigured_port0_op_MASK 0x00000001
4275#define lpfc_sli_misconfigured_port0_op_WORD word1
4276#define lpfc_sli_misconfigured_port0_severity_SHIFT 1
4277#define lpfc_sli_misconfigured_port0_severity_MASK 0x00000003
4278#define lpfc_sli_misconfigured_port0_severity_WORD word1
4279#define lpfc_sli_misconfigured_port1_op_SHIFT 8
4280#define lpfc_sli_misconfigured_port1_op_MASK 0x00000001
4281#define lpfc_sli_misconfigured_port1_op_WORD word1
4282#define lpfc_sli_misconfigured_port1_severity_SHIFT 9
4283#define lpfc_sli_misconfigured_port1_severity_MASK 0x00000003
4284#define lpfc_sli_misconfigured_port1_severity_WORD word1
4285#define lpfc_sli_misconfigured_port2_op_SHIFT 16
4286#define lpfc_sli_misconfigured_port2_op_MASK 0x00000001
4287#define lpfc_sli_misconfigured_port2_op_WORD word1
4288#define lpfc_sli_misconfigured_port2_severity_SHIFT 17
4289#define lpfc_sli_misconfigured_port2_severity_MASK 0x00000003
4290#define lpfc_sli_misconfigured_port2_severity_WORD word1
4291#define lpfc_sli_misconfigured_port3_op_SHIFT 24
4292#define lpfc_sli_misconfigured_port3_op_MASK 0x00000001
4293#define lpfc_sli_misconfigured_port3_op_WORD word1
4294#define lpfc_sli_misconfigured_port3_severity_SHIFT 25
4295#define lpfc_sli_misconfigured_port3_severity_MASK 0x00000003
4296#define lpfc_sli_misconfigured_port3_severity_WORD word1
4297 } theEvent;
4298#define LPFC_SLI_EVENT_STATUS_VALID 0x00
4299#define LPFC_SLI_EVENT_STATUS_NOT_PRESENT 0x01
4300#define LPFC_SLI_EVENT_STATUS_WRONG_TYPE 0x02
4301#define LPFC_SLI_EVENT_STATUS_UNSUPPORTED 0x03
4302#define LPFC_SLI_EVENT_STATUS_UNQUALIFIED 0x04
4303#define LPFC_SLI_EVENT_STATUS_UNCERTIFIED 0x05
4304};
4305
4306struct lpfc_acqe_cgn_signal {
4307 u32 word0;
4308#define lpfc_warn_acqe_SHIFT 0
4309#define lpfc_warn_acqe_MASK 0x7FFFFFFF
4310#define lpfc_warn_acqe_WORD word0
4311#define lpfc_imm_acqe_SHIFT 31
4312#define lpfc_imm_acqe_MASK 0x1
4313#define lpfc_imm_acqe_WORD word0
4314 u32 alarm_cnt;
4315 u32 word2;
4316 u32 trailer;
4317};
4318
4319struct lpfc_acqe_sli {
4320 uint32_t event_data1;
4321 uint32_t event_data2;
4322 uint32_t event_data3;
4323 uint32_t trailer;
4324#define LPFC_SLI_EVENT_TYPE_PORT_ERROR 0x1
4325#define LPFC_SLI_EVENT_TYPE_OVER_TEMP 0x2
4326#define LPFC_SLI_EVENT_TYPE_NORM_TEMP 0x3
4327#define LPFC_SLI_EVENT_TYPE_NVLOG_POST 0x4
4328#define LPFC_SLI_EVENT_TYPE_DIAG_DUMP 0x5
4329#define LPFC_SLI_EVENT_TYPE_MISCONFIGURED 0x9
4330#define LPFC_SLI_EVENT_TYPE_REMOTE_DPORT 0xA
4331#define LPFC_SLI_EVENT_TYPE_PORT_PARAMS_CHG 0xE
4332#define LPFC_SLI_EVENT_TYPE_MISCONF_FAWWN 0xF
4333#define LPFC_SLI_EVENT_TYPE_EEPROM_FAILURE 0x10
4334#define LPFC_SLI_EVENT_TYPE_CGN_SIGNAL 0x11
4335#define LPFC_SLI_EVENT_TYPE_RD_SIGNAL 0x12
4336#define LPFC_SLI_EVENT_TYPE_RESET_CM_STATS 0x13
4337};
4338
4339/*
4340 * Define the bootstrap mailbox (bmbx) region used to communicate
4341 * mailbox command between the host and port. The mailbox consists
4342 * of a payload area of 256 bytes and a completion queue of length
4343 * 16 bytes.
4344 */
4345struct lpfc_bmbx_create {
4346 struct lpfc_mqe mqe;
4347 struct lpfc_mcqe mcqe;
4348};
4349
4350#define SGL_ALIGN_SZ 64
4351#define SGL_PAGE_SIZE 4096
4352/* align SGL addr on a size boundary - adjust address up */
4353#define NO_XRI 0xffff
4354
4355struct wqe_common {
4356 uint32_t word6;
4357#define wqe_xri_tag_SHIFT 0
4358#define wqe_xri_tag_MASK 0x0000FFFF
4359#define wqe_xri_tag_WORD word6
4360#define wqe_ctxt_tag_SHIFT 16
4361#define wqe_ctxt_tag_MASK 0x0000FFFF
4362#define wqe_ctxt_tag_WORD word6
4363 uint32_t word7;
4364#define wqe_dif_SHIFT 0
4365#define wqe_dif_MASK 0x00000003
4366#define wqe_dif_WORD word7
4367#define LPFC_WQE_DIF_PASSTHRU 1
4368#define LPFC_WQE_DIF_STRIP 2
4369#define LPFC_WQE_DIF_INSERT 3
4370#define wqe_ct_SHIFT 2
4371#define wqe_ct_MASK 0x00000003
4372#define wqe_ct_WORD word7
4373#define wqe_status_SHIFT 4
4374#define wqe_status_MASK 0x0000000f
4375#define wqe_status_WORD word7
4376#define wqe_cmnd_SHIFT 8
4377#define wqe_cmnd_MASK 0x000000ff
4378#define wqe_cmnd_WORD word7
4379#define wqe_class_SHIFT 16
4380#define wqe_class_MASK 0x00000007
4381#define wqe_class_WORD word7
4382#define wqe_ar_SHIFT 19
4383#define wqe_ar_MASK 0x00000001
4384#define wqe_ar_WORD word7
4385#define wqe_ag_SHIFT wqe_ar_SHIFT
4386#define wqe_ag_MASK wqe_ar_MASK
4387#define wqe_ag_WORD wqe_ar_WORD
4388#define wqe_pu_SHIFT 20
4389#define wqe_pu_MASK 0x00000003
4390#define wqe_pu_WORD word7
4391#define wqe_erp_SHIFT 22
4392#define wqe_erp_MASK 0x00000001
4393#define wqe_erp_WORD word7
4394#define wqe_conf_SHIFT wqe_erp_SHIFT
4395#define wqe_conf_MASK wqe_erp_MASK
4396#define wqe_conf_WORD wqe_erp_WORD
4397#define wqe_lnk_SHIFT 23
4398#define wqe_lnk_MASK 0x00000001
4399#define wqe_lnk_WORD word7
4400#define wqe_tmo_SHIFT 24
4401#define wqe_tmo_MASK 0x000000ff
4402#define wqe_tmo_WORD word7
4403 uint32_t abort_tag; /* word 8 in WQE */
4404 uint32_t word9;
4405#define wqe_reqtag_SHIFT 0
4406#define wqe_reqtag_MASK 0x0000FFFF
4407#define wqe_reqtag_WORD word9
4408#define wqe_temp_rpi_SHIFT 16
4409#define wqe_temp_rpi_MASK 0x0000FFFF
4410#define wqe_temp_rpi_WORD word9
4411#define wqe_rcvoxid_SHIFT 16
4412#define wqe_rcvoxid_MASK 0x0000FFFF
4413#define wqe_rcvoxid_WORD word9
4414#define wqe_sof_SHIFT 24
4415#define wqe_sof_MASK 0x000000FF
4416#define wqe_sof_WORD word9
4417#define wqe_eof_SHIFT 16
4418#define wqe_eof_MASK 0x000000FF
4419#define wqe_eof_WORD word9
4420 uint32_t word10;
4421#define wqe_ebde_cnt_SHIFT 0
4422#define wqe_ebde_cnt_MASK 0x0000000f
4423#define wqe_ebde_cnt_WORD word10
4424#define wqe_xchg_SHIFT 4
4425#define wqe_xchg_MASK 0x00000001
4426#define wqe_xchg_WORD word10
4427#define LPFC_SCSI_XCHG 0x0
4428#define LPFC_NVME_XCHG 0x1
4429#define wqe_appid_SHIFT 5
4430#define wqe_appid_MASK 0x00000001
4431#define wqe_appid_WORD word10
4432#define wqe_oas_SHIFT 6
4433#define wqe_oas_MASK 0x00000001
4434#define wqe_oas_WORD word10
4435#define wqe_lenloc_SHIFT 7
4436#define wqe_lenloc_MASK 0x00000003
4437#define wqe_lenloc_WORD word10
4438#define LPFC_WQE_LENLOC_NONE 0
4439#define LPFC_WQE_LENLOC_WORD3 1
4440#define LPFC_WQE_LENLOC_WORD12 2
4441#define LPFC_WQE_LENLOC_WORD4 3
4442#define wqe_qosd_SHIFT 9
4443#define wqe_qosd_MASK 0x00000001
4444#define wqe_qosd_WORD word10
4445#define wqe_xbl_SHIFT 11
4446#define wqe_xbl_MASK 0x00000001
4447#define wqe_xbl_WORD word10
4448#define wqe_iod_SHIFT 13
4449#define wqe_iod_MASK 0x00000001
4450#define wqe_iod_WORD word10
4451#define LPFC_WQE_IOD_NONE 0
4452#define LPFC_WQE_IOD_WRITE 0
4453#define LPFC_WQE_IOD_READ 1
4454#define wqe_dbde_SHIFT 14
4455#define wqe_dbde_MASK 0x00000001
4456#define wqe_dbde_WORD word10
4457#define wqe_wqes_SHIFT 15
4458#define wqe_wqes_MASK 0x00000001
4459#define wqe_wqes_WORD word10
4460/* Note that this field overlaps above fields */
4461#define wqe_wqid_SHIFT 1
4462#define wqe_wqid_MASK 0x00007fff
4463#define wqe_wqid_WORD word10
4464#define wqe_pri_SHIFT 16
4465#define wqe_pri_MASK 0x00000007
4466#define wqe_pri_WORD word10
4467#define wqe_pv_SHIFT 19
4468#define wqe_pv_MASK 0x00000001
4469#define wqe_pv_WORD word10
4470#define wqe_xc_SHIFT 21
4471#define wqe_xc_MASK 0x00000001
4472#define wqe_xc_WORD word10
4473#define wqe_sr_SHIFT 22
4474#define wqe_sr_MASK 0x00000001
4475#define wqe_sr_WORD word10
4476#define wqe_ccpe_SHIFT 23
4477#define wqe_ccpe_MASK 0x00000001
4478#define wqe_ccpe_WORD word10
4479#define wqe_ccp_SHIFT 24
4480#define wqe_ccp_MASK 0x000000ff
4481#define wqe_ccp_WORD word10
4482 uint32_t word11;
4483#define wqe_cmd_type_SHIFT 0
4484#define wqe_cmd_type_MASK 0x0000000f
4485#define wqe_cmd_type_WORD word11
4486#define wqe_els_id_SHIFT 4
4487#define wqe_els_id_MASK 0x00000007
4488#define wqe_els_id_WORD word11
4489#define wqe_irsp_SHIFT 4
4490#define wqe_irsp_MASK 0x00000001
4491#define wqe_irsp_WORD word11
4492#define wqe_sup_SHIFT 6
4493#define wqe_sup_MASK 0x00000001
4494#define wqe_sup_WORD word11
4495#define wqe_ffrq_SHIFT 6
4496#define wqe_ffrq_MASK 0x00000001
4497#define wqe_ffrq_WORD word11
4498#define wqe_wqec_SHIFT 7
4499#define wqe_wqec_MASK 0x00000001
4500#define wqe_wqec_WORD word11
4501#define wqe_irsplen_SHIFT 8
4502#define wqe_irsplen_MASK 0x0000000f
4503#define wqe_irsplen_WORD word11
4504#define wqe_cqid_SHIFT 16
4505#define wqe_cqid_MASK 0x0000ffff
4506#define wqe_cqid_WORD word11
4507#define LPFC_WQE_CQ_ID_DEFAULT 0xffff
4508};
4509
4510struct wqe_did {
4511 uint32_t word5;
4512#define wqe_els_did_SHIFT 0
4513#define wqe_els_did_MASK 0x00FFFFFF
4514#define wqe_els_did_WORD word5
4515#define wqe_xmit_bls_pt_SHIFT 28
4516#define wqe_xmit_bls_pt_MASK 0x00000003
4517#define wqe_xmit_bls_pt_WORD word5
4518#define wqe_xmit_bls_ar_SHIFT 30
4519#define wqe_xmit_bls_ar_MASK 0x00000001
4520#define wqe_xmit_bls_ar_WORD word5
4521#define wqe_xmit_bls_xo_SHIFT 31
4522#define wqe_xmit_bls_xo_MASK 0x00000001
4523#define wqe_xmit_bls_xo_WORD word5
4524};
4525
4526struct lpfc_wqe_generic{
4527 struct ulp_bde64 bde;
4528 uint32_t word3;
4529 uint32_t word4;
4530 uint32_t word5;
4531 struct wqe_common wqe_com;
4532 uint32_t payload[4];
4533};
4534
4535enum els_request64_wqe_word11 {
4536 LPFC_ELS_ID_DEFAULT,
4537 LPFC_ELS_ID_LOGO,
4538 LPFC_ELS_ID_FDISC,
4539 LPFC_ELS_ID_FLOGI,
4540 LPFC_ELS_ID_PLOGI,
4541};
4542
4543struct els_request64_wqe {
4544 struct ulp_bde64 bde;
4545 uint32_t payload_len;
4546 uint32_t word4;
4547#define els_req64_sid_SHIFT 0
4548#define els_req64_sid_MASK 0x00FFFFFF
4549#define els_req64_sid_WORD word4
4550#define els_req64_sp_SHIFT 24
4551#define els_req64_sp_MASK 0x00000001
4552#define els_req64_sp_WORD word4
4553#define els_req64_vf_SHIFT 25
4554#define els_req64_vf_MASK 0x00000001
4555#define els_req64_vf_WORD word4
4556 struct wqe_did wqe_dest;
4557 struct wqe_common wqe_com; /* words 6-11 */
4558 uint32_t word12;
4559#define els_req64_vfid_SHIFT 1
4560#define els_req64_vfid_MASK 0x00000FFF
4561#define els_req64_vfid_WORD word12
4562#define els_req64_pri_SHIFT 13
4563#define els_req64_pri_MASK 0x00000007
4564#define els_req64_pri_WORD word12
4565 uint32_t word13;
4566#define els_req64_hopcnt_SHIFT 24
4567#define els_req64_hopcnt_MASK 0x000000ff
4568#define els_req64_hopcnt_WORD word13
4569 uint32_t word14;
4570 uint32_t max_response_payload_len;
4571};
4572
4573struct xmit_els_rsp64_wqe {
4574 struct ulp_bde64 bde;
4575 uint32_t response_payload_len;
4576 uint32_t word4;
4577#define els_rsp64_sid_SHIFT 0
4578#define els_rsp64_sid_MASK 0x00FFFFFF
4579#define els_rsp64_sid_WORD word4
4580#define els_rsp64_sp_SHIFT 24
4581#define els_rsp64_sp_MASK 0x00000001
4582#define els_rsp64_sp_WORD word4
4583 struct wqe_did wqe_dest;
4584 struct wqe_common wqe_com; /* words 6-11 */
4585 uint32_t word12;
4586#define wqe_rsp_temp_rpi_SHIFT 0
4587#define wqe_rsp_temp_rpi_MASK 0x0000FFFF
4588#define wqe_rsp_temp_rpi_WORD word12
4589 uint32_t rsvd_13_15[3];
4590};
4591
4592struct xmit_bls_rsp64_wqe {
4593 uint32_t payload0;
4594/* Payload0 for BA_ACC */
4595#define xmit_bls_rsp64_acc_seq_id_SHIFT 16
4596#define xmit_bls_rsp64_acc_seq_id_MASK 0x000000ff
4597#define xmit_bls_rsp64_acc_seq_id_WORD payload0
4598#define xmit_bls_rsp64_acc_seq_id_vald_SHIFT 24
4599#define xmit_bls_rsp64_acc_seq_id_vald_MASK 0x000000ff
4600#define xmit_bls_rsp64_acc_seq_id_vald_WORD payload0
4601/* Payload0 for BA_RJT */
4602#define xmit_bls_rsp64_rjt_vspec_SHIFT 0
4603#define xmit_bls_rsp64_rjt_vspec_MASK 0x000000ff
4604#define xmit_bls_rsp64_rjt_vspec_WORD payload0
4605#define xmit_bls_rsp64_rjt_expc_SHIFT 8
4606#define xmit_bls_rsp64_rjt_expc_MASK 0x000000ff
4607#define xmit_bls_rsp64_rjt_expc_WORD payload0
4608#define xmit_bls_rsp64_rjt_rsnc_SHIFT 16
4609#define xmit_bls_rsp64_rjt_rsnc_MASK 0x000000ff
4610#define xmit_bls_rsp64_rjt_rsnc_WORD payload0
4611 uint32_t word1;
4612#define xmit_bls_rsp64_rxid_SHIFT 0
4613#define xmit_bls_rsp64_rxid_MASK 0x0000ffff
4614#define xmit_bls_rsp64_rxid_WORD word1
4615#define xmit_bls_rsp64_oxid_SHIFT 16
4616#define xmit_bls_rsp64_oxid_MASK 0x0000ffff
4617#define xmit_bls_rsp64_oxid_WORD word1
4618 uint32_t word2;
4619#define xmit_bls_rsp64_seqcnthi_SHIFT 0
4620#define xmit_bls_rsp64_seqcnthi_MASK 0x0000ffff
4621#define xmit_bls_rsp64_seqcnthi_WORD word2
4622#define xmit_bls_rsp64_seqcntlo_SHIFT 16
4623#define xmit_bls_rsp64_seqcntlo_MASK 0x0000ffff
4624#define xmit_bls_rsp64_seqcntlo_WORD word2
4625 uint32_t rsrvd3;
4626 uint32_t rsrvd4;
4627 struct wqe_did wqe_dest;
4628 struct wqe_common wqe_com; /* words 6-11 */
4629 uint32_t word12;
4630#define xmit_bls_rsp64_temprpi_SHIFT 0
4631#define xmit_bls_rsp64_temprpi_MASK 0x0000ffff
4632#define xmit_bls_rsp64_temprpi_WORD word12
4633 uint32_t rsvd_13_15[3];
4634};
4635
4636struct wqe_rctl_dfctl {
4637 uint32_t word5;
4638#define wqe_si_SHIFT 2
4639#define wqe_si_MASK 0x000000001
4640#define wqe_si_WORD word5
4641#define wqe_la_SHIFT 3
4642#define wqe_la_MASK 0x000000001
4643#define wqe_la_WORD word5
4644#define wqe_xo_SHIFT 6
4645#define wqe_xo_MASK 0x000000001
4646#define wqe_xo_WORD word5
4647#define wqe_ls_SHIFT 7
4648#define wqe_ls_MASK 0x000000001
4649#define wqe_ls_WORD word5
4650#define wqe_dfctl_SHIFT 8
4651#define wqe_dfctl_MASK 0x0000000ff
4652#define wqe_dfctl_WORD word5
4653#define wqe_type_SHIFT 16
4654#define wqe_type_MASK 0x0000000ff
4655#define wqe_type_WORD word5
4656#define wqe_rctl_SHIFT 24
4657#define wqe_rctl_MASK 0x0000000ff
4658#define wqe_rctl_WORD word5
4659};
4660
4661struct xmit_seq64_wqe {
4662 struct ulp_bde64 bde;
4663 uint32_t rsvd3;
4664 uint32_t relative_offset;
4665 struct wqe_rctl_dfctl wge_ctl;
4666 struct wqe_common wqe_com; /* words 6-11 */
4667 uint32_t xmit_len;
4668 uint32_t rsvd_12_15[3];
4669};
4670struct xmit_bcast64_wqe {
4671 struct ulp_bde64 bde;
4672 uint32_t seq_payload_len;
4673 uint32_t rsvd4;
4674 struct wqe_rctl_dfctl wge_ctl; /* word 5 */
4675 struct wqe_common wqe_com; /* words 6-11 */
4676 uint32_t rsvd_12_15[4];
4677};
4678
4679struct gen_req64_wqe {
4680 struct ulp_bde64 bde;
4681 uint32_t request_payload_len;
4682 uint32_t relative_offset;
4683 struct wqe_rctl_dfctl wge_ctl; /* word 5 */
4684 struct wqe_common wqe_com; /* words 6-11 */
4685 uint32_t rsvd_12_14[3];
4686 uint32_t max_response_payload_len;
4687};
4688
4689/* Define NVME PRLI request to fabric. NVME is a
4690 * fabric-only protocol.
4691 * Updated to red-lined v1.08 on Sept 16, 2016
4692 */
4693struct lpfc_nvme_prli {
4694 uint32_t word1;
4695 /* The Response Code is defined in the FCP PRLI lpfc_hw.h */
4696#define prli_acc_rsp_code_SHIFT 8
4697#define prli_acc_rsp_code_MASK 0x0000000f
4698#define prli_acc_rsp_code_WORD word1
4699#define prli_estabImagePair_SHIFT 13
4700#define prli_estabImagePair_MASK 0x00000001
4701#define prli_estabImagePair_WORD word1
4702#define prli_type_code_ext_SHIFT 16
4703#define prli_type_code_ext_MASK 0x000000ff
4704#define prli_type_code_ext_WORD word1
4705#define prli_type_code_SHIFT 24
4706#define prli_type_code_MASK 0x000000ff
4707#define prli_type_code_WORD word1
4708 uint32_t word_rsvd2;
4709 uint32_t word_rsvd3;
4710
4711 uint32_t word4;
4712#define prli_fba_SHIFT 0
4713#define prli_fba_MASK 0x00000001
4714#define prli_fba_WORD word4
4715#define prli_disc_SHIFT 3
4716#define prli_disc_MASK 0x00000001
4717#define prli_disc_WORD word4
4718#define prli_tgt_SHIFT 4
4719#define prli_tgt_MASK 0x00000001
4720#define prli_tgt_WORD word4
4721#define prli_init_SHIFT 5
4722#define prli_init_MASK 0x00000001
4723#define prli_init_WORD word4
4724#define prli_conf_SHIFT 7
4725#define prli_conf_MASK 0x00000001
4726#define prli_conf_WORD word4
4727#define prli_nsler_SHIFT 8
4728#define prli_nsler_MASK 0x00000001
4729#define prli_nsler_WORD word4
4730 uint32_t word5;
4731#define prli_fb_sz_SHIFT 0
4732#define prli_fb_sz_MASK 0x0000ffff
4733#define prli_fb_sz_WORD word5
4734#define LPFC_NVMET_FB_SZ_MAX 65536 /* Driver target mode only. */
4735};
4736
4737struct create_xri_wqe {
4738 uint32_t rsrvd[5]; /* words 0-4 */
4739 struct wqe_did wqe_dest; /* word 5 */
4740 struct wqe_common wqe_com; /* words 6-11 */
4741 uint32_t rsvd_12_15[4]; /* word 12-15 */
4742};
4743
4744#define T_REQUEST_TAG 3
4745#define T_XRI_TAG 1
4746
4747struct cmf_sync_wqe {
4748 uint32_t rsrvd[3];
4749 uint32_t word3;
4750#define cmf_sync_interval_SHIFT 0
4751#define cmf_sync_interval_MASK 0x00000ffff
4752#define cmf_sync_interval_WORD word3
4753#define cmf_sync_afpin_SHIFT 16
4754#define cmf_sync_afpin_MASK 0x000000001
4755#define cmf_sync_afpin_WORD word3
4756#define cmf_sync_asig_SHIFT 17
4757#define cmf_sync_asig_MASK 0x000000001
4758#define cmf_sync_asig_WORD word3
4759#define cmf_sync_op_SHIFT 20
4760#define cmf_sync_op_MASK 0x00000000f
4761#define cmf_sync_op_WORD word3
4762#define cmf_sync_ver_SHIFT 24
4763#define cmf_sync_ver_MASK 0x0000000ff
4764#define cmf_sync_ver_WORD word3
4765#define LPFC_CMF_SYNC_VER 1
4766 uint32_t event_tag;
4767 uint32_t word5;
4768#define cmf_sync_wsigmax_SHIFT 0
4769#define cmf_sync_wsigmax_MASK 0x00000ffff
4770#define cmf_sync_wsigmax_WORD word5
4771#define cmf_sync_wsigcnt_SHIFT 16
4772#define cmf_sync_wsigcnt_MASK 0x00000ffff
4773#define cmf_sync_wsigcnt_WORD word5
4774 uint32_t word6;
4775 uint32_t word7;
4776#define cmf_sync_cmnd_SHIFT 8
4777#define cmf_sync_cmnd_MASK 0x0000000ff
4778#define cmf_sync_cmnd_WORD word7
4779 uint32_t word8;
4780 uint32_t word9;
4781#define cmf_sync_reqtag_SHIFT 0
4782#define cmf_sync_reqtag_MASK 0x00000ffff
4783#define cmf_sync_reqtag_WORD word9
4784#define cmf_sync_wfpinmax_SHIFT 16
4785#define cmf_sync_wfpinmax_MASK 0x0000000ff
4786#define cmf_sync_wfpinmax_WORD word9
4787#define cmf_sync_wfpincnt_SHIFT 24
4788#define cmf_sync_wfpincnt_MASK 0x0000000ff
4789#define cmf_sync_wfpincnt_WORD word9
4790 uint32_t word10;
4791#define cmf_sync_qosd_SHIFT 9
4792#define cmf_sync_qosd_MASK 0x00000001
4793#define cmf_sync_qosd_WORD word10
4794 uint32_t word11;
4795#define cmf_sync_cmd_type_SHIFT 0
4796#define cmf_sync_cmd_type_MASK 0x0000000f
4797#define cmf_sync_cmd_type_WORD word11
4798#define cmf_sync_wqec_SHIFT 7
4799#define cmf_sync_wqec_MASK 0x00000001
4800#define cmf_sync_wqec_WORD word11
4801#define cmf_sync_cqid_SHIFT 16
4802#define cmf_sync_cqid_MASK 0x0000ffff
4803#define cmf_sync_cqid_WORD word11
4804 uint32_t read_bytes;
4805 uint32_t word13;
4806#define cmf_sync_period_SHIFT 24
4807#define cmf_sync_period_MASK 0x000000ff
4808#define cmf_sync_period_WORD word13
4809 uint32_t word14;
4810 uint32_t word15;
4811};
4812
4813struct abort_cmd_wqe {
4814 uint32_t rsrvd[3];
4815 uint32_t word3;
4816#define abort_cmd_ia_SHIFT 0
4817#define abort_cmd_ia_MASK 0x000000001
4818#define abort_cmd_ia_WORD word3
4819#define abort_cmd_criteria_SHIFT 8
4820#define abort_cmd_criteria_MASK 0x0000000ff
4821#define abort_cmd_criteria_WORD word3
4822 uint32_t rsrvd4;
4823 uint32_t rsrvd5;
4824 struct wqe_common wqe_com; /* words 6-11 */
4825 uint32_t rsvd_12_15[4]; /* word 12-15 */
4826};
4827
4828struct fcp_iwrite64_wqe {
4829 struct ulp_bde64 bde;
4830 uint32_t word3;
4831#define cmd_buff_len_SHIFT 16
4832#define cmd_buff_len_MASK 0x00000ffff
4833#define cmd_buff_len_WORD word3
4834/* Note: payload_offset_len field depends on ASIC support */
4835#define payload_offset_len_SHIFT 0
4836#define payload_offset_len_MASK 0x0000ffff
4837#define payload_offset_len_WORD word3
4838 uint32_t total_xfer_len;
4839 uint32_t initial_xfer_len;
4840 struct wqe_common wqe_com; /* words 6-11 */
4841 uint32_t rsrvd12;
4842 struct ulp_bde64 ph_bde; /* words 13-15 */
4843};
4844
4845struct fcp_iread64_wqe {
4846 struct ulp_bde64 bde;
4847 uint32_t word3;
4848#define cmd_buff_len_SHIFT 16
4849#define cmd_buff_len_MASK 0x00000ffff
4850#define cmd_buff_len_WORD word3
4851/* Note: payload_offset_len field depends on ASIC support */
4852#define payload_offset_len_SHIFT 0
4853#define payload_offset_len_MASK 0x0000ffff
4854#define payload_offset_len_WORD word3
4855 uint32_t total_xfer_len; /* word 4 */
4856 uint32_t rsrvd5; /* word 5 */
4857 struct wqe_common wqe_com; /* words 6-11 */
4858 uint32_t rsrvd12;
4859 struct ulp_bde64 ph_bde; /* words 13-15 */
4860};
4861
4862struct fcp_icmnd64_wqe {
4863 struct ulp_bde64 bde; /* words 0-2 */
4864 uint32_t word3;
4865#define cmd_buff_len_SHIFT 16
4866#define cmd_buff_len_MASK 0x00000ffff
4867#define cmd_buff_len_WORD word3
4868/* Note: payload_offset_len field depends on ASIC support */
4869#define payload_offset_len_SHIFT 0
4870#define payload_offset_len_MASK 0x0000ffff
4871#define payload_offset_len_WORD word3
4872 uint32_t rsrvd4; /* word 4 */
4873 uint32_t rsrvd5; /* word 5 */
4874 struct wqe_common wqe_com; /* words 6-11 */
4875 uint32_t rsvd_12_15[4]; /* word 12-15 */
4876};
4877
4878struct fcp_trsp64_wqe {
4879 struct ulp_bde64 bde;
4880 uint32_t response_len;
4881 uint32_t rsvd_4_5[2];
4882 struct wqe_common wqe_com; /* words 6-11 */
4883 uint32_t rsvd_12_15[4]; /* word 12-15 */
4884};
4885
4886struct fcp_tsend64_wqe {
4887 struct ulp_bde64 bde;
4888 uint32_t payload_offset_len;
4889 uint32_t relative_offset;
4890 uint32_t reserved;
4891 struct wqe_common wqe_com; /* words 6-11 */
4892 uint32_t fcp_data_len; /* word 12 */
4893 uint32_t rsvd_13_15[3]; /* word 13-15 */
4894};
4895
4896struct fcp_treceive64_wqe {
4897 struct ulp_bde64 bde;
4898 uint32_t payload_offset_len;
4899 uint32_t relative_offset;
4900 uint32_t reserved;
4901 struct wqe_common wqe_com; /* words 6-11 */
4902 uint32_t fcp_data_len; /* word 12 */
4903 uint32_t rsvd_13_15[3]; /* word 13-15 */
4904};
4905#define TXRDY_PAYLOAD_LEN 12
4906
4907#define CMD_SEND_FRAME 0xE1
4908
4909struct send_frame_wqe {
4910 struct ulp_bde64 bde; /* words 0-2 */
4911 uint32_t frame_len; /* word 3 */
4912 uint32_t fc_hdr_wd0; /* word 4 */
4913 uint32_t fc_hdr_wd1; /* word 5 */
4914 struct wqe_common wqe_com; /* words 6-11 */
4915 uint32_t fc_hdr_wd2; /* word 12 */
4916 uint32_t fc_hdr_wd3; /* word 13 */
4917 uint32_t fc_hdr_wd4; /* word 14 */
4918 uint32_t fc_hdr_wd5; /* word 15 */
4919};
4920
4921#define ELS_RDF_REG_TAG_CNT 4
4922struct lpfc_els_rdf_reg_desc {
4923 struct fc_df_desc_fpin_reg_hdr reg_desc; /* descriptor header */
4924 __be32 desc_tags[ELS_RDF_REG_TAG_CNT];
4925 /* tags in reg_desc */
4926};
4927
4928struct lpfc_els_rdf_req {
4929 struct fc_els_rdf_hdr rdf; /* hdr up to descriptors */
4930 struct lpfc_els_rdf_reg_desc reg_d1; /* 1st descriptor */
4931};
4932
4933struct lpfc_els_rdf_rsp {
4934 struct fc_els_rdf_resp_hdr rdf_resp; /* hdr up to descriptors */
4935 struct lpfc_els_rdf_reg_desc reg_d1; /* 1st descriptor */
4936};
4937
4938union lpfc_wqe {
4939 uint32_t words[16];
4940 struct lpfc_wqe_generic generic;
4941 struct fcp_icmnd64_wqe fcp_icmd;
4942 struct fcp_iread64_wqe fcp_iread;
4943 struct fcp_iwrite64_wqe fcp_iwrite;
4944 struct abort_cmd_wqe abort_cmd;
4945 struct cmf_sync_wqe cmf_sync;
4946 struct create_xri_wqe create_xri;
4947 struct xmit_bcast64_wqe xmit_bcast64;
4948 struct xmit_seq64_wqe xmit_sequence;
4949 struct xmit_bls_rsp64_wqe xmit_bls_rsp;
4950 struct xmit_els_rsp64_wqe xmit_els_rsp;
4951 struct els_request64_wqe els_req;
4952 struct gen_req64_wqe gen_req;
4953 struct fcp_trsp64_wqe fcp_trsp;
4954 struct fcp_tsend64_wqe fcp_tsend;
4955 struct fcp_treceive64_wqe fcp_treceive;
4956 struct send_frame_wqe send_frame;
4957};
4958
4959union lpfc_wqe128 {
4960 uint32_t words[32];
4961 struct lpfc_wqe_generic generic;
4962 struct fcp_icmnd64_wqe fcp_icmd;
4963 struct fcp_iread64_wqe fcp_iread;
4964 struct fcp_iwrite64_wqe fcp_iwrite;
4965 struct abort_cmd_wqe abort_cmd;
4966 struct cmf_sync_wqe cmf_sync;
4967 struct create_xri_wqe create_xri;
4968 struct xmit_bcast64_wqe xmit_bcast64;
4969 struct xmit_seq64_wqe xmit_sequence;
4970 struct xmit_bls_rsp64_wqe xmit_bls_rsp;
4971 struct xmit_els_rsp64_wqe xmit_els_rsp;
4972 struct els_request64_wqe els_req;
4973 struct gen_req64_wqe gen_req;
4974 struct fcp_trsp64_wqe fcp_trsp;
4975 struct fcp_tsend64_wqe fcp_tsend;
4976 struct fcp_treceive64_wqe fcp_treceive;
4977 struct send_frame_wqe send_frame;
4978};
4979
4980#define MAGIC_NUMBER_G6 0xFEAA0003
4981#define MAGIC_NUMBER_G7 0xFEAA0005
4982#define MAGIC_NUMBER_G7P 0xFEAA0020
4983#define MAGIC_NUMBER_G8 0xFEAA0070
4984
4985struct lpfc_grp_hdr {
4986 uint32_t size;
4987 uint32_t magic_number;
4988 uint32_t word2;
4989#define lpfc_grp_hdr_file_type_SHIFT 24
4990#define lpfc_grp_hdr_file_type_MASK 0x000000FF
4991#define lpfc_grp_hdr_file_type_WORD word2
4992#define lpfc_grp_hdr_id_SHIFT 16
4993#define lpfc_grp_hdr_id_MASK 0x000000FF
4994#define lpfc_grp_hdr_id_WORD word2
4995 uint8_t rev_name[128];
4996 uint8_t date[12];
4997 uint8_t revision[32];
4998};
4999
5000/* Defines for WQE command type */
5001#define FCP_COMMAND 0x0
5002#define NVME_READ_CMD 0x0
5003#define FCP_COMMAND_DATA_OUT 0x1
5004#define NVME_WRITE_CMD 0x1
5005#define COMMAND_DATA_IN 0x0
5006#define COMMAND_DATA_OUT 0x1
5007#define FCP_COMMAND_TRECEIVE 0x2
5008#define FCP_COMMAND_TRSP 0x3
5009#define FCP_COMMAND_TSEND 0x7
5010#define OTHER_COMMAND 0x8
5011#define CMF_SYNC_COMMAND 0xA
5012#define ELS_COMMAND_NON_FIP 0xC
5013#define ELS_COMMAND_FIP 0xD
5014
5015#define LPFC_NVME_EMBED_CMD 0x0
5016#define LPFC_NVME_EMBED_WRITE 0x1
5017#define LPFC_NVME_EMBED_READ 0x2
5018
5019/* WQE Commands */
5020#define CMD_ABORT_XRI_WQE 0x0F
5021#define CMD_XMIT_SEQUENCE64_WQE 0x82
5022#define CMD_XMIT_BCAST64_WQE 0x84
5023#define CMD_ELS_REQUEST64_WQE 0x8A
5024#define CMD_XMIT_ELS_RSP64_WQE 0x95
5025#define CMD_XMIT_BLS_RSP64_WQE 0x97
5026#define CMD_FCP_IWRITE64_WQE 0x98
5027#define CMD_FCP_IREAD64_WQE 0x9A
5028#define CMD_FCP_ICMND64_WQE 0x9C
5029#define CMD_FCP_TSEND64_WQE 0x9F
5030#define CMD_FCP_TRECEIVE64_WQE 0xA1
5031#define CMD_FCP_TRSP64_WQE 0xA3
5032#define CMD_GEN_REQUEST64_WQE 0xC2
5033#define CMD_CMF_SYNC_WQE 0xE8
5034
5035#define CMD_WQE_MASK 0xff
5036
5037
5038#define LPFC_FW_DUMP 1
5039#define LPFC_FW_RESET 2
5040#define LPFC_DV_RESET 3
5041
5042/* On some kernels, enum fc_ls_tlv_dtag does not have
5043 * these 2 enums defined, on other kernels it does.
5044 * To get aound this we need to add these 2 defines here.
5045 */
5046#ifndef ELS_DTAG_LNK_FAULT_CAP
5047#define ELS_DTAG_LNK_FAULT_CAP 0x0001000D
5048#endif
5049#ifndef ELS_DTAG_CG_SIGNAL_CAP
5050#define ELS_DTAG_CG_SIGNAL_CAP 0x0001000F
5051#endif
5052
5053/*
5054 * Initializer useful for decoding FPIN string table.
5055 */
5056#define FC_FPIN_CONGN_SEVERITY_INIT { \
5057 { FPIN_CONGN_SEVERITY_WARNING, "Warning" }, \
5058 { FPIN_CONGN_SEVERITY_ERROR, "Alarm" }, \
5059}
5060
5061/* Used for logging FPIN messages */
5062#define LPFC_FPIN_WWPN_LINE_SZ 128
5063#define LPFC_FPIN_WWPN_LINE_CNT 6
5064#define LPFC_FPIN_WWPN_NUM_LINE 6