Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Driver for Broadcom MPI3 Storage Controllers
4 *
5 * Copyright (C) 2017-2023 Broadcom Inc.
6 * (mailto: mpi3mr-linuxdrv.pdl@broadcom.com)
7 *
8 */
9
10#ifndef MPI3MR_H_INCLUDED
11#define MPI3MR_H_INCLUDED
12
13#include <linux/blkdev.h>
14#include <linux/blk-mq.h>
15#include <linux/delay.h>
16#include <linux/dmapool.h>
17#include <linux/errno.h>
18#include <linux/init.h>
19#include <linux/io.h>
20#include <linux/interrupt.h>
21#include <linux/kernel.h>
22#include <linux/miscdevice.h>
23#include <linux/module.h>
24#include <linux/pci.h>
25#include <linux/aer.h>
26#include <linux/poll.h>
27#include <linux/sched.h>
28#include <linux/slab.h>
29#include <linux/types.h>
30#include <linux/uaccess.h>
31#include <linux/utsname.h>
32#include <linux/workqueue.h>
33#include <linux/unaligned.h>
34#include <scsi/scsi.h>
35#include <scsi/scsi_cmnd.h>
36#include <scsi/scsi_dbg.h>
37#include <scsi/scsi_device.h>
38#include <scsi/scsi_host.h>
39#include <scsi/scsi_tcq.h>
40#include <uapi/scsi/scsi_bsg_mpi3mr.h>
41#include <scsi/scsi_transport_sas.h>
42
43#include "mpi/mpi30_transport.h"
44#include "mpi/mpi30_cnfg.h"
45#include "mpi/mpi30_image.h"
46#include "mpi/mpi30_init.h"
47#include "mpi/mpi30_ioc.h"
48#include "mpi/mpi30_sas.h"
49#include "mpi/mpi30_pci.h"
50#include "mpi/mpi30_tool.h"
51#include "mpi3mr_debug.h"
52
53/* Global list and lock for storing multiple adapters managed by the driver */
54extern spinlock_t mrioc_list_lock;
55extern struct list_head mrioc_list;
56extern int prot_mask;
57extern atomic64_t event_counter;
58
59#define MPI3MR_DRIVER_VERSION "8.17.0.3.50"
60#define MPI3MR_DRIVER_RELDATE "09-January-2026"
61
62#define MPI3MR_DRIVER_NAME "mpi3mr"
63#define MPI3MR_DRIVER_LICENSE "GPL"
64#define MPI3MR_DRIVER_AUTHOR "Broadcom Inc. <mpi3mr-linuxdrv.pdl@broadcom.com>"
65#define MPI3MR_DRIVER_DESC "MPI3 Storage Controller Device Driver"
66
67#define MPI3MR_NAME_LENGTH 64
68#define IOCNAME "%s: "
69
70#define MPI3MR_DEFAULT_MAX_IO_SIZE (1 * 1024 * 1024)
71
72/* Definitions for internal SGL and Chain SGL buffers */
73#define MPI3MR_PAGE_SIZE_4K 4096
74#define MPI3MR_DEFAULT_SGL_ENTRIES 256
75#define MPI3MR_MAX_SGL_ENTRIES 2048
76
77/* Definitions for MAX values for shost */
78#define MPI3MR_MAX_CMDS_LUN 128
79#define MPI3MR_MAX_CDB_LENGTH 32
80
81/* Admin queue management definitions */
82#define MPI3MR_ADMIN_REQ_Q_SIZE (2 * MPI3MR_PAGE_SIZE_4K)
83#define MPI3MR_ADMIN_REPLY_Q_SIZE (8 * MPI3MR_PAGE_SIZE_4K)
84#define MPI3MR_ADMIN_REQ_FRAME_SZ 128
85#define MPI3MR_ADMIN_REPLY_FRAME_SZ 16
86
87/* Operational queue management definitions */
88#define MPI3MR_OP_REQ_Q_QD 512
89#define MPI3MR_OP_REP_Q_QD 1024
90#define MPI3MR_OP_REP_Q_QD2K 2048
91#define MPI3MR_OP_REP_Q_QD4K 4096
92#define MPI3MR_OP_REQ_Q_SEG_SIZE 4096
93#define MPI3MR_OP_REP_Q_SEG_SIZE 4096
94#define MPI3MR_MAX_SEG_LIST_SIZE 4096
95
96/* Reserved Host Tag definitions */
97#define MPI3MR_HOSTTAG_INVALID 0xFFFF
98#define MPI3MR_HOSTTAG_INITCMDS 1
99#define MPI3MR_HOSTTAG_BSG_CMDS 2
100#define MPI3MR_HOSTTAG_PEL_ABORT 3
101#define MPI3MR_HOSTTAG_PEL_WAIT 4
102#define MPI3MR_HOSTTAG_BLK_TMS 5
103#define MPI3MR_HOSTTAG_CFG_CMDS 6
104#define MPI3MR_HOSTTAG_TRANSPORT_CMDS 7
105
106#define MPI3MR_NUM_DEVRMCMD 16
107#define MPI3MR_HOSTTAG_DEVRMCMD_MIN (MPI3MR_HOSTTAG_TRANSPORT_CMDS + 1)
108#define MPI3MR_HOSTTAG_DEVRMCMD_MAX (MPI3MR_HOSTTAG_DEVRMCMD_MIN + \
109 MPI3MR_NUM_DEVRMCMD - 1)
110
111#define MPI3MR_INTERNAL_CMDS_RESVD MPI3MR_HOSTTAG_DEVRMCMD_MAX
112#define MPI3MR_NUM_EVTACKCMD 4
113#define MPI3MR_HOSTTAG_EVTACKCMD_MIN (MPI3MR_HOSTTAG_DEVRMCMD_MAX + 1)
114#define MPI3MR_HOSTTAG_EVTACKCMD_MAX (MPI3MR_HOSTTAG_EVTACKCMD_MIN + \
115 MPI3MR_NUM_EVTACKCMD - 1)
116
117/* Reduced resource count definition for crash kernel */
118#define MPI3MR_HOST_IOS_KDUMP 128
119
120/* command/controller interaction timeout definitions in seconds */
121#define MPI3MR_INTADMCMD_TIMEOUT 60
122#define MPI3MR_PORTENABLE_TIMEOUT 300
123#define MPI3MR_PORTENABLE_POLL_INTERVAL 5
124#define MPI3MR_ABORTTM_TIMEOUT 60
125#define MPI3MR_RESETTM_TIMEOUT 60
126#define MPI3MR_RESET_HOST_IOWAIT_TIMEOUT 5
127#define MPI3MR_TSUPDATE_INTERVAL 900
128#define MPI3MR_DEFAULT_SHUTDOWN_TIME 120
129#define MPI3MR_RAID_ERRREC_RESET_TIMEOUT 180
130#define MPI3MR_PREPARE_FOR_RESET_TIMEOUT 180
131#define MPI3MR_RESET_ACK_TIMEOUT 30
132#define MPI3MR_MUR_TIMEOUT 120
133#define MPI3MR_RESET_TIMEOUT 510
134
135#define MPI3MR_WATCHDOG_INTERVAL 1000 /* in milli seconds */
136
137#define MPI3MR_RESET_TOPOLOGY_SETTLE_TIME 10
138
139#define MPI3MR_SCMD_TIMEOUT (60 * HZ)
140#define MPI3MR_EH_SCMD_TIMEOUT (60 * HZ)
141
142/* Internal admin command state definitions*/
143#define MPI3MR_CMD_NOTUSED 0x8000
144#define MPI3MR_CMD_COMPLETE 0x0001
145#define MPI3MR_CMD_PENDING 0x0002
146#define MPI3MR_CMD_REPLY_VALID 0x0004
147#define MPI3MR_CMD_RESET 0x0008
148
149/* Definitions for Event replies and sense buffer allocated per controller */
150#define MPI3MR_NUM_EVT_REPLIES 64
151#define MPI3MR_SENSE_BUF_SZ 256
152#define MPI3MR_SENSEBUF_FACTOR 3
153#define MPI3MR_CHAINBUF_FACTOR 3
154#define MPI3MR_CHAINBUFDIX_FACTOR 2
155
156/* Invalid target device handle */
157#define MPI3MR_INVALID_DEV_HANDLE 0xFFFF
158
159/* Controller Reset related definitions */
160#define MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT 5
161#define MPI3MR_MAX_RESET_RETRY_COUNT 3
162#define MPI3MR_MAX_SHUTDOWN_RETRY_COUNT 2
163
164/* ResponseCode definitions */
165#define MPI3MR_RI_MASK_RESPCODE (0x000000FF)
166#define MPI3MR_RSP_IO_QUEUED_ON_IOC \
167 MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC
168
169#define MPI3MR_DEFAULT_MDTS (128 * 1024)
170#define MPI3MR_DEFAULT_PGSZEXP (12)
171
172/* Command retry count definitions */
173#define MPI3MR_DEV_RMHS_RETRY_COUNT 3
174#define MPI3MR_PEL_RETRY_COUNT 3
175
176/* Default target device queue depth */
177#define MPI3MR_DEFAULT_SDEV_QD 32
178
179/* Definitions for Threaded IRQ poll*/
180#define MPI3MR_IRQ_POLL_SLEEP 20
181#define MPI3MR_IRQ_POLL_TRIGGER_IOCOUNT 8
182
183/* Definitions for the controller security status*/
184#define MPI3MR_CTLR_SECURITY_STATUS_MASK 0x0C
185#define MPI3MR_CTLR_SECURE_DBG_STATUS_MASK 0x02
186
187#define MPI3MR_INVALID_DEVICE 0x00
188#define MPI3MR_CONFIG_SECURE_DEVICE 0x04
189#define MPI3MR_HARD_SECURE_DEVICE 0x08
190#define MPI3MR_TAMPERED_DEVICE 0x0C
191
192#define MPI3MR_DEFAULT_HDB_MAX_SZ (4 * 1024 * 1024)
193#define MPI3MR_DEFAULT_HDB_DEC_SZ (1 * 1024 * 1024)
194#define MPI3MR_DEFAULT_HDB_MIN_SZ (2 * 1024 * 1024)
195#define MPI3MR_MAX_NUM_HDB 2
196
197#define MPI3MR_HDB_TRIGGER_TYPE_UNKNOWN 0
198#define MPI3MR_HDB_TRIGGER_TYPE_FAULT 1
199#define MPI3MR_HDB_TRIGGER_TYPE_ELEMENT 2
200#define MPI3MR_HDB_TRIGGER_TYPE_GLOBAL 3
201#define MPI3MR_HDB_TRIGGER_TYPE_SOFT_RESET 4
202#define MPI3MR_HDB_TRIGGER_TYPE_FW_RELEASED 5
203
204#define MPI3MR_HDB_REFRESH_TYPE_RESERVED 0
205#define MPI3MR_HDB_REFRESH_TYPE_CURRENT 1
206#define MPI3MR_HDB_REFRESH_TYPE_DEFAULT 2
207#define MPI3MR_HDB_HDB_REFRESH_TYPE_PERSISTENT 3
208
209#define MPI3MR_DEFAULT_HDB_SZ (4 * 1024 * 1024)
210#define MPI3MR_MAX_NUM_HDB 2
211
212#define MPI3MR_HDB_QUERY_ELEMENT_TRIGGER_FORMAT_INDEX 0
213#define MPI3MR_HDB_QUERY_ELEMENT_TRIGGER_FORMAT_DATA 1
214
215#define MPI3MR_THRESHOLD_REPLY_COUNT 100
216
217/* SGE Flag definition */
218#define MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST \
219 (MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE | MPI3_SGE_FLAGS_DLAS_SYSTEM | \
220 MPI3_SGE_FLAGS_END_OF_LIST)
221
222/* MSI Index from Reply Queue Index */
223#define REPLY_QUEUE_IDX_TO_MSIX_IDX(qidx, offset) (qidx + offset)
224
225/*
226 * Maximum data transfer size definitions for management
227 * application commands
228 */
229#define MPI3MR_MAX_APP_XFER_SIZE (1 * 1024 * 1024)
230#define MPI3MR_MAX_APP_XFER_SEGMENTS 512
231/*
232 * 2048 sectors are for data buffers and additional 512 sectors for
233 * other buffers
234 */
235#define MPI3MR_MAX_APP_XFER_SECTORS (2048 + 512)
236
237#define MPI3MR_WRITE_SAME_MAX_LEN_256_BLKS 256
238#define MPI3MR_WRITE_SAME_MAX_LEN_2048_BLKS 2048
239
240#define MPI3MR_DRIVER_EVENT_PROCESS_TRIGGER (0xFFFD)
241
242/**
243 * struct mpi3mr_nvme_pt_sge - Structure to store SGEs for NVMe
244 * Encapsulated commands.
245 *
246 * @base_addr: Physical address
247 * @length: SGE length
248 * @rsvd: Reserved
249 * @rsvd1: Reserved
250 * @sub_type: sgl sub type
251 * @type: sgl type
252 */
253struct mpi3mr_nvme_pt_sge {
254 __le64 base_addr;
255 __le32 length;
256 u16 rsvd;
257 u8 rsvd1;
258 u8 sub_type:4;
259 u8 type:4;
260};
261
262/**
263 * struct mpi3mr_buf_map - local structure to
264 * track kernel and user buffers associated with an BSG
265 * structure.
266 *
267 * @bsg_buf: BSG buffer virtual address
268 * @bsg_buf_len: BSG buffer length
269 * @kern_buf: Kernel buffer virtual address
270 * @kern_buf_len: Kernel buffer length
271 * @kern_buf_dma: Kernel buffer DMA address
272 * @data_dir: Data direction.
273 */
274struct mpi3mr_buf_map {
275 void *bsg_buf;
276 u32 bsg_buf_len;
277 void *kern_buf;
278 u32 kern_buf_len;
279 dma_addr_t kern_buf_dma;
280 u8 data_dir;
281 u16 num_dma_desc;
282 struct dma_memory_desc *dma_desc;
283};
284
285/* IOC State definitions */
286enum mpi3mr_iocstate {
287 MRIOC_STATE_READY = 1,
288 MRIOC_STATE_RESET,
289 MRIOC_STATE_FAULT,
290 MRIOC_STATE_BECOMING_READY,
291 MRIOC_STATE_RESET_REQUESTED,
292 MRIOC_STATE_UNRECOVERABLE,
293};
294
295/* Reset reason code definitions*/
296enum mpi3mr_reset_reason {
297 MPI3MR_RESET_FROM_BRINGUP = 1,
298 MPI3MR_RESET_FROM_FAULT_WATCH = 2,
299 MPI3MR_RESET_FROM_APP = 3,
300 MPI3MR_RESET_FROM_EH_HOS = 4,
301 MPI3MR_RESET_FROM_TM_TIMEOUT = 5,
302 MPI3MR_RESET_FROM_APP_TIMEOUT = 6,
303 MPI3MR_RESET_FROM_MUR_FAILURE = 7,
304 MPI3MR_RESET_FROM_CTLR_CLEANUP = 8,
305 MPI3MR_RESET_FROM_CIACTIV_FAULT = 9,
306 MPI3MR_RESET_FROM_PE_TIMEOUT = 10,
307 MPI3MR_RESET_FROM_TSU_TIMEOUT = 11,
308 MPI3MR_RESET_FROM_DELREQQ_TIMEOUT = 12,
309 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT = 13,
310 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT = 14,
311 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT = 15,
312 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT = 16,
313 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT = 17,
314 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT = 18,
315 MPI3MR_RESET_FROM_EVTACK_TIMEOUT = 19,
316 MPI3MR_RESET_FROM_CIACTVRST_TIMER = 20,
317 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT = 21,
318 MPI3MR_RESET_FROM_PELABORT_TIMEOUT = 22,
319 MPI3MR_RESET_FROM_SYSFS = 23,
320 MPI3MR_RESET_FROM_SYSFS_TIMEOUT = 24,
321 MPI3MR_RESET_FROM_DIAG_BUFFER_POST_TIMEOUT = 25,
322 MPI3MR_RESET_FROM_DIAG_BUFFER_RELEASE_TIMEOUT = 26,
323 MPI3MR_RESET_FROM_FIRMWARE = 27,
324 MPI3MR_RESET_FROM_CFG_REQ_TIMEOUT = 29,
325 MPI3MR_RESET_FROM_SAS_TRANSPORT_TIMEOUT = 30,
326 MPI3MR_RESET_FROM_TRIGGER = 31,
327 MPI3MR_RESET_FROM_INVALID_COMPLETION = 32,
328};
329
330#define MPI3MR_RESET_REASON_OSTYPE_LINUX 1
331#define MPI3MR_RESET_REASON_OSTYPE_SHIFT 28
332#define MPI3MR_RESET_REASON_IOCNUM_SHIFT 20
333
334
335/* Queue type definitions */
336enum queue_type {
337 MPI3MR_DEFAULT_QUEUE = 0,
338 MPI3MR_POLL_QUEUE,
339};
340
341/**
342 * struct mpi3mr_compimg_ver - replica of component image
343 * version defined in mpi30_image.h in host endianness
344 *
345 */
346struct mpi3mr_compimg_ver {
347 u16 build_num;
348 u16 cust_id;
349 u8 ph_minor;
350 u8 ph_major;
351 u8 gen_minor;
352 u8 gen_major;
353};
354
355/**
356 * struct mpi3mr_ioc_facs - replica of component image version
357 * defined in mpi30_ioc.h in host endianness
358 *
359 */
360struct mpi3mr_ioc_facts {
361 u32 ioc_capabilities;
362 struct mpi3mr_compimg_ver fw_ver;
363 u32 mpi_version;
364 u32 diag_trace_sz;
365 u32 diag_fw_sz;
366 u32 diag_drvr_sz;
367 u16 max_reqs;
368 u16 product_id;
369 u16 op_req_sz;
370 u16 reply_sz;
371 u16 exceptions;
372 u16 max_perids;
373 u16 max_pds;
374 u16 max_sasexpanders;
375 u32 max_data_length;
376 u16 max_sasinitiators;
377 u16 max_enclosures;
378 u16 max_pcie_switches;
379 u16 max_nvme;
380 u16 max_vds;
381 u16 max_hpds;
382 u16 max_advhpds;
383 u16 max_raid_pds;
384 u16 min_devhandle;
385 u16 max_devhandle;
386 u16 max_op_req_q;
387 u16 max_op_reply_q;
388 u16 shutdown_timeout;
389 u8 ioc_num;
390 u8 who_init;
391 u16 max_msix_vectors;
392 u8 personality;
393 u8 dma_mask;
394 bool max_req_limit;
395 u8 protocol_flags;
396 u8 sge_mod_mask;
397 u8 sge_mod_value;
398 u8 sge_mod_shift;
399 u8 max_dev_per_tg;
400 u16 max_io_throttle_group;
401 u16 io_throttle_data_length;
402 u16 io_throttle_low;
403 u16 io_throttle_high;
404
405};
406
407/**
408 * struct segments - memory descriptor structure to store
409 * virtual and dma addresses for operational queue segments.
410 *
411 * @segment: virtual address
412 * @segment_dma: dma address
413 */
414struct segments {
415 void *segment;
416 dma_addr_t segment_dma;
417};
418
419/**
420 * struct op_req_qinfo - Operational Request Queue Information
421 *
422 * @ci: consumer index
423 * @pi: producer index
424 * @num_request: Maximum number of entries in the queue
425 * @qid: Queue Id starting from 1
426 * @reply_qid: Associated reply queue Id
427 * @num_segments: Number of discontiguous memory segments
428 * @segment_qd: Depth of each segments
429 * @q_lock: Concurrent queue access lock
430 * @q_segments: Segment descriptor pointer
431 * @q_segment_list: Segment list base virtual address
432 * @q_segment_list_dma: Segment list base DMA address
433 * @last_full_host_tag: Hosttag of last IO returned to SML
434 * due to queue full
435 * @qfull_io_count: Number of IOs returned back to SML
436 * due to queue full
437 * @qfull_instances: Total queue full occurrences.One occurrence
438 * starts with queue full detection and ends
439 * with queue full breaks.
440 *
441 */
442struct op_req_qinfo {
443 u16 ci;
444 u16 pi;
445 u16 num_requests;
446 u16 qid;
447 u16 reply_qid;
448 u16 num_segments;
449 u16 segment_qd;
450 spinlock_t q_lock;
451 struct segments *q_segments;
452 void *q_segment_list;
453 dma_addr_t q_segment_list_dma;
454 u16 last_full_host_tag;
455 u64 qfull_io_count;
456 u32 qfull_instances;
457
458};
459
460/**
461 * struct op_reply_qinfo - Operational Reply Queue Information
462 *
463 * @ci: consumer index
464 * @qid: Queue Id starting from 1
465 * @num_replies: Maximum number of entries in the queue
466 * @num_segments: Number of discontiguous memory segments
467 * @segment_qd: Depth of each segments
468 * @q_segments: Segment descriptor pointer
469 * @q_segment_list: Segment list base virtual address
470 * @q_segment_list_dma: Segment list base DMA address
471 * @ephase: Expected phased identifier for the reply queue
472 * @pend_ios: Number of IOs pending in HW for this queue
473 * @enable_irq_poll: Flag to indicate polling is enabled
474 * @in_use: Queue is handled by poll/ISR
475 * @qtype: Type of queue (types defined in enum queue_type)
476 * @qfull_watermark: Watermark defined in reply queue to avoid
477 * reply queue full
478 */
479struct op_reply_qinfo {
480 u16 ci;
481 u16 qid;
482 u16 num_replies;
483 u16 num_segments;
484 u16 segment_qd;
485 struct segments *q_segments;
486 void *q_segment_list;
487 dma_addr_t q_segment_list_dma;
488 u8 ephase;
489 atomic_t pend_ios;
490 bool enable_irq_poll;
491 atomic_t in_use;
492 enum queue_type qtype;
493 u16 qfull_watermark;
494};
495
496/**
497 * struct mpi3mr_intr_info - Interrupt cookie information
498 *
499 * @mrioc: Adapter instance reference
500 * @os_irq: irq number
501 * @msix_index: MSIx index
502 * @op_reply_q: Associated operational reply queue
503 * @name: Dev name for the irq claiming device
504 */
505struct mpi3mr_intr_info {
506 struct mpi3mr_ioc *mrioc;
507 int os_irq;
508 u16 msix_index;
509 struct op_reply_qinfo *op_reply_q;
510 char name[MPI3MR_NAME_LENGTH];
511};
512
513/**
514 * struct mpi3mr_throttle_group_info - Throttle group info
515 *
516 * @io_divert: Flag indicates io divert is on or off for the TG
517 * @need_qd_reduction: Flag to indicate QD reduction is needed
518 * @qd_reduction: Queue Depth reduction in units of 10%
519 * @fw_qd: QueueDepth value reported by the firmware
520 * @modified_qd: Modified QueueDepth value due to throttling
521 * @id: Throttle Group ID.
522 * @high: High limit to turn on throttling in 512 byte blocks
523 * @low: Low limit to turn off throttling in 512 byte blocks
524 * @pend_large_data_sz: Counter to track pending large data
525 */
526struct mpi3mr_throttle_group_info {
527 u8 io_divert;
528 u8 need_qd_reduction;
529 u8 qd_reduction;
530 u16 fw_qd;
531 u16 modified_qd;
532 u16 id;
533 u32 high;
534 u32 low;
535 atomic_t pend_large_data_sz;
536};
537
538/* HBA port flags */
539#define MPI3MR_HBA_PORT_FLAG_DIRTY 0x01
540#define MPI3MR_HBA_PORT_FLAG_NEW 0x02
541
542/* IOCTL data transfer sge*/
543#define MPI3MR_NUM_IOCTL_SGE 256
544#define MPI3MR_IOCTL_SGE_SIZE (8 * 1024)
545
546/**
547 * struct mpi3mr_hba_port - HBA's port information
548 * @port_id: Port number
549 * @flags: HBA port flags
550 */
551struct mpi3mr_hba_port {
552 struct list_head list;
553 u8 port_id;
554 u8 flags;
555};
556
557/**
558 * struct mpi3mr_sas_port - Internal SAS port information
559 * @port_list: List of ports belonging to a SAS node
560 * @num_phys: Number of phys associated with port
561 * @marked_responding: used while refresing the sas ports
562 * @lowest_phy: lowest phy ID of current sas port, valid for controller port
563 * @phy_mask: phy_mask of current sas port, valid for controller port
564 * @hba_port: HBA port entry
565 * @remote_identify: Attached device identification
566 * @rphy: SAS transport layer rphy object
567 * @port: SAS transport layer port object
568 * @phy_list: mpi3mr_sas_phy objects belonging to this port
569 */
570struct mpi3mr_sas_port {
571 struct list_head port_list;
572 u8 num_phys;
573 u8 marked_responding;
574 int lowest_phy;
575 u64 phy_mask;
576 struct mpi3mr_hba_port *hba_port;
577 struct sas_identify remote_identify;
578 struct sas_rphy *rphy;
579 struct sas_port *port;
580 struct list_head phy_list;
581};
582
583/**
584 * struct mpi3mr_sas_phy - Internal SAS Phy information
585 * @port_siblings: List of phys belonging to a port
586 * @identify: Phy identification
587 * @remote_identify: Attached device identification
588 * @phy: SAS transport layer Phy object
589 * @phy_id: Unique phy id within a port
590 * @handle: Firmware device handle for this phy
591 * @attached_handle: Firmware device handle for attached device
592 * @phy_belongs_to_port: Flag to indicate phy belongs to port
593 @hba_port: HBA port entry
594 */
595struct mpi3mr_sas_phy {
596 struct list_head port_siblings;
597 struct sas_identify identify;
598 struct sas_identify remote_identify;
599 struct sas_phy *phy;
600 u8 phy_id;
601 u16 handle;
602 u16 attached_handle;
603 u8 phy_belongs_to_port;
604 struct mpi3mr_hba_port *hba_port;
605};
606
607/**
608 * struct mpi3mr_sas_node - SAS host/expander information
609 * @list: List of sas nodes in a controller
610 * @parent_dev: Parent device class
611 * @num_phys: Number phys belonging to sas_node
612 * @sas_address: SAS address of sas_node
613 * @handle: Firmware device handle for this sas_host/expander
614 * @sas_address_parent: SAS address of parent expander or host
615 * @enclosure_handle: Firmware handle of enclosure of this node
616 * @device_info: Capabilities of this sas_host/expander
617 * @non_responding: used to refresh the expander devices during reset
618 * @host_node: Flag to indicate this is a host_node
619 * @hba_port: HBA port entry
620 * @phy: A list of phys that make up this sas_host/expander
621 * @sas_port_list: List of internal ports of this node
622 * @rphy: sas_rphy object of this expander node
623 */
624struct mpi3mr_sas_node {
625 struct list_head list;
626 struct device *parent_dev;
627 u8 num_phys;
628 u64 sas_address;
629 u16 handle;
630 u64 sas_address_parent;
631 u16 enclosure_handle;
632 u64 enclosure_logical_id;
633 u8 non_responding;
634 u8 host_node;
635 struct mpi3mr_hba_port *hba_port;
636 struct mpi3mr_sas_phy *phy;
637 struct list_head sas_port_list;
638 struct sas_rphy *rphy;
639};
640
641/**
642 * struct mpi3mr_enclosure_node - enclosure information
643 * @list: List of enclosures
644 * @pg0: Enclosure page 0;
645 */
646struct mpi3mr_enclosure_node {
647 struct list_head list;
648 struct mpi3_enclosure_page0 pg0;
649};
650
651/**
652 * struct tgt_dev_sas_sata - SAS/SATA device specific
653 * information cached from firmware given data
654 *
655 * @sas_address: World wide unique SAS address
656 * @sas_address_parent: Sas address of parent expander or host
657 * @dev_info: Device information bits
658 * @phy_id: Phy identifier provided in device page 0
659 * @attached_phy_id: Attached phy identifier provided in device page 0
660 * @negotiated_link_rate: Negotiated link rate from device page 0
661 * @sas_transport_attached: Is this device exposed to transport
662 * @pend_sas_rphy_add: Flag to check device is in process of add
663 * @hba_port: HBA port entry
664 * @rphy: SAS transport layer rphy object
665 */
666struct tgt_dev_sas_sata {
667 u64 sas_address;
668 u64 sas_address_parent;
669 u16 dev_info;
670 u8 phy_id;
671 u8 attached_phy_id;
672 u8 negotiated_link_rate;
673 u8 sas_transport_attached;
674 u8 pend_sas_rphy_add;
675 struct mpi3mr_hba_port *hba_port;
676 struct sas_rphy *rphy;
677};
678
679/**
680 * struct tgt_dev_pcie - PCIe device specific information cached
681 * from firmware given data
682 *
683 * @mdts: Maximum data transfer size
684 * @capb: Device capabilities
685 * @pgsz: Device page size
686 * @abort_to: Timeout for abort TM
687 * @reset_to: Timeout for Target/LUN reset TM
688 * @dev_info: Device information bits
689 */
690struct tgt_dev_pcie {
691 u32 mdts;
692 u16 capb;
693 u8 pgsz;
694 u8 abort_to;
695 u8 reset_to;
696 u16 dev_info;
697};
698
699/**
700 * struct tgt_dev_vd - virtual device specific information
701 * cached from firmware given data
702 *
703 * @state: State of the VD
704 * @tg_qd_reduction: Queue Depth reduction in units of 10%
705 * @tg_id: VDs throttle group ID
706 * @high: High limit to turn on throttling in 512 byte blocks
707 * @low: Low limit to turn off throttling in 512 byte blocks
708 * @tg: Pointer to throttle group info
709 */
710struct tgt_dev_vd {
711 u8 state;
712 u8 tg_qd_reduction;
713 u16 tg_id;
714 u32 tg_high;
715 u32 tg_low;
716 u8 abort_to;
717 u8 reset_to;
718 struct mpi3mr_throttle_group_info *tg;
719};
720
721
722/**
723 * union _form_spec_inf - union of device specific information
724 */
725union _form_spec_inf {
726 struct tgt_dev_sas_sata sas_sata_inf;
727 struct tgt_dev_pcie pcie_inf;
728 struct tgt_dev_vd vd_inf;
729};
730
731enum mpi3mr_dev_state {
732 MPI3MR_DEV_CREATED = 1,
733 MPI3MR_DEV_REMOVE_HS_STARTED = 2,
734 MPI3MR_DEV_DELETED = 3,
735};
736
737/**
738 * struct mpi3mr_tgt_dev - target device data structure
739 *
740 * @list: List pointer
741 * @starget: Scsi_target pointer
742 * @dev_handle: FW device handle
743 * @parent_handle: FW parent device handle
744 * @slot: Slot number
745 * @encl_handle: FW enclosure handle
746 * @perst_id: FW assigned Persistent ID
747 * @devpg0_flag: Device Page0 flag
748 * @dev_type: SAS/SATA/PCIE device type
749 * @is_hidden: Should be exposed to upper layers or not
750 * @host_exposed: Already exposed to host or not
751 * @io_unit_port: IO Unit port ID
752 * @non_stl: Is this device not to be attached with SAS TL
753 * @io_throttle_enabled: I/O throttling needed or not
754 * @wslen: Write same max length
755 * @q_depth: Device specific Queue Depth
756 * @wwid: World wide ID
757 * @enclosure_logical_id: Enclosure logical identifier
758 * @dev_spec: Device type specific information
759 * @abort_to: Timeout for abort TM
760 * @reset_to: Timeout for Target/LUN reset TM
761 * @ref_count: Reference count
762 * @state: device state
763 */
764struct mpi3mr_tgt_dev {
765 struct list_head list;
766 struct scsi_target *starget;
767 u16 dev_handle;
768 u16 parent_handle;
769 u16 slot;
770 u16 encl_handle;
771 u16 perst_id;
772 u16 devpg0_flag;
773 u8 dev_type;
774 u8 is_hidden;
775 u8 host_exposed;
776 u8 io_unit_port;
777 u8 non_stl;
778 u8 io_throttle_enabled;
779 u16 wslen;
780 u16 q_depth;
781 u64 wwid;
782 u64 enclosure_logical_id;
783 union _form_spec_inf dev_spec;
784 struct kref ref_count;
785 enum mpi3mr_dev_state state;
786};
787
788/**
789 * mpi3mr_tgtdev_get - k reference incrementor
790 * @s: Target device reference
791 *
792 * Increment target device reference count.
793 */
794static inline void mpi3mr_tgtdev_get(struct mpi3mr_tgt_dev *s)
795{
796 kref_get(&s->ref_count);
797}
798
799/**
800 * mpi3mr_free_tgtdev - target device memory dealloctor
801 * @r: k reference pointer of the target device
802 *
803 * Free target device memory when no reference.
804 */
805static inline void mpi3mr_free_tgtdev(struct kref *r)
806{
807 kfree(container_of(r, struct mpi3mr_tgt_dev, ref_count));
808}
809
810/**
811 * mpi3mr_tgtdev_put - k reference decrementor
812 * @s: Target device reference
813 *
814 * Decrement target device reference count.
815 */
816static inline void mpi3mr_tgtdev_put(struct mpi3mr_tgt_dev *s)
817{
818 kref_put(&s->ref_count, mpi3mr_free_tgtdev);
819}
820
821
822/**
823 * struct mpi3mr_stgt_priv_data - SCSI target private structure
824 *
825 * @starget: Scsi_target pointer
826 * @dev_handle: FW device handle
827 * @perst_id: FW assigned Persistent ID
828 * @num_luns: Number of Logical Units
829 * @block_io: I/O blocked to the device or not
830 * @dev_removed: Device removed in the Firmware
831 * @dev_removedelay: Device is waiting to be removed in FW
832 * @dev_type: Device type
833 * @dev_nvme_dif: Device is NVMe DIF enabled
834 * @wslen: Write same max length
835 * @io_throttle_enabled: I/O throttling needed or not
836 * @io_divert: Flag indicates io divert is on or off for the dev
837 * @throttle_group: Pointer to throttle group info
838 * @tgt_dev: Internal target device pointer
839 * @pend_count: Counter to track pending I/Os during error
840 * handling
841 */
842struct mpi3mr_stgt_priv_data {
843 struct scsi_target *starget;
844 u16 dev_handle;
845 u16 perst_id;
846 u32 num_luns;
847 atomic_t block_io;
848 u8 dev_removed;
849 u8 dev_removedelay;
850 u8 dev_type;
851 u8 dev_nvme_dif;
852 u16 wslen;
853 u8 io_throttle_enabled;
854 u8 io_divert;
855 struct mpi3mr_throttle_group_info *throttle_group;
856 struct mpi3mr_tgt_dev *tgt_dev;
857 u32 pend_count;
858};
859
860/**
861 * struct mpi3mr_stgt_priv_data - SCSI device private structure
862 *
863 * @tgt_priv_data: Scsi_target private data pointer
864 * @lun_id: LUN ID of the device
865 * @ncq_prio_enable: NCQ priority enable for SATA device
866 * @pend_count: Counter to track pending I/Os during error
867 * handling
868 * @wslen: Write same max length
869 */
870struct mpi3mr_sdev_priv_data {
871 struct mpi3mr_stgt_priv_data *tgt_priv_data;
872 u32 lun_id;
873 u8 ncq_prio_enable;
874 u32 pend_count;
875 u16 wslen;
876};
877
878/**
879 * struct mpi3mr_drv_cmd - Internal command tracker
880 *
881 * @mutex: Command mutex
882 * @done: Completeor for wakeup
883 * @reply: Firmware reply for internal commands
884 * @sensebuf: Sensebuf for SCSI IO commands
885 * @iou_rc: IO Unit control reason code
886 * @state: Command State
887 * @dev_handle: Firmware handle for device specific commands
888 * @ioc_status: IOC status from the firmware
889 * @ioc_loginfo:IOC log info from the firmware
890 * @is_waiting: Is the command issued in block mode
891 * @is_sense: Is Sense data present
892 * @retry_count: Retry count for retriable commands
893 * @host_tag: Host tag used by the command
894 * @callback: Callback for non blocking commands
895 */
896struct mpi3mr_drv_cmd {
897 struct mutex mutex;
898 struct completion done;
899 void *reply;
900 u8 *sensebuf;
901 u8 iou_rc;
902 u16 state;
903 u16 dev_handle;
904 u16 ioc_status;
905 u32 ioc_loginfo;
906 u8 is_waiting;
907 u8 is_sense;
908 u8 retry_count;
909 u16 host_tag;
910
911 void (*callback)(struct mpi3mr_ioc *mrioc,
912 struct mpi3mr_drv_cmd *drv_cmd);
913};
914
915/**
916 * union mpi3mr_trigger_data - Trigger data information
917 * @fault: Fault code
918 * @global: Global trigger data
919 * @element: element trigger data
920 */
921union mpi3mr_trigger_data {
922 u16 fault;
923 u64 global;
924 union mpi3_driver2_trigger_element element;
925};
926
927/**
928 * struct trigger_event_data - store trigger related
929 * information.
930 *
931 * @trace_hdb: Trace diag buffer descriptor reference
932 * @fw_hdb: FW diag buffer descriptor reference
933 * @trigger_type: Trigger type
934 * @trigger_specific_data: Trigger specific data
935 * @snapdump: Snapdump enable or disable flag
936 */
937struct trigger_event_data {
938 struct diag_buffer_desc *trace_hdb;
939 struct diag_buffer_desc *fw_hdb;
940 u8 trigger_type;
941 union mpi3mr_trigger_data trigger_specific_data;
942 bool snapdump;
943};
944
945/**
946 * struct diag_buffer_desc - memory descriptor structure to
947 * store virtual, dma addresses, size, buffer status for host
948 * diagnostic buffers.
949 *
950 * @type: Buffer type
951 * @trigger_data: Trigger data
952 * @trigger_type: Trigger type
953 * @status: Buffer status
954 * @size: Buffer size
955 * @addr: Virtual address
956 * @dma_addr: Buffer DMA address
957 * @is_segmented: The buffer is segmented or not
958 * @disabled_after_reset: The buffer is disabled after reset
959 */
960struct diag_buffer_desc {
961 u8 type;
962 union mpi3mr_trigger_data trigger_data;
963 u8 trigger_type;
964 u8 status;
965 u32 size;
966 void *addr;
967 dma_addr_t dma_addr;
968 bool is_segmented;
969 bool disabled_after_reset;
970};
971
972/**
973 * struct dma_memory_desc - memory descriptor structure to store
974 * virtual address, dma address and size for any generic dma
975 * memory allocations in the driver.
976 *
977 * @size: buffer size
978 * @addr: virtual address
979 * @dma_addr: dma address
980 */
981struct dma_memory_desc {
982 u32 size;
983 void *addr;
984 dma_addr_t dma_addr;
985};
986
987
988/**
989 * struct chain_element - memory descriptor structure to store
990 * virtual and dma addresses for chain elements.
991 *
992 * @addr: virtual address
993 * @dma_addr: dma address
994 */
995struct chain_element {
996 void *addr;
997 dma_addr_t dma_addr;
998};
999
1000/**
1001 * struct scmd_priv - SCSI command private data
1002 *
1003 * @host_tag: Host tag specific to operational queue
1004 * @in_lld_scope: Command in LLD scope or not
1005 * @meta_sg_valid: DIX command with meta data SGL or not
1006 * @scmd: SCSI Command pointer
1007 * @req_q_idx: Operational request queue index
1008 * @chain_idx: Chain frame index
1009 * @meta_chain_idx: Chain frame index of meta data SGL
1010 * @mpi3mr_scsiio_req: MPI SCSI IO request
1011 */
1012struct scmd_priv {
1013 u16 host_tag;
1014 u8 in_lld_scope;
1015 u8 meta_sg_valid;
1016 struct scsi_cmnd *scmd;
1017 u16 req_q_idx;
1018 int chain_idx;
1019 int meta_chain_idx;
1020 u8 mpi3mr_scsiio_req[MPI3MR_ADMIN_REQ_FRAME_SZ];
1021};
1022
1023/**
1024 * struct mpi3mr_ioc - Adapter anchor structure stored in shost
1025 * private data
1026 *
1027 * @list: List pointer
1028 * @pdev: PCI device pointer
1029 * @shost: Scsi_Host pointer
1030 * @id: Controller ID
1031 * @cpu_count: Number of online CPUs
1032 * @irqpoll_sleep: usleep unit used in threaded isr irqpoll
1033 * @name: Controller ASCII name
1034 * @driver_name: Driver ASCII name
1035 * @sysif_regs: System interface registers virtual address
1036 * @sysif_regs_phys: System interface registers physical address
1037 * @bars: PCI BARS
1038 * @dma_mask: DMA mask
1039 * @msix_count: Number of MSIX vectors used
1040 * @intr_enabled: Is interrupts enabled
1041 * @num_admin_req: Number of admin requests
1042 * @admin_req_q_sz: Admin request queue size
1043 * @admin_req_pi: Admin request queue producer index
1044 * @admin_req_ci: Admin request queue consumer index
1045 * @admin_req_base: Admin request queue base virtual address
1046 * @admin_req_dma: Admin request queue base dma address
1047 * @admin_req_lock: Admin queue access lock
1048 * @num_admin_replies: Number of admin replies
1049 * @admin_reply_q_sz: Admin reply queue size
1050 * @admin_reply_ci: Admin reply queue consumer index
1051 * @admin_reply_ephase:Admin reply queue expected phase
1052 * @admin_reply_base: Admin reply queue base virtual address
1053 * @admin_reply_dma: Admin reply queue base dma address
1054 * @admin_reply_q_in_use: Queue is handled by poll/ISR
1055 * @admin_pend_isr: Count of unprocessed admin ISR/poll calls
1056 * due to another thread processing replies
1057 * @ready_timeout: Controller ready timeout
1058 * @intr_info: Interrupt cookie pointer
1059 * @intr_info_count: Number of interrupt cookies
1060 * @is_intr_info_set: Flag to indicate intr info is setup
1061 * @num_queues: Number of operational queues
1062 * @num_op_req_q: Number of operational request queues
1063 * @req_qinfo: Operational request queue info pointer
1064 * @num_op_reply_q: Number of operational reply queues
1065 * @op_reply_qinfo: Operational reply queue info pointer
1066 * @init_cmds: Command tracker for initialization commands
1067 * @cfg_cmds: Command tracker for configuration requests
1068 * @facts: Cached IOC facts data
1069 * @op_reply_desc_sz: Operational reply descriptor size
1070 * @num_reply_bufs: Number of reply buffers allocated
1071 * @reply_buf_pool: Reply buffer pool
1072 * @reply_buf: Reply buffer base virtual address
1073 * @reply_buf_dma: Reply buffer DMA address
1074 * @reply_buf_dma_max_address: Reply DMA address max limit
1075 * @reply_free_qsz: Reply free queue size
1076 * @reply_free_q_pool: Reply free queue pool
1077 * @reply_free_q: Reply free queue base virtual address
1078 * @reply_free_q_dma: Reply free queue base DMA address
1079 * @reply_free_queue_lock: Reply free queue lock
1080 * @reply_free_queue_host_index: Reply free queue host index
1081 * @num_sense_bufs: Number of sense buffers
1082 * @sense_buf_pool: Sense buffer pool
1083 * @sense_buf: Sense buffer base virtual address
1084 * @sense_buf_dma: Sense buffer base DMA address
1085 * @sense_buf_q_sz: Sense buffer queue size
1086 * @sense_buf_q_pool: Sense buffer queue pool
1087 * @sense_buf_q: Sense buffer queue virtual address
1088 * @sense_buf_q_dma: Sense buffer queue DMA address
1089 * @sbq_lock: Sense buffer queue lock
1090 * @sbq_host_index: Sense buffer queuehost index
1091 * @event_masks: Event mask bitmap
1092 * @fwevt_worker_thread: Firmware event worker thread
1093 * @fwevt_lock: Firmware event lock
1094 * @fwevt_list: Firmware event list
1095 * @watchdog_work_q: Fault watchdog worker thread
1096 * @watchdog_work: Fault watchdog work
1097 * @watchdog_lock: Fault watchdog lock
1098 * @is_driver_loading: Is driver still loading
1099 * @scan_started: Async scan started
1100 * @scan_failed: Asycn scan failed
1101 * @stop_drv_processing: Stop all command processing
1102 * @device_refresh_on: Don't process the events until devices are refreshed
1103 * @max_host_ios: Maximum host I/O count
1104 * @max_sgl_entries: Max SGL entries per I/O
1105 * @chain_buf_count: Chain buffer count
1106 * @chain_buf_pool: Chain buffer pool
1107 * @chain_sgl_list: Chain SGL list
1108 * @chain_bitmap: Chain buffer allocator bitmap
1109 * @chain_buf_lock: Chain buffer list lock
1110 * @bsg_cmds: Command tracker for BSG command
1111 * @host_tm_cmds: Command tracker for task management commands
1112 * @dev_rmhs_cmds: Command tracker for device removal commands
1113 * @evtack_cmds: Command tracker for event ack commands
1114 * @devrem_bitmap: Device removal bitmap
1115 * @dev_handle_bitmap_bits: Number of bits in device handle bitmap
1116 * @removepend_bitmap: Remove pending bitmap
1117 * @delayed_rmhs_list: Delayed device removal list
1118 * @evtack_cmds_bitmap: Event Ack bitmap
1119 * @delayed_evtack_cmds_list: Delayed event acknowledgment list
1120 * @ts_update_counter: Timestamp update counter
1121 * @ts_update_interval: Timestamp update interval
1122 * @reset_in_progress: Reset in progress flag
1123 * @unrecoverable: Controller unrecoverable flag
1124 * @io_admin_reset_sync: Manage state of I/O ops during an admin reset process
1125 * @prev_reset_result: Result of previous reset
1126 * @reset_mutex: Controller reset mutex
1127 * @reset_waitq: Controller reset wait queue
1128 * @prepare_for_reset: Prepare for reset event received
1129 * @prepare_for_reset_timeout_counter: Prepare for reset timeout
1130 * @prp_list_virt: NVMe encapsulated PRP list virtual base
1131 * @prp_list_dma: NVMe encapsulated PRP list DMA
1132 * @prp_sz: NVME encapsulated PRP list size
1133 * @diagsave_timeout: Diagnostic information save timeout
1134 * @logging_level: Controller debug logging level
1135 * @flush_io_count: I/O count to flush after reset
1136 * @current_event: Firmware event currently in process
1137 * @driver_info: Driver, Kernel, OS information to firmware
1138 * @change_count: Topology change count
1139 * @pel_enabled: Persistent Event Log(PEL) enabled or not
1140 * @pel_abort_requested: PEL abort is requested or not
1141 * @pel_class: PEL Class identifier
1142 * @pel_locale: PEL Locale identifier
1143 * @pel_cmds: Command tracker for PEL wait command
1144 * @pel_abort_cmd: Command tracker for PEL abort command
1145 * @pel_newest_seqnum: Newest PEL sequenece number
1146 * @pel_seqnum_virt: PEL sequence number virtual address
1147 * @pel_seqnum_dma: PEL sequence number DMA address
1148 * @pel_seqnum_sz: PEL sequenece number size
1149 * @op_reply_q_offset: Operational reply queue offset with MSIx
1150 * @default_qcount: Total Default queues
1151 * @active_poll_qcount: Currently active poll queue count
1152 * @requested_poll_qcount: User requested poll queue count
1153 * @fault_during_init: Indicates a firmware fault occurred during initialization
1154 * @saved_fault_code: Firmware fault code captured at the time of failure
1155 * @saved_fault_info: Additional firmware-provided fault information
1156 * @fwfault_counter: Count of firmware faults detected by the driver
1157 * @bsg_dev: BSG device structure
1158 * @bsg_queue: Request queue for BSG device
1159 * @stop_bsgs: Stop BSG request flag
1160 * @logdata_buf: Circular buffer to store log data entries
1161 * @logdata_buf_idx: Index of entry in buffer to store
1162 * @logdata_entry_sz: log data entry size
1163 * @adm_req_q_bar_writeq_lock: Admin request queue lock
1164 * @adm_reply_q_bar_writeq_lock: Admin reply queue lock
1165 * @pend_large_data_sz: Counter to track pending large data
1166 * @io_throttle_data_length: I/O size to track in 512b blocks
1167 * @io_throttle_high: I/O size to start throttle in 512b blocks
1168 * @io_throttle_low: I/O size to stop throttle in 512b blocks
1169 * @num_io_throttle_group: Maximum number of throttle groups
1170 * @throttle_groups: Pointer to throttle group info structures
1171 * @sas_transport_enabled: SAS transport enabled or not
1172 * @scsi_device_channel: Channel ID for SCSI devices
1173 * @transport_cmds: Command tracker for SAS transport commands
1174 * @sas_hba: SAS node for the controller
1175 * @sas_expander_list: SAS node list of expanders
1176 * @sas_node_lock: Lock to protect SAS node list
1177 * @hba_port_table_list: List of HBA Ports
1178 * @enclosure_list: List of Enclosure objects
1179 * @diag_buffers: Host diagnostic buffers
1180 * @driver_pg2: Driver page 2 pointer
1181 * @reply_trigger_present: Reply trigger present flag
1182 * @event_trigger_present: Event trigger present flag
1183 * @scsisense_trigger_present: Scsi sense trigger present flag
1184 * @ioctl_dma_pool: DMA pool for IOCTL data buffers
1185 * @ioctl_sge: DMA buffer descriptors for IOCTL data
1186 * @ioctl_chain_sge: DMA buffer descriptor for IOCTL chain
1187 * @ioctl_resp_sge: DMA buffer descriptor for Mgmt cmd response
1188 * @ioctl_sges_allocated: Flag for IOCTL SGEs allocated or not
1189 * @trace_release_trigger_active: Trace trigger active flag
1190 * @fw_release_trigger_active: Fw release trigger active flag
1191 * @snapdump_trigger_active: Snapdump trigger active flag
1192 * @pci_err_recovery: PCI error recovery in progress
1193 * @block_on_pci_err: Block IO during PCI error recovery
1194 * @reply_qfull_count: Occurences of reply queue full avoidance kicking-in
1195 * @prevent_reply_qfull: Enable reply queue prevention
1196 * @seg_tb_support: Segmented trace buffer support
1197 * @num_tb_segs: Number of Segments in Trace buffer
1198 * @trace_buf_pool: DMA pool for Segmented trace buffer segments
1199 * @trace_buf: Trace buffer segments memory descriptor
1200 * @invalid_io_comp: Invalid IO completion
1201 */
1202struct mpi3mr_ioc {
1203 struct list_head list;
1204 struct pci_dev *pdev;
1205 struct Scsi_Host *shost;
1206 u8 id;
1207 int cpu_count;
1208 bool enable_segqueue;
1209 u32 irqpoll_sleep;
1210
1211 char name[MPI3MR_NAME_LENGTH];
1212 char driver_name[MPI3MR_NAME_LENGTH];
1213
1214 struct mpi3_sysif_registers __iomem *sysif_regs;
1215 resource_size_t sysif_regs_phys;
1216 int bars;
1217 u64 dma_mask;
1218
1219 u16 msix_count;
1220 u8 intr_enabled;
1221
1222 u16 num_admin_req;
1223 u32 admin_req_q_sz;
1224 u16 admin_req_pi;
1225 u16 admin_req_ci;
1226 void *admin_req_base;
1227 dma_addr_t admin_req_dma;
1228 spinlock_t admin_req_lock;
1229
1230 u16 num_admin_replies;
1231 u32 admin_reply_q_sz;
1232 u16 admin_reply_ci;
1233 u8 admin_reply_ephase;
1234 void *admin_reply_base;
1235 dma_addr_t admin_reply_dma;
1236 atomic_t admin_reply_q_in_use;
1237 atomic_t admin_pend_isr;
1238
1239 u32 ready_timeout;
1240
1241 struct mpi3mr_intr_info *intr_info;
1242 u16 intr_info_count;
1243 bool is_intr_info_set;
1244
1245 u16 num_queues;
1246 u16 num_op_req_q;
1247 struct op_req_qinfo *req_qinfo;
1248
1249 u16 num_op_reply_q;
1250 struct op_reply_qinfo *op_reply_qinfo;
1251
1252 struct mpi3mr_drv_cmd init_cmds;
1253 struct mpi3mr_drv_cmd cfg_cmds;
1254 struct mpi3mr_ioc_facts facts;
1255 u16 op_reply_desc_sz;
1256
1257 u32 num_reply_bufs;
1258 struct dma_pool *reply_buf_pool;
1259 u8 *reply_buf;
1260 dma_addr_t reply_buf_dma;
1261 dma_addr_t reply_buf_dma_max_address;
1262
1263 u16 reply_free_qsz;
1264 u16 reply_sz;
1265 struct dma_pool *reply_free_q_pool;
1266 __le64 *reply_free_q;
1267 dma_addr_t reply_free_q_dma;
1268 spinlock_t reply_free_queue_lock;
1269 u32 reply_free_queue_host_index;
1270
1271 u32 num_sense_bufs;
1272 struct dma_pool *sense_buf_pool;
1273 u8 *sense_buf;
1274 dma_addr_t sense_buf_dma;
1275
1276 u16 sense_buf_q_sz;
1277 struct dma_pool *sense_buf_q_pool;
1278 __le64 *sense_buf_q;
1279 dma_addr_t sense_buf_q_dma;
1280 spinlock_t sbq_lock;
1281 u32 sbq_host_index;
1282 u32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS];
1283
1284 struct workqueue_struct *fwevt_worker_thread;
1285 spinlock_t fwevt_lock;
1286 struct list_head fwevt_list;
1287
1288 struct workqueue_struct *watchdog_work_q;
1289 struct delayed_work watchdog_work;
1290 spinlock_t watchdog_lock;
1291
1292 u8 is_driver_loading;
1293 u8 scan_started;
1294 u16 scan_failed;
1295 u8 stop_drv_processing;
1296 u8 device_refresh_on;
1297
1298 u16 max_host_ios;
1299 spinlock_t tgtdev_lock;
1300 struct list_head tgtdev_list;
1301 u16 max_sgl_entries;
1302
1303 u32 chain_buf_count;
1304 struct dma_pool *chain_buf_pool;
1305 struct chain_element *chain_sgl_list;
1306 unsigned long *chain_bitmap;
1307 spinlock_t chain_buf_lock;
1308
1309 struct mpi3mr_drv_cmd bsg_cmds;
1310 struct mpi3mr_drv_cmd host_tm_cmds;
1311 struct mpi3mr_drv_cmd dev_rmhs_cmds[MPI3MR_NUM_DEVRMCMD];
1312 struct mpi3mr_drv_cmd evtack_cmds[MPI3MR_NUM_EVTACKCMD];
1313 unsigned long *devrem_bitmap;
1314 u16 dev_handle_bitmap_bits;
1315 unsigned long *removepend_bitmap;
1316 struct list_head delayed_rmhs_list;
1317 unsigned long *evtack_cmds_bitmap;
1318 struct list_head delayed_evtack_cmds_list;
1319
1320 u16 ts_update_counter;
1321 u16 ts_update_interval;
1322 u8 reset_in_progress;
1323 u8 unrecoverable;
1324 u8 io_admin_reset_sync;
1325 int prev_reset_result;
1326 struct mutex reset_mutex;
1327 wait_queue_head_t reset_waitq;
1328
1329 u8 prepare_for_reset;
1330 u16 prepare_for_reset_timeout_counter;
1331
1332 void *prp_list_virt;
1333 dma_addr_t prp_list_dma;
1334 u32 prp_sz;
1335
1336 u16 diagsave_timeout;
1337 int logging_level;
1338 u16 flush_io_count;
1339
1340 struct mpi3mr_fwevt *current_event;
1341 struct mpi3_driver_info_layout driver_info;
1342 u16 change_count;
1343
1344 u8 pel_enabled;
1345 u8 pel_abort_requested;
1346 u8 pel_class;
1347 u16 pel_locale;
1348 struct mpi3mr_drv_cmd pel_cmds;
1349 struct mpi3mr_drv_cmd pel_abort_cmd;
1350
1351 u32 pel_newest_seqnum;
1352 void *pel_seqnum_virt;
1353 dma_addr_t pel_seqnum_dma;
1354 u32 pel_seqnum_sz;
1355
1356 u16 op_reply_q_offset;
1357 u16 default_qcount;
1358 u16 active_poll_qcount;
1359 u16 requested_poll_qcount;
1360 u8 fault_during_init;
1361 u32 saved_fault_code;
1362 u32 saved_fault_info[3];
1363 u64 fwfault_counter;
1364
1365 struct device bsg_dev;
1366 struct request_queue *bsg_queue;
1367 u8 stop_bsgs;
1368 u8 *logdata_buf;
1369 u16 logdata_buf_idx;
1370 u16 logdata_entry_sz;
1371 spinlock_t adm_req_q_bar_writeq_lock;
1372 spinlock_t adm_reply_q_bar_writeq_lock;
1373
1374 atomic_t pend_large_data_sz;
1375 u32 io_throttle_data_length;
1376 u32 io_throttle_high;
1377 u32 io_throttle_low;
1378 u16 num_io_throttle_group;
1379 struct mpi3mr_throttle_group_info *throttle_groups;
1380
1381 u8 sas_transport_enabled;
1382 u8 scsi_device_channel;
1383 struct mpi3mr_drv_cmd transport_cmds;
1384 struct mpi3mr_sas_node sas_hba;
1385 struct list_head sas_expander_list;
1386 spinlock_t sas_node_lock;
1387 struct list_head hba_port_table_list;
1388 struct list_head enclosure_list;
1389
1390 struct dma_pool *ioctl_dma_pool;
1391 struct dma_memory_desc ioctl_sge[MPI3MR_NUM_IOCTL_SGE];
1392 struct dma_memory_desc ioctl_chain_sge;
1393 struct dma_memory_desc ioctl_resp_sge;
1394 bool ioctl_sges_allocated;
1395 bool reply_trigger_present;
1396 bool event_trigger_present;
1397 bool scsisense_trigger_present;
1398 struct diag_buffer_desc diag_buffers[MPI3MR_MAX_NUM_HDB];
1399 struct mpi3_driver_page2 *driver_pg2;
1400 spinlock_t trigger_lock;
1401 bool snapdump_trigger_active;
1402 bool trace_release_trigger_active;
1403 bool fw_release_trigger_active;
1404 bool pci_err_recovery;
1405 bool block_on_pci_err;
1406 atomic_t reply_qfull_count;
1407 bool prevent_reply_qfull;
1408 bool seg_tb_support;
1409 u32 num_tb_segs;
1410 struct dma_pool *trace_buf_pool;
1411 struct segments *trace_buf;
1412 u8 invalid_io_comp;
1413
1414};
1415
1416/**
1417 * struct mpi3mr_fwevt - Firmware event structure.
1418 *
1419 * @list: list head
1420 * @work: Work structure
1421 * @mrioc: Adapter instance reference
1422 * @event_id: MPI3 firmware event ID
1423 * @send_ack: Event acknowledgment required or not
1424 * @process_evt: Bottomhalf processing required or not
1425 * @evt_ctx: Event context to send in Ack
1426 * @event_data_size: size of the event data in bytes
1427 * @pending_at_sml: waiting for device add/remove API to complete
1428 * @discard: discard this event
1429 * @ref_count: kref count
1430 * @event_data: Actual MPI3 event data
1431 */
1432struct mpi3mr_fwevt {
1433 struct list_head list;
1434 struct work_struct work;
1435 struct mpi3mr_ioc *mrioc;
1436 u16 event_id;
1437 bool send_ack;
1438 bool process_evt;
1439 u32 evt_ctx;
1440 u16 event_data_size;
1441 bool pending_at_sml;
1442 bool discard;
1443 struct kref ref_count;
1444 char event_data[] __aligned(4);
1445};
1446
1447
1448/**
1449 * struct delayed_dev_rmhs_node - Delayed device removal node
1450 *
1451 * @list: list head
1452 * @handle: Device handle
1453 * @iou_rc: IO Unit Control Reason Code
1454 */
1455struct delayed_dev_rmhs_node {
1456 struct list_head list;
1457 u16 handle;
1458 u8 iou_rc;
1459};
1460
1461/**
1462 * struct delayed_evt_ack_node - Delayed event ack node
1463 * @list: list head
1464 * @event: MPI3 event ID
1465 * @event_ctx: event context
1466 */
1467struct delayed_evt_ack_node {
1468 struct list_head list;
1469 u8 event;
1470 u32 event_ctx;
1471};
1472
1473int mpi3mr_setup_resources(struct mpi3mr_ioc *mrioc);
1474void mpi3mr_cleanup_resources(struct mpi3mr_ioc *mrioc);
1475int mpi3mr_init_ioc(struct mpi3mr_ioc *mrioc);
1476int mpi3mr_reinit_ioc(struct mpi3mr_ioc *mrioc, u8 is_resume);
1477void mpi3mr_cleanup_ioc(struct mpi3mr_ioc *mrioc);
1478int mpi3mr_issue_port_enable(struct mpi3mr_ioc *mrioc, u8 async);
1479int mpi3mr_admin_request_post(struct mpi3mr_ioc *mrioc, void *admin_req,
1480u16 admin_req_sz, u8 ignore_reset);
1481int mpi3mr_op_request_post(struct mpi3mr_ioc *mrioc,
1482 struct op_req_qinfo *opreqq, u8 *req);
1483void mpi3mr_add_sg_single(void *paddr, u8 flags, u32 length,
1484 dma_addr_t dma_addr);
1485void mpi3mr_build_zero_len_sge(void *paddr);
1486void *mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_ioc *mrioc,
1487 dma_addr_t phys_addr);
1488void *mpi3mr_get_reply_virt_addr(struct mpi3mr_ioc *mrioc,
1489 dma_addr_t phys_addr);
1490void mpi3mr_repost_sense_buf(struct mpi3mr_ioc *mrioc,
1491 u64 sense_buf_dma);
1492
1493void mpi3mr_memset_buffers(struct mpi3mr_ioc *mrioc);
1494void mpi3mr_free_mem(struct mpi3mr_ioc *mrioc);
1495void mpi3mr_os_handle_events(struct mpi3mr_ioc *mrioc,
1496 struct mpi3_event_notification_reply *event_reply);
1497void mpi3mr_process_op_reply_desc(struct mpi3mr_ioc *mrioc,
1498 struct mpi3_default_reply_descriptor *reply_desc,
1499 u64 *reply_dma, u16 qidx);
1500void mpi3mr_start_watchdog(struct mpi3mr_ioc *mrioc);
1501void mpi3mr_stop_watchdog(struct mpi3mr_ioc *mrioc);
1502
1503int mpi3mr_soft_reset_handler(struct mpi3mr_ioc *mrioc,
1504 u16 reset_reason, u8 snapdump);
1505void mpi3mr_ioc_disable_intr(struct mpi3mr_ioc *mrioc);
1506void mpi3mr_ioc_enable_intr(struct mpi3mr_ioc *mrioc);
1507
1508enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_ioc *mrioc);
1509int mpi3mr_process_event_ack(struct mpi3mr_ioc *mrioc, u8 event,
1510 u32 event_ctx);
1511
1512void mpi3mr_wait_for_host_io(struct mpi3mr_ioc *mrioc, u32 timeout);
1513void mpi3mr_cleanup_fwevt_list(struct mpi3mr_ioc *mrioc);
1514void mpi3mr_flush_host_io(struct mpi3mr_ioc *mrioc);
1515void mpi3mr_invalidate_devhandles(struct mpi3mr_ioc *mrioc);
1516void mpi3mr_flush_delayed_cmd_lists(struct mpi3mr_ioc *mrioc);
1517void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code);
1518void mpi3mr_print_fault_info(struct mpi3mr_ioc *mrioc);
1519void mpi3mr_check_rh_fault_ioc(struct mpi3mr_ioc *mrioc, u32 reason_code);
1520int mpi3mr_process_op_reply_q(struct mpi3mr_ioc *mrioc,
1521 struct op_reply_qinfo *op_reply_q);
1522int mpi3mr_blk_mq_poll(struct Scsi_Host *shost, unsigned int queue_num);
1523void mpi3mr_bsg_init(struct mpi3mr_ioc *mrioc);
1524void mpi3mr_bsg_exit(struct mpi3mr_ioc *mrioc);
1525int mpi3mr_issue_tm(struct mpi3mr_ioc *mrioc, u8 tm_type,
1526 u16 handle, uint lun, u16 htag, ulong timeout,
1527 struct mpi3mr_drv_cmd *drv_cmd,
1528 u8 *resp_code, struct scsi_cmnd *scmd);
1529struct mpi3mr_tgt_dev *mpi3mr_get_tgtdev_by_handle(
1530 struct mpi3mr_ioc *mrioc, u16 handle);
1531void mpi3mr_pel_get_seqnum_complete(struct mpi3mr_ioc *mrioc,
1532 struct mpi3mr_drv_cmd *drv_cmd);
1533int mpi3mr_pel_get_seqnum_post(struct mpi3mr_ioc *mrioc,
1534 struct mpi3mr_drv_cmd *drv_cmd);
1535void mpi3mr_app_save_logdata_th(struct mpi3mr_ioc *mrioc, char *event_data,
1536 u16 event_data_size);
1537struct mpi3mr_enclosure_node *mpi3mr_enclosure_find_by_handle(
1538 struct mpi3mr_ioc *mrioc, u16 handle);
1539extern const struct attribute_group *mpi3mr_host_groups[];
1540extern const struct attribute_group *mpi3mr_dev_groups[];
1541
1542extern struct sas_function_template mpi3mr_transport_functions;
1543extern struct scsi_transport_template *mpi3mr_transport_template;
1544
1545int mpi3mr_cfg_get_dev_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
1546 struct mpi3_device_page0 *dev_pg0, u16 pg_sz, u32 form, u32 form_spec);
1547int mpi3mr_cfg_get_sas_phy_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
1548 struct mpi3_sas_phy_page0 *phy_pg0, u16 pg_sz, u32 form,
1549 u32 form_spec);
1550int mpi3mr_cfg_get_sas_phy_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
1551 struct mpi3_sas_phy_page1 *phy_pg1, u16 pg_sz, u32 form,
1552 u32 form_spec);
1553int mpi3mr_cfg_get_sas_exp_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
1554 struct mpi3_sas_expander_page0 *exp_pg0, u16 pg_sz, u32 form,
1555 u32 form_spec);
1556int mpi3mr_cfg_get_sas_exp_pg1(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
1557 struct mpi3_sas_expander_page1 *exp_pg1, u16 pg_sz, u32 form,
1558 u32 form_spec);
1559int mpi3mr_cfg_get_enclosure_pg0(struct mpi3mr_ioc *mrioc, u16 *ioc_status,
1560 struct mpi3_enclosure_page0 *encl_pg0, u16 pg_sz, u32 form,
1561 u32 form_spec);
1562int mpi3mr_cfg_get_sas_io_unit_pg0(struct mpi3mr_ioc *mrioc,
1563 struct mpi3_sas_io_unit_page0 *sas_io_unit_pg0, u16 pg_sz);
1564int mpi3mr_cfg_get_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc,
1565 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz);
1566int mpi3mr_cfg_set_sas_io_unit_pg1(struct mpi3mr_ioc *mrioc,
1567 struct mpi3_sas_io_unit_page1 *sas_io_unit_pg1, u16 pg_sz);
1568int mpi3mr_cfg_get_driver_pg1(struct mpi3mr_ioc *mrioc,
1569 struct mpi3_driver_page1 *driver_pg1, u16 pg_sz);
1570int mpi3mr_cfg_get_driver_pg2(struct mpi3mr_ioc *mrioc,
1571 struct mpi3_driver_page2 *driver_pg2, u16 pg_sz, u8 page_type);
1572
1573u8 mpi3mr_is_expander_device(u16 device_info);
1574int mpi3mr_expander_add(struct mpi3mr_ioc *mrioc, u16 handle);
1575void mpi3mr_expander_remove(struct mpi3mr_ioc *mrioc, u64 sas_address,
1576 struct mpi3mr_hba_port *hba_port);
1577struct mpi3mr_sas_node *__mpi3mr_expander_find_by_handle(struct mpi3mr_ioc
1578 *mrioc, u16 handle);
1579struct mpi3mr_hba_port *mpi3mr_get_hba_port_by_id(struct mpi3mr_ioc *mrioc,
1580 u8 port_id);
1581void mpi3mr_sas_host_refresh(struct mpi3mr_ioc *mrioc);
1582void mpi3mr_sas_host_add(struct mpi3mr_ioc *mrioc);
1583void mpi3mr_update_links(struct mpi3mr_ioc *mrioc,
1584 u64 sas_address_parent, u16 handle, u8 phy_number, u8 link_rate,
1585 struct mpi3mr_hba_port *hba_port);
1586void mpi3mr_remove_tgtdev_from_host(struct mpi3mr_ioc *mrioc,
1587 struct mpi3mr_tgt_dev *tgtdev);
1588int mpi3mr_report_tgtdev_to_sas_transport(struct mpi3mr_ioc *mrioc,
1589 struct mpi3mr_tgt_dev *tgtdev);
1590void mpi3mr_remove_tgtdev_from_sas_transport(struct mpi3mr_ioc *mrioc,
1591 struct mpi3mr_tgt_dev *tgtdev);
1592struct mpi3mr_tgt_dev *__mpi3mr_get_tgtdev_by_addr_and_rphy(
1593 struct mpi3mr_ioc *mrioc, u64 sas_address, struct sas_rphy *rphy);
1594void mpi3mr_print_device_event_notice(struct mpi3mr_ioc *mrioc,
1595 bool device_add);
1596void mpi3mr_refresh_sas_ports(struct mpi3mr_ioc *mrioc);
1597void mpi3mr_refresh_expanders(struct mpi3mr_ioc *mrioc);
1598void mpi3mr_add_event_wait_for_device_refresh(struct mpi3mr_ioc *mrioc);
1599void mpi3mr_flush_drv_cmds(struct mpi3mr_ioc *mrioc);
1600void mpi3mr_flush_cmds_for_unrecovered_controller(struct mpi3mr_ioc *mrioc);
1601void mpi3mr_free_enclosure_list(struct mpi3mr_ioc *mrioc);
1602int mpi3mr_process_admin_reply_q(struct mpi3mr_ioc *mrioc);
1603void mpi3mr_expander_node_remove(struct mpi3mr_ioc *mrioc,
1604 struct mpi3mr_sas_node *sas_expander);
1605void mpi3mr_alloc_diag_bufs(struct mpi3mr_ioc *mrioc);
1606int mpi3mr_post_diag_bufs(struct mpi3mr_ioc *mrioc);
1607int mpi3mr_issue_diag_buf_release(struct mpi3mr_ioc *mrioc,
1608 struct diag_buffer_desc *diag_buffer);
1609void mpi3mr_release_diag_bufs(struct mpi3mr_ioc *mrioc, u8 skip_rel_action);
1610void mpi3mr_set_trigger_data_in_hdb(struct diag_buffer_desc *hdb,
1611 u8 type, union mpi3mr_trigger_data *trigger_data, bool force);
1612int mpi3mr_refresh_trigger(struct mpi3mr_ioc *mrioc, u8 page_type);
1613struct diag_buffer_desc *mpi3mr_diag_buffer_for_type(struct mpi3mr_ioc *mrioc,
1614 u8 buf_type);
1615int mpi3mr_issue_diag_buf_post(struct mpi3mr_ioc *mrioc,
1616 struct diag_buffer_desc *diag_buffer);
1617void mpi3mr_set_trigger_data_in_all_hdb(struct mpi3mr_ioc *mrioc,
1618 u8 type, union mpi3mr_trigger_data *trigger_data, bool force);
1619void mpi3mr_reply_trigger(struct mpi3mr_ioc *mrioc, u16 iocstatus,
1620 u32 iocloginfo);
1621void mpi3mr_hdb_trigger_data_event(struct mpi3mr_ioc *mrioc,
1622 struct trigger_event_data *event_data);
1623void mpi3mr_scsisense_trigger(struct mpi3mr_ioc *mrioc, u8 senseky, u8 asc,
1624 u8 ascq);
1625void mpi3mr_event_trigger(struct mpi3mr_ioc *mrioc, u8 event);
1626void mpi3mr_global_trigger(struct mpi3mr_ioc *mrioc, u64 trigger_data);
1627void mpi3mr_hdbstatuschg_evt_th(struct mpi3mr_ioc *mrioc,
1628 struct mpi3_event_notification_reply *event_reply);
1629#endif /*MPI3MR_H_INCLUDED*/