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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * drivers/usb/host/ehci-orion.c
4 *
5 * Tzachi Perelstein <tzachi@marvell.com>
6 */
7
8#include <linux/kernel.h>
9#include <linux/module.h>
10#include <linux/platform_device.h>
11#include <linux/mbus.h>
12#include <linux/clk.h>
13#include <linux/platform_data/usb-ehci-orion.h>
14#include <linux/of.h>
15#include <linux/usb.h>
16#include <linux/usb/hcd.h>
17#include <linux/io.h>
18#include <linux/dma-mapping.h>
19
20#include "ehci.h"
21
22#define rdl(off) readl_relaxed(hcd->regs + (off))
23#define wrl(off, val) writel_relaxed((val), hcd->regs + (off))
24
25#define USB_CMD 0x140
26#define USB_CMD_RUN BIT(0)
27#define USB_CMD_RESET BIT(1)
28#define USB_MODE 0x1a8
29#define USB_MODE_MASK GENMASK(1, 0)
30#define USB_MODE_DEVICE 0x2
31#define USB_MODE_HOST 0x3
32#define USB_MODE_SDIS BIT(4)
33#define USB_CAUSE 0x310
34#define USB_MASK 0x314
35#define USB_WINDOW_CTRL(i) (0x320 + ((i) << 4))
36#define USB_WINDOW_BASE(i) (0x324 + ((i) << 4))
37#define USB_IPG 0x360
38#define USB_PHY_PWR_CTRL 0x400
39#define USB_PHY_TX_CTRL 0x420
40#define USB_PHY_RX_CTRL 0x430
41#define USB_PHY_IVREF_CTRL 0x440
42#define USB_PHY_TST_GRP_CTRL 0x450
43
44#define USB_SBUSCFG 0x90
45
46/* BAWR = BARD = 3 : Align read/write bursts packets larger than 128 bytes */
47#define USB_SBUSCFG_BAWR_ALIGN_128B (0x3 << 6)
48#define USB_SBUSCFG_BARD_ALIGN_128B (0x3 << 3)
49/* AHBBRST = 3 : Align AHB Burst to INCR16 (64 bytes) */
50#define USB_SBUSCFG_AHBBRST_INCR16 (0x3 << 0)
51
52#define USB_SBUSCFG_DEF_VAL (USB_SBUSCFG_BAWR_ALIGN_128B \
53 | USB_SBUSCFG_BARD_ALIGN_128B \
54 | USB_SBUSCFG_AHBBRST_INCR16)
55
56#define DRIVER_DESC "EHCI orion driver"
57
58#define hcd_to_orion_priv(h) ((struct orion_ehci_hcd *)hcd_to_ehci(h)->priv)
59
60struct orion_ehci_hcd {
61 struct clk *clk;
62};
63
64static struct hc_driver __read_mostly ehci_orion_hc_driver;
65
66/*
67 * Legacy DMA mask is 32 bit.
68 * AC5 has the DDR starting at 8GB, hence it requires
69 * a larger (34-bit) DMA mask, in order for DMA allocations
70 * to succeed:
71 */
72static const u64 dma_mask_orion = DMA_BIT_MASK(32);
73static const u64 dma_mask_ac5 = DMA_BIT_MASK(34);
74
75/*
76 * Implement Orion USB controller specification guidelines
77 */
78static void orion_usb_phy_v1_setup(struct usb_hcd *hcd)
79{
80 /* The below GLs are according to the Orion Errata document */
81 /*
82 * Clear interrupt cause and mask
83 */
84 wrl(USB_CAUSE, 0);
85 wrl(USB_MASK, 0);
86
87 /*
88 * Reset controller
89 */
90 wrl(USB_CMD, rdl(USB_CMD) | USB_CMD_RESET);
91 while (rdl(USB_CMD) & USB_CMD_RESET);
92
93 /*
94 * GL# USB-10: Set IPG for non start of frame packets
95 * Bits[14:8]=0xc
96 */
97 wrl(USB_IPG, (rdl(USB_IPG) & ~0x7f00) | 0xc00);
98
99 /*
100 * GL# USB-9: USB 2.0 Power Control
101 * BG_VSEL[7:6]=0x1
102 */
103 wrl(USB_PHY_PWR_CTRL, (rdl(USB_PHY_PWR_CTRL) & ~0xc0)| 0x40);
104
105 /*
106 * GL# USB-1: USB PHY Tx Control - force calibration to '8'
107 * TXDATA_BLOCK_EN[21]=0x1, EXT_RCAL_EN[13]=0x1, IMP_CAL[6:3]=0x8
108 */
109 wrl(USB_PHY_TX_CTRL, (rdl(USB_PHY_TX_CTRL) & ~0x78) | 0x202040);
110
111 /*
112 * GL# USB-3 GL# USB-9: USB PHY Rx Control
113 * RXDATA_BLOCK_LENGHT[31:30]=0x3, EDGE_DET_SEL[27:26]=0,
114 * CDR_FASTLOCK_EN[21]=0, DISCON_THRESHOLD[9:8]=0, SQ_THRESH[7:4]=0x1
115 */
116 wrl(USB_PHY_RX_CTRL, (rdl(USB_PHY_RX_CTRL) & ~0xc2003f0) | 0xc0000010);
117
118 /*
119 * GL# USB-3 GL# USB-9: USB PHY IVREF Control
120 * PLLVDD12[1:0]=0x2, RXVDD[5:4]=0x3, Reserved[19]=0
121 */
122 wrl(USB_PHY_IVREF_CTRL, (rdl(USB_PHY_IVREF_CTRL) & ~0x80003 ) | 0x32);
123
124 /*
125 * GL# USB-3 GL# USB-9: USB PHY Test Group Control
126 * REG_FIFO_SQ_RST[15]=0
127 */
128 wrl(USB_PHY_TST_GRP_CTRL, rdl(USB_PHY_TST_GRP_CTRL) & ~0x8000);
129
130 /*
131 * Stop and reset controller
132 */
133 wrl(USB_CMD, rdl(USB_CMD) & ~USB_CMD_RUN);
134 wrl(USB_CMD, rdl(USB_CMD) | USB_CMD_RESET);
135 while (rdl(USB_CMD) & USB_CMD_RESET);
136
137 /*
138 * GL# USB-5 Streaming disable REG_USB_MODE[4]=1
139 * TBD: This need to be done after each reset!
140 * GL# USB-4 Setup USB Host mode
141 */
142 wrl(USB_MODE, USB_MODE_SDIS | USB_MODE_HOST);
143}
144
145static void
146ehci_orion_conf_mbus_windows(struct usb_hcd *hcd,
147 const struct mbus_dram_target_info *dram)
148{
149 int i;
150
151 for (i = 0; i < 4; i++) {
152 wrl(USB_WINDOW_CTRL(i), 0);
153 wrl(USB_WINDOW_BASE(i), 0);
154 }
155
156 for (i = 0; i < dram->num_cs; i++) {
157 const struct mbus_dram_window *cs = dram->cs + i;
158
159 wrl(USB_WINDOW_CTRL(i), ((cs->size - 1) & 0xffff0000) |
160 (cs->mbus_attr << 8) |
161 (dram->mbus_dram_target_id << 4) | 1);
162 wrl(USB_WINDOW_BASE(i), cs->base);
163 }
164}
165
166static int ehci_orion_drv_reset(struct usb_hcd *hcd)
167{
168 struct device *dev = hcd->self.controller;
169 int ret;
170
171 ret = ehci_setup(hcd);
172 if (ret)
173 return ret;
174
175 /*
176 * For SoC without hlock, need to program sbuscfg value to guarantee
177 * AHB master's burst would not overrun or underrun FIFO.
178 *
179 * sbuscfg reg has to be set after usb controller reset, otherwise
180 * the value would be override to 0.
181 */
182 if (of_device_is_compatible(dev->of_node, "marvell,armada-3700-ehci"))
183 wrl(USB_SBUSCFG, USB_SBUSCFG_DEF_VAL);
184
185 return ret;
186}
187
188static int __maybe_unused ehci_orion_drv_suspend(struct device *dev)
189{
190 struct usb_hcd *hcd = dev_get_drvdata(dev);
191
192 return ehci_suspend(hcd, device_may_wakeup(dev));
193}
194
195static int __maybe_unused ehci_orion_drv_resume(struct device *dev)
196{
197 struct usb_hcd *hcd = dev_get_drvdata(dev);
198
199 return ehci_resume(hcd, false);
200}
201
202static SIMPLE_DEV_PM_OPS(ehci_orion_pm_ops, ehci_orion_drv_suspend,
203 ehci_orion_drv_resume);
204
205static const struct ehci_driver_overrides orion_overrides __initconst = {
206 .extra_priv_size = sizeof(struct orion_ehci_hcd),
207 .reset = ehci_orion_drv_reset,
208};
209
210static int ehci_orion_drv_probe(struct platform_device *pdev)
211{
212 struct orion_ehci_data *pd = dev_get_platdata(&pdev->dev);
213 const struct mbus_dram_target_info *dram;
214 struct resource *res;
215 struct usb_hcd *hcd;
216 struct ehci_hcd *ehci;
217 void __iomem *regs;
218 int irq, err;
219 enum orion_ehci_phy_ver phy_version;
220 struct orion_ehci_hcd *priv;
221 u64 *dma_mask_ptr;
222
223 if (usb_disabled())
224 return -ENODEV;
225
226 pr_debug("Initializing Orion-SoC USB Host Controller\n");
227
228 irq = platform_get_irq(pdev, 0);
229 if (irq < 0) {
230 err = irq;
231 goto err;
232 }
233
234 /*
235 * Right now device-tree probed devices don't get dma_mask
236 * set. Since shared usb code relies on it, set it here for
237 * now. Once we have dma capability bindings this can go away.
238 */
239 dma_mask_ptr = (u64 *)of_device_get_match_data(&pdev->dev);
240 err = dma_coerce_mask_and_coherent(&pdev->dev, *dma_mask_ptr);
241 if (err)
242 goto err;
243
244 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
245 if (IS_ERR(regs)) {
246 err = PTR_ERR(regs);
247 goto err;
248 }
249
250 hcd = usb_create_hcd(&ehci_orion_hc_driver,
251 &pdev->dev, dev_name(&pdev->dev));
252 if (!hcd) {
253 err = -ENOMEM;
254 goto err;
255 }
256
257 hcd->rsrc_start = res->start;
258 hcd->rsrc_len = resource_size(res);
259 hcd->regs = regs;
260
261 ehci = hcd_to_ehci(hcd);
262 ehci->caps = hcd->regs + 0x100;
263 hcd->has_tt = 1;
264
265 priv = hcd_to_orion_priv(hcd);
266 /*
267 * Not all platforms can gate the clock, so it is not an error if
268 * the clock does not exists.
269 */
270 priv->clk = devm_clk_get(&pdev->dev, NULL);
271 if (!IS_ERR(priv->clk)) {
272 err = clk_prepare_enable(priv->clk);
273 if (err)
274 goto err_put_hcd;
275 }
276
277 /*
278 * (Re-)program MBUS remapping windows if we are asked to.
279 */
280 dram = mv_mbus_dram_info();
281 if (dram)
282 ehci_orion_conf_mbus_windows(hcd, dram);
283
284 /*
285 * setup Orion USB controller.
286 */
287 if (pdev->dev.of_node)
288 phy_version = EHCI_PHY_NA;
289 else
290 phy_version = pd->phy_version;
291
292 switch (phy_version) {
293 case EHCI_PHY_NA: /* dont change USB phy settings */
294 break;
295 case EHCI_PHY_ORION:
296 orion_usb_phy_v1_setup(hcd);
297 break;
298 case EHCI_PHY_DD:
299 case EHCI_PHY_KW:
300 default:
301 dev_warn(&pdev->dev, "USB phy version isn't supported.\n");
302 }
303
304 err = usb_add_hcd(hcd, irq, IRQF_SHARED);
305 if (err)
306 goto err_dis_clk;
307
308 device_wakeup_enable(hcd->self.controller);
309 return 0;
310
311err_dis_clk:
312 if (!IS_ERR(priv->clk))
313 clk_disable_unprepare(priv->clk);
314err_put_hcd:
315 usb_put_hcd(hcd);
316err:
317 dev_err(&pdev->dev, "init %s fail, %d\n",
318 dev_name(&pdev->dev), err);
319
320 return err;
321}
322
323static void ehci_orion_drv_remove(struct platform_device *pdev)
324{
325 struct usb_hcd *hcd = platform_get_drvdata(pdev);
326 struct orion_ehci_hcd *priv = hcd_to_orion_priv(hcd);
327
328 usb_remove_hcd(hcd);
329
330 if (!IS_ERR(priv->clk))
331 clk_disable_unprepare(priv->clk);
332
333 usb_put_hcd(hcd);
334}
335
336static const struct of_device_id ehci_orion_dt_ids[] = {
337 { .compatible = "marvell,orion-ehci", .data = &dma_mask_orion},
338 { .compatible = "marvell,armada-3700-ehci", .data = &dma_mask_orion},
339 { .compatible = "marvell,ac5-ehci", .data = &dma_mask_ac5},
340 {},
341};
342MODULE_DEVICE_TABLE(of, ehci_orion_dt_ids);
343
344static struct platform_driver ehci_orion_driver = {
345 .probe = ehci_orion_drv_probe,
346 .remove = ehci_orion_drv_remove,
347 .shutdown = usb_hcd_platform_shutdown,
348 .driver = {
349 .name = "orion-ehci",
350 .of_match_table = ehci_orion_dt_ids,
351 .pm = &ehci_orion_pm_ops,
352 },
353};
354
355static int __init ehci_orion_init(void)
356{
357 if (usb_disabled())
358 return -ENODEV;
359
360 ehci_init_driver(&ehci_orion_hc_driver, &orion_overrides);
361 return platform_driver_register(&ehci_orion_driver);
362}
363module_init(ehci_orion_init);
364
365static void __exit ehci_orion_cleanup(void)
366{
367 platform_driver_unregister(&ehci_orion_driver);
368}
369module_exit(ehci_orion_cleanup);
370
371MODULE_DESCRIPTION(DRIVER_DESC);
372MODULE_ALIAS("platform:orion-ehci");
373MODULE_AUTHOR("Tzachi Perelstein");
374MODULE_LICENSE("GPL v2");