Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2010 Google, Inc.
4 * Copyright (C) 2013 NVIDIA Corporation
5 *
6 * Author:
7 * Erik Gilling <konkers@google.com>
8 * Benoit Goby <benoit@android.com>
9 * Venu Byravarasu <vbyravarasu@nvidia.com>
10 */
11
12#include <linux/delay.h>
13#include <linux/err.h>
14#include <linux/export.h>
15#include <linux/gpio/consumer.h>
16#include <linux/iopoll.h>
17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/of_platform.h>
20#include <linux/platform_device.h>
21#include <linux/resource.h>
22#include <linux/slab.h>
23#include <linux/spinlock.h>
24
25#include <linux/regulator/consumer.h>
26
27#include <linux/usb/ehci_def.h>
28#include <linux/usb/of.h>
29#include <linux/usb/tegra_usb_phy.h>
30#include <linux/usb/ulpi.h>
31
32#define USB_TXFILLTUNING 0x154
33#define USB_FIFO_TXFILL_THRES(x) (((x) & 0x1f) << 16)
34#define USB_FIFO_TXFILL_MASK 0x1f0000
35
36#define ULPI_VIEWPORT 0x170
37
38/* PORTSC PTS/PHCD bits, Tegra20 only */
39#define TEGRA_USB_PORTSC1 0x184
40#define TEGRA_USB_PORTSC1_PTS(x) (((x) & 0x3) << 30)
41#define TEGRA_USB_PORTSC1_PHCD BIT(23)
42#define TEGRA_USB_PORTSC1_WKOC BIT(22)
43#define TEGRA_USB_PORTSC1_WKDS BIT(21)
44#define TEGRA_USB_PORTSC1_WKCN BIT(20)
45
46/* HOSTPC1 PTS/PHCD bits, Tegra30 and above */
47#define TEGRA30_USB_PORTSC1 0x174
48#define TEGRA_USB_HOSTPC1_DEVLC 0x1b4
49#define TEGRA_USB_HOSTPC1_DEVLC_PTS(x) (((x) & 0x7) << 29)
50#define TEGRA_USB_HOSTPC1_DEVLC_PHCD BIT(22)
51#define TEGRA_USB_HOSTPC1_DEVLC_PTS_HSIC 4
52
53/* Bits of PORTSC1, which will get cleared by writing 1 into them */
54#define TEGRA_PORTSC1_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC)
55
56#define USB_SUSP_CTRL 0x400
57#define USB_WAKE_ON_RESUME_EN BIT(2)
58#define USB_WAKE_ON_CNNT_EN_DEV BIT(3)
59#define USB_WAKE_ON_DISCON_EN_DEV BIT(4)
60#define USB_SUSP_CLR BIT(5)
61#define USB_PHY_CLK_VALID BIT(7)
62#define UTMIP_RESET BIT(11)
63#define UTMIP_PHY_ENABLE BIT(12)
64#define ULPI_PHY_ENABLE BIT(13)
65#define USB_SUSP_SET BIT(14)
66#define UHSIC_RESET BIT(14)
67#define USB_WAKEUP_DEBOUNCE_COUNT(x) (((x) & 0x7) << 16)
68#define UHSIC_PHY_ENABLE BIT(19)
69
70#define USB_PHY_VBUS_SENSORS 0x404
71#define B_SESS_VLD_WAKEUP_EN BIT(14)
72#define A_SESS_VLD_WAKEUP_EN BIT(22)
73#define A_VBUS_VLD_WAKEUP_EN BIT(30)
74
75#define USB_PHY_VBUS_WAKEUP_ID 0x408
76#define ID_INT_EN BIT(0)
77#define ID_CHG_DET BIT(1)
78#define VBUS_WAKEUP_INT_EN BIT(8)
79#define VBUS_WAKEUP_CHG_DET BIT(9)
80#define VBUS_WAKEUP_STS BIT(10)
81#define VBUS_WAKEUP_WAKEUP_EN BIT(30)
82
83#define USB1_LEGACY_CTRL 0x410
84#define USB1_NO_LEGACY_MODE BIT(0)
85#define USB1_VBUS_SENSE_CTL_MASK (3 << 1)
86#define USB1_VBUS_SENSE_CTL_VBUS_WAKEUP (0 << 1)
87#define USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
88 (1 << 1)
89#define USB1_VBUS_SENSE_CTL_AB_SESS_VLD (2 << 1)
90#define USB1_VBUS_SENSE_CTL_A_SESS_VLD (3 << 1)
91
92#define ULPI_TIMING_CTRL_0 0x424
93#define ULPI_OUTPUT_PINMUX_BYP BIT(10)
94#define ULPI_CLKOUT_PINMUX_BYP BIT(11)
95
96#define ULPI_TIMING_CTRL_1 0x428
97#define ULPI_DATA_TRIMMER_LOAD BIT(0)
98#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1)
99#define ULPI_STPDIRNXT_TRIMMER_LOAD BIT(16)
100#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
101#define ULPI_DIR_TRIMMER_LOAD BIT(24)
102#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25)
103
104#define UTMIP_PLL_CFG1 0x804
105#define UTMIP_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
106#define UTMIP_PLLU_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)
107
108#define UTMIP_XCVR_CFG0 0x808
109#define UTMIP_XCVR_SETUP(x) (((x) & 0xf) << 0)
110#define UTMIP_XCVR_SETUP_MSB(x) ((((x) & 0x70) >> 4) << 22)
111#define UTMIP_XCVR_LSRSLEW(x) (((x) & 0x3) << 8)
112#define UTMIP_XCVR_LSFSLEW(x) (((x) & 0x3) << 10)
113#define UTMIP_FORCE_PD_POWERDOWN BIT(14)
114#define UTMIP_FORCE_PD2_POWERDOWN BIT(16)
115#define UTMIP_FORCE_PDZI_POWERDOWN BIT(18)
116#define UTMIP_XCVR_LSBIAS_SEL BIT(21)
117#define UTMIP_XCVR_HSSLEW(x) (((x) & 0x3) << 4)
118#define UTMIP_XCVR_HSSLEW_MSB(x) ((((x) & 0x1fc) >> 2) << 25)
119
120#define UTMIP_BIAS_CFG0 0x80c
121#define UTMIP_OTGPD BIT(11)
122#define UTMIP_BIASPD BIT(10)
123#define UTMIP_HSSQUELCH_LEVEL(x) (((x) & 0x3) << 0)
124#define UTMIP_HSDISCON_LEVEL(x) (((x) & 0x3) << 2)
125#define UTMIP_HSDISCON_LEVEL_MSB(x) ((((x) & 0x4) >> 2) << 24)
126
127#define UTMIP_HSRX_CFG0 0x810
128#define UTMIP_ELASTIC_LIMIT(x) (((x) & 0x1f) << 10)
129#define UTMIP_IDLE_WAIT(x) (((x) & 0x1f) << 15)
130
131#define UTMIP_HSRX_CFG1 0x814
132#define UTMIP_HS_SYNC_START_DLY(x) (((x) & 0x1f) << 1)
133
134#define UTMIP_TX_CFG0 0x820
135#define UTMIP_FS_PREABMLE_J BIT(19)
136#define UTMIP_HS_DISCON_DISABLE BIT(8)
137
138#define UTMIP_MISC_CFG0 0x824
139#define UTMIP_DPDM_OBSERVE BIT(26)
140#define UTMIP_DPDM_OBSERVE_SEL(x) (((x) & 0xf) << 27)
141#define UTMIP_DPDM_OBSERVE_SEL_FS_J UTMIP_DPDM_OBSERVE_SEL(0xf)
142#define UTMIP_DPDM_OBSERVE_SEL_FS_K UTMIP_DPDM_OBSERVE_SEL(0xe)
143#define UTMIP_DPDM_OBSERVE_SEL_FS_SE1 UTMIP_DPDM_OBSERVE_SEL(0xd)
144#define UTMIP_DPDM_OBSERVE_SEL_FS_SE0 UTMIP_DPDM_OBSERVE_SEL(0xc)
145#define UTMIP_SUSPEND_EXIT_ON_EDGE BIT(22)
146
147#define UTMIP_MISC_CFG1 0x828
148#define UTMIP_PLL_ACTIVE_DLY_COUNT(x) (((x) & 0x1f) << 18)
149#define UTMIP_PLLU_STABLE_COUNT(x) (((x) & 0xfff) << 6)
150
151#define UTMIP_DEBOUNCE_CFG0 0x82c
152#define UTMIP_BIAS_DEBOUNCE_A(x) (((x) & 0xffff) << 0)
153
154#define UTMIP_BAT_CHRG_CFG0 0x830
155#define UTMIP_PD_CHRG BIT(0)
156
157#define UTMIP_SPARE_CFG0 0x834
158#define FUSE_SETUP_SEL BIT(3)
159
160#define UTMIP_XCVR_CFG1 0x838
161#define UTMIP_FORCE_PDDISC_POWERDOWN BIT(0)
162#define UTMIP_FORCE_PDCHRP_POWERDOWN BIT(2)
163#define UTMIP_FORCE_PDDR_POWERDOWN BIT(4)
164#define UTMIP_XCVR_TERM_RANGE_ADJ(x) (((x) & 0xf) << 18)
165
166#define UTMIP_BIAS_CFG1 0x83c
167#define UTMIP_BIAS_PDTRK_COUNT(x) (((x) & 0x1f) << 3)
168
169/*
170 * Tegra20 has no UTMIP registers on PHY2 and UHSIC registers start from 0x800
171 * just where UTMIP registers should have been. This is the case only with Tegra20
172 * Tegra30+ have UTMIP registers at 0x800 and UHSIC registers are shifted by 0x400
173 * to 0xc00, but register layout is preserved.
174 */
175#define UHSIC_PLL_CFG1 0x804
176#define UHSIC_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
177#define UHSIC_PLLU_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 14)
178
179#define UHSIC_HSRX_CFG0 0x808
180#define UHSIC_ELASTIC_UNDERRUN_LIMIT(x) (((x) & 0x1f) << 2)
181#define UHSIC_ELASTIC_OVERRUN_LIMIT(x) (((x) & 0x1f) << 8)
182#define UHSIC_IDLE_WAIT(x) (((x) & 0x1f) << 13)
183
184#define UHSIC_HSRX_CFG1 0x80c
185#define UHSIC_HS_SYNC_START_DLY(x) (((x) & 0x1f) << 1)
186
187#define UHSIC_TX_CFG0 0x810
188#define UHSIC_HS_READY_WAIT_FOR_VALID BIT(9)
189
190#define UHSIC_MISC_CFG0 0x814
191#define UHSIC_SUSPEND_EXIT_ON_EDGE BIT(7)
192#define UHSIC_DETECT_SHORT_CONNECT BIT(8)
193#define UHSIC_FORCE_XCVR_MODE BIT(15)
194#define UHSIC_DISABLE_BUSRESET BIT(20)
195
196#define UHSIC_MISC_CFG1 0x818
197#define UHSIC_PLLU_STABLE_COUNT(x) (((x) & 0xfff) << 2)
198
199#define UHSIC_PADS_CFG0 0x81c
200#define UHSIC_TX_RTUNEN 0xf000
201#define UHSIC_TX_RTUNE(x) (((x) & 0xf) << 12)
202
203#define UHSIC_PADS_CFG1 0x820
204#define UHSIC_PD_BG BIT(2)
205#define UHSIC_PD_TX BIT(3)
206#define UHSIC_PD_TRK BIT(4)
207#define UHSIC_PD_RX BIT(5)
208#define UHSIC_PD_ZI BIT(6)
209#define UHSIC_RX_SEL BIT(7)
210#define UHSIC_RPD_DATA BIT(9)
211#define UHSIC_RPD_STROBE BIT(10)
212#define UHSIC_RPU_DATA BIT(11)
213#define UHSIC_RPU_STROBE BIT(12)
214
215#define UHSIC_CMD_CFG0 0x824
216#define UHSIC_PRETEND_CONNECT_DETECT BIT(5)
217
218#define UHSIC_STAT_CFG0 0x828
219#define UHSIC_CONNECT_DETECT BIT(0)
220
221/* For Tegra30 and above only, the address is different in Tegra20 */
222#define USB_USBMODE 0x1f8
223#define USB_USBMODE_MASK (3 << 0)
224#define USB_USBMODE_HOST (3 << 0)
225#define USB_USBMODE_DEVICE (2 << 0)
226
227#define PMC_USB_AO 0xf0
228#define VBUS_WAKEUP_PD_P0 BIT(2)
229#define ID_PD_P0 BIT(3)
230
231static DEFINE_SPINLOCK(utmip_pad_lock);
232static unsigned int utmip_pad_count;
233
234struct tegra_xtal_freq {
235 unsigned int freq;
236 u8 enable_delay;
237 u8 stable_count;
238 u8 active_delay;
239 u8 utmi_xtal_freq_count;
240 u16 hsic_xtal_freq_count;
241 u16 debounce;
242};
243
244static const struct tegra_xtal_freq tegra_freq_table[] = {
245 {
246 .freq = 12000000,
247 .enable_delay = 0x02,
248 .stable_count = 0x2F,
249 .active_delay = 0x04,
250 .utmi_xtal_freq_count = 0x76,
251 .hsic_xtal_freq_count = 0x1CA,
252 .debounce = 0x7530,
253 },
254 {
255 .freq = 13000000,
256 .enable_delay = 0x02,
257 .stable_count = 0x33,
258 .active_delay = 0x05,
259 .utmi_xtal_freq_count = 0x7F,
260 .hsic_xtal_freq_count = 0x1F0,
261 .debounce = 0x7EF4,
262 },
263 {
264 .freq = 19200000,
265 .enable_delay = 0x03,
266 .stable_count = 0x4B,
267 .active_delay = 0x06,
268 .utmi_xtal_freq_count = 0xBB,
269 .hsic_xtal_freq_count = 0x2DD,
270 .debounce = 0xBB80,
271 },
272 {
273 .freq = 26000000,
274 .enable_delay = 0x04,
275 .stable_count = 0x66,
276 .active_delay = 0x09,
277 .utmi_xtal_freq_count = 0xFE,
278 .hsic_xtal_freq_count = 0x3E0,
279 .debounce = 0xFDE8,
280 },
281};
282
283static inline struct tegra_usb_phy *to_tegra_usb_phy(struct usb_phy *u_phy)
284{
285 return container_of(u_phy, struct tegra_usb_phy, u_phy);
286}
287
288static void set_pts(struct tegra_usb_phy *phy, u8 pts_val)
289{
290 void __iomem *base = phy->regs;
291 u32 val;
292
293 if (phy->soc_config->has_hostpc) {
294 val = readl_relaxed(base + TEGRA_USB_HOSTPC1_DEVLC);
295 val &= ~TEGRA_USB_HOSTPC1_DEVLC_PTS(~0);
296 val |= TEGRA_USB_HOSTPC1_DEVLC_PTS(pts_val);
297 writel_relaxed(val, base + TEGRA_USB_HOSTPC1_DEVLC);
298 } else {
299 val = readl_relaxed(base + TEGRA_USB_PORTSC1);
300 val &= ~TEGRA_PORTSC1_RWC_BITS;
301 val &= ~TEGRA_USB_PORTSC1_PTS(~0);
302 val |= TEGRA_USB_PORTSC1_PTS(pts_val);
303 writel_relaxed(val, base + TEGRA_USB_PORTSC1);
304 }
305}
306
307static void set_phcd(struct tegra_usb_phy *phy, bool enable)
308{
309 void __iomem *base = phy->regs;
310 u32 val;
311
312 if (phy->soc_config->has_hostpc) {
313 val = readl_relaxed(base + TEGRA_USB_HOSTPC1_DEVLC);
314 if (enable)
315 val |= TEGRA_USB_HOSTPC1_DEVLC_PHCD;
316 else
317 val &= ~TEGRA_USB_HOSTPC1_DEVLC_PHCD;
318 writel_relaxed(val, base + TEGRA_USB_HOSTPC1_DEVLC);
319 } else {
320 val = readl_relaxed(base + TEGRA_USB_PORTSC1) & ~PORT_RWC_BITS;
321 if (enable)
322 val |= TEGRA_USB_PORTSC1_PHCD;
323 else
324 val &= ~TEGRA_USB_PORTSC1_PHCD;
325 writel_relaxed(val, base + TEGRA_USB_PORTSC1);
326 }
327}
328
329static int utmip_pad_open(struct tegra_usb_phy *phy)
330{
331 int ret;
332
333 ret = clk_prepare_enable(phy->pad_clk);
334 if (ret) {
335 dev_err(phy->u_phy.dev,
336 "Failed to enable UTMI-pads clock: %d\n", ret);
337 return ret;
338 }
339
340 spin_lock(&utmip_pad_lock);
341
342 ret = reset_control_deassert(phy->pad_rst);
343 if (ret) {
344 dev_err(phy->u_phy.dev,
345 "Failed to initialize UTMI-pads reset: %d\n", ret);
346 goto unlock;
347 }
348
349 ret = reset_control_assert(phy->pad_rst);
350 if (ret) {
351 dev_err(phy->u_phy.dev,
352 "Failed to assert UTMI-pads reset: %d\n", ret);
353 goto unlock;
354 }
355
356 udelay(1);
357
358 ret = reset_control_deassert(phy->pad_rst);
359 if (ret)
360 dev_err(phy->u_phy.dev,
361 "Failed to deassert UTMI-pads reset: %d\n", ret);
362unlock:
363 spin_unlock(&utmip_pad_lock);
364
365 clk_disable_unprepare(phy->pad_clk);
366
367 return ret;
368}
369
370static int utmip_pad_close(struct tegra_usb_phy *phy)
371{
372 int ret;
373
374 ret = clk_prepare_enable(phy->pad_clk);
375 if (ret) {
376 dev_err(phy->u_phy.dev,
377 "Failed to enable UTMI-pads clock: %d\n", ret);
378 return ret;
379 }
380
381 ret = reset_control_assert(phy->pad_rst);
382 if (ret)
383 dev_err(phy->u_phy.dev,
384 "Failed to assert UTMI-pads reset: %d\n", ret);
385
386 udelay(1);
387
388 clk_disable_unprepare(phy->pad_clk);
389
390 return ret;
391}
392
393static int utmip_pad_power_on(struct tegra_usb_phy *phy)
394{
395 struct tegra_utmip_config *config = phy->config;
396 void __iomem *base = phy->pad_regs;
397 u32 val;
398 int err;
399
400 err = clk_prepare_enable(phy->pad_clk);
401 if (err)
402 return err;
403
404 spin_lock(&utmip_pad_lock);
405
406 if (utmip_pad_count++ == 0) {
407 val = readl_relaxed(base + UTMIP_BIAS_CFG0);
408 val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
409
410 if (phy->soc_config->requires_extra_tuning_parameters) {
411 val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) |
412 UTMIP_HSDISCON_LEVEL(~0) |
413 UTMIP_HSDISCON_LEVEL_MSB(~0));
414
415 val |= UTMIP_HSSQUELCH_LEVEL(config->hssquelch_level);
416 val |= UTMIP_HSDISCON_LEVEL(config->hsdiscon_level);
417 val |= UTMIP_HSDISCON_LEVEL_MSB(config->hsdiscon_level);
418 }
419 writel_relaxed(val, base + UTMIP_BIAS_CFG0);
420 }
421
422 if (phy->pad_wakeup) {
423 phy->pad_wakeup = false;
424 utmip_pad_count--;
425 }
426
427 spin_unlock(&utmip_pad_lock);
428
429 clk_disable_unprepare(phy->pad_clk);
430
431 return 0;
432}
433
434static int utmip_pad_power_off(struct tegra_usb_phy *phy)
435{
436 void __iomem *base = phy->pad_regs;
437 u32 val;
438 int ret;
439
440 ret = clk_prepare_enable(phy->pad_clk);
441 if (ret)
442 return ret;
443
444 spin_lock(&utmip_pad_lock);
445
446 if (!utmip_pad_count) {
447 dev_err(phy->u_phy.dev, "UTMIP pad already powered off\n");
448 ret = -EINVAL;
449 goto ulock;
450 }
451
452 /*
453 * In accordance to TRM, OTG and Bias pad circuits could be turned off
454 * to save power if wake is enabled, but the VBUS-change detection
455 * method is board-specific and these circuits may need to be enabled
456 * to generate wakeup event, hence we will just keep them both enabled.
457 */
458 if (phy->wakeup_enabled) {
459 phy->pad_wakeup = true;
460 utmip_pad_count++;
461 }
462
463 if (--utmip_pad_count == 0) {
464 val = readl_relaxed(base + UTMIP_BIAS_CFG0);
465 val |= UTMIP_OTGPD | UTMIP_BIASPD;
466 writel_relaxed(val, base + UTMIP_BIAS_CFG0);
467 }
468ulock:
469 spin_unlock(&utmip_pad_lock);
470
471 clk_disable_unprepare(phy->pad_clk);
472
473 return ret;
474}
475
476static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result)
477{
478 u32 tmp;
479
480 return readl_relaxed_poll_timeout(reg, tmp, (tmp & mask) == result,
481 2000, 6000);
482}
483
484static void utmi_phy_clk_disable(struct tegra_usb_phy *phy)
485{
486 void __iomem *base = phy->regs;
487 u32 val;
488
489 /*
490 * The USB driver may have already initiated the phy clock
491 * disable so wait to see if the clock turns off and if not
492 * then proceed with gating the clock.
493 */
494 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) == 0)
495 return;
496
497 if (phy->is_legacy_phy) {
498 val = readl_relaxed(base + USB_SUSP_CTRL);
499 val |= USB_SUSP_SET;
500 writel_relaxed(val, base + USB_SUSP_CTRL);
501
502 usleep_range(10, 100);
503
504 val = readl_relaxed(base + USB_SUSP_CTRL);
505 val &= ~USB_SUSP_SET;
506 writel_relaxed(val, base + USB_SUSP_CTRL);
507 } else {
508 set_phcd(phy, true);
509 }
510
511 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0))
512 dev_err(phy->u_phy.dev,
513 "Timeout waiting for PHY to stabilize on disable\n");
514}
515
516static void utmi_phy_clk_enable(struct tegra_usb_phy *phy)
517{
518 void __iomem *base = phy->regs;
519 u32 val;
520
521 /*
522 * The USB driver may have already initiated the phy clock
523 * enable so wait to see if the clock turns on and if not
524 * then proceed with ungating the clock.
525 */
526 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
527 USB_PHY_CLK_VALID) == 0)
528 return;
529
530 if (phy->is_legacy_phy) {
531 val = readl_relaxed(base + USB_SUSP_CTRL);
532 val |= USB_SUSP_CLR;
533 writel_relaxed(val, base + USB_SUSP_CTRL);
534
535 usleep_range(10, 100);
536
537 val = readl_relaxed(base + USB_SUSP_CTRL);
538 val &= ~USB_SUSP_CLR;
539 writel_relaxed(val, base + USB_SUSP_CTRL);
540 } else {
541 set_phcd(phy, false);
542 }
543
544 if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
545 USB_PHY_CLK_VALID))
546 dev_err(phy->u_phy.dev,
547 "Timeout waiting for PHY to stabilize on enable\n");
548}
549
550static int utmi_phy_power_on(struct tegra_usb_phy *phy)
551{
552 struct tegra_utmip_config *config = phy->config;
553 void __iomem *base = phy->regs;
554 u32 val;
555 int err;
556
557 val = readl_relaxed(base + USB_SUSP_CTRL);
558 val |= UTMIP_RESET;
559 writel_relaxed(val, base + USB_SUSP_CTRL);
560
561 if (phy->is_legacy_phy) {
562 val = readl_relaxed(base + USB1_LEGACY_CTRL);
563 val |= USB1_NO_LEGACY_MODE;
564 writel_relaxed(val, base + USB1_LEGACY_CTRL);
565 }
566
567 val = readl_relaxed(base + UTMIP_TX_CFG0);
568 val |= UTMIP_FS_PREABMLE_J;
569 writel_relaxed(val, base + UTMIP_TX_CFG0);
570
571 val = readl_relaxed(base + UTMIP_HSRX_CFG0);
572 val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
573 val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
574 val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
575 writel_relaxed(val, base + UTMIP_HSRX_CFG0);
576
577 val = readl_relaxed(base + UTMIP_HSRX_CFG1);
578 val &= ~UTMIP_HS_SYNC_START_DLY(~0);
579 val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
580 writel_relaxed(val, base + UTMIP_HSRX_CFG1);
581
582 val = readl_relaxed(base + UTMIP_DEBOUNCE_CFG0);
583 val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
584 val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
585 writel_relaxed(val, base + UTMIP_DEBOUNCE_CFG0);
586
587 val = readl_relaxed(base + UTMIP_MISC_CFG0);
588 val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
589 writel_relaxed(val, base + UTMIP_MISC_CFG0);
590
591 if (!phy->soc_config->utmi_pll_config_in_car_module) {
592 val = readl_relaxed(base + UTMIP_MISC_CFG1);
593 val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) |
594 UTMIP_PLLU_STABLE_COUNT(~0));
595 val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) |
596 UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count);
597 writel_relaxed(val, base + UTMIP_MISC_CFG1);
598
599 val = readl_relaxed(base + UTMIP_PLL_CFG1);
600 val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) |
601 UTMIP_PLLU_ENABLE_DLY_COUNT(~0));
602 val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->utmi_xtal_freq_count) |
603 UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
604 writel_relaxed(val, base + UTMIP_PLL_CFG1);
605 }
606
607 val = readl_relaxed(base + USB_SUSP_CTRL);
608 val &= ~USB_WAKE_ON_RESUME_EN;
609 writel_relaxed(val, base + USB_SUSP_CTRL);
610
611 if (phy->mode != USB_DR_MODE_HOST) {
612 val = readl_relaxed(base + USB_SUSP_CTRL);
613 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
614 writel_relaxed(val, base + USB_SUSP_CTRL);
615
616 val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID);
617 val &= ~VBUS_WAKEUP_WAKEUP_EN;
618 val &= ~(ID_CHG_DET | VBUS_WAKEUP_CHG_DET);
619 writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID);
620
621 val = readl_relaxed(base + USB_PHY_VBUS_SENSORS);
622 val &= ~(A_VBUS_VLD_WAKEUP_EN | A_SESS_VLD_WAKEUP_EN);
623 val &= ~(B_SESS_VLD_WAKEUP_EN);
624 writel_relaxed(val, base + USB_PHY_VBUS_SENSORS);
625
626 val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0);
627 val &= ~UTMIP_PD_CHRG;
628 writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);
629 } else {
630 val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0);
631 val |= UTMIP_PD_CHRG;
632 writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);
633 }
634
635 err = utmip_pad_power_on(phy);
636 if (err)
637 return err;
638
639 val = readl_relaxed(base + UTMIP_XCVR_CFG0);
640 val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
641 UTMIP_FORCE_PDZI_POWERDOWN | UTMIP_XCVR_LSBIAS_SEL |
642 UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_SETUP_MSB(~0) |
643 UTMIP_XCVR_LSFSLEW(~0) | UTMIP_XCVR_LSRSLEW(~0));
644
645 if (!config->xcvr_setup_use_fuses) {
646 val |= UTMIP_XCVR_SETUP(config->xcvr_setup);
647 val |= UTMIP_XCVR_SETUP_MSB(config->xcvr_setup);
648 }
649 val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
650 val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
651
652 if (phy->soc_config->requires_extra_tuning_parameters) {
653 val &= ~(UTMIP_XCVR_HSSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
654 val |= UTMIP_XCVR_HSSLEW(config->xcvr_hsslew);
655 val |= UTMIP_XCVR_HSSLEW_MSB(config->xcvr_hsslew);
656 }
657 writel_relaxed(val, base + UTMIP_XCVR_CFG0);
658
659 val = readl_relaxed(base + UTMIP_XCVR_CFG1);
660 val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
661 UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
662 val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
663 writel_relaxed(val, base + UTMIP_XCVR_CFG1);
664
665 val = readl_relaxed(base + UTMIP_BIAS_CFG1);
666 val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
667 val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
668 writel_relaxed(val, base + UTMIP_BIAS_CFG1);
669
670 val = readl_relaxed(base + UTMIP_SPARE_CFG0);
671 if (config->xcvr_setup_use_fuses)
672 val |= FUSE_SETUP_SEL;
673 else
674 val &= ~FUSE_SETUP_SEL;
675 writel_relaxed(val, base + UTMIP_SPARE_CFG0);
676
677 if (!phy->is_legacy_phy) {
678 val = readl_relaxed(base + USB_SUSP_CTRL);
679 val |= UTMIP_PHY_ENABLE;
680 writel_relaxed(val, base + USB_SUSP_CTRL);
681 }
682
683 val = readl_relaxed(base + USB_SUSP_CTRL);
684 val &= ~UTMIP_RESET;
685 writel_relaxed(val, base + USB_SUSP_CTRL);
686
687 if (phy->is_legacy_phy) {
688 val = readl_relaxed(base + USB1_LEGACY_CTRL);
689 val &= ~USB1_VBUS_SENSE_CTL_MASK;
690 val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD;
691 writel_relaxed(val, base + USB1_LEGACY_CTRL);
692
693 val = readl_relaxed(base + USB_SUSP_CTRL);
694 val &= ~USB_SUSP_SET;
695 writel_relaxed(val, base + USB_SUSP_CTRL);
696 }
697
698 utmi_phy_clk_enable(phy);
699
700 if (phy->soc_config->requires_usbmode_setup) {
701 val = readl_relaxed(base + USB_USBMODE);
702 val &= ~USB_USBMODE_MASK;
703 if (phy->mode == USB_DR_MODE_HOST)
704 val |= USB_USBMODE_HOST;
705 else
706 val |= USB_USBMODE_DEVICE;
707 writel_relaxed(val, base + USB_USBMODE);
708 }
709
710 if (!phy->is_legacy_phy)
711 set_pts(phy, 0);
712
713 return 0;
714}
715
716static int utmi_phy_power_off(struct tegra_usb_phy *phy)
717{
718 void __iomem *base = phy->regs;
719 u32 val;
720
721 /*
722 * Give hardware time to settle down after VBUS disconnection,
723 * otherwise PHY will immediately wake up from suspend.
724 */
725 if (phy->wakeup_enabled && phy->mode != USB_DR_MODE_HOST)
726 readl_relaxed_poll_timeout(base + USB_PHY_VBUS_WAKEUP_ID,
727 val, !(val & VBUS_WAKEUP_STS),
728 5000, 100000);
729
730 utmi_phy_clk_disable(phy);
731
732 /* PHY won't resume if reset is asserted */
733 if (!phy->wakeup_enabled) {
734 val = readl_relaxed(base + USB_SUSP_CTRL);
735 val |= UTMIP_RESET;
736 writel_relaxed(val, base + USB_SUSP_CTRL);
737 }
738
739 val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0);
740 val |= UTMIP_PD_CHRG;
741 writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);
742
743 if (!phy->wakeup_enabled) {
744 val = readl_relaxed(base + UTMIP_XCVR_CFG0);
745 val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
746 UTMIP_FORCE_PDZI_POWERDOWN;
747 writel_relaxed(val, base + UTMIP_XCVR_CFG0);
748 }
749
750 val = readl_relaxed(base + UTMIP_XCVR_CFG1);
751 val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
752 UTMIP_FORCE_PDDR_POWERDOWN;
753 writel_relaxed(val, base + UTMIP_XCVR_CFG1);
754
755 if (phy->wakeup_enabled) {
756 val = readl_relaxed(base + USB_SUSP_CTRL);
757 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
758 val |= USB_WAKEUP_DEBOUNCE_COUNT(5);
759 val |= USB_WAKE_ON_RESUME_EN;
760 writel_relaxed(val, base + USB_SUSP_CTRL);
761
762 /*
763 * Ask VBUS sensor to generate wake event once cable is
764 * connected.
765 */
766 if (phy->mode != USB_DR_MODE_HOST) {
767 val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID);
768 val |= VBUS_WAKEUP_WAKEUP_EN;
769 val &= ~(ID_CHG_DET | VBUS_WAKEUP_CHG_DET);
770 writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID);
771
772 val = readl_relaxed(base + USB_PHY_VBUS_SENSORS);
773 val |= A_VBUS_VLD_WAKEUP_EN;
774 writel_relaxed(val, base + USB_PHY_VBUS_SENSORS);
775 }
776 }
777
778 return utmip_pad_power_off(phy);
779}
780
781static int ulpi_phy_power_on(struct tegra_usb_phy *phy)
782{
783 void __iomem *base = phy->regs;
784 u32 val;
785 int err;
786
787 gpiod_set_value_cansleep(phy->reset_gpio, 1);
788
789 err = clk_prepare_enable(phy->clk);
790 if (err)
791 return err;
792
793 usleep_range(5000, 6000);
794
795 gpiod_set_value_cansleep(phy->reset_gpio, 0);
796
797 usleep_range(1000, 2000);
798
799 val = readl_relaxed(base + USB_SUSP_CTRL);
800 val |= UHSIC_RESET;
801 writel_relaxed(val, base + USB_SUSP_CTRL);
802
803 val = readl_relaxed(base + ULPI_TIMING_CTRL_0);
804 val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
805 writel_relaxed(val, base + ULPI_TIMING_CTRL_0);
806
807 val = readl_relaxed(base + USB_SUSP_CTRL);
808 val |= ULPI_PHY_ENABLE;
809 writel_relaxed(val, base + USB_SUSP_CTRL);
810
811 val = 0;
812 writel_relaxed(val, base + ULPI_TIMING_CTRL_1);
813
814 val |= ULPI_DATA_TRIMMER_SEL(4);
815 val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
816 val |= ULPI_DIR_TRIMMER_SEL(4);
817 writel_relaxed(val, base + ULPI_TIMING_CTRL_1);
818 usleep_range(10, 100);
819
820 val |= ULPI_DATA_TRIMMER_LOAD;
821 val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
822 val |= ULPI_DIR_TRIMMER_LOAD;
823 writel_relaxed(val, base + ULPI_TIMING_CTRL_1);
824
825 /* Fix VbusInvalid due to floating VBUS */
826 err = usb_phy_io_write(phy->ulpi, 0x40, 0x08);
827 if (err) {
828 dev_err(phy->u_phy.dev, "ULPI write failed: %d\n", err);
829 goto disable_clk;
830 }
831
832 err = usb_phy_io_write(phy->ulpi, 0x80, 0x0B);
833 if (err) {
834 dev_err(phy->u_phy.dev, "ULPI write failed: %d\n", err);
835 goto disable_clk;
836 }
837
838 val = readl_relaxed(base + USB_SUSP_CTRL);
839 val |= USB_SUSP_CLR;
840 writel_relaxed(val, base + USB_SUSP_CTRL);
841 usleep_range(100, 1000);
842
843 val = readl_relaxed(base + USB_SUSP_CTRL);
844 val &= ~USB_SUSP_CLR;
845 writel_relaxed(val, base + USB_SUSP_CTRL);
846
847 return 0;
848
849disable_clk:
850 clk_disable_unprepare(phy->clk);
851
852 return err;
853}
854
855static int ulpi_phy_power_off(struct tegra_usb_phy *phy)
856{
857 gpiod_set_value_cansleep(phy->reset_gpio, 1);
858 usleep_range(5000, 6000);
859 clk_disable_unprepare(phy->clk);
860
861 /*
862 * Wakeup currently unimplemented for ULPI, thus PHY needs to be
863 * force-resumed.
864 */
865 if (WARN_ON_ONCE(phy->wakeup_enabled)) {
866 ulpi_phy_power_on(phy);
867 return -EOPNOTSUPP;
868 }
869
870 return 0;
871}
872
873static u32 tegra_hsic_readl(struct tegra_usb_phy *phy, u32 reg)
874{
875 void __iomem *base = phy->regs;
876 u32 shift = phy->soc_config->uhsic_registers_offset;
877
878 return readl_relaxed(base + shift + reg);
879}
880
881static void tegra_hsic_writel(struct tegra_usb_phy *phy, u32 reg, u32 value)
882{
883 void __iomem *base = phy->regs;
884 u32 shift = phy->soc_config->uhsic_registers_offset;
885
886 writel_relaxed(value, base + shift + reg);
887}
888
889static int uhsic_phy_power_on(struct tegra_usb_phy *phy)
890{
891 struct tegra_utmip_config *config = phy->config;
892 void __iomem *base = phy->regs;
893 u32 val;
894 int err = 0;
895
896 val = tegra_hsic_readl(phy, UHSIC_PADS_CFG1);
897 val &= ~(UHSIC_PD_BG | UHSIC_PD_TX | UHSIC_PD_TRK | UHSIC_PD_RX |
898 UHSIC_PD_ZI | UHSIC_RPD_DATA | UHSIC_RPD_STROBE);
899 val |= UHSIC_RX_SEL;
900 tegra_hsic_writel(phy, UHSIC_PADS_CFG1, val);
901
902 udelay(2);
903
904 val = readl_relaxed(base + USB_SUSP_CTRL);
905 val |= UHSIC_RESET;
906 writel_relaxed(val, base + USB_SUSP_CTRL);
907
908 udelay(30);
909
910 val = readl_relaxed(base + USB_SUSP_CTRL);
911 val |= UHSIC_PHY_ENABLE;
912 writel_relaxed(val, base + USB_SUSP_CTRL);
913
914 val = tegra_hsic_readl(phy, UHSIC_HSRX_CFG0);
915 val &= ~(UHSIC_IDLE_WAIT(~0) |
916 UHSIC_ELASTIC_UNDERRUN_LIMIT(~0) |
917 UHSIC_ELASTIC_OVERRUN_LIMIT(~0));
918 val |= UHSIC_IDLE_WAIT(config->idle_wait_delay) |
919 UHSIC_ELASTIC_UNDERRUN_LIMIT(config->elastic_limit) |
920 UHSIC_ELASTIC_OVERRUN_LIMIT(config->elastic_limit);
921 tegra_hsic_writel(phy, UHSIC_HSRX_CFG0, val);
922
923 val = tegra_hsic_readl(phy, UHSIC_HSRX_CFG1);
924 val &= ~UHSIC_HS_SYNC_START_DLY(~0);
925 val |= UHSIC_HS_SYNC_START_DLY(config->hssync_start_delay);
926 tegra_hsic_writel(phy, UHSIC_HSRX_CFG1, val);
927
928 val = tegra_hsic_readl(phy, UHSIC_MISC_CFG0);
929 val |= UHSIC_SUSPEND_EXIT_ON_EDGE;
930 tegra_hsic_writel(phy, UHSIC_MISC_CFG0, val);
931
932 val = tegra_hsic_readl(phy, UHSIC_MISC_CFG1);
933 val &= ~UHSIC_PLLU_STABLE_COUNT(~0);
934 val |= UHSIC_PLLU_STABLE_COUNT(phy->freq->stable_count);
935 tegra_hsic_writel(phy, UHSIC_MISC_CFG1, val);
936
937 val = tegra_hsic_readl(phy, UHSIC_PLL_CFG1);
938 val &= ~(UHSIC_XTAL_FREQ_COUNT(~0) |
939 UHSIC_PLLU_ENABLE_DLY_COUNT(~0));
940 val |= UHSIC_XTAL_FREQ_COUNT(phy->freq->hsic_xtal_freq_count) |
941 UHSIC_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
942 tegra_hsic_writel(phy, UHSIC_PLL_CFG1, val);
943
944 val = readl_relaxed(base + USB_SUSP_CTRL);
945 val &= ~UHSIC_RESET;
946 writel_relaxed(val, base + USB_SUSP_CTRL);
947
948 udelay(2);
949
950 if (phy->soc_config->requires_usbmode_setup) {
951 val = readl_relaxed(base + USB_USBMODE);
952 val &= ~USB_USBMODE_MASK;
953 if (phy->mode == USB_DR_MODE_HOST)
954 val |= USB_USBMODE_HOST;
955 else
956 val |= USB_USBMODE_DEVICE;
957 writel_relaxed(val, base + USB_USBMODE);
958 }
959
960 set_pts(phy, phy->soc_config->uhsic_pts_value);
961
962 val = readl_relaxed(base + USB_TXFILLTUNING);
963 if ((val & USB_FIFO_TXFILL_MASK) != USB_FIFO_TXFILL_THRES(0x10)) {
964 val = USB_FIFO_TXFILL_THRES(0x10);
965 writel_relaxed(val, base + USB_TXFILLTUNING);
966 }
967
968 val = readl_relaxed(base + phy->soc_config->portsc1_offset);
969 val &= ~(TEGRA_USB_PORTSC1_WKOC | TEGRA_USB_PORTSC1_WKDS |
970 TEGRA_USB_PORTSC1_WKCN);
971 writel_relaxed(val, base + phy->soc_config->portsc1_offset);
972
973 val = tegra_hsic_readl(phy, UHSIC_PADS_CFG0);
974 val &= ~UHSIC_TX_RTUNEN;
975 val |= UHSIC_TX_RTUNE(phy->soc_config->uhsic_tx_rtune);
976 tegra_hsic_writel(phy, UHSIC_PADS_CFG0, val);
977
978 err = utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
979 USB_PHY_CLK_VALID);
980
981 if (err)
982 dev_err(phy->u_phy.dev,
983 "Timeout waiting for PHY to stabilize on enable (HSIC)\n");
984
985 return err;
986}
987
988static int uhsic_phy_power_off(struct tegra_usb_phy *phy)
989{
990 void __iomem *base = phy->regs;
991 u32 val;
992
993 set_phcd(phy, true);
994
995 val = tegra_hsic_readl(phy, UHSIC_PADS_CFG1);
996 val |= (UHSIC_PD_BG | UHSIC_PD_TX | UHSIC_PD_TRK | UHSIC_PD_RX |
997 UHSIC_PD_ZI | UHSIC_RPD_DATA | UHSIC_RPD_STROBE);
998 tegra_hsic_writel(phy, UHSIC_PADS_CFG1, val);
999
1000 val = readl_relaxed(base + USB_SUSP_CTRL);
1001 val |= UHSIC_RESET;
1002 writel_relaxed(val, base + USB_SUSP_CTRL);
1003
1004 udelay(30);
1005
1006 val = readl_relaxed(base + USB_SUSP_CTRL);
1007 val &= ~UHSIC_PHY_ENABLE;
1008 writel_relaxed(val, base + USB_SUSP_CTRL);
1009
1010 return 0;
1011}
1012
1013static int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
1014{
1015 int err = 0;
1016
1017 if (phy->powered_on)
1018 return 0;
1019
1020 switch (phy->phy_type) {
1021 case USBPHY_INTERFACE_MODE_UTMI:
1022 err = utmi_phy_power_on(phy);
1023 break;
1024
1025 case USBPHY_INTERFACE_MODE_ULPI:
1026 err = ulpi_phy_power_on(phy);
1027 break;
1028
1029 case USBPHY_INTERFACE_MODE_HSIC:
1030 err = uhsic_phy_power_on(phy);
1031 break;
1032
1033 default:
1034 break;
1035 }
1036
1037 if (err)
1038 return err;
1039
1040 phy->powered_on = true;
1041
1042 /* Let PHY settle down */
1043 usleep_range(2000, 2500);
1044
1045 return 0;
1046}
1047
1048static int tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
1049{
1050 int err = 0;
1051
1052 if (!phy->powered_on)
1053 return 0;
1054
1055 switch (phy->phy_type) {
1056 case USBPHY_INTERFACE_MODE_UTMI:
1057 err = utmi_phy_power_off(phy);
1058 break;
1059
1060 case USBPHY_INTERFACE_MODE_ULPI:
1061 err = ulpi_phy_power_off(phy);
1062 break;
1063
1064 case USBPHY_INTERFACE_MODE_HSIC:
1065 err = uhsic_phy_power_off(phy);
1066 break;
1067
1068 default:
1069 break;
1070 }
1071
1072 if (err)
1073 return err;
1074
1075 phy->powered_on = false;
1076
1077 return 0;
1078}
1079
1080static void tegra_usb_phy_shutdown(struct usb_phy *u_phy)
1081{
1082 struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
1083
1084 if (WARN_ON(!phy->freq))
1085 return;
1086
1087 usb_phy_set_wakeup(u_phy, false);
1088 tegra_usb_phy_power_off(phy);
1089
1090 if (phy->phy_type == USBPHY_INTERFACE_MODE_UTMI)
1091 utmip_pad_close(phy);
1092
1093 regulator_disable(phy->vbus);
1094 clk_disable_unprepare(phy->pll_u);
1095
1096 phy->freq = NULL;
1097}
1098
1099static irqreturn_t tegra_usb_phy_isr(int irq, void *data)
1100{
1101 u32 val, int_mask = ID_CHG_DET | VBUS_WAKEUP_CHG_DET;
1102 struct tegra_usb_phy *phy = data;
1103 void __iomem *base = phy->regs;
1104
1105 /*
1106 * The PHY interrupt also wakes the USB controller driver since
1107 * interrupt is shared. We don't do anything in the PHY driver,
1108 * so just clear the interrupt.
1109 */
1110 val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID);
1111 writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID);
1112
1113 return val & int_mask ? IRQ_HANDLED : IRQ_NONE;
1114}
1115
1116static int tegra_usb_phy_set_wakeup(struct usb_phy *u_phy, bool enable)
1117{
1118 struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
1119 void __iomem *base = phy->regs;
1120 int ret = 0;
1121 u32 val;
1122
1123 if (phy->wakeup_enabled && phy->mode != USB_DR_MODE_HOST &&
1124 phy->irq > 0) {
1125 disable_irq(phy->irq);
1126
1127 val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID);
1128 val &= ~(ID_INT_EN | VBUS_WAKEUP_INT_EN);
1129 writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID);
1130
1131 enable_irq(phy->irq);
1132
1133 free_irq(phy->irq, phy);
1134
1135 phy->wakeup_enabled = false;
1136 }
1137
1138 if (enable && phy->mode != USB_DR_MODE_HOST && phy->irq > 0) {
1139 ret = request_irq(phy->irq, tegra_usb_phy_isr, IRQF_SHARED,
1140 dev_name(phy->u_phy.dev), phy);
1141 if (!ret) {
1142 disable_irq(phy->irq);
1143
1144 /*
1145 * USB clock will be resumed once wake event will be
1146 * generated. The ID-change event requires to have
1147 * interrupts enabled, otherwise it won't be generated.
1148 */
1149 val = readl_relaxed(base + USB_PHY_VBUS_WAKEUP_ID);
1150 val |= ID_INT_EN | VBUS_WAKEUP_INT_EN;
1151 writel_relaxed(val, base + USB_PHY_VBUS_WAKEUP_ID);
1152
1153 enable_irq(phy->irq);
1154 } else {
1155 dev_err(phy->u_phy.dev,
1156 "Failed to request interrupt: %d", ret);
1157 enable = false;
1158 }
1159 }
1160
1161 phy->wakeup_enabled = enable;
1162
1163 return ret;
1164}
1165
1166static int tegra_usb_phy_set_suspend(struct usb_phy *u_phy, int suspend)
1167{
1168 struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
1169 int ret;
1170
1171 if (WARN_ON(!phy->freq))
1172 return -EINVAL;
1173
1174 /*
1175 * PHY is sharing IRQ with the CI driver, hence here we either
1176 * disable interrupt for both PHY and CI or for CI only. The
1177 * interrupt needs to be disabled while hardware is reprogrammed
1178 * because interrupt touches the programmed registers, and thus,
1179 * there could be a race condition.
1180 */
1181 if (phy->irq > 0)
1182 disable_irq(phy->irq);
1183
1184 if (suspend)
1185 ret = tegra_usb_phy_power_off(phy);
1186 else
1187 ret = tegra_usb_phy_power_on(phy);
1188
1189 if (phy->irq > 0)
1190 enable_irq(phy->irq);
1191
1192 return ret;
1193}
1194
1195static int tegra_usb_phy_configure_pmc(struct tegra_usb_phy *phy)
1196{
1197 int err, val = 0;
1198
1199 /* older device-trees don't have PMC regmap */
1200 if (!phy->pmc_regmap)
1201 return 0;
1202
1203 /*
1204 * Tegra20 has a different layout of PMC USB register bits and AO is
1205 * enabled by default after system reset on Tegra20, so assume nothing
1206 * to do on Tegra20.
1207 */
1208 if (!phy->soc_config->requires_pmc_ao_power_up)
1209 return 0;
1210
1211 /* enable VBUS wake-up detector */
1212 if (phy->mode != USB_DR_MODE_HOST)
1213 val |= VBUS_WAKEUP_PD_P0 << phy->instance * 4;
1214
1215 /* enable ID-pin ACC detector for OTG mode switching */
1216 if (phy->mode == USB_DR_MODE_OTG)
1217 val |= ID_PD_P0 << phy->instance * 4;
1218
1219 /* disable detectors to reset them */
1220 err = regmap_set_bits(phy->pmc_regmap, PMC_USB_AO, val);
1221 if (err) {
1222 dev_err(phy->u_phy.dev, "Failed to disable PMC AO: %d\n", err);
1223 return err;
1224 }
1225
1226 usleep_range(10, 100);
1227
1228 /* enable detectors */
1229 err = regmap_clear_bits(phy->pmc_regmap, PMC_USB_AO, val);
1230 if (err) {
1231 dev_err(phy->u_phy.dev, "Failed to enable PMC AO: %d\n", err);
1232 return err;
1233 }
1234
1235 /* detectors starts to work after 10ms */
1236 usleep_range(10000, 15000);
1237
1238 return 0;
1239}
1240
1241static int tegra_usb_phy_init(struct usb_phy *u_phy)
1242{
1243 struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
1244 unsigned long parent_rate;
1245 unsigned int i;
1246 int err;
1247
1248 if (WARN_ON(phy->freq))
1249 return 0;
1250
1251 err = clk_prepare_enable(phy->pll_u);
1252 if (err)
1253 return err;
1254
1255 parent_rate = clk_get_rate(clk_get_parent(phy->pll_u));
1256 for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) {
1257 if (tegra_freq_table[i].freq == parent_rate) {
1258 phy->freq = &tegra_freq_table[i];
1259 break;
1260 }
1261 }
1262 if (!phy->freq) {
1263 dev_err(phy->u_phy.dev, "Invalid pll_u parent rate %ld\n",
1264 parent_rate);
1265 err = -EINVAL;
1266 goto disable_clk;
1267 }
1268
1269 err = regulator_enable(phy->vbus);
1270 if (err) {
1271 dev_err(phy->u_phy.dev,
1272 "Failed to enable USB VBUS regulator: %d\n", err);
1273 goto disable_clk;
1274 }
1275
1276 if (phy->phy_type == USBPHY_INTERFACE_MODE_UTMI) {
1277 err = utmip_pad_open(phy);
1278 if (err)
1279 goto disable_vbus;
1280 }
1281
1282 err = tegra_usb_phy_configure_pmc(phy);
1283 if (err)
1284 goto close_phy;
1285
1286 err = tegra_usb_phy_power_on(phy);
1287 if (err)
1288 goto close_phy;
1289
1290 return 0;
1291
1292close_phy:
1293 if (phy->phy_type == USBPHY_INTERFACE_MODE_UTMI)
1294 utmip_pad_close(phy);
1295
1296disable_vbus:
1297 regulator_disable(phy->vbus);
1298
1299disable_clk:
1300 clk_disable_unprepare(phy->pll_u);
1301
1302 phy->freq = NULL;
1303
1304 return err;
1305}
1306
1307static int read_utmi_param(struct platform_device *pdev, const char *param,
1308 u8 *dest)
1309{
1310 u32 value;
1311 int err;
1312
1313 err = of_property_read_u32(pdev->dev.of_node, param, &value);
1314 if (err)
1315 dev_err(&pdev->dev,
1316 "Failed to read USB UTMI parameter %s: %d\n",
1317 param, err);
1318 else
1319 *dest = value;
1320
1321 return err;
1322}
1323
1324static int utmi_phy_probe(struct tegra_usb_phy *tegra_phy,
1325 struct platform_device *pdev)
1326{
1327 struct tegra_utmip_config *config;
1328 struct resource *res;
1329 int err;
1330
1331 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1332 if (!res) {
1333 dev_err(&pdev->dev, "Failed to get UTMI pad regs\n");
1334 return -ENXIO;
1335 }
1336
1337 /*
1338 * Note that UTMI pad registers are shared by all PHYs, therefore
1339 * devm_platform_ioremap_resource() can't be used here.
1340 */
1341 tegra_phy->pad_regs = devm_ioremap(&pdev->dev, res->start,
1342 resource_size(res));
1343 if (!tegra_phy->pad_regs) {
1344 dev_err(&pdev->dev, "Failed to remap UTMI pad regs\n");
1345 return -ENOMEM;
1346 }
1347
1348 tegra_phy->config = devm_kzalloc(&pdev->dev, sizeof(*config),
1349 GFP_KERNEL);
1350 if (!tegra_phy->config)
1351 return -ENOMEM;
1352
1353 config = tegra_phy->config;
1354
1355 err = read_utmi_param(pdev, "nvidia,hssync-start-delay",
1356 &config->hssync_start_delay);
1357 if (err)
1358 return err;
1359
1360 err = read_utmi_param(pdev, "nvidia,elastic-limit",
1361 &config->elastic_limit);
1362 if (err)
1363 return err;
1364
1365 err = read_utmi_param(pdev, "nvidia,idle-wait-delay",
1366 &config->idle_wait_delay);
1367 if (err)
1368 return err;
1369
1370 err = read_utmi_param(pdev, "nvidia,term-range-adj",
1371 &config->term_range_adj);
1372 if (err)
1373 return err;
1374
1375 err = read_utmi_param(pdev, "nvidia,xcvr-lsfslew",
1376 &config->xcvr_lsfslew);
1377 if (err)
1378 return err;
1379
1380 err = read_utmi_param(pdev, "nvidia,xcvr-lsrslew",
1381 &config->xcvr_lsrslew);
1382 if (err)
1383 return err;
1384
1385 if (tegra_phy->soc_config->requires_extra_tuning_parameters) {
1386 err = read_utmi_param(pdev, "nvidia,xcvr-hsslew",
1387 &config->xcvr_hsslew);
1388 if (err)
1389 return err;
1390
1391 err = read_utmi_param(pdev, "nvidia,hssquelch-level",
1392 &config->hssquelch_level);
1393 if (err)
1394 return err;
1395
1396 err = read_utmi_param(pdev, "nvidia,hsdiscon-level",
1397 &config->hsdiscon_level);
1398 if (err)
1399 return err;
1400 }
1401
1402 config->xcvr_setup_use_fuses = of_property_read_bool(
1403 pdev->dev.of_node, "nvidia,xcvr-setup-use-fuses");
1404
1405 if (!config->xcvr_setup_use_fuses) {
1406 err = read_utmi_param(pdev, "nvidia,xcvr-setup",
1407 &config->xcvr_setup);
1408 if (err)
1409 return err;
1410 }
1411
1412 return 0;
1413}
1414
1415static void tegra_usb_phy_put_pmc_device(void *dev)
1416{
1417 put_device(dev);
1418}
1419
1420static int tegra_usb_phy_parse_pmc(struct device *dev,
1421 struct tegra_usb_phy *phy)
1422{
1423 struct platform_device *pmc_pdev;
1424 struct of_phandle_args args;
1425 int err;
1426
1427 err = of_parse_phandle_with_fixed_args(dev->of_node, "nvidia,pmc",
1428 1, 0, &args);
1429 if (err) {
1430 if (err != -ENOENT)
1431 return err;
1432
1433 dev_warn_once(dev, "nvidia,pmc is missing, please update your device-tree\n");
1434 return 0;
1435 }
1436
1437 pmc_pdev = of_find_device_by_node(args.np);
1438 of_node_put(args.np);
1439 if (!pmc_pdev)
1440 return -ENODEV;
1441
1442 err = devm_add_action_or_reset(dev, tegra_usb_phy_put_pmc_device,
1443 &pmc_pdev->dev);
1444 if (err)
1445 return err;
1446
1447 if (!platform_get_drvdata(pmc_pdev))
1448 return -EPROBE_DEFER;
1449
1450 phy->pmc_regmap = dev_get_regmap(&pmc_pdev->dev, "usb_sleepwalk");
1451 if (!phy->pmc_regmap)
1452 return -EINVAL;
1453
1454 phy->instance = args.args[0];
1455
1456 return 0;
1457}
1458
1459static const struct tegra_phy_soc_config tegra20_soc_config = {
1460 .utmi_pll_config_in_car_module = false,
1461 .has_hostpc = false,
1462 .requires_usbmode_setup = false,
1463 .requires_extra_tuning_parameters = false,
1464 .requires_pmc_ao_power_up = false,
1465 .uhsic_registers_offset = 0,
1466 .uhsic_tx_rtune = 0, /* 40 ohm */
1467 .uhsic_pts_value = 0, /* UTMI */
1468 .portsc1_offset = TEGRA_USB_PORTSC1,
1469};
1470
1471static const struct tegra_phy_soc_config tegra30_soc_config = {
1472 .utmi_pll_config_in_car_module = true,
1473 .has_hostpc = true,
1474 .requires_usbmode_setup = true,
1475 .requires_extra_tuning_parameters = true,
1476 .requires_pmc_ao_power_up = true,
1477 .uhsic_registers_offset = 0x400,
1478 .uhsic_tx_rtune = 8, /* 50 ohm */
1479 .uhsic_pts_value = TEGRA_USB_HOSTPC1_DEVLC_PTS_HSIC,
1480 .portsc1_offset = TEGRA30_USB_PORTSC1,
1481};
1482
1483static const struct of_device_id tegra_usb_phy_id_table[] = {
1484 { .compatible = "nvidia,tegra30-usb-phy", .data = &tegra30_soc_config },
1485 { .compatible = "nvidia,tegra20-usb-phy", .data = &tegra20_soc_config },
1486 { },
1487};
1488MODULE_DEVICE_TABLE(of, tegra_usb_phy_id_table);
1489
1490static int tegra_usb_phy_probe(struct platform_device *pdev)
1491{
1492 struct device_node *np = pdev->dev.of_node;
1493 struct tegra_usb_phy *tegra_phy;
1494 struct reset_control *reset;
1495 struct gpio_desc *gpiod;
1496 struct resource *res;
1497 struct usb_phy *phy;
1498 int err;
1499
1500 tegra_phy = devm_kzalloc(&pdev->dev, sizeof(*tegra_phy), GFP_KERNEL);
1501 if (!tegra_phy)
1502 return -ENOMEM;
1503
1504 tegra_phy->soc_config = of_device_get_match_data(&pdev->dev);
1505 tegra_phy->irq = platform_get_irq_optional(pdev, 0);
1506
1507 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1508 if (!res) {
1509 dev_err(&pdev->dev, "Failed to get I/O memory\n");
1510 return -ENXIO;
1511 }
1512
1513 /*
1514 * Note that PHY and USB controller are using shared registers,
1515 * therefore devm_platform_ioremap_resource() can't be used here.
1516 */
1517 tegra_phy->regs = devm_ioremap(&pdev->dev, res->start,
1518 resource_size(res));
1519 if (!tegra_phy->regs) {
1520 dev_err(&pdev->dev, "Failed to remap I/O memory\n");
1521 return -ENOMEM;
1522 }
1523
1524 tegra_phy->is_legacy_phy =
1525 of_property_read_bool(np, "nvidia,has-legacy-mode");
1526
1527 if (of_property_present(np, "dr_mode"))
1528 tegra_phy->mode = usb_get_dr_mode(&pdev->dev);
1529 else
1530 tegra_phy->mode = USB_DR_MODE_HOST;
1531
1532 if (tegra_phy->mode == USB_DR_MODE_UNKNOWN) {
1533 dev_err(&pdev->dev, "dr_mode is invalid\n");
1534 return -EINVAL;
1535 }
1536
1537 /* On some boards, the VBUS regulator doesn't need to be controlled */
1538 tegra_phy->vbus = devm_regulator_get(&pdev->dev, "vbus");
1539 if (IS_ERR(tegra_phy->vbus))
1540 return PTR_ERR(tegra_phy->vbus);
1541
1542 tegra_phy->pll_u = devm_clk_get(&pdev->dev, "pll_u");
1543 err = PTR_ERR_OR_ZERO(tegra_phy->pll_u);
1544 if (err) {
1545 dev_err(&pdev->dev, "Failed to get pll_u clock: %d\n", err);
1546 return err;
1547 }
1548
1549 err = tegra_usb_phy_parse_pmc(&pdev->dev, tegra_phy);
1550 if (err) {
1551 dev_err_probe(&pdev->dev, err, "Failed to get PMC regmap\n");
1552 return err;
1553 }
1554
1555 tegra_phy->phy_type = of_usb_get_phy_mode(np);
1556 switch (tegra_phy->phy_type) {
1557 case USBPHY_INTERFACE_MODE_UTMI:
1558 case USBPHY_INTERFACE_MODE_HSIC:
1559 err = utmi_phy_probe(tegra_phy, pdev);
1560 if (err)
1561 return err;
1562
1563 tegra_phy->pad_clk = devm_clk_get(&pdev->dev, "utmi-pads");
1564 err = PTR_ERR_OR_ZERO(tegra_phy->pad_clk);
1565 if (err) {
1566 dev_err(&pdev->dev,
1567 "Failed to get UTMIP pad clock: %d\n", err);
1568 return err;
1569 }
1570
1571 reset = devm_reset_control_get_optional_shared(&pdev->dev,
1572 "utmi-pads");
1573 err = PTR_ERR_OR_ZERO(reset);
1574 if (err) {
1575 dev_err(&pdev->dev,
1576 "Failed to get UTMI-pads reset: %d\n", err);
1577 return err;
1578 }
1579 tegra_phy->pad_rst = reset;
1580 break;
1581
1582 case USBPHY_INTERFACE_MODE_ULPI:
1583 tegra_phy->clk = devm_clk_get(&pdev->dev, "ulpi-link");
1584 err = PTR_ERR_OR_ZERO(tegra_phy->clk);
1585 if (err) {
1586 dev_err(&pdev->dev,
1587 "Failed to get ULPI clock: %d\n", err);
1588 return err;
1589 }
1590
1591 gpiod = devm_gpiod_get(&pdev->dev, "nvidia,phy-reset",
1592 GPIOD_OUT_HIGH);
1593 err = PTR_ERR_OR_ZERO(gpiod);
1594 if (err) {
1595 dev_err(&pdev->dev,
1596 "Request failed for reset GPIO: %d\n", err);
1597 return err;
1598 }
1599
1600 err = gpiod_set_consumer_name(gpiod, "ulpi_phy_reset_b");
1601 if (err) {
1602 dev_err(&pdev->dev,
1603 "Failed to set up reset GPIO name: %d\n", err);
1604 return err;
1605 }
1606
1607 tegra_phy->reset_gpio = gpiod;
1608
1609 phy = devm_otg_ulpi_create(&pdev->dev,
1610 &ulpi_viewport_access_ops, 0);
1611 if (!phy) {
1612 dev_err(&pdev->dev, "Failed to create ULPI OTG\n");
1613 return -ENOMEM;
1614 }
1615
1616 tegra_phy->ulpi = phy;
1617 tegra_phy->ulpi->io_priv = tegra_phy->regs + ULPI_VIEWPORT;
1618 break;
1619
1620 default:
1621 dev_err(&pdev->dev, "phy_type %u is invalid or unsupported\n",
1622 tegra_phy->phy_type);
1623 return -EINVAL;
1624 }
1625
1626 tegra_phy->u_phy.dev = &pdev->dev;
1627 tegra_phy->u_phy.init = tegra_usb_phy_init;
1628 tegra_phy->u_phy.shutdown = tegra_usb_phy_shutdown;
1629 tegra_phy->u_phy.set_wakeup = tegra_usb_phy_set_wakeup;
1630 tegra_phy->u_phy.set_suspend = tegra_usb_phy_set_suspend;
1631
1632 platform_set_drvdata(pdev, tegra_phy);
1633
1634 return usb_add_phy_dev(&tegra_phy->u_phy);
1635}
1636
1637static void tegra_usb_phy_remove(struct platform_device *pdev)
1638{
1639 struct tegra_usb_phy *tegra_phy = platform_get_drvdata(pdev);
1640
1641 usb_remove_phy(&tegra_phy->u_phy);
1642}
1643
1644static struct platform_driver tegra_usb_phy_driver = {
1645 .probe = tegra_usb_phy_probe,
1646 .remove = tegra_usb_phy_remove,
1647 .driver = {
1648 .name = "tegra-phy",
1649 .of_match_table = tegra_usb_phy_id_table,
1650 },
1651};
1652module_platform_driver(tegra_usb_phy_driver);
1653
1654MODULE_DESCRIPTION("Tegra USB PHY driver");
1655MODULE_LICENSE("GPL v2");