Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2017 - 2022: Samsung Electronics Co., Ltd.
4 * https://www.samsung.com
5 * Copyright (c) 2017-2022 Tesla, Inc.
6 * https://www.tesla.com
7 *
8 * The constants defined in this header are being used in dts
9 * and fsd platform driver.
10 */
11
12#ifndef _DT_BINDINGS_CLOCK_FSD_H
13#define _DT_BINDINGS_CLOCK_FSD_H
14
15/* CMU */
16#define DOUT_CMU_PLL_SHARED0_DIV4 1
17#define DOUT_CMU_PERIC_SHARED1DIV36 2
18#define DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK 3
19#define DOUT_CMU_PERIC_SHARED0DIV20 4
20#define DOUT_CMU_PERIC_SHARED1DIV4_DMACLK 5
21#define DOUT_CMU_PLL_SHARED0_DIV6 6
22#define DOUT_CMU_FSYS0_SHARED1DIV4 7
23#define DOUT_CMU_FSYS0_SHARED0DIV4 8
24#define DOUT_CMU_FSYS1_SHARED0DIV8 9
25#define DOUT_CMU_FSYS1_SHARED0DIV4 10
26#define CMU_CPUCL_SWITCH_GATE 11
27#define DOUT_CMU_IMEM_TCUCLK 12
28#define DOUT_CMU_IMEM_ACLK 13
29#define DOUT_CMU_IMEM_DMACLK 14
30#define GAT_CMU_FSYS0_SHARED0DIV4 15
31
32/* PERIC */
33#define PERIC_SCLK_UART0 1
34#define PERIC_PCLK_UART0 2
35#define PERIC_SCLK_UART1 3
36#define PERIC_PCLK_UART1 4
37#define PERIC_DMA0_IPCLKPORT_ACLK 5
38#define PERIC_DMA1_IPCLKPORT_ACLK 6
39#define PERIC_PWM0_IPCLKPORT_I_PCLK_S0 7
40#define PERIC_PWM1_IPCLKPORT_I_PCLK_S0 8
41#define PERIC_PCLK_SPI0 9
42#define PERIC_SCLK_SPI0 10
43#define PERIC_PCLK_SPI1 11
44#define PERIC_SCLK_SPI1 12
45#define PERIC_PCLK_SPI2 13
46#define PERIC_SCLK_SPI2 14
47#define PERIC_PCLK_TDM0 15
48#define PERIC_PCLK_HSI2C0 16
49#define PERIC_PCLK_HSI2C1 17
50#define PERIC_PCLK_HSI2C2 18
51#define PERIC_PCLK_HSI2C3 19
52#define PERIC_PCLK_HSI2C4 20
53#define PERIC_PCLK_HSI2C5 21
54#define PERIC_PCLK_HSI2C6 22
55#define PERIC_PCLK_HSI2C7 23
56#define PERIC_MCAN0_IPCLKPORT_CCLK 24
57#define PERIC_MCAN0_IPCLKPORT_PCLK 25
58#define PERIC_MCAN1_IPCLKPORT_CCLK 26
59#define PERIC_MCAN1_IPCLKPORT_PCLK 27
60#define PERIC_MCAN2_IPCLKPORT_CCLK 28
61#define PERIC_MCAN2_IPCLKPORT_PCLK 29
62#define PERIC_MCAN3_IPCLKPORT_CCLK 30
63#define PERIC_MCAN3_IPCLKPORT_PCLK 31
64#define PERIC_PCLK_ADCIF 32
65#define PERIC_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I 33
66#define PERIC_EQOS_TOP_IPCLKPORT_ACLK_I 34
67#define PERIC_EQOS_TOP_IPCLKPORT_HCLK_I 35
68#define PERIC_EQOS_TOP_IPCLKPORT_RGMII_CLK_I 36
69#define PERIC_EQOS_TOP_IPCLKPORT_CLK_RX_I 37
70#define PERIC_BUS_D_PERIC_IPCLKPORT_EQOSCLK 38
71#define PERIC_BUS_P_PERIC_IPCLKPORT_EQOSCLK 39
72#define PERIC_HCLK_TDM0 40
73#define PERIC_PCLK_TDM1 41
74#define PERIC_HCLK_TDM1 42
75#define PERIC_EQOS_PHYRXCLK_MUX 43
76#define PERIC_EQOS_PHYRXCLK 44
77#define PERIC_DOUT_RGMII_CLK 45
78
79/* FSYS0 */
80#define UFS0_MPHY_REFCLK_IXTAL24 1
81#define UFS0_MPHY_REFCLK_IXTAL26 2
82#define UFS1_MPHY_REFCLK_IXTAL24 3
83#define UFS1_MPHY_REFCLK_IXTAL26 4
84#define UFS0_TOP0_HCLK_BUS 5
85#define UFS0_TOP0_ACLK 6
86#define UFS0_TOP0_CLK_UNIPRO 7
87#define UFS0_TOP0_FMP_CLK 8
88#define UFS1_TOP1_HCLK_BUS 9
89#define UFS1_TOP1_ACLK 10
90#define UFS1_TOP1_CLK_UNIPRO 11
91#define UFS1_TOP1_FMP_CLK 12
92#define PCIE_SUBCTRL_INST0_DBI_ACLK_SOC 13
93#define PCIE_SUBCTRL_INST0_AUX_CLK_SOC 14
94#define PCIE_SUBCTRL_INST0_MSTR_ACLK_SOC 15
95#define PCIE_SUBCTRL_INST0_SLV_ACLK_SOC 16
96#define FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I 17
97#define FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I 18
98#define FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I 19
99#define FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I 20
100#define FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I 21
101#define FSYS0_DOUT_FSYS0_PERIBUS_GRP 22
102
103/* FSYS1 */
104#define PCIE_LINK0_IPCLKPORT_DBI_ACLK 1
105#define PCIE_LINK0_IPCLKPORT_AUX_ACLK 2
106#define PCIE_LINK0_IPCLKPORT_MSTR_ACLK 3
107#define PCIE_LINK0_IPCLKPORT_SLV_ACLK 4
108#define PCIE_LINK1_IPCLKPORT_DBI_ACLK 5
109#define PCIE_LINK1_IPCLKPORT_AUX_ACLK 6
110#define PCIE_LINK1_IPCLKPORT_MSTR_ACLK 7
111#define PCIE_LINK1_IPCLKPORT_SLV_ACLK 8
112
113/* IMEM */
114#define IMEM_DMA0_IPCLKPORT_ACLK 1
115#define IMEM_DMA1_IPCLKPORT_ACLK 2
116#define IMEM_WDT0_IPCLKPORT_PCLK 3
117#define IMEM_WDT1_IPCLKPORT_PCLK 4
118#define IMEM_WDT2_IPCLKPORT_PCLK 5
119#define IMEM_MCT_PCLK 6
120#define IMEM_TMU_CPU0_IPCLKPORT_I_CLK_TS 7
121#define IMEM_TMU_CPU2_IPCLKPORT_I_CLK_TS 8
122#define IMEM_TMU_TOP_IPCLKPORT_I_CLK_TS 9
123#define IMEM_TMU_GPU_IPCLKPORT_I_CLK_TS 10
124#define IMEM_TMU_GT_IPCLKPORT_I_CLK_TS 11
125
126/* MFC */
127#define MFC_MFC_IPCLKPORT_ACLK 1
128
129/* CAM_CSI */
130#define CAM_CSI0_0_IPCLKPORT_I_ACLK 1
131#define CAM_CSI0_1_IPCLKPORT_I_ACLK 2
132#define CAM_CSI0_2_IPCLKPORT_I_ACLK 3
133#define CAM_CSI0_3_IPCLKPORT_I_ACLK 4
134#define CAM_CSI1_0_IPCLKPORT_I_ACLK 5
135#define CAM_CSI1_1_IPCLKPORT_I_ACLK 6
136#define CAM_CSI1_2_IPCLKPORT_I_ACLK 7
137#define CAM_CSI1_3_IPCLKPORT_I_ACLK 8
138#define CAM_CSI2_0_IPCLKPORT_I_ACLK 9
139#define CAM_CSI2_1_IPCLKPORT_I_ACLK 10
140#define CAM_CSI2_2_IPCLKPORT_I_ACLK 11
141#define CAM_CSI2_3_IPCLKPORT_I_ACLK 12
142#define CAM_CSI_PLL 13
143#define CAM_CSI0_0_IPCLKPORT_I_PCLK 14
144#define CAM_CSI0_1_IPCLKPORT_I_PCLK 15
145#define CAM_CSI0_2_IPCLKPORT_I_PCLK 16
146#define CAM_CSI0_3_IPCLKPORT_I_PCLK 17
147#define CAM_CSI1_0_IPCLKPORT_I_PCLK 18
148#define CAM_CSI1_1_IPCLKPORT_I_PCLK 19
149#define CAM_CSI1_2_IPCLKPORT_I_PCLK 20
150#define CAM_CSI1_3_IPCLKPORT_I_PCLK 21
151#define CAM_CSI2_0_IPCLKPORT_I_PCLK 22
152#define CAM_CSI2_1_IPCLKPORT_I_PCLK 23
153#define CAM_CSI2_2_IPCLKPORT_I_PCLK 24
154#define CAM_CSI2_3_IPCLKPORT_I_PCLK 25
155
156#endif /*_DT_BINDINGS_CLOCK_FSD_H */