Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2/*
3 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
4 * Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com>
5 */
6
7#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_MILOS_H
8#define _DT_BINDINGS_CLK_QCOM_DISP_CC_MILOS_H
9
10/* DISP_CC clocks */
11#define DISP_CC_PLL0 0
12#define DISP_CC_MDSS_ACCU_CLK 1
13#define DISP_CC_MDSS_AHB1_CLK 2
14#define DISP_CC_MDSS_AHB_CLK 3
15#define DISP_CC_MDSS_AHB_CLK_SRC 4
16#define DISP_CC_MDSS_BYTE0_CLK 5
17#define DISP_CC_MDSS_BYTE0_CLK_SRC 6
18#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 7
19#define DISP_CC_MDSS_BYTE0_INTF_CLK 8
20#define DISP_CC_MDSS_DPTX0_AUX_CLK 9
21#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 10
22#define DISP_CC_MDSS_DPTX0_CRYPTO_CLK 11
23#define DISP_CC_MDSS_DPTX0_LINK_CLK 12
24#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 13
25#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 14
26#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 15
27#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 16
28#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 17
29#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 18
30#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 19
31#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 20
32#define DISP_CC_MDSS_ESC0_CLK 21
33#define DISP_CC_MDSS_ESC0_CLK_SRC 22
34#define DISP_CC_MDSS_MDP1_CLK 23
35#define DISP_CC_MDSS_MDP_CLK 24
36#define DISP_CC_MDSS_MDP_CLK_SRC 25
37#define DISP_CC_MDSS_MDP_LUT1_CLK 26
38#define DISP_CC_MDSS_MDP_LUT_CLK 27
39#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 28
40#define DISP_CC_MDSS_PCLK0_CLK 29
41#define DISP_CC_MDSS_PCLK0_CLK_SRC 30
42#define DISP_CC_MDSS_RSCC_AHB_CLK 31
43#define DISP_CC_MDSS_RSCC_VSYNC_CLK 32
44#define DISP_CC_MDSS_VSYNC1_CLK 33
45#define DISP_CC_MDSS_VSYNC_CLK 34
46#define DISP_CC_MDSS_VSYNC_CLK_SRC 35
47#define DISP_CC_SLEEP_CLK 36
48#define DISP_CC_SLEEP_CLK_SRC 37
49#define DISP_CC_XO_CLK 38
50#define DISP_CC_XO_CLK_SRC 39
51
52/* DISP_CC resets */
53#define DISP_CC_MDSS_CORE_BCR 0
54#define DISP_CC_MDSS_CORE_INT2_BCR 1
55#define DISP_CC_MDSS_RSCC_BCR 2
56
57/* DISP_CC power domains */
58#define DISP_CC_MDSS_CORE_GDSC 0
59#define DISP_CC_MDSS_CORE_INT2_GDSC 1
60
61#endif