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1/* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*-
2 *
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Copyright 2014 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
24 * OTHER DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32#ifndef __AMDGPU_DRM_H__
33#define __AMDGPU_DRM_H__
34
35#include "drm.h"
36
37#if defined(__cplusplus)
38extern "C" {
39#endif
40
41#define DRM_AMDGPU_GEM_CREATE 0x00
42#define DRM_AMDGPU_GEM_MMAP 0x01
43#define DRM_AMDGPU_CTX 0x02
44#define DRM_AMDGPU_BO_LIST 0x03
45#define DRM_AMDGPU_CS 0x04
46#define DRM_AMDGPU_INFO 0x05
47#define DRM_AMDGPU_GEM_METADATA 0x06
48#define DRM_AMDGPU_GEM_WAIT_IDLE 0x07
49#define DRM_AMDGPU_GEM_VA 0x08
50#define DRM_AMDGPU_WAIT_CS 0x09
51#define DRM_AMDGPU_GEM_OP 0x10
52#define DRM_AMDGPU_GEM_USERPTR 0x11
53#define DRM_AMDGPU_WAIT_FENCES 0x12
54#define DRM_AMDGPU_VM 0x13
55#define DRM_AMDGPU_FENCE_TO_HANDLE 0x14
56#define DRM_AMDGPU_SCHED 0x15
57#define DRM_AMDGPU_USERQ 0x16
58#define DRM_AMDGPU_USERQ_SIGNAL 0x17
59#define DRM_AMDGPU_USERQ_WAIT 0x18
60#define DRM_AMDGPU_GEM_LIST_HANDLES 0x19
61
62#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
63#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
64#define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx)
65#define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list)
66#define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs)
67#define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info)
68#define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata)
69#define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle)
70#define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va)
71#define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
72#define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
73#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
74#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
75#define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
76#define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
77#define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
78#define DRM_IOCTL_AMDGPU_USERQ DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ, union drm_amdgpu_userq)
79#define DRM_IOCTL_AMDGPU_USERQ_SIGNAL DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_SIGNAL, struct drm_amdgpu_userq_signal)
80#define DRM_IOCTL_AMDGPU_USERQ_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_WAIT, struct drm_amdgpu_userq_wait)
81#define DRM_IOCTL_AMDGPU_GEM_LIST_HANDLES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_LIST_HANDLES, struct drm_amdgpu_gem_list_handles)
82
83/**
84 * DOC: memory domains
85 *
86 * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible.
87 * Memory in this pool could be swapped out to disk if there is pressure.
88 *
89 * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the
90 * GPU's virtual address space via gart. Gart memory linearizes non-contiguous
91 * pages of system memory, allows GPU access system memory in a linearized
92 * fashion.
93 *
94 * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory
95 * carved out by the BIOS.
96 *
97 * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data
98 * across shader threads.
99 *
100 * %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the
101 * execution of all the waves on a device.
102 *
103 * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines
104 * for appending data.
105 *
106 * %AMDGPU_GEM_DOMAIN_DOORBELL Doorbell. It is an MMIO region for
107 * signalling user mode queues.
108 */
109#define AMDGPU_GEM_DOMAIN_CPU 0x1
110#define AMDGPU_GEM_DOMAIN_GTT 0x2
111#define AMDGPU_GEM_DOMAIN_VRAM 0x4
112#define AMDGPU_GEM_DOMAIN_GDS 0x8
113#define AMDGPU_GEM_DOMAIN_GWS 0x10
114#define AMDGPU_GEM_DOMAIN_OA 0x20
115#define AMDGPU_GEM_DOMAIN_DOORBELL 0x40
116#define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \
117 AMDGPU_GEM_DOMAIN_GTT | \
118 AMDGPU_GEM_DOMAIN_VRAM | \
119 AMDGPU_GEM_DOMAIN_GDS | \
120 AMDGPU_GEM_DOMAIN_GWS | \
121 AMDGPU_GEM_DOMAIN_OA | \
122 AMDGPU_GEM_DOMAIN_DOORBELL)
123
124/* Flag that CPU access will be required for the case of VRAM domain */
125#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
126/* Flag that CPU access will not work, this VRAM domain is invisible */
127#define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1)
128/* Flag that USWC attributes should be used for GTT */
129#define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2)
130/* Flag that the memory should be in VRAM and cleared */
131#define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3)
132/* Flag that allocating the BO should use linear VRAM */
133#define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5)
134/* Flag that BO is always valid in this VM */
135#define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)
136/* Flag that BO sharing will be explicitly synchronized */
137#define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7)
138/* Flag that indicates allocating MQD gart on GFX9, where the mtype
139 * for the second page onward should be set to NC. It should never
140 * be used by user space applications.
141 */
142#define AMDGPU_GEM_CREATE_CP_MQD_GFX9 (1 << 8)
143/* Flag that BO may contain sensitive data that must be wiped before
144 * releasing the memory
145 */
146#define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9)
147/* Flag that BO will be encrypted and that the TMZ bit should be
148 * set in the PTEs when mapping this buffer via GPUVM or
149 * accessing it with various hw blocks
150 */
151#define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10)
152/* Flag that BO will be used only in preemptible context, which does
153 * not require GTT memory accounting
154 */
155#define AMDGPU_GEM_CREATE_PREEMPTIBLE (1 << 11)
156/* Flag that BO can be discarded under memory pressure without keeping the
157 * content.
158 */
159#define AMDGPU_GEM_CREATE_DISCARDABLE (1 << 12)
160/* Flag that BO is shared coherently between multiple devices or CPU threads.
161 * May depend on GPU instructions to flush caches to system scope explicitly.
162 *
163 * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and
164 * may override the MTYPE selected in AMDGPU_VA_OP_MAP.
165 */
166#define AMDGPU_GEM_CREATE_COHERENT (1 << 13)
167/* Flag that BO should not be cached by GPU. Coherent without having to flush
168 * GPU caches explicitly
169 *
170 * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and
171 * may override the MTYPE selected in AMDGPU_VA_OP_MAP.
172 */
173#define AMDGPU_GEM_CREATE_UNCACHED (1 << 14)
174/* Flag that BO should be coherent across devices when using device-level
175 * atomics. May depend on GPU instructions to flush caches to device scope
176 * explicitly, promoting them to system scope automatically.
177 *
178 * This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and
179 * may override the MTYPE selected in AMDGPU_VA_OP_MAP.
180 */
181#define AMDGPU_GEM_CREATE_EXT_COHERENT (1 << 15)
182/* Set PTE.D and recompress during GTT->VRAM moves according to TILING flags. */
183#define AMDGPU_GEM_CREATE_GFX12_DCC (1 << 16)
184
185struct drm_amdgpu_gem_create_in {
186 /** the requested memory size */
187 __u64 bo_size;
188 /** physical start_addr alignment in bytes for some HW requirements */
189 __u64 alignment;
190 /** the requested memory domains */
191 __u64 domains;
192 /** allocation flags */
193 __u64 domain_flags;
194};
195
196struct drm_amdgpu_gem_create_out {
197 /** returned GEM object handle */
198 __u32 handle;
199 __u32 _pad;
200};
201
202union drm_amdgpu_gem_create {
203 struct drm_amdgpu_gem_create_in in;
204 struct drm_amdgpu_gem_create_out out;
205};
206
207/** Opcode to create new residency list. */
208#define AMDGPU_BO_LIST_OP_CREATE 0
209/** Opcode to destroy previously created residency list */
210#define AMDGPU_BO_LIST_OP_DESTROY 1
211/** Opcode to update resource information in the list */
212#define AMDGPU_BO_LIST_OP_UPDATE 2
213
214struct drm_amdgpu_bo_list_in {
215 /** Type of operation */
216 __u32 operation;
217 /** Handle of list or 0 if we want to create one */
218 __u32 list_handle;
219 /** Number of BOs in list */
220 __u32 bo_number;
221 /** Size of each element describing BO */
222 __u32 bo_info_size;
223 /** Pointer to array describing BOs */
224 __u64 bo_info_ptr;
225};
226
227struct drm_amdgpu_bo_list_entry {
228 /** Handle of BO */
229 __u32 bo_handle;
230 /** New (if specified) BO priority to be used during migration */
231 __u32 bo_priority;
232};
233
234struct drm_amdgpu_bo_list_out {
235 /** Handle of resource list */
236 __u32 list_handle;
237 __u32 _pad;
238};
239
240union drm_amdgpu_bo_list {
241 struct drm_amdgpu_bo_list_in in;
242 struct drm_amdgpu_bo_list_out out;
243};
244
245/* context related */
246#define AMDGPU_CTX_OP_ALLOC_CTX 1
247#define AMDGPU_CTX_OP_FREE_CTX 2
248#define AMDGPU_CTX_OP_QUERY_STATE 3
249#define AMDGPU_CTX_OP_QUERY_STATE2 4
250#define AMDGPU_CTX_OP_GET_STABLE_PSTATE 5
251#define AMDGPU_CTX_OP_SET_STABLE_PSTATE 6
252
253/* GPU reset status */
254#define AMDGPU_CTX_NO_RESET 0
255/* this the context caused it */
256#define AMDGPU_CTX_GUILTY_RESET 1
257/* some other context caused it */
258#define AMDGPU_CTX_INNOCENT_RESET 2
259/* unknown cause */
260#define AMDGPU_CTX_UNKNOWN_RESET 3
261
262/* indicate gpu reset occurred after ctx created */
263#define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0)
264/* indicate vram lost occurred after ctx created */
265#define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1)
266/* indicate some job from this context once cause gpu hang */
267#define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2)
268/* indicate some errors are detected by RAS */
269#define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3)
270#define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4)
271/* indicate that the reset hasn't completed yet */
272#define AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS (1<<5)
273
274/* Context priority level */
275#define AMDGPU_CTX_PRIORITY_UNSET -2048
276#define AMDGPU_CTX_PRIORITY_VERY_LOW -1023
277#define AMDGPU_CTX_PRIORITY_LOW -512
278#define AMDGPU_CTX_PRIORITY_NORMAL 0
279/*
280 * When used in struct drm_amdgpu_ctx_in, a priority above NORMAL requires
281 * CAP_SYS_NICE or DRM_MASTER
282*/
283#define AMDGPU_CTX_PRIORITY_HIGH 512
284#define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023
285
286/* select a stable profiling pstate for perfmon tools */
287#define AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK 0xf
288#define AMDGPU_CTX_STABLE_PSTATE_NONE 0
289#define AMDGPU_CTX_STABLE_PSTATE_STANDARD 1
290#define AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK 2
291#define AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK 3
292#define AMDGPU_CTX_STABLE_PSTATE_PEAK 4
293
294struct drm_amdgpu_ctx_in {
295 /** AMDGPU_CTX_OP_* */
296 __u32 op;
297 /** Flags */
298 __u32 flags;
299 __u32 ctx_id;
300 /** AMDGPU_CTX_PRIORITY_* */
301 __s32 priority;
302};
303
304union drm_amdgpu_ctx_out {
305 struct {
306 __u32 ctx_id;
307 __u32 _pad;
308 } alloc;
309
310 struct {
311 /** For future use, no flags defined so far */
312 __u64 flags;
313 /** Number of resets caused by this context so far. */
314 __u32 hangs;
315 /** Reset status since the last call of the ioctl. */
316 __u32 reset_status;
317 } state;
318
319 struct {
320 __u32 flags;
321 __u32 _pad;
322 } pstate;
323};
324
325union drm_amdgpu_ctx {
326 struct drm_amdgpu_ctx_in in;
327 union drm_amdgpu_ctx_out out;
328};
329
330/* user queue IOCTL operations */
331#define AMDGPU_USERQ_OP_CREATE 1
332#define AMDGPU_USERQ_OP_FREE 2
333
334/* queue priority levels */
335/* low < normal low < normal high < high */
336#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_MASK 0x3
337#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_SHIFT 0
338#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_LOW 0
339#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_LOW 1
340#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_NORMAL_HIGH 2
341#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_PRIORITY_HIGH 3 /* admin only */
342/* for queues that need access to protected content */
343#define AMDGPU_USERQ_CREATE_FLAGS_QUEUE_SECURE (1 << 2)
344
345/*
346 * This structure is a container to pass input configuration
347 * info for all supported userqueue related operations.
348 * For operation AMDGPU_USERQ_OP_CREATE: user is expected
349 * to set all fields, excep the parameter 'queue_id'.
350 * For operation AMDGPU_USERQ_OP_FREE: the only input parameter expected
351 * to be set is 'queue_id', eveything else is ignored.
352 */
353struct drm_amdgpu_userq_in {
354 /** AMDGPU_USERQ_OP_* */
355 __u32 op;
356 /** Queue id passed for operation USERQ_OP_FREE */
357 __u32 queue_id;
358 /** the target GPU engine to execute workload (AMDGPU_HW_IP_*) */
359 __u32 ip_type;
360 /**
361 * @doorbell_handle: the handle of doorbell GEM object
362 * associated with this userqueue client.
363 */
364 __u32 doorbell_handle;
365 /**
366 * @doorbell_offset: 32-bit offset of the doorbell in the doorbell bo.
367 * Kernel will generate absolute doorbell offset using doorbell_handle
368 * and doorbell_offset in the doorbell bo.
369 */
370 __u32 doorbell_offset;
371 /**
372 * @flags: flags used for queue parameters
373 */
374 __u32 flags;
375 /**
376 * @queue_va: Virtual address of the GPU memory which holds the queue
377 * object. The queue holds the workload packets.
378 */
379 __u64 queue_va;
380 /**
381 * @queue_size: Size of the queue in bytes, this needs to be 256-byte
382 * aligned.
383 */
384 __u64 queue_size;
385 /**
386 * @rptr_va : Virtual address of the GPU memory which holds the ring RPTR.
387 * This object must be at least 8 byte in size and aligned to 8-byte offset.
388 */
389 __u64 rptr_va;
390 /**
391 * @wptr_va : Virtual address of the GPU memory which holds the ring WPTR.
392 * This object must be at least 8 byte in size and aligned to 8-byte offset.
393 *
394 * Queue, RPTR and WPTR can come from the same object, as long as the size
395 * and alignment related requirements are met.
396 */
397 __u64 wptr_va;
398 /**
399 * @mqd: MQD (memory queue descriptor) is a set of parameters which allow
400 * the GPU to uniquely define and identify a usermode queue.
401 *
402 * MQD data can be of different size for different GPU IP/engine and
403 * their respective versions/revisions, so this points to a __u64 *
404 * which holds IP specific MQD of this usermode queue.
405 */
406 __u64 mqd;
407 /**
408 * @size: size of MQD data in bytes, it must match the MQD structure
409 * size of the respective engine/revision defined in UAPI for ex, for
410 * gfx11 workloads, size = sizeof(drm_amdgpu_userq_mqd_gfx11).
411 */
412 __u64 mqd_size;
413};
414
415/* The structure to carry output of userqueue ops */
416struct drm_amdgpu_userq_out {
417 /**
418 * For operation AMDGPU_USERQ_OP_CREATE: This field contains a unique
419 * queue ID to represent the newly created userqueue in the system, otherwise
420 * it should be ignored.
421 */
422 __u32 queue_id;
423 __u32 _pad;
424};
425
426union drm_amdgpu_userq {
427 struct drm_amdgpu_userq_in in;
428 struct drm_amdgpu_userq_out out;
429};
430
431/* GFX V11 IP specific MQD parameters */
432struct drm_amdgpu_userq_mqd_gfx11 {
433 /**
434 * @shadow_va: Virtual address of the GPU memory to hold the shadow buffer.
435 * Use AMDGPU_INFO_IOCTL to find the exact size of the object.
436 */
437 __u64 shadow_va;
438 /**
439 * @csa_va: Virtual address of the GPU memory to hold the CSA buffer.
440 * Use AMDGPU_INFO_IOCTL to find the exact size of the object.
441 */
442 __u64 csa_va;
443};
444
445/* GFX V11 SDMA IP specific MQD parameters */
446struct drm_amdgpu_userq_mqd_sdma_gfx11 {
447 /**
448 * @csa_va: Virtual address of the GPU memory to hold the CSA buffer.
449 * This must be a from a separate GPU object, and use AMDGPU_INFO IOCTL
450 * to get the size.
451 */
452 __u64 csa_va;
453};
454
455/* GFX V11 Compute IP specific MQD parameters */
456struct drm_amdgpu_userq_mqd_compute_gfx11 {
457 /**
458 * @eop_va: Virtual address of the GPU memory to hold the EOP buffer.
459 * This must be a from a separate GPU object, and use AMDGPU_INFO IOCTL
460 * to get the size.
461 */
462 __u64 eop_va;
463};
464
465/* userq signal/wait ioctl */
466struct drm_amdgpu_userq_signal {
467 /**
468 * @queue_id: Queue handle used by the userq fence creation function
469 * to retrieve the WPTR.
470 */
471 __u32 queue_id;
472 __u32 pad;
473 /**
474 * @syncobj_handles: The list of syncobj handles submitted by the user queue
475 * job to be signaled.
476 */
477 __u64 syncobj_handles;
478 /**
479 * @num_syncobj_handles: A count that represents the number of syncobj handles in
480 * @syncobj_handles.
481 */
482 __u16 num_syncobj_handles;
483 __u16 pad0;
484 __u32 pad1;
485 /**
486 * @bo_read_handles: The list of BO handles that the submitted user queue job
487 * is using for read only. This will update BO fences in the kernel.
488 */
489 __u64 bo_read_handles;
490 /**
491 * @bo_write_handles: The list of BO handles that the submitted user queue job
492 * is using for write only. This will update BO fences in the kernel.
493 */
494 __u64 bo_write_handles;
495 /**
496 * @num_bo_read_handles: A count that represents the number of read BO handles in
497 * @bo_read_handles.
498 */
499 __u32 num_bo_read_handles;
500 /**
501 * @num_bo_write_handles: A count that represents the number of write BO handles in
502 * @bo_write_handles.
503 */
504 __u32 num_bo_write_handles;
505};
506
507struct drm_amdgpu_userq_fence_info {
508 /**
509 * @va: A gpu address allocated for each queue which stores the
510 * read pointer (RPTR) value.
511 */
512 __u64 va;
513 /**
514 * @value: A 64 bit value represents the write pointer (WPTR) of the
515 * queue commands which compared with the RPTR value to signal the
516 * fences.
517 */
518 __u64 value;
519};
520
521struct drm_amdgpu_userq_wait {
522 /**
523 * @waitq_id: Queue handle used by the userq wait IOCTL to retrieve the
524 * wait queue and maintain the fence driver references in it.
525 */
526 __u32 waitq_id;
527 __u32 pad;
528 /**
529 * @syncobj_handles: The list of syncobj handles submitted by the user queue
530 * job to get the va/value pairs.
531 */
532 __u64 syncobj_handles;
533 /**
534 * @syncobj_timeline_handles: The list of timeline syncobj handles submitted by
535 * the user queue job to get the va/value pairs at given @syncobj_timeline_points.
536 */
537 __u64 syncobj_timeline_handles;
538 /**
539 * @syncobj_timeline_points: The list of timeline syncobj points submitted by the
540 * user queue job for the corresponding @syncobj_timeline_handles.
541 */
542 __u64 syncobj_timeline_points;
543 /**
544 * @bo_read_handles: The list of read BO handles submitted by the user queue
545 * job to get the va/value pairs.
546 */
547 __u64 bo_read_handles;
548 /**
549 * @bo_write_handles: The list of write BO handles submitted by the user queue
550 * job to get the va/value pairs.
551 */
552 __u64 bo_write_handles;
553 /**
554 * @num_syncobj_timeline_handles: A count that represents the number of timeline
555 * syncobj handles in @syncobj_timeline_handles.
556 */
557 __u16 num_syncobj_timeline_handles;
558 /**
559 * @num_fences: This field can be used both as input and output. As input it defines
560 * the maximum number of fences that can be returned and as output it will specify
561 * how many fences were actually returned from the ioctl.
562 */
563 __u16 num_fences;
564 /**
565 * @num_syncobj_handles: A count that represents the number of syncobj handles in
566 * @syncobj_handles.
567 */
568 __u16 num_syncobj_handles;
569 __u16 pad0;
570 /**
571 * @num_bo_read_handles: A count that represents the number of read BO handles in
572 * @bo_read_handles.
573 */
574 __u32 num_bo_read_handles;
575 /**
576 * @num_bo_write_handles: A count that represents the number of write BO handles in
577 * @bo_write_handles.
578 */
579 __u32 num_bo_write_handles;
580 /**
581 * @out_fences: The field is a return value from the ioctl containing the list of
582 * address/value pairs to wait for.
583 */
584 __u64 out_fences;
585};
586
587/* vm ioctl */
588#define AMDGPU_VM_OP_RESERVE_VMID 1
589#define AMDGPU_VM_OP_UNRESERVE_VMID 2
590
591struct drm_amdgpu_vm_in {
592 /** AMDGPU_VM_OP_* */
593 __u32 op;
594 __u32 flags;
595};
596
597struct drm_amdgpu_vm_out {
598 /** For future use, no flags defined so far */
599 __u64 flags;
600};
601
602union drm_amdgpu_vm {
603 struct drm_amdgpu_vm_in in;
604 struct drm_amdgpu_vm_out out;
605};
606
607/* sched ioctl */
608#define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1
609#define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2
610
611struct drm_amdgpu_sched_in {
612 /* AMDGPU_SCHED_OP_* */
613 __u32 op;
614 __u32 fd;
615 /** AMDGPU_CTX_PRIORITY_* */
616 __s32 priority;
617 __u32 ctx_id;
618};
619
620union drm_amdgpu_sched {
621 struct drm_amdgpu_sched_in in;
622};
623
624/*
625 * This is not a reliable API and you should expect it to fail for any
626 * number of reasons and have fallback path that do not use userptr to
627 * perform any operation.
628 */
629#define AMDGPU_GEM_USERPTR_READONLY (1 << 0)
630#define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1)
631#define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2)
632#define AMDGPU_GEM_USERPTR_REGISTER (1 << 3)
633
634struct drm_amdgpu_gem_userptr {
635 __u64 addr;
636 __u64 size;
637 /* AMDGPU_GEM_USERPTR_* */
638 __u32 flags;
639 /* Resulting GEM handle */
640 __u32 handle;
641};
642
643/* SI-CI-VI: */
644/* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */
645#define AMDGPU_TILING_ARRAY_MODE_SHIFT 0
646#define AMDGPU_TILING_ARRAY_MODE_MASK 0xf
647#define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4
648#define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f
649#define AMDGPU_TILING_TILE_SPLIT_SHIFT 9
650#define AMDGPU_TILING_TILE_SPLIT_MASK 0x7
651#define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12
652#define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7
653#define AMDGPU_TILING_BANK_WIDTH_SHIFT 15
654#define AMDGPU_TILING_BANK_WIDTH_MASK 0x3
655#define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17
656#define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3
657#define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19
658#define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3
659#define AMDGPU_TILING_NUM_BANKS_SHIFT 21
660#define AMDGPU_TILING_NUM_BANKS_MASK 0x3
661
662/* GFX9 - GFX11: */
663#define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0
664#define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f
665#define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5
666#define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF
667#define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29
668#define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF
669#define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43
670#define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1
671#define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44
672#define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1
673#define AMDGPU_TILING_SCANOUT_SHIFT 63
674#define AMDGPU_TILING_SCANOUT_MASK 0x1
675
676/* GFX12 and later: */
677#define AMDGPU_TILING_GFX12_SWIZZLE_MODE_SHIFT 0
678#define AMDGPU_TILING_GFX12_SWIZZLE_MODE_MASK 0x7
679/* These are DCC recompression settings for memory management: */
680#define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_SHIFT 3
681#define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 /* 0:64B, 1:128B, 2:256B */
682#define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_SHIFT 5
683#define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_MASK 0x7 /* CB_COLOR0_INFO.NUMBER_TYPE */
684#define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_SHIFT 8
685#define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_MASK 0x3f /* [0:4]:CB_COLOR0_INFO.FORMAT, [5]:MM */
686/* When clearing the buffer or moving it from VRAM to GTT, don't compress and set DCC metadata
687 * to uncompressed. Set when parts of an allocation bypass DCC and read raw data. */
688#define AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE_SHIFT 14
689#define AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE_MASK 0x1
690/* bit gap */
691#define AMDGPU_TILING_GFX12_SCANOUT_SHIFT 63
692#define AMDGPU_TILING_GFX12_SCANOUT_MASK 0x1
693
694/* Set/Get helpers for tiling flags. */
695#define AMDGPU_TILING_SET(field, value) \
696 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
697#define AMDGPU_TILING_GET(value, field) \
698 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
699
700#define AMDGPU_GEM_METADATA_OP_SET_METADATA 1
701#define AMDGPU_GEM_METADATA_OP_GET_METADATA 2
702
703/** The same structure is shared for input/output */
704struct drm_amdgpu_gem_metadata {
705 /** GEM Object handle */
706 __u32 handle;
707 /** Do we want get or set metadata */
708 __u32 op;
709 struct {
710 /** For future use, no flags defined so far */
711 __u64 flags;
712 /** family specific tiling info */
713 __u64 tiling_info;
714 __u32 data_size_bytes;
715 __u32 data[64];
716 } data;
717};
718
719struct drm_amdgpu_gem_mmap_in {
720 /** the GEM object handle */
721 __u32 handle;
722 __u32 _pad;
723};
724
725struct drm_amdgpu_gem_mmap_out {
726 /** mmap offset from the vma offset manager */
727 __u64 addr_ptr;
728};
729
730union drm_amdgpu_gem_mmap {
731 struct drm_amdgpu_gem_mmap_in in;
732 struct drm_amdgpu_gem_mmap_out out;
733};
734
735struct drm_amdgpu_gem_wait_idle_in {
736 /** GEM object handle */
737 __u32 handle;
738 /** For future use, no flags defined so far */
739 __u32 flags;
740 /** Absolute timeout to wait */
741 __u64 timeout;
742};
743
744struct drm_amdgpu_gem_wait_idle_out {
745 /** BO status: 0 - BO is idle, 1 - BO is busy */
746 __u32 status;
747 /** Returned current memory domain */
748 __u32 domain;
749};
750
751union drm_amdgpu_gem_wait_idle {
752 struct drm_amdgpu_gem_wait_idle_in in;
753 struct drm_amdgpu_gem_wait_idle_out out;
754};
755
756struct drm_amdgpu_wait_cs_in {
757 /* Command submission handle
758 * handle equals 0 means none to wait for
759 * handle equals ~0ull means wait for the latest sequence number
760 */
761 __u64 handle;
762 /** Absolute timeout to wait */
763 __u64 timeout;
764 __u32 ip_type;
765 __u32 ip_instance;
766 __u32 ring;
767 __u32 ctx_id;
768};
769
770struct drm_amdgpu_wait_cs_out {
771 /** CS status: 0 - CS completed, 1 - CS still busy */
772 __u64 status;
773};
774
775union drm_amdgpu_wait_cs {
776 struct drm_amdgpu_wait_cs_in in;
777 struct drm_amdgpu_wait_cs_out out;
778};
779
780struct drm_amdgpu_fence {
781 __u32 ctx_id;
782 __u32 ip_type;
783 __u32 ip_instance;
784 __u32 ring;
785 __u64 seq_no;
786};
787
788struct drm_amdgpu_wait_fences_in {
789 /** This points to uint64_t * which points to fences */
790 __u64 fences;
791 __u32 fence_count;
792 __u32 wait_all;
793 __u64 timeout_ns;
794};
795
796struct drm_amdgpu_wait_fences_out {
797 __u32 status;
798 __u32 first_signaled;
799};
800
801union drm_amdgpu_wait_fences {
802 struct drm_amdgpu_wait_fences_in in;
803 struct drm_amdgpu_wait_fences_out out;
804};
805
806#define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0
807#define AMDGPU_GEM_OP_SET_PLACEMENT 1
808#define AMDGPU_GEM_OP_GET_MAPPING_INFO 2
809
810struct drm_amdgpu_gem_vm_entry {
811 /* Start of mapping (in bytes) */
812 __u64 addr;
813
814 /* Size of mapping (in bytes) */
815 __u64 size;
816
817 /* Mapping offset */
818 __u64 offset;
819
820 /* flags needed to recreate mapping */
821 __u64 flags;
822};
823
824/* Sets or returns a value associated with a buffer. */
825struct drm_amdgpu_gem_op {
826 /** GEM object handle */
827 __u32 handle;
828 /** AMDGPU_GEM_OP_* */
829 __u32 op;
830 /** Input or return value. For MAPPING_INFO op: pointer to array of struct drm_amdgpu_gem_vm_entry */
831 __u64 value;
832 /** For MAPPING_INFO op: number of mappings (in/out) */
833 __u32 num_entries;
834
835 __u32 padding;
836};
837
838#define AMDGPU_GEM_LIST_HANDLES_FLAG_IS_IMPORT (1 << 0)
839
840struct drm_amdgpu_gem_list_handles {
841 /* User pointer to array of drm_amdgpu_gem_bo_info_entry */
842 __u64 entries;
843
844 /* Size of entries buffer / Number of handles in process (if larger than size of buffer, must retry) */
845 __u32 num_entries;
846
847 __u32 padding;
848};
849
850struct drm_amdgpu_gem_list_handles_entry {
851 /* gem handle of buffer object */
852 __u32 gem_handle;
853
854 /* Currently just one flag: IS_IMPORT */
855 __u32 flags;
856
857 /* Size of bo */
858 __u64 size;
859
860 /* Preferred domains for GEM_CREATE */
861 __u64 preferred_domains;
862
863 /* GEM_CREATE flags for re-creation of buffer */
864 __u64 alloc_flags;
865
866 /* physical start_addr alignment in bytes for some HW requirements */
867 __u64 alignment;
868};
869
870#define AMDGPU_VA_OP_MAP 1
871#define AMDGPU_VA_OP_UNMAP 2
872#define AMDGPU_VA_OP_CLEAR 3
873#define AMDGPU_VA_OP_REPLACE 4
874
875/* Delay the page table update till the next CS */
876#define AMDGPU_VM_DELAY_UPDATE (1 << 0)
877
878/* Mapping flags */
879/* readable mapping */
880#define AMDGPU_VM_PAGE_READABLE (1 << 1)
881/* writable mapping */
882#define AMDGPU_VM_PAGE_WRITEABLE (1 << 2)
883/* executable mapping, new for VI */
884#define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3)
885/* unmapped page of partially resident textures */
886#define AMDGPU_VM_PAGE_PRT (1 << 4)
887/* MTYPE flags use bit 5 to 8 */
888#define AMDGPU_VM_MTYPE_MASK (0xf << 5)
889/* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */
890#define AMDGPU_VM_MTYPE_DEFAULT (0 << 5)
891/* Use Non Coherent MTYPE instead of default MTYPE */
892#define AMDGPU_VM_MTYPE_NC (1 << 5)
893/* Use Write Combine MTYPE instead of default MTYPE */
894#define AMDGPU_VM_MTYPE_WC (2 << 5)
895/* Use Cache Coherent MTYPE instead of default MTYPE */
896#define AMDGPU_VM_MTYPE_CC (3 << 5)
897/* Use UnCached MTYPE instead of default MTYPE */
898#define AMDGPU_VM_MTYPE_UC (4 << 5)
899/* Use Read Write MTYPE instead of default MTYPE */
900#define AMDGPU_VM_MTYPE_RW (5 << 5)
901/* don't allocate MALL */
902#define AMDGPU_VM_PAGE_NOALLOC (1 << 9)
903
904struct drm_amdgpu_gem_va {
905 /** GEM object handle */
906 __u32 handle;
907 __u32 _pad;
908 /** AMDGPU_VA_OP_* */
909 __u32 operation;
910 /** AMDGPU_VM_PAGE_* */
911 __u32 flags;
912 /** va address to assign . Must be correctly aligned.*/
913 __u64 va_address;
914 /** Specify offset inside of BO to assign. Must be correctly aligned.*/
915 __u64 offset_in_bo;
916 /** Specify mapping size. Must be correctly aligned. */
917 __u64 map_size;
918 /**
919 * vm_timeline_point is a sequence number used to add new timeline point.
920 */
921 __u64 vm_timeline_point;
922 /**
923 * The vm page table update fence is installed in given vm_timeline_syncobj_out
924 * at vm_timeline_point.
925 */
926 __u32 vm_timeline_syncobj_out;
927 /** the number of syncobj handles in @input_fence_syncobj_handles */
928 __u32 num_syncobj_handles;
929 /** Array of sync object handle to wait for given input fences */
930 __u64 input_fence_syncobj_handles;
931};
932
933#define AMDGPU_HW_IP_GFX 0
934#define AMDGPU_HW_IP_COMPUTE 1
935#define AMDGPU_HW_IP_DMA 2
936#define AMDGPU_HW_IP_UVD 3
937#define AMDGPU_HW_IP_VCE 4
938#define AMDGPU_HW_IP_UVD_ENC 5
939#define AMDGPU_HW_IP_VCN_DEC 6
940/*
941 * From VCN4, AMDGPU_HW_IP_VCN_ENC is re-used to support
942 * both encoding and decoding jobs.
943 */
944#define AMDGPU_HW_IP_VCN_ENC 7
945#define AMDGPU_HW_IP_VCN_JPEG 8
946#define AMDGPU_HW_IP_VPE 9
947#define AMDGPU_HW_IP_NUM 10
948
949#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
950
951#define AMDGPU_CHUNK_ID_IB 0x01
952#define AMDGPU_CHUNK_ID_FENCE 0x02
953#define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03
954#define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04
955#define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05
956#define AMDGPU_CHUNK_ID_BO_HANDLES 0x06
957#define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07
958#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08
959#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09
960#define AMDGPU_CHUNK_ID_CP_GFX_SHADOW 0x0a
961
962struct drm_amdgpu_cs_chunk {
963 __u32 chunk_id;
964 __u32 length_dw;
965 __u64 chunk_data;
966};
967
968struct drm_amdgpu_cs_in {
969 /** Rendering context id */
970 __u32 ctx_id;
971 /** Handle of resource list associated with CS */
972 __u32 bo_list_handle;
973 __u32 num_chunks;
974 __u32 flags;
975 /** this points to __u64 * which point to cs chunks */
976 __u64 chunks;
977};
978
979struct drm_amdgpu_cs_out {
980 __u64 handle;
981};
982
983union drm_amdgpu_cs {
984 struct drm_amdgpu_cs_in in;
985 struct drm_amdgpu_cs_out out;
986};
987
988/* Specify flags to be used for IB */
989
990/* This IB should be submitted to CE */
991#define AMDGPU_IB_FLAG_CE (1<<0)
992
993/* Preamble flag, which means the IB could be dropped if no context switch */
994#define AMDGPU_IB_FLAG_PREAMBLE (1<<1)
995
996/* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */
997#define AMDGPU_IB_FLAG_PREEMPT (1<<2)
998
999/* The IB fence should do the L2 writeback but not invalidate any shader
1000 * caches (L2/vL1/sL1/I$). */
1001#define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3)
1002
1003/* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER.
1004 * This will reset wave ID counters for the IB.
1005 */
1006#define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4)
1007
1008/* Flag the IB as secure (TMZ)
1009 */
1010#define AMDGPU_IB_FLAGS_SECURE (1 << 5)
1011
1012/* Tell KMD to flush and invalidate caches
1013 */
1014#define AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6)
1015
1016struct drm_amdgpu_cs_chunk_ib {
1017 __u32 _pad;
1018 /** AMDGPU_IB_FLAG_* */
1019 __u32 flags;
1020 /** Virtual address to begin IB execution */
1021 __u64 va_start;
1022 /** Size of submission */
1023 __u32 ib_bytes;
1024 /** HW IP to submit to */
1025 __u32 ip_type;
1026 /** HW IP index of the same type to submit to */
1027 __u32 ip_instance;
1028 /** Ring index to submit to */
1029 __u32 ring;
1030};
1031
1032struct drm_amdgpu_cs_chunk_dep {
1033 __u32 ip_type;
1034 __u32 ip_instance;
1035 __u32 ring;
1036 __u32 ctx_id;
1037 __u64 handle;
1038};
1039
1040struct drm_amdgpu_cs_chunk_fence {
1041 __u32 handle;
1042 __u32 offset;
1043};
1044
1045struct drm_amdgpu_cs_chunk_sem {
1046 __u32 handle;
1047};
1048
1049struct drm_amdgpu_cs_chunk_syncobj {
1050 __u32 handle;
1051 __u32 flags;
1052 __u64 point;
1053};
1054
1055#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0
1056#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1
1057#define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2
1058
1059union drm_amdgpu_fence_to_handle {
1060 struct {
1061 struct drm_amdgpu_fence fence;
1062 __u32 what;
1063 __u32 pad;
1064 } in;
1065 struct {
1066 __u32 handle;
1067 } out;
1068};
1069
1070struct drm_amdgpu_cs_chunk_data {
1071 union {
1072 struct drm_amdgpu_cs_chunk_ib ib_data;
1073 struct drm_amdgpu_cs_chunk_fence fence_data;
1074 };
1075};
1076
1077#define AMDGPU_CS_CHUNK_CP_GFX_SHADOW_FLAGS_INIT_SHADOW 0x1
1078
1079struct drm_amdgpu_cs_chunk_cp_gfx_shadow {
1080 __u64 shadow_va;
1081 __u64 csa_va;
1082 __u64 gds_va;
1083 __u64 flags;
1084};
1085
1086/*
1087 * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU
1088 *
1089 */
1090#define AMDGPU_IDS_FLAGS_FUSION 0x01
1091#define AMDGPU_IDS_FLAGS_PREEMPTION 0x02
1092#define AMDGPU_IDS_FLAGS_TMZ 0x04
1093#define AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD 0x08
1094#define AMDGPU_IDS_FLAGS_GANG_SUBMIT 0x10
1095
1096/*
1097 * Query h/w info: Flag identifying VF/PF/PT mode
1098 *
1099 */
1100#define AMDGPU_IDS_FLAGS_MODE_MASK 0x300
1101#define AMDGPU_IDS_FLAGS_MODE_SHIFT 0x8
1102#define AMDGPU_IDS_FLAGS_MODE_PF 0x0
1103#define AMDGPU_IDS_FLAGS_MODE_VF 0x1
1104#define AMDGPU_IDS_FLAGS_MODE_PT 0x2
1105
1106/* indicate if acceleration can be working */
1107#define AMDGPU_INFO_ACCEL_WORKING 0x00
1108/* get the crtc_id from the mode object id? */
1109#define AMDGPU_INFO_CRTC_FROM_ID 0x01
1110/* query hw IP info */
1111#define AMDGPU_INFO_HW_IP_INFO 0x02
1112/* query hw IP instance count for the specified type */
1113#define AMDGPU_INFO_HW_IP_COUNT 0x03
1114/* timestamp for GL_ARB_timer_query */
1115#define AMDGPU_INFO_TIMESTAMP 0x05
1116/* Query the firmware version */
1117#define AMDGPU_INFO_FW_VERSION 0x0e
1118 /* Subquery id: Query VCE firmware version */
1119 #define AMDGPU_INFO_FW_VCE 0x1
1120 /* Subquery id: Query UVD firmware version */
1121 #define AMDGPU_INFO_FW_UVD 0x2
1122 /* Subquery id: Query GMC firmware version */
1123 #define AMDGPU_INFO_FW_GMC 0x03
1124 /* Subquery id: Query GFX ME firmware version */
1125 #define AMDGPU_INFO_FW_GFX_ME 0x04
1126 /* Subquery id: Query GFX PFP firmware version */
1127 #define AMDGPU_INFO_FW_GFX_PFP 0x05
1128 /* Subquery id: Query GFX CE firmware version */
1129 #define AMDGPU_INFO_FW_GFX_CE 0x06
1130 /* Subquery id: Query GFX RLC firmware version */
1131 #define AMDGPU_INFO_FW_GFX_RLC 0x07
1132 /* Subquery id: Query GFX MEC firmware version */
1133 #define AMDGPU_INFO_FW_GFX_MEC 0x08
1134 /* Subquery id: Query SMC firmware version */
1135 #define AMDGPU_INFO_FW_SMC 0x0a
1136 /* Subquery id: Query SDMA firmware version */
1137 #define AMDGPU_INFO_FW_SDMA 0x0b
1138 /* Subquery id: Query PSP SOS firmware version */
1139 #define AMDGPU_INFO_FW_SOS 0x0c
1140 /* Subquery id: Query PSP ASD firmware version */
1141 #define AMDGPU_INFO_FW_ASD 0x0d
1142 /* Subquery id: Query VCN firmware version */
1143 #define AMDGPU_INFO_FW_VCN 0x0e
1144 /* Subquery id: Query GFX RLC SRLC firmware version */
1145 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f
1146 /* Subquery id: Query GFX RLC SRLG firmware version */
1147 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10
1148 /* Subquery id: Query GFX RLC SRLS firmware version */
1149 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11
1150 /* Subquery id: Query DMCU firmware version */
1151 #define AMDGPU_INFO_FW_DMCU 0x12
1152 #define AMDGPU_INFO_FW_TA 0x13
1153 /* Subquery id: Query DMCUB firmware version */
1154 #define AMDGPU_INFO_FW_DMCUB 0x14
1155 /* Subquery id: Query TOC firmware version */
1156 #define AMDGPU_INFO_FW_TOC 0x15
1157 /* Subquery id: Query CAP firmware version */
1158 #define AMDGPU_INFO_FW_CAP 0x16
1159 /* Subquery id: Query GFX RLCP firmware version */
1160 #define AMDGPU_INFO_FW_GFX_RLCP 0x17
1161 /* Subquery id: Query GFX RLCV firmware version */
1162 #define AMDGPU_INFO_FW_GFX_RLCV 0x18
1163 /* Subquery id: Query MES_KIQ firmware version */
1164 #define AMDGPU_INFO_FW_MES_KIQ 0x19
1165 /* Subquery id: Query MES firmware version */
1166 #define AMDGPU_INFO_FW_MES 0x1a
1167 /* Subquery id: Query IMU firmware version */
1168 #define AMDGPU_INFO_FW_IMU 0x1b
1169 /* Subquery id: Query VPE firmware version */
1170 #define AMDGPU_INFO_FW_VPE 0x1c
1171
1172/* number of bytes moved for TTM migration */
1173#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
1174/* the used VRAM size */
1175#define AMDGPU_INFO_VRAM_USAGE 0x10
1176/* the used GTT size */
1177#define AMDGPU_INFO_GTT_USAGE 0x11
1178/* Information about GDS, etc. resource configuration */
1179#define AMDGPU_INFO_GDS_CONFIG 0x13
1180/* Query information about VRAM and GTT domains */
1181#define AMDGPU_INFO_VRAM_GTT 0x14
1182/* Query information about register in MMR address space*/
1183#define AMDGPU_INFO_READ_MMR_REG 0x15
1184/* Query information about device: rev id, family, etc. */
1185#define AMDGPU_INFO_DEV_INFO 0x16
1186/* visible vram usage */
1187#define AMDGPU_INFO_VIS_VRAM_USAGE 0x17
1188/* number of TTM buffer evictions */
1189#define AMDGPU_INFO_NUM_EVICTIONS 0x18
1190/* Query memory about VRAM and GTT domains */
1191#define AMDGPU_INFO_MEMORY 0x19
1192/* Query vce clock table */
1193#define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A
1194/* Query vbios related information */
1195#define AMDGPU_INFO_VBIOS 0x1B
1196 /* Subquery id: Query vbios size */
1197 #define AMDGPU_INFO_VBIOS_SIZE 0x1
1198 /* Subquery id: Query vbios image */
1199 #define AMDGPU_INFO_VBIOS_IMAGE 0x2
1200 /* Subquery id: Query vbios info */
1201 #define AMDGPU_INFO_VBIOS_INFO 0x3
1202/* Query UVD handles */
1203#define AMDGPU_INFO_NUM_HANDLES 0x1C
1204/* Query sensor related information */
1205#define AMDGPU_INFO_SENSOR 0x1D
1206 /* Subquery id: Query GPU shader clock */
1207 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1
1208 /* Subquery id: Query GPU memory clock */
1209 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2
1210 /* Subquery id: Query GPU temperature */
1211 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3
1212 /* Subquery id: Query GPU load */
1213 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4
1214 /* Subquery id: Query average GPU power */
1215 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5
1216 /* Subquery id: Query northbridge voltage */
1217 #define AMDGPU_INFO_SENSOR_VDDNB 0x6
1218 /* Subquery id: Query graphics voltage */
1219 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7
1220 /* Subquery id: Query GPU stable pstate shader clock */
1221 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8
1222 /* Subquery id: Query GPU stable pstate memory clock */
1223 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9
1224 /* Subquery id: Query GPU peak pstate shader clock */
1225 #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK 0xa
1226 /* Subquery id: Query GPU peak pstate memory clock */
1227 #define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK 0xb
1228 /* Subquery id: Query input GPU power */
1229 #define AMDGPU_INFO_SENSOR_GPU_INPUT_POWER 0xc
1230/* Number of VRAM page faults on CPU access. */
1231#define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E
1232#define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F
1233/* query ras mask of enabled features*/
1234#define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20
1235/* RAS MASK: UMC (VRAM) */
1236#define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0)
1237/* RAS MASK: SDMA */
1238#define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1)
1239/* RAS MASK: GFX */
1240#define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2)
1241/* RAS MASK: MMHUB */
1242#define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3)
1243/* RAS MASK: ATHUB */
1244#define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4)
1245/* RAS MASK: PCIE */
1246#define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5)
1247/* RAS MASK: HDP */
1248#define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6)
1249/* RAS MASK: XGMI */
1250#define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7)
1251/* RAS MASK: DF */
1252#define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8)
1253/* RAS MASK: SMN */
1254#define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9)
1255/* RAS MASK: SEM */
1256#define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10)
1257/* RAS MASK: MP0 */
1258#define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11)
1259/* RAS MASK: MP1 */
1260#define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12)
1261/* RAS MASK: FUSE */
1262#define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13)
1263/* query video encode/decode caps */
1264#define AMDGPU_INFO_VIDEO_CAPS 0x21
1265 /* Subquery id: Decode */
1266 #define AMDGPU_INFO_VIDEO_CAPS_DECODE 0
1267 /* Subquery id: Encode */
1268 #define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1
1269/* Query the max number of IBs per gang per submission */
1270#define AMDGPU_INFO_MAX_IBS 0x22
1271/* query last page fault info */
1272#define AMDGPU_INFO_GPUVM_FAULT 0x23
1273/* query FW object size and alignment */
1274#define AMDGPU_INFO_UQ_FW_AREAS 0x24
1275
1276#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
1277#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
1278#define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8
1279#define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff
1280
1281struct drm_amdgpu_query_fw {
1282 /** AMDGPU_INFO_FW_* */
1283 __u32 fw_type;
1284 /**
1285 * Index of the IP if there are more IPs of
1286 * the same type.
1287 */
1288 __u32 ip_instance;
1289 /**
1290 * Index of the engine. Whether this is used depends
1291 * on the firmware type. (e.g. MEC, SDMA)
1292 */
1293 __u32 index;
1294 __u32 _pad;
1295};
1296
1297/* Input structure for the INFO ioctl */
1298struct drm_amdgpu_info {
1299 /* Where the return value will be stored */
1300 __u64 return_pointer;
1301 /* The size of the return value. Just like "size" in "snprintf",
1302 * it limits how many bytes the kernel can write. */
1303 __u32 return_size;
1304 /* The query request id. */
1305 __u32 query;
1306
1307 union {
1308 struct {
1309 __u32 id;
1310 __u32 _pad;
1311 } mode_crtc;
1312
1313 struct {
1314 /** AMDGPU_HW_IP_* */
1315 __u32 type;
1316 /**
1317 * Index of the IP if there are more IPs of the same
1318 * type. Ignored by AMDGPU_INFO_HW_IP_COUNT.
1319 */
1320 __u32 ip_instance;
1321 } query_hw_ip;
1322
1323 struct {
1324 __u32 dword_offset;
1325 /** number of registers to read */
1326 __u32 count;
1327 __u32 instance;
1328 /** For future use, no flags defined so far */
1329 __u32 flags;
1330 } read_mmr_reg;
1331
1332 struct drm_amdgpu_query_fw query_fw;
1333
1334 struct {
1335 __u32 type;
1336 __u32 offset;
1337 } vbios_info;
1338
1339 struct {
1340 __u32 type;
1341 } sensor_info;
1342
1343 struct {
1344 __u32 type;
1345 } video_cap;
1346 };
1347};
1348
1349struct drm_amdgpu_info_gds {
1350 /** GDS GFX partition size */
1351 __u32 gds_gfx_partition_size;
1352 /** GDS compute partition size */
1353 __u32 compute_partition_size;
1354 /** total GDS memory size */
1355 __u32 gds_total_size;
1356 /** GWS size per GFX partition */
1357 __u32 gws_per_gfx_partition;
1358 /** GSW size per compute partition */
1359 __u32 gws_per_compute_partition;
1360 /** OA size per GFX partition */
1361 __u32 oa_per_gfx_partition;
1362 /** OA size per compute partition */
1363 __u32 oa_per_compute_partition;
1364 __u32 _pad;
1365};
1366
1367struct drm_amdgpu_info_vram_gtt {
1368 __u64 vram_size;
1369 __u64 vram_cpu_accessible_size;
1370 __u64 gtt_size;
1371};
1372
1373struct drm_amdgpu_heap_info {
1374 /** max. physical memory */
1375 __u64 total_heap_size;
1376
1377 /** Theoretical max. available memory in the given heap */
1378 __u64 usable_heap_size;
1379
1380 /**
1381 * Number of bytes allocated in the heap. This includes all processes
1382 * and private allocations in the kernel. It changes when new buffers
1383 * are allocated, freed, and moved. It cannot be larger than
1384 * heap_size.
1385 */
1386 __u64 heap_usage;
1387
1388 /**
1389 * Theoretical possible max. size of buffer which
1390 * could be allocated in the given heap
1391 */
1392 __u64 max_allocation;
1393};
1394
1395struct drm_amdgpu_memory_info {
1396 struct drm_amdgpu_heap_info vram;
1397 struct drm_amdgpu_heap_info cpu_accessible_vram;
1398 struct drm_amdgpu_heap_info gtt;
1399};
1400
1401struct drm_amdgpu_info_firmware {
1402 __u32 ver;
1403 __u32 feature;
1404};
1405
1406struct drm_amdgpu_info_vbios {
1407 __u8 name[64];
1408 __u8 vbios_pn[64];
1409 __u32 version;
1410 __u32 pad;
1411 __u8 vbios_ver_str[32];
1412 __u8 date[32];
1413};
1414
1415#define AMDGPU_VRAM_TYPE_UNKNOWN 0
1416#define AMDGPU_VRAM_TYPE_GDDR1 1
1417#define AMDGPU_VRAM_TYPE_DDR2 2
1418#define AMDGPU_VRAM_TYPE_GDDR3 3
1419#define AMDGPU_VRAM_TYPE_GDDR4 4
1420#define AMDGPU_VRAM_TYPE_GDDR5 5
1421#define AMDGPU_VRAM_TYPE_HBM 6
1422#define AMDGPU_VRAM_TYPE_DDR3 7
1423#define AMDGPU_VRAM_TYPE_DDR4 8
1424#define AMDGPU_VRAM_TYPE_GDDR6 9
1425#define AMDGPU_VRAM_TYPE_DDR5 10
1426#define AMDGPU_VRAM_TYPE_LPDDR4 11
1427#define AMDGPU_VRAM_TYPE_LPDDR5 12
1428#define AMDGPU_VRAM_TYPE_HBM3E 13
1429#define AMDGPU_VRAM_TYPE_HBM4 14
1430
1431struct drm_amdgpu_info_device {
1432 /** PCI Device ID */
1433 __u32 device_id;
1434 /** Internal chip revision: A0, A1, etc.) */
1435 __u32 chip_rev;
1436 __u32 external_rev;
1437 /** Revision id in PCI Config space */
1438 __u32 pci_rev;
1439 __u32 family;
1440 __u32 num_shader_engines;
1441 __u32 num_shader_arrays_per_engine;
1442 /* in KHz */
1443 __u32 gpu_counter_freq;
1444 __u64 max_engine_clock;
1445 __u64 max_memory_clock;
1446 /* cu information */
1447 __u32 cu_active_number;
1448 /* NOTE: cu_ao_mask is INVALID, DON'T use it */
1449 __u32 cu_ao_mask;
1450 __u32 cu_bitmap[4][4];
1451 /** Render backend pipe mask. One render backend is CB+DB. */
1452 __u32 enabled_rb_pipes_mask;
1453 __u32 num_rb_pipes;
1454 __u32 num_hw_gfx_contexts;
1455 /* PCIe version (the smaller of the GPU and the CPU/motherboard) */
1456 __u32 pcie_gen;
1457 __u64 ids_flags;
1458 /** Starting virtual address for UMDs. */
1459 __u64 virtual_address_offset;
1460 /** The maximum virtual address */
1461 __u64 virtual_address_max;
1462 /** Required alignment of virtual addresses. */
1463 __u32 virtual_address_alignment;
1464 /** Page table entry - fragment size */
1465 __u32 pte_fragment_size;
1466 __u32 gart_page_size;
1467 /** constant engine ram size*/
1468 __u32 ce_ram_size;
1469 /** video memory type info*/
1470 __u32 vram_type;
1471 /** video memory bit width*/
1472 __u32 vram_bit_width;
1473 /* vce harvesting instance */
1474 __u32 vce_harvest_config;
1475 /* gfx double offchip LDS buffers */
1476 __u32 gc_double_offchip_lds_buf;
1477 /* NGG Primitive Buffer */
1478 __u64 prim_buf_gpu_addr;
1479 /* NGG Position Buffer */
1480 __u64 pos_buf_gpu_addr;
1481 /* NGG Control Sideband */
1482 __u64 cntl_sb_buf_gpu_addr;
1483 /* NGG Parameter Cache */
1484 __u64 param_buf_gpu_addr;
1485 __u32 prim_buf_size;
1486 __u32 pos_buf_size;
1487 __u32 cntl_sb_buf_size;
1488 __u32 param_buf_size;
1489 /* wavefront size*/
1490 __u32 wave_front_size;
1491 /* shader visible vgprs*/
1492 __u32 num_shader_visible_vgprs;
1493 /* CU per shader array*/
1494 __u32 num_cu_per_sh;
1495 /* number of tcc blocks*/
1496 __u32 num_tcc_blocks;
1497 /* gs vgt table depth*/
1498 __u32 gs_vgt_table_depth;
1499 /* gs primitive buffer depth*/
1500 __u32 gs_prim_buffer_depth;
1501 /* max gs wavefront per vgt*/
1502 __u32 max_gs_waves_per_vgt;
1503 /* PCIe number of lanes (the smaller of the GPU and the CPU/motherboard) */
1504 __u32 pcie_num_lanes;
1505 /* always on cu bitmap */
1506 __u32 cu_ao_bitmap[4][4];
1507 /** Starting high virtual address for UMDs. */
1508 __u64 high_va_offset;
1509 /** The maximum high virtual address */
1510 __u64 high_va_max;
1511 /* gfx10 pa_sc_tile_steering_override */
1512 __u32 pa_sc_tile_steering_override;
1513 /* disabled TCCs */
1514 __u64 tcc_disabled_mask;
1515 __u64 min_engine_clock;
1516 __u64 min_memory_clock;
1517 /* The following fields are only set on gfx11+, older chips set 0. */
1518 __u32 tcp_cache_size; /* AKA GL0, VMEM cache */
1519 __u32 num_sqc_per_wgp;
1520 __u32 sqc_data_cache_size; /* AKA SMEM cache */
1521 __u32 sqc_inst_cache_size;
1522 __u32 gl1c_cache_size;
1523 __u32 gl2c_cache_size;
1524 __u64 mall_size; /* AKA infinity cache */
1525 /* high 32 bits of the rb pipes mask */
1526 __u32 enabled_rb_pipes_mask_hi;
1527 /* shadow area size for gfx11 */
1528 __u32 shadow_size;
1529 /* shadow area base virtual alignment for gfx11 */
1530 __u32 shadow_alignment;
1531 /* context save area size for gfx11 */
1532 __u32 csa_size;
1533 /* context save area base virtual alignment for gfx11 */
1534 __u32 csa_alignment;
1535 /* Userq IP mask (1 << AMDGPU_HW_IP_*) */
1536 __u32 userq_ip_mask;
1537 __u32 pad;
1538};
1539
1540struct drm_amdgpu_info_hw_ip {
1541 /** Version of h/w IP */
1542 __u32 hw_ip_version_major;
1543 __u32 hw_ip_version_minor;
1544 /** Capabilities */
1545 __u64 capabilities_flags;
1546 /** command buffer address start alignment*/
1547 __u32 ib_start_alignment;
1548 /** command buffer size alignment*/
1549 __u32 ib_size_alignment;
1550 /** Bitmask of available rings. Bit 0 means ring 0, etc. */
1551 __u32 available_rings;
1552 /** version info: bits 23:16 major, 15:8 minor, 7:0 revision */
1553 __u32 ip_discovery_version;
1554 /* Userq available slots */
1555 __u32 userq_num_slots;
1556};
1557
1558struct drm_amdgpu_info_num_handles {
1559 /** Max handles as supported by firmware for UVD */
1560 __u32 uvd_max_handles;
1561 /** Handles currently in use for UVD */
1562 __u32 uvd_used_handles;
1563};
1564
1565#define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6
1566
1567struct drm_amdgpu_info_vce_clock_table_entry {
1568 /** System clock */
1569 __u32 sclk;
1570 /** Memory clock */
1571 __u32 mclk;
1572 /** VCE clock */
1573 __u32 eclk;
1574 __u32 pad;
1575};
1576
1577struct drm_amdgpu_info_vce_clock_table {
1578 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES];
1579 __u32 num_valid_entries;
1580 __u32 pad;
1581};
1582
1583/* query video encode/decode caps */
1584#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2 0
1585#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4 1
1586#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1 2
1587#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC 3
1588#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC 4
1589#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG 5
1590#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9 6
1591#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1 7
1592#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT 8
1593
1594struct drm_amdgpu_info_video_codec_info {
1595 __u32 valid;
1596 __u32 max_width;
1597 __u32 max_height;
1598 __u32 max_pixels_per_frame;
1599 __u32 max_level;
1600 __u32 pad;
1601};
1602
1603struct drm_amdgpu_info_video_caps {
1604 struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT];
1605};
1606
1607#define AMDGPU_VMHUB_TYPE_MASK 0xff
1608#define AMDGPU_VMHUB_TYPE_SHIFT 0
1609#define AMDGPU_VMHUB_TYPE_GFX 0
1610#define AMDGPU_VMHUB_TYPE_MM0 1
1611#define AMDGPU_VMHUB_TYPE_MM1 2
1612#define AMDGPU_VMHUB_IDX_MASK 0xff00
1613#define AMDGPU_VMHUB_IDX_SHIFT 8
1614
1615struct drm_amdgpu_info_gpuvm_fault {
1616 __u64 addr;
1617 __u32 status;
1618 __u32 vmhub;
1619};
1620
1621struct drm_amdgpu_info_uq_metadata_gfx {
1622 /* shadow area size for gfx11 */
1623 __u32 shadow_size;
1624 /* shadow area base virtual alignment for gfx11 */
1625 __u32 shadow_alignment;
1626 /* context save area size for gfx11 */
1627 __u32 csa_size;
1628 /* context save area base virtual alignment for gfx11 */
1629 __u32 csa_alignment;
1630};
1631
1632struct drm_amdgpu_info_uq_metadata_compute {
1633 /* EOP size for gfx11 */
1634 __u32 eop_size;
1635 /* EOP base virtual alignment for gfx11 */
1636 __u32 eop_alignment;
1637};
1638
1639struct drm_amdgpu_info_uq_metadata_sdma {
1640 /* context save area size for sdma6 */
1641 __u32 csa_size;
1642 /* context save area base virtual alignment for sdma6 */
1643 __u32 csa_alignment;
1644};
1645
1646struct drm_amdgpu_info_uq_metadata {
1647 union {
1648 struct drm_amdgpu_info_uq_metadata_gfx gfx;
1649 struct drm_amdgpu_info_uq_metadata_compute compute;
1650 struct drm_amdgpu_info_uq_metadata_sdma sdma;
1651 };
1652};
1653
1654/*
1655 * Supported GPU families
1656 */
1657#define AMDGPU_FAMILY_UNKNOWN 0
1658#define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */
1659#define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */
1660#define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */
1661#define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */
1662#define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */
1663#define AMDGPU_FAMILY_AI 141 /* Vega10 */
1664#define AMDGPU_FAMILY_RV 142 /* Raven */
1665#define AMDGPU_FAMILY_NV 143 /* Navi10 */
1666#define AMDGPU_FAMILY_VGH 144 /* Van Gogh */
1667#define AMDGPU_FAMILY_GC_11_0_0 145 /* GC 11.0.0 */
1668#define AMDGPU_FAMILY_YC 146 /* Yellow Carp */
1669#define AMDGPU_FAMILY_GC_11_0_1 148 /* GC 11.0.1 */
1670#define AMDGPU_FAMILY_GC_10_3_6 149 /* GC 10.3.6 */
1671#define AMDGPU_FAMILY_GC_10_3_7 151 /* GC 10.3.7 */
1672#define AMDGPU_FAMILY_GC_11_5_0 150 /* GC 11.5.0 */
1673#define AMDGPU_FAMILY_GC_11_5_4 154 /* GC 11.5.4 */
1674#define AMDGPU_FAMILY_GC_12_0_0 152 /* GC 12.0.0 */
1675
1676#if defined(__cplusplus)
1677}
1678#endif
1679
1680#endif