Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1/* SPDX-License-Identifier: GPL-2.0-only */
2
3#ifndef SELFTEST_KVM_PROCESSOR_H
4#define SELFTEST_KVM_PROCESSOR_H
5
6#ifndef __ASSEMBLER__
7#include "ucall_common.h"
8
9#else
10/* general registers */
11#define zero $r0
12#define ra $r1
13#define tp $r2
14#define sp $r3
15#define a0 $r4
16#define a1 $r5
17#define a2 $r6
18#define a3 $r7
19#define a4 $r8
20#define a5 $r9
21#define a6 $r10
22#define a7 $r11
23#define t0 $r12
24#define t1 $r13
25#define t2 $r14
26#define t3 $r15
27#define t4 $r16
28#define t5 $r17
29#define t6 $r18
30#define t7 $r19
31#define t8 $r20
32#define u0 $r21
33#define fp $r22
34#define s0 $r23
35#define s1 $r24
36#define s2 $r25
37#define s3 $r26
38#define s4 $r27
39#define s5 $r28
40#define s6 $r29
41#define s7 $r30
42#define s8 $r31
43#endif
44
45/*
46 * LoongArch page table entry definition
47 * Original header file arch/loongarch/include/asm/loongarch.h
48 */
49#define _PAGE_VALID_SHIFT 0
50#define _PAGE_DIRTY_SHIFT 1
51#define _PAGE_PLV_SHIFT 2 /* 2~3, two bits */
52#define PLV_KERN 0
53#define PLV_USER 3
54#define PLV_MASK 0x3
55#define _CACHE_SHIFT 4 /* 4~5, two bits */
56#define _PAGE_PRESENT_SHIFT 7
57#define _PAGE_WRITE_SHIFT 8
58
59#define _PAGE_VALID BIT_ULL(_PAGE_VALID_SHIFT)
60#define _PAGE_PRESENT BIT_ULL(_PAGE_PRESENT_SHIFT)
61#define _PAGE_WRITE BIT_ULL(_PAGE_WRITE_SHIFT)
62#define _PAGE_DIRTY BIT_ULL(_PAGE_DIRTY_SHIFT)
63#define _PAGE_USER (PLV_USER << _PAGE_PLV_SHIFT)
64#define __READABLE (_PAGE_VALID)
65#define __WRITEABLE (_PAGE_DIRTY | _PAGE_WRITE)
66/* Coherent Cached */
67#define _CACHE_CC BIT_ULL(_CACHE_SHIFT)
68#define PS_4K 0x0000000c
69#define PS_16K 0x0000000e
70#define PS_64K 0x00000010
71#define PS_DEFAULT_SIZE PS_16K
72
73/* LoongArch Basic CSR registers */
74#define LOONGARCH_CSR_CRMD 0x0 /* Current mode info */
75#define CSR_CRMD_PG_SHIFT 4
76#define CSR_CRMD_PG BIT_ULL(CSR_CRMD_PG_SHIFT)
77#define CSR_CRMD_IE_SHIFT 2
78#define CSR_CRMD_IE BIT_ULL(CSR_CRMD_IE_SHIFT)
79#define CSR_CRMD_PLV_SHIFT 0
80#define CSR_CRMD_PLV_WIDTH 2
81#define CSR_CRMD_PLV (0x3UL << CSR_CRMD_PLV_SHIFT)
82#define PLV_MASK 0x3
83#define LOONGARCH_CSR_PRMD 0x1
84#define LOONGARCH_CSR_EUEN 0x2
85#define LOONGARCH_CSR_ECFG 0x4
86#define ECFGB_PMU 10
87#define ECFGF_PMU (BIT_ULL(ECFGB_PMU))
88#define ECFGB_TIMER 11
89#define ECFGF_TIMER (BIT_ULL(ECFGB_TIMER))
90#define LOONGARCH_CSR_ESTAT 0x5 /* Exception status */
91#define CSR_ESTAT_EXC_SHIFT 16
92#define CSR_ESTAT_EXC_WIDTH 6
93#define CSR_ESTAT_EXC (0x3f << CSR_ESTAT_EXC_SHIFT)
94#define EXCCODE_INT 0 /* Interrupt */
95#define INT_PMI 10 /* PMU interrupt */
96#define INT_TI 11 /* Timer interrupt*/
97#define LOONGARCH_CSR_ERA 0x6 /* ERA */
98#define LOONGARCH_CSR_BADV 0x7 /* Bad virtual address */
99#define LOONGARCH_CSR_EENTRY 0xc
100#define LOONGARCH_CSR_TLBIDX 0x10 /* TLB Index, EHINV, PageSize */
101#define CSR_TLBIDX_PS_SHIFT 24
102#define CSR_TLBIDX_PS_WIDTH 6
103#define CSR_TLBIDX_PS (0x3fUL << CSR_TLBIDX_PS_SHIFT)
104#define CSR_TLBIDX_SIZEM 0x3f000000
105#define CSR_TLBIDX_SIZE CSR_TLBIDX_PS_SHIFT
106#define LOONGARCH_CSR_ASID 0x18 /* ASID */
107#define LOONGARCH_CSR_PGDL 0x19
108#define LOONGARCH_CSR_PGDH 0x1a
109/* Page table base */
110#define LOONGARCH_CSR_PGD 0x1b
111#define LOONGARCH_CSR_PWCTL0 0x1c
112#define LOONGARCH_CSR_PWCTL1 0x1d
113#define LOONGARCH_CSR_STLBPGSIZE 0x1e
114#define LOONGARCH_CSR_CPUID 0x20
115#define LOONGARCH_CSR_KS0 0x30
116#define LOONGARCH_CSR_KS1 0x31
117#define LOONGARCH_CSR_TMID 0x40
118#define LOONGARCH_CSR_TCFG 0x41
119#define CSR_TCFG_VAL (BIT_ULL(48) - BIT_ULL(2))
120#define CSR_TCFG_PERIOD_SHIFT 1
121#define CSR_TCFG_PERIOD (0x1UL << CSR_TCFG_PERIOD_SHIFT)
122#define CSR_TCFG_EN (0x1UL)
123#define LOONGARCH_CSR_TVAL 0x42
124#define LOONGARCH_CSR_TINTCLR 0x44 /* Timer interrupt clear */
125#define CSR_TINTCLR_TI_SHIFT 0
126#define CSR_TINTCLR_TI (1 << CSR_TINTCLR_TI_SHIFT)
127/* TLB refill exception entry */
128#define LOONGARCH_CSR_TLBRENTRY 0x88
129#define LOONGARCH_CSR_TLBRSAVE 0x8b
130#define LOONGARCH_CSR_TLBREHI 0x8e
131#define CSR_TLBREHI_PS_SHIFT 0
132#define CSR_TLBREHI_PS (0x3fUL << CSR_TLBREHI_PS_SHIFT)
133
134#define read_cpucfg(reg) \
135({ \
136 register unsigned long __v; \
137 __asm__ __volatile__( \
138 "cpucfg %0, %1\n\t" \
139 : "=r" (__v) \
140 : "r" (reg) \
141 : "memory"); \
142 __v; \
143})
144
145#define csr_read(csr) \
146({ \
147 register unsigned long __v; \
148 __asm__ __volatile__( \
149 "csrrd %[val], %[reg]\n\t" \
150 : [val] "=r" (__v) \
151 : [reg] "i" (csr) \
152 : "memory"); \
153 __v; \
154})
155
156#define csr_write(v, csr) \
157({ \
158 register unsigned long __v = v; \
159 __asm__ __volatile__ ( \
160 "csrwr %[val], %[reg]\n\t" \
161 : [val] "+r" (__v) \
162 : [reg] "i" (csr) \
163 : "memory"); \
164 __v; \
165})
166
167#define EXREGS_GPRS (32)
168
169#ifndef __ASSEMBLER__
170void handle_tlb_refill(void);
171void handle_exception(void);
172
173struct ex_regs {
174 unsigned long regs[EXREGS_GPRS];
175 unsigned long pc;
176 unsigned long estat;
177 unsigned long badv;
178 unsigned long prmd;
179};
180
181#define PC_OFFSET_EXREGS offsetof(struct ex_regs, pc)
182#define ESTAT_OFFSET_EXREGS offsetof(struct ex_regs, estat)
183#define BADV_OFFSET_EXREGS offsetof(struct ex_regs, badv)
184#define PRMD_OFFSET_EXREGS offsetof(struct ex_regs, prmd)
185#define EXREGS_SIZE sizeof(struct ex_regs)
186
187#define VECTOR_NUM 64
188
189typedef void(*handler_fn)(struct ex_regs *);
190
191struct handlers {
192 handler_fn exception_handlers[VECTOR_NUM];
193};
194
195void loongarch_vcpu_setup(struct kvm_vcpu *vcpu);
196void vm_init_descriptor_tables(struct kvm_vm *vm);
197void vm_install_exception_handler(struct kvm_vm *vm, int vector, handler_fn handler);
198
199static inline void cpu_relax(void)
200{
201 asm volatile("nop" ::: "memory");
202}
203
204static inline void local_irq_enable(void)
205{
206 unsigned int flags = CSR_CRMD_IE;
207 register unsigned int mask asm("$t0") = CSR_CRMD_IE;
208
209 __asm__ __volatile__(
210 "csrxchg %[val], %[mask], %[reg]\n\t"
211 : [val] "+r" (flags)
212 : [mask] "r" (mask), [reg] "i" (LOONGARCH_CSR_CRMD)
213 : "memory");
214}
215
216static inline void local_irq_disable(void)
217{
218 unsigned int flags = 0;
219 register unsigned int mask asm("$t0") = CSR_CRMD_IE;
220
221 __asm__ __volatile__(
222 "csrxchg %[val], %[mask], %[reg]\n\t"
223 : [val] "+r" (flags)
224 : [mask] "r" (mask), [reg] "i" (LOONGARCH_CSR_CRMD)
225 : "memory");
226}
227#else
228#define PC_OFFSET_EXREGS ((EXREGS_GPRS + 0) * 8)
229#define ESTAT_OFFSET_EXREGS ((EXREGS_GPRS + 1) * 8)
230#define BADV_OFFSET_EXREGS ((EXREGS_GPRS + 2) * 8)
231#define PRMD_OFFSET_EXREGS ((EXREGS_GPRS + 3) * 8)
232#define EXREGS_SIZE ((EXREGS_GPRS + 4) * 8)
233#endif
234
235#endif /* SELFTEST_KVM_PROCESSOR_H */