Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Check for KVM_GET_REG_LIST regressions.
4 *
5 * Copyright (c) 2023 Intel Corporation
6 *
7 */
8#include <stdio.h>
9#include "kvm_util.h"
10#include "test_util.h"
11#include "processor.h"
12
13#define REG_MASK (KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK)
14
15enum {
16 VCPU_FEATURE_ISA_EXT = 0,
17 VCPU_FEATURE_SBI_EXT,
18};
19
20enum {
21 KVM_RISC_V_REG_OFFSET_VSTART = 0,
22 KVM_RISC_V_REG_OFFSET_VL,
23 KVM_RISC_V_REG_OFFSET_VTYPE,
24 KVM_RISC_V_REG_OFFSET_VCSR,
25 KVM_RISC_V_REG_OFFSET_VLENB,
26 KVM_RISC_V_REG_OFFSET_MAX,
27};
28
29static bool isa_ext_cant_disable[KVM_RISCV_ISA_EXT_MAX];
30
31bool filter_reg(__u64 reg)
32{
33 switch (reg & ~REG_MASK) {
34 /*
35 * Same set of ISA_EXT registers are not present on all host because
36 * ISA_EXT registers are visible to the KVM user space based on the
37 * ISA extensions available on the host. Also, disabling an ISA
38 * extension using corresponding ISA_EXT register does not affect
39 * the visibility of the ISA_EXT register itself.
40 *
41 * Based on above, we should filter-out all ISA_EXT registers.
42 *
43 * Note: The below list is alphabetically sorted.
44 */
45 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_A:
46 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_C:
47 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_D:
48 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_F:
49 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_H:
50 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_I:
51 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_M:
52 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_V:
53 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SMNPM:
54 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SMSTATEEN:
55 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSAIA:
56 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSCOFPMF:
57 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSNPM:
58 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSTC:
59 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVADE:
60 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVADU:
61 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVINVAL:
62 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVNAPOT:
63 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVPBMT:
64 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVVPTC:
65 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZAAMO:
66 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZABHA:
67 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZACAS:
68 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZALASR:
69 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZALRSC:
70 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZAWRS:
71 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBA:
72 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBB:
73 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBC:
74 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBKB:
75 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBKC:
76 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBKX:
77 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBS:
78 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCA:
79 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCB:
80 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCD:
81 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCF:
82 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCLSD:
83 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZCMOP:
84 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFA:
85 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFBFMIN:
86 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFH:
87 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZFHMIN:
88 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOM:
89 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOP:
90 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOZ:
91 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICCRSE:
92 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICNTR:
93 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICOND:
94 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICSR:
95 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIFENCEI:
96 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIHINTNTL:
97 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIHINTPAUSE:
98 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIHPM:
99 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZILSD:
100 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIMOP:
101 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKND:
102 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKNE:
103 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKNH:
104 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKR:
105 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKSED:
106 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKSH:
107 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKT:
108 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZTSO:
109 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVBB:
110 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVBC:
111 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVFBFMIN:
112 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVFBFWMA:
113 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVFH:
114 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVFHMIN:
115 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKB:
116 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKG:
117 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKNED:
118 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKNHA:
119 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKNHB:
120 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKSED:
121 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKSH:
122 case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZVKT:
123 /*
124 * Like ISA_EXT registers, SBI_EXT registers are only visible when the
125 * host supports them and disabling them does not affect the visibility
126 * of the SBI_EXT register itself.
127 */
128 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_V01:
129 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_TIME:
130 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_IPI:
131 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_RFENCE:
132 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_SRST:
133 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_HSM:
134 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_PMU:
135 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_DBCN:
136 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_SUSP:
137 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_STA:
138 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_FWFT:
139 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_MPXY:
140 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_EXPERIMENTAL:
141 case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_VENDOR:
142 return true;
143 /* AIA registers are always available when Ssaia can't be disabled */
144 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siselect):
145 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio1):
146 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio2):
147 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(sieh):
148 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siph):
149 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio1h):
150 case KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio2h):
151 return isa_ext_cant_disable[KVM_RISCV_ISA_EXT_SSAIA];
152 default:
153 break;
154 }
155
156 return false;
157}
158
159bool check_reject_set(int err)
160{
161 return err == EINVAL;
162}
163
164static int override_vector_reg_size(struct kvm_vcpu *vcpu, struct vcpu_reg_sublist *s,
165 u64 feature)
166{
167 unsigned long vlenb_reg = 0;
168 int rc;
169 u64 reg, size;
170
171 /* Enable V extension so that we can get the vlenb register */
172 rc = __vcpu_set_reg(vcpu, feature, 1);
173 if (rc)
174 return rc;
175
176 vlenb_reg = vcpu_get_reg(vcpu, s->regs[KVM_RISC_V_REG_OFFSET_VLENB]);
177 if (!vlenb_reg) {
178 TEST_FAIL("Can't compute vector register size from zero vlenb\n");
179 return -EPERM;
180 }
181
182 size = __builtin_ctzl(vlenb_reg);
183 size <<= KVM_REG_SIZE_SHIFT;
184
185 for (int i = 0; i < 32; i++) {
186 reg = KVM_REG_RISCV | KVM_REG_RISCV_VECTOR | size | KVM_REG_RISCV_VECTOR_REG(i);
187 s->regs[KVM_RISC_V_REG_OFFSET_MAX + i] = reg;
188 }
189
190 /* We should assert if disabling failed here while enabling succeeded before */
191 vcpu_set_reg(vcpu, feature, 0);
192
193 return 0;
194}
195
196void finalize_vcpu(struct kvm_vcpu *vcpu, struct vcpu_reg_list *c)
197{
198 unsigned long isa_ext_state[KVM_RISCV_ISA_EXT_MAX] = { 0 };
199 struct vcpu_reg_sublist *s;
200 u64 feature;
201 int rc;
202
203 for (int i = 0; i < KVM_RISCV_ISA_EXT_MAX; i++)
204 __vcpu_get_reg(vcpu, RISCV_ISA_EXT_REG(i), &isa_ext_state[i]);
205
206 /*
207 * Disable all extensions which were enabled by default
208 * if they were available in the risc-v host.
209 */
210 for (int i = 0; i < KVM_RISCV_ISA_EXT_MAX; i++) {
211 rc = __vcpu_set_reg(vcpu, RISCV_ISA_EXT_REG(i), 0);
212 if (rc && isa_ext_state[i])
213 isa_ext_cant_disable[i] = true;
214 }
215
216 for (int i = 0; i < KVM_RISCV_SBI_EXT_MAX; i++) {
217 rc = __vcpu_set_reg(vcpu, RISCV_SBI_EXT_REG(i), 0);
218 TEST_ASSERT(!rc || (rc == -1 && errno == ENOENT), "Unexpected error");
219 }
220
221 for_each_sublist(c, s) {
222 if (!s->feature)
223 continue;
224
225 if (s->feature == KVM_RISCV_ISA_EXT_V) {
226 feature = RISCV_ISA_EXT_REG(s->feature);
227 rc = override_vector_reg_size(vcpu, s, feature);
228 if (rc)
229 goto skip;
230 }
231
232 switch (s->feature_type) {
233 case VCPU_FEATURE_ISA_EXT:
234 feature = RISCV_ISA_EXT_REG(s->feature);
235 break;
236 case VCPU_FEATURE_SBI_EXT:
237 feature = RISCV_SBI_EXT_REG(s->feature);
238 break;
239 default:
240 TEST_FAIL("Unknown feature type");
241 }
242
243 /* Try to enable the desired extension */
244 __vcpu_set_reg(vcpu, feature, 1);
245
246skip:
247 /* Double check whether the desired extension was enabled */
248 __TEST_REQUIRE(__vcpu_has_ext(vcpu, feature),
249 "%s not available, skipping tests", s->name);
250 }
251}
252
253static const char *config_id_to_str(const char *prefix, __u64 id)
254{
255 /* reg_off is the offset into struct kvm_riscv_config */
256 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CONFIG);
257
258 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CONFIG);
259
260 switch (reg_off) {
261 case KVM_REG_RISCV_CONFIG_REG(isa):
262 return "KVM_REG_RISCV_CONFIG_REG(isa)";
263 case KVM_REG_RISCV_CONFIG_REG(zicbom_block_size):
264 return "KVM_REG_RISCV_CONFIG_REG(zicbom_block_size)";
265 case KVM_REG_RISCV_CONFIG_REG(zicboz_block_size):
266 return "KVM_REG_RISCV_CONFIG_REG(zicboz_block_size)";
267 case KVM_REG_RISCV_CONFIG_REG(zicbop_block_size):
268 return "KVM_REG_RISCV_CONFIG_REG(zicbop_block_size)";
269 case KVM_REG_RISCV_CONFIG_REG(mvendorid):
270 return "KVM_REG_RISCV_CONFIG_REG(mvendorid)";
271 case KVM_REG_RISCV_CONFIG_REG(marchid):
272 return "KVM_REG_RISCV_CONFIG_REG(marchid)";
273 case KVM_REG_RISCV_CONFIG_REG(mimpid):
274 return "KVM_REG_RISCV_CONFIG_REG(mimpid)";
275 case KVM_REG_RISCV_CONFIG_REG(satp_mode):
276 return "KVM_REG_RISCV_CONFIG_REG(satp_mode)";
277 }
278
279 return strdup_printf("%lld /* UNKNOWN */", reg_off);
280}
281
282static const char *core_id_to_str(const char *prefix, __u64 id)
283{
284 /* reg_off is the offset into struct kvm_riscv_core */
285 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CORE);
286
287 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CORE);
288
289 switch (reg_off) {
290 case KVM_REG_RISCV_CORE_REG(regs.pc):
291 return "KVM_REG_RISCV_CORE_REG(regs.pc)";
292 case KVM_REG_RISCV_CORE_REG(regs.ra):
293 return "KVM_REG_RISCV_CORE_REG(regs.ra)";
294 case KVM_REG_RISCV_CORE_REG(regs.sp):
295 return "KVM_REG_RISCV_CORE_REG(regs.sp)";
296 case KVM_REG_RISCV_CORE_REG(regs.gp):
297 return "KVM_REG_RISCV_CORE_REG(regs.gp)";
298 case KVM_REG_RISCV_CORE_REG(regs.tp):
299 return "KVM_REG_RISCV_CORE_REG(regs.tp)";
300 case KVM_REG_RISCV_CORE_REG(regs.t0) ... KVM_REG_RISCV_CORE_REG(regs.t2):
301 return strdup_printf("KVM_REG_RISCV_CORE_REG(regs.t%lld)",
302 reg_off - KVM_REG_RISCV_CORE_REG(regs.t0));
303 case KVM_REG_RISCV_CORE_REG(regs.s0) ... KVM_REG_RISCV_CORE_REG(regs.s1):
304 return strdup_printf("KVM_REG_RISCV_CORE_REG(regs.s%lld)",
305 reg_off - KVM_REG_RISCV_CORE_REG(regs.s0));
306 case KVM_REG_RISCV_CORE_REG(regs.a0) ... KVM_REG_RISCV_CORE_REG(regs.a7):
307 return strdup_printf("KVM_REG_RISCV_CORE_REG(regs.a%lld)",
308 reg_off - KVM_REG_RISCV_CORE_REG(regs.a0));
309 case KVM_REG_RISCV_CORE_REG(regs.s2) ... KVM_REG_RISCV_CORE_REG(regs.s11):
310 return strdup_printf("KVM_REG_RISCV_CORE_REG(regs.s%lld)",
311 reg_off - KVM_REG_RISCV_CORE_REG(regs.s2) + 2);
312 case KVM_REG_RISCV_CORE_REG(regs.t3) ... KVM_REG_RISCV_CORE_REG(regs.t6):
313 return strdup_printf("KVM_REG_RISCV_CORE_REG(regs.t%lld)",
314 reg_off - KVM_REG_RISCV_CORE_REG(regs.t3) + 3);
315 case KVM_REG_RISCV_CORE_REG(mode):
316 return "KVM_REG_RISCV_CORE_REG(mode)";
317 }
318
319 return strdup_printf("%lld /* UNKNOWN */", reg_off);
320}
321
322#define RISCV_CSR_GENERAL(csr) \
323 "KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(" #csr ")"
324#define RISCV_CSR_AIA(csr) \
325 "KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_REG(" #csr ")"
326#define RISCV_CSR_SMSTATEEN(csr) \
327 "KVM_REG_RISCV_CSR_SMSTATEEN | KVM_REG_RISCV_CSR_REG(" #csr ")"
328
329static const char *general_csr_id_to_str(__u64 reg_off)
330{
331 /* reg_off is the offset into struct kvm_riscv_csr */
332 switch (reg_off) {
333 case KVM_REG_RISCV_CSR_REG(sstatus):
334 return RISCV_CSR_GENERAL(sstatus);
335 case KVM_REG_RISCV_CSR_REG(sie):
336 return RISCV_CSR_GENERAL(sie);
337 case KVM_REG_RISCV_CSR_REG(stvec):
338 return RISCV_CSR_GENERAL(stvec);
339 case KVM_REG_RISCV_CSR_REG(sscratch):
340 return RISCV_CSR_GENERAL(sscratch);
341 case KVM_REG_RISCV_CSR_REG(sepc):
342 return RISCV_CSR_GENERAL(sepc);
343 case KVM_REG_RISCV_CSR_REG(scause):
344 return RISCV_CSR_GENERAL(scause);
345 case KVM_REG_RISCV_CSR_REG(stval):
346 return RISCV_CSR_GENERAL(stval);
347 case KVM_REG_RISCV_CSR_REG(sip):
348 return RISCV_CSR_GENERAL(sip);
349 case KVM_REG_RISCV_CSR_REG(satp):
350 return RISCV_CSR_GENERAL(satp);
351 case KVM_REG_RISCV_CSR_REG(scounteren):
352 return RISCV_CSR_GENERAL(scounteren);
353 case KVM_REG_RISCV_CSR_REG(senvcfg):
354 return RISCV_CSR_GENERAL(senvcfg);
355 }
356
357 return strdup_printf("KVM_REG_RISCV_CSR_GENERAL | %lld /* UNKNOWN */", reg_off);
358}
359
360static const char *aia_csr_id_to_str(__u64 reg_off)
361{
362 /* reg_off is the offset into struct kvm_riscv_aia_csr */
363 switch (reg_off) {
364 case KVM_REG_RISCV_CSR_AIA_REG(siselect):
365 return RISCV_CSR_AIA(siselect);
366 case KVM_REG_RISCV_CSR_AIA_REG(iprio1):
367 return RISCV_CSR_AIA(iprio1);
368 case KVM_REG_RISCV_CSR_AIA_REG(iprio2):
369 return RISCV_CSR_AIA(iprio2);
370 case KVM_REG_RISCV_CSR_AIA_REG(sieh):
371 return RISCV_CSR_AIA(sieh);
372 case KVM_REG_RISCV_CSR_AIA_REG(siph):
373 return RISCV_CSR_AIA(siph);
374 case KVM_REG_RISCV_CSR_AIA_REG(iprio1h):
375 return RISCV_CSR_AIA(iprio1h);
376 case KVM_REG_RISCV_CSR_AIA_REG(iprio2h):
377 return RISCV_CSR_AIA(iprio2h);
378 }
379
380 return strdup_printf("KVM_REG_RISCV_CSR_AIA | %lld /* UNKNOWN */", reg_off);
381}
382
383static const char *smstateen_csr_id_to_str(__u64 reg_off)
384{
385 /* reg_off is the offset into struct kvm_riscv_smstateen_csr */
386 switch (reg_off) {
387 case KVM_REG_RISCV_CSR_SMSTATEEN_REG(sstateen0):
388 return RISCV_CSR_SMSTATEEN(sstateen0);
389 }
390
391 TEST_FAIL("Unknown smstateen csr reg: 0x%llx", reg_off);
392 return NULL;
393}
394
395static const char *csr_id_to_str(const char *prefix, __u64 id)
396{
397 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CSR);
398 __u64 reg_subtype = reg_off & KVM_REG_RISCV_SUBTYPE_MASK;
399
400 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_CSR);
401
402 reg_off &= ~KVM_REG_RISCV_SUBTYPE_MASK;
403
404 switch (reg_subtype) {
405 case KVM_REG_RISCV_CSR_GENERAL:
406 return general_csr_id_to_str(reg_off);
407 case KVM_REG_RISCV_CSR_AIA:
408 return aia_csr_id_to_str(reg_off);
409 case KVM_REG_RISCV_CSR_SMSTATEEN:
410 return smstateen_csr_id_to_str(reg_off);
411 }
412
413 return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off);
414}
415
416static const char *timer_id_to_str(const char *prefix, __u64 id)
417{
418 /* reg_off is the offset into struct kvm_riscv_timer */
419 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_TIMER);
420
421 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_TIMER);
422
423 switch (reg_off) {
424 case KVM_REG_RISCV_TIMER_REG(frequency):
425 return "KVM_REG_RISCV_TIMER_REG(frequency)";
426 case KVM_REG_RISCV_TIMER_REG(time):
427 return "KVM_REG_RISCV_TIMER_REG(time)";
428 case KVM_REG_RISCV_TIMER_REG(compare):
429 return "KVM_REG_RISCV_TIMER_REG(compare)";
430 case KVM_REG_RISCV_TIMER_REG(state):
431 return "KVM_REG_RISCV_TIMER_REG(state)";
432 }
433
434 return strdup_printf("%lld /* UNKNOWN */", reg_off);
435}
436
437static const char *fp_f_id_to_str(const char *prefix, __u64 id)
438{
439 /* reg_off is the offset into struct __riscv_f_ext_state */
440 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_FP_F);
441
442 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_F);
443
444 switch (reg_off) {
445 case KVM_REG_RISCV_FP_F_REG(f[0]) ...
446 KVM_REG_RISCV_FP_F_REG(f[31]):
447 return strdup_printf("KVM_REG_RISCV_FP_F_REG(f[%lld])", reg_off);
448 case KVM_REG_RISCV_FP_F_REG(fcsr):
449 return "KVM_REG_RISCV_FP_F_REG(fcsr)";
450 }
451
452 return strdup_printf("%lld /* UNKNOWN */", reg_off);
453}
454
455static const char *fp_d_id_to_str(const char *prefix, __u64 id)
456{
457 /* reg_off is the offset into struct __riscv_d_ext_state */
458 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_FP_D);
459
460 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_FP_D);
461
462 switch (reg_off) {
463 case KVM_REG_RISCV_FP_D_REG(f[0]) ...
464 KVM_REG_RISCV_FP_D_REG(f[31]):
465 return strdup_printf("KVM_REG_RISCV_FP_D_REG(f[%lld])", reg_off);
466 case KVM_REG_RISCV_FP_D_REG(fcsr):
467 return "KVM_REG_RISCV_FP_D_REG(fcsr)";
468 }
469
470 return strdup_printf("%lld /* UNKNOWN */", reg_off);
471}
472
473static const char *vector_id_to_str(const char *prefix, __u64 id)
474{
475 /* reg_off is the offset into struct __riscv_v_ext_state */
476 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_VECTOR);
477 int reg_index = 0;
478
479 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_VECTOR);
480
481 if (reg_off >= KVM_REG_RISCV_VECTOR_REG(0))
482 reg_index = reg_off - KVM_REG_RISCV_VECTOR_REG(0);
483 switch (reg_off) {
484 case KVM_REG_RISCV_VECTOR_REG(0) ...
485 KVM_REG_RISCV_VECTOR_REG(31):
486 return strdup_printf("KVM_REG_RISCV_VECTOR_REG(%d)", reg_index);
487 case KVM_REG_RISCV_VECTOR_CSR_REG(vstart):
488 return "KVM_REG_RISCV_VECTOR_CSR_REG(vstart)";
489 case KVM_REG_RISCV_VECTOR_CSR_REG(vl):
490 return "KVM_REG_RISCV_VECTOR_CSR_REG(vl)";
491 case KVM_REG_RISCV_VECTOR_CSR_REG(vtype):
492 return "KVM_REG_RISCV_VECTOR_CSR_REG(vtype)";
493 case KVM_REG_RISCV_VECTOR_CSR_REG(vcsr):
494 return "KVM_REG_RISCV_VECTOR_CSR_REG(vcsr)";
495 case KVM_REG_RISCV_VECTOR_CSR_REG(vlenb):
496 return "KVM_REG_RISCV_VECTOR_CSR_REG(vlenb)";
497 }
498
499 return strdup_printf("%lld /* UNKNOWN */", reg_off);
500}
501
502#define KVM_ISA_EXT_ARR(ext) \
503[KVM_RISCV_ISA_EXT_##ext] = "KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_" #ext
504
505static const char *isa_ext_single_id_to_str(__u64 reg_off)
506{
507 static const char * const kvm_isa_ext_reg_name[] = {
508 KVM_ISA_EXT_ARR(A),
509 KVM_ISA_EXT_ARR(C),
510 KVM_ISA_EXT_ARR(D),
511 KVM_ISA_EXT_ARR(F),
512 KVM_ISA_EXT_ARR(H),
513 KVM_ISA_EXT_ARR(I),
514 KVM_ISA_EXT_ARR(M),
515 KVM_ISA_EXT_ARR(V),
516 KVM_ISA_EXT_ARR(SMNPM),
517 KVM_ISA_EXT_ARR(SMSTATEEN),
518 KVM_ISA_EXT_ARR(SSAIA),
519 KVM_ISA_EXT_ARR(SSCOFPMF),
520 KVM_ISA_EXT_ARR(SSNPM),
521 KVM_ISA_EXT_ARR(SSTC),
522 KVM_ISA_EXT_ARR(SVADE),
523 KVM_ISA_EXT_ARR(SVADU),
524 KVM_ISA_EXT_ARR(SVINVAL),
525 KVM_ISA_EXT_ARR(SVNAPOT),
526 KVM_ISA_EXT_ARR(SVPBMT),
527 KVM_ISA_EXT_ARR(SVVPTC),
528 KVM_ISA_EXT_ARR(ZAAMO),
529 KVM_ISA_EXT_ARR(ZABHA),
530 KVM_ISA_EXT_ARR(ZACAS),
531 KVM_ISA_EXT_ARR(ZALASR),
532 KVM_ISA_EXT_ARR(ZALRSC),
533 KVM_ISA_EXT_ARR(ZAWRS),
534 KVM_ISA_EXT_ARR(ZBA),
535 KVM_ISA_EXT_ARR(ZBB),
536 KVM_ISA_EXT_ARR(ZBC),
537 KVM_ISA_EXT_ARR(ZBKB),
538 KVM_ISA_EXT_ARR(ZBKC),
539 KVM_ISA_EXT_ARR(ZBKX),
540 KVM_ISA_EXT_ARR(ZBS),
541 KVM_ISA_EXT_ARR(ZCA),
542 KVM_ISA_EXT_ARR(ZCB),
543 KVM_ISA_EXT_ARR(ZCD),
544 KVM_ISA_EXT_ARR(ZCF),
545 KVM_ISA_EXT_ARR(ZCLSD),
546 KVM_ISA_EXT_ARR(ZCMOP),
547 KVM_ISA_EXT_ARR(ZFA),
548 KVM_ISA_EXT_ARR(ZFBFMIN),
549 KVM_ISA_EXT_ARR(ZFH),
550 KVM_ISA_EXT_ARR(ZFHMIN),
551 KVM_ISA_EXT_ARR(ZICBOM),
552 KVM_ISA_EXT_ARR(ZICBOP),
553 KVM_ISA_EXT_ARR(ZICBOZ),
554 KVM_ISA_EXT_ARR(ZICCRSE),
555 KVM_ISA_EXT_ARR(ZICNTR),
556 KVM_ISA_EXT_ARR(ZICOND),
557 KVM_ISA_EXT_ARR(ZICSR),
558 KVM_ISA_EXT_ARR(ZIFENCEI),
559 KVM_ISA_EXT_ARR(ZIHINTNTL),
560 KVM_ISA_EXT_ARR(ZIHINTPAUSE),
561 KVM_ISA_EXT_ARR(ZIHPM),
562 KVM_ISA_EXT_ARR(ZILSD),
563 KVM_ISA_EXT_ARR(ZIMOP),
564 KVM_ISA_EXT_ARR(ZKND),
565 KVM_ISA_EXT_ARR(ZKNE),
566 KVM_ISA_EXT_ARR(ZKNH),
567 KVM_ISA_EXT_ARR(ZKR),
568 KVM_ISA_EXT_ARR(ZKSED),
569 KVM_ISA_EXT_ARR(ZKSH),
570 KVM_ISA_EXT_ARR(ZKT),
571 KVM_ISA_EXT_ARR(ZTSO),
572 KVM_ISA_EXT_ARR(ZVBB),
573 KVM_ISA_EXT_ARR(ZVBC),
574 KVM_ISA_EXT_ARR(ZVFBFMIN),
575 KVM_ISA_EXT_ARR(ZVFBFWMA),
576 KVM_ISA_EXT_ARR(ZVFH),
577 KVM_ISA_EXT_ARR(ZVFHMIN),
578 KVM_ISA_EXT_ARR(ZVKB),
579 KVM_ISA_EXT_ARR(ZVKG),
580 KVM_ISA_EXT_ARR(ZVKNED),
581 KVM_ISA_EXT_ARR(ZVKNHA),
582 KVM_ISA_EXT_ARR(ZVKNHB),
583 KVM_ISA_EXT_ARR(ZVKSED),
584 KVM_ISA_EXT_ARR(ZVKSH),
585 KVM_ISA_EXT_ARR(ZVKT),
586 };
587
588 if (reg_off >= ARRAY_SIZE(kvm_isa_ext_reg_name))
589 return strdup_printf("KVM_REG_RISCV_ISA_SINGLE | %lld /* UNKNOWN */", reg_off);
590
591 return kvm_isa_ext_reg_name[reg_off];
592}
593
594static const char *isa_ext_multi_id_to_str(__u64 reg_subtype, __u64 reg_off)
595{
596 const char *unknown = "";
597
598 if (reg_off > KVM_REG_RISCV_ISA_MULTI_REG_LAST)
599 unknown = " /* UNKNOWN */";
600
601 switch (reg_subtype) {
602 case KVM_REG_RISCV_ISA_MULTI_EN:
603 return strdup_printf("KVM_REG_RISCV_ISA_MULTI_EN | %lld%s", reg_off, unknown);
604 case KVM_REG_RISCV_ISA_MULTI_DIS:
605 return strdup_printf("KVM_REG_RISCV_ISA_MULTI_DIS | %lld%s", reg_off, unknown);
606 }
607
608 return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off);
609}
610
611static const char *isa_ext_id_to_str(const char *prefix, __u64 id)
612{
613 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_ISA_EXT);
614 __u64 reg_subtype = reg_off & KVM_REG_RISCV_SUBTYPE_MASK;
615
616 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_ISA_EXT);
617
618 reg_off &= ~KVM_REG_RISCV_SUBTYPE_MASK;
619
620 switch (reg_subtype) {
621 case KVM_REG_RISCV_ISA_SINGLE:
622 return isa_ext_single_id_to_str(reg_off);
623 case KVM_REG_RISCV_ISA_MULTI_EN:
624 case KVM_REG_RISCV_ISA_MULTI_DIS:
625 return isa_ext_multi_id_to_str(reg_subtype, reg_off);
626 }
627
628 return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off);
629}
630
631#define KVM_SBI_EXT_ARR(ext) \
632[ext] = "KVM_REG_RISCV_SBI_SINGLE | " #ext
633
634static const char *sbi_ext_single_id_to_str(__u64 reg_off)
635{
636 /* reg_off is KVM_RISCV_SBI_EXT_ID */
637 static const char * const kvm_sbi_ext_reg_name[] = {
638 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_V01),
639 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_TIME),
640 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_IPI),
641 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_RFENCE),
642 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_SRST),
643 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_HSM),
644 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_PMU),
645 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_DBCN),
646 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_SUSP),
647 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_STA),
648 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_FWFT),
649 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_MPXY),
650 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_EXPERIMENTAL),
651 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_VENDOR),
652 };
653
654 if (reg_off >= ARRAY_SIZE(kvm_sbi_ext_reg_name))
655 return strdup_printf("KVM_REG_RISCV_SBI_SINGLE | %lld /* UNKNOWN */", reg_off);
656
657 return kvm_sbi_ext_reg_name[reg_off];
658}
659
660static const char *sbi_ext_multi_id_to_str(__u64 reg_subtype, __u64 reg_off)
661{
662 const char *unknown = "";
663
664 if (reg_off > KVM_REG_RISCV_SBI_MULTI_REG_LAST)
665 unknown = " /* UNKNOWN */";
666
667 switch (reg_subtype) {
668 case KVM_REG_RISCV_SBI_MULTI_EN:
669 return strdup_printf("KVM_REG_RISCV_SBI_MULTI_EN | %lld%s", reg_off, unknown);
670 case KVM_REG_RISCV_SBI_MULTI_DIS:
671 return strdup_printf("KVM_REG_RISCV_SBI_MULTI_DIS | %lld%s", reg_off, unknown);
672 }
673
674 return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off);
675}
676
677static const char *sbi_ext_id_to_str(const char *prefix, __u64 id)
678{
679 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_SBI_EXT);
680 __u64 reg_subtype = reg_off & KVM_REG_RISCV_SUBTYPE_MASK;
681
682 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_SBI_EXT);
683
684 reg_off &= ~KVM_REG_RISCV_SUBTYPE_MASK;
685
686 switch (reg_subtype) {
687 case KVM_REG_RISCV_SBI_SINGLE:
688 return sbi_ext_single_id_to_str(reg_off);
689 case KVM_REG_RISCV_SBI_MULTI_EN:
690 case KVM_REG_RISCV_SBI_MULTI_DIS:
691 return sbi_ext_multi_id_to_str(reg_subtype, reg_off);
692 }
693
694 return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off);
695}
696
697static const char *sbi_sta_id_to_str(__u64 reg_off)
698{
699 switch (reg_off) {
700 case 0: return "KVM_REG_RISCV_SBI_STA | KVM_REG_RISCV_SBI_STA_REG(shmem_lo)";
701 case 1: return "KVM_REG_RISCV_SBI_STA | KVM_REG_RISCV_SBI_STA_REG(shmem_hi)";
702 }
703 return strdup_printf("KVM_REG_RISCV_SBI_STA | %lld /* UNKNOWN */", reg_off);
704}
705
706static const char *sbi_fwft_id_to_str(__u64 reg_off)
707{
708 switch (reg_off) {
709 case 0: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misaligned_deleg.enable)";
710 case 1: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misaligned_deleg.flags)";
711 case 2: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misaligned_deleg.value)";
712 case 3: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.enable)";
713 case 4: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.flags)";
714 case 5: return "KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.value)";
715 }
716 return strdup_printf("KVM_REG_RISCV_SBI_FWFT | %lld /* UNKNOWN */", reg_off);
717}
718
719static const char *sbi_id_to_str(const char *prefix, __u64 id)
720{
721 __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_SBI_STATE);
722 __u64 reg_subtype = reg_off & KVM_REG_RISCV_SUBTYPE_MASK;
723
724 assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_SBI_STATE);
725
726 reg_off &= ~KVM_REG_RISCV_SUBTYPE_MASK;
727
728 switch (reg_subtype) {
729 case KVM_REG_RISCV_SBI_STA:
730 return sbi_sta_id_to_str(reg_off);
731 case KVM_REG_RISCV_SBI_FWFT:
732 return sbi_fwft_id_to_str(reg_off);
733 }
734
735 return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off);
736}
737
738void print_reg(const char *prefix, __u64 id)
739{
740 const char *reg_size = NULL;
741
742 TEST_ASSERT((id & KVM_REG_ARCH_MASK) == KVM_REG_RISCV,
743 "%s: KVM_REG_RISCV missing in reg id: 0x%llx", prefix, id);
744
745 switch (id & KVM_REG_SIZE_MASK) {
746 case KVM_REG_SIZE_U32:
747 reg_size = "KVM_REG_SIZE_U32";
748 break;
749 case KVM_REG_SIZE_U64:
750 reg_size = "KVM_REG_SIZE_U64";
751 break;
752 case KVM_REG_SIZE_U128:
753 reg_size = "KVM_REG_SIZE_U128";
754 break;
755 case KVM_REG_SIZE_U256:
756 reg_size = "KVM_REG_SIZE_U256";
757 break;
758 default:
759 printf("\tKVM_REG_RISCV | (%lld << KVM_REG_SIZE_SHIFT) | 0x%llx /* UNKNOWN */,\n",
760 (id & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT, id & ~REG_MASK);
761 return;
762 }
763
764 switch (id & KVM_REG_RISCV_TYPE_MASK) {
765 case KVM_REG_RISCV_CONFIG:
766 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_CONFIG | %s,\n",
767 reg_size, config_id_to_str(prefix, id));
768 break;
769 case KVM_REG_RISCV_CORE:
770 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_CORE | %s,\n",
771 reg_size, core_id_to_str(prefix, id));
772 break;
773 case KVM_REG_RISCV_CSR:
774 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_CSR | %s,\n",
775 reg_size, csr_id_to_str(prefix, id));
776 break;
777 case KVM_REG_RISCV_TIMER:
778 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_TIMER | %s,\n",
779 reg_size, timer_id_to_str(prefix, id));
780 break;
781 case KVM_REG_RISCV_FP_F:
782 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_FP_F | %s,\n",
783 reg_size, fp_f_id_to_str(prefix, id));
784 break;
785 case KVM_REG_RISCV_FP_D:
786 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_FP_D | %s,\n",
787 reg_size, fp_d_id_to_str(prefix, id));
788 break;
789 case KVM_REG_RISCV_VECTOR:
790 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_VECTOR | %s,\n",
791 reg_size, vector_id_to_str(prefix, id));
792 break;
793 case KVM_REG_RISCV_ISA_EXT:
794 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_ISA_EXT | %s,\n",
795 reg_size, isa_ext_id_to_str(prefix, id));
796 break;
797 case KVM_REG_RISCV_SBI_EXT:
798 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_SBI_EXT | %s,\n",
799 reg_size, sbi_ext_id_to_str(prefix, id));
800 break;
801 case KVM_REG_RISCV_SBI_STATE:
802 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_SBI_STATE | %s,\n",
803 reg_size, sbi_id_to_str(prefix, id));
804 break;
805 default:
806 printf("\tKVM_REG_RISCV | %s | 0x%llx /* UNKNOWN */,\n",
807 reg_size, id & ~REG_MASK);
808 return;
809 }
810}
811
812/*
813 * The current blessed list was primed with the output of kernel version
814 * v6.5-rc3 and then later updated with new registers.
815 */
816static __u64 base_regs[] = {
817 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(isa),
818 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicbom_block_size),
819 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(mvendorid),
820 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(marchid),
821 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(mimpid),
822 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicboz_block_size),
823 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(satp_mode),
824 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicbop_block_size),
825 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.pc),
826 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.ra),
827 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.sp),
828 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.gp),
829 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.tp),
830 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t0),
831 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t1),
832 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t2),
833 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s0),
834 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s1),
835 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a0),
836 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a1),
837 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a2),
838 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a3),
839 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a4),
840 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a5),
841 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a6),
842 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.a7),
843 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s2),
844 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s3),
845 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s4),
846 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s5),
847 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s6),
848 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s7),
849 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s8),
850 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s9),
851 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s10),
852 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.s11),
853 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t3),
854 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t4),
855 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t5),
856 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(regs.t6),
857 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CORE | KVM_REG_RISCV_CORE_REG(mode),
858 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(sstatus),
859 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(sie),
860 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(stvec),
861 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(sscratch),
862 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(sepc),
863 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(scause),
864 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(stval),
865 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(sip),
866 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(satp),
867 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(scounteren),
868 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(senvcfg),
869 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(frequency),
870 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(time),
871 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(compare),
872 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(state),
873};
874
875/*
876 * The skips_set list registers that should skip set test.
877 * - KVM_REG_RISCV_TIMER_REG(state): set would fail if it was not initialized properly.
878 */
879static __u64 base_skips_set[] = {
880 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(state),
881};
882
883static __u64 sbi_base_regs[] = {
884 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_V01,
885 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_TIME,
886 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_IPI,
887 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_RFENCE,
888 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_SRST,
889 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_HSM,
890 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_EXPERIMENTAL,
891 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_VENDOR,
892};
893
894static __u64 sbi_sta_regs[] = {
895 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_STA,
896 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_STA | KVM_REG_RISCV_SBI_STA_REG(shmem_lo),
897 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_STA | KVM_REG_RISCV_SBI_STA_REG(shmem_hi),
898};
899
900static __u64 sbi_fwft_regs[] = {
901 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_FWFT,
902 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misaligned_deleg.enable),
903 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misaligned_deleg.flags),
904 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(misaligned_deleg.value),
905 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.enable),
906 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.flags),
907 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_STATE | KVM_REG_RISCV_SBI_FWFT | KVM_REG_RISCV_SBI_FWFT_REG(pointer_masking.value),
908};
909
910static __u64 zicbom_regs[] = {
911 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicbom_block_size),
912 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOM,
913};
914
915static __u64 zicbop_regs[] = {
916 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicbop_block_size),
917 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOP,
918};
919
920static __u64 zicboz_regs[] = {
921 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicboz_block_size),
922 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOZ,
923};
924
925static __u64 aia_regs[] = {
926 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siselect),
927 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio1),
928 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio2),
929 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(sieh),
930 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(siph),
931 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio1h),
932 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_AIA_REG(iprio2h),
933 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SSAIA,
934};
935
936static __u64 smstateen_regs[] = {
937 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_SMSTATEEN | KVM_REG_RISCV_CSR_SMSTATEEN_REG(sstateen0),
938 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SMSTATEEN,
939};
940
941static __u64 fp_f_regs[] = {
942 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[0]),
943 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[1]),
944 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[2]),
945 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[3]),
946 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[4]),
947 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[5]),
948 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[6]),
949 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[7]),
950 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[8]),
951 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[9]),
952 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[10]),
953 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[11]),
954 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[12]),
955 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[13]),
956 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[14]),
957 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[15]),
958 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[16]),
959 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[17]),
960 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[18]),
961 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[19]),
962 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[20]),
963 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[21]),
964 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[22]),
965 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[23]),
966 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[24]),
967 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[25]),
968 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[26]),
969 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[27]),
970 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[28]),
971 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[29]),
972 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[30]),
973 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[31]),
974 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(fcsr),
975 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_F,
976};
977
978static __u64 fp_d_regs[] = {
979 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[0]),
980 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[1]),
981 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[2]),
982 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[3]),
983 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[4]),
984 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[5]),
985 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[6]),
986 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[7]),
987 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[8]),
988 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[9]),
989 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[10]),
990 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[11]),
991 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[12]),
992 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[13]),
993 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[14]),
994 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[15]),
995 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[16]),
996 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[17]),
997 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[18]),
998 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[19]),
999 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[20]),
1000 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[21]),
1001 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[22]),
1002 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[23]),
1003 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[24]),
1004 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[25]),
1005 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[26]),
1006 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[27]),
1007 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[28]),
1008 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[29]),
1009 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[30]),
1010 KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(f[31]),
1011 KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_D | KVM_REG_RISCV_FP_D_REG(fcsr),
1012 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_D,
1013};
1014
1015/* Define a default vector registers with length. This will be overwritten at runtime */
1016static __u64 vector_regs[] = {
1017 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_CSR_REG(vstart),
1018 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_CSR_REG(vl),
1019 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_CSR_REG(vtype),
1020 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_CSR_REG(vcsr),
1021 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_CSR_REG(vlenb),
1022 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(0),
1023 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(1),
1024 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(2),
1025 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(3),
1026 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(4),
1027 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(5),
1028 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(6),
1029 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(7),
1030 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(8),
1031 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(9),
1032 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(10),
1033 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(11),
1034 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(12),
1035 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(13),
1036 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(14),
1037 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(15),
1038 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(16),
1039 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(17),
1040 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(18),
1041 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(19),
1042 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(20),
1043 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(21),
1044 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(22),
1045 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(23),
1046 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(24),
1047 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(25),
1048 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(26),
1049 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(27),
1050 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(28),
1051 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(29),
1052 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(30),
1053 KVM_REG_RISCV | KVM_REG_SIZE_U128 | KVM_REG_RISCV_VECTOR | KVM_REG_RISCV_VECTOR_REG(31),
1054 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_V,
1055};
1056
1057#define SUBLIST_BASE \
1058 {"base", .regs = base_regs, .regs_n = ARRAY_SIZE(base_regs), \
1059 .skips_set = base_skips_set, .skips_set_n = ARRAY_SIZE(base_skips_set),}
1060#define SUBLIST_SBI_BASE \
1061 {"sbi-base", .feature_type = VCPU_FEATURE_SBI_EXT, .feature = KVM_RISCV_SBI_EXT_V01, \
1062 .regs = sbi_base_regs, .regs_n = ARRAY_SIZE(sbi_base_regs),}
1063#define SUBLIST_SBI_STA \
1064 {"sbi-sta", .feature_type = VCPU_FEATURE_SBI_EXT, .feature = KVM_RISCV_SBI_EXT_STA, \
1065 .regs = sbi_sta_regs, .regs_n = ARRAY_SIZE(sbi_sta_regs),}
1066#define SUBLIST_SBI_FWFT \
1067 {"sbi-fwft", .feature_type = VCPU_FEATURE_SBI_EXT, .feature = KVM_RISCV_SBI_EXT_FWFT, \
1068 .regs = sbi_fwft_regs, .regs_n = ARRAY_SIZE(sbi_fwft_regs),}
1069#define SUBLIST_ZICBOM \
1070 {"zicbom", .feature = KVM_RISCV_ISA_EXT_ZICBOM, .regs = zicbom_regs, .regs_n = ARRAY_SIZE(zicbom_regs),}
1071#define SUBLIST_ZICBOP \
1072 {"zicbop", .feature = KVM_RISCV_ISA_EXT_ZICBOP, .regs = zicbop_regs, .regs_n = ARRAY_SIZE(zicbop_regs),}
1073#define SUBLIST_ZICBOZ \
1074 {"zicboz", .feature = KVM_RISCV_ISA_EXT_ZICBOZ, .regs = zicboz_regs, .regs_n = ARRAY_SIZE(zicboz_regs),}
1075#define SUBLIST_AIA \
1076 {"aia", .feature = KVM_RISCV_ISA_EXT_SSAIA, .regs = aia_regs, .regs_n = ARRAY_SIZE(aia_regs),}
1077#define SUBLIST_SMSTATEEN \
1078 {"smstateen", .feature = KVM_RISCV_ISA_EXT_SMSTATEEN, .regs = smstateen_regs, .regs_n = ARRAY_SIZE(smstateen_regs),}
1079#define SUBLIST_FP_F \
1080 {"fp_f", .feature = KVM_RISCV_ISA_EXT_F, .regs = fp_f_regs, \
1081 .regs_n = ARRAY_SIZE(fp_f_regs),}
1082#define SUBLIST_FP_D \
1083 {"fp_d", .feature = KVM_RISCV_ISA_EXT_D, .regs = fp_d_regs, \
1084 .regs_n = ARRAY_SIZE(fp_d_regs),}
1085
1086#define SUBLIST_V \
1087 {"v", .feature = KVM_RISCV_ISA_EXT_V, .regs = vector_regs, .regs_n = ARRAY_SIZE(vector_regs),}
1088
1089#define KVM_ISA_EXT_SIMPLE_CONFIG(ext, extu) \
1090static __u64 regs_##ext[] = { \
1091 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | \
1092 KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | \
1093 KVM_RISCV_ISA_EXT_##extu, \
1094}; \
1095static struct vcpu_reg_list config_##ext = { \
1096 .sublists = { \
1097 SUBLIST_BASE, \
1098 { \
1099 .name = #ext, \
1100 .feature = KVM_RISCV_ISA_EXT_##extu, \
1101 .regs = regs_##ext, \
1102 .regs_n = ARRAY_SIZE(regs_##ext), \
1103 }, \
1104 {0}, \
1105 }, \
1106} \
1107
1108#define KVM_SBI_EXT_SIMPLE_CONFIG(ext, extu) \
1109static __u64 regs_sbi_##ext[] = { \
1110 KVM_REG_RISCV | KVM_REG_SIZE_ULONG | \
1111 KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | \
1112 KVM_RISCV_SBI_EXT_##extu, \
1113}; \
1114static struct vcpu_reg_list config_sbi_##ext = { \
1115 .sublists = { \
1116 SUBLIST_BASE, \
1117 { \
1118 .name = "sbi-"#ext, \
1119 .feature_type = VCPU_FEATURE_SBI_EXT, \
1120 .feature = KVM_RISCV_SBI_EXT_##extu, \
1121 .regs = regs_sbi_##ext, \
1122 .regs_n = ARRAY_SIZE(regs_sbi_##ext), \
1123 }, \
1124 {0}, \
1125 }, \
1126} \
1127
1128#define KVM_ISA_EXT_SUBLIST_CONFIG(ext, extu) \
1129static struct vcpu_reg_list config_##ext = { \
1130 .sublists = { \
1131 SUBLIST_BASE, \
1132 SUBLIST_##extu, \
1133 {0}, \
1134 }, \
1135} \
1136
1137#define KVM_SBI_EXT_SUBLIST_CONFIG(ext, extu) \
1138static struct vcpu_reg_list config_sbi_##ext = { \
1139 .sublists = { \
1140 SUBLIST_BASE, \
1141 SUBLIST_SBI_##extu, \
1142 {0}, \
1143 }, \
1144} \
1145
1146/* Note: The below list is alphabetically sorted. */
1147
1148KVM_SBI_EXT_SUBLIST_CONFIG(base, BASE);
1149KVM_SBI_EXT_SUBLIST_CONFIG(sta, STA);
1150KVM_SBI_EXT_SIMPLE_CONFIG(pmu, PMU);
1151KVM_SBI_EXT_SIMPLE_CONFIG(dbcn, DBCN);
1152KVM_SBI_EXT_SIMPLE_CONFIG(susp, SUSP);
1153KVM_SBI_EXT_SIMPLE_CONFIG(mpxy, MPXY);
1154KVM_SBI_EXT_SUBLIST_CONFIG(fwft, FWFT);
1155
1156KVM_ISA_EXT_SUBLIST_CONFIG(aia, AIA);
1157KVM_ISA_EXT_SUBLIST_CONFIG(fp_f, FP_F);
1158KVM_ISA_EXT_SUBLIST_CONFIG(fp_d, FP_D);
1159KVM_ISA_EXT_SUBLIST_CONFIG(v, V);
1160KVM_ISA_EXT_SIMPLE_CONFIG(h, H);
1161KVM_ISA_EXT_SIMPLE_CONFIG(smnpm, SMNPM);
1162KVM_ISA_EXT_SUBLIST_CONFIG(smstateen, SMSTATEEN);
1163KVM_ISA_EXT_SIMPLE_CONFIG(sscofpmf, SSCOFPMF);
1164KVM_ISA_EXT_SIMPLE_CONFIG(ssnpm, SSNPM);
1165KVM_ISA_EXT_SIMPLE_CONFIG(sstc, SSTC);
1166KVM_ISA_EXT_SIMPLE_CONFIG(svade, SVADE);
1167KVM_ISA_EXT_SIMPLE_CONFIG(svadu, SVADU);
1168KVM_ISA_EXT_SIMPLE_CONFIG(svinval, SVINVAL);
1169KVM_ISA_EXT_SIMPLE_CONFIG(svnapot, SVNAPOT);
1170KVM_ISA_EXT_SIMPLE_CONFIG(svpbmt, SVPBMT);
1171KVM_ISA_EXT_SIMPLE_CONFIG(svvptc, SVVPTC);
1172KVM_ISA_EXT_SIMPLE_CONFIG(zaamo, ZAAMO);
1173KVM_ISA_EXT_SIMPLE_CONFIG(zabha, ZABHA);
1174KVM_ISA_EXT_SIMPLE_CONFIG(zacas, ZACAS);
1175KVM_ISA_EXT_SIMPLE_CONFIG(zalasr, ZALASR);
1176KVM_ISA_EXT_SIMPLE_CONFIG(zalrsc, ZALRSC);
1177KVM_ISA_EXT_SIMPLE_CONFIG(zawrs, ZAWRS);
1178KVM_ISA_EXT_SIMPLE_CONFIG(zba, ZBA);
1179KVM_ISA_EXT_SIMPLE_CONFIG(zbb, ZBB);
1180KVM_ISA_EXT_SIMPLE_CONFIG(zbc, ZBC);
1181KVM_ISA_EXT_SIMPLE_CONFIG(zbkb, ZBKB);
1182KVM_ISA_EXT_SIMPLE_CONFIG(zbkc, ZBKC);
1183KVM_ISA_EXT_SIMPLE_CONFIG(zbkx, ZBKX);
1184KVM_ISA_EXT_SIMPLE_CONFIG(zbs, ZBS);
1185KVM_ISA_EXT_SIMPLE_CONFIG(zca, ZCA);
1186KVM_ISA_EXT_SIMPLE_CONFIG(zcb, ZCB);
1187KVM_ISA_EXT_SIMPLE_CONFIG(zcd, ZCD);
1188KVM_ISA_EXT_SIMPLE_CONFIG(zcf, ZCF);
1189KVM_ISA_EXT_SIMPLE_CONFIG(zclsd, ZCLSD);
1190KVM_ISA_EXT_SIMPLE_CONFIG(zcmop, ZCMOP);
1191KVM_ISA_EXT_SIMPLE_CONFIG(zfa, ZFA);
1192KVM_ISA_EXT_SIMPLE_CONFIG(zfbfmin, ZFBFMIN);
1193KVM_ISA_EXT_SIMPLE_CONFIG(zfh, ZFH);
1194KVM_ISA_EXT_SIMPLE_CONFIG(zfhmin, ZFHMIN);
1195KVM_ISA_EXT_SUBLIST_CONFIG(zicbom, ZICBOM);
1196KVM_ISA_EXT_SUBLIST_CONFIG(zicbop, ZICBOP);
1197KVM_ISA_EXT_SUBLIST_CONFIG(zicboz, ZICBOZ);
1198KVM_ISA_EXT_SIMPLE_CONFIG(ziccrse, ZICCRSE);
1199KVM_ISA_EXT_SIMPLE_CONFIG(zicntr, ZICNTR);
1200KVM_ISA_EXT_SIMPLE_CONFIG(zicond, ZICOND);
1201KVM_ISA_EXT_SIMPLE_CONFIG(zicsr, ZICSR);
1202KVM_ISA_EXT_SIMPLE_CONFIG(zifencei, ZIFENCEI);
1203KVM_ISA_EXT_SIMPLE_CONFIG(zihintntl, ZIHINTNTL);
1204KVM_ISA_EXT_SIMPLE_CONFIG(zihintpause, ZIHINTPAUSE);
1205KVM_ISA_EXT_SIMPLE_CONFIG(zihpm, ZIHPM);
1206KVM_ISA_EXT_SIMPLE_CONFIG(zilsd, ZILSD);
1207KVM_ISA_EXT_SIMPLE_CONFIG(zimop, ZIMOP);
1208KVM_ISA_EXT_SIMPLE_CONFIG(zknd, ZKND);
1209KVM_ISA_EXT_SIMPLE_CONFIG(zkne, ZKNE);
1210KVM_ISA_EXT_SIMPLE_CONFIG(zknh, ZKNH);
1211KVM_ISA_EXT_SIMPLE_CONFIG(zkr, ZKR);
1212KVM_ISA_EXT_SIMPLE_CONFIG(zksed, ZKSED);
1213KVM_ISA_EXT_SIMPLE_CONFIG(zksh, ZKSH);
1214KVM_ISA_EXT_SIMPLE_CONFIG(zkt, ZKT);
1215KVM_ISA_EXT_SIMPLE_CONFIG(ztso, ZTSO);
1216KVM_ISA_EXT_SIMPLE_CONFIG(zvbb, ZVBB);
1217KVM_ISA_EXT_SIMPLE_CONFIG(zvbc, ZVBC);
1218KVM_ISA_EXT_SIMPLE_CONFIG(zvfbfmin, ZVFBFMIN);
1219KVM_ISA_EXT_SIMPLE_CONFIG(zvfbfwma, ZVFBFWMA);
1220KVM_ISA_EXT_SIMPLE_CONFIG(zvfh, ZVFH);
1221KVM_ISA_EXT_SIMPLE_CONFIG(zvfhmin, ZVFHMIN);
1222KVM_ISA_EXT_SIMPLE_CONFIG(zvkb, ZVKB);
1223KVM_ISA_EXT_SIMPLE_CONFIG(zvkg, ZVKG);
1224KVM_ISA_EXT_SIMPLE_CONFIG(zvkned, ZVKNED);
1225KVM_ISA_EXT_SIMPLE_CONFIG(zvknha, ZVKNHA);
1226KVM_ISA_EXT_SIMPLE_CONFIG(zvknhb, ZVKNHB);
1227KVM_ISA_EXT_SIMPLE_CONFIG(zvksed, ZVKSED);
1228KVM_ISA_EXT_SIMPLE_CONFIG(zvksh, ZVKSH);
1229KVM_ISA_EXT_SIMPLE_CONFIG(zvkt, ZVKT);
1230
1231struct vcpu_reg_list *vcpu_configs[] = {
1232 &config_sbi_base,
1233 &config_sbi_sta,
1234 &config_sbi_pmu,
1235 &config_sbi_dbcn,
1236 &config_sbi_susp,
1237 &config_sbi_mpxy,
1238 &config_sbi_fwft,
1239 &config_aia,
1240 &config_fp_f,
1241 &config_fp_d,
1242 &config_h,
1243 &config_v,
1244 &config_smnpm,
1245 &config_smstateen,
1246 &config_sscofpmf,
1247 &config_ssnpm,
1248 &config_sstc,
1249 &config_svade,
1250 &config_svadu,
1251 &config_svinval,
1252 &config_svnapot,
1253 &config_svpbmt,
1254 &config_svvptc,
1255 &config_zaamo,
1256 &config_zabha,
1257 &config_zacas,
1258 &config_zalrsc,
1259 &config_zalasr,
1260 &config_zawrs,
1261 &config_zba,
1262 &config_zbb,
1263 &config_zbc,
1264 &config_zbkb,
1265 &config_zbkc,
1266 &config_zbkx,
1267 &config_zbs,
1268 &config_zca,
1269 &config_zcb,
1270 &config_zcd,
1271 &config_zcf,
1272 &config_zclsd,
1273 &config_zcmop,
1274 &config_zfa,
1275 &config_zfbfmin,
1276 &config_zfh,
1277 &config_zfhmin,
1278 &config_zicbom,
1279 &config_zicbop,
1280 &config_zicboz,
1281 &config_ziccrse,
1282 &config_zicntr,
1283 &config_zicond,
1284 &config_zicsr,
1285 &config_zifencei,
1286 &config_zihintntl,
1287 &config_zihintpause,
1288 &config_zihpm,
1289 &config_zilsd,
1290 &config_zimop,
1291 &config_zknd,
1292 &config_zkne,
1293 &config_zknh,
1294 &config_zkr,
1295 &config_zksed,
1296 &config_zksh,
1297 &config_zkt,
1298 &config_ztso,
1299 &config_zvbb,
1300 &config_zvbc,
1301 &config_zvfbfmin,
1302 &config_zvfbfwma,
1303 &config_zvfh,
1304 &config_zvfhmin,
1305 &config_zvkb,
1306 &config_zvkg,
1307 &config_zvkned,
1308 &config_zvknha,
1309 &config_zvknhb,
1310 &config_zvksed,
1311 &config_zvksh,
1312 &config_zvkt,
1313};
1314int vcpu_configs_n = ARRAY_SIZE(vcpu_configs);