Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * ucna_injection_test
4 *
5 * Copyright (C) 2022, Google LLC.
6 *
7 * This work is licensed under the terms of the GNU GPL, version 2.
8 *
9 * Test that user space can inject UnCorrectable No Action required (UCNA)
10 * memory errors to the guest.
11 *
12 * The test starts one vCPU with the MCG_CMCI_P enabled. It verifies that
13 * proper UCNA errors can be injected to a vCPU with MCG_CMCI_P and
14 * corresponding per-bank control register (MCI_CTL2) bit enabled.
15 * The test also checks that the UCNA errors get recorded in the
16 * Machine Check bank registers no matter the error signal interrupts get
17 * delivered into the guest or not.
18 *
19 */
20#include <pthread.h>
21#include <inttypes.h>
22#include <string.h>
23#include <time.h>
24
25#include "kvm_util.h"
26#include "mce.h"
27#include "processor.h"
28#include "test_util.h"
29#include "apic.h"
30
31#define SYNC_FIRST_UCNA 9
32#define SYNC_SECOND_UCNA 10
33#define SYNC_GP 11
34#define FIRST_UCNA_ADDR 0xdeadbeef
35#define SECOND_UCNA_ADDR 0xcafeb0ba
36
37/*
38 * Vector for the CMCI interrupt.
39 * Value is arbitrary. Any value in 0x20-0xFF should work:
40 * https://wiki.osdev.org/Interrupt_Vector_Table
41 */
42#define CMCI_VECTOR 0xa9
43
44#define UCNA_BANK 0x7 // IMC0 bank
45
46#define MCI_CTL2_RESERVED_BIT BIT_ULL(29)
47
48static u64 supported_mcg_caps;
49
50/*
51 * Record states about the injected UCNA.
52 * The variables started with the 'i_' prefixes are recorded in interrupt
53 * handler. Variables without the 'i_' prefixes are recorded in guest main
54 * execution thread.
55 */
56static volatile u64 i_ucna_rcvd;
57static volatile u64 i_ucna_addr;
58static volatile u64 ucna_addr;
59static volatile u64 ucna_addr2;
60
61struct thread_params {
62 struct kvm_vcpu *vcpu;
63 u64 *p_i_ucna_rcvd;
64 u64 *p_i_ucna_addr;
65 u64 *p_ucna_addr;
66 u64 *p_ucna_addr2;
67};
68
69static void verify_apic_base_addr(void)
70{
71 u64 msr = rdmsr(MSR_IA32_APICBASE);
72 u64 base = GET_APIC_BASE(msr);
73
74 GUEST_ASSERT(base == APIC_DEFAULT_GPA);
75}
76
77static void ucna_injection_guest_code(void)
78{
79 u64 ctl2;
80 verify_apic_base_addr();
81 xapic_enable();
82
83 /* Sets up the interrupt vector and enables per-bank CMCI sigaling. */
84 xapic_write_reg(APIC_LVTCMCI, CMCI_VECTOR | APIC_DM_FIXED);
85 ctl2 = rdmsr(MSR_IA32_MCx_CTL2(UCNA_BANK));
86 wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 | MCI_CTL2_CMCI_EN);
87
88 /* Enables interrupt in guest. */
89 sti();
90
91 /* Let user space inject the first UCNA */
92 GUEST_SYNC(SYNC_FIRST_UCNA);
93
94 ucna_addr = rdmsr(MSR_IA32_MCx_ADDR(UCNA_BANK));
95
96 /* Disables the per-bank CMCI signaling. */
97 ctl2 = rdmsr(MSR_IA32_MCx_CTL2(UCNA_BANK));
98 wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 & ~MCI_CTL2_CMCI_EN);
99
100 /* Let the user space inject the second UCNA */
101 GUEST_SYNC(SYNC_SECOND_UCNA);
102
103 ucna_addr2 = rdmsr(MSR_IA32_MCx_ADDR(UCNA_BANK));
104 GUEST_DONE();
105}
106
107static void cmci_disabled_guest_code(void)
108{
109 u64 ctl2 = rdmsr(MSR_IA32_MCx_CTL2(UCNA_BANK));
110 wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 | MCI_CTL2_CMCI_EN);
111
112 GUEST_DONE();
113}
114
115static void cmci_enabled_guest_code(void)
116{
117 u64 ctl2 = rdmsr(MSR_IA32_MCx_CTL2(UCNA_BANK));
118 wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 | MCI_CTL2_RESERVED_BIT);
119
120 GUEST_DONE();
121}
122
123static void guest_cmci_handler(struct ex_regs *regs)
124{
125 i_ucna_rcvd++;
126 i_ucna_addr = rdmsr(MSR_IA32_MCx_ADDR(UCNA_BANK));
127 xapic_write_reg(APIC_EOI, 0);
128}
129
130static void guest_gp_handler(struct ex_regs *regs)
131{
132 GUEST_SYNC(SYNC_GP);
133}
134
135static void run_vcpu_expect_gp(struct kvm_vcpu *vcpu)
136{
137 struct ucall uc;
138
139 vcpu_run(vcpu);
140
141 TEST_ASSERT_KVM_EXIT_REASON(vcpu, KVM_EXIT_IO);
142 TEST_ASSERT(get_ucall(vcpu, &uc) == UCALL_SYNC,
143 "Expect UCALL_SYNC");
144 TEST_ASSERT(uc.args[1] == SYNC_GP, "#GP is expected.");
145 printf("vCPU received GP in guest.\n");
146}
147
148static void inject_ucna(struct kvm_vcpu *vcpu, u64 addr)
149{
150 /*
151 * A UCNA error is indicated with VAL=1, UC=1, PCC=0, S=0 and AR=0 in
152 * the IA32_MCi_STATUS register.
153 * MSCOD=1 (BIT[16] - MscodDataRdErr).
154 * MCACOD=0x0090 (Memory controller error format, channel 0)
155 */
156 u64 status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
157 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | 0x10090;
158 struct kvm_x86_mce mce = {};
159 mce.status = status;
160 mce.mcg_status = 0;
161 /*
162 * MCM_ADDR_PHYS indicates the reported address is a physical address.
163 * Lowest 6 bits is the recoverable address LSB, i.e., the injected MCE
164 * is at 4KB granularity.
165 */
166 mce.misc = (MCM_ADDR_PHYS << 6) | 0xc;
167 mce.addr = addr;
168 mce.bank = UCNA_BANK;
169
170 vcpu_ioctl(vcpu, KVM_X86_SET_MCE, &mce);
171}
172
173static void *run_ucna_injection(void *arg)
174{
175 struct thread_params *params = (struct thread_params *)arg;
176 struct ucall uc;
177 int old;
178 int r;
179
180 r = pthread_setcanceltype(PTHREAD_CANCEL_ASYNCHRONOUS, &old);
181 TEST_ASSERT(r == 0,
182 "pthread_setcanceltype failed with errno=%d",
183 r);
184
185 vcpu_run(params->vcpu);
186
187 TEST_ASSERT_KVM_EXIT_REASON(params->vcpu, KVM_EXIT_IO);
188 TEST_ASSERT(get_ucall(params->vcpu, &uc) == UCALL_SYNC,
189 "Expect UCALL_SYNC");
190 TEST_ASSERT(uc.args[1] == SYNC_FIRST_UCNA, "Injecting first UCNA.");
191
192 printf("Injecting first UCNA at %#x.\n", FIRST_UCNA_ADDR);
193
194 inject_ucna(params->vcpu, FIRST_UCNA_ADDR);
195 vcpu_run(params->vcpu);
196
197 TEST_ASSERT_KVM_EXIT_REASON(params->vcpu, KVM_EXIT_IO);
198 TEST_ASSERT(get_ucall(params->vcpu, &uc) == UCALL_SYNC,
199 "Expect UCALL_SYNC");
200 TEST_ASSERT(uc.args[1] == SYNC_SECOND_UCNA, "Injecting second UCNA.");
201
202 printf("Injecting second UCNA at %#x.\n", SECOND_UCNA_ADDR);
203
204 inject_ucna(params->vcpu, SECOND_UCNA_ADDR);
205 vcpu_run(params->vcpu);
206
207 TEST_ASSERT_KVM_EXIT_REASON(params->vcpu, KVM_EXIT_IO);
208 if (get_ucall(params->vcpu, &uc) == UCALL_ABORT) {
209 TEST_ASSERT(false, "vCPU assertion failure: %s.",
210 (const char *)uc.args[0]);
211 }
212
213 return NULL;
214}
215
216static void test_ucna_injection(struct kvm_vcpu *vcpu, struct thread_params *params)
217{
218 struct kvm_vm *vm = vcpu->vm;
219 params->vcpu = vcpu;
220 params->p_i_ucna_rcvd = (u64 *)addr_gva2hva(vm, (u64)&i_ucna_rcvd);
221 params->p_i_ucna_addr = (u64 *)addr_gva2hva(vm, (u64)&i_ucna_addr);
222 params->p_ucna_addr = (u64 *)addr_gva2hva(vm, (u64)&ucna_addr);
223 params->p_ucna_addr2 = (u64 *)addr_gva2hva(vm, (u64)&ucna_addr2);
224
225 run_ucna_injection(params);
226
227 TEST_ASSERT(*params->p_i_ucna_rcvd == 1, "Only first UCNA get signaled.");
228 TEST_ASSERT(*params->p_i_ucna_addr == FIRST_UCNA_ADDR,
229 "Only first UCNA reported addr get recorded via interrupt.");
230 TEST_ASSERT(*params->p_ucna_addr == FIRST_UCNA_ADDR,
231 "First injected UCNAs should get exposed via registers.");
232 TEST_ASSERT(*params->p_ucna_addr2 == SECOND_UCNA_ADDR,
233 "Second injected UCNAs should get exposed via registers.");
234
235 printf("Test successful.\n"
236 "UCNA CMCI interrupts received: %ld\n"
237 "Last UCNA address received via CMCI: %lx\n"
238 "First UCNA address in vCPU thread: %lx\n"
239 "Second UCNA address in vCPU thread: %lx\n",
240 *params->p_i_ucna_rcvd, *params->p_i_ucna_addr,
241 *params->p_ucna_addr, *params->p_ucna_addr2);
242}
243
244static void setup_mce_cap(struct kvm_vcpu *vcpu, bool enable_cmci_p)
245{
246 u64 mcg_caps = MCG_CTL_P | MCG_SER_P | MCG_LMCE_P | KVM_MAX_MCE_BANKS;
247 if (enable_cmci_p)
248 mcg_caps |= MCG_CMCI_P;
249
250 mcg_caps &= supported_mcg_caps | MCG_CAP_BANKS_MASK;
251 vcpu_ioctl(vcpu, KVM_X86_SETUP_MCE, &mcg_caps);
252}
253
254static struct kvm_vcpu *create_vcpu_with_mce_cap(struct kvm_vm *vm, u32 vcpuid,
255 bool enable_cmci_p, void *guest_code)
256{
257 struct kvm_vcpu *vcpu = vm_vcpu_add(vm, vcpuid, guest_code);
258 setup_mce_cap(vcpu, enable_cmci_p);
259 return vcpu;
260}
261
262int main(int argc, char *argv[])
263{
264 struct thread_params params;
265 struct kvm_vm *vm;
266 struct kvm_vcpu *ucna_vcpu;
267 struct kvm_vcpu *cmcidis_vcpu;
268 struct kvm_vcpu *cmci_vcpu;
269
270 kvm_check_cap(KVM_CAP_MCE);
271
272 vm = __vm_create(VM_SHAPE_DEFAULT, 3, 0);
273
274 kvm_ioctl(vm->kvm_fd, KVM_X86_GET_MCE_CAP_SUPPORTED,
275 &supported_mcg_caps);
276
277 if (!(supported_mcg_caps & MCG_CMCI_P)) {
278 print_skip("MCG_CMCI_P is not supported");
279 exit(KSFT_SKIP);
280 }
281
282 ucna_vcpu = create_vcpu_with_mce_cap(vm, 0, true, ucna_injection_guest_code);
283 cmcidis_vcpu = create_vcpu_with_mce_cap(vm, 1, false, cmci_disabled_guest_code);
284 cmci_vcpu = create_vcpu_with_mce_cap(vm, 2, true, cmci_enabled_guest_code);
285
286 vm_install_exception_handler(vm, CMCI_VECTOR, guest_cmci_handler);
287 vm_install_exception_handler(vm, GP_VECTOR, guest_gp_handler);
288
289 virt_pg_map(vm, APIC_DEFAULT_GPA, APIC_DEFAULT_GPA);
290
291 test_ucna_injection(ucna_vcpu, ¶ms);
292 run_vcpu_expect_gp(cmcidis_vcpu);
293 run_vcpu_expect_gp(cmci_vcpu);
294
295 kvm_vm_free(vm);
296}