Merge tag 'mlx5-psp-ifc' of git://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux

+6

drivers/net/ethernet/mellanox/mlx5/core/fw.c

··· 294 294 return err; 295 295 } 296 296 297 + if (MLX5_CAP_GEN(dev, psp)) { 298 + err = mlx5_core_get_caps(dev, MLX5_CAP_PSP); 299 + if (err) 300 + return err; 301 + } 302 + 297 303 return 0; 298 304 } 299 305

+1

drivers/net/ethernet/mellanox/mlx5/core/main.c

··· 1798 1798 MLX5_CAP_VDPA_EMULATION, 1799 1799 MLX5_CAP_IPSEC, 1800 1800 MLX5_CAP_PORT_SELECTION, 1801 + MLX5_CAP_PSP, 1801 1802 MLX5_CAP_MACSEC, 1802 1803 MLX5_CAP_ADV_VIRTUALIZATION, 1803 1804 MLX5_CAP_CRYPTO,

+1 -1

drivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.c

··· 1280 1280 struct mlx5hws_definer_fc *fc = cd->fc; 1281 1281 struct mlx5hws_definer_fc *curr_fc; 1282 1282 1283 - if (HWS_IS_FLD_SET_SZ(match_param, misc_parameters_2.reserved_at_1a0, 0x8) || 1283 + if (HWS_IS_FLD_SET_SZ(match_param, misc_parameters_2.psp_syndrome, 0x8) || 1284 1284 HWS_IS_FLD_SET_SZ(match_param, 1285 1285 misc_parameters_2.ipsec_next_header, 0x8) || 1286 1286 HWS_IS_FLD_SET_SZ(match_param, misc_parameters_2.reserved_at_1c0, 0x40) ||

+4

include/linux/mlx5/device.h

··· 1248 1248 MLX5_CAP_IPSEC, 1249 1249 MLX5_CAP_CRYPTO = 0x1a, 1250 1250 MLX5_CAP_SHAMPO = 0x1d, 1251 + MLX5_CAP_PSP = 0x1e, 1251 1252 MLX5_CAP_MACSEC = 0x1f, 1252 1253 MLX5_CAP_GENERAL_2 = 0x20, 1253 1254 MLX5_CAP_PORT_SELECTION = 0x25, ··· 1487 1486 1488 1487 #define MLX5_CAP_SHAMPO(mdev, cap) \ 1489 1488 MLX5_GET(shampo_cap, mdev->caps.hca[MLX5_CAP_SHAMPO]->cur, cap) 1489 + 1490 + #define MLX5_CAP_PSP(mdev, cap)\ 1491 + MLX5_GET(psp_cap, (mdev)->caps.hca[MLX5_CAP_PSP]->cur, cap) 1490 1492 1491 1493 enum { 1492 1494 MLX5_CMD_STAT_OK = 0x0,

+91 -4

include/linux/mlx5/mlx5_ifc.h

··· 314 314 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 315 315 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 316 316 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 317 + MLX5_CMD_OP_PSP_GEN_SPI = 0xb10, 318 + MLX5_CMD_OP_PSP_ROTATE_KEY = 0xb11, 317 319 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 318 320 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 319 321 MLX5_CMD_OP_SYNC_CRYPTO = 0xb12, ··· 491 489 u8 execute_aso[0x1]; 492 490 u8 reserved_at_47[0x19]; 493 491 494 - u8 reserved_at_60[0x2]; 492 + u8 reformat_l2_to_l3_psp_tunnel[0x1]; 493 + u8 reformat_l3_psp_tunnel_to_l2[0x1]; 495 494 u8 reformat_insert[0x1]; 496 495 u8 reformat_remove[0x1]; 497 496 u8 macsec_encrypt[0x1]; 498 497 u8 macsec_decrypt[0x1]; 499 - u8 reserved_at_66[0x2]; 498 + u8 psp_encrypt[0x1]; 499 + u8 psp_decrypt[0x1]; 500 500 u8 reformat_add_macsec[0x1]; 501 501 u8 reformat_remove_macsec[0x1]; 502 502 u8 reparse[0x1]; ··· 707 703 708 704 u8 metadata_reg_a[0x20]; 709 705 710 - u8 reserved_at_1a0[0x8]; 706 + u8 psp_syndrome[0x8]; 711 707 u8 macsec_syndrome[0x8]; 712 708 u8 ipsec_syndrome[0x8]; 713 709 u8 ipsec_next_header[0x8]; ··· 1515 1511 u8 reserved_at_40[0x7c0]; 1516 1512 }; 1517 1513 1514 + struct mlx5_ifc_psp_cap_bits { 1515 + u8 reserved_at_0[0x1]; 1516 + u8 psp_crypto_offload[0x1]; 1517 + u8 reserved_at_2[0x1]; 1518 + u8 psp_crypto_esp_aes_gcm_256_encrypt[0x1]; 1519 + u8 psp_crypto_esp_aes_gcm_128_encrypt[0x1]; 1520 + u8 psp_crypto_esp_aes_gcm_256_decrypt[0x1]; 1521 + u8 psp_crypto_esp_aes_gcm_128_decrypt[0x1]; 1522 + u8 reserved_at_7[0x4]; 1523 + u8 log_max_num_of_psp_spi[0x5]; 1524 + u8 reserved_at_10[0x10]; 1525 + 1526 + u8 reserved_at_20[0x7e0]; 1527 + }; 1528 + 1518 1529 enum { 1519 1530 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1520 1531 MLX5_WQ_TYPE_CYCLIC = 0x1, ··· 1895 1876 1896 1877 u8 reserved_at_2a0[0x7]; 1897 1878 u8 mkey_pcie_tph[0x1]; 1898 - u8 reserved_at_2a8[0x3]; 1879 + u8 reserved_at_2a8[0x2]; 1880 + 1881 + u8 psp[0x1]; 1899 1882 u8 shampo[0x1]; 1900 1883 u8 reserved_at_2ac[0x4]; 1901 1884 u8 max_wqe_sz_rq[0x10]; ··· 3824 3803 struct mlx5_ifc_macsec_cap_bits macsec_cap; 3825 3804 struct mlx5_ifc_crypto_cap_bits crypto_cap; 3826 3805 struct mlx5_ifc_ipsec_cap_bits ipsec_cap; 3806 + struct mlx5_ifc_psp_cap_bits psp_cap; 3827 3807 u8 reserved_at_0[0x8000]; 3828 3808 }; 3829 3809 ··· 3854 3832 enum { 3855 3833 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 3856 3834 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1, 3835 + MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_PSP = 0x2, 3857 3836 }; 3858 3837 3859 3838 struct mlx5_ifc_vlan_bits { ··· 7182 7159 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa, 7183 7160 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb, 7184 7161 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc, 7162 + MLX5_REFORMAT_TYPE_ADD_PSP_TUNNEL = 0xd, 7163 + MLX5_REFORMAT_TYPE_DEL_PSP_TUNNEL = 0xe, 7185 7164 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 7186 7165 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 7187 7166 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, ··· 7310 7285 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 7311 7286 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 7312 7287 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 7288 + MLX5_ACTION_IN_FIELD_PSP_SYNDROME = 0x71, 7313 7289 }; 7314 7290 7315 7291 struct mlx5_ifc_alloc_modify_header_context_out_bits { ··· 13105 13079 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1, 13106 13080 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2, 13107 13081 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4, 13082 + MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_PSP = 0x6, 13108 13083 }; 13109 13084 13110 13085 struct mlx5_ifc_tls_static_params_bits { ··· 13521 13494 enum mlx5e_pcie_cong_event_mod_field { 13522 13495 MLX5_PCIE_CONG_EVENT_MOD_EVENT_EN = BIT(0), 13523 13496 MLX5_PCIE_CONG_EVENT_MOD_THRESH = BIT(2), 13497 + }; 13498 + 13499 + struct mlx5_ifc_psp_rotate_key_in_bits { 13500 + u8 opcode[0x10]; 13501 + u8 uid[0x10]; 13502 + 13503 + u8 reserved_at_20[0x10]; 13504 + u8 op_mod[0x10]; 13505 + 13506 + u8 reserved_at_40[0x40]; 13507 + }; 13508 + 13509 + struct mlx5_ifc_psp_rotate_key_out_bits { 13510 + u8 status[0x8]; 13511 + u8 reserved_at_8[0x18]; 13512 + 13513 + u8 syndrome[0x20]; 13514 + 13515 + u8 reserved_at_40[0x40]; 13516 + }; 13517 + 13518 + enum mlx5_psp_gen_spi_in_key_size { 13519 + MLX5_PSP_GEN_SPI_IN_KEY_SIZE_128 = 0x0, 13520 + MLX5_PSP_GEN_SPI_IN_KEY_SIZE_256 = 0x1, 13521 + }; 13522 + 13523 + struct mlx5_ifc_key_spi_bits { 13524 + u8 spi[0x20]; 13525 + 13526 + u8 reserved_at_20[0x60]; 13527 + 13528 + u8 key[8][0x20]; 13529 + }; 13530 + 13531 + struct mlx5_ifc_psp_gen_spi_in_bits { 13532 + u8 opcode[0x10]; 13533 + u8 uid[0x10]; 13534 + 13535 + u8 reserved_at_20[0x10]; 13536 + u8 op_mod[0x10]; 13537 + 13538 + u8 reserved_at_40[0x20]; 13539 + 13540 + u8 key_size[0x2]; 13541 + u8 reserved_at_62[0xe]; 13542 + u8 num_of_spi[0x10]; 13543 + }; 13544 + 13545 + struct mlx5_ifc_psp_gen_spi_out_bits { 13546 + u8 status[0x8]; 13547 + u8 reserved_at_8[0x18]; 13548 + 13549 + u8 syndrome[0x20]; 13550 + 13551 + u8 reserved_at_40[0x10]; 13552 + u8 num_of_spi[0x10]; 13553 + 13554 + u8 reserved_at_60[0x20]; 13555 + 13556 + struct mlx5_ifc_key_spi_bits key_spi[]; 13524 13557 }; 13525 13558 13526 13559 #endif /* MLX5_IFC_H */

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