Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm: Drop msm_read/writel
Totally useless.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Andrew Halaney <ahalaney@redhat.com>
Patchwork: https://patchwork.freedesktop.org/patch/588804/
Link: https://lore.kernel.org/r/20240410-topic-msm_rw-v1-1-e1fede9ffaba@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
authored by
Konrad Dybcio
and committed by
Dmitry Baryshkov
0efadfb0
b662ade1
+42
-45
+1
-1
drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+1
-1
drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+6
-6
drivers/gpu/drm/msm/adreno/a6xx_gmu.h
+6
-6
drivers/gpu/drm/msm/adreno/a6xx_gmu.h
···
103
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static inline u32 gmu_read(struct a6xx_gmu *gmu, u32 offset)
105
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{
106
-
return msm_readl(gmu->mmio + (offset << 2));
106
+
return readl(gmu->mmio + (offset << 2));
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}
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static inline void gmu_write(struct a6xx_gmu *gmu, u32 offset, u32 value)
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{
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-
msm_writel(value, gmu->mmio + (offset << 2));
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+
writel(value, gmu->mmio + (offset << 2));
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}
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static inline void
···
131
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{
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u64 val;
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-
val = (u64) msm_readl(gmu->mmio + (lo << 2));
135
-
val |= ((u64) msm_readl(gmu->mmio + (hi << 2)) << 32);
134
+
val = (u64) readl(gmu->mmio + (lo << 2));
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+
val |= ((u64) readl(gmu->mmio + (hi << 2)) << 32);
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return val;
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}
···
143
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static inline u32 gmu_read_rscc(struct a6xx_gmu *gmu, u32 offset)
145
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{
146
-
return msm_readl(gmu->rscc + (offset << 2));
146
+
return readl(gmu->rscc + (offset << 2));
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}
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static inline void gmu_write_rscc(struct a6xx_gmu *gmu, u32 offset, u32 value)
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{
151
-
msm_writel(value, gmu->rscc + (offset << 2));
151
+
writel(value, gmu->rscc + (offset << 2));
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}
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#define gmu_poll_timeout_rscc(gmu, addr, val, cond, interval, timeout) \
+2
-2
drivers/gpu/drm/msm/adreno/a6xx_gpu.h
+2
-2
drivers/gpu/drm/msm/adreno/a6xx_gpu.h
···
69
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70
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static inline u32 a6xx_llc_read(struct a6xx_gpu *a6xx_gpu, u32 reg)
71
71
{
72
-
return msm_readl(a6xx_gpu->llc_mmio + (reg << 2));
72
+
return readl(a6xx_gpu->llc_mmio + (reg << 2));
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}
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static inline void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 value)
76
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{
77
-
msm_writel(value, a6xx_gpu->llc_mmio + (reg << 2));
77
+
writel(value, a6xx_gpu->llc_mmio + (reg << 2));
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}
79
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#define shadowptr(_a6xx_gpu, _ring) ((_a6xx_gpu)->shadow_iova + \
+2
-2
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
+2
-2
drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
···
192
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}
193
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#define cxdbg_write(ptr, offset, val) \
195
-
msm_writel((val), (ptr) + ((offset) << 2))
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+
writel((val), (ptr) + ((offset) << 2))
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#define cxdbg_read(ptr, offset) \
198
-
msm_readl((ptr) + ((offset) << 2))
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+
readl((ptr) + ((offset) << 2))
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/* read a value from the CX debug bus */
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static int cx_debugbus_read(void __iomem *cxdbg, u32 block, u32 offset,
+2
-2
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h
+2
-2
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.h
···
44
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static inline void mdp4_write(struct mdp4_kms *mdp4_kms, u32 reg, u32 data)
46
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{
47
-
msm_writel(data, mdp4_kms->mmio + reg);
47
+
writel(data, mdp4_kms->mmio + reg);
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}
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static inline u32 mdp4_read(struct mdp4_kms *mdp4_kms, u32 reg)
51
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{
52
-
return msm_readl(mdp4_kms->mmio + reg);
52
+
return readl(mdp4_kms->mmio + reg);
53
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}
54
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static inline uint32_t pipe2flush(enum mdp4_pipe pipe)
+2
-2
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h
+2
-2
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h
···
171
171
static inline void mdp5_write(struct mdp5_kms *mdp5_kms, u32 reg, u32 data)
172
172
{
173
173
WARN_ON(mdp5_kms->enable_count <= 0);
174
-
msm_writel(data, mdp5_kms->mmio + reg);
174
+
writel(data, mdp5_kms->mmio + reg);
175
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}
176
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static inline u32 mdp5_read(struct mdp5_kms *mdp5_kms, u32 reg)
178
178
{
179
179
WARN_ON(mdp5_kms->enable_count <= 0);
180
-
return msm_readl(mdp5_kms->mmio + reg);
180
+
return readl(mdp5_kms->mmio + reg);
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}
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static inline const char *stage2name(enum mdp_mixer_stage_id stage)
+5
-5
drivers/gpu/drm/msm/dsi/dsi_host.c
+5
-5
drivers/gpu/drm/msm/dsi/dsi_host.c
···
55
55
* scratch register which we never touch)
56
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*/
57
57
58
-
ver = msm_readl(base + REG_DSI_VERSION);
58
+
ver = readl(base + REG_DSI_VERSION);
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if (ver) {
60
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/* older dsi host, there is no register shift */
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ver = FIELD(ver, DSI_VERSION_MAJOR);
···
73
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* registers are shifted down, read DSI_VERSION again with
74
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* the shifted offset
75
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*/
76
-
ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION);
76
+
ver = readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION);
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ver = FIELD(ver, DSI_VERSION_MAJOR);
78
78
if (ver == MSM_DSI_VER_MAJOR_6G) {
79
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/* 6G version */
80
80
*major = ver;
81
-
*minor = msm_readl(base + REG_DSI_6G_HW_VERSION);
81
+
*minor = readl(base + REG_DSI_6G_HW_VERSION);
82
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return 0;
83
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} else {
84
84
return -EINVAL;
···
186
186
187
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static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg)
188
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{
189
-
return msm_readl(msm_host->ctrl_base + reg);
189
+
return readl(msm_host->ctrl_base + reg);
190
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}
191
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static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data)
192
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{
193
-
msm_writel(data, msm_host->ctrl_base + reg);
193
+
writel(data, msm_host->ctrl_base + reg);
194
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}
195
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static const struct msm_dsi_cfg_handler *dsi_get_config(
+4
-4
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+4
-4
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
···
12
12
13
13
#include "dsi.h"
14
14
15
-
#define dsi_phy_read(offset) msm_readl((offset))
16
-
#define dsi_phy_write(offset, data) msm_writel((data), (offset))
17
-
#define dsi_phy_write_udelay(offset, data, delay_us) { msm_writel((data), (offset)); udelay(delay_us); }
18
-
#define dsi_phy_write_ndelay(offset, data, delay_ns) { msm_writel((data), (offset)); ndelay(delay_ns); }
15
+
#define dsi_phy_read(offset) readl((offset))
16
+
#define dsi_phy_write(offset, data) writel((data), (offset))
17
+
#define dsi_phy_write_udelay(offset, data, delay_us) { writel((data), (offset)); udelay(delay_us); }
18
+
#define dsi_phy_write_ndelay(offset, data, delay_ns) { writel((data), (offset)); ndelay(delay_ns); }
19
19
20
20
struct msm_dsi_phy_ops {
21
21
int (*pll_init)(struct msm_dsi_phy *phy);
+5
-5
drivers/gpu/drm/msm/hdmi/hdmi.h
+5
-5
drivers/gpu/drm/msm/hdmi/hdmi.h
···
115
115
116
116
static inline void hdmi_write(struct hdmi *hdmi, u32 reg, u32 data)
117
117
{
118
-
msm_writel(data, hdmi->mmio + reg);
118
+
writel(data, hdmi->mmio + reg);
119
119
}
120
120
121
121
static inline u32 hdmi_read(struct hdmi *hdmi, u32 reg)
122
122
{
123
-
return msm_readl(hdmi->mmio + reg);
123
+
return readl(hdmi->mmio + reg);
124
124
}
125
125
126
126
static inline u32 hdmi_qfprom_read(struct hdmi *hdmi, u32 reg)
127
127
{
128
-
return msm_readl(hdmi->qfprom_mmio + reg);
128
+
return readl(hdmi->qfprom_mmio + reg);
129
129
}
130
130
131
131
/*
···
166
166
167
167
static inline void hdmi_phy_write(struct hdmi_phy *phy, u32 reg, u32 data)
168
168
{
169
-
msm_writel(data, phy->mmio + reg);
169
+
writel(data, phy->mmio + reg);
170
170
}
171
171
172
172
static inline u32 hdmi_phy_read(struct hdmi_phy *phy, u32 reg)
173
173
{
174
-
return msm_readl(phy->mmio + reg);
174
+
return readl(phy->mmio + reg);
175
175
}
176
176
177
177
int msm_hdmi_phy_resource_enable(struct hdmi_phy *phy);
+3
-3
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
+3
-3
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
···
86
86
static inline void hdmi_pll_write(struct hdmi_pll_8996 *pll, int offset,
87
87
u32 data)
88
88
{
89
-
msm_writel(data, pll->mmio_qserdes_com + offset);
89
+
writel(data, pll->mmio_qserdes_com + offset);
90
90
}
91
91
92
92
static inline u32 hdmi_pll_read(struct hdmi_pll_8996 *pll, int offset)
93
93
{
94
-
return msm_readl(pll->mmio_qserdes_com + offset);
94
+
return readl(pll->mmio_qserdes_com + offset);
95
95
}
96
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97
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static inline void hdmi_tx_chan_write(struct hdmi_pll_8996 *pll, int channel,
98
98
int offset, int data)
99
99
{
100
-
msm_writel(data, pll->mmio_qserdes_tx[channel] + offset);
100
+
writel(data, pll->mmio_qserdes_tx[channel] + offset);
101
101
}
102
102
103
103
static inline u32 pll_get_cpctrl(u64 frac_start, unsigned long ref_clk,
+2
-2
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
+2
-2
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
···
236
236
237
237
static inline void pll_write(struct hdmi_pll_8960 *pll, u32 reg, u32 data)
238
238
{
239
-
msm_writel(data, pll->mmio + reg);
239
+
writel(data, pll->mmio + reg);
240
240
}
241
241
242
242
static inline u32 pll_read(struct hdmi_pll_8960 *pll, u32 reg)
243
243
{
244
-
return msm_readl(pll->mmio + reg);
244
+
return readl(pll->mmio + reg);
245
245
}
246
246
247
247
static inline struct hdmi_phy *pll_get_phy(struct hdmi_pll_8960 *pll)
+2
-5
drivers/gpu/drm/msm/msm_drv.h
+2
-5
drivers/gpu/drm/msm/msm_drv.h
···
488
488
489
489
struct icc_path *msm_icc_get(struct device *dev, const char *name);
490
490
491
-
#define msm_writel(data, addr) writel((data), (addr))
492
-
#define msm_readl(addr) readl((addr))
493
-
494
491
static inline void msm_rmw(void __iomem *addr, u32 mask, u32 or)
495
492
{
496
-
u32 val = msm_readl(addr);
493
+
u32 val = readl(addr);
497
494
498
495
val &= ~mask;
499
-
msm_writel(val | or, addr);
496
+
writel(val | or, addr);
500
497
}
501
498
502
499
/**
+6
-6
drivers/gpu/drm/msm/msm_gpu.h
+6
-6
drivers/gpu/drm/msm/msm_gpu.h
···
555
555
556
556
static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data)
557
557
{
558
-
msm_writel(data, gpu->mmio + (reg << 2));
558
+
writel(data, gpu->mmio + (reg << 2));
559
559
}
560
560
561
561
static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg)
562
562
{
563
-
return msm_readl(gpu->mmio + (reg << 2));
563
+
return readl(gpu->mmio + (reg << 2));
564
564
}
565
565
566
566
static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or)
···
586
586
* when the lo is read, so make sure to read the lo first to trigger
587
587
* that
588
588
*/
589
-
val = (u64) msm_readl(gpu->mmio + (reg << 2));
590
-
val |= ((u64) msm_readl(gpu->mmio + ((reg + 1) << 2)) << 32);
589
+
val = (u64) readl(gpu->mmio + (reg << 2));
590
+
val |= ((u64) readl(gpu->mmio + ((reg + 1) << 2)) << 32);
591
591
592
592
return val;
593
593
}
···
595
595
static inline void gpu_write64(struct msm_gpu *gpu, u32 reg, u64 val)
596
596
{
597
597
/* Why not a writeq here? Read the screed above */
598
-
msm_writel(lower_32_bits(val), gpu->mmio + (reg << 2));
599
-
msm_writel(upper_32_bits(val), gpu->mmio + ((reg + 1) << 2));
598
+
writel(lower_32_bits(val), gpu->mmio + (reg << 2));
599
+
writel(upper_32_bits(val), gpu->mmio + ((reg + 1) << 2));
600
600
}
601
601
602
602
int msm_gpu_pm_suspend(struct msm_gpu *gpu);