Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'soc-drivers-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC driver updates from Arnd Bergmann:
"The main change this time was the introduction of the drivers/genpd
subsystem that gets split out from drivers/soc to keep common
functionality together.
The SCMI driver subsystem gets an update to version 3.2 of the
specification. There are also updates to memory, reset and other
firmware drivers.
On the soc driver side, the updates are mostly cleanups across a
number of Arm platforms. On driver for loongarch adds power management
for DT based systems, another driver is for HiSilicon's Arm server
chips with their HCCS system health interface.
The remaining updates for the most part add support for additional
hardware in existing drivers or contain minor cleanups. Most of these
are for the Qualcomm Snapdragon platform"
* tag 'soc-drivers-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (136 commits)
bus: fsl-mc: Use common ranges functions
soc: kunpeng_hccs: fix some sparse warnings about incorrect type
soc: loongson2_pm: add power management support
soc: dt-bindings: add loongson-2 pm
soc: rockchip: grf: Fix SDMMC not working on RK3588 with bus-width > 1
genpd: rockchip: Add PD_VO entry for rv1126
bus: ti-sysc: Fix cast to enum warning
soc: kunpeng_hccs: add MAILBOX dependency
MAINTAINERS: remove OXNAS entry
dt-bindings: interrupt-controller: arm,versatile-fpga-irq: mark oxnas compatible as deprecated
irqchip: irq-versatile-fpga: remove obsolete oxnas compatible
soc: qcom: aoss: Tidy up qmp_send() callers
soc: qcom: aoss: Format string in qmp_send()
soc: qcom: aoss: Move length requirements from caller
soc: kunpeng_hccs: fix size_t format string
soc: ti: k3-socinfo.c: Add JTAG ID for AM62PX
dt-bindings: firmware: qcom: scm: Updating VMID list
firmware: imx: scu-irq: support identifying SCU wakeup source from sysfs
firmware: imx: scu-irq: enlarge the IMX_SC_IRQ_NUM_GROUP
firmware: imx: scu-irq: add imx_scu_irq_get_status
...
+3827
-1113
+81
Documentation/ABI/testing/sysfs-devices-platform-kunpeng_hccs
+81
Documentation/ABI/testing/sysfs-devices-platform-kunpeng_hccs
···
1
+
What: /sys/devices/platform/HISI04Bx:00/chipX/all_linked
2
+
What: /sys/devices/platform/HISI04Bx:00/chipX/linked_full_lane
3
+
What: /sys/devices/platform/HISI04Bx:00/chipX/crc_err_cnt
4
+
Date: November 2023
5
+
KernelVersion: 6.6
6
+
Contact: Huisong Li <lihuisong@huawei.org>
7
+
Description:
8
+
The /sys/devices/platform/HISI04Bx:00/chipX/ directory
9
+
contains read-only attributes exposing some summarization
10
+
information of all HCCS ports under a specified chip.
11
+
The X in 'chipX' indicates the Xth chip on platform.
12
+
13
+
There are following attributes in this directory:
14
+
15
+
================= ==== =========================================
16
+
all_linked: (RO) if all enabled ports on this chip are
17
+
linked (bool).
18
+
linked_full_lane: (RO) if all linked ports on this chip are full
19
+
lane (bool).
20
+
crc_err_cnt: (RO) total CRC err count for all ports on this
21
+
chip.
22
+
================= ==== =========================================
23
+
24
+
What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/all_linked
25
+
What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/linked_full_lane
26
+
What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/crc_err_cnt
27
+
Date: November 2023
28
+
KernelVersion: 6.6
29
+
Contact: Huisong Li <lihuisong@huawei.org>
30
+
Description:
31
+
The /sys/devices/platform/HISI04Bx:00/chipX/dieY/ directory
32
+
contains read-only attributes exposing some summarization
33
+
information of all HCCS ports under a specified die.
34
+
The Y in 'dieY' indicates the hardware id of the die on chip who
35
+
has chip id X.
36
+
37
+
There are following attributes in this directory:
38
+
39
+
================= ==== =========================================
40
+
all_linked: (RO) if all enabled ports on this die are
41
+
linked (bool).
42
+
linked_full_lane: (RO) if all linked ports on this die are full
43
+
lane (bool).
44
+
crc_err_cnt: (RO) total CRC err count for all ports on this
45
+
die.
46
+
================= ==== =========================================
47
+
48
+
What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/type
49
+
What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/lane_mode
50
+
What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/enable
51
+
What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/cur_lane_num
52
+
What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/link_fsm
53
+
What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/lane_mask
54
+
What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/crc_err_cnt
55
+
Date: November 2023
56
+
KernelVersion: 6.6
57
+
Contact: Huisong Li <lihuisong@huawei.org>
58
+
Description:
59
+
The /sys/devices/platform/HISI04Bx/chipX/dieX/hccsN/ directory
60
+
contains read-only attributes exposing information about
61
+
a HCCS port. The N value in 'hccsN' indicates this port id.
62
+
The X in 'chipX' indicates the ID of the chip to which the
63
+
HCCS port belongs. For example, X ranges from to 'n - 1' if the
64
+
chip number on platform is n.
65
+
The Y in 'dieY' indicates the hardware id of the die to which
66
+
the hccs port belongs.
67
+
Note: type, lane_mode and enable are fixed attributes on running
68
+
platform.
69
+
70
+
The HCCS port have the following attributes:
71
+
72
+
============= ==== =============================================
73
+
type: (RO) port type (string), e.g. HCCS-v1 -> H32
74
+
lane_mode: (RO) the lane mode of this port (string), e.g. x8
75
+
enable: (RO) indicate if this port is enabled (bool).
76
+
cur_lane_num: (RO) current lane number of this port.
77
+
link_fsm: (RO) link finite state machine of this port.
78
+
lane_mask: (RO) current lane mask of this port, every bit
79
+
indicates a lane.
80
+
crc_err_cnt: (RO) CRC err count on this port.
81
+
============= ==== =============================================
+2
-2
Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
+2
-2
Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
···
82
82
examples:
83
83
- |
84
84
#include <dt-bindings/clock/qcom,rpmh.h>
85
-
#include <dt-bindings/power/qcom-rpmpd.h>
85
+
#include <dt-bindings/power/qcom,rpmhpd.h>
86
86
clock-controller@af00000 {
87
87
compatible = "qcom,sm8250-dispcc";
88
88
reg = <0x0af00000 0x10000>;
···
103
103
#clock-cells = <1>;
104
104
#reset-cells = <1>;
105
105
#power-domain-cells = <1>;
106
-
power-domains = <&rpmhpd SM8250_MMCX>;
106
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
107
107
required-opps = <&rpmhpd_opp_low_svs>;
108
108
};
109
109
...
+2
-2
Documentation/devicetree/bindings/clock/qcom,sm8350-videocc.yaml
+2
-2
Documentation/devicetree/bindings/clock/qcom,sm8350-videocc.yaml
···
51
51
examples:
52
52
- |
53
53
#include <dt-bindings/clock/qcom,rpmh.h>
54
-
#include <dt-bindings/power/qcom-rpmpd.h>
54
+
#include <dt-bindings/power/qcom,rpmhpd.h>
55
55
56
56
clock-controller@abf0000 {
57
57
compatible = "qcom,sm8350-videocc";
···
59
59
clocks = <&rpmhcc RPMH_CXO_CLK>,
60
60
<&rpmhcc RPMH_CXO_CLK_A>,
61
61
<&sleep_clk>;
62
-
power-domains = <&rpmhpd SM8350_MMCX>;
62
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
63
63
required-opps = <&rpmhpd_opp_low_svs>;
64
64
#clock-cells = <1>;
65
65
#reset-cells = <1>;
+2
-2
Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
+2
-2
Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
···
64
64
- |
65
65
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
66
66
#include <dt-bindings/clock/qcom,rpmh.h>
67
-
#include <dt-bindings/power/qcom-rpmpd.h>
67
+
#include <dt-bindings/power/qcom,rpmhpd.h>
68
68
clock-controller@ade0000 {
69
69
compatible = "qcom,sm8450-camcc";
70
70
reg = <0xade0000 0x20000>;
···
72
72
<&rpmhcc RPMH_CXO_CLK>,
73
73
<&rpmhcc RPMH_CXO_CLK_A>,
74
74
<&sleep_clk>;
75
-
power-domains = <&rpmhpd SM8450_MMCX>;
75
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
76
76
required-opps = <&rpmhpd_opp_low_svs>;
77
77
#clock-cells = <1>;
78
78
#reset-cells = <1>;
+2
-2
Documentation/devicetree/bindings/clock/qcom,sm8450-dispcc.yaml
+2
-2
Documentation/devicetree/bindings/clock/qcom,sm8450-dispcc.yaml
···
76
76
- |
77
77
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
78
78
#include <dt-bindings/clock/qcom,rpmh.h>
79
-
#include <dt-bindings/power/qcom-rpmpd.h>
79
+
#include <dt-bindings/power/qcom,rpmhpd.h>
80
80
clock-controller@af00000 {
81
81
compatible = "qcom,sm8450-dispcc";
82
82
reg = <0x0af00000 0x10000>;
···
91
91
#clock-cells = <1>;
92
92
#reset-cells = <1>;
93
93
#power-domain-cells = <1>;
94
-
power-domains = <&rpmhpd SM8450_MMCX>;
94
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
95
95
required-opps = <&rpmhpd_opp_low_svs>;
96
96
};
97
97
...
+2
-2
Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
+2
-2
Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
···
64
64
- |
65
65
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
66
66
#include <dt-bindings/clock/qcom,rpmh.h>
67
-
#include <dt-bindings/power/qcom-rpmpd.h>
67
+
#include <dt-bindings/power/qcom,rpmhpd.h>
68
68
videocc: clock-controller@aaf0000 {
69
69
compatible = "qcom,sm8450-videocc";
70
70
reg = <0x0aaf0000 0x10000>;
71
71
clocks = <&rpmhcc RPMH_CXO_CLK>,
72
72
<&gcc GCC_VIDEO_AHB_CLK>;
73
-
power-domains = <&rpmhpd SM8450_MMCX>;
73
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
74
74
required-opps = <&rpmhpd_opp_low_svs>;
75
75
#clock-cells = <1>;
76
76
#reset-cells = <1>;
+2
-2
Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml
+2
-2
Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml
···
76
76
- |
77
77
#include <dt-bindings/clock/qcom,sm8550-gcc.h>
78
78
#include <dt-bindings/clock/qcom,rpmh.h>
79
-
#include <dt-bindings/power/qcom-rpmpd.h>
79
+
#include <dt-bindings/power/qcom,rpmhpd.h>
80
80
clock-controller@af00000 {
81
81
compatible = "qcom,sm8550-dispcc";
82
82
reg = <0x0af00000 0x10000>;
···
99
99
#clock-cells = <1>;
100
100
#reset-cells = <1>;
101
101
#power-domain-cells = <1>;
102
-
power-domains = <&rpmhpd SM8550_MMCX>;
102
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
103
103
required-opps = <&rpmhpd_opp_low_svs>;
104
104
};
105
105
...
+2
-2
Documentation/devicetree/bindings/clock/qcom,videocc.yaml
+2
-2
Documentation/devicetree/bindings/clock/qcom,videocc.yaml
···
124
124
examples:
125
125
- |
126
126
#include <dt-bindings/clock/qcom,rpmh.h>
127
-
#include <dt-bindings/power/qcom-rpmpd.h>
127
+
#include <dt-bindings/power/qcom,rpmhpd.h>
128
128
clock-controller@ab00000 {
129
129
compatible = "qcom,sdm845-videocc";
130
130
reg = <0x0ab00000 0x10000>;
···
133
133
#clock-cells = <1>;
134
134
#reset-cells = <1>;
135
135
#power-domain-cells = <1>;
136
-
power-domains = <&rpmhpd SM8250_MMCX>;
136
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
137
137
required-opps = <&rpmhpd_opp_low_svs>;
138
138
};
139
139
...
+2
-2
Documentation/devicetree/bindings/display/msm/qcom,sm8250-dpu.yaml
+2
-2
Documentation/devicetree/bindings/display/msm/qcom,sm8250-dpu.yaml
···
54
54
#include <dt-bindings/clock/qcom,gcc-sm8250.h>
55
55
#include <dt-bindings/interrupt-controller/arm-gic.h>
56
56
#include <dt-bindings/interconnect/qcom,sm8250.h>
57
-
#include <dt-bindings/power/qcom-rpmpd.h>
57
+
#include <dt-bindings/power/qcom,rpmhpd.h>
58
58
59
59
display-controller@ae01000 {
60
60
compatible = "qcom,sm8250-dpu";
···
72
72
assigned-clock-rates = <19200000>;
73
73
74
74
operating-points-v2 = <&mdp_opp_table>;
75
-
power-domains = <&rpmhpd SM8250_MMCX>;
75
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
76
76
77
77
interrupt-parent = <&mdss>;
78
78
interrupts = <0>;
+4
-4
Documentation/devicetree/bindings/display/msm/qcom,sm8250-mdss.yaml
+4
-4
Documentation/devicetree/bindings/display/msm/qcom,sm8250-mdss.yaml
···
76
76
#include <dt-bindings/clock/qcom,rpmh.h>
77
77
#include <dt-bindings/interrupt-controller/arm-gic.h>
78
78
#include <dt-bindings/interconnect/qcom,sm8250.h>
79
-
#include <dt-bindings/power/qcom-rpmpd.h>
79
+
#include <dt-bindings/power/qcom,rpmhpd.h>
80
80
81
81
display-subsystem@ae00000 {
82
82
compatible = "qcom,sm8250-mdss";
···
121
121
assigned-clock-rates = <19200000>;
122
122
123
123
operating-points-v2 = <&mdp_opp_table>;
124
-
power-domains = <&rpmhpd SM8250_MMCX>;
124
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
125
125
126
126
interrupt-parent = <&mdss>;
127
127
interrupts = <0>;
···
196
196
assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
197
197
198
198
operating-points-v2 = <&dsi_opp_table>;
199
-
power-domains = <&rpmhpd SM8250_MMCX>;
199
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
200
200
201
201
phys = <&dsi0_phy>;
202
202
phy-names = "dsi";
···
286
286
assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
287
287
288
288
operating-points-v2 = <&dsi_opp_table>;
289
-
power-domains = <&rpmhpd SM8250_MMCX>;
289
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
290
290
291
291
phys = <&dsi1_phy>;
292
292
phy-names = "dsi";
+2
-2
Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
+2
-2
Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml
···
51
51
#include <dt-bindings/clock/qcom,gcc-sm8350.h>
52
52
#include <dt-bindings/interrupt-controller/arm-gic.h>
53
53
#include <dt-bindings/interconnect/qcom,sm8350.h>
54
-
#include <dt-bindings/power/qcom-rpmpd.h>
54
+
#include <dt-bindings/power/qcom,rpmhpd.h>
55
55
56
56
display-controller@ae01000 {
57
57
compatible = "qcom,sm8350-dpu";
···
76
76
assigned-clock-rates = <19200000>;
77
77
78
78
operating-points-v2 = <&mdp_opp_table>;
79
-
power-domains = <&rpmhpd SM8350_MMCX>;
79
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
80
80
81
81
interrupt-parent = <&mdss>;
82
82
interrupts = <0>;
+3
-3
Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
+3
-3
Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml
···
81
81
#include <dt-bindings/clock/qcom,rpmh.h>
82
82
#include <dt-bindings/interrupt-controller/arm-gic.h>
83
83
#include <dt-bindings/interconnect/qcom,sm8350.h>
84
-
#include <dt-bindings/power/qcom-rpmpd.h>
84
+
#include <dt-bindings/power/qcom,rpmhpd.h>
85
85
86
86
display-subsystem@ae00000 {
87
87
compatible = "qcom,sm8350-mdss";
···
134
134
assigned-clock-rates = <19200000>;
135
135
136
136
operating-points-v2 = <&mdp_opp_table>;
137
-
power-domains = <&rpmhpd SM8350_MMCX>;
137
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
138
138
139
139
interrupt-parent = <&mdss>;
140
140
interrupts = <0>;
···
203
203
<&mdss_dsi0_phy 1>;
204
204
205
205
operating-points-v2 = <&dsi_opp_table>;
206
-
power-domains = <&rpmhpd SM8350_MMCX>;
206
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
207
207
208
208
phys = <&mdss_dsi0_phy>;
209
209
+2
-2
Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml
+2
-2
Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml
···
58
58
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
59
59
#include <dt-bindings/interrupt-controller/arm-gic.h>
60
60
#include <dt-bindings/interconnect/qcom,sm8450.h>
61
-
#include <dt-bindings/power/qcom-rpmpd.h>
61
+
#include <dt-bindings/power/qcom,rpmhpd.h>
62
62
63
63
display-controller@ae01000 {
64
64
compatible = "qcom,sm8450-dpu";
···
83
83
assigned-clock-rates = <19200000>;
84
84
85
85
operating-points-v2 = <&mdp_opp_table>;
86
-
power-domains = <&rpmhpd SM8450_MMCX>;
86
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
87
87
88
88
interrupt-parent = <&mdss>;
89
89
interrupts = <0>;
+4
-4
Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml
+4
-4
Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml
···
76
76
#include <dt-bindings/clock/qcom,rpmh.h>
77
77
#include <dt-bindings/interrupt-controller/arm-gic.h>
78
78
#include <dt-bindings/interconnect/qcom,sm8450.h>
79
-
#include <dt-bindings/power/qcom-rpmpd.h>
79
+
#include <dt-bindings/power/qcom,rpmhpd.h>
80
80
81
81
display-subsystem@ae00000 {
82
82
compatible = "qcom,sm8450-mdss";
···
130
130
assigned-clock-rates = <19200000>;
131
131
132
132
operating-points-v2 = <&mdp_opp_table>;
133
-
power-domains = <&rpmhpd SM8450_MMCX>;
133
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
134
134
135
135
interrupt-parent = <&mdss>;
136
136
interrupts = <0>;
···
210
210
assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
211
211
212
212
operating-points-v2 = <&dsi_opp_table>;
213
-
power-domains = <&rpmhpd SM8450_MMCX>;
213
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
214
214
215
215
phys = <&dsi0_phy>;
216
216
phy-names = "dsi";
···
305
305
assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
306
306
307
307
operating-points-v2 = <&dsi_opp_table>;
308
-
power-domains = <&rpmhpd SM8450_MMCX>;
308
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
309
309
310
310
phys = <&dsi1_phy>;
311
311
phy-names = "dsi";
+2
-2
Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.yaml
+2
-2
Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.yaml
···
57
57
#include <dt-bindings/clock/qcom,sm8550-dispcc.h>
58
58
#include <dt-bindings/clock/qcom,sm8550-gcc.h>
59
59
#include <dt-bindings/interrupt-controller/arm-gic.h>
60
-
#include <dt-bindings/power/qcom-rpmpd.h>
60
+
#include <dt-bindings/power/qcom,rpmhpd.h>
61
61
62
62
display-controller@ae01000 {
63
63
compatible = "qcom,sm8550-dpu";
···
82
82
assigned-clock-rates = <19200000>;
83
83
84
84
operating-points-v2 = <&mdp_opp_table>;
85
-
power-domains = <&rpmhpd SM8550_MMCX>;
85
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
86
86
87
87
interrupt-parent = <&mdss>;
88
88
interrupts = <0>;
+4
-4
Documentation/devicetree/bindings/display/msm/qcom,sm8550-mdss.yaml
+4
-4
Documentation/devicetree/bindings/display/msm/qcom,sm8550-mdss.yaml
···
76
76
#include <dt-bindings/clock/qcom,rpmh.h>
77
77
#include <dt-bindings/interrupt-controller/arm-gic.h>
78
78
#include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
79
-
#include <dt-bindings/power/qcom-rpmpd.h>
79
+
#include <dt-bindings/power/qcom,rpmhpd.h>
80
80
81
81
display-subsystem@ae00000 {
82
82
compatible = "qcom,sm8550-mdss";
···
130
130
assigned-clock-rates = <19200000>;
131
131
132
132
operating-points-v2 = <&mdp_opp_table>;
133
-
power-domains = <&rpmhpd SM8550_MMCX>;
133
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
134
134
135
135
interrupt-parent = <&mdss>;
136
136
interrupts = <0>;
···
205
205
assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
206
206
207
207
operating-points-v2 = <&dsi_opp_table>;
208
-
power-domains = <&rpmhpd SM8550_MMCX>;
208
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
209
209
210
210
phys = <&dsi0_phy>;
211
211
phy-names = "dsi";
···
294
294
assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
295
295
296
296
operating-points-v2 = <&dsi_opp_table>;
297
-
power-domains = <&rpmhpd SM8550_MMCX>;
297
+
power-domains = <&rpmhpd RPMHPD_MMCX>;
298
298
299
299
phys = <&dsi1_phy>;
300
300
phy-names = "dsi";
+1
Documentation/devicetree/bindings/firmware/qcom,scm.yaml
+1
Documentation/devicetree/bindings/firmware/qcom,scm.yaml
+3
-1
Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.txt
+3
-1
Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.txt
···
6
6
instance can handle up to 32 interrupts.
7
7
8
8
Required properties:
9
-
- compatible: "arm,versatile-fpga-irq" or "oxsemi,ox810se-rps-irq"
9
+
- compatible: "arm,versatile-fpga-irq"
10
10
- interrupt-controller: Identifies the node as an interrupt controller
11
11
- #interrupt-cells: The number of cells to define the interrupts. Must be 1
12
12
as the FPGA IRQ controller has no configuration options for interrupt
···
18
18
the interrupts are valid. Unconnected/unused lines are set to 0, and
19
19
the system till not make it possible for devices to request these
20
20
interrupts.
21
+
22
+
The "oxsemi,ox810se-rps-irq" compatible is deprecated.
21
23
22
24
Example:
23
25
+2
-2
Documentation/devicetree/bindings/media/qcom,sm8250-venus.yaml
+2
-2
Documentation/devicetree/bindings/media/qcom,sm8250-venus.yaml
···
106
106
#include <dt-bindings/clock/qcom,videocc-sm8250.h>
107
107
#include <dt-bindings/interconnect/qcom,sm8250.h>
108
108
#include <dt-bindings/clock/qcom,gcc-sm8250.h>
109
-
#include <dt-bindings/power/qcom-rpmpd.h>
109
+
#include <dt-bindings/power/qcom,rpmhpd.h>
110
110
111
111
venus: video-codec@aa00000 {
112
112
compatible = "qcom,sm8250-venus";
···
114
114
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
115
115
power-domains = <&videocc MVS0C_GDSC>,
116
116
<&videocc MVS0_GDSC>,
117
-
<&rpmhpd SM8250_MX>;
117
+
<&rpmhpd RPMHPD_MX>;
118
118
power-domain-names = "venus", "vcodec0", "mx";
119
119
120
120
clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
+1
Documentation/devicetree/bindings/memory-controllers/ingenic,nemc.yaml
+1
Documentation/devicetree/bindings/memory-controllers/ingenic,nemc.yaml
+2
Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml
+2
Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml
+2
-2
Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
+2
-2
Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
···
215
215
#include <dt-bindings/interrupt-controller/arm-gic.h>
216
216
#include <dt-bindings/clock/qcom,gcc-sm8250.h>
217
217
#include <dt-bindings/clock/qcom,rpmh.h>
218
-
#include <dt-bindings/power/qcom-rpmpd.h>
218
+
#include <dt-bindings/power/qcom,rpmhpd.h>
219
219
220
220
sdhc_2: mmc@8804000 {
221
221
compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
···
232
232
iommus = <&apps_smmu 0x4a0 0x0>;
233
233
qcom,dll-config = <0x0007642c>;
234
234
qcom,ddr-config = <0x80040868>;
235
-
power-domains = <&rpmhpd SM8250_CX>;
235
+
power-domains = <&rpmhpd RPMHPD_CX>;
236
236
237
237
operating-points-v2 = <&sdhc2_opp_table>;
238
238
+59
Documentation/devicetree/bindings/net/davicom,dm9000.yaml
+59
Documentation/devicetree/bindings/net/davicom,dm9000.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/net/davicom,dm9000.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Davicom DM9000 Fast Ethernet Controller
8
+
9
+
maintainers:
10
+
- Paul Cercueil <paul@crapouillou.net>
11
+
12
+
properties:
13
+
compatible:
14
+
const: davicom,dm9000
15
+
16
+
reg:
17
+
items:
18
+
- description: Address registers
19
+
- description: Data registers
20
+
21
+
interrupts:
22
+
maxItems: 1
23
+
24
+
davicom,no-eeprom:
25
+
type: boolean
26
+
description: Configuration EEPROM is not available
27
+
28
+
davicom,ext-phy:
29
+
type: boolean
30
+
description: Use external PHY
31
+
32
+
reset-gpios:
33
+
maxItems: 1
34
+
35
+
vcc-supply: true
36
+
37
+
required:
38
+
- compatible
39
+
- reg
40
+
- interrupts
41
+
42
+
allOf:
43
+
- $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
44
+
- $ref: /schemas/net/ethernet-controller.yaml#
45
+
46
+
unevaluatedProperties: false
47
+
48
+
examples:
49
+
- |
50
+
#include <dt-bindings/interrupt-controller/irq.h>
51
+
52
+
ethernet@a8000000 {
53
+
compatible = "davicom,dm9000";
54
+
reg = <0xa8000000 0x2>, <0xa8000002 0x2>;
55
+
interrupt-parent = <&gph1>;
56
+
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
57
+
local-mac-address = [00 00 de ad be ef];
58
+
davicom,no-eeprom;
59
+
};
-27
Documentation/devicetree/bindings/net/davicom-dm9000.txt
-27
Documentation/devicetree/bindings/net/davicom-dm9000.txt
···
1
-
Davicom DM9000 Fast Ethernet controller
2
-
3
-
Required properties:
4
-
- compatible = "davicom,dm9000";
5
-
- reg : physical addresses and sizes of registers, must contain 2 entries:
6
-
first entry : address register,
7
-
second entry : data register.
8
-
- interrupts : interrupt specifier specific to interrupt controller
9
-
10
-
Optional properties:
11
-
- davicom,no-eeprom : Configuration EEPROM is not available
12
-
- davicom,ext-phy : Use external PHY
13
-
- reset-gpios : phandle of gpio that will be used to reset chip during probe
14
-
- vcc-supply : phandle of regulator that will be used to enable power to chip
15
-
16
-
Example:
17
-
18
-
ethernet@18000000 {
19
-
compatible = "davicom,dm9000";
20
-
reg = <0x18000000 0x2 0x18000004 0x2>;
21
-
interrupt-parent = <&gpn>;
22
-
interrupts = <7 4>;
23
-
local-mac-address = [00 00 de ad be ef];
24
-
davicom,no-eeprom;
25
-
reset-gpios = <&gpf 12 GPIO_ACTIVE_LOW>;
26
-
vcc-supply = <ð0_power>;
27
-
};
+2
-1
Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml
+2
-1
Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml
···
12
12
- Jianxin Pan <jianxin.pan@amlogic.com>
13
13
14
14
description: |+
15
-
Secure Power Domains used in Meson A1/C1/S4 SoCs, and should be the child node
15
+
Secure Power Domains used in Meson A1/C1/S4 & C3 SoCs, and should be the child node
16
16
of secure-monitor.
17
17
18
18
properties:
···
20
20
enum:
21
21
- amlogic,meson-a1-pwrc
22
22
- amlogic,meson-s4-pwrc
23
+
- amlogic,c3-pwrc
23
24
24
25
"#power-domain-cells":
25
26
const: 1
+1
Documentation/devicetree/bindings/power/qcom,rpmpd.yaml
+1
Documentation/devicetree/bindings/power/qcom,rpmpd.yaml
-3
Documentation/devicetree/bindings/remoteproc/qcom,glink-edge.yaml
-3
Documentation/devicetree/bindings/remoteproc/qcom,glink-edge.yaml
+1
-1
Documentation/devicetree/bindings/remoteproc/qcom,glink-rpm-edge.yaml
+1
-1
Documentation/devicetree/bindings/remoteproc/qcom,glink-rpm-edge.yaml
+171
Documentation/devicetree/bindings/remoteproc/qcom,rpm-proc.yaml
+171
Documentation/devicetree/bindings/remoteproc/qcom,rpm-proc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/remoteproc/qcom,rpm-proc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Qualcomm Resource Power Manager (RPM) Processor/Subsystem
8
+
9
+
maintainers:
10
+
- Bjorn Andersson <andersson@kernel.org>
11
+
- Konrad Dybcio <konrad.dybcio@linaro.org>
12
+
- Stephan Gerhold <stephan@gerhold.net>
13
+
14
+
description: |
15
+
Resource Power Manager (RPM) subsystem found in various Qualcomm platforms:
16
+
17
+
+--------------------------------------------+
18
+
| RPM subsystem (qcom,rpm-proc) |
19
+
| |
20
+
reset | +---------------+ +-----+ +-----+ |
21
+
--------->| | | MPM | | CPR | ... |
22
+
IPC interrupts | | ARM Cortex-M3 |--- +-----+ +-----+ |
23
+
----------------->| | | | | |
24
+
| +---------------+ |---------------------- |
25
+
| +---------------+ | |
26
+
| | Code RAM |--| +------------------+ |
27
+
| +---------------+ | | | |
28
+
| +---------------+ |--| Message RAM | |
29
+
| | Data RAM |--| | | |
30
+
| +---------------+ | +------------------+ |
31
+
+--------------------|-----------------------+
32
+
v
33
+
NoC
34
+
35
+
The firmware running on the processor inside the RPM subsystem allows each
36
+
component in the system to vote for state of the system resources, such as
37
+
clocks, regulators and bus frequencies. It implements multiple separate
38
+
communication interfaces that are described in subnodes, e.g. SMD and MPM:
39
+
40
+
+------------------------------+
41
+
| ARM Cortex-M3 |
42
+
| | +------------------------------+
43
+
| +--------------------------+ | | Message RAM |
44
+
| | RPM firmware | | | |
45
+
IPC IRQ 0 | | +----------------------+ | | | +--------------------------+ |
46
+
-------------->| SMD server |<------->| SMD data structures | |
47
+
| | | +--------------+ | | | | | +--------------+ | |
48
+
| | | | rpm_requests | ... | | | | | | rpm_requests | ... | |
49
+
| | | +--------------+ | | | | | +--------------+ | |
50
+
IPC IRQ 1 | | +----------------------+ | | | +--------------------------+ |
51
+
-------------->| MPM virtualization |<--------| MPM register copy (vMPM) | |
52
+
| | +----------------------+ | | | +--------------------------+ |
53
+
| | ... | | | | ... |
54
+
| +--------------------|-----+ | +------------------------------+
55
+
+----------------------|-------+
56
+
v
57
+
+--------------+
58
+
| MPM Hardware |
59
+
+--------------+
60
+
61
+
The services provided by the firmware are only available after the firmware
62
+
has been loaded and the processor has been released from reset. Usually this
63
+
happens early in the boot process before the operating system is started.
64
+
65
+
properties:
66
+
compatible:
67
+
items:
68
+
- enum:
69
+
- qcom,apq8084-rpm-proc
70
+
- qcom,ipq6018-rpm-proc
71
+
- qcom,ipq9574-rpm-proc
72
+
- qcom,mdm9607-rpm-proc
73
+
- qcom,msm8226-rpm-proc
74
+
- qcom,msm8610-rpm-proc
75
+
- qcom,msm8909-rpm-proc
76
+
- qcom,msm8916-rpm-proc
77
+
- qcom,msm8917-rpm-proc
78
+
- qcom,msm8936-rpm-proc
79
+
- qcom,msm8937-rpm-proc
80
+
- qcom,msm8952-rpm-proc
81
+
- qcom,msm8953-rpm-proc
82
+
- qcom,msm8974-rpm-proc
83
+
- qcom,msm8976-rpm-proc
84
+
- qcom,msm8994-rpm-proc
85
+
- qcom,msm8996-rpm-proc
86
+
- qcom,msm8998-rpm-proc
87
+
- qcom,qcm2290-rpm-proc
88
+
- qcom,qcs404-rpm-proc
89
+
- qcom,sdm660-rpm-proc
90
+
- qcom,sm6115-rpm-proc
91
+
- qcom,sm6125-rpm-proc
92
+
- qcom,sm6375-rpm-proc
93
+
- const: qcom,rpm-proc
94
+
95
+
smd-edge:
96
+
$ref: /schemas/remoteproc/qcom,smd-edge.yaml#
97
+
description:
98
+
Qualcomm Shared Memory subnode which represents communication edge,
99
+
channels and devices related to the RPM subsystem.
100
+
101
+
glink-edge:
102
+
$ref: /schemas/remoteproc/qcom,glink-rpm-edge.yaml#
103
+
description:
104
+
Qualcomm G-Link subnode which represents communication edge,
105
+
channels and devices related to the RPM subsystem.
106
+
107
+
interrupt-controller:
108
+
type: object
109
+
$ref: /schemas/interrupt-controller/qcom,mpm.yaml#
110
+
description:
111
+
MSM Power Manager (MPM) interrupt controller that monitors interrupts
112
+
when the system is asleep.
113
+
114
+
master-stats:
115
+
$ref: /schemas/soc/qcom/qcom,rpm-master-stats.yaml#
116
+
description:
117
+
Subsystem-level low-power mode statistics provided by RPM.
118
+
119
+
required:
120
+
- compatible
121
+
122
+
oneOf:
123
+
- required:
124
+
- smd-edge
125
+
- required:
126
+
- glink-edge
127
+
128
+
additionalProperties: false
129
+
130
+
examples:
131
+
# SMD
132
+
- |
133
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
134
+
#include <dt-bindings/interrupt-controller/irq.h>
135
+
136
+
remoteproc {
137
+
compatible = "qcom,msm8916-rpm-proc", "qcom,rpm-proc";
138
+
139
+
smd-edge {
140
+
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
141
+
qcom,ipc = <&apcs 8 0>;
142
+
qcom,smd-edge = <15>;
143
+
144
+
rpm-requests {
145
+
compatible = "qcom,rpm-msm8916";
146
+
qcom,smd-channels = "rpm_requests";
147
+
/* ... */
148
+
};
149
+
};
150
+
};
151
+
# GLINK
152
+
- |
153
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
154
+
#include <dt-bindings/interrupt-controller/irq.h>
155
+
156
+
remoteproc {
157
+
compatible = "qcom,qcm2290-rpm-proc", "qcom,rpm-proc";
158
+
159
+
glink-edge {
160
+
compatible = "qcom,glink-rpm";
161
+
interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
162
+
qcom,rpm-msg-ram = <&rpm_msg_ram>;
163
+
mboxes = <&apcs_glb 0>;
164
+
165
+
rpm-requests {
166
+
compatible = "qcom,rpm-qcm2290";
167
+
qcom,glink-channels = "rpm_requests";
168
+
/* ... */
169
+
};
170
+
};
171
+
};
+3
-3
Documentation/devicetree/bindings/remoteproc/qcom,sm8350-pas.yaml
+3
-3
Documentation/devicetree/bindings/remoteproc/qcom,sm8350-pas.yaml
···
139
139
#include <dt-bindings/clock/qcom,rpmh.h>
140
140
#include <dt-bindings/interrupt-controller/irq.h>
141
141
#include <dt-bindings/mailbox/qcom-ipcc.h>
142
-
#include <dt-bindings/power/qcom-rpmpd.h>
142
+
#include <dt-bindings/power/qcom,rpmhpd.h>
143
143
144
144
remoteproc@30000000 {
145
145
compatible = "qcom,sm8450-adsp-pas";
···
160
160
161
161
memory-region = <&adsp_mem>;
162
162
163
-
power-domains = <&rpmhpd SM8450_LCX>,
164
-
<&rpmhpd SM8450_LMX>;
163
+
power-domains = <&rpmhpd RPMHPD_LCX>,
164
+
<&rpmhpd RPMHPD_LMX>;
165
165
power-domain-names = "lcx", "lmx";
166
166
167
167
qcom,qmp = <&aoss_qmp>;
+1
Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml
+1
Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml
+52
Documentation/devicetree/bindings/soc/loongson/loongson,ls2k-pmc.yaml
+52
Documentation/devicetree/bindings/soc/loongson/loongson,ls2k-pmc.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/soc/loongson/loongson,ls2k-pmc.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Loongson-2 Power Manager controller
8
+
9
+
maintainers:
10
+
- Yinbo Zhu <zhuyinbo@loongson.cn>
11
+
12
+
properties:
13
+
compatible:
14
+
items:
15
+
- enum:
16
+
- loongson,ls2k0500-pmc
17
+
- loongson,ls2k1000-pmc
18
+
- const: syscon
19
+
20
+
reg:
21
+
maxItems: 1
22
+
23
+
interrupts:
24
+
maxItems: 1
25
+
26
+
loongson,suspend-address:
27
+
$ref: /schemas/types.yaml#/definitions/uint64
28
+
description:
29
+
The "loongson,suspend-address" is a deep sleep state (Suspend To
30
+
RAM) firmware entry address which was jumped from kernel and it's
31
+
value was dependent on specific platform firmware code. In
32
+
addition, the PM need according to it to indicate that current
33
+
SoC whether support Suspend To RAM.
34
+
35
+
required:
36
+
- compatible
37
+
- reg
38
+
- interrupts
39
+
40
+
additionalProperties: false
41
+
42
+
examples:
43
+
- |
44
+
#include <dt-bindings/interrupt-controller/irq.h>
45
+
46
+
power-management@1fe27000 {
47
+
compatible = "loongson,ls2k1000-pmc", "syscon";
48
+
reg = <0x1fe27000 0x58>;
49
+
interrupt-parent = <&liointc1>;
50
+
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
51
+
loongson,suspend-address = <0x0 0x1c000500>;
52
+
};
+17
-6
Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml
+17
-6
Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml
···
34
34
- qcom,rpm-apq8084
35
35
- qcom,rpm-ipq6018
36
36
- qcom,rpm-ipq9574
37
+
- qcom,rpm-mdm9607
37
38
- qcom,rpm-msm8226
39
+
- qcom,rpm-msm8610
38
40
- qcom,rpm-msm8909
39
41
- qcom,rpm-msm8916
42
+
- qcom,rpm-msm8917
40
43
- qcom,rpm-msm8936
44
+
- qcom,rpm-msm8937
45
+
- qcom,rpm-msm8952
41
46
- qcom,rpm-msm8953
42
47
- qcom,rpm-msm8974
43
48
- qcom,rpm-msm8976
44
49
- qcom,rpm-msm8994
45
50
- qcom,rpm-msm8996
46
51
- qcom,rpm-msm8998
52
+
- qcom,rpm-qcm2290
53
+
- qcom,rpm-qcs404
47
54
- qcom,rpm-sdm660
48
55
- qcom,rpm-sm6115
49
56
- qcom,rpm-sm6125
50
57
- qcom,rpm-sm6375
51
-
- qcom,rpm-qcm2290
52
-
- qcom,rpm-qcs404
53
58
54
59
clock-controller:
55
60
$ref: /schemas/clock/qcom,rpmcc.yaml#
···
86
81
contains:
87
82
enum:
88
83
- qcom,rpm-apq8084
84
+
- qcom,rpm-mdm9607
89
85
- qcom,rpm-msm8226
86
+
- qcom,rpm-msm8610
87
+
- qcom,rpm-msm8909
90
88
- qcom,rpm-msm8916
89
+
- qcom,rpm-msm8917
91
90
- qcom,rpm-msm8936
91
+
- qcom,rpm-msm8937
92
+
- qcom,rpm-msm8952
93
+
- qcom,rpm-msm8953
92
94
- qcom,rpm-msm8974
93
95
- qcom,rpm-msm8976
94
-
- qcom,rpm-msm8953
95
96
- qcom,rpm-msm8994
96
97
then:
97
98
properties:
···
120
109
#include <dt-bindings/interrupt-controller/arm-gic.h>
121
110
#include <dt-bindings/interrupt-controller/irq.h>
122
111
123
-
smd {
124
-
compatible = "qcom,smd";
112
+
remoteproc {
113
+
compatible = "qcom,msm8916-rpm-proc", "qcom,rpm-proc";
125
114
126
-
rpm {
115
+
smd-edge {
127
116
interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
128
117
qcom,ipc = <&apcs 8 0>;
129
118
qcom,smd-edge = <15>;
+7
Documentation/devicetree/bindings/soc/qcom/qcom,smd.yaml
+7
Documentation/devicetree/bindings/soc/qcom/qcom,smd.yaml
···
15
15
The Qualcomm Shared Memory Driver is a FIFO based communication channel for
16
16
sending data between the various subsystems in Qualcomm platforms.
17
17
18
+
Using the top-level SMD node is deprecated. Instead, the SMD edges are defined
19
+
directly below the device node representing the respective remote subsystem
20
+
or remote processor.
21
+
22
+
deprecated: true
23
+
18
24
properties:
19
25
compatible:
20
26
const: qcom,smd
···
43
37
# The following example represents a smd node, with one edge representing the
44
38
# "rpm" subsystem. For the "rpm" subsystem we have a device tied to the
45
39
# "rpm_request" channel.
40
+
# NOTE: This is deprecated, represent the RPM using "qcom,rpm-proc" instead.
46
41
- |
47
42
#include <dt-bindings/interrupt-controller/arm-gic.h>
48
43
+25
-1
Documentation/devicetree/bindings/sram/qcom,ocmem.yaml
+25
-1
Documentation/devicetree/bindings/sram/qcom,ocmem.yaml
···
15
15
16
16
properties:
17
17
compatible:
18
-
const: qcom,msm8974-ocmem
18
+
enum:
19
+
- qcom,msm8226-ocmem # v1.1.0
20
+
- qcom,msm8974-ocmem # v1.4.0
19
21
20
22
reg:
21
23
items:
···
30
28
- const: mem
31
29
32
30
clocks:
31
+
minItems: 1
33
32
items:
34
33
- description: Core clock
35
34
- description: Interface clock
36
35
37
36
clock-names:
37
+
minItems: 1
38
38
items:
39
39
- const: core
40
40
- const: iface
···
61
57
- ranges
62
58
63
59
additionalProperties: false
60
+
61
+
allOf:
62
+
- if:
63
+
properties:
64
+
compatible:
65
+
contains:
66
+
enum:
67
+
- qcom,msm8974-ocmem
68
+
then:
69
+
properties:
70
+
clocks:
71
+
minItems: 2
72
+
clock-names:
73
+
minItems: 2
74
+
else:
75
+
properties:
76
+
clocks:
77
+
minItems: 1
78
+
clock-names:
79
+
minItems: 1
64
80
65
81
patternProperties:
66
82
"-sram@[0-9a-f]+$":
+23
-20
MAINTAINERS
+23
-20
MAINTAINERS
···
2508
2508
W: http://www.digriz.org.uk/ts78xx/kernel
2509
2509
F: arch/arm/mach-orion5x/ts78xx-*
2510
2510
2511
-
ARM/OXNAS platform support
2512
-
M: Neil Armstrong <neil.armstrong@linaro.org>
2513
-
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
2514
-
L: linux-oxnas@groups.io (moderated for non-subscribers)
2515
-
S: Maintained
2516
-
F: arch/arm/boot/dts/ox8*.dts*
2517
-
F: arch/arm/mach-oxnas/
2518
-
F: drivers/power/reset/oxnas-restart.c
2519
-
N: oxnas
2520
-
2521
2511
ARM/QUALCOMM CHROMEBOOK SUPPORT
2522
2512
R: cros-qcom-dts-watchers@chromium.org
2523
2513
F: arch/arm64/boot/dts/qcom/sc7180*
···
2935
2945
M: Lorenzo Pieralisi <lpieralisi@kernel.org>
2936
2946
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
2937
2947
S: Maintained
2938
-
F: */*/*/vexpress*
2939
-
F: */*/vexpress*
2940
-
F: arch/arm/boot/dts/arm/vexpress*
2948
+
N: mps2
2949
+
N: vexpress
2941
2950
F: arch/arm/mach-versatile/
2942
2951
F: arch/arm64/boot/dts/arm/
2943
-
F: drivers/clk/versatile/clk-vexpress-osc.c
2944
2952
F: drivers/clocksource/timer-versatile.c
2945
-
N: mps2
2953
+
X: drivers/cpufreq/vexpress-spc-cpufreq.c
2954
+
X: Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml
2946
2955
2947
2956
ARM/VFP SUPPORT
2948
2957
M: Russell King <linux@armlinux.org.uk>
···
5391
5402
R: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
5392
5403
L: linux-pm@vger.kernel.org
5393
5404
L: linux-samsung-soc@vger.kernel.org
5394
-
S: Supported
5405
+
S: Maintained
5395
5406
F: arch/arm/mach-exynos/pm.c
5396
5407
F: drivers/cpuidle/cpuidle-exynos.c
5397
5408
F: include/linux/platform_data/cpuidle-exynos.h
···
9367
9378
F: Documentation/devicetree/bindings/i2c/hisilicon,ascend910-i2c.yaml
9368
9379
F: drivers/i2c/busses/i2c-hisi.c
9369
9380
9381
+
HISILICON KUNPENG SOC HCCS DRIVER
9382
+
M: Huisong Li <lihuisong@huawei.com>
9383
+
S: Maintained
9384
+
F: Documentation/ABI/testing/sysfs-devices-platform-kunpeng_hccs
9385
+
F: drivers/soc/hisilicon/kunpeng_hccs.c
9386
+
F: drivers/soc/hisilicon/kunpeng_hccs.h
9387
+
9370
9388
HISILICON LPC BUS DRIVER
9371
9389
M: Jay Fang <f.fangjian@huawei.com>
9372
9390
S: Maintained
···
12349
12353
F: Documentation/devicetree/bindings/hwinfo/loongson,ls2k-chipid.yaml
12350
12354
F: drivers/soc/loongson/loongson2_guts.c
12351
12355
12356
+
LOONGSON-2 SOC SERIES PM DRIVER
12357
+
M: Yinbo Zhu <zhuyinbo@loongson.cn>
12358
+
L: linux-pm@vger.kernel.org
12359
+
S: Maintained
12360
+
F: Documentation/devicetree/bindings/soc/loongson/loongson,ls2k-pmc.yaml
12361
+
F: drivers/soc/loongson/loongson2_pm.c
12362
+
12352
12363
LOONGSON-2 SOC SERIES PINCTRL DRIVER
12353
12364
M: zhanghongchen <zhanghongchen@loongson.cn>
12354
12365
M: Yinbo Zhu <zhuyinbo@loongson.cn>
···
12905
12902
MAXIM MUIC CHARGER DRIVERS FOR EXYNOS BASED BOARDS
12906
12903
M: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
12907
12904
L: linux-pm@vger.kernel.org
12908
-
S: Supported
12905
+
S: Maintained
12909
12906
B: mailto:linux-samsung-soc@vger.kernel.org
12910
12907
F: Documentation/devicetree/bindings/power/supply/maxim,max14577.yaml
12911
12908
F: Documentation/devicetree/bindings/power/supply/maxim,max77693.yaml
···
12916
12913
M: Chanwoo Choi <cw00.choi@samsung.com>
12917
12914
M: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
12918
12915
L: linux-kernel@vger.kernel.org
12919
-
S: Supported
12916
+
S: Maintained
12920
12917
B: mailto:linux-samsung-soc@vger.kernel.org
12921
12918
F: Documentation/devicetree/bindings/*/maxim,max14577.yaml
12922
12919
F: Documentation/devicetree/bindings/*/maxim,max77686.yaml
···
18887
18884
M: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
18888
18885
L: linux-kernel@vger.kernel.org
18889
18886
L: linux-samsung-soc@vger.kernel.org
18890
-
S: Supported
18887
+
S: Maintained
18891
18888
B: mailto:linux-samsung-soc@vger.kernel.org
18892
18889
F: Documentation/devicetree/bindings/clock/samsung,s2mps11.yaml
18893
18890
F: Documentation/devicetree/bindings/mfd/samsung,s2m*.yaml
···
18959
18956
M: Chanwoo Choi <cw00.choi@samsung.com>
18960
18957
R: Alim Akhtar <alim.akhtar@samsung.com>
18961
18958
L: linux-samsung-soc@vger.kernel.org
18962
-
S: Supported
18959
+
S: Maintained
18963
18960
T: git git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git
18964
18961
T: git git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk.git
18965
18962
F: Documentation/devicetree/bindings/clock/samsung,*.yaml
+2
-1
drivers/bus/Kconfig
+2
-1
drivers/bus/Kconfig
+13
-77
drivers/bus/fsl-mc/fsl-mc-bus.c
+13
-77
drivers/bus/fsl-mc/fsl-mc-bus.c
···
994
994
}
995
995
EXPORT_SYMBOL_GPL(fsl_mc_get_endpoint);
996
996
997
-
static int parse_mc_ranges(struct device *dev,
998
-
int *paddr_cells,
999
-
int *mc_addr_cells,
1000
-
int *mc_size_cells,
1001
-
const __be32 **ranges_start)
1002
-
{
1003
-
const __be32 *prop;
1004
-
int range_tuple_cell_count;
1005
-
int ranges_len;
1006
-
int tuple_len;
1007
-
struct device_node *mc_node = dev->of_node;
1008
-
1009
-
*ranges_start = of_get_property(mc_node, "ranges", &ranges_len);
1010
-
if (!(*ranges_start) || !ranges_len) {
1011
-
dev_warn(dev,
1012
-
"missing or empty ranges property for device tree node '%pOFn'\n",
1013
-
mc_node);
1014
-
return 0;
1015
-
}
1016
-
1017
-
*paddr_cells = of_n_addr_cells(mc_node);
1018
-
1019
-
prop = of_get_property(mc_node, "#address-cells", NULL);
1020
-
if (prop)
1021
-
*mc_addr_cells = be32_to_cpup(prop);
1022
-
else
1023
-
*mc_addr_cells = *paddr_cells;
1024
-
1025
-
prop = of_get_property(mc_node, "#size-cells", NULL);
1026
-
if (prop)
1027
-
*mc_size_cells = be32_to_cpup(prop);
1028
-
else
1029
-
*mc_size_cells = of_n_size_cells(mc_node);
1030
-
1031
-
range_tuple_cell_count = *paddr_cells + *mc_addr_cells +
1032
-
*mc_size_cells;
1033
-
1034
-
tuple_len = range_tuple_cell_count * sizeof(__be32);
1035
-
if (ranges_len % tuple_len != 0) {
1036
-
dev_err(dev, "malformed ranges property '%pOFn'\n", mc_node);
1037
-
return -EINVAL;
1038
-
}
1039
-
1040
-
return ranges_len / tuple_len;
1041
-
}
1042
-
1043
997
static int get_mc_addr_translation_ranges(struct device *dev,
1044
998
struct fsl_mc_addr_translation_range
1045
999
**ranges,
1046
1000
u8 *num_ranges)
1047
1001
{
1048
-
int ret;
1049
-
int paddr_cells;
1050
-
int mc_addr_cells;
1051
-
int mc_size_cells;
1052
-
int i;
1053
-
const __be32 *ranges_start;
1054
-
const __be32 *cell;
1002
+
struct fsl_mc_addr_translation_range *r;
1003
+
struct of_range_parser parser;
1004
+
struct of_range range;
1055
1005
1056
-
ret = parse_mc_ranges(dev,
1057
-
&paddr_cells,
1058
-
&mc_addr_cells,
1059
-
&mc_size_cells,
1060
-
&ranges_start);
1061
-
if (ret < 0)
1062
-
return ret;
1063
-
1064
-
*num_ranges = ret;
1065
-
if (!ret) {
1006
+
of_range_parser_init(&parser, dev->of_node);
1007
+
*num_ranges = of_range_count(&parser);
1008
+
if (!*num_ranges) {
1066
1009
/*
1067
1010
* Missing or empty ranges property ("ranges;") for the
1068
1011
* 'fsl,qoriq-mc' node. In this case, identity mapping
···
1021
1078
if (!(*ranges))
1022
1079
return -ENOMEM;
1023
1080
1024
-
cell = ranges_start;
1025
-
for (i = 0; i < *num_ranges; ++i) {
1026
-
struct fsl_mc_addr_translation_range *range = &(*ranges)[i];
1027
-
1028
-
range->mc_region_type = of_read_number(cell, 1);
1029
-
range->start_mc_offset = of_read_number(cell + 1,
1030
-
mc_addr_cells - 1);
1031
-
cell += mc_addr_cells;
1032
-
range->start_phys_addr = of_read_number(cell, paddr_cells);
1033
-
cell += paddr_cells;
1034
-
range->end_mc_offset = range->start_mc_offset +
1035
-
of_read_number(cell, mc_size_cells);
1036
-
1037
-
cell += mc_size_cells;
1081
+
r = *ranges;
1082
+
for_each_of_range(&parser, &range) {
1083
+
r->mc_region_type = range.flags;
1084
+
r->start_mc_offset = range.bus_addr;
1085
+
r->end_mc_offset = range.bus_addr + range.size;
1086
+
r->start_phys_addr = range.cpu_addr;
1087
+
r++;
1038
1088
}
1039
1089
1040
1090
return 0;
+1
-1
drivers/bus/imx-weim.c
+1
-1
drivers/bus/imx-weim.c
+10
-11
drivers/bus/omap_l3_smx.c
+10
-11
drivers/bus/omap_l3_smx.c
···
166
166
irqreturn_t ret = IRQ_NONE;
167
167
168
168
int_type = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
169
-
if (!int_type) {
169
+
if (!int_type)
170
170
status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_0);
171
-
/*
172
-
* if we have a timeout error, there's nothing we can
173
-
* do besides rebooting the board. So let's BUG on any
174
-
* of such errors and handle the others. timeout error
175
-
* is severe and not expected to occur.
176
-
*/
177
-
BUG_ON(status & L3_STATUS_0_TIMEOUT_MASK);
178
-
} else {
171
+
else
179
172
status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_1);
180
-
/* No timeout error for debug sources */
181
-
}
182
173
183
174
/* identify the error source */
184
175
err_source = __ffs(status);
···
180
189
error_addr = omap3_l3_readll(base, L3_ERROR_LOG_ADDR);
181
190
ret |= omap3_l3_block_irq(l3, error, error_addr);
182
191
}
192
+
193
+
/*
194
+
* if we have a timeout error, there's nothing we can
195
+
* do besides rebooting the board. So let's BUG on any
196
+
* of such errors and handle the others. timeout error
197
+
* is severe and not expected to occur.
198
+
*/
199
+
BUG_ON(!int_type && status & L3_STATUS_0_TIMEOUT_MASK);
183
200
184
201
/* Clear the status register */
185
202
clear = (L3_AGENT_STATUS_CLEAR_IA << int_type) |
+1
-3
drivers/bus/sunxi-rsb.c
+1
-3
drivers/bus/sunxi-rsb.c
···
746
746
{
747
747
struct device *dev = &pdev->dev;
748
748
struct device_node *np = dev->of_node;
749
-
struct resource *r;
750
749
struct sunxi_rsb *rsb;
751
750
u32 clk_freq = 3000000;
752
751
int irq, ret;
···
765
766
rsb->dev = dev;
766
767
rsb->clk_freq = clk_freq;
767
768
platform_set_drvdata(pdev, rsb);
768
-
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
769
-
rsb->regs = devm_ioremap_resource(dev, r);
769
+
rsb->regs = devm_platform_ioremap_resource(pdev, 0);
770
770
if (IS_ERR(rsb->regs))
771
771
return PTR_ERR(rsb->regs);
772
772
+1
-3
drivers/bus/tegra-gmi.c
+1
-3
drivers/bus/tegra-gmi.c
···
211
211
{
212
212
struct device *dev = &pdev->dev;
213
213
struct tegra_gmi *gmi;
214
-
struct resource *res;
215
214
int err;
216
215
217
216
gmi = devm_kzalloc(dev, sizeof(*gmi), GFP_KERNEL);
···
220
221
platform_set_drvdata(pdev, gmi);
221
222
gmi->dev = dev;
222
223
223
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
224
-
gmi->base = devm_ioremap_resource(dev, res);
224
+
gmi->base = devm_platform_ioremap_resource(pdev, 0);
225
225
if (IS_ERR(gmi->base))
226
226
return PTR_ERR(gmi->base);
227
227
+4
-1
drivers/bus/ti-sysc.c
+4
-1
drivers/bus/ti-sysc.c
···
109
109
* @cookie: data used by legacy platform callbacks
110
110
* @name: name if available
111
111
* @revision: interconnect target module revision
112
+
* @sysconfig: saved sysconfig register value
112
113
* @reserved: target module is reserved and already in use
113
114
* @enabled: sysc runtime enabled status
114
115
* @needs_resume: runtime resume needed on resume from suspend
···
1525
1524
SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff,
1526
1525
SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1527
1526
SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff,
1527
+
SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1528
+
SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47424e03, 0xffffffff,
1528
1529
SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE),
1529
1530
1530
1531
/* Quirks that need to be set based on the module address */
···
3109
3106
3110
3107
match = soc_device_match(sysc_soc_match);
3111
3108
if (match && match->data)
3112
-
sysc_soc->soc = (int)match->data;
3109
+
sysc_soc->soc = (enum sysc_soc)(uintptr_t)match->data;
3113
3110
3114
3111
/*
3115
3112
* Check and warn about possible old incomplete dtb. We now want to see
+1
-3
drivers/bus/vexpress-config.c
+1
-3
drivers/bus/vexpress-config.c
···
350
350
static int vexpress_syscfg_probe(struct platform_device *pdev)
351
351
{
352
352
struct vexpress_syscfg *syscfg;
353
-
struct resource *res;
354
353
struct vexpress_config_bridge *bridge;
355
354
struct device_node *node;
356
355
int master;
···
361
362
syscfg->dev = &pdev->dev;
362
363
INIT_LIST_HEAD(&syscfg->funcs);
363
364
364
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
365
-
syscfg->base = devm_ioremap_resource(&pdev->dev, res);
365
+
syscfg->base = devm_platform_ioremap_resource(pdev, 0);
366
366
if (IS_ERR(syscfg->base))
367
367
return PTR_ERR(syscfg->base);
368
368
+348
-82
drivers/firmware/arm_scmi/perf.c
+348
-82
drivers/firmware/arm_scmi/perf.c
···
2
2
/*
3
3
* System Control and Management Interface (SCMI) Performance Protocol
4
4
*
5
-
* Copyright (C) 2018-2022 ARM Ltd.
5
+
* Copyright (C) 2018-2023 ARM Ltd.
6
6
*/
7
7
8
8
#define pr_fmt(fmt) "SCMI Notifications PERF - " fmt
9
9
10
10
#include <linux/bits.h>
11
-
#include <linux/of.h>
11
+
#include <linux/hashtable.h>
12
12
#include <linux/io.h>
13
+
#include <linux/log2.h>
13
14
#include <linux/module.h>
15
+
#include <linux/of.h>
14
16
#include <linux/platform_device.h>
15
17
#include <linux/pm_opp.h>
16
18
#include <linux/scmi_protocol.h>
17
19
#include <linux/sort.h>
20
+
#include <linux/xarray.h>
18
21
19
22
#include <trace/events/scmi.h>
20
23
···
49
46
u32 perf;
50
47
u32 power;
51
48
u32 trans_latency_us;
49
+
u32 indicative_freq;
50
+
u32 level_index;
51
+
struct hlist_node hash;
52
52
};
53
53
54
54
struct scmi_msg_resp_perf_attributes {
···
72
66
#define SUPPORTS_PERF_LEVEL_NOTIFY(x) ((x) & BIT(28))
73
67
#define SUPPORTS_PERF_FASTCHANNELS(x) ((x) & BIT(27))
74
68
#define SUPPORTS_EXTENDED_NAMES(x) ((x) & BIT(26))
69
+
#define SUPPORTS_LEVEL_INDEXING(x) ((x) & BIT(25))
75
70
__le32 rate_limit_us;
76
71
__le32 sustained_freq_khz;
77
72
__le32 sustained_perf_level;
···
129
122
} opp[];
130
123
};
131
124
125
+
struct scmi_msg_resp_perf_describe_levels_v4 {
126
+
__le16 num_returned;
127
+
__le16 num_remaining;
128
+
struct {
129
+
__le32 perf_val;
130
+
__le32 power;
131
+
__le16 transition_latency_us;
132
+
__le16 reserved;
133
+
__le32 indicative_freq;
134
+
__le32 level_index;
135
+
} opp[];
136
+
};
137
+
132
138
struct perf_dom_info {
139
+
u32 id;
133
140
bool set_limits;
134
141
bool set_perf;
135
142
bool perf_limit_notify;
136
143
bool perf_level_notify;
137
144
bool perf_fastchannels;
145
+
bool level_indexing_mode;
138
146
u32 opp_count;
139
147
u32 sustained_freq_khz;
140
148
u32 sustained_perf_level;
···
157
135
char name[SCMI_MAX_STR_SIZE];
158
136
struct scmi_opp opp[MAX_OPPS];
159
137
struct scmi_fc_info *fc_info;
138
+
struct xarray opps_by_idx;
139
+
struct xarray opps_by_lvl;
140
+
DECLARE_HASHTABLE(opps_by_freq, ilog2(MAX_OPPS));
160
141
};
142
+
143
+
#define LOOKUP_BY_FREQ(__htp, __freq) \
144
+
({ \
145
+
/* u32 cast is needed to pick right hash func */ \
146
+
u32 f_ = (u32)(__freq); \
147
+
struct scmi_opp *_opp; \
148
+
\
149
+
hash_for_each_possible((__htp), _opp, hash, f_) \
150
+
if (_opp->indicative_freq == f_) \
151
+
break; \
152
+
_opp; \
153
+
})
161
154
162
155
struct scmi_perf_info {
163
156
u32 version;
164
-
int num_domains;
157
+
u16 num_domains;
165
158
enum scmi_power_scale power_scale;
166
159
u64 stats_addr;
167
160
u32 stats_size;
···
223
186
return ret;
224
187
}
225
188
189
+
static void scmi_perf_xa_destroy(void *data)
190
+
{
191
+
int domain;
192
+
struct scmi_perf_info *pinfo = data;
193
+
194
+
for (domain = 0; domain < pinfo->num_domains; domain++) {
195
+
xa_destroy(&((pinfo->dom_info + domain)->opps_by_idx));
196
+
xa_destroy(&((pinfo->dom_info + domain)->opps_by_lvl));
197
+
}
198
+
}
199
+
226
200
static int
227
201
scmi_perf_domain_attributes_get(const struct scmi_protocol_handle *ph,
228
-
u32 domain, struct perf_dom_info *dom_info,
202
+
struct perf_dom_info *dom_info,
229
203
u32 version)
230
204
{
231
205
int ret;
···
245
197
struct scmi_msg_resp_perf_domain_attributes *attr;
246
198
247
199
ret = ph->xops->xfer_get_init(ph, PERF_DOMAIN_ATTRIBUTES,
248
-
sizeof(domain), sizeof(*attr), &t);
200
+
sizeof(dom_info->id), sizeof(*attr), &t);
249
201
if (ret)
250
202
return ret;
251
203
252
-
put_unaligned_le32(domain, t->tx.buf);
204
+
put_unaligned_le32(dom_info->id, t->tx.buf);
253
205
attr = t->rx.buf;
254
206
255
207
ret = ph->xops->do_xfer(ph, t);
···
261
213
dom_info->perf_limit_notify = SUPPORTS_PERF_LIMIT_NOTIFY(flags);
262
214
dom_info->perf_level_notify = SUPPORTS_PERF_LEVEL_NOTIFY(flags);
263
215
dom_info->perf_fastchannels = SUPPORTS_PERF_FASTCHANNELS(flags);
216
+
if (PROTOCOL_REV_MAJOR(version) >= 0x4)
217
+
dom_info->level_indexing_mode =
218
+
SUPPORTS_LEVEL_INDEXING(flags);
264
219
dom_info->sustained_freq_khz =
265
220
le32_to_cpu(attr->sustained_freq_khz);
266
221
dom_info->sustained_perf_level =
···
287
236
*/
288
237
if (!ret && PROTOCOL_REV_MAJOR(version) >= 0x3 &&
289
238
SUPPORTS_EXTENDED_NAMES(flags))
290
-
ph->hops->extended_name_get(ph, PERF_DOMAIN_NAME_GET, domain,
291
-
dom_info->name, SCMI_MAX_STR_SIZE);
239
+
ph->hops->extended_name_get(ph, PERF_DOMAIN_NAME_GET,
240
+
dom_info->id, dom_info->name,
241
+
SCMI_MAX_STR_SIZE);
242
+
243
+
if (dom_info->level_indexing_mode) {
244
+
xa_init(&dom_info->opps_by_idx);
245
+
xa_init(&dom_info->opps_by_lvl);
246
+
hash_init(dom_info->opps_by_freq);
247
+
}
292
248
293
249
return ret;
294
250
}
···
308
250
}
309
251
310
252
struct scmi_perf_ipriv {
311
-
u32 domain;
253
+
u32 version;
312
254
struct perf_dom_info *perf_dom;
313
255
};
314
256
···
319
261
struct scmi_msg_perf_describe_levels *msg = message;
320
262
const struct scmi_perf_ipriv *p = priv;
321
263
322
-
msg->domain = cpu_to_le32(p->domain);
264
+
msg->domain = cpu_to_le32(p->perf_dom->id);
323
265
/* Set the number of OPPs to be skipped/already read */
324
266
msg->level_index = cpu_to_le32(desc_index);
325
267
}
···
335
277
return 0;
336
278
}
337
279
280
+
static inline void
281
+
process_response_opp(struct scmi_opp *opp, unsigned int loop_idx,
282
+
const struct scmi_msg_resp_perf_describe_levels *r)
283
+
{
284
+
opp->perf = le32_to_cpu(r->opp[loop_idx].perf_val);
285
+
opp->power = le32_to_cpu(r->opp[loop_idx].power);
286
+
opp->trans_latency_us =
287
+
le16_to_cpu(r->opp[loop_idx].transition_latency_us);
288
+
}
289
+
290
+
static inline void
291
+
process_response_opp_v4(struct perf_dom_info *dom, struct scmi_opp *opp,
292
+
unsigned int loop_idx,
293
+
const struct scmi_msg_resp_perf_describe_levels_v4 *r)
294
+
{
295
+
opp->perf = le32_to_cpu(r->opp[loop_idx].perf_val);
296
+
opp->power = le32_to_cpu(r->opp[loop_idx].power);
297
+
opp->trans_latency_us =
298
+
le16_to_cpu(r->opp[loop_idx].transition_latency_us);
299
+
300
+
/* Note that PERF v4 reports always five 32-bit words */
301
+
opp->indicative_freq = le32_to_cpu(r->opp[loop_idx].indicative_freq);
302
+
if (dom->level_indexing_mode) {
303
+
opp->level_index = le32_to_cpu(r->opp[loop_idx].level_index);
304
+
305
+
xa_store(&dom->opps_by_idx, opp->level_index, opp, GFP_KERNEL);
306
+
xa_store(&dom->opps_by_lvl, opp->perf, opp, GFP_KERNEL);
307
+
hash_add(dom->opps_by_freq, &opp->hash, opp->indicative_freq);
308
+
}
309
+
}
310
+
338
311
static int
339
312
iter_perf_levels_process_response(const struct scmi_protocol_handle *ph,
340
313
const void *response,
341
314
struct scmi_iterator_state *st, void *priv)
342
315
{
343
316
struct scmi_opp *opp;
344
-
const struct scmi_msg_resp_perf_describe_levels *r = response;
345
317
struct scmi_perf_ipriv *p = priv;
346
318
347
319
opp = &p->perf_dom->opp[st->desc_index + st->loop_idx];
348
-
opp->perf = le32_to_cpu(r->opp[st->loop_idx].perf_val);
349
-
opp->power = le32_to_cpu(r->opp[st->loop_idx].power);
350
-
opp->trans_latency_us =
351
-
le16_to_cpu(r->opp[st->loop_idx].transition_latency_us);
320
+
if (PROTOCOL_REV_MAJOR(p->version) <= 0x3)
321
+
process_response_opp(opp, st->loop_idx, response);
322
+
else
323
+
process_response_opp_v4(p->perf_dom, opp, st->loop_idx,
324
+
response);
352
325
p->perf_dom->opp_count++;
353
326
354
-
dev_dbg(ph->dev, "Level %d Power %d Latency %dus\n",
355
-
opp->perf, opp->power, opp->trans_latency_us);
327
+
dev_dbg(ph->dev, "Level %d Power %d Latency %dus Ifreq %d Index %d\n",
328
+
opp->perf, opp->power, opp->trans_latency_us,
329
+
opp->indicative_freq, opp->level_index);
356
330
357
331
return 0;
358
332
}
359
333
360
334
static int
361
-
scmi_perf_describe_levels_get(const struct scmi_protocol_handle *ph, u32 domain,
362
-
struct perf_dom_info *perf_dom)
335
+
scmi_perf_describe_levels_get(const struct scmi_protocol_handle *ph,
336
+
struct perf_dom_info *perf_dom, u32 version)
363
337
{
364
338
int ret;
365
339
void *iter;
···
401
311
.process_response = iter_perf_levels_process_response,
402
312
};
403
313
struct scmi_perf_ipriv ppriv = {
404
-
.domain = domain,
314
+
.version = version,
405
315
.perf_dom = perf_dom,
406
316
};
407
317
···
423
333
return ret;
424
334
}
425
335
426
-
static int scmi_perf_mb_limits_set(const struct scmi_protocol_handle *ph,
427
-
u32 domain, u32 max_perf, u32 min_perf)
336
+
static int scmi_perf_msg_limits_set(const struct scmi_protocol_handle *ph,
337
+
u32 domain, u32 max_perf, u32 min_perf)
428
338
{
429
339
int ret;
430
340
struct scmi_xfer *t;
···
446
356
return ret;
447
357
}
448
358
449
-
static int scmi_perf_limits_set(const struct scmi_protocol_handle *ph,
450
-
u32 domain, u32 max_perf, u32 min_perf)
359
+
static inline struct perf_dom_info *
360
+
scmi_perf_domain_lookup(const struct scmi_protocol_handle *ph, u32 domain)
451
361
{
452
362
struct scmi_perf_info *pi = ph->get_priv(ph);
453
-
struct perf_dom_info *dom = pi->dom_info + domain;
454
363
455
-
if (PROTOCOL_REV_MAJOR(pi->version) >= 0x3 && !max_perf && !min_perf)
456
-
return -EINVAL;
364
+
if (domain >= pi->num_domains)
365
+
return ERR_PTR(-EINVAL);
457
366
367
+
return pi->dom_info + domain;
368
+
}
369
+
370
+
static int __scmi_perf_limits_set(const struct scmi_protocol_handle *ph,
371
+
struct perf_dom_info *dom, u32 max_perf,
372
+
u32 min_perf)
373
+
{
458
374
if (dom->fc_info && dom->fc_info[PERF_FC_LIMIT].set_addr) {
459
375
struct scmi_fc_info *fci = &dom->fc_info[PERF_FC_LIMIT];
460
376
461
377
trace_scmi_fc_call(SCMI_PROTOCOL_PERF, PERF_LIMITS_SET,
462
-
domain, min_perf, max_perf);
378
+
dom->id, min_perf, max_perf);
463
379
iowrite32(max_perf, fci->set_addr);
464
380
iowrite32(min_perf, fci->set_addr + 4);
465
381
ph->hops->fastchannel_db_ring(fci->set_db);
466
382
return 0;
467
383
}
468
384
469
-
return scmi_perf_mb_limits_set(ph, domain, max_perf, min_perf);
385
+
return scmi_perf_msg_limits_set(ph, dom->id, max_perf, min_perf);
470
386
}
471
387
472
-
static int scmi_perf_mb_limits_get(const struct scmi_protocol_handle *ph,
473
-
u32 domain, u32 *max_perf, u32 *min_perf)
388
+
static int scmi_perf_limits_set(const struct scmi_protocol_handle *ph,
389
+
u32 domain, u32 max_perf, u32 min_perf)
390
+
{
391
+
struct scmi_perf_info *pi = ph->get_priv(ph);
392
+
struct perf_dom_info *dom;
393
+
394
+
dom = scmi_perf_domain_lookup(ph, domain);
395
+
if (IS_ERR(dom))
396
+
return PTR_ERR(dom);
397
+
398
+
if (PROTOCOL_REV_MAJOR(pi->version) >= 0x3 && !max_perf && !min_perf)
399
+
return -EINVAL;
400
+
401
+
if (dom->level_indexing_mode) {
402
+
struct scmi_opp *opp;
403
+
404
+
if (min_perf) {
405
+
opp = xa_load(&dom->opps_by_lvl, min_perf);
406
+
if (!opp)
407
+
return -EIO;
408
+
409
+
min_perf = opp->level_index;
410
+
}
411
+
412
+
if (max_perf) {
413
+
opp = xa_load(&dom->opps_by_lvl, max_perf);
414
+
if (!opp)
415
+
return -EIO;
416
+
417
+
max_perf = opp->level_index;
418
+
}
419
+
}
420
+
421
+
return __scmi_perf_limits_set(ph, dom, max_perf, min_perf);
422
+
}
423
+
424
+
static int scmi_perf_msg_limits_get(const struct scmi_protocol_handle *ph,
425
+
u32 domain, u32 *max_perf, u32 *min_perf)
474
426
{
475
427
int ret;
476
428
struct scmi_xfer *t;
···
537
405
return ret;
538
406
}
539
407
540
-
static int scmi_perf_limits_get(const struct scmi_protocol_handle *ph,
541
-
u32 domain, u32 *max_perf, u32 *min_perf)
408
+
static int __scmi_perf_limits_get(const struct scmi_protocol_handle *ph,
409
+
struct perf_dom_info *dom, u32 *max_perf,
410
+
u32 *min_perf)
542
411
{
543
-
struct scmi_perf_info *pi = ph->get_priv(ph);
544
-
struct perf_dom_info *dom = pi->dom_info + domain;
545
-
546
412
if (dom->fc_info && dom->fc_info[PERF_FC_LIMIT].get_addr) {
547
413
struct scmi_fc_info *fci = &dom->fc_info[PERF_FC_LIMIT];
548
414
549
415
*max_perf = ioread32(fci->get_addr);
550
416
*min_perf = ioread32(fci->get_addr + 4);
551
417
trace_scmi_fc_call(SCMI_PROTOCOL_PERF, PERF_LIMITS_GET,
552
-
domain, *min_perf, *max_perf);
418
+
dom->id, *min_perf, *max_perf);
553
419
return 0;
554
420
}
555
421
556
-
return scmi_perf_mb_limits_get(ph, domain, max_perf, min_perf);
422
+
return scmi_perf_msg_limits_get(ph, dom->id, max_perf, min_perf);
557
423
}
558
424
559
-
static int scmi_perf_mb_level_set(const struct scmi_protocol_handle *ph,
560
-
u32 domain, u32 level, bool poll)
425
+
static int scmi_perf_limits_get(const struct scmi_protocol_handle *ph,
426
+
u32 domain, u32 *max_perf, u32 *min_perf)
427
+
{
428
+
int ret;
429
+
struct perf_dom_info *dom;
430
+
431
+
dom = scmi_perf_domain_lookup(ph, domain);
432
+
if (IS_ERR(dom))
433
+
return PTR_ERR(dom);
434
+
435
+
ret = __scmi_perf_limits_get(ph, dom, max_perf, min_perf);
436
+
if (ret)
437
+
return ret;
438
+
439
+
if (dom->level_indexing_mode) {
440
+
struct scmi_opp *opp;
441
+
442
+
opp = xa_load(&dom->opps_by_idx, *min_perf);
443
+
if (!opp)
444
+
return -EIO;
445
+
446
+
*min_perf = opp->perf;
447
+
448
+
opp = xa_load(&dom->opps_by_idx, *max_perf);
449
+
if (!opp)
450
+
return -EIO;
451
+
452
+
*max_perf = opp->perf;
453
+
}
454
+
455
+
return 0;
456
+
}
457
+
458
+
static int scmi_perf_msg_level_set(const struct scmi_protocol_handle *ph,
459
+
u32 domain, u32 level, bool poll)
561
460
{
562
461
int ret;
563
462
struct scmi_xfer *t;
···
609
446
return ret;
610
447
}
611
448
612
-
static int scmi_perf_level_set(const struct scmi_protocol_handle *ph,
613
-
u32 domain, u32 level, bool poll)
449
+
static int __scmi_perf_level_set(const struct scmi_protocol_handle *ph,
450
+
struct perf_dom_info *dom, u32 level,
451
+
bool poll)
614
452
{
615
-
struct scmi_perf_info *pi = ph->get_priv(ph);
616
-
struct perf_dom_info *dom = pi->dom_info + domain;
617
-
618
453
if (dom->fc_info && dom->fc_info[PERF_FC_LEVEL].set_addr) {
619
454
struct scmi_fc_info *fci = &dom->fc_info[PERF_FC_LEVEL];
620
455
621
456
trace_scmi_fc_call(SCMI_PROTOCOL_PERF, PERF_LEVEL_SET,
622
-
domain, level, 0);
457
+
dom->id, level, 0);
623
458
iowrite32(level, fci->set_addr);
624
459
ph->hops->fastchannel_db_ring(fci->set_db);
625
460
return 0;
626
461
}
627
462
628
-
return scmi_perf_mb_level_set(ph, domain, level, poll);
463
+
return scmi_perf_msg_level_set(ph, dom->id, level, poll);
629
464
}
630
465
631
-
static int scmi_perf_mb_level_get(const struct scmi_protocol_handle *ph,
632
-
u32 domain, u32 *level, bool poll)
466
+
static int scmi_perf_level_set(const struct scmi_protocol_handle *ph,
467
+
u32 domain, u32 level, bool poll)
468
+
{
469
+
struct perf_dom_info *dom;
470
+
471
+
dom = scmi_perf_domain_lookup(ph, domain);
472
+
if (IS_ERR(dom))
473
+
return PTR_ERR(dom);
474
+
475
+
if (dom->level_indexing_mode) {
476
+
struct scmi_opp *opp;
477
+
478
+
opp = xa_load(&dom->opps_by_lvl, level);
479
+
if (!opp)
480
+
return -EIO;
481
+
482
+
level = opp->level_index;
483
+
}
484
+
485
+
return __scmi_perf_level_set(ph, dom, level, poll);
486
+
}
487
+
488
+
static int scmi_perf_msg_level_get(const struct scmi_protocol_handle *ph,
489
+
u32 domain, u32 *level, bool poll)
633
490
{
634
491
int ret;
635
492
struct scmi_xfer *t;
···
670
487
return ret;
671
488
}
672
489
673
-
static int scmi_perf_level_get(const struct scmi_protocol_handle *ph,
674
-
u32 domain, u32 *level, bool poll)
490
+
static int __scmi_perf_level_get(const struct scmi_protocol_handle *ph,
491
+
struct perf_dom_info *dom, u32 *level,
492
+
bool poll)
675
493
{
676
-
struct scmi_perf_info *pi = ph->get_priv(ph);
677
-
struct perf_dom_info *dom = pi->dom_info + domain;
678
-
679
494
if (dom->fc_info && dom->fc_info[PERF_FC_LEVEL].get_addr) {
680
495
*level = ioread32(dom->fc_info[PERF_FC_LEVEL].get_addr);
681
496
trace_scmi_fc_call(SCMI_PROTOCOL_PERF, PERF_LEVEL_GET,
682
-
domain, *level, 0);
497
+
dom->id, *level, 0);
683
498
return 0;
684
499
}
685
500
686
-
return scmi_perf_mb_level_get(ph, domain, level, poll);
501
+
return scmi_perf_msg_level_get(ph, dom->id, level, poll);
502
+
}
503
+
504
+
static int scmi_perf_level_get(const struct scmi_protocol_handle *ph,
505
+
u32 domain, u32 *level, bool poll)
506
+
{
507
+
int ret;
508
+
struct perf_dom_info *dom;
509
+
510
+
dom = scmi_perf_domain_lookup(ph, domain);
511
+
if (IS_ERR(dom))
512
+
return PTR_ERR(dom);
513
+
514
+
ret = __scmi_perf_level_get(ph, dom, level, poll);
515
+
if (ret)
516
+
return ret;
517
+
518
+
if (dom->level_indexing_mode) {
519
+
struct scmi_opp *opp;
520
+
521
+
opp = xa_load(&dom->opps_by_idx, *level);
522
+
if (!opp)
523
+
return -EIO;
524
+
525
+
*level = opp->perf;
526
+
}
527
+
528
+
return 0;
687
529
}
688
530
689
531
static int scmi_perf_level_limits_notify(const struct scmi_protocol_handle *ph,
···
782
574
unsigned long freq;
783
575
struct scmi_opp *opp;
784
576
struct perf_dom_info *dom;
785
-
struct scmi_perf_info *pi = ph->get_priv(ph);
786
577
787
578
domain = scmi_dev_domain_id(dev);
788
579
if (domain < 0)
789
-
return domain;
580
+
return -EINVAL;
790
581
791
-
dom = pi->dom_info + domain;
582
+
dom = scmi_perf_domain_lookup(ph, domain);
583
+
if (IS_ERR(dom))
584
+
return PTR_ERR(dom);
792
585
793
586
for (opp = dom->opp, idx = 0; idx < dom->opp_count; idx++, opp++) {
794
-
freq = opp->perf * dom->mult_factor;
587
+
if (!dom->level_indexing_mode)
588
+
freq = opp->perf * dom->mult_factor;
589
+
else
590
+
freq = opp->indicative_freq * 1000;
795
591
796
592
ret = dev_pm_opp_add(dev, freq, 0);
797
593
if (ret) {
798
594
dev_warn(dev, "failed to add opp %luHz\n", freq);
799
595
800
596
while (idx-- > 0) {
801
-
freq = (--opp)->perf * dom->mult_factor;
597
+
if (!dom->level_indexing_mode)
598
+
freq = (--opp)->perf * dom->mult_factor;
599
+
else
600
+
freq = (--opp)->indicative_freq * 1000;
802
601
dev_pm_opp_remove(dev, freq);
803
602
}
804
603
return ret;
805
604
}
605
+
606
+
dev_dbg(dev, "[%d][%s]:: Registered OPP[%d] %lu\n",
607
+
domain, dom->name, idx, freq);
806
608
}
807
609
return 0;
808
610
}
···
821
603
scmi_dvfs_transition_latency_get(const struct scmi_protocol_handle *ph,
822
604
struct device *dev)
823
605
{
606
+
int domain;
824
607
struct perf_dom_info *dom;
825
-
struct scmi_perf_info *pi = ph->get_priv(ph);
826
-
int domain = scmi_dev_domain_id(dev);
827
608
609
+
domain = scmi_dev_domain_id(dev);
828
610
if (domain < 0)
829
-
return domain;
611
+
return -EINVAL;
830
612
831
-
dom = pi->dom_info + domain;
613
+
dom = scmi_perf_domain_lookup(ph, domain);
614
+
if (IS_ERR(dom))
615
+
return PTR_ERR(dom);
616
+
832
617
/* uS to nS */
833
618
return dom->opp[dom->opp_count - 1].trans_latency_us * 1000;
834
619
}
···
839
618
static int scmi_dvfs_freq_set(const struct scmi_protocol_handle *ph, u32 domain,
840
619
unsigned long freq, bool poll)
841
620
{
842
-
struct scmi_perf_info *pi = ph->get_priv(ph);
843
-
struct perf_dom_info *dom = pi->dom_info + domain;
621
+
unsigned int level;
622
+
struct perf_dom_info *dom;
844
623
845
-
return scmi_perf_level_set(ph, domain, freq / dom->mult_factor, poll);
624
+
dom = scmi_perf_domain_lookup(ph, domain);
625
+
if (IS_ERR(dom))
626
+
return PTR_ERR(dom);
627
+
628
+
if (!dom->level_indexing_mode) {
629
+
level = freq / dom->mult_factor;
630
+
} else {
631
+
struct scmi_opp *opp;
632
+
633
+
opp = LOOKUP_BY_FREQ(dom->opps_by_freq, freq / 1000);
634
+
if (!opp)
635
+
return -EIO;
636
+
637
+
level = opp->level_index;
638
+
}
639
+
640
+
return __scmi_perf_level_set(ph, dom, level, poll);
846
641
}
847
642
848
643
static int scmi_dvfs_freq_get(const struct scmi_protocol_handle *ph, u32 domain,
···
866
629
{
867
630
int ret;
868
631
u32 level;
869
-
struct scmi_perf_info *pi = ph->get_priv(ph);
870
-
struct perf_dom_info *dom = pi->dom_info + domain;
632
+
struct perf_dom_info *dom;
871
633
872
-
ret = scmi_perf_level_get(ph, domain, &level, poll);
873
-
if (!ret)
634
+
dom = scmi_perf_domain_lookup(ph, domain);
635
+
if (IS_ERR(dom))
636
+
return PTR_ERR(dom);
637
+
638
+
ret = __scmi_perf_level_get(ph, dom, &level, poll);
639
+
if (ret)
640
+
return ret;
641
+
642
+
if (!dom->level_indexing_mode) {
874
643
*freq = level * dom->mult_factor;
644
+
} else {
645
+
struct scmi_opp *opp;
646
+
647
+
opp = xa_load(&dom->opps_by_idx, level);
648
+
if (!opp)
649
+
return -EIO;
650
+
651
+
*freq = opp->indicative_freq * 1000;
652
+
}
875
653
876
654
return ret;
877
655
}
···
895
643
u32 domain, unsigned long *freq,
896
644
unsigned long *power)
897
645
{
898
-
struct scmi_perf_info *pi = ph->get_priv(ph);
899
646
struct perf_dom_info *dom;
900
647
unsigned long opp_freq;
901
648
int idx, ret = -EINVAL;
902
649
struct scmi_opp *opp;
903
650
904
-
dom = pi->dom_info + domain;
905
-
if (!dom)
906
-
return -EIO;
651
+
dom = scmi_perf_domain_lookup(ph, domain);
652
+
if (IS_ERR(dom))
653
+
return PTR_ERR(dom);
907
654
908
655
for (opp = dom->opp, idx = 0; idx < dom->opp_count; idx++, opp++) {
909
-
opp_freq = opp->perf * dom->mult_factor;
656
+
if (!dom->level_indexing_mode)
657
+
opp_freq = opp->perf * dom->mult_factor;
658
+
else
659
+
opp_freq = opp->indicative_freq * 1000;
660
+
910
661
if (opp_freq < *freq)
911
662
continue;
912
663
···
925
670
static bool scmi_fast_switch_possible(const struct scmi_protocol_handle *ph,
926
671
struct device *dev)
927
672
{
673
+
int domain;
928
674
struct perf_dom_info *dom;
929
-
struct scmi_perf_info *pi = ph->get_priv(ph);
930
675
931
-
dom = pi->dom_info + scmi_dev_domain_id(dev);
676
+
domain = scmi_dev_domain_id(dev);
677
+
if (domain < 0)
678
+
return false;
679
+
680
+
dom = scmi_perf_domain_lookup(ph, domain);
681
+
if (IS_ERR(dom))
682
+
return false;
932
683
933
684
return dom->fc_info && dom->fc_info[PERF_FC_LEVEL].set_addr;
934
685
}
···
1092
831
for (domain = 0; domain < pinfo->num_domains; domain++) {
1093
832
struct perf_dom_info *dom = pinfo->dom_info + domain;
1094
833
1095
-
scmi_perf_domain_attributes_get(ph, domain, dom, version);
1096
-
scmi_perf_describe_levels_get(ph, domain, dom);
834
+
dom->id = domain;
835
+
scmi_perf_domain_attributes_get(ph, dom, version);
836
+
scmi_perf_describe_levels_get(ph, dom, version);
1097
837
1098
838
if (dom->perf_fastchannels)
1099
-
scmi_perf_domain_init_fc(ph, domain, &dom->fc_info);
839
+
scmi_perf_domain_init_fc(ph, dom->id, &dom->fc_info);
1100
840
}
841
+
842
+
ret = devm_add_action_or_reset(ph->dev, scmi_perf_xa_destroy, pinfo);
843
+
if (ret)
844
+
return ret;
1101
845
1102
846
pinfo->version = version;
1103
847
+101
-17
drivers/firmware/imx/imx-scu-irq.c
+101
-17
drivers/firmware/imx/imx-scu-irq.c
···
1
1
// SPDX-License-Identifier: GPL-2.0+
2
2
/*
3
-
* Copyright 2019 NXP
3
+
* Copyright 2019,2023 NXP
4
4
*
5
5
* Implementation of the SCU IRQ functions using MU.
6
6
*
···
9
9
#include <dt-bindings/firmware/imx/rsrc.h>
10
10
#include <linux/firmware/imx/ipc.h>
11
11
#include <linux/firmware/imx/sci.h>
12
+
#include <linux/kobject.h>
12
13
#include <linux/mailbox_client.h>
13
14
#include <linux/suspend.h>
15
+
#include <linux/sysfs.h>
14
16
15
17
#define IMX_SC_IRQ_FUNC_ENABLE 1
16
18
#define IMX_SC_IRQ_FUNC_STATUS 2
17
-
#define IMX_SC_IRQ_NUM_GROUP 4
19
+
#define IMX_SC_IRQ_NUM_GROUP 9
18
20
19
21
static u32 mu_resource_id;
20
22
···
42
40
u8 enable;
43
41
} __packed;
44
42
43
+
struct scu_wakeup {
44
+
u32 mask;
45
+
u32 wakeup_src;
46
+
bool valid;
47
+
};
48
+
49
+
/* Sysfs functions */
50
+
static struct kobject *wakeup_obj;
51
+
static ssize_t wakeup_source_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf);
52
+
static struct kobj_attribute wakeup_source_attr =
53
+
__ATTR(wakeup_src, 0660, wakeup_source_show, NULL);
54
+
55
+
static struct scu_wakeup scu_irq_wakeup[IMX_SC_IRQ_NUM_GROUP];
56
+
45
57
static struct imx_sc_ipc *imx_sc_irq_ipc_handle;
46
58
static struct work_struct imx_sc_irq_work;
47
-
static ATOMIC_NOTIFIER_HEAD(imx_scu_irq_notifier_chain);
59
+
static BLOCKING_NOTIFIER_HEAD(imx_scu_irq_notifier_chain);
48
60
49
61
int imx_scu_irq_register_notifier(struct notifier_block *nb)
50
62
{
51
-
return atomic_notifier_chain_register(
63
+
return blocking_notifier_chain_register(
52
64
&imx_scu_irq_notifier_chain, nb);
53
65
}
54
66
EXPORT_SYMBOL(imx_scu_irq_register_notifier);
55
67
56
68
int imx_scu_irq_unregister_notifier(struct notifier_block *nb)
57
69
{
58
-
return atomic_notifier_chain_unregister(
70
+
return blocking_notifier_chain_unregister(
59
71
&imx_scu_irq_notifier_chain, nb);
60
72
}
61
73
EXPORT_SYMBOL(imx_scu_irq_unregister_notifier);
62
74
63
75
static int imx_scu_irq_notifier_call_chain(unsigned long status, u8 *group)
64
76
{
65
-
return atomic_notifier_call_chain(&imx_scu_irq_notifier_chain,
77
+
return blocking_notifier_call_chain(&imx_scu_irq_notifier_chain,
66
78
status, (void *)group);
67
79
}
68
80
69
81
static void imx_scu_irq_work_handler(struct work_struct *work)
70
82
{
71
-
struct imx_sc_msg_irq_get_status msg;
72
-
struct imx_sc_rpc_msg *hdr = &msg.hdr;
73
83
u32 irq_status;
74
84
int ret;
75
85
u8 i;
76
86
77
87
for (i = 0; i < IMX_SC_IRQ_NUM_GROUP; i++) {
78
-
hdr->ver = IMX_SC_RPC_VERSION;
79
-
hdr->svc = IMX_SC_RPC_SVC_IRQ;
80
-
hdr->func = IMX_SC_IRQ_FUNC_STATUS;
81
-
hdr->size = 2;
88
+
if (scu_irq_wakeup[i].mask) {
89
+
scu_irq_wakeup[i].valid = false;
90
+
scu_irq_wakeup[i].wakeup_src = 0;
91
+
}
82
92
83
-
msg.data.req.resource = mu_resource_id;
84
-
msg.data.req.group = i;
85
-
86
-
ret = imx_scu_call_rpc(imx_sc_irq_ipc_handle, &msg, true);
93
+
ret = imx_scu_irq_get_status(i, &irq_status);
87
94
if (ret) {
88
95
pr_err("get irq group %d status failed, ret %d\n",
89
96
i, ret);
90
97
return;
91
98
}
92
99
93
-
irq_status = msg.data.resp.status;
94
100
if (!irq_status)
95
101
continue;
102
+
if (scu_irq_wakeup[i].mask & irq_status) {
103
+
scu_irq_wakeup[i].valid = true;
104
+
scu_irq_wakeup[i].wakeup_src = irq_status & scu_irq_wakeup[i].mask;
105
+
} else {
106
+
scu_irq_wakeup[i].wakeup_src = irq_status;
107
+
}
96
108
97
109
pm_system_wakeup();
98
110
imx_scu_irq_notifier_call_chain(irq_status, &i);
99
111
}
100
112
}
113
+
114
+
int imx_scu_irq_get_status(u8 group, u32 *irq_status)
115
+
{
116
+
struct imx_sc_msg_irq_get_status msg;
117
+
struct imx_sc_rpc_msg *hdr = &msg.hdr;
118
+
int ret;
119
+
120
+
hdr->ver = IMX_SC_RPC_VERSION;
121
+
hdr->svc = IMX_SC_RPC_SVC_IRQ;
122
+
hdr->func = IMX_SC_IRQ_FUNC_STATUS;
123
+
hdr->size = 2;
124
+
125
+
msg.data.req.resource = mu_resource_id;
126
+
msg.data.req.group = group;
127
+
128
+
ret = imx_scu_call_rpc(imx_sc_irq_ipc_handle, &msg, true);
129
+
if (ret)
130
+
return ret;
131
+
132
+
if (irq_status)
133
+
*irq_status = msg.data.resp.status;
134
+
135
+
return 0;
136
+
}
137
+
EXPORT_SYMBOL(imx_scu_irq_get_status);
101
138
102
139
int imx_scu_irq_group_enable(u8 group, u32 mask, u8 enable)
103
140
{
···
162
121
pr_err("enable irq failed, group %d, mask %d, ret %d\n",
163
122
group, mask, ret);
164
123
124
+
if (enable)
125
+
scu_irq_wakeup[group].mask |= mask;
126
+
else
127
+
scu_irq_wakeup[group].mask &= ~mask;
128
+
165
129
return ret;
166
130
}
167
131
EXPORT_SYMBOL(imx_scu_irq_group_enable);
···
174
128
static void imx_scu_irq_callback(struct mbox_client *c, void *msg)
175
129
{
176
130
schedule_work(&imx_sc_irq_work);
131
+
}
132
+
133
+
static ssize_t wakeup_source_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
134
+
{
135
+
int i;
136
+
137
+
for (i = 0; i < IMX_SC_IRQ_NUM_GROUP; i++) {
138
+
if (!scu_irq_wakeup[i].wakeup_src)
139
+
continue;
140
+
141
+
if (scu_irq_wakeup[i].valid)
142
+
sprintf(buf, "Wakeup source group = %d, irq = 0x%x\n",
143
+
i, scu_irq_wakeup[i].wakeup_src);
144
+
else
145
+
sprintf(buf, "Spurious SCU wakeup, group = %d, irq = 0x%x\n",
146
+
i, scu_irq_wakeup[i].wakeup_src);
147
+
}
148
+
149
+
return strlen(buf);
177
150
}
178
151
179
152
int imx_scu_enable_general_irq_channel(struct device *dev)
···
233
168
i = 1;
234
169
235
170
mu_resource_id = IMX_SC_R_MU_0A + i;
171
+
172
+
/* Create directory under /sysfs/firmware */
173
+
wakeup_obj = kobject_create_and_add("scu_wakeup_source", firmware_kobj);
174
+
if (!wakeup_obj) {
175
+
ret = -ENOMEM;
176
+
goto free_ch;
177
+
}
178
+
179
+
ret = sysfs_create_file(wakeup_obj, &wakeup_source_attr.attr);
180
+
if (ret) {
181
+
dev_err(dev, "Cannot create wakeup source src file......\n");
182
+
kobject_put(wakeup_obj);
183
+
goto free_ch;
184
+
}
185
+
186
+
return 0;
187
+
188
+
free_ch:
189
+
mbox_free_channel(ch);
236
190
237
191
return ret;
238
192
}
+17
-3
drivers/firmware/imx/imx-scu-soc.c
+17
-3
drivers/firmware/imx/imx-scu-soc.c
···
78
78
return msg.data.resp.id;
79
79
}
80
80
81
+
static const char *imx_scu_soc_name(u32 id)
82
+
{
83
+
switch (id) {
84
+
case 0x1:
85
+
return "i.MX8QM";
86
+
case 0x2:
87
+
return "i.MX8QXP";
88
+
case 0xe:
89
+
return "i.MX8DXL";
90
+
default:
91
+
break;
92
+
}
93
+
94
+
return "NULL";
95
+
}
96
+
81
97
int imx_scu_soc_init(struct device *dev)
82
98
{
83
99
struct soc_device_attribute *soc_dev_attr;
···
129
113
130
114
/* format soc_id value passed from SCU firmware */
131
115
val = id & 0x1f;
132
-
soc_dev_attr->soc_id = devm_kasprintf(dev, GFP_KERNEL, "0x%x", val);
133
-
if (!soc_dev_attr->soc_id)
134
-
return -ENOMEM;
116
+
soc_dev_attr->soc_id = imx_scu_soc_name(val);
135
117
136
118
/* format revision value passed from SCU firmware */
137
119
val = (id >> 5) & 0xf;
+7
-2
drivers/firmware/imx/imx-scu.c
+7
-2
drivers/firmware/imx/imx-scu.c
···
20
20
#include <linux/platform_device.h>
21
21
22
22
#define SCU_MU_CHAN_NUM 8
23
-
#define MAX_RX_TIMEOUT (msecs_to_jiffies(30))
23
+
#define MAX_RX_TIMEOUT (msecs_to_jiffies(3000))
24
24
25
25
struct imx_sc_chan {
26
26
struct imx_sc_ipc *sc_ipc;
···
353
353
},
354
354
.probe = imx_scu_probe,
355
355
};
356
-
builtin_platform_driver(imx_scu_driver);
356
+
357
+
static int __init imx_scu_driver_init(void)
358
+
{
359
+
return platform_driver_register(&imx_scu_driver);
360
+
}
361
+
subsys_initcall_sync(imx_scu_driver_init);
357
362
358
363
MODULE_AUTHOR("Dong Aisheng <aisheng.dong@nxp.com>");
359
364
MODULE_DESCRIPTION("IMX SCU firmware protocol driver");
+2
drivers/firmware/meson/meson_sm.c
+2
drivers/firmware/meson/meson_sm.c
+50
-108
drivers/firmware/qcom_scm.c
+50
-108
drivers/firmware/qcom_scm.c
···
26
26
static bool download_mode = IS_ENABLED(CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT);
27
27
module_param(download_mode, bool, 0);
28
28
29
-
#define SCM_HAS_CORE_CLK BIT(0)
30
-
#define SCM_HAS_IFACE_CLK BIT(1)
31
-
#define SCM_HAS_BUS_CLK BIT(2)
32
-
33
29
struct qcom_scm {
34
30
struct device *dev;
35
31
struct clk *core_clk;
···
347
351
return qcom_scm_set_boot_addr(entry, qcom_scm_cpu_warm_bits);
348
352
return 0;
349
353
}
350
-
EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr);
354
+
EXPORT_SYMBOL_GPL(qcom_scm_set_warm_boot_addr);
351
355
352
356
/**
353
357
* qcom_scm_set_cold_boot_addr() - Set the cold boot address for all cpus
···
360
364
return qcom_scm_set_boot_addr(entry, qcom_scm_cpu_cold_bits);
361
365
return 0;
362
366
}
363
-
EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr);
367
+
EXPORT_SYMBOL_GPL(qcom_scm_set_cold_boot_addr);
364
368
365
369
/**
366
370
* qcom_scm_cpu_power_down() - Power down the cpu
···
382
386
383
387
qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, NULL);
384
388
}
385
-
EXPORT_SYMBOL(qcom_scm_cpu_power_down);
389
+
EXPORT_SYMBOL_GPL(qcom_scm_cpu_power_down);
386
390
387
391
int qcom_scm_set_remote_state(u32 state, u32 id)
388
392
{
···
401
405
402
406
return ret ? : res.result[0];
403
407
}
404
-
EXPORT_SYMBOL(qcom_scm_set_remote_state);
408
+
EXPORT_SYMBOL_GPL(qcom_scm_set_remote_state);
405
409
406
410
static int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
407
411
{
···
511
515
512
516
return ret ? : res.result[0];
513
517
}
514
-
EXPORT_SYMBOL(qcom_scm_pas_init_image);
518
+
EXPORT_SYMBOL_GPL(qcom_scm_pas_init_image);
515
519
516
520
/**
517
521
* qcom_scm_pas_metadata_release() - release metadata context
···
528
532
ctx->phys = 0;
529
533
ctx->size = 0;
530
534
}
531
-
EXPORT_SYMBOL(qcom_scm_pas_metadata_release);
535
+
EXPORT_SYMBOL_GPL(qcom_scm_pas_metadata_release);
532
536
533
537
/**
534
538
* qcom_scm_pas_mem_setup() - Prepare the memory related to a given peripheral
···
567
571
568
572
return ret ? : res.result[0];
569
573
}
570
-
EXPORT_SYMBOL(qcom_scm_pas_mem_setup);
574
+
EXPORT_SYMBOL_GPL(qcom_scm_pas_mem_setup);
571
575
572
576
/**
573
577
* qcom_scm_pas_auth_and_reset() - Authenticate the given peripheral firmware
···
602
606
603
607
return ret ? : res.result[0];
604
608
}
605
-
EXPORT_SYMBOL(qcom_scm_pas_auth_and_reset);
609
+
EXPORT_SYMBOL_GPL(qcom_scm_pas_auth_and_reset);
606
610
607
611
/**
608
612
* qcom_scm_pas_shutdown() - Shut down the remote processor
···
637
641
638
642
return ret ? : res.result[0];
639
643
}
640
-
EXPORT_SYMBOL(qcom_scm_pas_shutdown);
644
+
EXPORT_SYMBOL_GPL(qcom_scm_pas_shutdown);
641
645
642
646
/**
643
647
* qcom_scm_pas_supported() - Check if the peripheral authentication service is
···
666
670
667
671
return ret ? false : !!res.result[0];
668
672
}
669
-
EXPORT_SYMBOL(qcom_scm_pas_supported);
673
+
EXPORT_SYMBOL_GPL(qcom_scm_pas_supported);
670
674
671
675
static int __qcom_scm_pas_mss_reset(struct device *dev, bool reset)
672
676
{
···
728
732
729
733
return ret < 0 ? ret : 0;
730
734
}
731
-
EXPORT_SYMBOL(qcom_scm_io_readl);
735
+
EXPORT_SYMBOL_GPL(qcom_scm_io_readl);
732
736
733
737
int qcom_scm_io_writel(phys_addr_t addr, unsigned int val)
734
738
{
···
743
747
744
748
return qcom_scm_call_atomic(__scm->dev, &desc, NULL);
745
749
}
746
-
EXPORT_SYMBOL(qcom_scm_io_writel);
750
+
EXPORT_SYMBOL_GPL(qcom_scm_io_writel);
747
751
748
752
/**
749
753
* qcom_scm_restore_sec_cfg_available() - Check if secure environment
···
756
760
return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_MP,
757
761
QCOM_SCM_MP_RESTORE_SEC_CFG);
758
762
}
759
-
EXPORT_SYMBOL(qcom_scm_restore_sec_cfg_available);
763
+
EXPORT_SYMBOL_GPL(qcom_scm_restore_sec_cfg_available);
760
764
761
765
int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare)
762
766
{
···
775
779
776
780
return ret ? : res.result[0];
777
781
}
778
-
EXPORT_SYMBOL(qcom_scm_restore_sec_cfg);
782
+
EXPORT_SYMBOL_GPL(qcom_scm_restore_sec_cfg);
779
783
780
784
int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size)
781
785
{
···
796
800
797
801
return ret ? : res.result[1];
798
802
}
799
-
EXPORT_SYMBOL(qcom_scm_iommu_secure_ptbl_size);
803
+
EXPORT_SYMBOL_GPL(qcom_scm_iommu_secure_ptbl_size);
800
804
801
805
int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare)
802
806
{
···
820
824
821
825
return ret;
822
826
}
823
-
EXPORT_SYMBOL(qcom_scm_iommu_secure_ptbl_init);
827
+
EXPORT_SYMBOL_GPL(qcom_scm_iommu_secure_ptbl_init);
824
828
825
829
int qcom_scm_iommu_set_cp_pool_size(u32 spare, u32 size)
826
830
{
···
835
839
836
840
return qcom_scm_call(__scm->dev, &desc, NULL);
837
841
}
838
-
EXPORT_SYMBOL(qcom_scm_iommu_set_cp_pool_size);
842
+
EXPORT_SYMBOL_GPL(qcom_scm_iommu_set_cp_pool_size);
839
843
840
844
int qcom_scm_mem_protect_video_var(u32 cp_start, u32 cp_size,
841
845
u32 cp_nonpixel_start,
···
859
863
860
864
return ret ? : res.result[0];
861
865
}
862
-
EXPORT_SYMBOL(qcom_scm_mem_protect_video_var);
866
+
EXPORT_SYMBOL_GPL(qcom_scm_mem_protect_video_var);
863
867
864
868
static int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region,
865
869
size_t mem_sz, phys_addr_t src, size_t src_sz,
···
968
972
*srcvm = next_vm;
969
973
return 0;
970
974
}
971
-
EXPORT_SYMBOL(qcom_scm_assign_mem);
975
+
EXPORT_SYMBOL_GPL(qcom_scm_assign_mem);
972
976
973
977
/**
974
978
* qcom_scm_ocmem_lock_available() - is OCMEM lock/unlock interface available
···
978
982
return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_OCMEM,
979
983
QCOM_SCM_OCMEM_LOCK_CMD);
980
984
}
981
-
EXPORT_SYMBOL(qcom_scm_ocmem_lock_available);
985
+
EXPORT_SYMBOL_GPL(qcom_scm_ocmem_lock_available);
982
986
983
987
/**
984
988
* qcom_scm_ocmem_lock() - call OCMEM lock interface to assign an OCMEM
···
1004
1008
1005
1009
return qcom_scm_call(__scm->dev, &desc, NULL);
1006
1010
}
1007
-
EXPORT_SYMBOL(qcom_scm_ocmem_lock);
1011
+
EXPORT_SYMBOL_GPL(qcom_scm_ocmem_lock);
1008
1012
1009
1013
/**
1010
1014
* qcom_scm_ocmem_unlock() - call OCMEM unlock interface to release an OCMEM
···
1027
1031
1028
1032
return qcom_scm_call(__scm->dev, &desc, NULL);
1029
1033
}
1030
-
EXPORT_SYMBOL(qcom_scm_ocmem_unlock);
1034
+
EXPORT_SYMBOL_GPL(qcom_scm_ocmem_unlock);
1031
1035
1032
1036
/**
1033
1037
* qcom_scm_ice_available() - Is the ICE key programming interface available?
···
1042
1046
__qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_ES,
1043
1047
QCOM_SCM_ES_CONFIG_SET_ICE_KEY);
1044
1048
}
1045
-
EXPORT_SYMBOL(qcom_scm_ice_available);
1049
+
EXPORT_SYMBOL_GPL(qcom_scm_ice_available);
1046
1050
1047
1051
/**
1048
1052
* qcom_scm_ice_invalidate_key() - Invalidate an inline encryption key
···
1068
1072
1069
1073
return qcom_scm_call(__scm->dev, &desc, NULL);
1070
1074
}
1071
-
EXPORT_SYMBOL(qcom_scm_ice_invalidate_key);
1075
+
EXPORT_SYMBOL_GPL(qcom_scm_ice_invalidate_key);
1072
1076
1073
1077
/**
1074
1078
* qcom_scm_ice_set_key() - Set an inline encryption key
···
1134
1138
dma_free_coherent(__scm->dev, key_size, keybuf, key_phys);
1135
1139
return ret;
1136
1140
}
1137
-
EXPORT_SYMBOL(qcom_scm_ice_set_key);
1141
+
EXPORT_SYMBOL_GPL(qcom_scm_ice_set_key);
1138
1142
1139
1143
/**
1140
1144
* qcom_scm_hdcp_available() - Check if secure environment supports HDCP.
···
1156
1160
1157
1161
return avail;
1158
1162
}
1159
-
EXPORT_SYMBOL(qcom_scm_hdcp_available);
1163
+
EXPORT_SYMBOL_GPL(qcom_scm_hdcp_available);
1160
1164
1161
1165
/**
1162
1166
* qcom_scm_hdcp_req() - Send HDCP request.
···
1203
1207
1204
1208
return ret;
1205
1209
}
1206
-
EXPORT_SYMBOL(qcom_scm_hdcp_req);
1210
+
EXPORT_SYMBOL_GPL(qcom_scm_hdcp_req);
1207
1211
1208
1212
int qcom_scm_iommu_set_pt_format(u32 sec_id, u32 ctx_num, u32 pt_fmt)
1209
1213
{
···
1219
1223
1220
1224
return qcom_scm_call(__scm->dev, &desc, NULL);
1221
1225
}
1222
-
EXPORT_SYMBOL(qcom_scm_iommu_set_pt_format);
1226
+
EXPORT_SYMBOL_GPL(qcom_scm_iommu_set_pt_format);
1223
1227
1224
1228
int qcom_scm_qsmmu500_wait_safe_toggle(bool en)
1225
1229
{
···
1235
1239
1236
1240
return qcom_scm_call_atomic(__scm->dev, &desc, NULL);
1237
1241
}
1238
-
EXPORT_SYMBOL(qcom_scm_qsmmu500_wait_safe_toggle);
1242
+
EXPORT_SYMBOL_GPL(qcom_scm_qsmmu500_wait_safe_toggle);
1239
1243
1240
1244
bool qcom_scm_lmh_dcvsh_available(void)
1241
1245
{
1242
1246
return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_LMH, QCOM_SCM_LMH_LIMIT_DCVSH);
1243
1247
}
1244
-
EXPORT_SYMBOL(qcom_scm_lmh_dcvsh_available);
1248
+
EXPORT_SYMBOL_GPL(qcom_scm_lmh_dcvsh_available);
1245
1249
1246
1250
int qcom_scm_lmh_profile_change(u32 profile_id)
1247
1251
{
···
1255
1259
1256
1260
return qcom_scm_call(__scm->dev, &desc, NULL);
1257
1261
}
1258
-
EXPORT_SYMBOL(qcom_scm_lmh_profile_change);
1262
+
EXPORT_SYMBOL_GPL(qcom_scm_lmh_profile_change);
1259
1263
1260
1264
int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val,
1261
1265
u64 limit_node, u32 node_id, u64 version)
···
1293
1297
dma_free_coherent(__scm->dev, payload_size, payload_buf, payload_phys);
1294
1298
return ret;
1295
1299
}
1296
-
EXPORT_SYMBOL(qcom_scm_lmh_dcvsh);
1300
+
EXPORT_SYMBOL_GPL(qcom_scm_lmh_dcvsh);
1297
1301
1298
1302
static int qcom_scm_find_dload_address(struct device *dev, u64 *addr)
1299
1303
{
···
1328
1332
{
1329
1333
return !!__scm;
1330
1334
}
1331
-
EXPORT_SYMBOL(qcom_scm_is_available);
1335
+
EXPORT_SYMBOL_GPL(qcom_scm_is_available);
1332
1336
1333
1337
static int qcom_scm_assert_valid_wq_ctx(u32 wq_ctx)
1334
1338
{
···
1401
1405
static int qcom_scm_probe(struct platform_device *pdev)
1402
1406
{
1403
1407
struct qcom_scm *scm;
1404
-
unsigned long clks;
1405
1408
int irq, ret;
1406
1409
1407
1410
scm = devm_kzalloc(&pdev->dev, sizeof(*scm), GFP_KERNEL);
···
1413
1418
1414
1419
mutex_init(&scm->scm_bw_lock);
1415
1420
1416
-
clks = (unsigned long)of_device_get_match_data(&pdev->dev);
1417
-
1418
1421
scm->path = devm_of_icc_get(&pdev->dev, NULL);
1419
1422
if (IS_ERR(scm->path))
1420
1423
return dev_err_probe(&pdev->dev, PTR_ERR(scm->path),
1421
1424
"failed to acquire interconnect path\n");
1422
1425
1423
-
scm->core_clk = devm_clk_get(&pdev->dev, "core");
1424
-
if (IS_ERR(scm->core_clk)) {
1425
-
if (PTR_ERR(scm->core_clk) == -EPROBE_DEFER)
1426
-
return PTR_ERR(scm->core_clk);
1426
+
scm->core_clk = devm_clk_get_optional(&pdev->dev, "core");
1427
+
if (IS_ERR(scm->core_clk))
1428
+
return PTR_ERR(scm->core_clk);
1427
1429
1428
-
if (clks & SCM_HAS_CORE_CLK) {
1429
-
dev_err(&pdev->dev, "failed to acquire core clk\n");
1430
-
return PTR_ERR(scm->core_clk);
1431
-
}
1430
+
scm->iface_clk = devm_clk_get_optional(&pdev->dev, "iface");
1431
+
if (IS_ERR(scm->iface_clk))
1432
+
return PTR_ERR(scm->iface_clk);
1432
1433
1433
-
scm->core_clk = NULL;
1434
-
}
1435
-
1436
-
scm->iface_clk = devm_clk_get(&pdev->dev, "iface");
1437
-
if (IS_ERR(scm->iface_clk)) {
1438
-
if (PTR_ERR(scm->iface_clk) == -EPROBE_DEFER)
1439
-
return PTR_ERR(scm->iface_clk);
1440
-
1441
-
if (clks & SCM_HAS_IFACE_CLK) {
1442
-
dev_err(&pdev->dev, "failed to acquire iface clk\n");
1443
-
return PTR_ERR(scm->iface_clk);
1444
-
}
1445
-
1446
-
scm->iface_clk = NULL;
1447
-
}
1448
-
1449
-
scm->bus_clk = devm_clk_get(&pdev->dev, "bus");
1450
-
if (IS_ERR(scm->bus_clk)) {
1451
-
if (PTR_ERR(scm->bus_clk) == -EPROBE_DEFER)
1452
-
return PTR_ERR(scm->bus_clk);
1453
-
1454
-
if (clks & SCM_HAS_BUS_CLK) {
1455
-
dev_err(&pdev->dev, "failed to acquire bus clk\n");
1456
-
return PTR_ERR(scm->bus_clk);
1457
-
}
1458
-
1459
-
scm->bus_clk = NULL;
1460
-
}
1434
+
scm->bus_clk = devm_clk_get_optional(&pdev->dev, "bus");
1435
+
if (IS_ERR(scm->bus_clk))
1436
+
return PTR_ERR(scm->bus_clk);
1461
1437
1462
1438
scm->reset.ops = &qcom_scm_pas_reset_ops;
1463
1439
scm->reset.nr_resets = 1;
···
1478
1512
}
1479
1513
1480
1514
static const struct of_device_id qcom_scm_dt_match[] = {
1481
-
{ .compatible = "qcom,scm-apq8064",
1482
-
/* FIXME: This should have .data = (void *) SCM_HAS_CORE_CLK */
1483
-
},
1484
-
{ .compatible = "qcom,scm-apq8084", .data = (void *)(SCM_HAS_CORE_CLK |
1485
-
SCM_HAS_IFACE_CLK |
1486
-
SCM_HAS_BUS_CLK)
1487
-
},
1488
-
{ .compatible = "qcom,scm-ipq4019" },
1489
-
{ .compatible = "qcom,scm-mdm9607", .data = (void *)(SCM_HAS_CORE_CLK |
1490
-
SCM_HAS_IFACE_CLK |
1491
-
SCM_HAS_BUS_CLK) },
1492
-
{ .compatible = "qcom,scm-msm8660", .data = (void *) SCM_HAS_CORE_CLK },
1493
-
{ .compatible = "qcom,scm-msm8960", .data = (void *) SCM_HAS_CORE_CLK },
1494
-
{ .compatible = "qcom,scm-msm8916", .data = (void *)(SCM_HAS_CORE_CLK |
1495
-
SCM_HAS_IFACE_CLK |
1496
-
SCM_HAS_BUS_CLK)
1497
-
},
1498
-
{ .compatible = "qcom,scm-msm8953", .data = (void *)(SCM_HAS_CORE_CLK |
1499
-
SCM_HAS_IFACE_CLK |
1500
-
SCM_HAS_BUS_CLK)
1501
-
},
1502
-
{ .compatible = "qcom,scm-msm8974", .data = (void *)(SCM_HAS_CORE_CLK |
1503
-
SCM_HAS_IFACE_CLK |
1504
-
SCM_HAS_BUS_CLK)
1505
-
},
1506
-
{ .compatible = "qcom,scm-msm8976", .data = (void *)(SCM_HAS_CORE_CLK |
1507
-
SCM_HAS_IFACE_CLK |
1508
-
SCM_HAS_BUS_CLK)
1509
-
},
1510
-
{ .compatible = "qcom,scm-msm8994" },
1511
-
{ .compatible = "qcom,scm-msm8996" },
1512
-
{ .compatible = "qcom,scm-sm6375", .data = (void *)SCM_HAS_CORE_CLK },
1513
1515
{ .compatible = "qcom,scm" },
1516
+
1517
+
/* Legacy entries kept for backwards compatibility */
1518
+
{ .compatible = "qcom,scm-apq8064" },
1519
+
{ .compatible = "qcom,scm-apq8084" },
1520
+
{ .compatible = "qcom,scm-ipq4019" },
1521
+
{ .compatible = "qcom,scm-msm8953" },
1522
+
{ .compatible = "qcom,scm-msm8974" },
1523
+
{ .compatible = "qcom,scm-msm8996" },
1514
1524
{}
1515
1525
};
1516
1526
MODULE_DEVICE_TABLE(of, qcom_scm_dt_match);
+9
-40
drivers/firmware/ti_sci.c
+9
-40
drivers/firmware/ti_sci.c
···
97
97
* @node: list head
98
98
* @host_id: Host ID
99
99
* @users: Number of users of this instance
100
-
* @is_suspending: Flag set to indicate in suspend path.
101
100
*/
102
101
struct ti_sci_info {
103
102
struct device *dev;
···
115
116
u8 host_id;
116
117
/* protected by ti_sci_list_mutex */
117
118
int users;
118
-
bool is_suspending;
119
119
};
120
120
121
121
#define cl_to_ti_sci_info(c) container_of(c, struct ti_sci_info, cl)
···
416
418
417
419
ret = 0;
418
420
419
-
if (!info->is_suspending) {
421
+
if (system_state <= SYSTEM_RUNNING) {
420
422
/* And we wait for the response. */
421
423
timeout = msecs_to_jiffies(info->desc->max_rx_timeout_ms);
422
424
if (!wait_for_completion_timeout(&xfer->done, timeout))
423
425
ret = -ETIMEDOUT;
424
426
} else {
425
427
/*
426
-
* If we are suspending, we cannot use wait_for_completion_timeout
428
+
* If we are !running, we cannot use wait_for_completion_timeout
427
429
* during noirq phase, so we must manually poll the completion.
428
430
*/
429
431
ret = read_poll_timeout_atomic(try_wait_for_completion, done_state,
···
1976
1978
* @src_index: IRQ source index within the source device
1977
1979
* @dst_id: Device ID of the IRQ destination
1978
1980
* @dst_host_irq: IRQ number of the destination device
1979
-
* @vint_irq: Boolean specifying if this interrupt belongs to
1980
-
* Interrupt Aggregator.
1981
1981
*
1982
1982
* Return: 0 if all went fine, else return appropriate error.
1983
1983
*/
···
2022
2026
* @src_index: IRQ source index within the source device
2023
2027
* @dst_id: Device ID of the IRQ destination
2024
2028
* @dst_host_irq: IRQ number of the destination device
2025
-
* @vint_irq: Boolean specifying if this interrupt belongs to
2026
-
* Interrupt Aggregator.
2027
2029
*
2028
2030
* Return: 0 if all went fine, else return appropriate error.
2029
2031
*/
···
2614
2620
* configuration flags
2615
2621
* @handle: Pointer to TI SCI handle
2616
2622
* @proc_id: Processor ID this request is for
2623
+
* @bootvector: Processor Boot vector (start address)
2617
2624
* @config_flags_set: Configuration flags to be set
2618
2625
* @config_flags_clear: Configuration flags to be cleared.
2619
2626
*
···
2731
2736
}
2732
2737
2733
2738
/**
2734
-
* ti_sci_cmd_get_boot_status() - Command to get the processor boot status
2739
+
* ti_sci_cmd_proc_get_status() - Command to get the processor boot status
2735
2740
* @handle: Pointer to TI SCI handle
2736
2741
* @proc_id: Processor ID this request is for
2742
+
* @bv: Processor Boot vector (start address)
2743
+
* @cfg_flags: Processor specific configuration flags
2744
+
* @ctrl_flags: Processor specific control flags
2745
+
* @sts_flags: Processor specific status flags
2737
2746
*
2738
2747
* Return: 0 if all went well, else returns appropriate error value.
2739
2748
*/
···
3255
3256
* @handle: TISCI handle
3256
3257
* @dev: Device pointer to which the resource is assigned
3257
3258
* @dev_id: TISCI device id to which the resource is assigned
3258
-
* @suub_type: TISCI resource subytpe representing the resource.
3259
+
* @sub_type: TISCI resource subytpe representing the resource.
3259
3260
*
3260
3261
* Return: Pointer to ti_sci_resource if all went well else appropriate
3261
3262
* error pointer.
···
3279
3280
/* call fail OR pass, we should not be here in the first place */
3280
3281
return NOTIFY_BAD;
3281
3282
}
3282
-
3283
-
static void ti_sci_set_is_suspending(struct ti_sci_info *info, bool is_suspending)
3284
-
{
3285
-
info->is_suspending = is_suspending;
3286
-
}
3287
-
3288
-
static int ti_sci_suspend(struct device *dev)
3289
-
{
3290
-
struct ti_sci_info *info = dev_get_drvdata(dev);
3291
-
/*
3292
-
* We must switch operation to polled mode now as drivers and the genpd
3293
-
* layer may make late TI SCI calls to change clock and device states
3294
-
* from the noirq phase of suspend.
3295
-
*/
3296
-
ti_sci_set_is_suspending(info, true);
3297
-
3298
-
return 0;
3299
-
}
3300
-
3301
-
static int ti_sci_resume(struct device *dev)
3302
-
{
3303
-
struct ti_sci_info *info = dev_get_drvdata(dev);
3304
-
3305
-
ti_sci_set_is_suspending(info, false);
3306
-
3307
-
return 0;
3308
-
}
3309
-
3310
-
static DEFINE_SIMPLE_DEV_PM_OPS(ti_sci_pm_ops, ti_sci_suspend, ti_sci_resume);
3311
3283
3312
3284
/* Description for K2G */
3313
3285
static const struct ti_sci_desc ti_sci_pmmc_k2g_desc = {
···
3486
3516
.driver = {
3487
3517
.name = "ti-sci",
3488
3518
.of_match_table = of_match_ptr(ti_sci_of_match),
3489
-
.pm = &ti_sci_pm_ops,
3490
3519
},
3491
3520
};
3492
3521
module_platform_driver(ti_sci_driver);
+1
-2
drivers/genpd/amlogic/meson-ee-pwrc.c
+1
-2
drivers/genpd/amlogic/meson-ee-pwrc.c
···
4
4
* Author: Neil Armstrong <narmstrong@baylibre.com>
5
5
*/
6
6
7
-
#include <linux/of_address.h>
8
7
#include <linux/platform_device.h>
9
8
#include <linux/pm_domain.h>
10
9
#include <linux/bitfield.h>
11
10
#include <linux/regmap.h>
12
11
#include <linux/mfd/syscon.h>
13
-
#include <linux/of_device.h>
12
+
#include <linux/of.h>
14
13
#include <linux/reset-controller.h>
15
14
#include <linux/reset.h>
16
15
#include <linux/clk.h>
+1
-2
drivers/genpd/amlogic/meson-gx-pwrc-vpu.c
+1
-2
drivers/genpd/amlogic/meson-gx-pwrc-vpu.c
···
5
5
* SPDX-License-Identifier: GPL-2.0+
6
6
*/
7
7
8
-
#include <linux/of_address.h>
9
8
#include <linux/platform_device.h>
10
9
#include <linux/pm_domain.h>
11
10
#include <linux/bitfield.h>
12
11
#include <linux/regmap.h>
13
12
#include <linux/mfd/syscon.h>
14
-
#include <linux/of_device.h>
13
+
#include <linux/of.h>
15
14
#include <linux/reset.h>
16
15
#include <linux/clk.h>
17
16
#include <linux/module.h>
+28
-2
drivers/genpd/amlogic/meson-secure-pwrc.c
+28
-2
drivers/genpd/amlogic/meson-secure-pwrc.c
···
7
7
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8
8
9
9
#include <linux/io.h>
10
-
#include <linux/of_device.h>
10
+
#include <linux/of.h>
11
11
#include <linux/platform_device.h>
12
12
#include <linux/pm_domain.h>
13
13
#include <dt-bindings/power/meson-a1-power.h>
14
+
#include <dt-bindings/power/amlogic,c3-pwrc.h>
14
15
#include <dt-bindings/power/meson-s4-power.h>
15
16
#include <linux/arm-smccc.h>
16
17
#include <linux/firmware/meson/meson_sm.h>
···
121
120
SEC_PD(RSA, 0),
122
121
};
123
122
123
+
static struct meson_secure_pwrc_domain_desc c3_pwrc_domains[] = {
124
+
SEC_PD(C3_NNA, 0),
125
+
SEC_PD(C3_AUDIO, GENPD_FLAG_ALWAYS_ON),
126
+
SEC_PD(C3_SDIOA, GENPD_FLAG_ALWAYS_ON),
127
+
SEC_PD(C3_EMMC, GENPD_FLAG_ALWAYS_ON),
128
+
SEC_PD(C3_USB_COMB, GENPD_FLAG_ALWAYS_ON),
129
+
SEC_PD(C3_SDCARD, GENPD_FLAG_ALWAYS_ON),
130
+
SEC_PD(C3_ETH, GENPD_FLAG_ALWAYS_ON),
131
+
SEC_PD(C3_GE2D, GENPD_FLAG_ALWAYS_ON),
132
+
SEC_PD(C3_CVE, GENPD_FLAG_ALWAYS_ON),
133
+
SEC_PD(C3_GDC_WRAP, GENPD_FLAG_ALWAYS_ON),
134
+
SEC_PD(C3_ISP_TOP, GENPD_FLAG_ALWAYS_ON),
135
+
SEC_PD(C3_MIPI_ISP_WRAP, GENPD_FLAG_ALWAYS_ON),
136
+
SEC_PD(C3_VCODEC, 0),
137
+
};
138
+
124
139
static struct meson_secure_pwrc_domain_desc s4_pwrc_domains[] = {
125
140
SEC_PD(S4_DOS_HEVC, 0),
126
141
SEC_PD(S4_DOS_VDEC, 0),
···
196
179
for (i = 0 ; i < match->count ; ++i) {
197
180
struct meson_secure_pwrc_domain *dom = &pwrc->domains[i];
198
181
199
-
if (!match->domains[i].index)
182
+
if (!match->domains[i].name)
200
183
continue;
201
184
202
185
dom->pwrc = pwrc;
···
219
202
.count = ARRAY_SIZE(a1_pwrc_domains),
220
203
};
221
204
205
+
static struct meson_secure_pwrc_domain_data amlogic_secure_c3_pwrc_data = {
206
+
.domains = c3_pwrc_domains,
207
+
.count = ARRAY_SIZE(c3_pwrc_domains),
208
+
};
209
+
222
210
static struct meson_secure_pwrc_domain_data meson_secure_s4_pwrc_data = {
223
211
.domains = s4_pwrc_domains,
224
212
.count = ARRAY_SIZE(s4_pwrc_domains),
···
233
211
{
234
212
.compatible = "amlogic,meson-a1-pwrc",
235
213
.data = &meson_secure_a1_pwrc_data,
214
+
},
215
+
{
216
+
.compatible = "amlogic,c3-pwrc",
217
+
.data = &amlogic_secure_c3_pwrc_data,
236
218
},
237
219
{
238
220
.compatible = "amlogic,meson-s4-pwrc",
-1
drivers/genpd/bcm/bcm-pmb.c
-1
drivers/genpd/bcm/bcm-pmb.c
-1
drivers/genpd/bcm/bcm63xx-power.c
-1
drivers/genpd/bcm/bcm63xx-power.c
+1
-1
drivers/genpd/bcm/raspberrypi-power.c
+1
-1
drivers/genpd/bcm/raspberrypi-power.c
+1
-1
drivers/genpd/imx/gpcv2.c
+1
-1
drivers/genpd/imx/gpcv2.c
+2
-1
drivers/genpd/imx/imx8m-blk-ctrl.c
+2
-1
drivers/genpd/imx/imx8m-blk-ctrl.c
···
8
8
#include <linux/device.h>
9
9
#include <linux/interconnect.h>
10
10
#include <linux/module.h>
11
-
#include <linux/of_device.h>
11
+
#include <linux/of.h>
12
+
#include <linux/of_platform.h>
12
13
#include <linux/platform_device.h>
13
14
#include <linux/pm_domain.h>
14
15
#include <linux/pm_runtime.h>
+1
-1
drivers/genpd/imx/imx8mp-blk-ctrl.c
+1
-1
drivers/genpd/imx/imx8mp-blk-ctrl.c
+16
-1
drivers/genpd/imx/imx93-blk-ctrl.c
+16
-1
drivers/genpd/imx/imx93-blk-ctrl.c
···
6
6
#include <linux/clk.h>
7
7
#include <linux/device.h>
8
8
#include <linux/module.h>
9
-
#include <linux/of_device.h>
9
+
#include <linux/of.h>
10
10
#include <linux/platform_device.h>
11
11
#include <linux/pm_domain.h>
12
12
#include <linux/pm_runtime.h>
···
187
187
return 0;
188
188
}
189
189
190
+
static struct lock_class_key blk_ctrl_genpd_lock_class;
191
+
190
192
static int imx93_blk_ctrl_probe(struct platform_device *pdev)
191
193
{
192
194
struct device *dev = &pdev->dev;
···
270
268
dev_err_probe(dev, ret, "failed to init power domain\n");
271
269
goto cleanup_pds;
272
270
}
271
+
272
+
/*
273
+
* We use runtime PM to trigger power on/off of the upstream GPC
274
+
* domain, as a strict hierarchical parent/child power domain
275
+
* setup doesn't allow us to meet the sequencing requirements.
276
+
* This means we have nested locking of genpd locks, without the
277
+
* nesting being visible at the genpd level, so we need a
278
+
* separate lock class to make lockdep aware of the fact that
279
+
* this are separate domain locks that can be nested without a
280
+
* self-deadlock.
281
+
*/
282
+
lockdep_set_class(&domain->genpd.mlock,
283
+
&blk_ctrl_genpd_lock_class);
273
284
274
285
bc->onecell_data.domains[i] = &domain->genpd;
275
286
}
+1
-1
drivers/genpd/imx/imx93-pd.c
+1
-1
drivers/genpd/imx/imx93-pd.c
-1
drivers/genpd/qcom/cpr.c
-1
drivers/genpd/qcom/cpr.c
+67
-51
drivers/genpd/qcom/rpmhpd.c
+67
-51
drivers/genpd/qcom/rpmhpd.c
···
9
9
#include <linux/pm_domain.h>
10
10
#include <linux/slab.h>
11
11
#include <linux/of.h>
12
-
#include <linux/of_device.h>
13
12
#include <linux/platform_device.h>
14
13
#include <linux/pm_opp.h>
15
14
#include <soc/qcom/cmd-db.h>
16
15
#include <soc/qcom/rpmh.h>
17
16
#include <dt-bindings/power/qcom-rpmpd.h>
17
+
#include <dt-bindings/power/qcom,rpmhpd.h>
18
18
19
19
#define domain_to_rpmhpd(domain) container_of(domain, struct rpmhpd, pd)
20
20
···
307
307
.num_pds = ARRAY_SIZE(sdx65_rpmhpds),
308
308
};
309
309
310
+
/* SDX75 RPMH powerdomains */
311
+
static struct rpmhpd *sdx75_rpmhpds[] = {
312
+
[RPMHPD_CX] = &cx,
313
+
[RPMHPD_CX_AO] = &cx_ao,
314
+
[RPMHPD_MSS] = &mss,
315
+
[RPMHPD_MX] = &mx,
316
+
[RPMHPD_MX_AO] = &mx_ao,
317
+
[RPMHPD_MXC] = &mxc,
318
+
};
319
+
320
+
static const struct rpmhpd_desc sdx75_desc = {
321
+
.rpmhpds = sdx75_rpmhpds,
322
+
.num_pds = ARRAY_SIZE(sdx75_rpmhpds),
323
+
};
324
+
310
325
/* SM6350 RPMH powerdomains */
311
326
static struct rpmhpd *sm6350_rpmhpds[] = {
312
327
[SM6350_CX] = &cx_w_mx_parent,
···
374
359
375
360
/* SM8250 RPMH powerdomains */
376
361
static struct rpmhpd *sm8250_rpmhpds[] = {
377
-
[SM8250_CX] = &cx_w_mx_parent,
378
-
[SM8250_CX_AO] = &cx_ao_w_mx_parent,
379
-
[SM8250_EBI] = &ebi,
380
-
[SM8250_GFX] = &gfx,
381
-
[SM8250_LCX] = &lcx,
382
-
[SM8250_LMX] = &lmx,
383
-
[SM8250_MMCX] = &mmcx,
384
-
[SM8250_MMCX_AO] = &mmcx_ao,
385
-
[SM8250_MX] = &mx,
386
-
[SM8250_MX_AO] = &mx_ao,
362
+
[RPMHPD_CX] = &cx_w_mx_parent,
363
+
[RPMHPD_CX_AO] = &cx_ao_w_mx_parent,
364
+
[RPMHPD_EBI] = &ebi,
365
+
[RPMHPD_GFX] = &gfx,
366
+
[RPMHPD_LCX] = &lcx,
367
+
[RPMHPD_LMX] = &lmx,
368
+
[RPMHPD_MMCX] = &mmcx,
369
+
[RPMHPD_MMCX_AO] = &mmcx_ao,
370
+
[RPMHPD_MX] = &mx,
371
+
[RPMHPD_MX_AO] = &mx_ao,
387
372
};
388
373
389
374
static const struct rpmhpd_desc sm8250_desc = {
···
393
378
394
379
/* SM8350 Power domains */
395
380
static struct rpmhpd *sm8350_rpmhpds[] = {
396
-
[SM8350_CX] = &cx_w_mx_parent,
397
-
[SM8350_CX_AO] = &cx_ao_w_mx_parent,
398
-
[SM8350_EBI] = &ebi,
399
-
[SM8350_GFX] = &gfx,
400
-
[SM8350_LCX] = &lcx,
401
-
[SM8350_LMX] = &lmx,
402
-
[SM8350_MMCX] = &mmcx,
403
-
[SM8350_MMCX_AO] = &mmcx_ao,
404
-
[SM8350_MSS] = &mss,
405
-
[SM8350_MX] = &mx,
406
-
[SM8350_MX_AO] = &mx_ao,
407
-
[SM8350_MXC] = &mxc,
408
-
[SM8350_MXC_AO] = &mxc_ao,
381
+
[RPMHPD_CX] = &cx_w_mx_parent,
382
+
[RPMHPD_CX_AO] = &cx_ao_w_mx_parent,
383
+
[RPMHPD_EBI] = &ebi,
384
+
[RPMHPD_GFX] = &gfx,
385
+
[RPMHPD_LCX] = &lcx,
386
+
[RPMHPD_LMX] = &lmx,
387
+
[RPMHPD_MMCX] = &mmcx,
388
+
[RPMHPD_MMCX_AO] = &mmcx_ao,
389
+
[RPMHPD_MSS] = &mss,
390
+
[RPMHPD_MX] = &mx,
391
+
[RPMHPD_MX_AO] = &mx_ao,
392
+
[RPMHPD_MXC] = &mxc,
393
+
[RPMHPD_MXC_AO] = &mxc_ao,
409
394
};
410
395
411
396
static const struct rpmhpd_desc sm8350_desc = {
···
415
400
416
401
/* SM8450 RPMH powerdomains */
417
402
static struct rpmhpd *sm8450_rpmhpds[] = {
418
-
[SM8450_CX] = &cx,
419
-
[SM8450_CX_AO] = &cx_ao,
420
-
[SM8450_EBI] = &ebi,
421
-
[SM8450_GFX] = &gfx,
422
-
[SM8450_LCX] = &lcx,
423
-
[SM8450_LMX] = &lmx,
424
-
[SM8450_MMCX] = &mmcx_w_cx_parent,
425
-
[SM8450_MMCX_AO] = &mmcx_ao_w_cx_parent,
426
-
[SM8450_MSS] = &mss,
427
-
[SM8450_MX] = &mx,
428
-
[SM8450_MX_AO] = &mx_ao,
429
-
[SM8450_MXC] = &mxc,
430
-
[SM8450_MXC_AO] = &mxc_ao,
403
+
[RPMHPD_CX] = &cx,
404
+
[RPMHPD_CX_AO] = &cx_ao,
405
+
[RPMHPD_EBI] = &ebi,
406
+
[RPMHPD_GFX] = &gfx,
407
+
[RPMHPD_LCX] = &lcx,
408
+
[RPMHPD_LMX] = &lmx,
409
+
[RPMHPD_MMCX] = &mmcx_w_cx_parent,
410
+
[RPMHPD_MMCX_AO] = &mmcx_ao_w_cx_parent,
411
+
[RPMHPD_MSS] = &mss,
412
+
[RPMHPD_MX] = &mx,
413
+
[RPMHPD_MX_AO] = &mx_ao,
414
+
[RPMHPD_MXC] = &mxc,
415
+
[RPMHPD_MXC_AO] = &mxc_ao,
431
416
};
432
417
433
418
static const struct rpmhpd_desc sm8450_desc = {
···
437
422
438
423
/* SM8550 RPMH powerdomains */
439
424
static struct rpmhpd *sm8550_rpmhpds[] = {
440
-
[SM8550_CX] = &cx,
441
-
[SM8550_CX_AO] = &cx_ao,
442
-
[SM8550_EBI] = &ebi,
443
-
[SM8550_GFX] = &gfx,
444
-
[SM8550_LCX] = &lcx,
445
-
[SM8550_LMX] = &lmx,
446
-
[SM8550_MMCX] = &mmcx_w_cx_parent,
447
-
[SM8550_MMCX_AO] = &mmcx_ao_w_cx_parent,
448
-
[SM8550_MSS] = &mss,
449
-
[SM8550_MX] = &mx,
450
-
[SM8550_MX_AO] = &mx_ao,
451
-
[SM8550_MXC] = &mxc,
452
-
[SM8550_MXC_AO] = &mxc_ao,
453
-
[SM8550_NSP] = &nsp,
425
+
[RPMHPD_CX] = &cx,
426
+
[RPMHPD_CX_AO] = &cx_ao,
427
+
[RPMHPD_EBI] = &ebi,
428
+
[RPMHPD_GFX] = &gfx,
429
+
[RPMHPD_LCX] = &lcx,
430
+
[RPMHPD_LMX] = &lmx,
431
+
[RPMHPD_MMCX] = &mmcx_w_cx_parent,
432
+
[RPMHPD_MMCX_AO] = &mmcx_ao_w_cx_parent,
433
+
[RPMHPD_MSS] = &mss,
434
+
[RPMHPD_MX] = &mx,
435
+
[RPMHPD_MX_AO] = &mx_ao,
436
+
[RPMHPD_MXC] = &mxc,
437
+
[RPMHPD_MXC_AO] = &mxc_ao,
438
+
[RPMHPD_NSP] = &nsp,
454
439
};
455
440
456
441
static const struct rpmhpd_desc sm8550_desc = {
···
560
545
{ .compatible = "qcom,sdm845-rpmhpd", .data = &sdm845_desc },
561
546
{ .compatible = "qcom,sdx55-rpmhpd", .data = &sdx55_desc},
562
547
{ .compatible = "qcom,sdx65-rpmhpd", .data = &sdx65_desc},
548
+
{ .compatible = "qcom,sdx75-rpmhpd", .data = &sdx75_desc},
563
549
{ .compatible = "qcom,sm6350-rpmhpd", .data = &sm6350_desc },
564
550
{ .compatible = "qcom,sm8150-rpmhpd", .data = &sm8150_desc },
565
551
{ .compatible = "qcom,sm8250-rpmhpd", .data = &sm8250_desc },
+33
-2
drivers/genpd/qcom/rpmpd.c
+33
-2
drivers/genpd/qcom/rpmpd.c
···
8
8
#include <linux/mutex.h>
9
9
#include <linux/pm_domain.h>
10
10
#include <linux/of.h>
11
-
#include <linux/of_device.h>
12
11
#include <linux/platform_device.h>
13
12
#include <linux/pm_opp.h>
14
13
#include <linux/soc/qcom/smd-rpm.h>
···
57
58
struct qcom_smd_rpm *rpm;
58
59
unsigned int max_state;
59
60
__le32 key;
61
+
bool state_synced;
60
62
};
61
63
62
64
struct rpmpd_desc {
···
823
823
unsigned int this_active_corner = 0, this_sleep_corner = 0;
824
824
unsigned int peer_active_corner = 0, peer_sleep_corner = 0;
825
825
826
-
to_active_sleep(pd, pd->corner, &this_active_corner, &this_sleep_corner);
826
+
/* Clamp to the highest corner/level if sync_state isn't done yet */
827
+
if (!pd->state_synced)
828
+
this_active_corner = this_sleep_corner = pd->max_state - 1;
829
+
else
830
+
to_active_sleep(pd, pd->corner, &this_active_corner, &this_sleep_corner);
827
831
828
832
if (peer && peer->enabled)
829
833
to_active_sleep(peer, peer->corner, &peer_active_corner,
···
977
973
return of_genpd_add_provider_onecell(pdev->dev.of_node, data);
978
974
}
979
975
976
+
static void rpmpd_sync_state(struct device *dev)
977
+
{
978
+
const struct rpmpd_desc *desc = of_device_get_match_data(dev);
979
+
struct rpmpd **rpmpds = desc->rpmpds;
980
+
struct rpmpd *pd;
981
+
unsigned int i;
982
+
int ret;
983
+
984
+
mutex_lock(&rpmpd_lock);
985
+
for (i = 0; i < desc->num_pds; i++) {
986
+
pd = rpmpds[i];
987
+
if (!pd)
988
+
continue;
989
+
990
+
pd->state_synced = true;
991
+
992
+
if (!pd->enabled)
993
+
pd->corner = 0;
994
+
995
+
ret = rpmpd_aggregate_corner(pd);
996
+
if (ret)
997
+
dev_err(dev, "failed to sync %s: %d\n", pd->pd.name, ret);
998
+
}
999
+
mutex_unlock(&rpmpd_lock);
1000
+
}
1001
+
980
1002
static struct platform_driver rpmpd_driver = {
981
1003
.driver = {
982
1004
.name = "qcom-rpmpd",
983
1005
.of_match_table = rpmpd_match_table,
984
1006
.suppress_bind_attrs = true,
1007
+
.sync_state = rpmpd_sync_state,
985
1008
},
986
1009
.probe = rpmpd_probe,
987
1010
};
+1
drivers/genpd/rockchip/pm-domains.c
+1
drivers/genpd/rockchip/pm-domains.c
···
976
976
static const struct rockchip_domain_info rv1126_pm_domains[] = {
977
977
[RV1126_PD_VEPU] = DOMAIN_RV1126("vepu", BIT(2), BIT(9), BIT(9), false),
978
978
[RV1126_PD_VI] = DOMAIN_RV1126("vi", BIT(4), BIT(6), BIT(6), false),
979
+
[RV1126_PD_VO] = DOMAIN_RV1126("vo", BIT(5), BIT(7), BIT(7), false),
979
980
[RV1126_PD_ISPP] = DOMAIN_RV1126("ispp", BIT(1), BIT(8), BIT(8), false),
980
981
[RV1126_PD_VDPU] = DOMAIN_RV1126("vdpu", BIT(3), BIT(10), BIT(10), false),
981
982
[RV1126_PD_NVM] = DOMAIN_RV1126("nvm", BIT(7), BIT(11), BIT(11), false),
+2
-1
drivers/genpd/samsung/exynos-pm-domains.c
+2
-1
drivers/genpd/samsung/exynos-pm-domains.c
···
11
11
12
12
#include <linux/io.h>
13
13
#include <linux/err.h>
14
+
#include <linux/platform_device.h>
14
15
#include <linux/slab.h>
15
16
#include <linux/pm_domain.h>
16
17
#include <linux/delay.h>
18
+
#include <linux/of.h>
17
19
#include <linux/of_address.h>
18
-
#include <linux/of_platform.h>
19
20
#include <linux/pm_runtime.h>
20
21
21
22
struct exynos_pm_domain_config {
+4
-9
drivers/genpd/ti/omap_prm.c
+4
-9
drivers/genpd/ti/omap_prm.c
···
13
13
#include <linux/iopoll.h>
14
14
#include <linux/module.h>
15
15
#include <linux/of.h>
16
-
#include <linux/of_device.h>
17
16
#include <linux/platform_device.h>
18
17
#include <linux/pm_clock.h>
19
18
#include <linux/pm_domain.h>
···
942
943
struct omap_prm *prm;
943
944
int ret;
944
945
945
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
946
-
if (!res)
947
-
return -ENODEV;
948
-
949
946
data = of_device_get_match_data(&pdev->dev);
950
947
if (!data)
951
948
return -ENOTSUPP;
···
950
955
if (!prm)
951
956
return -ENOMEM;
952
957
958
+
prm->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
959
+
if (IS_ERR(prm->base))
960
+
return PTR_ERR(prm->base);
961
+
953
962
while (data->base != res->start) {
954
963
if (!data->base)
955
964
return -EINVAL;
···
961
962
}
962
963
963
964
prm->data = data;
964
-
965
-
prm->base = devm_ioremap_resource(&pdev->dev, res);
966
-
if (IS_ERR(prm->base))
967
-
return PTR_ERR(prm->base);
968
965
969
966
ret = omap_prm_domain_init(&pdev->dev, prm);
970
967
if (ret)
-1
drivers/irqchip/irq-versatile-fpga.c
-1
drivers/irqchip/irq-versatile-fpga.c
+1
-2
drivers/memory/brcmstb_dpfe.c
+1
-2
drivers/memory/brcmstb_dpfe.c
-1
drivers/memory/da8xx-ddrctl.c
-1
drivers/memory/da8xx-ddrctl.c
+1
-1
drivers/memory/fsl_ifc.c
+1
-1
drivers/memory/fsl_ifc.c
-1
drivers/memory/jz4780-nemc.c
-1
drivers/memory/jz4780-nemc.c
+1
drivers/memory/pl353-smc.c
+1
drivers/memory/pl353-smc.c
-1
drivers/memory/renesas-rpc-if.c
-1
drivers/memory/renesas-rpc-if.c
+1
-1
drivers/memory/samsung/exynos5422-dmc.c
+1
-1
drivers/memory/samsung/exynos5422-dmc.c
+2
drivers/memory/stm32-fmc2-ebi.c
+2
drivers/memory/stm32-fmc2-ebi.c
···
7
7
#include <linux/clk.h>
8
8
#include <linux/mfd/syscon.h>
9
9
#include <linux/module.h>
10
+
#include <linux/of.h>
10
11
#include <linux/of_platform.h>
11
12
#include <linux/pinctrl/consumer.h>
13
+
#include <linux/platform_device.h>
12
14
#include <linux/regmap.h>
13
15
#include <linux/reset.h>
14
16
+1
-1
drivers/memory/tegra/mc.c
+1
-1
drivers/memory/tegra/mc.c
+1
-1
drivers/memory/tegra/tegra124.c
+1
-1
drivers/memory/tegra/tegra124.c
+71
-65
drivers/memory/tegra/tegra186-emc.c
+71
-65
drivers/memory/tegra/tegra186-emc.c
···
155
155
tegra186_emc_debug_max_rate_get,
156
156
tegra186_emc_debug_max_rate_set, "%llu\n");
157
157
158
+
static int tegra186_emc_get_emc_dvfs_latency(struct tegra186_emc *emc)
159
+
{
160
+
struct mrq_emc_dvfs_latency_response response;
161
+
struct tegra_bpmp_message msg;
162
+
unsigned int i;
163
+
int err;
164
+
165
+
memset(&msg, 0, sizeof(msg));
166
+
msg.mrq = MRQ_EMC_DVFS_LATENCY;
167
+
msg.tx.data = NULL;
168
+
msg.tx.size = 0;
169
+
msg.rx.data = &response;
170
+
msg.rx.size = sizeof(response);
171
+
172
+
err = tegra_bpmp_transfer(emc->bpmp, &msg);
173
+
if (err < 0) {
174
+
dev_err(emc->dev, "failed to EMC DVFS pairs: %d\n", err);
175
+
return err;
176
+
}
177
+
if (msg.rx.ret < 0) {
178
+
dev_err(emc->dev, "EMC DVFS MRQ failed: %d (BPMP error code)\n", msg.rx.ret);
179
+
return -EINVAL;
180
+
}
181
+
182
+
emc->debugfs.min_rate = ULONG_MAX;
183
+
emc->debugfs.max_rate = 0;
184
+
185
+
emc->num_dvfs = response.num_pairs;
186
+
187
+
emc->dvfs = devm_kmalloc_array(emc->dev, emc->num_dvfs, sizeof(*emc->dvfs), GFP_KERNEL);
188
+
if (!emc->dvfs)
189
+
return -ENOMEM;
190
+
191
+
dev_dbg(emc->dev, "%u DVFS pairs:\n", emc->num_dvfs);
192
+
193
+
for (i = 0; i < emc->num_dvfs; i++) {
194
+
emc->dvfs[i].rate = response.pairs[i].freq * 1000;
195
+
emc->dvfs[i].latency = response.pairs[i].latency;
196
+
197
+
if (emc->dvfs[i].rate < emc->debugfs.min_rate)
198
+
emc->debugfs.min_rate = emc->dvfs[i].rate;
199
+
200
+
if (emc->dvfs[i].rate > emc->debugfs.max_rate)
201
+
emc->debugfs.max_rate = emc->dvfs[i].rate;
202
+
203
+
dev_dbg(emc->dev, " %2u: %lu Hz -> %lu us\n", i,
204
+
emc->dvfs[i].rate, emc->dvfs[i].latency);
205
+
}
206
+
207
+
err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate, emc->debugfs.max_rate);
208
+
if (err < 0) {
209
+
dev_err(emc->dev, "failed to set rate range [%lu-%lu] for %pC\n",
210
+
emc->debugfs.min_rate, emc->debugfs.max_rate, emc->clk);
211
+
return err;
212
+
}
213
+
214
+
emc->debugfs.root = debugfs_create_dir("emc", NULL);
215
+
debugfs_create_file("available_rates", 0444, emc->debugfs.root, emc,
216
+
&tegra186_emc_debug_available_rates_fops);
217
+
debugfs_create_file("min_rate", 0644, emc->debugfs.root, emc,
218
+
&tegra186_emc_debug_min_rate_fops);
219
+
debugfs_create_file("max_rate", 0644, emc->debugfs.root, emc,
220
+
&tegra186_emc_debug_max_rate_fops);
221
+
222
+
return 0;
223
+
}
224
+
158
225
/*
159
226
* tegra_emc_icc_set_bw() - Set BW api for EMC provider
160
227
* @src: ICC node for External Memory Controller (EMC)
···
318
251
static int tegra186_emc_probe(struct platform_device *pdev)
319
252
{
320
253
struct tegra_mc *mc = dev_get_drvdata(pdev->dev.parent);
321
-
struct mrq_emc_dvfs_latency_response response;
322
-
struct tegra_bpmp_message msg;
323
254
struct tegra186_emc *emc;
324
-
unsigned int i;
325
255
int err;
326
256
327
257
emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL);
···
339
275
platform_set_drvdata(pdev, emc);
340
276
emc->dev = &pdev->dev;
341
277
342
-
memset(&msg, 0, sizeof(msg));
343
-
msg.mrq = MRQ_EMC_DVFS_LATENCY;
344
-
msg.tx.data = NULL;
345
-
msg.tx.size = 0;
346
-
msg.rx.data = &response;
347
-
msg.rx.size = sizeof(response);
348
-
349
-
err = tegra_bpmp_transfer(emc->bpmp, &msg);
350
-
if (err < 0) {
351
-
dev_err(&pdev->dev, "failed to EMC DVFS pairs: %d\n", err);
352
-
goto put_bpmp;
278
+
if (tegra_bpmp_mrq_is_supported(emc->bpmp, MRQ_EMC_DVFS_LATENCY)) {
279
+
err = tegra186_emc_get_emc_dvfs_latency(emc);
280
+
if (err)
281
+
goto put_bpmp;
353
282
}
354
-
if (msg.rx.ret < 0) {
355
-
err = -EINVAL;
356
-
dev_err(&pdev->dev, "EMC DVFS MRQ failed: %d (BPMP error code)\n", msg.rx.ret);
357
-
goto put_bpmp;
358
-
}
359
-
360
-
emc->debugfs.min_rate = ULONG_MAX;
361
-
emc->debugfs.max_rate = 0;
362
-
363
-
emc->num_dvfs = response.num_pairs;
364
-
365
-
emc->dvfs = devm_kmalloc_array(&pdev->dev, emc->num_dvfs,
366
-
sizeof(*emc->dvfs), GFP_KERNEL);
367
-
if (!emc->dvfs) {
368
-
err = -ENOMEM;
369
-
goto put_bpmp;
370
-
}
371
-
372
-
dev_dbg(&pdev->dev, "%u DVFS pairs:\n", emc->num_dvfs);
373
-
374
-
for (i = 0; i < emc->num_dvfs; i++) {
375
-
emc->dvfs[i].rate = response.pairs[i].freq * 1000;
376
-
emc->dvfs[i].latency = response.pairs[i].latency;
377
-
378
-
if (emc->dvfs[i].rate < emc->debugfs.min_rate)
379
-
emc->debugfs.min_rate = emc->dvfs[i].rate;
380
-
381
-
if (emc->dvfs[i].rate > emc->debugfs.max_rate)
382
-
emc->debugfs.max_rate = emc->dvfs[i].rate;
383
-
384
-
dev_dbg(&pdev->dev, " %2u: %lu Hz -> %lu us\n", i,
385
-
emc->dvfs[i].rate, emc->dvfs[i].latency);
386
-
}
387
-
388
-
err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate,
389
-
emc->debugfs.max_rate);
390
-
if (err < 0) {
391
-
dev_err(&pdev->dev,
392
-
"failed to set rate range [%lu-%lu] for %pC\n",
393
-
emc->debugfs.min_rate, emc->debugfs.max_rate,
394
-
emc->clk);
395
-
goto put_bpmp;
396
-
}
397
-
398
-
emc->debugfs.root = debugfs_create_dir("emc", NULL);
399
-
debugfs_create_file("available_rates", S_IRUGO, emc->debugfs.root,
400
-
emc, &tegra186_emc_debug_available_rates_fops);
401
-
debugfs_create_file("min_rate", S_IRUGO | S_IWUSR, emc->debugfs.root,
402
-
emc, &tegra186_emc_debug_min_rate_fops);
403
-
debugfs_create_file("max_rate", S_IRUGO | S_IWUSR, emc->debugfs.root,
404
-
emc, &tegra186_emc_debug_max_rate_fops);
405
283
406
284
if (mc && mc->soc->icc_ops) {
407
285
if (tegra_bpmp_mrq_is_supported(emc->bpmp, MRQ_BWMGR_INT)) {
+2
-1
drivers/memory/tegra/tegra186.c
+2
-1
drivers/memory/tegra/tegra186.c
+2
-1
drivers/memory/tegra/tegra20.c
+2
-1
drivers/memory/tegra/tegra20.c
+2
-2
drivers/memory/tegra/tegra210-emc-core.c
+2
-2
drivers/memory/tegra/tegra210-emc-core.c
···
9
9
#include <linux/debugfs.h>
10
10
#include <linux/delay.h>
11
11
#include <linux/kernel.h>
12
+
#include <linux/mod_devicetable.h>
12
13
#include <linux/module.h>
13
-
#include <linux/of_address.h>
14
-
#include <linux/of_platform.h>
15
14
#include <linux/of_reserved_mem.h>
15
+
#include <linux/platform_device.h>
16
16
#include <linux/slab.h>
17
17
#include <linux/thermal.h>
18
18
#include <soc/tegra/fuse.h>
+377
-243
drivers/memory/tegra/tegra234.c
+377
-243
drivers/memory/tegra/tegra234.c
···
12
12
#include <soc/tegra/bpmp.h>
13
13
#include "mc.h"
14
14
15
+
/*
16
+
* MC Client entries are sorted in the increasing order of the
17
+
* override and security register offsets.
18
+
*/
15
19
static const struct tegra_mc_client tegra234_mc_clients[] = {
16
20
{
17
21
.id = TEGRA234_MEMORY_CLIENT_HDAR,
···
30
26
},
31
27
},
32
28
}, {
29
+
.id = TEGRA234_MEMORY_CLIENT_NVENCSRD,
30
+
.name = "nvencsrd",
31
+
.bpmp_id = TEGRA_ICC_BPMP_NVENC,
32
+
.type = TEGRA_ICC_NISO,
33
+
.sid = TEGRA234_SID_NVENC,
34
+
.regs = {
35
+
.sid = {
36
+
.override = 0xe0,
37
+
.security = 0xe4,
38
+
},
39
+
},
40
+
}, {
41
+
.id = TEGRA234_MEMORY_CLIENT_PCIE6AR,
42
+
.name = "pcie6ar",
43
+
.bpmp_id = TEGRA_ICC_BPMP_PCIE_6,
44
+
.type = TEGRA_ICC_NISO,
45
+
.sid = TEGRA234_SID_PCIE6,
46
+
.regs = {
47
+
.sid = {
48
+
.override = 0x140,
49
+
.security = 0x144,
50
+
},
51
+
},
52
+
}, {
53
+
.id = TEGRA234_MEMORY_CLIENT_PCIE6AW,
54
+
.name = "pcie6aw",
55
+
.bpmp_id = TEGRA_ICC_BPMP_PCIE_6,
56
+
.type = TEGRA_ICC_NISO,
57
+
.sid = TEGRA234_SID_PCIE6,
58
+
.regs = {
59
+
.sid = {
60
+
.override = 0x148,
61
+
.security = 0x14c,
62
+
},
63
+
},
64
+
}, {
65
+
.id = TEGRA234_MEMORY_CLIENT_PCIE7AR,
66
+
.name = "pcie7ar",
67
+
.bpmp_id = TEGRA_ICC_BPMP_PCIE_7,
68
+
.type = TEGRA_ICC_NISO,
69
+
.sid = TEGRA234_SID_PCIE7,
70
+
.regs = {
71
+
.sid = {
72
+
.override = 0x150,
73
+
.security = 0x154,
74
+
},
75
+
},
76
+
}, {
77
+
.id = TEGRA234_MEMORY_CLIENT_NVENCSWR,
78
+
.name = "nvencswr",
79
+
.bpmp_id = TEGRA_ICC_BPMP_NVENC,
80
+
.type = TEGRA_ICC_NISO,
81
+
.sid = TEGRA234_SID_NVENC,
82
+
.regs = {
83
+
.sid = {
84
+
.override = 0x158,
85
+
.security = 0x15c,
86
+
},
87
+
},
88
+
}, {
89
+
.id = TEGRA234_MEMORY_CLIENT_DLA0RDB,
90
+
.name = "dla0rdb",
91
+
.sid = TEGRA234_SID_NVDLA0,
92
+
.regs = {
93
+
.sid = {
94
+
.override = 0x160,
95
+
.security = 0x164,
96
+
},
97
+
},
98
+
}, {
99
+
.id = TEGRA234_MEMORY_CLIENT_DLA0RDB1,
100
+
.name = "dla0rdb1",
101
+
.sid = TEGRA234_SID_NVDLA0,
102
+
.regs = {
103
+
.sid = {
104
+
.override = 0x168,
105
+
.security = 0x16c,
106
+
},
107
+
},
108
+
}, {
109
+
.id = TEGRA234_MEMORY_CLIENT_DLA0WRB,
110
+
.name = "dla0wrb",
111
+
.sid = TEGRA234_SID_NVDLA0,
112
+
.regs = {
113
+
.sid = {
114
+
.override = 0x170,
115
+
.security = 0x174,
116
+
},
117
+
},
118
+
}, {
119
+
.id = TEGRA234_MEMORY_CLIENT_DLA1RDB,
120
+
.name = "dla0rdb",
121
+
.sid = TEGRA234_SID_NVDLA1,
122
+
.regs = {
123
+
.sid = {
124
+
.override = 0x178,
125
+
.security = 0x17c,
126
+
},
127
+
},
128
+
}, {
129
+
.id = TEGRA234_MEMORY_CLIENT_PCIE7AW,
130
+
.name = "pcie7aw",
131
+
.bpmp_id = TEGRA_ICC_BPMP_PCIE_7,
132
+
.type = TEGRA_ICC_NISO,
133
+
.sid = TEGRA234_SID_PCIE7,
134
+
.regs = {
135
+
.sid = {
136
+
.override = 0x180,
137
+
.security = 0x184,
138
+
},
139
+
},
140
+
}, {
141
+
.id = TEGRA234_MEMORY_CLIENT_PCIE8AR,
142
+
.name = "pcie8ar",
143
+
.bpmp_id = TEGRA_ICC_BPMP_PCIE_8,
144
+
.type = TEGRA_ICC_NISO,
145
+
.sid = TEGRA234_SID_PCIE8,
146
+
.regs = {
147
+
.sid = {
148
+
.override = 0x190,
149
+
.security = 0x194,
150
+
},
151
+
},
152
+
}, {
33
153
.id = TEGRA234_MEMORY_CLIENT_HDAW,
34
154
.name = "hdaw",
35
155
.bpmp_id = TEGRA_ICC_BPMP_HDA,
···
163
35
.sid = {
164
36
.override = 0x1a8,
165
37
.security = 0x1ac,
38
+
},
39
+
},
40
+
}, {
41
+
.id = TEGRA234_MEMORY_CLIENT_PCIE8AW,
42
+
.name = "pcie8aw",
43
+
.bpmp_id = TEGRA_ICC_BPMP_PCIE_8,
44
+
.type = TEGRA_ICC_NISO,
45
+
.sid = TEGRA234_SID_PCIE8,
46
+
.regs = {
47
+
.sid = {
48
+
.override = 0x1d8,
49
+
.security = 0x1dc,
50
+
},
51
+
},
52
+
}, {
53
+
.id = TEGRA234_MEMORY_CLIENT_PCIE9AR,
54
+
.name = "pcie9ar",
55
+
.bpmp_id = TEGRA_ICC_BPMP_PCIE_9,
56
+
.type = TEGRA_ICC_NISO,
57
+
.sid = TEGRA234_SID_PCIE9,
58
+
.regs = {
59
+
.sid = {
60
+
.override = 0x1e0,
61
+
.security = 0x1e4,
62
+
},
63
+
},
64
+
}, {
65
+
.id = TEGRA234_MEMORY_CLIENT_PCIE6AR1,
66
+
.name = "pcie6ar1",
67
+
.bpmp_id = TEGRA_ICC_BPMP_PCIE_6,
68
+
.type = TEGRA_ICC_NISO,
69
+
.sid = TEGRA234_SID_PCIE6,
70
+
.regs = {
71
+
.sid = {
72
+
.override = 0x1e8,
73
+
.security = 0x1ec,
74
+
},
75
+
},
76
+
}, {
77
+
.id = TEGRA234_MEMORY_CLIENT_PCIE9AW,
78
+
.name = "pcie9aw",
79
+
.bpmp_id = TEGRA_ICC_BPMP_PCIE_9,
80
+
.type = TEGRA_ICC_NISO,
81
+
.sid = TEGRA234_SID_PCIE9,
82
+
.regs = {
83
+
.sid = {
84
+
.override = 0x1f0,
85
+
.security = 0x1f4,
86
+
},
87
+
},
88
+
}, {
89
+
.id = TEGRA234_MEMORY_CLIENT_PCIE10AR,
90
+
.name = "pcie10ar",
91
+
.bpmp_id = TEGRA_ICC_BPMP_PCIE_10,
92
+
.type = TEGRA_ICC_NISO,
93
+
.sid = TEGRA234_SID_PCIE10,
94
+
.regs = {
95
+
.sid = {
96
+
.override = 0x1f8,
97
+
.security = 0x1fc,
98
+
},
99
+
},
100
+
}, {
101
+
.id = TEGRA234_MEMORY_CLIENT_PCIE10AW,
102
+
.name = "pcie10aw",
103
+
.bpmp_id = TEGRA_ICC_BPMP_PCIE_10,
104
+
.type = TEGRA_ICC_NISO,
105
+
.sid = TEGRA234_SID_PCIE10,
106
+
.regs = {
107
+
.sid = {
108
+
.override = 0x200,
109
+
.security = 0x204,
110
+
},
111
+
},
112
+
}, {
113
+
.id = TEGRA234_MEMORY_CLIENT_PCIE10AR1,
114
+
.name = "pcie10ar1",
115
+
.bpmp_id = TEGRA_ICC_BPMP_PCIE_10,
116
+
.type = TEGRA_ICC_NISO,
117
+
.sid = TEGRA234_SID_PCIE10,
118
+
.regs = {
119
+
.sid = {
120
+
.override = 0x240,
121
+
.security = 0x244,
122
+
},
123
+
},
124
+
}, {
125
+
.id = TEGRA234_MEMORY_CLIENT_PCIE7AR1,
126
+
.name = "pcie7ar1",
127
+
.bpmp_id = TEGRA_ICC_BPMP_PCIE_7,
128
+
.type = TEGRA_ICC_NISO,
129
+
.sid = TEGRA234_SID_PCIE7,
130
+
.regs = {
131
+
.sid = {
132
+
.override = 0x248,
133
+
.security = 0x24c,
166
134
},
167
135
},
168
136
}, {
···
382
158
},
383
159
},
384
160
}, {
161
+
.id = TEGRA234_MEMORY_CLIENT_VICSRD,
162
+
.name = "vicsrd",
163
+
.bpmp_id = TEGRA_ICC_BPMP_VIC,
164
+
.type = TEGRA_ICC_NISO,
165
+
.sid = TEGRA234_SID_VIC,
166
+
.regs = {
167
+
.sid = {
168
+
.override = 0x360,
169
+
.security = 0x364,
170
+
},
171
+
},
172
+
}, {
173
+
.id = TEGRA234_MEMORY_CLIENT_VICSWR,
174
+
.name = "vicswr",
175
+
.bpmp_id = TEGRA_ICC_BPMP_VIC,
176
+
.type = TEGRA_ICC_NISO,
177
+
.sid = TEGRA234_SID_VIC,
178
+
.regs = {
179
+
.sid = {
180
+
.override = 0x368,
181
+
.security = 0x36c,
182
+
},
183
+
},
184
+
}, {
185
+
.id = TEGRA234_MEMORY_CLIENT_DLA1RDB1,
186
+
.name = "dla0rdb1",
187
+
.sid = TEGRA234_SID_NVDLA1,
188
+
.regs = {
189
+
.sid = {
190
+
.override = 0x370,
191
+
.security = 0x374,
192
+
},
193
+
},
194
+
}, {
195
+
.id = TEGRA234_MEMORY_CLIENT_DLA1WRB,
196
+
.name = "dla0wrb",
197
+
.sid = TEGRA234_SID_NVDLA1,
198
+
.regs = {
199
+
.sid = {
200
+
.override = 0x378,
201
+
.security = 0x37c,
202
+
},
203
+
},
204
+
}, {
385
205
.id = TEGRA234_MEMORY_CLIENT_VI2W,
386
206
.name = "vi2w",
387
207
.bpmp_id = TEGRA_ICC_BPMP_VI2,
···
450
182
},
451
183
},
452
184
}, {
453
-
.id = TEGRA234_MEMORY_CLIENT_VI2FALW,
454
-
.name = "vi2falw",
455
-
.bpmp_id = TEGRA_ICC_BPMP_VI2FAL,
456
-
.type = TEGRA_ICC_ISO_VIFAL,
457
-
.sid = TEGRA234_SID_ISO_VI2FALC,
185
+
.id = TEGRA234_MEMORY_CLIENT_NVDECSRD,
186
+
.name = "nvdecsrd",
187
+
.bpmp_id = TEGRA_ICC_BPMP_NVDEC,
188
+
.type = TEGRA_ICC_NISO,
189
+
.sid = TEGRA234_SID_NVDEC,
458
190
.regs = {
459
191
.sid = {
460
-
.override = 0x3e0,
461
-
.security = 0x3e4,
192
+
.override = 0x3c0,
193
+
.security = 0x3c4,
194
+
},
195
+
},
196
+
}, {
197
+
.id = TEGRA234_MEMORY_CLIENT_NVDECSWR,
198
+
.name = "nvdecswr",
199
+
.bpmp_id = TEGRA_ICC_BPMP_NVDEC,
200
+
.type = TEGRA_ICC_NISO,
201
+
.sid = TEGRA234_SID_NVDEC,
202
+
.regs = {
203
+
.sid = {
204
+
.override = 0x3c8,
205
+
.security = 0x3cc,
462
206
},
463
207
},
464
208
}, {
···
498
218
},
499
219
},
500
220
}, {
221
+
.id = TEGRA234_MEMORY_CLIENT_VI2FALW,
222
+
.name = "vi2falw",
223
+
.bpmp_id = TEGRA_ICC_BPMP_VI2FAL,
224
+
.type = TEGRA_ICC_ISO_VIFAL,
225
+
.sid = TEGRA234_SID_ISO_VI2FALC,
226
+
.regs = {
227
+
.sid = {
228
+
.override = 0x3e0,
229
+
.security = 0x3e4,
230
+
},
231
+
},
232
+
}, {
233
+
.id = TEGRA234_MEMORY_CLIENT_NVJPGSRD,
234
+
.name = "nvjpgsrd",
235
+
.bpmp_id = TEGRA_ICC_BPMP_NVJPG_0,
236
+
.type = TEGRA_ICC_NISO,
237
+
.sid = TEGRA234_SID_NVJPG,
238
+
.regs = {
239
+
.sid = {
240
+
.override = 0x3f0,
241
+
.security = 0x3f4,
242
+
},
243
+
},
244
+
}, {
245
+
.id = TEGRA234_MEMORY_CLIENT_NVJPGSWR,
246
+
.name = "nvjpgswr",
247
+
.bpmp_id = TEGRA_ICC_BPMP_NVJPG_0,
248
+
.type = TEGRA_ICC_NISO,
249
+
.sid = TEGRA234_SID_NVJPG,
250
+
.regs = {
251
+
.sid = {
252
+
.override = 0x3f8,
253
+
.security = 0x3fc,
254
+
},
255
+
},
256
+
}, {
501
257
.id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR,
502
258
.name = "nvdisplayr",
503
259
.bpmp_id = TEGRA_ICC_BPMP_DISPLAY,
···
543
227
.sid = {
544
228
.override = 0x490,
545
229
.security = 0x494,
546
-
},
547
-
},
548
-
}, {
549
-
.id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR1,
550
-
.name = "nvdisplayr1",
551
-
.bpmp_id = TEGRA_ICC_BPMP_DISPLAY,
552
-
.type = TEGRA_ICC_ISO_DISPLAY,
553
-
.sid = TEGRA234_SID_ISO_NVDISPLAY,
554
-
.regs = {
555
-
.sid = {
556
-
.override = 0x508,
557
-
.security = 0x50c,
558
230
},
559
231
},
560
232
}, {
···
610
306
},
611
307
},
612
308
}, {
309
+
.id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR1,
310
+
.name = "nvdisplayr1",
311
+
.bpmp_id = TEGRA_ICC_BPMP_DISPLAY,
312
+
.type = TEGRA_ICC_ISO_DISPLAY,
313
+
.sid = TEGRA234_SID_ISO_NVDISPLAY,
314
+
.regs = {
315
+
.sid = {
316
+
.override = 0x508,
317
+
.security = 0x50c,
318
+
},
319
+
},
320
+
}, {
613
321
.id = TEGRA234_MEMORY_CLIENT_DLA0RDA,
614
322
.name = "dla0rda",
615
323
.sid = TEGRA234_SID_NVDLA0,
···
652
336
},
653
337
},
654
338
}, {
655
-
.id = TEGRA234_MEMORY_CLIENT_DLA0RDB,
656
-
.name = "dla0rdb",
657
-
.sid = TEGRA234_SID_NVDLA0,
658
-
.regs = {
659
-
.sid = {
660
-
.override = 0x160,
661
-
.security = 0x164,
662
-
},
663
-
},
664
-
}, {
665
-
.id = TEGRA234_MEMORY_CLIENT_DLA0RDA1,
666
-
.name = "dla0rda1",
667
-
.sid = TEGRA234_SID_NVDLA0,
668
-
.regs = {
669
-
.sid = {
670
-
.override = 0x748,
671
-
.security = 0x74c,
672
-
},
673
-
},
674
-
}, {
675
339
.id = TEGRA234_MEMORY_CLIENT_DLA0FALWRB,
676
340
.name = "dla0falwrb",
677
341
.sid = TEGRA234_SID_NVDLA0,
···
659
363
.sid = {
660
364
.override = 0x608,
661
365
.security = 0x60c,
662
-
},
663
-
},
664
-
}, {
665
-
.id = TEGRA234_MEMORY_CLIENT_DLA0RDB1,
666
-
.name = "dla0rdb1",
667
-
.sid = TEGRA234_SID_NVDLA0,
668
-
.regs = {
669
-
.sid = {
670
-
.override = 0x168,
671
-
.security = 0x16c,
672
-
},
673
-
},
674
-
}, {
675
-
.id = TEGRA234_MEMORY_CLIENT_DLA0WRB,
676
-
.name = "dla0wrb",
677
-
.sid = TEGRA234_SID_NVDLA0,
678
-
.regs = {
679
-
.sid = {
680
-
.override = 0x170,
681
-
.security = 0x174,
682
366
},
683
367
},
684
368
}, {
···
692
416
},
693
417
},
694
418
}, {
695
-
.id = TEGRA234_MEMORY_CLIENT_DLA1RDB,
696
-
.name = "dla0rdb",
697
-
.sid = TEGRA234_SID_NVDLA1,
698
-
.regs = {
699
-
.sid = {
700
-
.override = 0x178,
701
-
.security = 0x17c,
702
-
},
703
-
},
704
-
}, {
705
-
.id = TEGRA234_MEMORY_CLIENT_DLA1RDA1,
706
-
.name = "dla0rda1",
707
-
.sid = TEGRA234_SID_NVDLA1,
708
-
.regs = {
709
-
.sid = {
710
-
.override = 0x750,
711
-
.security = 0x754,
712
-
},
713
-
},
714
-
}, {
715
419
.id = TEGRA234_MEMORY_CLIENT_DLA1FALWRB,
716
420
.name = "dla0falwrb",
717
421
.sid = TEGRA234_SID_NVDLA1,
···
699
443
.sid = {
700
444
.override = 0x628,
701
445
.security = 0x62c,
702
-
},
703
-
},
704
-
}, {
705
-
.id = TEGRA234_MEMORY_CLIENT_DLA1RDB1,
706
-
.name = "dla0rdb1",
707
-
.sid = TEGRA234_SID_NVDLA1,
708
-
.regs = {
709
-
.sid = {
710
-
.override = 0x370,
711
-
.security = 0x374,
712
-
},
713
-
},
714
-
}, {
715
-
.id = TEGRA234_MEMORY_CLIENT_DLA1WRB,
716
-
.name = "dla0wrb",
717
-
.sid = TEGRA234_SID_NVDLA1,
718
-
.regs = {
719
-
.sid = {
720
-
.override = 0x378,
721
-
.security = 0x37c,
722
446
},
723
447
},
724
448
}, {
···
846
610
},
847
611
},
848
612
}, {
613
+
.id = TEGRA234_MEMORY_CLIENT_DLA0RDA1,
614
+
.name = "dla0rda1",
615
+
.sid = TEGRA234_SID_NVDLA0,
616
+
.regs = {
617
+
.sid = {
618
+
.override = 0x748,
619
+
.security = 0x74c,
620
+
},
621
+
},
622
+
}, {
623
+
.id = TEGRA234_MEMORY_CLIENT_DLA1RDA1,
624
+
.name = "dla0rda1",
625
+
.sid = TEGRA234_SID_NVDLA1,
626
+
.regs = {
627
+
.sid = {
628
+
.override = 0x750,
629
+
.security = 0x754,
630
+
},
631
+
},
632
+
}, {
849
633
.id = TEGRA234_MEMORY_CLIENT_PCIE5R1,
850
634
.name = "pcie5r1",
851
635
.bpmp_id = TEGRA_ICC_BPMP_PCIE_5,
···
878
622
},
879
623
},
880
624
}, {
881
-
.id = TEGRA234_MEMORY_CLIENT_PCIE6AR,
882
-
.name = "pcie6ar",
883
-
.bpmp_id = TEGRA_ICC_BPMP_PCIE_6,
625
+
.id = TEGRA234_MEMORY_CLIENT_NVJPG1SRD,
626
+
.name = "nvjpg1srd",
627
+
.bpmp_id = TEGRA_ICC_BPMP_NVJPG_1,
884
628
.type = TEGRA_ICC_NISO,
885
-
.sid = TEGRA234_SID_PCIE6,
629
+
.sid = TEGRA234_SID_NVJPG1,
886
630
.regs = {
887
631
.sid = {
888
-
.override = 0x140,
889
-
.security = 0x144,
632
+
.override = 0x918,
633
+
.security = 0x91c,
890
634
},
891
635
},
892
636
}, {
893
-
.id = TEGRA234_MEMORY_CLIENT_PCIE6AW,
894
-
.name = "pcie6aw",
895
-
.bpmp_id = TEGRA_ICC_BPMP_PCIE_6,
637
+
.id = TEGRA234_MEMORY_CLIENT_NVJPG1SWR,
638
+
.name = "nvjpg1swr",
639
+
.bpmp_id = TEGRA_ICC_BPMP_NVJPG_1,
896
640
.type = TEGRA_ICC_NISO,
897
-
.sid = TEGRA234_SID_PCIE6,
641
+
.sid = TEGRA234_SID_NVJPG1,
898
642
.regs = {
899
643
.sid = {
900
-
.override = 0x148,
901
-
.security = 0x14c,
902
-
},
903
-
},
904
-
}, {
905
-
.id = TEGRA234_MEMORY_CLIENT_PCIE6AR1,
906
-
.name = "pcie6ar1",
907
-
.bpmp_id = TEGRA_ICC_BPMP_PCIE_6,
908
-
.type = TEGRA_ICC_NISO,
909
-
.sid = TEGRA234_SID_PCIE6,
910
-
.regs = {
911
-
.sid = {
912
-
.override = 0x1e8,
913
-
.security = 0x1ec,
914
-
},
915
-
},
916
-
}, {
917
-
.id = TEGRA234_MEMORY_CLIENT_PCIE7AR,
918
-
.name = "pcie7ar",
919
-
.bpmp_id = TEGRA_ICC_BPMP_PCIE_7,
920
-
.type = TEGRA_ICC_NISO,
921
-
.sid = TEGRA234_SID_PCIE7,
922
-
.regs = {
923
-
.sid = {
924
-
.override = 0x150,
925
-
.security = 0x154,
926
-
},
927
-
},
928
-
}, {
929
-
.id = TEGRA234_MEMORY_CLIENT_PCIE7AW,
930
-
.name = "pcie7aw",
931
-
.bpmp_id = TEGRA_ICC_BPMP_PCIE_7,
932
-
.type = TEGRA_ICC_NISO,
933
-
.sid = TEGRA234_SID_PCIE7,
934
-
.regs = {
935
-
.sid = {
936
-
.override = 0x180,
937
-
.security = 0x184,
938
-
},
939
-
},
940
-
}, {
941
-
.id = TEGRA234_MEMORY_CLIENT_PCIE7AR1,
942
-
.name = "pcie7ar1",
943
-
.bpmp_id = TEGRA_ICC_BPMP_PCIE_7,
944
-
.type = TEGRA_ICC_NISO,
945
-
.sid = TEGRA234_SID_PCIE7,
946
-
.regs = {
947
-
.sid = {
948
-
.override = 0x248,
949
-
.security = 0x24c,
950
-
},
951
-
},
952
-
}, {
953
-
.id = TEGRA234_MEMORY_CLIENT_PCIE8AR,
954
-
.name = "pcie8ar",
955
-
.bpmp_id = TEGRA_ICC_BPMP_PCIE_8,
956
-
.type = TEGRA_ICC_NISO,
957
-
.sid = TEGRA234_SID_PCIE8,
958
-
.regs = {
959
-
.sid = {
960
-
.override = 0x190,
961
-
.security = 0x194,
962
-
},
963
-
},
964
-
}, {
965
-
.id = TEGRA234_MEMORY_CLIENT_PCIE8AW,
966
-
.name = "pcie8aw",
967
-
.bpmp_id = TEGRA_ICC_BPMP_PCIE_8,
968
-
.type = TEGRA_ICC_NISO,
969
-
.sid = TEGRA234_SID_PCIE8,
970
-
.regs = {
971
-
.sid = {
972
-
.override = 0x1d8,
973
-
.security = 0x1dc,
974
-
},
975
-
},
976
-
}, {
977
-
.id = TEGRA234_MEMORY_CLIENT_PCIE9AR,
978
-
.name = "pcie9ar",
979
-
.bpmp_id = TEGRA_ICC_BPMP_PCIE_9,
980
-
.type = TEGRA_ICC_NISO,
981
-
.sid = TEGRA234_SID_PCIE9,
982
-
.regs = {
983
-
.sid = {
984
-
.override = 0x1e0,
985
-
.security = 0x1e4,
986
-
},
987
-
},
988
-
}, {
989
-
.id = TEGRA234_MEMORY_CLIENT_PCIE9AW,
990
-
.name = "pcie9aw",
991
-
.bpmp_id = TEGRA_ICC_BPMP_PCIE_9,
992
-
.type = TEGRA_ICC_NISO,
993
-
.sid = TEGRA234_SID_PCIE9,
994
-
.regs = {
995
-
.sid = {
996
-
.override = 0x1f0,
997
-
.security = 0x1f4,
998
-
},
999
-
},
1000
-
}, {
1001
-
.id = TEGRA234_MEMORY_CLIENT_PCIE10AR,
1002
-
.name = "pcie10ar",
1003
-
.bpmp_id = TEGRA_ICC_BPMP_PCIE_10,
1004
-
.type = TEGRA_ICC_NISO,
1005
-
.sid = TEGRA234_SID_PCIE10,
1006
-
.regs = {
1007
-
.sid = {
1008
-
.override = 0x1f8,
1009
-
.security = 0x1fc,
1010
-
},
1011
-
},
1012
-
}, {
1013
-
.id = TEGRA234_MEMORY_CLIENT_PCIE10AW,
1014
-
.name = "pcie10aw",
1015
-
.bpmp_id = TEGRA_ICC_BPMP_PCIE_10,
1016
-
.type = TEGRA_ICC_NISO,
1017
-
.sid = TEGRA234_SID_PCIE10,
1018
-
.regs = {
1019
-
.sid = {
1020
-
.override = 0x200,
1021
-
.security = 0x204,
1022
-
},
1023
-
},
1024
-
}, {
1025
-
.id = TEGRA234_MEMORY_CLIENT_PCIE10AR1,
1026
-
.name = "pcie10ar1",
1027
-
.bpmp_id = TEGRA_ICC_BPMP_PCIE_10,
1028
-
.type = TEGRA_ICC_NISO,
1029
-
.sid = TEGRA234_SID_PCIE10,
1030
-
.regs = {
1031
-
.sid = {
1032
-
.override = 0x240,
1033
-
.security = 0x244,
644
+
.override = 0x920,
645
+
.security = 0x924,
1034
646
},
1035
647
},
1036
648
}, {
···
915
791
.id = TEGRA_ICC_MC_CPU_CLUSTER2,
916
792
.name = "sw_cluster2",
917
793
.bpmp_id = TEGRA_ICC_BPMP_CPU_CLUSTER2,
794
+
.type = TEGRA_ICC_NISO,
795
+
}, {
796
+
.id = TEGRA234_MEMORY_CLIENT_NVL1R,
797
+
.name = "nvl1r",
798
+
.bpmp_id = TEGRA_ICC_BPMP_GPU,
799
+
.type = TEGRA_ICC_NISO,
800
+
}, {
801
+
.id = TEGRA234_MEMORY_CLIENT_NVL1W,
802
+
.name = "nvl1w",
803
+
.bpmp_id = TEGRA_ICC_BPMP_GPU,
918
804
.type = TEGRA_ICC_NISO,
919
805
},
920
806
};
+1
-1
drivers/memory/tegra/tegra30-emc.c
+1
-1
drivers/memory/tegra/tegra30-emc.c
+1
-1
drivers/memory/tegra/tegra30.c
+1
-1
drivers/memory/tegra/tegra30.c
+1
-4
drivers/net/ipa/ipa_power.c
+1
-4
drivers/net/ipa/ipa_power.c
···
324
324
{
325
325
static const char fmt[] = "{ class: bcm, res: ipa_pc, val: %c }";
326
326
struct ipa_power *power = ipa->power;
327
-
char buf[36]; /* Exactly enough for fmt[]; size a multiple of 4 */
328
327
int ret;
329
328
330
329
if (!power->qmp)
331
330
return; /* Not needed on this platform */
332
331
333
-
(void)snprintf(buf, sizeof(buf), fmt, enable ? '1' : '0');
334
-
335
-
ret = qmp_send(power->qmp, buf, sizeof(buf));
332
+
ret = qmp_send(power->qmp, fmt, enable ? '1' : '0');
336
333
if (ret)
337
334
dev_err(power->dev, "error %d sending QMP %sable request\n",
338
335
ret, enable ? "en" : "dis");
+1
-7
drivers/remoteproc/qcom_q6v5.c
+1
-7
drivers/remoteproc/qcom_q6v5.c
···
23
23
24
24
static int q6v5_load_state_toggle(struct qcom_q6v5 *q6v5, bool enable)
25
25
{
26
-
char buf[Q6V5_LOAD_STATE_MSG_LEN];
27
26
int ret;
28
27
29
28
if (!q6v5->qmp)
30
29
return 0;
31
30
32
-
ret = snprintf(buf, sizeof(buf),
33
-
"{class: image, res: load_state, name: %s, val: %s}",
31
+
ret = qmp_send(q6v5->qmp, "{class: image, res: load_state, name: %s, val: %s}",
34
32
q6v5->load_state, enable ? "on" : "off");
35
-
36
-
WARN_ON(ret >= Q6V5_LOAD_STATE_MSG_LEN);
37
-
38
-
ret = qmp_send(q6v5->qmp, buf, sizeof(buf));
39
33
if (ret)
40
34
dev_err(q6v5->dev, "failed to toggle load state\n");
41
35
-1
drivers/reset/hisilicon/hi6220_reset.c
-1
drivers/reset/hisilicon/hi6220_reset.c
+3
-3
drivers/reset/hisilicon/reset-hi3660.c
+3
-3
drivers/reset/hisilicon/reset-hi3660.c
···
6
6
#include <linux/kernel.h>
7
7
#include <linux/mfd/syscon.h>
8
8
#include <linux/module.h>
9
-
#include <linux/of_device.h>
9
+
#include <linux/of.h>
10
10
#include <linux/platform_device.h>
11
11
#include <linux/regmap.h>
12
12
#include <linux/reset-controller.h>
···
90
90
"hisi,rst-syscon");
91
91
}
92
92
if (IS_ERR(rc->map)) {
93
-
dev_err(dev, "failed to get hisilicon,rst-syscon\n");
94
-
return PTR_ERR(rc->map);
93
+
return dev_err_probe(dev, PTR_ERR(rc->map),
94
+
"failed to get hisilicon,rst-syscon\n");
95
95
}
96
96
97
97
rc->rst.ops = &hi3660_reset_ops,
-2
drivers/reset/reset-ath79.c
-2
drivers/reset/reset-ath79.c
-2
drivers/reset/reset-bcm6345.c
-2
drivers/reset/reset-bcm6345.c
+1
-1
drivers/reset/reset-imx7.c
+1
-1
drivers/reset/reset-imx7.c
+1
-1
drivers/reset/reset-intel-gw.c
+1
-1
drivers/reset/reset-intel-gw.c
-1
drivers/reset/reset-k210.c
-1
drivers/reset/reset-k210.c
-1
drivers/reset/reset-lantiq.c
-1
drivers/reset/reset-lantiq.c
-2
drivers/reset/reset-lpc18xx.c
-2
drivers/reset/reset-lpc18xx.c
+2
-1
drivers/reset/reset-meson-audio-arb.c
+2
-1
drivers/reset/reset-meson-audio-arb.c
-3
drivers/reset/reset-meson.c
-3
drivers/reset/reset-meson.c
···
14
14
#include <linux/reset-controller.h>
15
15
#include <linux/slab.h>
16
16
#include <linux/types.h>
17
-
#include <linux/of_device.h>
18
17
19
18
#define BITS_PER_REG 32
20
19
···
127
128
data->param = of_device_get_match_data(&pdev->dev);
128
129
if (!data->param)
129
130
return -ENODEV;
130
-
131
-
platform_set_drvdata(pdev, data);
132
131
133
132
spin_lock_init(&data->lock);
134
133
+2
-1
drivers/reset/reset-microchip-sparx5.c
+2
-1
drivers/reset/reset-microchip-sparx5.c
···
7
7
* https://github.com/microchip-ung/sparx-5_reginfo
8
8
*/
9
9
#include <linux/mfd/syscon.h>
10
-
#include <linux/of_device.h>
10
+
#include <linux/of.h>
11
11
#include <linux/module.h>
12
12
#include <linux/platform_device.h>
13
+
#include <linux/property.h>
13
14
#include <linux/regmap.h>
14
15
#include <linux/reset-controller.h>
15
16
+1
drivers/reset/reset-mpfs.c
+1
drivers/reset/reset-mpfs.c
-2
drivers/reset/reset-npcm.c
-2
drivers/reset/reset-npcm.c
+1
-1
drivers/reset/reset-qcom-aoss.c
+1
-1
drivers/reset/reset-qcom-aoss.c
+1
-1
drivers/reset/reset-qcom-pdc.c
+1
-1
drivers/reset/reset-qcom-pdc.c
-1
drivers/reset/reset-simple.c
-1
drivers/reset/reset-simple.c
-2
drivers/reset/reset-ti-syscon.c
-2
drivers/reset/reset-ti-syscon.c
+1
-3
drivers/reset/reset-uniphier-glue.c
+1
-3
drivers/reset/reset-uniphier-glue.c
···
6
6
7
7
#include <linux/clk.h>
8
8
#include <linux/module.h>
9
-
#include <linux/of_device.h>
9
+
#include <linux/of.h>
10
10
#include <linux/platform_device.h>
11
11
#include <linux/reset.h>
12
12
#include <linux/reset/reset-simple.h>
···
98
98
priv->rdata.rcdev.ops = &reset_simple_ops;
99
99
priv->rdata.rcdev.of_node = dev->of_node;
100
100
priv->rdata.active_low = true;
101
-
102
-
platform_set_drvdata(pdev, priv);
103
101
104
102
return devm_reset_controller_register(dev, &priv->rdata.rcdev);
105
103
}
-1
drivers/reset/reset-uniphier.c
-1
drivers/reset/reset-uniphier.c
-1
drivers/reset/reset-zynq.c
-1
drivers/reset/reset-zynq.c
+7
-3
drivers/reset/reset-zynqmp.c
+7
-3
drivers/reset/reset-zynqmp.c
···
9
9
#include <linux/platform_device.h>
10
10
#include <linux/reset-controller.h>
11
11
#include <linux/firmware/xlnx-zynqmp.h>
12
-
#include <linux/of_device.h>
13
12
14
13
#define ZYNQMP_NR_RESETS (ZYNQMP_PM_RESET_END - ZYNQMP_PM_RESET_START)
15
14
#define ZYNQMP_RESET_ID ZYNQMP_PM_RESET_START
16
15
#define VERSAL_NR_RESETS 95
16
+
#define VERSAL_NET_NR_RESETS 176
17
17
18
18
struct zynqmp_reset_soc_data {
19
19
u32 reset_id;
···
88
88
.num_resets = VERSAL_NR_RESETS,
89
89
};
90
90
91
+
static const struct zynqmp_reset_soc_data versal_net_reset_data = {
92
+
.reset_id = 0,
93
+
.num_resets = VERSAL_NET_NR_RESETS,
94
+
};
95
+
91
96
static const struct reset_control_ops zynqmp_reset_ops = {
92
97
.reset = zynqmp_reset_reset,
93
98
.assert = zynqmp_reset_assert,
···
112
107
if (!priv->data)
113
108
return -EINVAL;
114
109
115
-
platform_set_drvdata(pdev, priv);
116
-
117
110
priv->rcdev.ops = &zynqmp_reset_ops;
118
111
priv->rcdev.owner = THIS_MODULE;
119
112
priv->rcdev.of_node = pdev->dev.of_node;
···
125
122
static const struct of_device_id zynqmp_reset_dt_ids[] = {
126
123
{ .compatible = "xlnx,zynqmp-reset", .data = &zynqmp_reset_data, },
127
124
{ .compatible = "xlnx,versal-reset", .data = &versal_reset_data, },
125
+
{ .compatible = "xlnx,versal-net-reset", .data = &versal_net_reset_data, },
128
126
{ /* sentinel */ },
129
127
};
130
128
+5
-5
drivers/rpmsg/qcom_smd.c
+5
-5
drivers/rpmsg/qcom_smd.c
···
1479
1479
struct qcom_smd_edge *edge;
1480
1480
int ret;
1481
1481
1482
+
if (!qcom_smem_is_available())
1483
+
return ERR_PTR(-EPROBE_DEFER);
1484
+
1482
1485
edge = kzalloc(sizeof(*edge), GFP_KERNEL);
1483
1486
if (!edge)
1484
1487
return ERR_PTR(-ENOMEM);
···
1556
1553
static int qcom_smd_probe(struct platform_device *pdev)
1557
1554
{
1558
1555
struct device_node *node;
1559
-
void *p;
1560
1556
1561
-
/* Wait for smem */
1562
-
p = qcom_smem_get(QCOM_SMEM_HOST_ANY, smem_items[0].alloc_tbl_id, NULL);
1563
-
if (PTR_ERR(p) == -EPROBE_DEFER)
1564
-
return PTR_ERR(p);
1557
+
if (!qcom_smem_is_available())
1558
+
return -EPROBE_DEFER;
1565
1559
1566
1560
for_each_available_child_of_node(pdev->dev.of_node, node)
1567
1561
qcom_smd_register_edge(&pdev->dev, node);
+1
drivers/soc/Kconfig
+1
drivers/soc/Kconfig
+1
drivers/soc/Makefile
+1
drivers/soc/Makefile
+1
drivers/soc/amlogic/meson-canvas.c
+1
drivers/soc/amlogic/meson-canvas.c
+21
drivers/soc/hisilicon/Kconfig
+21
drivers/soc/hisilicon/Kconfig
···
1
+
# SPDX-License-Identifier: GPL-2.0-only
2
+
3
+
menu "Hisilicon SoC drivers"
4
+
depends on ARCH_HISI || COMPILE_TEST
5
+
6
+
config KUNPENG_HCCS
7
+
tristate "HCCS driver on Kunpeng SoC"
8
+
depends on ACPI
9
+
depends on MAILBOX
10
+
depends on ARM64 || COMPILE_TEST
11
+
help
12
+
The Huawei Cache Coherence System (HCCS) is a multi-chip
13
+
interconnection bus protocol.
14
+
The performance of application may be affected if some HCCS
15
+
ports are not in full lane status, have a large number of CRC
16
+
errors and so on.
17
+
18
+
Say M here if you want to include support for querying the
19
+
health status and port information of HCCS on Kunpeng SoC.
20
+
21
+
endmenu
+2
drivers/soc/hisilicon/Makefile
+2
drivers/soc/hisilicon/Makefile
+1276
drivers/soc/hisilicon/kunpeng_hccs.c
+1276
drivers/soc/hisilicon/kunpeng_hccs.c
···
1
+
// SPDX-License-Identifier: GPL-2.0+
2
+
/*
3
+
* The Huawei Cache Coherence System (HCCS) is a multi-chip interconnection
4
+
* bus protocol.
5
+
*
6
+
* Copyright (c) 2023 Hisilicon Limited.
7
+
* Author: Huisong Li <lihuisong@huawei.com>
8
+
*
9
+
* HCCS driver for Kunpeng SoC provides the following features:
10
+
* - Retrieve the following information about each port:
11
+
* - port type
12
+
* - lane mode
13
+
* - enable
14
+
* - current lane mode
15
+
* - link finite state machine
16
+
* - lane mask
17
+
* - CRC error count
18
+
*
19
+
* - Retrieve the following information about all the ports on the chip or
20
+
* the die:
21
+
* - if all enabled ports are in linked
22
+
* - if all linked ports are in full lane
23
+
* - CRC error count sum
24
+
*/
25
+
#include <linux/acpi.h>
26
+
#include <linux/iopoll.h>
27
+
#include <linux/platform_device.h>
28
+
#include <linux/sysfs.h>
29
+
30
+
#include <acpi/pcc.h>
31
+
32
+
#include "kunpeng_hccs.h"
33
+
34
+
/* PCC defines */
35
+
#define HCCS_PCC_SIGNATURE_MASK 0x50434300
36
+
#define HCCS_PCC_STATUS_CMD_COMPLETE BIT(0)
37
+
38
+
/*
39
+
* Arbitrary retries in case the remote processor is slow to respond
40
+
* to PCC commands
41
+
*/
42
+
#define HCCS_PCC_CMD_WAIT_RETRIES_NUM 500ULL
43
+
#define HCCS_POLL_STATUS_TIME_INTERVAL_US 3
44
+
45
+
static struct hccs_port_info *kobj_to_port_info(struct kobject *k)
46
+
{
47
+
return container_of(k, struct hccs_port_info, kobj);
48
+
}
49
+
50
+
static struct hccs_die_info *kobj_to_die_info(struct kobject *k)
51
+
{
52
+
return container_of(k, struct hccs_die_info, kobj);
53
+
}
54
+
55
+
static struct hccs_chip_info *kobj_to_chip_info(struct kobject *k)
56
+
{
57
+
return container_of(k, struct hccs_chip_info, kobj);
58
+
}
59
+
60
+
struct hccs_register_ctx {
61
+
struct device *dev;
62
+
u8 chan_id;
63
+
int err;
64
+
};
65
+
66
+
static acpi_status hccs_get_register_cb(struct acpi_resource *ares,
67
+
void *context)
68
+
{
69
+
struct acpi_resource_generic_register *reg;
70
+
struct hccs_register_ctx *ctx = context;
71
+
72
+
if (ares->type != ACPI_RESOURCE_TYPE_GENERIC_REGISTER)
73
+
return AE_OK;
74
+
75
+
reg = &ares->data.generic_reg;
76
+
if (reg->space_id != ACPI_ADR_SPACE_PLATFORM_COMM) {
77
+
dev_err(ctx->dev, "Bad register resource.\n");
78
+
ctx->err = -EINVAL;
79
+
return AE_ERROR;
80
+
}
81
+
ctx->chan_id = reg->access_size;
82
+
83
+
return AE_OK;
84
+
}
85
+
86
+
static int hccs_get_pcc_chan_id(struct hccs_dev *hdev)
87
+
{
88
+
acpi_handle handle = ACPI_HANDLE(hdev->dev);
89
+
struct hccs_register_ctx ctx = {0};
90
+
acpi_status status;
91
+
92
+
if (!acpi_has_method(handle, METHOD_NAME__CRS))
93
+
return -ENODEV;
94
+
95
+
ctx.dev = hdev->dev;
96
+
status = acpi_walk_resources(handle, METHOD_NAME__CRS,
97
+
hccs_get_register_cb, &ctx);
98
+
if (ACPI_FAILURE(status))
99
+
return ctx.err;
100
+
hdev->chan_id = ctx.chan_id;
101
+
102
+
return 0;
103
+
}
104
+
105
+
static void hccs_chan_tx_done(struct mbox_client *cl, void *msg, int ret)
106
+
{
107
+
if (ret < 0)
108
+
pr_debug("TX did not complete: CMD sent:0x%x, ret:%d\n",
109
+
*(u8 *)msg, ret);
110
+
else
111
+
pr_debug("TX completed. CMD sent:0x%x, ret:%d\n",
112
+
*(u8 *)msg, ret);
113
+
}
114
+
115
+
static void hccs_unregister_pcc_channel(struct hccs_dev *hdev)
116
+
{
117
+
struct hccs_mbox_client_info *cl_info = &hdev->cl_info;
118
+
119
+
if (cl_info->pcc_comm_addr)
120
+
iounmap(cl_info->pcc_comm_addr);
121
+
pcc_mbox_free_channel(hdev->cl_info.pcc_chan);
122
+
}
123
+
124
+
static int hccs_register_pcc_channel(struct hccs_dev *hdev)
125
+
{
126
+
struct hccs_mbox_client_info *cl_info = &hdev->cl_info;
127
+
struct mbox_client *cl = &cl_info->client;
128
+
struct pcc_mbox_chan *pcc_chan;
129
+
struct device *dev = hdev->dev;
130
+
int rc;
131
+
132
+
cl->dev = dev;
133
+
cl->tx_block = false;
134
+
cl->knows_txdone = true;
135
+
cl->tx_done = hccs_chan_tx_done;
136
+
pcc_chan = pcc_mbox_request_channel(cl, hdev->chan_id);
137
+
if (IS_ERR(pcc_chan)) {
138
+
dev_err(dev, "PPC channel request failed.\n");
139
+
rc = -ENODEV;
140
+
goto out;
141
+
}
142
+
cl_info->pcc_chan = pcc_chan;
143
+
cl_info->mbox_chan = pcc_chan->mchan;
144
+
145
+
/*
146
+
* pcc_chan->latency is just a nominal value. In reality the remote
147
+
* processor could be much slower to reply. So add an arbitrary amount
148
+
* of wait on top of nominal.
149
+
*/
150
+
cl_info->deadline_us =
151
+
HCCS_PCC_CMD_WAIT_RETRIES_NUM * pcc_chan->latency;
152
+
if (cl_info->mbox_chan->mbox->txdone_irq) {
153
+
dev_err(dev, "PCC IRQ in PCCT is enabled.\n");
154
+
rc = -EINVAL;
155
+
goto err_mbx_channel_free;
156
+
}
157
+
158
+
if (pcc_chan->shmem_base_addr) {
159
+
cl_info->pcc_comm_addr = ioremap(pcc_chan->shmem_base_addr,
160
+
pcc_chan->shmem_size);
161
+
if (!cl_info->pcc_comm_addr) {
162
+
dev_err(dev, "Failed to ioremap PCC communication region for channel-%d.\n",
163
+
hdev->chan_id);
164
+
rc = -ENOMEM;
165
+
goto err_mbx_channel_free;
166
+
}
167
+
}
168
+
169
+
return 0;
170
+
171
+
err_mbx_channel_free:
172
+
pcc_mbox_free_channel(cl_info->pcc_chan);
173
+
out:
174
+
return rc;
175
+
}
176
+
177
+
static int hccs_check_chan_cmd_complete(struct hccs_dev *hdev)
178
+
{
179
+
struct hccs_mbox_client_info *cl_info = &hdev->cl_info;
180
+
struct acpi_pcct_shared_memory __iomem *comm_base =
181
+
cl_info->pcc_comm_addr;
182
+
u16 status;
183
+
int ret;
184
+
185
+
/*
186
+
* Poll PCC status register every 3us(delay_us) for maximum of
187
+
* deadline_us(timeout_us) until PCC command complete bit is set(cond)
188
+
*/
189
+
ret = readw_poll_timeout(&comm_base->status, status,
190
+
status & HCCS_PCC_STATUS_CMD_COMPLETE,
191
+
HCCS_POLL_STATUS_TIME_INTERVAL_US,
192
+
cl_info->deadline_us);
193
+
if (unlikely(ret))
194
+
dev_err(hdev->dev, "poll PCC status failed, ret = %d.\n", ret);
195
+
196
+
return ret;
197
+
}
198
+
199
+
static int hccs_pcc_cmd_send(struct hccs_dev *hdev, u8 cmd,
200
+
struct hccs_desc *desc)
201
+
{
202
+
struct hccs_mbox_client_info *cl_info = &hdev->cl_info;
203
+
void __iomem *comm_space = cl_info->pcc_comm_addr +
204
+
sizeof(struct acpi_pcct_shared_memory);
205
+
struct hccs_fw_inner_head *fw_inner_head;
206
+
struct acpi_pcct_shared_memory tmp = {0};
207
+
u16 comm_space_size;
208
+
int ret;
209
+
210
+
/* Write signature for this subspace */
211
+
tmp.signature = HCCS_PCC_SIGNATURE_MASK | hdev->chan_id;
212
+
/* Write to the shared command region */
213
+
tmp.command = cmd;
214
+
/* Clear cmd complete bit */
215
+
tmp.status = 0;
216
+
memcpy_toio(cl_info->pcc_comm_addr, (void *)&tmp,
217
+
sizeof(struct acpi_pcct_shared_memory));
218
+
219
+
/* Copy the message to the PCC comm space */
220
+
comm_space_size = HCCS_PCC_SHARE_MEM_BYTES -
221
+
sizeof(struct acpi_pcct_shared_memory);
222
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memcpy_toio(comm_space, (void *)desc, comm_space_size);
223
+
224
+
/* Ring doorbell */
225
+
ret = mbox_send_message(cl_info->mbox_chan, &cmd);
226
+
if (ret < 0) {
227
+
dev_err(hdev->dev, "Send PCC mbox message failed, ret = %d.\n",
228
+
ret);
229
+
goto end;
230
+
}
231
+
232
+
/* Wait for completion */
233
+
ret = hccs_check_chan_cmd_complete(hdev);
234
+
if (ret)
235
+
goto end;
236
+
237
+
/* Copy response data */
238
+
memcpy_fromio((void *)desc, comm_space, comm_space_size);
239
+
fw_inner_head = &desc->rsp.fw_inner_head;
240
+
if (fw_inner_head->retStatus) {
241
+
dev_err(hdev->dev, "Execute PCC command failed, error code = %u.\n",
242
+
fw_inner_head->retStatus);
243
+
ret = -EIO;
244
+
}
245
+
246
+
end:
247
+
mbox_client_txdone(cl_info->mbox_chan, ret);
248
+
return ret;
249
+
}
250
+
251
+
static void hccs_init_req_desc(struct hccs_desc *desc)
252
+
{
253
+
struct hccs_req_desc *req = &desc->req;
254
+
255
+
memset(desc, 0, sizeof(*desc));
256
+
req->req_head.module_code = HCCS_SERDES_MODULE_CODE;
257
+
}
258
+
259
+
static int hccs_get_dev_caps(struct hccs_dev *hdev)
260
+
{
261
+
struct hccs_desc desc;
262
+
int ret;
263
+
264
+
hccs_init_req_desc(&desc);
265
+
ret = hccs_pcc_cmd_send(hdev, HCCS_GET_DEV_CAP, &desc);
266
+
if (ret) {
267
+
dev_err(hdev->dev, "Get device capabilities failed, ret = %d.\n",
268
+
ret);
269
+
return ret;
270
+
}
271
+
memcpy(&hdev->caps, desc.rsp.data, sizeof(hdev->caps));
272
+
273
+
return 0;
274
+
}
275
+
276
+
static int hccs_query_chip_num_on_platform(struct hccs_dev *hdev)
277
+
{
278
+
struct hccs_desc desc;
279
+
int ret;
280
+
281
+
hccs_init_req_desc(&desc);
282
+
ret = hccs_pcc_cmd_send(hdev, HCCS_GET_CHIP_NUM, &desc);
283
+
if (ret) {
284
+
dev_err(hdev->dev, "query system chip number failed, ret = %d.\n",
285
+
ret);
286
+
return ret;
287
+
}
288
+
289
+
hdev->chip_num = *((u8 *)&desc.rsp.data);
290
+
if (!hdev->chip_num) {
291
+
dev_err(hdev->dev, "chip num obtained from firmware is zero.\n");
292
+
return -EINVAL;
293
+
}
294
+
295
+
return 0;
296
+
}
297
+
298
+
static int hccs_get_chip_info(struct hccs_dev *hdev,
299
+
struct hccs_chip_info *chip)
300
+
{
301
+
struct hccs_die_num_req_param *req_param;
302
+
struct hccs_desc desc;
303
+
int ret;
304
+
305
+
hccs_init_req_desc(&desc);
306
+
req_param = (struct hccs_die_num_req_param *)desc.req.data;
307
+
req_param->chip_id = chip->chip_id;
308
+
ret = hccs_pcc_cmd_send(hdev, HCCS_GET_DIE_NUM, &desc);
309
+
if (ret)
310
+
return ret;
311
+
312
+
chip->die_num = *((u8 *)&desc.rsp.data);
313
+
314
+
return 0;
315
+
}
316
+
317
+
static int hccs_query_chip_info_on_platform(struct hccs_dev *hdev)
318
+
{
319
+
struct hccs_chip_info *chip;
320
+
int ret;
321
+
u8 idx;
322
+
323
+
ret = hccs_query_chip_num_on_platform(hdev);
324
+
if (ret) {
325
+
dev_err(hdev->dev, "query chip number on platform failed, ret = %d.\n",
326
+
ret);
327
+
return ret;
328
+
}
329
+
330
+
hdev->chips = devm_kzalloc(hdev->dev,
331
+
hdev->chip_num * sizeof(struct hccs_chip_info),
332
+
GFP_KERNEL);
333
+
if (!hdev->chips) {
334
+
dev_err(hdev->dev, "allocate all chips memory failed.\n");
335
+
return -ENOMEM;
336
+
}
337
+
338
+
for (idx = 0; idx < hdev->chip_num; idx++) {
339
+
chip = &hdev->chips[idx];
340
+
chip->chip_id = idx;
341
+
ret = hccs_get_chip_info(hdev, chip);
342
+
if (ret) {
343
+
dev_err(hdev->dev, "get chip%u info failed, ret = %d.\n",
344
+
idx, ret);
345
+
return ret;
346
+
}
347
+
chip->hdev = hdev;
348
+
}
349
+
350
+
return 0;
351
+
}
352
+
353
+
static int hccs_query_die_info_on_chip(struct hccs_dev *hdev, u8 chip_id,
354
+
u8 die_idx, struct hccs_die_info *die)
355
+
{
356
+
struct hccs_die_info_req_param *req_param;
357
+
struct hccs_die_info_rsp_data *rsp_data;
358
+
struct hccs_desc desc;
359
+
int ret;
360
+
361
+
hccs_init_req_desc(&desc);
362
+
req_param = (struct hccs_die_info_req_param *)desc.req.data;
363
+
req_param->chip_id = chip_id;
364
+
req_param->die_idx = die_idx;
365
+
ret = hccs_pcc_cmd_send(hdev, HCCS_GET_DIE_INFO, &desc);
366
+
if (ret)
367
+
return ret;
368
+
369
+
rsp_data = (struct hccs_die_info_rsp_data *)desc.rsp.data;
370
+
die->die_id = rsp_data->die_id;
371
+
die->port_num = rsp_data->port_num;
372
+
die->min_port_id = rsp_data->min_port_id;
373
+
die->max_port_id = rsp_data->max_port_id;
374
+
if (die->min_port_id > die->max_port_id) {
375
+
dev_err(hdev->dev, "min port id(%u) > max port id(%u) on die_idx(%u).\n",
376
+
die->min_port_id, die->max_port_id, die_idx);
377
+
return -EINVAL;
378
+
}
379
+
if (die->max_port_id > HCCS_DIE_MAX_PORT_ID) {
380
+
dev_err(hdev->dev, "max port id(%u) on die_idx(%u) is too big.\n",
381
+
die->max_port_id, die_idx);
382
+
return -EINVAL;
383
+
}
384
+
385
+
return 0;
386
+
}
387
+
388
+
static int hccs_query_all_die_info_on_platform(struct hccs_dev *hdev)
389
+
{
390
+
struct device *dev = hdev->dev;
391
+
struct hccs_chip_info *chip;
392
+
struct hccs_die_info *die;
393
+
u8 i, j;
394
+
int ret;
395
+
396
+
for (i = 0; i < hdev->chip_num; i++) {
397
+
chip = &hdev->chips[i];
398
+
if (!chip->die_num)
399
+
continue;
400
+
401
+
chip->dies = devm_kzalloc(hdev->dev,
402
+
chip->die_num * sizeof(struct hccs_die_info),
403
+
GFP_KERNEL);
404
+
if (!chip->dies) {
405
+
dev_err(dev, "allocate all dies memory on chip%u failed.\n",
406
+
i);
407
+
return -ENOMEM;
408
+
}
409
+
410
+
for (j = 0; j < chip->die_num; j++) {
411
+
die = &chip->dies[j];
412
+
ret = hccs_query_die_info_on_chip(hdev, i, j, die);
413
+
if (ret) {
414
+
dev_err(dev, "get die idx (%u) info on chip%u failed, ret = %d.\n",
415
+
j, i, ret);
416
+
return ret;
417
+
}
418
+
die->chip = chip;
419
+
}
420
+
}
421
+
422
+
return 0;
423
+
}
424
+
425
+
static int hccs_get_bd_info(struct hccs_dev *hdev, u8 opcode,
426
+
struct hccs_desc *desc,
427
+
void *buf, size_t buf_len,
428
+
struct hccs_rsp_head *rsp_head)
429
+
{
430
+
struct hccs_rsp_head *head;
431
+
struct hccs_rsp_desc *rsp;
432
+
int ret;
433
+
434
+
ret = hccs_pcc_cmd_send(hdev, opcode, desc);
435
+
if (ret)
436
+
return ret;
437
+
438
+
rsp = &desc->rsp;
439
+
head = &rsp->rsp_head;
440
+
if (head->data_len > buf_len) {
441
+
dev_err(hdev->dev,
442
+
"buffer overflow (buf_len = %zu, data_len = %u)!\n",
443
+
buf_len, head->data_len);
444
+
return -ENOMEM;
445
+
}
446
+
447
+
memcpy(buf, rsp->data, head->data_len);
448
+
*rsp_head = *head;
449
+
450
+
return 0;
451
+
}
452
+
453
+
static int hccs_get_all_port_attr(struct hccs_dev *hdev,
454
+
struct hccs_die_info *die,
455
+
struct hccs_port_attr *attrs, u16 size)
456
+
{
457
+
struct hccs_die_comm_req_param *req_param;
458
+
struct hccs_req_head *req_head;
459
+
struct hccs_rsp_head rsp_head;
460
+
struct hccs_desc desc;
461
+
size_t left_buf_len;
462
+
u32 data_len = 0;
463
+
u8 start_id;
464
+
u8 *buf;
465
+
int ret;
466
+
467
+
buf = (u8 *)attrs;
468
+
left_buf_len = sizeof(struct hccs_port_attr) * size;
469
+
start_id = die->min_port_id;
470
+
while (start_id <= die->max_port_id) {
471
+
hccs_init_req_desc(&desc);
472
+
req_head = &desc.req.req_head;
473
+
req_head->start_id = start_id;
474
+
req_param = (struct hccs_die_comm_req_param *)desc.req.data;
475
+
req_param->chip_id = die->chip->chip_id;
476
+
req_param->die_id = die->die_id;
477
+
478
+
ret = hccs_get_bd_info(hdev, HCCS_GET_DIE_PORT_INFO, &desc,
479
+
buf + data_len, left_buf_len, &rsp_head);
480
+
if (ret) {
481
+
dev_err(hdev->dev,
482
+
"get the information of port%u on die%u failed, ret = %d.\n",
483
+
start_id, die->die_id, ret);
484
+
return ret;
485
+
}
486
+
487
+
data_len += rsp_head.data_len;
488
+
left_buf_len -= rsp_head.data_len;
489
+
if (unlikely(rsp_head.next_id <= start_id)) {
490
+
dev_err(hdev->dev,
491
+
"next port id (%u) is not greater than last start id (%u) on die%u.\n",
492
+
rsp_head.next_id, start_id, die->die_id);
493
+
return -EINVAL;
494
+
}
495
+
start_id = rsp_head.next_id;
496
+
}
497
+
498
+
return 0;
499
+
}
500
+
501
+
static int hccs_get_all_port_info_on_die(struct hccs_dev *hdev,
502
+
struct hccs_die_info *die)
503
+
{
504
+
struct hccs_port_attr *attrs;
505
+
struct hccs_port_info *port;
506
+
int ret;
507
+
u8 i;
508
+
509
+
attrs = kcalloc(die->port_num, sizeof(struct hccs_port_attr),
510
+
GFP_KERNEL);
511
+
if (!attrs)
512
+
return -ENOMEM;
513
+
514
+
ret = hccs_get_all_port_attr(hdev, die, attrs, die->port_num);
515
+
if (ret)
516
+
goto out;
517
+
518
+
for (i = 0; i < die->port_num; i++) {
519
+
port = &die->ports[i];
520
+
port->port_id = attrs[i].port_id;
521
+
port->port_type = attrs[i].port_type;
522
+
port->lane_mode = attrs[i].lane_mode;
523
+
port->enable = attrs[i].enable;
524
+
port->die = die;
525
+
}
526
+
527
+
out:
528
+
kfree(attrs);
529
+
return ret;
530
+
}
531
+
532
+
static int hccs_query_all_port_info_on_platform(struct hccs_dev *hdev)
533
+
{
534
+
535
+
struct device *dev = hdev->dev;
536
+
struct hccs_chip_info *chip;
537
+
struct hccs_die_info *die;
538
+
u8 i, j;
539
+
int ret;
540
+
541
+
for (i = 0; i < hdev->chip_num; i++) {
542
+
chip = &hdev->chips[i];
543
+
for (j = 0; j < chip->die_num; j++) {
544
+
die = &chip->dies[j];
545
+
if (!die->port_num)
546
+
continue;
547
+
548
+
die->ports = devm_kzalloc(dev,
549
+
die->port_num * sizeof(struct hccs_port_info),
550
+
GFP_KERNEL);
551
+
if (!die->ports) {
552
+
dev_err(dev, "allocate ports memory on chip%u/die%u failed.\n",
553
+
i, die->die_id);
554
+
return -ENOMEM;
555
+
}
556
+
557
+
ret = hccs_get_all_port_info_on_die(hdev, die);
558
+
if (ret) {
559
+
dev_err(dev, "get all port info on chip%u/die%u failed, ret = %d.\n",
560
+
i, die->die_id, ret);
561
+
return ret;
562
+
}
563
+
}
564
+
}
565
+
566
+
return 0;
567
+
}
568
+
569
+
static int hccs_get_hw_info(struct hccs_dev *hdev)
570
+
{
571
+
int ret;
572
+
573
+
ret = hccs_query_chip_info_on_platform(hdev);
574
+
if (ret) {
575
+
dev_err(hdev->dev, "query chip info on platform failed, ret = %d.\n",
576
+
ret);
577
+
return ret;
578
+
}
579
+
580
+
ret = hccs_query_all_die_info_on_platform(hdev);
581
+
if (ret) {
582
+
dev_err(hdev->dev, "query all die info on platform failed, ret = %d.\n",
583
+
ret);
584
+
return ret;
585
+
}
586
+
587
+
ret = hccs_query_all_port_info_on_platform(hdev);
588
+
if (ret) {
589
+
dev_err(hdev->dev, "query all port info on platform failed, ret = %d.\n",
590
+
ret);
591
+
return ret;
592
+
}
593
+
594
+
return 0;
595
+
}
596
+
597
+
static int hccs_query_port_link_status(struct hccs_dev *hdev,
598
+
const struct hccs_port_info *port,
599
+
struct hccs_link_status *link_status)
600
+
{
601
+
const struct hccs_die_info *die = port->die;
602
+
const struct hccs_chip_info *chip = die->chip;
603
+
struct hccs_port_comm_req_param *req_param;
604
+
struct hccs_desc desc;
605
+
int ret;
606
+
607
+
hccs_init_req_desc(&desc);
608
+
req_param = (struct hccs_port_comm_req_param *)desc.req.data;
609
+
req_param->chip_id = chip->chip_id;
610
+
req_param->die_id = die->die_id;
611
+
req_param->port_id = port->port_id;
612
+
ret = hccs_pcc_cmd_send(hdev, HCCS_GET_PORT_LINK_STATUS, &desc);
613
+
if (ret) {
614
+
dev_err(hdev->dev,
615
+
"get port link status info failed, ret = %d.\n", ret);
616
+
return ret;
617
+
}
618
+
619
+
*link_status = *((struct hccs_link_status *)desc.rsp.data);
620
+
621
+
return 0;
622
+
}
623
+
624
+
static int hccs_query_port_crc_err_cnt(struct hccs_dev *hdev,
625
+
const struct hccs_port_info *port,
626
+
u64 *crc_err_cnt)
627
+
{
628
+
const struct hccs_die_info *die = port->die;
629
+
const struct hccs_chip_info *chip = die->chip;
630
+
struct hccs_port_comm_req_param *req_param;
631
+
struct hccs_desc desc;
632
+
int ret;
633
+
634
+
hccs_init_req_desc(&desc);
635
+
req_param = (struct hccs_port_comm_req_param *)desc.req.data;
636
+
req_param->chip_id = chip->chip_id;
637
+
req_param->die_id = die->die_id;
638
+
req_param->port_id = port->port_id;
639
+
ret = hccs_pcc_cmd_send(hdev, HCCS_GET_PORT_CRC_ERR_CNT, &desc);
640
+
if (ret) {
641
+
dev_err(hdev->dev,
642
+
"get port crc error count failed, ret = %d.\n", ret);
643
+
return ret;
644
+
}
645
+
646
+
memcpy(crc_err_cnt, &desc.rsp.data, sizeof(u64));
647
+
648
+
return 0;
649
+
}
650
+
651
+
static int hccs_get_die_all_link_status(struct hccs_dev *hdev,
652
+
const struct hccs_die_info *die,
653
+
u8 *all_linked)
654
+
{
655
+
struct hccs_die_comm_req_param *req_param;
656
+
struct hccs_desc desc;
657
+
int ret;
658
+
659
+
if (die->port_num == 0) {
660
+
*all_linked = 1;
661
+
return 0;
662
+
}
663
+
664
+
hccs_init_req_desc(&desc);
665
+
req_param = (struct hccs_die_comm_req_param *)desc.req.data;
666
+
req_param->chip_id = die->chip->chip_id;
667
+
req_param->die_id = die->die_id;
668
+
ret = hccs_pcc_cmd_send(hdev, HCCS_GET_DIE_PORTS_LINK_STA, &desc);
669
+
if (ret) {
670
+
dev_err(hdev->dev,
671
+
"get link status of all ports failed on die%u, ret = %d.\n",
672
+
die->die_id, ret);
673
+
return ret;
674
+
}
675
+
676
+
*all_linked = *((u8 *)&desc.rsp.data);
677
+
678
+
return 0;
679
+
}
680
+
681
+
static int hccs_get_die_all_port_lane_status(struct hccs_dev *hdev,
682
+
const struct hccs_die_info *die,
683
+
u8 *full_lane)
684
+
{
685
+
struct hccs_die_comm_req_param *req_param;
686
+
struct hccs_desc desc;
687
+
int ret;
688
+
689
+
if (die->port_num == 0) {
690
+
*full_lane = 1;
691
+
return 0;
692
+
}
693
+
694
+
hccs_init_req_desc(&desc);
695
+
req_param = (struct hccs_die_comm_req_param *)desc.req.data;
696
+
req_param->chip_id = die->chip->chip_id;
697
+
req_param->die_id = die->die_id;
698
+
ret = hccs_pcc_cmd_send(hdev, HCCS_GET_DIE_PORTS_LANE_STA, &desc);
699
+
if (ret) {
700
+
dev_err(hdev->dev, "get lane status of all ports failed on die%u, ret = %d.\n",
701
+
die->die_id, ret);
702
+
return ret;
703
+
}
704
+
705
+
*full_lane = *((u8 *)&desc.rsp.data);
706
+
707
+
return 0;
708
+
}
709
+
710
+
static int hccs_get_die_total_crc_err_cnt(struct hccs_dev *hdev,
711
+
const struct hccs_die_info *die,
712
+
u64 *total_crc_err_cnt)
713
+
{
714
+
struct hccs_die_comm_req_param *req_param;
715
+
struct hccs_desc desc;
716
+
int ret;
717
+
718
+
if (die->port_num == 0) {
719
+
*total_crc_err_cnt = 0;
720
+
return 0;
721
+
}
722
+
723
+
hccs_init_req_desc(&desc);
724
+
req_param = (struct hccs_die_comm_req_param *)desc.req.data;
725
+
req_param->chip_id = die->chip->chip_id;
726
+
req_param->die_id = die->die_id;
727
+
ret = hccs_pcc_cmd_send(hdev, HCCS_GET_DIE_PORTS_CRC_ERR_CNT, &desc);
728
+
if (ret) {
729
+
dev_err(hdev->dev, "get crc error count sum failed on die%u, ret = %d.\n",
730
+
die->die_id, ret);
731
+
return ret;
732
+
}
733
+
734
+
memcpy(total_crc_err_cnt, &desc.rsp.data, sizeof(u64));
735
+
736
+
return 0;
737
+
}
738
+
739
+
static ssize_t hccs_show(struct kobject *k, struct attribute *attr, char *buf)
740
+
{
741
+
struct kobj_attribute *kobj_attr;
742
+
743
+
kobj_attr = container_of(attr, struct kobj_attribute, attr);
744
+
745
+
return kobj_attr->show(k, kobj_attr, buf);
746
+
}
747
+
748
+
static const struct sysfs_ops hccs_comm_ops = {
749
+
.show = hccs_show,
750
+
};
751
+
752
+
static ssize_t type_show(struct kobject *kobj, struct kobj_attribute *attr,
753
+
char *buf)
754
+
{
755
+
const struct hccs_port_info *port = kobj_to_port_info(kobj);
756
+
757
+
return sysfs_emit(buf, "HCCS-v%u\n", port->port_type);
758
+
}
759
+
static struct kobj_attribute hccs_type_attr = __ATTR_RO(type);
760
+
761
+
static ssize_t lane_mode_show(struct kobject *kobj, struct kobj_attribute *attr,
762
+
char *buf)
763
+
{
764
+
const struct hccs_port_info *port = kobj_to_port_info(kobj);
765
+
766
+
return sysfs_emit(buf, "x%u\n", port->lane_mode);
767
+
}
768
+
static struct kobj_attribute lane_mode_attr = __ATTR_RO(lane_mode);
769
+
770
+
static ssize_t enable_show(struct kobject *kobj,
771
+
struct kobj_attribute *attr, char *buf)
772
+
{
773
+
const struct hccs_port_info *port = kobj_to_port_info(kobj);
774
+
775
+
return sysfs_emit(buf, "%u\n", port->enable);
776
+
}
777
+
static struct kobj_attribute port_enable_attr = __ATTR_RO(enable);
778
+
779
+
static ssize_t cur_lane_num_show(struct kobject *kobj,
780
+
struct kobj_attribute *attr, char *buf)
781
+
{
782
+
const struct hccs_port_info *port = kobj_to_port_info(kobj);
783
+
struct hccs_dev *hdev = port->die->chip->hdev;
784
+
struct hccs_link_status link_status = {0};
785
+
int ret;
786
+
787
+
mutex_lock(&hdev->lock);
788
+
ret = hccs_query_port_link_status(hdev, port, &link_status);
789
+
mutex_unlock(&hdev->lock);
790
+
if (ret)
791
+
return ret;
792
+
793
+
return sysfs_emit(buf, "%u\n", link_status.lane_num);
794
+
}
795
+
static struct kobj_attribute cur_lane_num_attr = __ATTR_RO(cur_lane_num);
796
+
797
+
static ssize_t link_fsm_show(struct kobject *kobj,
798
+
struct kobj_attribute *attr, char *buf)
799
+
{
800
+
const struct hccs_port_info *port = kobj_to_port_info(kobj);
801
+
struct hccs_dev *hdev = port->die->chip->hdev;
802
+
struct hccs_link_status link_status = {0};
803
+
const struct {
804
+
u8 link_fsm;
805
+
char *str;
806
+
} link_fsm_map[] = {
807
+
{HCCS_PORT_RESET, "reset"},
808
+
{HCCS_PORT_SETUP, "setup"},
809
+
{HCCS_PORT_CONFIG, "config"},
810
+
{HCCS_PORT_READY, "link-up"},
811
+
};
812
+
const char *link_fsm_str = "unknown";
813
+
size_t i;
814
+
int ret;
815
+
816
+
mutex_lock(&hdev->lock);
817
+
ret = hccs_query_port_link_status(hdev, port, &link_status);
818
+
mutex_unlock(&hdev->lock);
819
+
if (ret)
820
+
return ret;
821
+
822
+
for (i = 0; i < ARRAY_SIZE(link_fsm_map); i++) {
823
+
if (link_fsm_map[i].link_fsm == link_status.link_fsm) {
824
+
link_fsm_str = link_fsm_map[i].str;
825
+
break;
826
+
}
827
+
}
828
+
829
+
return sysfs_emit(buf, "%s\n", link_fsm_str);
830
+
}
831
+
static struct kobj_attribute link_fsm_attr = __ATTR_RO(link_fsm);
832
+
833
+
static ssize_t lane_mask_show(struct kobject *kobj,
834
+
struct kobj_attribute *attr, char *buf)
835
+
{
836
+
const struct hccs_port_info *port = kobj_to_port_info(kobj);
837
+
struct hccs_dev *hdev = port->die->chip->hdev;
838
+
struct hccs_link_status link_status = {0};
839
+
int ret;
840
+
841
+
mutex_lock(&hdev->lock);
842
+
ret = hccs_query_port_link_status(hdev, port, &link_status);
843
+
mutex_unlock(&hdev->lock);
844
+
if (ret)
845
+
return ret;
846
+
847
+
return sysfs_emit(buf, "0x%x\n", link_status.lane_mask);
848
+
}
849
+
static struct kobj_attribute lane_mask_attr = __ATTR_RO(lane_mask);
850
+
851
+
static ssize_t crc_err_cnt_show(struct kobject *kobj,
852
+
struct kobj_attribute *attr, char *buf)
853
+
{
854
+
const struct hccs_port_info *port = kobj_to_port_info(kobj);
855
+
struct hccs_dev *hdev = port->die->chip->hdev;
856
+
u64 crc_err_cnt;
857
+
int ret;
858
+
859
+
mutex_lock(&hdev->lock);
860
+
ret = hccs_query_port_crc_err_cnt(hdev, port, &crc_err_cnt);
861
+
mutex_unlock(&hdev->lock);
862
+
if (ret)
863
+
return ret;
864
+
865
+
return sysfs_emit(buf, "%llu\n", crc_err_cnt);
866
+
}
867
+
static struct kobj_attribute crc_err_cnt_attr = __ATTR_RO(crc_err_cnt);
868
+
869
+
static struct attribute *hccs_port_default_attrs[] = {
870
+
&hccs_type_attr.attr,
871
+
&lane_mode_attr.attr,
872
+
&port_enable_attr.attr,
873
+
&cur_lane_num_attr.attr,
874
+
&link_fsm_attr.attr,
875
+
&lane_mask_attr.attr,
876
+
&crc_err_cnt_attr.attr,
877
+
NULL,
878
+
};
879
+
ATTRIBUTE_GROUPS(hccs_port_default);
880
+
881
+
static const struct kobj_type hccs_port_type = {
882
+
.sysfs_ops = &hccs_comm_ops,
883
+
.default_groups = hccs_port_default_groups,
884
+
};
885
+
886
+
static ssize_t all_linked_on_die_show(struct kobject *kobj,
887
+
struct kobj_attribute *attr, char *buf)
888
+
{
889
+
const struct hccs_die_info *die = kobj_to_die_info(kobj);
890
+
struct hccs_dev *hdev = die->chip->hdev;
891
+
u8 all_linked;
892
+
int ret;
893
+
894
+
mutex_lock(&hdev->lock);
895
+
ret = hccs_get_die_all_link_status(hdev, die, &all_linked);
896
+
mutex_unlock(&hdev->lock);
897
+
if (ret)
898
+
return ret;
899
+
900
+
return sysfs_emit(buf, "%u\n", all_linked);
901
+
}
902
+
static struct kobj_attribute all_linked_on_die_attr =
903
+
__ATTR(all_linked, 0444, all_linked_on_die_show, NULL);
904
+
905
+
static ssize_t linked_full_lane_on_die_show(struct kobject *kobj,
906
+
struct kobj_attribute *attr,
907
+
char *buf)
908
+
{
909
+
const struct hccs_die_info *die = kobj_to_die_info(kobj);
910
+
struct hccs_dev *hdev = die->chip->hdev;
911
+
u8 full_lane;
912
+
int ret;
913
+
914
+
mutex_lock(&hdev->lock);
915
+
ret = hccs_get_die_all_port_lane_status(hdev, die, &full_lane);
916
+
mutex_unlock(&hdev->lock);
917
+
if (ret)
918
+
return ret;
919
+
920
+
return sysfs_emit(buf, "%u\n", full_lane);
921
+
}
922
+
static struct kobj_attribute linked_full_lane_on_die_attr =
923
+
__ATTR(linked_full_lane, 0444, linked_full_lane_on_die_show, NULL);
924
+
925
+
static ssize_t crc_err_cnt_sum_on_die_show(struct kobject *kobj,
926
+
struct kobj_attribute *attr,
927
+
char *buf)
928
+
{
929
+
const struct hccs_die_info *die = kobj_to_die_info(kobj);
930
+
struct hccs_dev *hdev = die->chip->hdev;
931
+
u64 total_crc_err_cnt;
932
+
int ret;
933
+
934
+
mutex_lock(&hdev->lock);
935
+
ret = hccs_get_die_total_crc_err_cnt(hdev, die, &total_crc_err_cnt);
936
+
mutex_unlock(&hdev->lock);
937
+
if (ret)
938
+
return ret;
939
+
940
+
return sysfs_emit(buf, "%llu\n", total_crc_err_cnt);
941
+
}
942
+
static struct kobj_attribute crc_err_cnt_sum_on_die_attr =
943
+
__ATTR(crc_err_cnt, 0444, crc_err_cnt_sum_on_die_show, NULL);
944
+
945
+
static struct attribute *hccs_die_default_attrs[] = {
946
+
&all_linked_on_die_attr.attr,
947
+
&linked_full_lane_on_die_attr.attr,
948
+
&crc_err_cnt_sum_on_die_attr.attr,
949
+
NULL,
950
+
};
951
+
ATTRIBUTE_GROUPS(hccs_die_default);
952
+
953
+
static const struct kobj_type hccs_die_type = {
954
+
.sysfs_ops = &hccs_comm_ops,
955
+
.default_groups = hccs_die_default_groups,
956
+
};
957
+
958
+
static ssize_t all_linked_on_chip_show(struct kobject *kobj,
959
+
struct kobj_attribute *attr, char *buf)
960
+
{
961
+
const struct hccs_chip_info *chip = kobj_to_chip_info(kobj);
962
+
struct hccs_dev *hdev = chip->hdev;
963
+
const struct hccs_die_info *die;
964
+
u8 all_linked = 1;
965
+
u8 i, tmp;
966
+
int ret;
967
+
968
+
mutex_lock(&hdev->lock);
969
+
for (i = 0; i < chip->die_num; i++) {
970
+
die = &chip->dies[i];
971
+
ret = hccs_get_die_all_link_status(hdev, die, &tmp);
972
+
if (ret) {
973
+
mutex_unlock(&hdev->lock);
974
+
return ret;
975
+
}
976
+
if (tmp != all_linked) {
977
+
all_linked = 0;
978
+
break;
979
+
}
980
+
}
981
+
mutex_unlock(&hdev->lock);
982
+
983
+
return sysfs_emit(buf, "%u\n", all_linked);
984
+
}
985
+
static struct kobj_attribute all_linked_on_chip_attr =
986
+
__ATTR(all_linked, 0444, all_linked_on_chip_show, NULL);
987
+
988
+
static ssize_t linked_full_lane_on_chip_show(struct kobject *kobj,
989
+
struct kobj_attribute *attr,
990
+
char *buf)
991
+
{
992
+
const struct hccs_chip_info *chip = kobj_to_chip_info(kobj);
993
+
struct hccs_dev *hdev = chip->hdev;
994
+
const struct hccs_die_info *die;
995
+
u8 full_lane = 1;
996
+
u8 i, tmp;
997
+
int ret;
998
+
999
+
mutex_lock(&hdev->lock);
1000
+
for (i = 0; i < chip->die_num; i++) {
1001
+
die = &chip->dies[i];
1002
+
ret = hccs_get_die_all_port_lane_status(hdev, die, &tmp);
1003
+
if (ret) {
1004
+
mutex_unlock(&hdev->lock);
1005
+
return ret;
1006
+
}
1007
+
if (tmp != full_lane) {
1008
+
full_lane = 0;
1009
+
break;
1010
+
}
1011
+
}
1012
+
mutex_unlock(&hdev->lock);
1013
+
1014
+
return sysfs_emit(buf, "%u\n", full_lane);
1015
+
}
1016
+
static struct kobj_attribute linked_full_lane_on_chip_attr =
1017
+
__ATTR(linked_full_lane, 0444, linked_full_lane_on_chip_show, NULL);
1018
+
1019
+
static ssize_t crc_err_cnt_sum_on_chip_show(struct kobject *kobj,
1020
+
struct kobj_attribute *attr,
1021
+
char *buf)
1022
+
{
1023
+
const struct hccs_chip_info *chip = kobj_to_chip_info(kobj);
1024
+
u64 crc_err_cnt, total_crc_err_cnt = 0;
1025
+
struct hccs_dev *hdev = chip->hdev;
1026
+
const struct hccs_die_info *die;
1027
+
int ret;
1028
+
u16 i;
1029
+
1030
+
mutex_lock(&hdev->lock);
1031
+
for (i = 0; i < chip->die_num; i++) {
1032
+
die = &chip->dies[i];
1033
+
ret = hccs_get_die_total_crc_err_cnt(hdev, die, &crc_err_cnt);
1034
+
if (ret) {
1035
+
mutex_unlock(&hdev->lock);
1036
+
return ret;
1037
+
}
1038
+
1039
+
total_crc_err_cnt += crc_err_cnt;
1040
+
}
1041
+
mutex_unlock(&hdev->lock);
1042
+
1043
+
return sysfs_emit(buf, "%llu\n", total_crc_err_cnt);
1044
+
}
1045
+
static struct kobj_attribute crc_err_cnt_sum_on_chip_attr =
1046
+
__ATTR(crc_err_cnt, 0444, crc_err_cnt_sum_on_chip_show, NULL);
1047
+
1048
+
static struct attribute *hccs_chip_default_attrs[] = {
1049
+
&all_linked_on_chip_attr.attr,
1050
+
&linked_full_lane_on_chip_attr.attr,
1051
+
&crc_err_cnt_sum_on_chip_attr.attr,
1052
+
NULL,
1053
+
};
1054
+
ATTRIBUTE_GROUPS(hccs_chip_default);
1055
+
1056
+
static const struct kobj_type hccs_chip_type = {
1057
+
.sysfs_ops = &hccs_comm_ops,
1058
+
.default_groups = hccs_chip_default_groups,
1059
+
};
1060
+
1061
+
static void hccs_remove_die_dir(struct hccs_die_info *die)
1062
+
{
1063
+
struct hccs_port_info *port;
1064
+
u8 i;
1065
+
1066
+
for (i = 0; i < die->port_num; i++) {
1067
+
port = &die->ports[i];
1068
+
if (port->dir_created)
1069
+
kobject_put(&port->kobj);
1070
+
}
1071
+
1072
+
kobject_put(&die->kobj);
1073
+
}
1074
+
1075
+
static void hccs_remove_chip_dir(struct hccs_chip_info *chip)
1076
+
{
1077
+
struct hccs_die_info *die;
1078
+
u8 i;
1079
+
1080
+
for (i = 0; i < chip->die_num; i++) {
1081
+
die = &chip->dies[i];
1082
+
if (die->dir_created)
1083
+
hccs_remove_die_dir(die);
1084
+
}
1085
+
1086
+
kobject_put(&chip->kobj);
1087
+
}
1088
+
1089
+
static void hccs_remove_topo_dirs(struct hccs_dev *hdev)
1090
+
{
1091
+
u8 i;
1092
+
1093
+
for (i = 0; i < hdev->chip_num; i++)
1094
+
hccs_remove_chip_dir(&hdev->chips[i]);
1095
+
}
1096
+
1097
+
static int hccs_create_hccs_dir(struct hccs_dev *hdev,
1098
+
struct hccs_die_info *die,
1099
+
struct hccs_port_info *port)
1100
+
{
1101
+
int ret;
1102
+
1103
+
ret = kobject_init_and_add(&port->kobj, &hccs_port_type,
1104
+
&die->kobj, "hccs%d", port->port_id);
1105
+
if (ret) {
1106
+
kobject_put(&port->kobj);
1107
+
return ret;
1108
+
}
1109
+
1110
+
return 0;
1111
+
}
1112
+
1113
+
static int hccs_create_die_dir(struct hccs_dev *hdev,
1114
+
struct hccs_chip_info *chip,
1115
+
struct hccs_die_info *die)
1116
+
{
1117
+
struct hccs_port_info *port;
1118
+
int ret;
1119
+
u16 i;
1120
+
1121
+
ret = kobject_init_and_add(&die->kobj, &hccs_die_type,
1122
+
&chip->kobj, "die%d", die->die_id);
1123
+
if (ret) {
1124
+
kobject_put(&die->kobj);
1125
+
return ret;
1126
+
}
1127
+
1128
+
for (i = 0; i < die->port_num; i++) {
1129
+
port = &die->ports[i];
1130
+
ret = hccs_create_hccs_dir(hdev, die, port);
1131
+
if (ret) {
1132
+
dev_err(hdev->dev, "create hccs%d dir failed.\n",
1133
+
port->port_id);
1134
+
goto err;
1135
+
}
1136
+
port->dir_created = true;
1137
+
}
1138
+
1139
+
return 0;
1140
+
err:
1141
+
hccs_remove_die_dir(die);
1142
+
1143
+
return ret;
1144
+
}
1145
+
1146
+
static int hccs_create_chip_dir(struct hccs_dev *hdev,
1147
+
struct hccs_chip_info *chip)
1148
+
{
1149
+
struct hccs_die_info *die;
1150
+
int ret;
1151
+
u16 id;
1152
+
1153
+
ret = kobject_init_and_add(&chip->kobj, &hccs_chip_type,
1154
+
&hdev->dev->kobj, "chip%d", chip->chip_id);
1155
+
if (ret) {
1156
+
kobject_put(&chip->kobj);
1157
+
return ret;
1158
+
}
1159
+
1160
+
for (id = 0; id < chip->die_num; id++) {
1161
+
die = &chip->dies[id];
1162
+
ret = hccs_create_die_dir(hdev, chip, die);
1163
+
if (ret)
1164
+
goto err;
1165
+
die->dir_created = true;
1166
+
}
1167
+
1168
+
return 0;
1169
+
err:
1170
+
hccs_remove_chip_dir(chip);
1171
+
1172
+
return ret;
1173
+
}
1174
+
1175
+
static int hccs_create_topo_dirs(struct hccs_dev *hdev)
1176
+
{
1177
+
struct hccs_chip_info *chip;
1178
+
u8 id, k;
1179
+
int ret;
1180
+
1181
+
for (id = 0; id < hdev->chip_num; id++) {
1182
+
chip = &hdev->chips[id];
1183
+
ret = hccs_create_chip_dir(hdev, chip);
1184
+
if (ret) {
1185
+
dev_err(hdev->dev, "init chip%d dir failed!\n", id);
1186
+
goto err;
1187
+
}
1188
+
}
1189
+
1190
+
return 0;
1191
+
err:
1192
+
for (k = 0; k < id; k++)
1193
+
hccs_remove_chip_dir(&hdev->chips[k]);
1194
+
1195
+
return ret;
1196
+
}
1197
+
1198
+
static int hccs_probe(struct platform_device *pdev)
1199
+
{
1200
+
struct acpi_device *acpi_dev;
1201
+
struct hccs_dev *hdev;
1202
+
int rc;
1203
+
1204
+
if (acpi_disabled) {
1205
+
dev_err(&pdev->dev, "acpi is disabled.\n");
1206
+
return -ENODEV;
1207
+
}
1208
+
acpi_dev = ACPI_COMPANION(&pdev->dev);
1209
+
if (!acpi_dev)
1210
+
return -ENODEV;
1211
+
1212
+
hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
1213
+
if (!hdev)
1214
+
return -ENOMEM;
1215
+
hdev->acpi_dev = acpi_dev;
1216
+
hdev->dev = &pdev->dev;
1217
+
platform_set_drvdata(pdev, hdev);
1218
+
1219
+
mutex_init(&hdev->lock);
1220
+
rc = hccs_get_pcc_chan_id(hdev);
1221
+
if (rc)
1222
+
return rc;
1223
+
rc = hccs_register_pcc_channel(hdev);
1224
+
if (rc)
1225
+
return rc;
1226
+
1227
+
rc = hccs_get_dev_caps(hdev);
1228
+
if (rc)
1229
+
goto unregister_pcc_chan;
1230
+
1231
+
rc = hccs_get_hw_info(hdev);
1232
+
if (rc)
1233
+
goto unregister_pcc_chan;
1234
+
1235
+
rc = hccs_create_topo_dirs(hdev);
1236
+
if (rc)
1237
+
goto unregister_pcc_chan;
1238
+
1239
+
return 0;
1240
+
1241
+
unregister_pcc_chan:
1242
+
hccs_unregister_pcc_channel(hdev);
1243
+
1244
+
return rc;
1245
+
}
1246
+
1247
+
static int hccs_remove(struct platform_device *pdev)
1248
+
{
1249
+
struct hccs_dev *hdev = platform_get_drvdata(pdev);
1250
+
1251
+
hccs_remove_topo_dirs(hdev);
1252
+
hccs_unregister_pcc_channel(hdev);
1253
+
1254
+
return 0;
1255
+
}
1256
+
1257
+
static const struct acpi_device_id hccs_acpi_match[] = {
1258
+
{ "HISI04B1"},
1259
+
{ ""},
1260
+
};
1261
+
MODULE_DEVICE_TABLE(acpi, hccs_acpi_match);
1262
+
1263
+
static struct platform_driver hccs_driver = {
1264
+
.probe = hccs_probe,
1265
+
.remove = hccs_remove,
1266
+
.driver = {
1267
+
.name = "kunpeng_hccs",
1268
+
.acpi_match_table = hccs_acpi_match,
1269
+
},
1270
+
};
1271
+
1272
+
module_platform_driver(hccs_driver);
1273
+
1274
+
MODULE_DESCRIPTION("Kunpeng SoC HCCS driver");
1275
+
MODULE_LICENSE("GPL");
1276
+
MODULE_AUTHOR("Huisong Li <lihuisong@huawei.com>");
+191
drivers/soc/hisilicon/kunpeng_hccs.h
+191
drivers/soc/hisilicon/kunpeng_hccs.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0+ */
2
+
/* Copyright (c) 2023 Hisilicon Limited. */
3
+
4
+
#ifndef __KUNPENG_HCCS_H__
5
+
#define __KUNPENG_HCCS_H__
6
+
7
+
/*
8
+
* |--------------- Chip0 ---------------|---------------- ChipN -------------|
9
+
* |--------Die0-------|--------DieN-------|--------Die0-------|-------DieN-------|
10
+
* | P0 | P1 | P2 | P3 | P0 | P1 | P2 | P3 | P0 | P1 | P2 | P3 |P0 | P1 | P2 | P3 |
11
+
*/
12
+
13
+
/*
14
+
* This value cannot be 255, otherwise the loop of the multi-BD communication
15
+
* case cannot end.
16
+
*/
17
+
#define HCCS_DIE_MAX_PORT_ID 254
18
+
19
+
struct hccs_port_info {
20
+
u8 port_id;
21
+
u8 port_type;
22
+
u8 lane_mode;
23
+
bool enable; /* if the port is enabled */
24
+
struct kobject kobj;
25
+
bool dir_created;
26
+
struct hccs_die_info *die; /* point to the die the port is located */
27
+
};
28
+
29
+
struct hccs_die_info {
30
+
u8 die_id;
31
+
u8 port_num;
32
+
u8 min_port_id;
33
+
u8 max_port_id;
34
+
struct hccs_port_info *ports;
35
+
struct kobject kobj;
36
+
bool dir_created;
37
+
struct hccs_chip_info *chip; /* point to the chip the die is located */
38
+
};
39
+
40
+
struct hccs_chip_info {
41
+
u8 chip_id;
42
+
u8 die_num;
43
+
struct hccs_die_info *dies;
44
+
struct kobject kobj;
45
+
struct hccs_dev *hdev;
46
+
};
47
+
48
+
struct hccs_mbox_client_info {
49
+
struct mbox_client client;
50
+
struct mbox_chan *mbox_chan;
51
+
struct pcc_mbox_chan *pcc_chan;
52
+
u64 deadline_us;
53
+
void __iomem *pcc_comm_addr;
54
+
};
55
+
56
+
struct hccs_dev {
57
+
struct device *dev;
58
+
struct acpi_device *acpi_dev;
59
+
u64 caps;
60
+
u8 chip_num;
61
+
struct hccs_chip_info *chips;
62
+
u8 chan_id;
63
+
struct mutex lock;
64
+
struct hccs_mbox_client_info cl_info;
65
+
};
66
+
67
+
#define HCCS_SERDES_MODULE_CODE 0x32
68
+
enum hccs_subcmd_type {
69
+
HCCS_GET_CHIP_NUM = 0x1,
70
+
HCCS_GET_DIE_NUM,
71
+
HCCS_GET_DIE_INFO,
72
+
HCCS_GET_DIE_PORT_INFO,
73
+
HCCS_GET_DEV_CAP,
74
+
HCCS_GET_PORT_LINK_STATUS,
75
+
HCCS_GET_PORT_CRC_ERR_CNT,
76
+
HCCS_GET_DIE_PORTS_LANE_STA,
77
+
HCCS_GET_DIE_PORTS_LINK_STA,
78
+
HCCS_GET_DIE_PORTS_CRC_ERR_CNT,
79
+
HCCS_SUB_CMD_MAX = 255,
80
+
};
81
+
82
+
struct hccs_die_num_req_param {
83
+
u8 chip_id;
84
+
};
85
+
86
+
struct hccs_die_info_req_param {
87
+
u8 chip_id;
88
+
u8 die_idx;
89
+
};
90
+
91
+
struct hccs_die_info_rsp_data {
92
+
u8 die_id;
93
+
u8 port_num;
94
+
u8 min_port_id;
95
+
u8 max_port_id;
96
+
};
97
+
98
+
struct hccs_port_attr {
99
+
u8 port_id;
100
+
u8 port_type;
101
+
u8 lane_mode;
102
+
u8 enable : 1; /* if the port is enabled */
103
+
u16 rsv[2];
104
+
};
105
+
106
+
/*
107
+
* The common command request for getting the information of all HCCS port on
108
+
* specified DIE.
109
+
*/
110
+
struct hccs_die_comm_req_param {
111
+
u8 chip_id;
112
+
u8 die_id; /* id in hardware */
113
+
};
114
+
115
+
/* The common command request for getting the information of a specific port */
116
+
struct hccs_port_comm_req_param {
117
+
u8 chip_id;
118
+
u8 die_id;
119
+
u8 port_id;
120
+
};
121
+
122
+
#define HCCS_PORT_RESET 1
123
+
#define HCCS_PORT_SETUP 2
124
+
#define HCCS_PORT_CONFIG 3
125
+
#define HCCS_PORT_READY 4
126
+
struct hccs_link_status {
127
+
u8 lane_mask; /* indicate which lanes are used. */
128
+
u8 link_fsm : 3; /* link fsm, 1: reset 2: setup 3: config 4: link-up */
129
+
u8 lane_num : 5; /* current lane number */
130
+
};
131
+
132
+
struct hccs_req_head {
133
+
u8 module_code; /* set to 0x32 for serdes */
134
+
u8 start_id;
135
+
u8 rsv[2];
136
+
};
137
+
138
+
struct hccs_rsp_head {
139
+
u8 data_len;
140
+
u8 next_id;
141
+
u8 rsv[2];
142
+
};
143
+
144
+
struct hccs_fw_inner_head {
145
+
u8 retStatus; /* 0: success, other: failure */
146
+
u8 rsv[7];
147
+
};
148
+
149
+
#define HCCS_PCC_SHARE_MEM_BYTES 64
150
+
#define HCCS_FW_INNER_HEAD_BYTES 8
151
+
#define HCCS_RSP_HEAD_BYTES 4
152
+
153
+
#define HCCS_MAX_RSP_DATA_BYTES (HCCS_PCC_SHARE_MEM_BYTES - \
154
+
HCCS_FW_INNER_HEAD_BYTES - \
155
+
HCCS_RSP_HEAD_BYTES)
156
+
#define HCCS_MAX_RSP_DATA_SIZE_MAX (HCCS_MAX_RSP_DATA_BYTES / 4)
157
+
158
+
/*
159
+
* Note: Actual available size of data field also depands on the PCC header
160
+
* bytes of the specific type. Driver needs to copy the response data in the
161
+
* communication space based on the real length.
162
+
*/
163
+
struct hccs_rsp_desc {
164
+
struct hccs_fw_inner_head fw_inner_head; /* 8 Bytes */
165
+
struct hccs_rsp_head rsp_head; /* 4 Bytes */
166
+
u32 data[HCCS_MAX_RSP_DATA_SIZE_MAX];
167
+
};
168
+
169
+
#define HCCS_REQ_HEAD_BYTES 4
170
+
#define HCCS_MAX_REQ_DATA_BYTES (HCCS_PCC_SHARE_MEM_BYTES - \
171
+
HCCS_REQ_HEAD_BYTES)
172
+
#define HCCS_MAX_REQ_DATA_SIZE_MAX (HCCS_MAX_REQ_DATA_BYTES / 4)
173
+
174
+
/*
175
+
* Note: Actual available size of data field also depands on the PCC header
176
+
* bytes of the specific type. Driver needs to copy the request data to the
177
+
* communication space based on the real length.
178
+
*/
179
+
struct hccs_req_desc {
180
+
struct hccs_req_head req_head; /* 4 Bytes */
181
+
u32 data[HCCS_MAX_REQ_DATA_SIZE_MAX];
182
+
};
183
+
184
+
struct hccs_desc {
185
+
union {
186
+
struct hccs_req_desc req;
187
+
struct hccs_rsp_desc rsp;
188
+
};
189
+
};
190
+
191
+
#endif /* __KUNPENG_HCCS_H__ */
+10
drivers/soc/loongson/Kconfig
+10
drivers/soc/loongson/Kconfig
···
16
16
SoCs. Initially only reading SVR and registering soc device are
17
17
supported. Other guts accesses, such as reading firmware configuration
18
18
by default, should eventually be added into this driver as well.
19
+
20
+
config LOONGSON2_PM
21
+
bool "Loongson-2 SoC Power Management Controller Driver"
22
+
depends on LOONGARCH && OF
23
+
help
24
+
The Loongson-2's power management controller was ACPI, supports ACPI
25
+
S2Idle (Suspend To Idle), ACPI S3 (Suspend To RAM), ACPI S4 (Suspend To
26
+
Disk), ACPI S5 (Soft Shutdown) and supports multiple wake-up methods
27
+
(USB, GMAC, PWRBTN, etc.). This driver was to add power management
28
+
controller support that base on dts for Loongson-2 series SoCs.
+1
drivers/soc/loongson/Makefile
+1
drivers/soc/loongson/Makefile
+215
drivers/soc/loongson/loongson2_pm.c
+215
drivers/soc/loongson/loongson2_pm.c
···
1
+
// SPDX-License-Identifier: GPL-2.0+
2
+
/*
3
+
* Loongson-2 PM Support
4
+
*
5
+
* Copyright (C) 2023 Loongson Technology Corporation Limited
6
+
*/
7
+
8
+
#include <linux/io.h>
9
+
#include <linux/of.h>
10
+
#include <linux/init.h>
11
+
#include <linux/input.h>
12
+
#include <linux/suspend.h>
13
+
#include <linux/interrupt.h>
14
+
#include <linux/pm_wakeirq.h>
15
+
#include <linux/platform_device.h>
16
+
#include <asm/bootinfo.h>
17
+
#include <asm/suspend.h>
18
+
19
+
#define LOONGSON2_PM1_CNT_REG 0x14
20
+
#define LOONGSON2_PM1_STS_REG 0x0c
21
+
#define LOONGSON2_PM1_ENA_REG 0x10
22
+
#define LOONGSON2_GPE0_STS_REG 0x28
23
+
#define LOONGSON2_GPE0_ENA_REG 0x2c
24
+
25
+
#define LOONGSON2_PM1_PWRBTN_STS BIT(8)
26
+
#define LOONGSON2_PM1_PCIEXP_WAKE_STS BIT(14)
27
+
#define LOONGSON2_PM1_WAKE_STS BIT(15)
28
+
#define LOONGSON2_PM1_CNT_INT_EN BIT(0)
29
+
#define LOONGSON2_PM1_PWRBTN_EN LOONGSON2_PM1_PWRBTN_STS
30
+
31
+
static struct loongson2_pm {
32
+
void __iomem *base;
33
+
struct input_dev *dev;
34
+
bool suspended;
35
+
} loongson2_pm;
36
+
37
+
#define loongson2_pm_readw(reg) readw(loongson2_pm.base + reg)
38
+
#define loongson2_pm_readl(reg) readl(loongson2_pm.base + reg)
39
+
#define loongson2_pm_writew(val, reg) writew(val, loongson2_pm.base + reg)
40
+
#define loongson2_pm_writel(val, reg) writel(val, loongson2_pm.base + reg)
41
+
42
+
static void loongson2_pm_status_clear(void)
43
+
{
44
+
u16 value;
45
+
46
+
value = loongson2_pm_readw(LOONGSON2_PM1_STS_REG);
47
+
value |= (LOONGSON2_PM1_PWRBTN_STS | LOONGSON2_PM1_PCIEXP_WAKE_STS |
48
+
LOONGSON2_PM1_WAKE_STS);
49
+
loongson2_pm_writew(value, LOONGSON2_PM1_STS_REG);
50
+
loongson2_pm_writel(loongson2_pm_readl(LOONGSON2_GPE0_STS_REG), LOONGSON2_GPE0_STS_REG);
51
+
}
52
+
53
+
static void loongson2_pm_irq_enable(void)
54
+
{
55
+
u16 value;
56
+
57
+
value = loongson2_pm_readw(LOONGSON2_PM1_CNT_REG);
58
+
value |= LOONGSON2_PM1_CNT_INT_EN;
59
+
loongson2_pm_writew(value, LOONGSON2_PM1_CNT_REG);
60
+
61
+
value = loongson2_pm_readw(LOONGSON2_PM1_ENA_REG);
62
+
value |= LOONGSON2_PM1_PWRBTN_EN;
63
+
loongson2_pm_writew(value, LOONGSON2_PM1_ENA_REG);
64
+
}
65
+
66
+
static int loongson2_suspend_enter(suspend_state_t state)
67
+
{
68
+
loongson2_pm_status_clear();
69
+
loongarch_common_suspend();
70
+
loongarch_suspend_enter();
71
+
loongarch_common_resume();
72
+
loongson2_pm_irq_enable();
73
+
pm_set_resume_via_firmware();
74
+
75
+
return 0;
76
+
}
77
+
78
+
static int loongson2_suspend_begin(suspend_state_t state)
79
+
{
80
+
pm_set_suspend_via_firmware();
81
+
82
+
return 0;
83
+
}
84
+
85
+
static int loongson2_suspend_valid_state(suspend_state_t state)
86
+
{
87
+
return (state == PM_SUSPEND_MEM);
88
+
}
89
+
90
+
static const struct platform_suspend_ops loongson2_suspend_ops = {
91
+
.valid = loongson2_suspend_valid_state,
92
+
.begin = loongson2_suspend_begin,
93
+
.enter = loongson2_suspend_enter,
94
+
};
95
+
96
+
static int loongson2_power_button_init(struct device *dev, int irq)
97
+
{
98
+
int ret;
99
+
struct input_dev *button;
100
+
101
+
button = input_allocate_device();
102
+
if (!dev)
103
+
return -ENOMEM;
104
+
105
+
button->name = "Power Button";
106
+
button->phys = "pm/button/input0";
107
+
button->id.bustype = BUS_HOST;
108
+
button->dev.parent = NULL;
109
+
input_set_capability(button, EV_KEY, KEY_POWER);
110
+
111
+
ret = input_register_device(button);
112
+
if (ret)
113
+
goto free_dev;
114
+
115
+
dev_pm_set_wake_irq(&button->dev, irq);
116
+
device_set_wakeup_capable(&button->dev, true);
117
+
device_set_wakeup_enable(&button->dev, true);
118
+
119
+
loongson2_pm.dev = button;
120
+
dev_info(dev, "Power Button: Init successful!\n");
121
+
122
+
return 0;
123
+
124
+
free_dev:
125
+
input_free_device(button);
126
+
127
+
return ret;
128
+
}
129
+
130
+
static irqreturn_t loongson2_pm_irq_handler(int irq, void *dev_id)
131
+
{
132
+
u16 status = loongson2_pm_readw(LOONGSON2_PM1_STS_REG);
133
+
134
+
if (!loongson2_pm.suspended && (status & LOONGSON2_PM1_PWRBTN_STS)) {
135
+
pr_info("Power Button pressed...\n");
136
+
input_report_key(loongson2_pm.dev, KEY_POWER, 1);
137
+
input_sync(loongson2_pm.dev);
138
+
input_report_key(loongson2_pm.dev, KEY_POWER, 0);
139
+
input_sync(loongson2_pm.dev);
140
+
}
141
+
142
+
loongson2_pm_status_clear();
143
+
144
+
return IRQ_HANDLED;
145
+
}
146
+
147
+
static int __maybe_unused loongson2_pm_suspend(struct device *dev)
148
+
{
149
+
loongson2_pm.suspended = true;
150
+
151
+
return 0;
152
+
}
153
+
154
+
static int __maybe_unused loongson2_pm_resume(struct device *dev)
155
+
{
156
+
loongson2_pm.suspended = false;
157
+
158
+
return 0;
159
+
}
160
+
static SIMPLE_DEV_PM_OPS(loongson2_pm_ops, loongson2_pm_suspend, loongson2_pm_resume);
161
+
162
+
static int loongson2_pm_probe(struct platform_device *pdev)
163
+
{
164
+
int irq, retval;
165
+
u64 suspend_addr;
166
+
struct device *dev = &pdev->dev;
167
+
168
+
loongson2_pm.base = devm_platform_ioremap_resource(pdev, 0);
169
+
if (IS_ERR(loongson2_pm.base))
170
+
return PTR_ERR(loongson2_pm.base);
171
+
172
+
irq = platform_get_irq(pdev, 0);
173
+
if (irq < 0)
174
+
return irq;
175
+
176
+
if (!device_property_read_u64(dev, "loongson,suspend-address", &suspend_addr))
177
+
loongson_sysconf.suspend_addr = (u64)phys_to_virt(suspend_addr);
178
+
else
179
+
dev_err(dev, "No loongson,suspend-address, could not support S3!\n");
180
+
181
+
if (loongson2_power_button_init(dev, irq))
182
+
return -EINVAL;
183
+
184
+
retval = devm_request_irq(&pdev->dev, irq, loongson2_pm_irq_handler,
185
+
IRQF_SHARED, "pm_irq", &loongson2_pm);
186
+
if (retval)
187
+
return retval;
188
+
189
+
loongson2_pm_irq_enable();
190
+
loongson2_pm_status_clear();
191
+
192
+
if (loongson_sysconf.suspend_addr)
193
+
suspend_set_ops(&loongson2_suspend_ops);
194
+
195
+
return 0;
196
+
}
197
+
198
+
static const struct of_device_id loongson2_pm_match[] = {
199
+
{ .compatible = "loongson,ls2k0500-pmc", },
200
+
{ .compatible = "loongson,ls2k1000-pmc", },
201
+
{},
202
+
};
203
+
204
+
static struct platform_driver loongson2_pm_driver = {
205
+
.driver = {
206
+
.name = "ls2k-pm",
207
+
.pm = &loongson2_pm_ops,
208
+
.of_match_table = loongson2_pm_match,
209
+
},
210
+
.probe = loongson2_pm_probe,
211
+
};
212
+
module_platform_driver(loongson2_pm_driver);
213
+
214
+
MODULE_DESCRIPTION("Loongson-2 PM driver");
215
+
MODULE_LICENSE("GPL");
+1
drivers/soc/qcom/Kconfig
+1
drivers/soc/qcom/Kconfig
···
191
191
tristate "Qualcomm Resource Power Manager (RPM) over SMD"
192
192
depends on ARCH_QCOM || COMPILE_TEST
193
193
depends on RPMSG
194
+
depends on RPMSG_QCOM_SMD || RPMSG_QCOM_SMD=n
194
195
help
195
196
If you say yes to this option, support will be included for the
196
197
Resource Power Manager system found in the Qualcomm 8974 based
+1
-1
drivers/soc/qcom/Makefile
+1
-1
drivers/soc/qcom/Makefile
···
17
17
obj-$(CONFIG_QCOM_RPMH) += qcom_rpmh.o
18
18
qcom_rpmh-y += rpmh-rsc.o
19
19
qcom_rpmh-y += rpmh.o
20
-
obj-$(CONFIG_QCOM_SMD_RPM) += smd-rpm.o
20
+
obj-$(CONFIG_QCOM_SMD_RPM) += rpm-proc.o smd-rpm.o
21
21
obj-$(CONFIG_QCOM_SMEM) += smem.o
22
22
obj-$(CONFIG_QCOM_SMEM_STATE) += smem_state.o
23
23
obj-$(CONFIG_QCOM_SMP2P) += smp2p.o
+1
-1
drivers/soc/qcom/cmd-db.c
+1
-1
drivers/soc/qcom/cmd-db.c
···
284
284
ent = rsc_to_entry_header(rsc);
285
285
for (j = 0; j < le16_to_cpu(rsc->cnt); j++, ent++) {
286
286
seq_printf(seq, "0x%05x: %*pEp", le32_to_cpu(ent->addr),
287
-
(int)sizeof(ent->id), ent->id);
287
+
(int)strnlen(ent->id, sizeof(ent->id)), ent->id);
288
288
289
289
len = le16_to_cpu(ent->len);
290
290
if (len) {
+8
-22
drivers/soc/qcom/icc-bwmon.c
+8
-22
drivers/soc/qcom/icc-bwmon.c
···
12
12
#include <linux/io.h>
13
13
#include <linux/kernel.h>
14
14
#include <linux/module.h>
15
-
#include <linux/of_device.h>
15
+
#include <linux/of.h>
16
16
#include <linux/platform_device.h>
17
17
#include <linux/pm_opp.h>
18
18
#include <linux/regmap.h>
···
165
165
struct icc_bwmon_data {
166
166
unsigned int sample_ms;
167
167
unsigned int count_unit_kb; /* kbytes */
168
-
unsigned int default_highbw_kbps;
169
-
unsigned int default_medbw_kbps;
170
-
unsigned int default_lowbw_kbps;
171
168
u8 zone1_thres_count;
172
169
u8 zone3_thres_count;
173
170
unsigned int quirks;
···
561
564
static void bwmon_start(struct icc_bwmon *bwmon)
562
565
{
563
566
const struct icc_bwmon_data *data = bwmon->data;
567
+
u32 bw_low = 0;
564
568
int window;
569
+
570
+
/* No need to check for errors, as this must have succeeded before. */
571
+
dev_pm_opp_find_bw_ceil(bwmon->dev, &bw_low, 0);
565
572
566
573
bwmon_clear_counters(bwmon, true);
567
574
···
573
572
/* Maximum sampling window: 0xffffff for v4 and 0xfffff for v5 */
574
573
regmap_field_write(bwmon->regs[F_SAMPLE_WINDOW], window);
575
574
576
-
bwmon_set_threshold(bwmon, bwmon->regs[F_THRESHOLD_HIGH],
577
-
data->default_highbw_kbps);
578
-
bwmon_set_threshold(bwmon, bwmon->regs[F_THRESHOLD_MED],
579
-
data->default_medbw_kbps);
580
-
bwmon_set_threshold(bwmon, bwmon->regs[F_THRESHOLD_LOW],
581
-
data->default_lowbw_kbps);
575
+
bwmon_set_threshold(bwmon, bwmon->regs[F_THRESHOLD_HIGH], bw_low);
576
+
bwmon_set_threshold(bwmon, bwmon->regs[F_THRESHOLD_MED], bw_low);
577
+
bwmon_set_threshold(bwmon, bwmon->regs[F_THRESHOLD_LOW], 0);
582
578
583
579
regmap_field_write(bwmon->regs[F_THRESHOLD_COUNT_ZONE0],
584
580
BWMON_THRESHOLD_COUNT_ZONE0_DEFAULT);
···
805
807
static const struct icc_bwmon_data msm8998_bwmon_data = {
806
808
.sample_ms = 4,
807
809
.count_unit_kb = 1024,
808
-
.default_highbw_kbps = 4800 * 1024, /* 4.8 GBps */
809
-
.default_medbw_kbps = 512 * 1024, /* 512 MBps */
810
-
.default_lowbw_kbps = 0,
811
810
.zone1_thres_count = 16,
812
811
.zone3_thres_count = 1,
813
812
.quirks = BWMON_HAS_GLOBAL_IRQ,
···
817
822
static const struct icc_bwmon_data sdm845_cpu_bwmon_data = {
818
823
.sample_ms = 4,
819
824
.count_unit_kb = 64,
820
-
.default_highbw_kbps = 4800 * 1024, /* 4.8 GBps */
821
-
.default_medbw_kbps = 512 * 1024, /* 512 MBps */
822
-
.default_lowbw_kbps = 0,
823
825
.zone1_thres_count = 16,
824
826
.zone3_thres_count = 1,
825
827
.quirks = BWMON_HAS_GLOBAL_IRQ,
···
827
835
static const struct icc_bwmon_data sdm845_llcc_bwmon_data = {
828
836
.sample_ms = 4,
829
837
.count_unit_kb = 1024,
830
-
.default_highbw_kbps = 800 * 1024, /* 800 MBps */
831
-
.default_medbw_kbps = 256 * 1024, /* 256 MBps */
832
-
.default_lowbw_kbps = 0,
833
838
.zone1_thres_count = 16,
834
839
.zone3_thres_count = 1,
835
840
.regmap_fields = sdm845_llcc_bwmon_reg_fields,
···
836
847
static const struct icc_bwmon_data sc7280_llcc_bwmon_data = {
837
848
.sample_ms = 4,
838
849
.count_unit_kb = 64,
839
-
.default_highbw_kbps = 800 * 1024, /* 800 MBps */
840
-
.default_medbw_kbps = 256 * 1024, /* 256 MBps */
841
-
.default_lowbw_kbps = 0,
842
850
.zone1_thres_count = 16,
843
851
.zone3_thres_count = 1,
844
852
.quirks = BWMON_NEEDS_FORCE_CLEAR,
+2
drivers/soc/qcom/ice.c
+2
drivers/soc/qcom/ice.c
-1
drivers/soc/qcom/llcc-qcom.c
-1
drivers/soc/qcom/llcc-qcom.c
+38
-30
drivers/soc/qcom/ocmem.c
+38
-30
drivers/soc/qcom/ocmem.c
···
14
14
#include <linux/io.h>
15
15
#include <linux/kernel.h>
16
16
#include <linux/module.h>
17
-
#include <linux/of_device.h>
17
+
#include <linux/of.h>
18
+
#include <linux/of_platform.h>
18
19
#include <linux/platform_device.h>
19
20
#include <linux/firmware/qcom/qcom_scm.h>
20
21
#include <linux/sizes.h>
···
55
54
const struct ocmem_config *config;
56
55
struct resource *memory;
57
56
void __iomem *mmio;
57
+
struct clk *core_clk;
58
+
struct clk *iface_clk;
58
59
unsigned int num_ports;
59
60
unsigned int num_macros;
60
61
bool interleaved;
···
83
80
#define OCMEM_HW_VERSION_MINOR(val) FIELD_GET(GENMASK(27, 16), val)
84
81
#define OCMEM_HW_VERSION_STEP(val) FIELD_GET(GENMASK(15, 0), val)
85
82
86
-
#define OCMEM_HW_PROFILE_NUM_PORTS(val) FIELD_PREP(0x0000000f, (val))
87
-
#define OCMEM_HW_PROFILE_NUM_MACROS(val) FIELD_PREP(0x00003f00, (val))
83
+
#define OCMEM_HW_PROFILE_NUM_PORTS(val) FIELD_GET(0x0000000f, (val))
84
+
#define OCMEM_HW_PROFILE_NUM_MACROS(val) FIELD_GET(0x00003f00, (val))
88
85
89
86
#define OCMEM_HW_PROFILE_LAST_REGN_HALFSIZE 0x00010000
90
87
#define OCMEM_HW_PROFILE_INTERLEAVING 0x00020000
···
97
94
#define OCMEM_PSGSC_CTL_MACRO1_MODE(val) FIELD_PREP(0x00000070, (val))
98
95
#define OCMEM_PSGSC_CTL_MACRO2_MODE(val) FIELD_PREP(0x00000700, (val))
99
96
#define OCMEM_PSGSC_CTL_MACRO3_MODE(val) FIELD_PREP(0x00007000, (val))
100
-
101
-
#define OCMEM_CLK_CORE_IDX 0
102
-
static struct clk_bulk_data ocmem_clks[] = {
103
-
{
104
-
.id = "core",
105
-
},
106
-
{
107
-
.id = "iface",
108
-
},
109
-
};
110
97
111
98
static inline void ocmem_write(struct ocmem *ocmem, u32 reg, u32 data)
112
99
{
···
313
320
ocmem->dev = dev;
314
321
ocmem->config = device_get_match_data(dev);
315
322
316
-
ret = devm_clk_bulk_get(dev, ARRAY_SIZE(ocmem_clks), ocmem_clks);
317
-
if (ret) {
318
-
if (ret != -EPROBE_DEFER)
319
-
dev_err(dev, "Unable to get clocks\n");
323
+
ocmem->core_clk = devm_clk_get(dev, "core");
324
+
if (IS_ERR(ocmem->core_clk))
325
+
return dev_err_probe(dev, PTR_ERR(ocmem->core_clk),
326
+
"Unable to get core clock\n");
320
327
321
-
return ret;
322
-
}
328
+
ocmem->iface_clk = devm_clk_get_optional(dev, "iface");
329
+
if (IS_ERR(ocmem->iface_clk))
330
+
return dev_err_probe(dev, PTR_ERR(ocmem->iface_clk),
331
+
"Unable to get iface clock\n");
323
332
324
333
ocmem->mmio = devm_platform_ioremap_resource_byname(pdev, "ctrl");
325
-
if (IS_ERR(ocmem->mmio)) {
326
-
dev_err(&pdev->dev, "Failed to ioremap ocmem_ctrl resource\n");
327
-
return PTR_ERR(ocmem->mmio);
328
-
}
334
+
if (IS_ERR(ocmem->mmio))
335
+
return dev_err_probe(&pdev->dev, PTR_ERR(ocmem->mmio),
336
+
"Failed to ioremap ocmem_ctrl resource\n");
329
337
330
338
ocmem->memory = platform_get_resource_byname(pdev, IORESOURCE_MEM,
331
339
"mem");
···
336
342
}
337
343
338
344
/* The core clock is synchronous with graphics */
339
-
WARN_ON(clk_set_rate(ocmem_clks[OCMEM_CLK_CORE_IDX].clk, 1000) < 0);
345
+
WARN_ON(clk_set_rate(ocmem->core_clk, 1000) < 0);
340
346
341
-
ret = clk_bulk_prepare_enable(ARRAY_SIZE(ocmem_clks), ocmem_clks);
347
+
ret = clk_prepare_enable(ocmem->core_clk);
348
+
if (ret)
349
+
return dev_err_probe(ocmem->dev, ret, "Failed to enable core clock\n");
350
+
351
+
ret = clk_prepare_enable(ocmem->iface_clk);
342
352
if (ret) {
343
-
dev_info(ocmem->dev, "Failed to enable clocks\n");
344
-
return ret;
353
+
clk_disable_unprepare(ocmem->core_clk);
354
+
return dev_err_probe(ocmem->dev, ret, "Failed to enable iface clock\n");
345
355
}
346
356
347
357
if (qcom_scm_restore_sec_cfg_available()) {
348
358
dev_dbg(dev, "configuring scm\n");
349
359
ret = qcom_scm_restore_sec_cfg(QCOM_SCM_OCMEM_DEV_ID, 0);
350
360
if (ret) {
351
-
dev_err(dev, "Could not enable secure configuration\n");
361
+
dev_err_probe(dev, ret, "Could not enable secure configuration\n");
352
362
goto err_clk_disable;
353
363
}
354
364
}
···
411
413
return 0;
412
414
413
415
err_clk_disable:
414
-
clk_bulk_disable_unprepare(ARRAY_SIZE(ocmem_clks), ocmem_clks);
416
+
clk_disable_unprepare(ocmem->core_clk);
417
+
clk_disable_unprepare(ocmem->iface_clk);
415
418
return ret;
416
419
}
417
420
418
421
static int ocmem_dev_remove(struct platform_device *pdev)
419
422
{
420
-
clk_bulk_disable_unprepare(ARRAY_SIZE(ocmem_clks), ocmem_clks);
423
+
struct ocmem *ocmem = platform_get_drvdata(pdev);
424
+
425
+
clk_disable_unprepare(ocmem->core_clk);
426
+
clk_disable_unprepare(ocmem->iface_clk);
421
427
422
428
return 0;
423
429
}
430
+
431
+
static const struct ocmem_config ocmem_8226_config = {
432
+
.num_regions = 1,
433
+
.macro_size = SZ_128K,
434
+
};
424
435
425
436
static const struct ocmem_config ocmem_8974_config = {
426
437
.num_regions = 3,
···
437
430
};
438
431
439
432
static const struct of_device_id ocmem_of_match[] = {
433
+
{ .compatible = "qcom,msm8226-ocmem", .data = &ocmem_8226_config },
440
434
{ .compatible = "qcom,msm8974-ocmem", .data = &ocmem_8974_config },
441
435
{ }
442
436
};
+2
-6
drivers/soc/qcom/pmic_glink.c
+2
-6
drivers/soc/qcom/pmic_glink.c
···
4
4
* Copyright (c) 2022, Linaro Ltd
5
5
*/
6
6
#include <linux/auxiliary_bus.h>
7
-
#include <linux/of_device.h>
8
7
#include <linux/module.h>
8
+
#include <linux/of.h>
9
9
#include <linux/platform_device.h>
10
10
#include <linux/rpmsg.h>
11
11
#include <linux/slab.h>
···
342
342
BIT(PMIC_GLINK_CLIENT_ALTMODE) |
343
343
BIT(PMIC_GLINK_CLIENT_UCSI);
344
344
345
-
/* Do not handle altmode for now on those platforms */
346
-
static const unsigned long pmic_glink_sm8550_client_mask = BIT(PMIC_GLINK_CLIENT_BATT) |
347
-
BIT(PMIC_GLINK_CLIENT_UCSI);
348
-
349
345
static const struct of_device_id pmic_glink_of_match[] = {
350
346
{ .compatible = "qcom,sm8450-pmic-glink", .data = &pmic_glink_sm8450_client_mask },
351
-
{ .compatible = "qcom,sm8550-pmic-glink", .data = &pmic_glink_sm8550_client_mask },
347
+
{ .compatible = "qcom,sm8550-pmic-glink", .data = &pmic_glink_sm8450_client_mask },
352
348
{ .compatible = "qcom,pmic-glink" },
353
349
{}
354
350
};
+61
-1
drivers/soc/qcom/pmic_glink_altmode.c
+61
-1
drivers/soc/qcom/pmic_glink_altmode.c
···
6
6
#include <linux/auxiliary_bus.h>
7
7
#include <linux/bitfield.h>
8
8
#include <linux/module.h>
9
+
#include <linux/of.h>
9
10
#include <linux/of_device.h>
10
11
#include <linux/mutex.h>
11
12
#include <linux/property.h>
···
16
15
#include <linux/usb/typec_altmode.h>
17
16
#include <linux/usb/typec_dp.h>
18
17
#include <linux/usb/typec_mux.h>
18
+
#include <linux/usb/typec_retimer.h>
19
19
20
20
#include <linux/soc/qcom/pmic_glink.h>
21
21
···
70
68
struct typec_switch *typec_switch;
71
69
struct typec_mux *typec_mux;
72
70
struct typec_mux_state state;
71
+
struct typec_retimer *typec_retimer;
72
+
struct typec_retimer_state retimer_state;
73
73
struct typec_altmode dp_alt;
74
74
75
75
struct work_struct work;
···
161
157
ret = typec_mux_set(port->typec_mux, &port->state);
162
158
if (ret)
163
159
dev_err(altmode->dev, "failed to switch mux to DP\n");
160
+
161
+
port->retimer_state.alt = &port->dp_alt;
162
+
port->retimer_state.data = &dp_data;
163
+
port->retimer_state.mode = TYPEC_MODAL_STATE(mode);
164
+
165
+
ret = typec_retimer_set(port->typec_retimer, &port->retimer_state);
166
+
if (ret)
167
+
dev_err(altmode->dev, "failed to setup retimer to DP\n");
164
168
}
165
169
166
170
static void pmic_glink_altmode_enable_usb(struct pmic_glink_altmode *altmode,
···
183
171
ret = typec_mux_set(port->typec_mux, &port->state);
184
172
if (ret)
185
173
dev_err(altmode->dev, "failed to switch mux to USB\n");
174
+
175
+
port->retimer_state.alt = NULL;
176
+
port->retimer_state.data = NULL;
177
+
port->retimer_state.mode = TYPEC_STATE_USB;
178
+
179
+
ret = typec_retimer_set(port->typec_retimer, &port->retimer_state);
180
+
if (ret)
181
+
dev_err(altmode->dev, "failed to setup retimer to USB\n");
182
+
}
183
+
184
+
static void pmic_glink_altmode_safe(struct pmic_glink_altmode *altmode,
185
+
struct pmic_glink_altmode_port *port)
186
+
{
187
+
int ret;
188
+
189
+
port->state.alt = NULL;
190
+
port->state.data = NULL;
191
+
port->state.mode = TYPEC_STATE_SAFE;
192
+
193
+
ret = typec_mux_set(port->typec_mux, &port->state);
194
+
if (ret)
195
+
dev_err(altmode->dev, "failed to switch mux to safe mode\n");
196
+
197
+
port->retimer_state.alt = NULL;
198
+
port->retimer_state.data = NULL;
199
+
port->retimer_state.mode = TYPEC_STATE_SAFE;
200
+
201
+
ret = typec_retimer_set(port->typec_retimer, &port->retimer_state);
202
+
if (ret)
203
+
dev_err(altmode->dev, "failed to setup retimer to USB\n");
186
204
}
187
205
188
206
static void pmic_glink_altmode_worker(struct work_struct *work)
···
222
180
223
181
typec_switch_set(alt_port->typec_switch, alt_port->orientation);
224
182
225
-
if (alt_port->svid == USB_TYPEC_DP_SID)
183
+
if (alt_port->svid == USB_TYPEC_DP_SID && alt_port->mode == 0xff)
184
+
pmic_glink_altmode_safe(altmode, alt_port);
185
+
else if (alt_port->svid == USB_TYPEC_DP_SID)
226
186
pmic_glink_altmode_enable_dp(altmode, alt_port, alt_port->mode,
227
187
alt_port->hpd_state, alt_port->hpd_irq);
228
188
else
···
375
331
.attach = pmic_glink_altmode_attach,
376
332
};
377
333
334
+
static void pmic_glink_altmode_put_retimer(void *data)
335
+
{
336
+
typec_retimer_put(data);
337
+
}
338
+
378
339
static void pmic_glink_altmode_put_mux(void *data)
379
340
{
380
341
typec_mux_put(data);
···
483
434
484
435
ret = devm_add_action_or_reset(dev, pmic_glink_altmode_put_mux,
485
436
alt_port->typec_mux);
437
+
if (ret)
438
+
return ret;
439
+
440
+
alt_port->typec_retimer = fwnode_typec_retimer_get(fwnode);
441
+
if (IS_ERR(alt_port->typec_retimer))
442
+
return dev_err_probe(dev, PTR_ERR(alt_port->typec_retimer),
443
+
"failed to acquire retimer-switch for port: %d\n",
444
+
port);
445
+
446
+
ret = devm_add_action_or_reset(dev, pmic_glink_altmode_put_retimer,
447
+
alt_port->typec_retimer);
486
448
if (ret)
487
449
return ret;
488
450
+24
-25
drivers/soc/qcom/qcom_aoss.c
+24
-25
drivers/soc/qcom/qcom_aoss.c
···
205
205
/**
206
206
* qmp_send() - send a message to the AOSS
207
207
* @qmp: qmp context
208
-
* @data: message to be sent
209
-
* @len: length of the message
208
+
* @fmt: format string for message to be sent
209
+
* @...: arguments for the format string
210
210
*
211
-
* Transmit @data to AOSS and wait for the AOSS to acknowledge the message.
212
-
* @len must be a multiple of 4 and not longer than the mailbox size. Access is
213
-
* synchronized by this implementation.
211
+
* Transmit message to AOSS and wait for the AOSS to acknowledge the message.
212
+
* data must not be longer than the mailbox size. Access is synchronized by
213
+
* this implementation.
214
214
*
215
215
* Return: 0 on success, negative errno on failure
216
216
*/
217
-
int qmp_send(struct qmp *qmp, const void *data, size_t len)
217
+
int qmp_send(struct qmp *qmp, const char *fmt, ...)
218
218
{
219
+
char buf[QMP_MSG_LEN];
219
220
long time_left;
221
+
va_list args;
222
+
int len;
220
223
int ret;
221
224
222
-
if (WARN_ON(IS_ERR_OR_NULL(qmp) || !data))
225
+
if (WARN_ON(IS_ERR_OR_NULL(qmp) || !fmt))
223
226
return -EINVAL;
224
227
225
-
if (WARN_ON(len + sizeof(u32) > qmp->size))
226
-
return -EINVAL;
228
+
memset(buf, 0, sizeof(buf));
229
+
va_start(args, fmt);
230
+
len = vsnprintf(buf, sizeof(buf), fmt, args);
231
+
va_end(args);
227
232
228
-
if (WARN_ON(len % sizeof(u32)))
233
+
if (WARN_ON(len >= sizeof(buf)))
229
234
return -EINVAL;
230
235
231
236
mutex_lock(&qmp->tx_lock);
232
237
233
238
/* The message RAM only implements 32-bit accesses */
234
239
__iowrite32_copy(qmp->msgram + qmp->offset + sizeof(u32),
235
-
data, len / sizeof(u32));
236
-
writel(len, qmp->msgram + qmp->offset);
240
+
buf, sizeof(buf) / sizeof(u32));
241
+
writel(sizeof(buf), qmp->msgram + qmp->offset);
237
242
238
-
/* Read back len to confirm data written in message RAM */
243
+
/* Read back length to confirm data written in message RAM */
239
244
readl(qmp->msgram + qmp->offset);
240
245
qmp_kick(qmp);
241
246
···
264
259
265
260
static int qmp_qdss_clk_prepare(struct clk_hw *hw)
266
261
{
267
-
static const char buf[QMP_MSG_LEN] = "{class: clock, res: qdss, val: 1}";
262
+
static const char *buf = "{class: clock, res: qdss, val: 1}";
268
263
struct qmp *qmp = container_of(hw, struct qmp, qdss_clk);
269
264
270
-
return qmp_send(qmp, buf, sizeof(buf));
265
+
return qmp_send(qmp, buf);
271
266
}
272
267
273
268
static void qmp_qdss_clk_unprepare(struct clk_hw *hw)
274
269
{
275
-
static const char buf[QMP_MSG_LEN] = "{class: clock, res: qdss, val: 0}";
270
+
static const char *buf = "{class: clock, res: qdss, val: 0}";
276
271
struct qmp *qmp = container_of(hw, struct qmp, qdss_clk);
277
272
278
-
qmp_send(qmp, buf, sizeof(buf));
273
+
qmp_send(qmp, buf);
279
274
}
280
275
281
276
static const struct clk_ops qmp_qdss_clk_ops = {
···
334
329
unsigned long state)
335
330
{
336
331
struct qmp_cooling_device *qmp_cdev = cdev->devdata;
337
-
char buf[QMP_MSG_LEN] = {};
338
332
bool cdev_state;
339
333
int ret;
340
334
···
343
339
if (qmp_cdev->state == state)
344
340
return 0;
345
341
346
-
snprintf(buf, sizeof(buf),
347
-
"{class: volt_flr, event:zero_temp, res:%s, value:%s}",
348
-
qmp_cdev->name,
349
-
cdev_state ? "on" : "off");
350
-
351
-
ret = qmp_send(qmp_cdev->qmp, buf, sizeof(buf));
352
-
342
+
ret = qmp_send(qmp_cdev->qmp, "{class: volt_flr, event:zero_temp, res:%s, value:%s}",
343
+
qmp_cdev->name, cdev_state ? "on" : "off");
353
344
if (!ret)
354
345
qmp_cdev->state = cdev_state;
355
346
+3
-8
drivers/soc/qcom/qcom_gsbi.c
+3
-8
drivers/soc/qcom/qcom_gsbi.c
···
129
129
const struct of_device_id *match;
130
130
void __iomem *base;
131
131
struct gsbi_info *gsbi;
132
-
int i, ret;
132
+
int i;
133
133
u32 mask, gsbi_num;
134
134
const struct crci_config *config = NULL;
135
135
···
178
178
179
179
dev_info(&pdev->dev, "GSBI port protocol: %d crci: %d\n",
180
180
gsbi->mode, gsbi->crci);
181
-
gsbi->hclk = devm_clk_get(&pdev->dev, "iface");
181
+
gsbi->hclk = devm_clk_get_enabled(&pdev->dev, "iface");
182
182
if (IS_ERR(gsbi->hclk))
183
183
return PTR_ERR(gsbi->hclk);
184
-
185
-
clk_prepare_enable(gsbi->hclk);
186
184
187
185
writel_relaxed((gsbi->mode << GSBI_PROTOCOL_SHIFT) | gsbi->crci,
188
186
base + GSBI_CTRL_REG);
···
209
211
210
212
platform_set_drvdata(pdev, gsbi);
211
213
212
-
ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
213
-
if (ret)
214
-
clk_disable_unprepare(gsbi->hclk);
215
-
return ret;
214
+
return of_platform_populate(node, NULL, NULL, &pdev->dev);
216
215
}
217
216
218
217
static int gsbi_remove(struct platform_device *pdev)
+2
-2
drivers/soc/qcom/qmi_encdec.c
+2
-2
drivers/soc/qcom/qmi_encdec.c
···
534
534
decoded_bytes += rc;
535
535
}
536
536
537
-
if (string_len > temp_ei->elem_len) {
538
-
pr_err("%s: String len %d > Max Len %d\n",
537
+
if (string_len >= temp_ei->elem_len) {
538
+
pr_err("%s: String len %d >= Max Len %d\n",
539
539
__func__, string_len, temp_ei->elem_len);
540
540
return -ETOOSMALL;
541
541
} else if (string_len > tlv_len) {
+77
drivers/soc/qcom/rpm-proc.c
+77
drivers/soc/qcom/rpm-proc.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/* Copyright (c) 2021-2023, Stephan Gerhold <stephan@gerhold.net> */
3
+
4
+
#include <linux/module.h>
5
+
#include <linux/of.h>
6
+
#include <linux/of_platform.h>
7
+
#include <linux/platform_device.h>
8
+
#include <linux/rpmsg/qcom_smd.h>
9
+
10
+
static int rpm_proc_probe(struct platform_device *pdev)
11
+
{
12
+
struct qcom_smd_edge *edge = NULL;
13
+
struct device *dev = &pdev->dev;
14
+
struct device_node *edge_node;
15
+
int ret;
16
+
17
+
edge_node = of_get_child_by_name(dev->of_node, "smd-edge");
18
+
if (edge_node) {
19
+
edge = qcom_smd_register_edge(dev, edge_node);
20
+
of_node_put(edge_node);
21
+
if (IS_ERR(edge))
22
+
return dev_err_probe(dev, PTR_ERR(edge),
23
+
"Failed to register smd-edge\n");
24
+
}
25
+
26
+
ret = devm_of_platform_populate(dev);
27
+
if (ret) {
28
+
dev_err(dev, "Failed to populate child devices: %d\n", ret);
29
+
goto err;
30
+
}
31
+
32
+
platform_set_drvdata(pdev, edge);
33
+
return 0;
34
+
err:
35
+
if (edge)
36
+
qcom_smd_unregister_edge(edge);
37
+
return ret;
38
+
}
39
+
40
+
static void rpm_proc_remove(struct platform_device *pdev)
41
+
{
42
+
struct qcom_smd_edge *edge = platform_get_drvdata(pdev);
43
+
44
+
if (edge)
45
+
qcom_smd_unregister_edge(edge);
46
+
}
47
+
48
+
static const struct of_device_id rpm_proc_of_match[] = {
49
+
{ .compatible = "qcom,rpm-proc", },
50
+
{ /* sentinel */ }
51
+
};
52
+
MODULE_DEVICE_TABLE(of, rpm_proc_of_match);
53
+
54
+
static struct platform_driver rpm_proc_driver = {
55
+
.probe = rpm_proc_probe,
56
+
.remove_new = rpm_proc_remove,
57
+
.driver = {
58
+
.name = "qcom-rpm-proc",
59
+
.of_match_table = rpm_proc_of_match,
60
+
},
61
+
};
62
+
63
+
static int __init rpm_proc_init(void)
64
+
{
65
+
return platform_driver_register(&rpm_proc_driver);
66
+
}
67
+
arch_initcall(rpm_proc_init);
68
+
69
+
static void __exit rpm_proc_exit(void)
70
+
{
71
+
platform_driver_unregister(&rpm_proc_driver);
72
+
}
73
+
module_exit(rpm_proc_exit);
74
+
75
+
MODULE_DESCRIPTION("Qualcomm RPM processor/subsystem driver");
76
+
MODULE_AUTHOR("Stephan Gerhold <stephan@gerhold.net>");
77
+
MODULE_LICENSE("GPL");
+1
-1
drivers/soc/qcom/rpmh-rsc.c
+1
-1
drivers/soc/qcom/rpmh-rsc.c
···
516
516
write_tcs_cmd(drv, drv->regs[RSC_DRV_CMD_MSGID], tcs_id, j, msgid);
517
517
write_tcs_cmd(drv, drv->regs[RSC_DRV_CMD_ADDR], tcs_id, j, cmd->addr);
518
518
write_tcs_cmd(drv, drv->regs[RSC_DRV_CMD_DATA], tcs_id, j, cmd->data);
519
-
trace_rpmh_send_msg(drv, tcs_id, j, msgid, cmd);
519
+
trace_rpmh_send_msg(drv, tcs_id, msg->state, j, msgid, cmd);
520
520
}
521
521
522
522
cmd_enable |= read_tcs_reg(drv, drv->regs[RSC_DRV_CMD_ENABLE], tcs_id);
+9
-26
drivers/soc/qcom/smd-rpm.c
+9
-26
drivers/soc/qcom/smd-rpm.c
···
199
199
struct qcom_smd_rpm *rpm;
200
200
int ret;
201
201
202
+
if (!rpdev->dev.of_node)
203
+
return -EINVAL;
204
+
202
205
rpm = devm_kzalloc(&rpdev->dev, sizeof(*rpm), GFP_KERNEL);
203
206
if (!rpm)
204
207
return -ENOMEM;
···
233
230
of_platform_depopulate(&rpdev->dev);
234
231
}
235
232
236
-
static const struct of_device_id qcom_smd_rpm_of_match[] = {
237
-
{ .compatible = "qcom,rpm-apq8084" },
238
-
{ .compatible = "qcom,rpm-ipq6018" },
239
-
{ .compatible = "qcom,rpm-ipq9574" },
240
-
{ .compatible = "qcom,rpm-msm8226" },
241
-
{ .compatible = "qcom,rpm-msm8909" },
242
-
{ .compatible = "qcom,rpm-msm8916" },
243
-
{ .compatible = "qcom,rpm-msm8936" },
244
-
{ .compatible = "qcom,rpm-msm8953" },
245
-
{ .compatible = "qcom,rpm-msm8974" },
246
-
{ .compatible = "qcom,rpm-msm8976" },
247
-
{ .compatible = "qcom,rpm-msm8994" },
248
-
{ .compatible = "qcom,rpm-msm8996" },
249
-
{ .compatible = "qcom,rpm-msm8998" },
250
-
{ .compatible = "qcom,rpm-sdm660" },
251
-
{ .compatible = "qcom,rpm-sm6115" },
252
-
{ .compatible = "qcom,rpm-sm6125" },
253
-
{ .compatible = "qcom,rpm-sm6375" },
254
-
{ .compatible = "qcom,rpm-qcm2290" },
255
-
{ .compatible = "qcom,rpm-qcs404" },
256
-
{}
233
+
static const struct rpmsg_device_id qcom_smd_rpm_id_table[] = {
234
+
{ .name = "rpm_requests", },
235
+
{ /* sentinel */ }
257
236
};
258
-
MODULE_DEVICE_TABLE(of, qcom_smd_rpm_of_match);
237
+
MODULE_DEVICE_TABLE(rpmsg, qcom_smd_rpm_id_table);
259
238
260
239
static struct rpmsg_driver qcom_smd_rpm_driver = {
261
240
.probe = qcom_smd_rpm_probe,
262
241
.remove = qcom_smd_rpm_remove,
263
242
.callback = qcom_smd_rpm_callback,
264
-
.drv = {
265
-
.name = "qcom_smd_rpm",
266
-
.of_match_table = qcom_smd_rpm_of_match,
267
-
},
243
+
.id_table = qcom_smd_rpm_id_table,
244
+
.drv.name = "qcom_smd_rpm",
268
245
};
269
246
270
247
static int __init qcom_smd_rpm_init(void)
+14
-4
drivers/soc/qcom/smem.c
+14
-4
drivers/soc/qcom/smem.c
···
359
359
/* Timeout (ms) for the trylock of remote spinlocks */
360
360
#define HWSPINLOCK_TIMEOUT 1000
361
361
362
+
/**
363
+
* qcom_smem_is_available() - Check if SMEM is available
364
+
*
365
+
* Return: true if SMEM is available, false otherwise.
366
+
*/
367
+
bool qcom_smem_is_available(void)
368
+
{
369
+
return !!__smem;
370
+
}
371
+
EXPORT_SYMBOL(qcom_smem_is_available);
372
+
362
373
static int qcom_smem_alloc_private(struct qcom_smem *smem,
363
374
struct smem_partition *part,
364
375
unsigned item,
···
735
724
736
725
static bool addr_in_range(void __iomem *base, size_t size, void *addr)
737
726
{
738
-
return base && (addr >= base && addr < base + size);
727
+
return base && ((void __iomem *)addr >= base && (void __iomem *)addr < base + size);
739
728
}
740
729
741
730
/**
···
1070
1059
struct reserved_mem *rmem;
1071
1060
struct qcom_smem *smem;
1072
1061
unsigned long flags;
1073
-
size_t array_size;
1074
1062
int num_regions;
1075
1063
int hwlock_id;
1076
1064
u32 version;
···
1081
1071
if (of_property_present(pdev->dev.of_node, "qcom,rpm-msg-ram"))
1082
1072
num_regions++;
1083
1073
1084
-
array_size = num_regions * sizeof(struct smem_region);
1085
-
smem = devm_kzalloc(&pdev->dev, sizeof(*smem) + array_size, GFP_KERNEL);
1074
+
smem = devm_kzalloc(&pdev->dev, struct_size(smem, regions, num_regions),
1075
+
GFP_KERNEL);
1086
1076
if (!smem)
1087
1077
return -ENOMEM;
1088
1078
+2
-1
drivers/soc/qcom/socinfo.c
+2
-1
drivers/soc/qcom/socinfo.c
···
371
371
{ qcom_board_id(SDA429W) },
372
372
{ qcom_board_id(SM8350) },
373
373
{ qcom_board_id(QCM2290) },
374
+
{ qcom_board_id(SM7125) },
374
375
{ qcom_board_id(SM6115) },
375
376
{ qcom_board_id(IPQ5010) },
376
377
{ qcom_board_id(IPQ5018) },
···
406
405
{ qcom_board_id(SA8775P) },
407
406
{ qcom_board_id(QRU1000) },
408
407
{ qcom_board_id(QDU1000) },
408
+
{ qcom_board_id(SM4450) },
409
409
{ qcom_board_id(QDU1010) },
410
-
{ qcom_board_id(IPQ5019) },
411
410
{ qcom_board_id(QRU1032) },
412
411
{ qcom_board_id(QRU1052) },
413
412
{ qcom_board_id(QRU1062) },
+1
-5
drivers/soc/qcom/spm.c
+1
-5
drivers/soc/qcom/spm.c
···
12
12
#include <linux/module.h>
13
13
#include <linux/slab.h>
14
14
#include <linux/of.h>
15
-
#include <linux/of_address.h>
16
-
#include <linux/of_device.h>
17
15
#include <linux/err.h>
18
16
#include <linux/platform_device.h>
19
17
#include <soc/qcom/spm.h>
···
273
275
{
274
276
const struct of_device_id *match_id;
275
277
struct spm_driver_data *drv;
276
-
struct resource *res;
277
278
void __iomem *addr;
278
279
279
280
drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL);
280
281
if (!drv)
281
282
return -ENOMEM;
282
283
283
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
284
-
drv->reg_base = devm_ioremap_resource(&pdev->dev, res);
284
+
drv->reg_base = devm_platform_ioremap_resource(pdev, 0);
285
285
if (IS_ERR(drv->reg_base))
286
286
return PTR_ERR(drv->reg_base);
287
287
+12
-4
drivers/soc/qcom/trace-rpmh.h
+12
-4
drivers/soc/qcom/trace-rpmh.h
···
38
38
39
39
TRACE_EVENT(rpmh_send_msg,
40
40
41
-
TP_PROTO(struct rsc_drv *d, int m, int n, u32 h,
41
+
TP_PROTO(struct rsc_drv *d, int m, enum rpmh_state state, int n, u32 h,
42
42
const struct tcs_cmd *c),
43
43
44
-
TP_ARGS(d, m, n, h, c),
44
+
TP_ARGS(d, m, state, n, h, c),
45
45
46
46
TP_STRUCT__entry(
47
47
__string(name, d->name)
48
48
__field(int, m)
49
+
__field(u32, state)
49
50
__field(int, n)
50
51
__field(u32, hdr)
51
52
__field(u32, addr)
···
57
56
TP_fast_assign(
58
57
__assign_str(name, d->name);
59
58
__entry->m = m;
59
+
__entry->state = state;
60
60
__entry->n = n;
61
61
__entry->hdr = h;
62
62
__entry->addr = c->addr;
···
65
63
__entry->wait = c->wait;
66
64
),
67
65
68
-
TP_printk("%s: send-msg: tcs(m): %d cmd(n): %d msgid: %#x addr: %#x data: %#x complete: %d",
69
-
__get_str(name), __entry->m, __entry->n, __entry->hdr,
66
+
TP_printk("%s: tcs(m): %d [%s] cmd(n): %d msgid: %#x addr: %#x data: %#x complete: %d",
67
+
__get_str(name), __entry->m,
68
+
__print_symbolic(__entry->state,
69
+
{ RPMH_SLEEP_STATE, "sleep" },
70
+
{ RPMH_WAKE_ONLY_STATE, "wake" },
71
+
{ RPMH_ACTIVE_ONLY_STATE, "active" }),
72
+
__entry->n,
73
+
__entry->hdr,
70
74
__entry->addr, __entry->data, __entry->wait)
71
75
);
72
76
+1
drivers/soc/qcom/wcnss_ctrl.c
+1
drivers/soc/qcom/wcnss_ctrl.c
+14
drivers/soc/rockchip/grf.c
+14
drivers/soc/rockchip/grf.c
···
121
121
.num_values = ARRAY_SIZE(rk3566_defaults),
122
122
};
123
123
124
+
#define RK3588_GRF_SOC_CON6 0x0318
125
+
126
+
static const struct rockchip_grf_value rk3588_defaults[] __initconst = {
127
+
{ "jtag switching", RK3588_GRF_SOC_CON6, HIWORD_UPDATE(0, 1, 14) },
128
+
};
129
+
130
+
static const struct rockchip_grf_info rk3588_sysgrf __initconst = {
131
+
.values = rk3588_defaults,
132
+
.num_values = ARRAY_SIZE(rk3588_defaults),
133
+
};
134
+
124
135
125
136
static const struct of_device_id rockchip_grf_dt_match[] __initconst = {
126
137
{
···
158
147
}, {
159
148
.compatible = "rockchip,rk3566-pipe-grf",
160
149
.data = (void *)&rk3566_pipegrf,
150
+
}, {
151
+
.compatible = "rockchip,rk3588-sys-grf",
152
+
.data = (void *)&rk3588_sysgrf,
161
153
},
162
154
{ /* sentinel */ },
163
155
};
-1
drivers/soc/samsung/exynos-chipid.c
-1
drivers/soc/samsung/exynos-chipid.c
+1
-1
drivers/soc/samsung/exynos-pmu.c
+1
-1
drivers/soc/samsung/exynos-pmu.c
+1
-1
drivers/soc/sunxi/sunxi_sram.c
+1
-1
drivers/soc/sunxi/sunxi_sram.c
+2
-10
drivers/soc/tegra/cbb/tegra-cbb.c
+2
-10
drivers/soc/tegra/cbb/tegra-cbb.c
···
7
7
#include <linux/cpufeature.h>
8
8
#include <linux/debugfs.h>
9
9
#include <linux/module.h>
10
-
#include <linux/of.h>
11
-
#include <linux/of_device.h>
12
10
#include <linux/platform_device.h>
13
11
#include <linux/device.h>
14
12
#include <linux/io.h>
15
-
#include <linux/of_irq.h>
16
-
#include <linux/of_address.h>
17
13
#include <linux/interrupt.h>
18
14
#include <linux/ioport.h>
19
15
#include <soc/tegra/fuse.h>
···
122
126
123
127
if (num_intr == 2) {
124
128
irq = platform_get_irq(pdev, index);
125
-
if (irq <= 0) {
126
-
dev_err(&pdev->dev, "failed to get non-secure IRQ: %d\n", irq);
129
+
if (irq <= 0)
127
130
return -ENOENT;
128
-
}
129
131
130
132
*nonsec_irq = irq;
131
133
index++;
132
134
}
133
135
134
136
irq = platform_get_irq(pdev, index);
135
-
if (irq <= 0) {
136
-
dev_err(&pdev->dev, "failed to get secure IRQ: %d\n", irq);
137
+
if (irq <= 0)
137
138
return -ENOENT;
138
-
}
139
139
140
140
*sec_irq = irq;
141
141
+1
-3
drivers/soc/tegra/cbb/tegra194-cbb.c
+1
-3
drivers/soc/tegra/cbb/tegra194-cbb.c
···
15
15
#include <linux/debugfs.h>
16
16
#include <linux/module.h>
17
17
#include <linux/of.h>
18
-
#include <linux/of_device.h>
18
+
#include <linux/of_address.h>
19
19
#include <linux/platform_device.h>
20
20
#include <linux/device.h>
21
21
#include <linux/io.h>
22
-
#include <linux/of_irq.h>
23
-
#include <linux/of_address.h>
24
22
#include <linux/interrupt.h>
25
23
#include <linux/ioport.h>
26
24
#include <soc/tegra/fuse.h>
-3
drivers/soc/tegra/cbb/tegra234-cbb.c
-3
drivers/soc/tegra/cbb/tegra234-cbb.c
···
16
16
#include <linux/debugfs.h>
17
17
#include <linux/module.h>
18
18
#include <linux/of.h>
19
-
#include <linux/of_device.h>
20
19
#include <linux/platform_device.h>
21
20
#include <linux/device.h>
22
21
#include <linux/io.h>
23
-
#include <linux/of_irq.h>
24
-
#include <linux/of_address.h>
25
22
#include <linux/interrupt.h>
26
23
#include <linux/ioport.h>
27
24
#include <soc/tegra/fuse.h>
+3
-6
drivers/soc/tegra/fuse/fuse-tegra.c
+3
-6
drivers/soc/tegra/fuse/fuse-tegra.c
···
125
125
return err;
126
126
127
127
/* take over the memory region from the early initialization */
128
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
128
+
fuse->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
129
+
if (IS_ERR(fuse->base))
130
+
return PTR_ERR(fuse->base);
129
131
fuse->phys = res->start;
130
-
fuse->base = devm_ioremap_resource(&pdev->dev, res);
131
-
if (IS_ERR(fuse->base)) {
132
-
err = PTR_ERR(fuse->base);
133
-
return err;
134
-
}
135
132
136
133
fuse->clk = devm_clk_get(&pdev->dev, "fuse");
137
134
if (IS_ERR(fuse->clk)) {
+1
-1
drivers/soc/tegra/fuse/fuse-tegra20.c
+1
-1
drivers/soc/tegra/fuse/fuse-tegra20.c
-2
drivers/soc/tegra/fuse/fuse-tegra30.c
-2
drivers/soc/tegra/fuse/fuse-tegra30.c
+2
-2
drivers/soc/tegra/fuse/tegra-apbmisc.c
+2
-2
drivers/soc/tegra/fuse/tegra-apbmisc.c
···
4
4
*/
5
5
6
6
#include <linux/export.h>
7
+
#include <linux/io.h>
7
8
#include <linux/kernel.h>
8
9
#include <linux/of.h>
9
10
#include <linux/of_address.h>
10
-
#include <linux/io.h>
11
11
12
-
#include <soc/tegra/fuse.h>
13
12
#include <soc/tegra/common.h>
13
+
#include <soc/tegra/fuse.h>
14
14
15
15
#include "fuse.h"
16
16
+11
-20
drivers/soc/ti/k3-ringacc.c
+11
-20
drivers/soc/ti/k3-ringacc.c
···
9
9
#include <linux/io.h>
10
10
#include <linux/module.h>
11
11
#include <linux/of.h>
12
-
#include <linux/of_device.h>
13
12
#include <linux/platform_device.h>
14
13
#include <linux/sys_soc.h>
15
14
#include <linux/dma/ti-cppi5.h>
···
124
125
* @occ: Occupancy
125
126
* @windex: Write index
126
127
* @rindex: Read index
128
+
* @tdown_complete: Tear down complete state
127
129
*/
128
130
struct k3_ring_state {
129
131
u32 free;
···
192
192
* @num_rings: number of ring in RA
193
193
* @rings_inuse: bitfield for ring usage tracking
194
194
* @rm_gp_range: general purpose rings range from tisci
195
-
* @dma_ring_reset_quirk: DMA reset w/a enable
195
+
* @dma_ring_reset_quirk: DMA reset workaround enable
196
196
* @num_proxies: number of RA proxies
197
197
* @proxy_inuse: bitfield for proxy usage tracking
198
198
* @rings: array of rings descriptors (struct @k3_ring)
···
229
229
};
230
230
231
231
/**
232
-
* struct k3_ringacc - Rings accelerator SoC data
232
+
* struct k3_ringacc_soc_data - Rings accelerator SoC data
233
233
*
234
-
* @dma_ring_reset_quirk: DMA reset w/a enable
234
+
* @dma_ring_reset_quirk: DMA reset workaround enable
235
235
*/
236
236
struct k3_ringacc_soc_data {
237
237
unsigned dma_ring_reset_quirk:1;
···
1368
1368
const struct soc_device_attribute *soc;
1369
1369
void __iomem *base_fifo, *base_rt;
1370
1370
struct device *dev = &pdev->dev;
1371
-
struct resource *res;
1372
1371
int ret, i;
1373
1372
1374
1373
dev->msi.domain = of_msi_get_domain(dev, dev->of_node,
1375
1374
DOMAIN_BUS_TI_SCI_INTA_MSI);
1376
-
if (!dev->msi.domain) {
1377
-
dev_err(dev, "Failed to get MSI domain\n");
1375
+
if (!dev->msi.domain)
1378
1376
return -EPROBE_DEFER;
1379
-
}
1380
1377
1381
1378
ret = k3_ringacc_probe_dt(ringacc);
1382
1379
if (ret)
···
1386
1389
ringacc->dma_ring_reset_quirk = soc_data->dma_ring_reset_quirk;
1387
1390
}
1388
1391
1389
-
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rt");
1390
-
base_rt = devm_ioremap_resource(dev, res);
1392
+
base_rt = devm_platform_ioremap_resource_byname(pdev, "rt");
1391
1393
if (IS_ERR(base_rt))
1392
1394
return PTR_ERR(base_rt);
1393
1395
1394
-
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fifos");
1395
-
base_fifo = devm_ioremap_resource(dev, res);
1396
+
base_fifo = devm_platform_ioremap_resource_byname(pdev, "fifos");
1396
1397
if (IS_ERR(base_fifo))
1397
1398
return PTR_ERR(base_fifo);
1398
1399
1399
-
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "proxy_gcfg");
1400
-
ringacc->proxy_gcfg = devm_ioremap_resource(dev, res);
1400
+
ringacc->proxy_gcfg = devm_platform_ioremap_resource_byname(pdev, "proxy_gcfg");
1401
1401
if (IS_ERR(ringacc->proxy_gcfg))
1402
1402
return PTR_ERR(ringacc->proxy_gcfg);
1403
1403
1404
-
res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1405
-
"proxy_target");
1406
-
ringacc->proxy_target_base = devm_ioremap_resource(dev, res);
1404
+
ringacc->proxy_target_base = devm_platform_ioremap_resource_byname(pdev,
1405
+
"proxy_target");
1407
1406
if (IS_ERR(ringacc->proxy_target_base))
1408
1407
return PTR_ERR(ringacc->proxy_target_base);
1409
1408
···
1466
1473
struct device *dev = &pdev->dev;
1467
1474
struct k3_ringacc *ringacc;
1468
1475
void __iomem *base_rt;
1469
-
struct resource *res;
1470
1476
int i;
1471
1477
1472
1478
ringacc = devm_kzalloc(dev, sizeof(*ringacc), GFP_KERNEL);
···
1480
1488
1481
1489
mutex_init(&ringacc->req_lock);
1482
1490
1483
-
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ringrt");
1484
-
base_rt = devm_ioremap_resource(dev, res);
1491
+
base_rt = devm_platform_ioremap_resource_byname(pdev, "ringrt");
1485
1492
if (IS_ERR(base_rt))
1486
1493
return ERR_CAST(base_rt);
1487
1494
+1
drivers/soc/ti/k3-socinfo.c
+1
drivers/soc/ti/k3-socinfo.c
+3
-1
drivers/soc/ti/pruss.c
+3
-1
drivers/soc/ti/pruss.c
···
14
14
#include <linux/io.h>
15
15
#include <linux/mfd/syscon.h>
16
16
#include <linux/module.h>
17
+
#include <linux/of.h>
17
18
#include <linux/of_address.h>
18
-
#include <linux/of_device.h>
19
+
#include <linux/of_platform.h>
20
+
#include <linux/platform_device.h>
19
21
#include <linux/pm_runtime.h>
20
22
#include <linux/pruss_driver.h>
21
23
#include <linux/regmap.h>
+2
-1
drivers/soc/ti/ti_sci_inta_msi.c
+2
-1
drivers/soc/ti/ti_sci_inta_msi.c
···
9
9
#include <linux/irq.h>
10
10
#include <linux/irqdomain.h>
11
11
#include <linux/msi.h>
12
+
#include <linux/of.h>
12
13
#include <linux/of_address.h>
13
-
#include <linux/of_device.h>
14
14
#include <linux/of_irq.h>
15
+
#include <linux/platform_device.h>
15
16
#include <linux/soc/ti/ti_sci_inta_msi.h>
16
17
#include <linux/soc/ti/ti_sci_protocol.h>
17
18
+2
-4
drivers/soc/xilinx/xlnx_event_manager.c
+2
-4
drivers/soc/xilinx/xlnx_event_manager.c
···
666
666
return ret;
667
667
}
668
668
669
-
static int xlnx_event_manager_remove(struct platform_device *pdev)
669
+
static void xlnx_event_manager_remove(struct platform_device *pdev)
670
670
{
671
671
int i;
672
672
struct registered_event_data *eve_data;
···
691
691
xlnx_event_cleanup_sgi(pdev);
692
692
693
693
event_manager_availability = -EACCES;
694
-
695
-
return ret;
696
694
}
697
695
698
696
static struct platform_driver xlnx_event_manager_driver = {
699
697
.probe = xlnx_event_manager_probe,
700
-
.remove = xlnx_event_manager_remove,
698
+
.remove_new = xlnx_event_manager_remove,
701
699
.driver = {
702
700
.name = "xlnx_event_manager",
703
701
},
+3
-2
drivers/soc/xilinx/zynqmp_power.c
+3
-2
drivers/soc/xilinx/zynqmp_power.c
···
11
11
12
12
#include <linux/mailbox_client.h>
13
13
#include <linux/module.h>
14
+
#include <linux/of.h>
14
15
#include <linux/platform_device.h>
15
16
#include <linux/reboot.h>
16
17
#include <linux/suspend.h>
···
243
242
}
244
243
} else if (of_property_present(pdev->dev.of_node, "interrupts")) {
245
244
irq = platform_get_irq(pdev, 0);
246
-
if (irq <= 0)
247
-
return -ENXIO;
245
+
if (irq < 0)
246
+
return irq;
248
247
249
248
ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
250
249
zynqmp_pm_isr,
+2
-1
include/dt-bindings/arm/qcom,ids.h
+2
-1
include/dt-bindings/arm/qcom,ids.h
···
215
215
#define QCOM_ID_SDA429W 437
216
216
#define QCOM_ID_SM8350 439
217
217
#define QCOM_ID_QCM2290 441
218
+
#define QCOM_ID_SM7125 443
218
219
#define QCOM_ID_SM6115 444
219
220
#define QCOM_ID_IPQ5010 446
220
221
#define QCOM_ID_IPQ5018 447
···
250
249
#define QCOM_ID_SA8775P 534
251
250
#define QCOM_ID_QRU1000 539
252
251
#define QCOM_ID_QDU1000 545
252
+
#define QCOM_ID_SM4450 568
253
253
#define QCOM_ID_QDU1010 587
254
-
#define QCOM_ID_IPQ5019 569
255
254
#define QCOM_ID_QRU1032 588
256
255
#define QCOM_ID_QRU1052 589
257
256
#define QCOM_ID_QRU1062 590
+21
include/dt-bindings/firmware/qcom,scm.h
+21
include/dt-bindings/firmware/qcom,scm.h
···
2
2
/*
3
3
* Copyright (c) 2010-2015, 2018-2019 The Linux Foundation. All rights reserved.
4
4
* Copyright (C) 2015 Linaro Ltd.
5
+
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
5
6
*/
6
7
7
8
#ifndef _DT_BINDINGS_FIRMWARE_QCOM_SCM_H
8
9
#define _DT_BINDINGS_FIRMWARE_QCOM_SCM_H
9
10
11
+
#define QCOM_SCM_VMID_TZ 0x1
10
12
#define QCOM_SCM_VMID_HLOS 0x3
11
13
#define QCOM_SCM_VMID_SSC_Q6 0x5
12
14
#define QCOM_SCM_VMID_ADSP_Q6 0x6
15
+
#define QCOM_SCM_VMID_CP_TOUCH 0x8
16
+
#define QCOM_SCM_VMID_CP_BITSTREAM 0x9
17
+
#define QCOM_SCM_VMID_CP_PIXEL 0xA
18
+
#define QCOM_SCM_VMID_CP_NON_PIXEL 0xB
19
+
#define QCOM_SCM_VMID_CP_CAMERA 0xD
20
+
#define QCOM_SCM_VMID_HLOS_FREE 0xE
13
21
#define QCOM_SCM_VMID_MSS_MSA 0xF
22
+
#define QCOM_SCM_VMID_MSS_NONMSA 0x10
23
+
#define QCOM_SCM_VMID_CP_SEC_DISPLAY 0x11
24
+
#define QCOM_SCM_VMID_CP_APP 0x12
25
+
#define QCOM_SCM_VMID_LPASS 0x16
14
26
#define QCOM_SCM_VMID_WLAN 0x18
15
27
#define QCOM_SCM_VMID_WLAN_CE 0x19
28
+
#define QCOM_SCM_VMID_CP_SPSS_SP 0x1A
29
+
#define QCOM_SCM_VMID_CP_CAMERA_PREVIEW 0x1D
30
+
#define QCOM_SCM_VMID_CDSP 0x1E
31
+
#define QCOM_SCM_VMID_CP_SPSS_SP_SHARED 0x22
32
+
#define QCOM_SCM_VMID_CP_SPSS_HLOS_SHARED 0x24
33
+
#define QCOM_SCM_VMID_ADSP_HEAP 0x25
34
+
#define QCOM_SCM_VMID_CP_CDSP 0x2A
16
35
#define QCOM_SCM_VMID_NAV 0x2B
36
+
#define QCOM_SCM_VMID_TVM 0x2D
37
+
#define QCOM_SCM_VMID_OEMVM 0x31
17
38
18
39
#endif
+25
include/dt-bindings/power/amlogic,c3-pwrc.h
+25
include/dt-bindings/power/amlogic,c3-pwrc.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
2
+
/*
3
+
* Copyright (c) 2023 Amlogic, Inc.
4
+
* Author: hongyu chen1 <hongyu.chen1@amlogic.com>
5
+
*/
6
+
#ifndef _DT_BINDINGS_AMLOGIC_C3_POWER_H
7
+
#define _DT_BINDINGS_AMLOGIC_C3_POWER_H
8
+
9
+
#define PWRC_C3_NNA_ID 0
10
+
#define PWRC_C3_AUDIO_ID 1
11
+
#define PWRC_C3_RESV_SEC_ID 2
12
+
#define PWRC_C3_SDIOA_ID 3
13
+
#define PWRC_C3_EMMC_ID 4
14
+
#define PWRC_C3_USB_COMB_ID 5
15
+
#define PWRC_C3_SDCARD_ID 6
16
+
#define PWRC_C3_ETH_ID 7
17
+
#define PWRC_C3_RESV0_ID 8
18
+
#define PWRC_C3_GE2D_ID 9
19
+
#define PWRC_C3_CVE_ID 10
20
+
#define PWRC_C3_GDC_WRAP_ID 11
21
+
#define PWRC_C3_ISP_TOP_ID 12
22
+
#define PWRC_C3_MIPI_ISP_WRAP_ID 13
23
+
#define PWRC_C3_VCODEC_ID 14
24
+
25
+
#endif
+30
include/dt-bindings/power/qcom,rpmhpd.h
+30
include/dt-bindings/power/qcom,rpmhpd.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
4
+
*/
5
+
6
+
#ifndef _DT_BINDINGS_POWER_QCOM_RPMHPD_H
7
+
#define _DT_BINDINGS_POWER_QCOM_RPMHPD_H
8
+
9
+
/* Generic RPMH Power Domain Indexes */
10
+
#define RPMHPD_CX 0
11
+
#define RPMHPD_CX_AO 1
12
+
#define RPMHPD_EBI 2
13
+
#define RPMHPD_GFX 3
14
+
#define RPMHPD_LCX 4
15
+
#define RPMHPD_LMX 5
16
+
#define RPMHPD_MMCX 6
17
+
#define RPMHPD_MMCX_AO 7
18
+
#define RPMHPD_MX 8
19
+
#define RPMHPD_MX_AO 9
20
+
#define RPMHPD_MXC 10
21
+
#define RPMHPD_MXC_AO 11
22
+
#define RPMHPD_MSS 12
23
+
#define RPMHPD_NSP 13
24
+
#define RPMHPD_NSP0 14
25
+
#define RPMHPD_NSP1 15
26
+
#define RPMHPD_QPHY 16
27
+
#define RPMHPD_DDR 17
28
+
#define RPMHPD_XO 18
29
+
30
+
#endif
+11
-5
include/linux/firmware/imx/sci.h
+11
-5
include/linux/firmware/imx/sci.h
···
21
21
int imx_scu_irq_register_notifier(struct notifier_block *nb);
22
22
int imx_scu_irq_unregister_notifier(struct notifier_block *nb);
23
23
int imx_scu_irq_group_enable(u8 group, u32 mask, u8 enable);
24
+
int imx_scu_irq_get_status(u8 group, u32 *irq_status);
24
25
int imx_scu_soc_init(struct device *dev);
25
26
#else
26
27
static inline int imx_scu_soc_init(struct device *dev)
27
28
{
28
-
return -ENOTSUPP;
29
+
return -EOPNOTSUPP;
29
30
}
30
31
31
32
static inline int imx_scu_enable_general_irq_channel(struct device *dev)
32
33
{
33
-
return -ENOTSUPP;
34
+
return -EOPNOTSUPP;
34
35
}
35
36
36
37
static inline int imx_scu_irq_register_notifier(struct notifier_block *nb)
37
38
{
38
-
return -ENOTSUPP;
39
+
return -EOPNOTSUPP;
39
40
}
40
41
41
42
static inline int imx_scu_irq_unregister_notifier(struct notifier_block *nb)
42
43
{
43
-
return -ENOTSUPP;
44
+
return -EOPNOTSUPP;
44
45
}
45
46
46
47
static inline int imx_scu_irq_group_enable(u8 group, u32 mask, u8 enable)
47
48
{
48
-
return -ENOTSUPP;
49
+
return -EOPNOTSUPP;
50
+
}
51
+
52
+
static inline int imx_scu_irq_get_status(u8 group, u32 *irq_status)
53
+
{
54
+
return -EOPNOTSUPP;
49
55
}
50
56
#endif
51
57
#endif /* _SC_SCI_H */
+1
-1
include/linux/firmware/qcom/qcom_scm.h
+1
-1
include/linux/firmware/qcom/qcom_scm.h
···
75
75
extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
76
76
size_t size,
77
77
struct qcom_scm_pas_metadata *ctx);
78
-
void qcom_scm_pas_metadata_release(struct qcom_scm_pas_metadata *ctx);
78
+
extern void qcom_scm_pas_metadata_release(struct qcom_scm_pas_metadata *ctx);
79
79
extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
80
80
phys_addr_t size);
81
81
extern int qcom_scm_pas_auth_and_reset(u32 peripheral);
+2
-2
include/linux/soc/qcom/qcom_aoss.h
+2
-2
include/linux/soc/qcom/qcom_aoss.h
···
13
13
14
14
#if IS_ENABLED(CONFIG_QCOM_AOSS_QMP)
15
15
16
-
int qmp_send(struct qmp *qmp, const void *data, size_t len);
16
+
int qmp_send(struct qmp *qmp, const char *fmt, ...);
17
17
struct qmp *qmp_get(struct device *dev);
18
18
void qmp_put(struct qmp *qmp);
19
19
20
20
#else
21
21
22
-
static inline int qmp_send(struct qmp *qmp, const void *data, size_t len)
22
+
static inline int qmp_send(struct qmp *qmp, const char *fmt, ...)
23
23
{
24
24
return -ENODEV;
25
25
}