Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/{i915, xe}: Extract pcode definitions to common header
There are certain register definitions which are commonly shared
by i915, xe and display. Extract the same to a common header to
avoid duplication.
Move GEN6_PCODE_MAILBOX to common pcode header to make intel_cdclk.c
free from including i915_reg.h.
v3: Include pcode header as required, instead in i915_reg.h (Jani)
v2: Make the header granular and per feature (Jani)
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patch.msgid.link/20260205094341.1882816-6-uma.shankar@intel.com
+130
-101
+1
drivers/gpu/drm/i915/display/hsw_ips.c
+1
drivers/gpu/drm/i915/display/hsw_ips.c
+1
drivers/gpu/drm/i915/display/intel_bw.c
+1
drivers/gpu/drm/i915/display/intel_bw.c
+1
-1
drivers/gpu/drm/i915/display/intel_cdclk.c
+1
-1
drivers/gpu/drm/i915/display/intel_cdclk.c
+1
drivers/gpu/drm/i915/display/intel_display_power.c
+1
drivers/gpu/drm/i915/display/intel_display_power.c
+1
drivers/gpu/drm/i915/display/intel_display_power_well.c
+1
drivers/gpu/drm/i915/display/intel_display_power_well.c
+1
drivers/gpu/drm/i915/display/intel_dram.c
+1
drivers/gpu/drm/i915/display/intel_dram.c
+1
drivers/gpu/drm/i915/display/intel_hdcp.c
+1
drivers/gpu/drm/i915/display/intel_hdcp.c
+1
drivers/gpu/drm/i915/display/skl_watermark.c
+1
drivers/gpu/drm/i915/display/skl_watermark.c
+1
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+1
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
+2
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
+2
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c
+2
drivers/gpu/drm/i915/gt/intel_llc.c
+2
drivers/gpu/drm/i915/gt/intel_llc.c
+1
drivers/gpu/drm/i915/gt/intel_rc6.c
+1
drivers/gpu/drm/i915/gt/intel_rc6.c
+1
drivers/gpu/drm/i915/gt/intel_rps.c
+1
drivers/gpu/drm/i915/gt/intel_rps.c
+1
drivers/gpu/drm/i915/gvt/handlers.c
+1
drivers/gpu/drm/i915/gvt/handlers.c
+1
drivers/gpu/drm/i915/i915_driver.c
+1
drivers/gpu/drm/i915/i915_driver.c
+2
drivers/gpu/drm/i915/i915_hwmon.c
+2
drivers/gpu/drm/i915/i915_hwmon.c
-100
drivers/gpu/drm/i915/i915_reg.h
-100
drivers/gpu/drm/i915/i915_reg.h
···
957
957
#define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7)
958
958
#define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3)
959
959
960
-
#define GEN6_PCODE_MAILBOX _MMIO(0x138124)
961
-
#define GEN6_PCODE_READY (1 << 31)
962
-
#define GEN6_PCODE_MB_PARAM2 REG_GENMASK(23, 16)
963
-
#define GEN6_PCODE_MB_PARAM1 REG_GENMASK(15, 8)
964
-
#define GEN6_PCODE_MB_COMMAND REG_GENMASK(7, 0)
965
-
#define GEN6_PCODE_ERROR_MASK 0xFF
966
-
#define GEN6_PCODE_SUCCESS 0x0
967
-
#define GEN6_PCODE_ILLEGAL_CMD 0x1
968
-
#define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
969
-
#define GEN6_PCODE_TIMEOUT 0x3
970
-
#define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF
971
-
#define GEN7_PCODE_TIMEOUT 0x2
972
-
#define GEN7_PCODE_ILLEGAL_DATA 0x3
973
-
#define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4
974
-
#define GEN11_PCODE_LOCKED 0x6
975
-
#define GEN11_PCODE_REJECTED 0x11
976
-
#define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
977
-
#define GEN6_PCODE_WRITE_RC6VIDS 0x4
978
-
#define GEN6_PCODE_READ_RC6VIDS 0x5
979
-
#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
980
-
#define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
981
-
#define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18
982
-
#define GEN9_PCODE_READ_MEM_LATENCY 0x6
983
-
#define GEN9_MEM_LATENCY_LEVEL_3_7_MASK REG_GENMASK(31, 24)
984
-
#define GEN9_MEM_LATENCY_LEVEL_2_6_MASK REG_GENMASK(23, 16)
985
-
#define GEN9_MEM_LATENCY_LEVEL_1_5_MASK REG_GENMASK(15, 8)
986
-
#define GEN9_MEM_LATENCY_LEVEL_0_4_MASK REG_GENMASK(7, 0)
987
-
#define SKL_PCODE_LOAD_HDCP_KEYS 0x5
988
-
#define SKL_PCODE_CDCLK_CONTROL 0x7
989
-
#define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3
990
-
#define SKL_CDCLK_READY_FOR_CHANGE 0x1
991
-
#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
992
-
#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
993
-
#define GEN6_READ_OC_PARAMS 0xc
994
-
#define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
995
-
#define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
996
-
#define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
997
-
#define ADL_PCODE_MEM_SS_READ_PSF_GV_INFO ((0) | (0x2 << 8))
998
-
#define DISPLAY_TO_PCODE_CDCLK_MAX 0x28D
999
-
#define DISPLAY_TO_PCODE_VOLTAGE_MASK REG_GENMASK(1, 0)
1000
-
#define DISPLAY_TO_PCODE_VOLTAGE_MAX DISPLAY_TO_PCODE_VOLTAGE_MASK
1001
-
#define DISPLAY_TO_PCODE_CDCLK_VALID REG_BIT(27)
1002
-
#define DISPLAY_TO_PCODE_PIPE_COUNT_VALID REG_BIT(31)
1003
-
#define DISPLAY_TO_PCODE_CDCLK_MASK REG_GENMASK(25, 16)
1004
-
#define DISPLAY_TO_PCODE_PIPE_COUNT_MASK REG_GENMASK(30, 28)
1005
-
#define DISPLAY_TO_PCODE_CDCLK(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_CDCLK_MASK, (x))
1006
-
#define DISPLAY_TO_PCODE_PIPE_COUNT(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_PIPE_COUNT_MASK, (x))
1007
-
#define DISPLAY_TO_PCODE_VOLTAGE(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_VOLTAGE_MASK, (x))
1008
-
#define DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, num_pipes, voltage_level) \
1009
-
((DISPLAY_TO_PCODE_CDCLK(cdclk)) | \
1010
-
(DISPLAY_TO_PCODE_PIPE_COUNT(num_pipes)) | \
1011
-
(DISPLAY_TO_PCODE_VOLTAGE(voltage_level)))
1012
-
#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
1013
-
#define ICL_PCODE_REP_QGV_MASK REG_GENMASK(1, 0)
1014
-
#define ICL_PCODE_REP_QGV_SAFE REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0)
1015
-
#define ICL_PCODE_REP_QGV_POLL REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 1)
1016
-
#define ICL_PCODE_REP_QGV_REJECTED REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 2)
1017
-
#define ADLS_PCODE_REP_PSF_MASK REG_GENMASK(3, 2)
1018
-
#define ADLS_PCODE_REP_PSF_SAFE REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0)
1019
-
#define ADLS_PCODE_REP_PSF_POLL REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 1)
1020
-
#define ADLS_PCODE_REP_PSF_REJECTED REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 2)
1021
-
#define ICL_PCODE_REQ_QGV_PT_MASK REG_GENMASK(7, 0)
1022
-
#define ICL_PCODE_REQ_QGV_PT(x) REG_FIELD_PREP(ICL_PCODE_REQ_QGV_PT_MASK, (x))
1023
-
#define ADLS_PCODE_REQ_PSF_PT_MASK REG_GENMASK(10, 8)
1024
-
#define ADLS_PCODE_REQ_PSF_PT(x) REG_FIELD_PREP(ADLS_PCODE_REQ_PSF_PT_MASK, (x))
1025
-
#define GEN6_PCODE_READ_D_COMP 0x10
1026
-
#define GEN6_PCODE_WRITE_D_COMP 0x11
1027
-
#define ICL_PCODE_EXIT_TCCOLD 0x12
1028
-
#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
1029
-
#define DISPLAY_IPS_CONTROL 0x19
1030
-
#define TGL_PCODE_TCCOLD 0x26
1031
-
#define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0)
1032
-
#define TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ 0
1033
-
#define TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ REG_BIT(0)
1034
-
/* See also IPS_CTL */
1035
-
#define IPS_PCODE_CONTROL (1 << 30)
1036
-
#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
1037
-
#define GEN9_PCODE_SAGV_CONTROL 0x21
1038
-
#define GEN9_SAGV_DISABLE 0x0
1039
-
#define GEN9_SAGV_IS_DISABLED 0x1
1040
-
#define GEN9_SAGV_ENABLE 0x3
1041
-
#define DG1_PCODE_STATUS 0x7E
1042
-
#define DG1_UNCORE_GET_INIT_STATUS 0x0
1043
-
#define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1
1044
-
#define PCODE_POWER_SETUP 0x7C
1045
-
#define POWER_SETUP_SUBCOMMAND_READ_I1 0x4
1046
-
#define POWER_SETUP_SUBCOMMAND_WRITE_I1 0x5
1047
-
#define POWER_SETUP_I1_WATTS REG_BIT(31)
1048
-
#define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */
1049
-
#define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0)
1050
-
#define POWER_SETUP_SUBCOMMAND_G8_ENABLE 0x6
1051
-
#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
1052
-
#define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* pvc */
1053
-
/* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
1054
-
#define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0
1055
-
#define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1
1056
-
/* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */
1057
-
/* XEHP_PCODE_FREQUENCY_CONFIG param2 */
1058
-
#define PCODE_MBOX_DOMAIN_NONE 0x0
1059
-
#define PCODE_MBOX_DOMAIN_MEDIAFF 0x3
1060
960
#define GEN6_PCODE_DATA _MMIO(0x138128)
1061
961
#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
1062
962
#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
+2
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+2
drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+1
drivers/gpu/drm/i915/intel_pcode.c
+1
drivers/gpu/drm/i915/intel_pcode.c
+108
include/drm/intel/intel_pcode_regs.h
+108
include/drm/intel/intel_pcode_regs.h
···
1
+
/* SPDX-License-Identifier: MIT */
2
+
/* Copyright © 2026 Intel Corporation */
3
+
4
+
#ifndef _INTEL_PCODE_REGS_H_
5
+
#define _INTEL_PCODE_REGS_H_
6
+
7
+
#define GEN6_PCODE_MAILBOX _MMIO(0x138124)
8
+
#define GEN6_PCODE_READY (1 << 31)
9
+
#define GEN6_PCODE_MB_PARAM2 REG_GENMASK(23, 16)
10
+
#define GEN6_PCODE_MB_PARAM1 REG_GENMASK(15, 8)
11
+
#define GEN6_PCODE_MB_COMMAND REG_GENMASK(7, 0)
12
+
#define GEN6_PCODE_ERROR_MASK 0xFF
13
+
#define GEN6_PCODE_SUCCESS 0x0
14
+
#define GEN6_PCODE_ILLEGAL_CMD 0x1
15
+
#define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
16
+
#define GEN6_PCODE_TIMEOUT 0x3
17
+
#define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF
18
+
#define GEN7_PCODE_TIMEOUT 0x2
19
+
#define GEN7_PCODE_ILLEGAL_DATA 0x3
20
+
#define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4
21
+
#define GEN11_PCODE_LOCKED 0x6
22
+
#define GEN11_PCODE_REJECTED 0x11
23
+
#define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
24
+
#define GEN6_PCODE_WRITE_RC6VIDS 0x4
25
+
#define GEN6_PCODE_READ_RC6VIDS 0x5
26
+
#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
27
+
#define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
28
+
#define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18
29
+
#define GEN9_PCODE_READ_MEM_LATENCY 0x6
30
+
#define GEN9_MEM_LATENCY_LEVEL_3_7_MASK REG_GENMASK(31, 24)
31
+
#define GEN9_MEM_LATENCY_LEVEL_2_6_MASK REG_GENMASK(23, 16)
32
+
#define GEN9_MEM_LATENCY_LEVEL_1_5_MASK REG_GENMASK(15, 8)
33
+
#define GEN9_MEM_LATENCY_LEVEL_0_4_MASK REG_GENMASK(7, 0)
34
+
#define SKL_PCODE_LOAD_HDCP_KEYS 0x5
35
+
#define SKL_PCODE_CDCLK_CONTROL 0x7
36
+
#define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3
37
+
#define SKL_CDCLK_READY_FOR_CHANGE 0x1
38
+
#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
39
+
#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
40
+
#define GEN6_READ_OC_PARAMS 0xc
41
+
#define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
42
+
#define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
43
+
#define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
44
+
#define ADL_PCODE_MEM_SS_READ_PSF_GV_INFO ((0) | (0x2 << 8))
45
+
#define DISPLAY_TO_PCODE_CDCLK_MAX 0x28D
46
+
#define DISPLAY_TO_PCODE_VOLTAGE_MASK REG_GENMASK(1, 0)
47
+
#define DISPLAY_TO_PCODE_VOLTAGE_MAX DISPLAY_TO_PCODE_VOLTAGE_MASK
48
+
#define DISPLAY_TO_PCODE_CDCLK_VALID REG_BIT(27)
49
+
#define DISPLAY_TO_PCODE_PIPE_COUNT_VALID REG_BIT(31)
50
+
#define DISPLAY_TO_PCODE_CDCLK_MASK REG_GENMASK(25, 16)
51
+
#define DISPLAY_TO_PCODE_PIPE_COUNT_MASK REG_GENMASK(30, 28)
52
+
#define DISPLAY_TO_PCODE_CDCLK(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_CDCLK_MASK, (x))
53
+
#define DISPLAY_TO_PCODE_PIPE_COUNT(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_PIPE_COUNT_MASK, (x))
54
+
#define DISPLAY_TO_PCODE_VOLTAGE(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_VOLTAGE_MASK, (x))
55
+
#define DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, num_pipes, voltage_level) \
56
+
((DISPLAY_TO_PCODE_CDCLK(cdclk)) | \
57
+
(DISPLAY_TO_PCODE_PIPE_COUNT(num_pipes)) | \
58
+
(DISPLAY_TO_PCODE_VOLTAGE(voltage_level)))
59
+
#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
60
+
#define ICL_PCODE_REP_QGV_MASK REG_GENMASK(1, 0)
61
+
#define ICL_PCODE_REP_QGV_SAFE REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0)
62
+
#define ICL_PCODE_REP_QGV_POLL REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 1)
63
+
#define ICL_PCODE_REP_QGV_REJECTED REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 2)
64
+
#define ADLS_PCODE_REP_PSF_MASK REG_GENMASK(3, 2)
65
+
#define ADLS_PCODE_REP_PSF_SAFE REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0)
66
+
#define ADLS_PCODE_REP_PSF_POLL REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 1)
67
+
#define ADLS_PCODE_REP_PSF_REJECTED REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 2)
68
+
#define ICL_PCODE_REQ_QGV_PT_MASK REG_GENMASK(7, 0)
69
+
#define ICL_PCODE_REQ_QGV_PT(x) REG_FIELD_PREP(ICL_PCODE_REQ_QGV_PT_MASK, (x))
70
+
#define ADLS_PCODE_REQ_PSF_PT_MASK REG_GENMASK(10, 8)
71
+
#define ADLS_PCODE_REQ_PSF_PT(x) REG_FIELD_PREP(ADLS_PCODE_REQ_PSF_PT_MASK, (x))
72
+
#define GEN6_PCODE_READ_D_COMP 0x10
73
+
#define GEN6_PCODE_WRITE_D_COMP 0x11
74
+
#define ICL_PCODE_EXIT_TCCOLD 0x12
75
+
#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
76
+
#define DISPLAY_IPS_CONTROL 0x19
77
+
#define TGL_PCODE_TCCOLD 0x26
78
+
#define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0)
79
+
#define TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ 0
80
+
#define TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ REG_BIT(0)
81
+
/* See also IPS_CTL */
82
+
#define IPS_PCODE_CONTROL (1 << 30)
83
+
#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
84
+
#define GEN9_PCODE_SAGV_CONTROL 0x21
85
+
#define GEN9_SAGV_DISABLE 0x0
86
+
#define GEN9_SAGV_IS_DISABLED 0x1
87
+
#define GEN9_SAGV_ENABLE 0x3
88
+
#define DG1_PCODE_STATUS 0x7E
89
+
#define DG1_UNCORE_GET_INIT_STATUS 0x0
90
+
#define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1
91
+
#define PCODE_POWER_SETUP 0x7C
92
+
#define POWER_SETUP_SUBCOMMAND_READ_I1 0x4
93
+
#define POWER_SETUP_SUBCOMMAND_WRITE_I1 0x5
94
+
#define POWER_SETUP_I1_WATTS REG_BIT(31)
95
+
#define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */
96
+
#define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0)
97
+
#define POWER_SETUP_SUBCOMMAND_G8_ENABLE 0x6
98
+
#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
99
+
#define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* pvc */
100
+
/* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
101
+
#define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0
102
+
#define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1
103
+
/* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */
104
+
/* XEHP_PCODE_FREQUENCY_CONFIG param2 */
105
+
#define PCODE_MBOX_DOMAIN_NONE 0x0
106
+
#define PCODE_MBOX_DOMAIN_MEDIAFF 0x3
107
+
108
+
#endif