Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: update GPU addresses for SMU and PSP
add amdgpu_bo_fb_aper_addr() and update the cached GPU addresses to use
the FB aperture address for SMU and PSP.
2 reasons for this change:
1. when pdb0 is enabled, gpu addr from amdgpu_bo_create_kernel() is GART
aperture address, it is not compatible with SMU and PSP, it need to be
updated to use FB aperture address.
2. Since FB aperture address will change after switching to new GPU
index after hibernation, it need to be updated on resume.
Signed-off-by: Jiang Liu <gerry@linux.alibaba.com>
Signed-off-by: Samuel Zhang <guoqing.zhang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Samuel Zhang
and committed by
Alex Deucher
18b66a6c
0f566f0e
+65
+20
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+20
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
···
1473
1473
}
1474
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/**
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+
* amdgpu_bo_fb_aper_addr - return FB aperture GPU offset of the VRAM bo
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+
* @bo: amdgpu VRAM buffer object for which we query the offset
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+
*
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* Returns:
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* current FB aperture GPU offset of the object.
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+
*/
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+
u64 amdgpu_bo_fb_aper_addr(struct amdgpu_bo *bo)
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+
{
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+
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
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+
uint64_t offset, fb_base;
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+
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+
WARN_ON_ONCE(bo->tbo.resource->mem_type != TTM_PL_VRAM);
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+
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+
fb_base = adev->gmc.fb_start;
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+
fb_base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
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+
offset = (bo->tbo.resource->start << PAGE_SHIFT) + fb_base;
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+
return amdgpu_gmc_sign_extend(offset);
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+
}
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+
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+
/**
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* amdgpu_bo_gpu_offset_no_check - return GPU offset of bo
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* @bo: amdgpu object for which we query the offset
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*
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
···
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bool intr);
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int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr);
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u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo);
307
+
u64 amdgpu_bo_fb_aper_addr(struct amdgpu_bo *bo);
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u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo);
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uint32_t amdgpu_bo_mem_stats_placement(struct amdgpu_bo *bo);
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uint32_t amdgpu_bo_get_preferred_domain(struct amdgpu_device *adev,
+23
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+23
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
···
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872
&psp->tmr_bo, &psp->tmr_mc_addr,
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pptr);
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}
875
+
if (amdgpu_virt_xgmi_migrate_enabled(psp->adev) && psp->tmr_bo)
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+
psp->tmr_mc_addr = amdgpu_bo_fb_aper_addr(psp->tmr_bo);
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return ret;
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}
···
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psp_copy_fw(psp, context->bin_desc.start_addr,
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context->bin_desc.size_bytes);
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+
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+
if (amdgpu_virt_xgmi_migrate_enabled(psp->adev) &&
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+
context->mem_context.shared_bo)
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+
context->mem_context.shared_mc_addr =
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+
amdgpu_bo_fb_aper_addr(context->mem_context.shared_bo);
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psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context);
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···
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return false;
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}
2347
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+
static void psp_update_gpu_addresses(struct amdgpu_device *adev)
2342
+
{
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+
struct psp_context *psp = &adev->psp;
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+
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+
if (psp->cmd_buf_bo && psp->cmd_buf_mem) {
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+
psp->fw_pri_mc_addr = amdgpu_bo_fb_aper_addr(psp->fw_pri_bo);
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+
psp->fence_buf_mc_addr = amdgpu_bo_fb_aper_addr(psp->fence_buf_bo);
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+
psp->cmd_buf_mc_addr = amdgpu_bo_fb_aper_addr(psp->cmd_buf_bo);
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+
}
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+
if (adev->firmware.rbuf && psp->km_ring.ring_mem)
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+
psp->km_ring.ring_mem_mc_addr = amdgpu_bo_fb_aper_addr(adev->firmware.rbuf);
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+
}
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+
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static int psp_hw_start(struct psp_context *psp)
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{
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struct amdgpu_device *adev = psp->adev;
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int ret;
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+
2359
+
if (amdgpu_virt_xgmi_migrate_enabled(adev))
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+
psp_update_gpu_addresses(adev);
2352
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if (!amdgpu_sriov_vf(adev)) {
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if ((is_psp_fw_valid(psp->kdb)) &&
+3
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+3
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
···
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adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM;
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}
1157
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+
if (amdgpu_virt_xgmi_migrate_enabled(adev) && adev->firmware.fw_buf)
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+
adev->firmware.fw_buf_mc = amdgpu_bo_fb_aper_addr(adev->firmware.fw_buf);
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+
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for (i = 0; i < adev->firmware.max_ucodes; i++) {
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ucode = &adev->firmware.ucode[i];
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if (ucode->fw) {
+18
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+18
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
···
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1004
return 0;
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}
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+
static void smu_update_gpu_addresses(struct smu_context *smu)
1008
+
{
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+
struct smu_table_context *smu_table = &smu->smu_table;
1010
+
struct smu_table *pm_status_table = smu_table->tables + SMU_TABLE_PMSTATUSLOG;
1011
+
struct smu_table *driver_table = &(smu_table->driver_table);
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+
struct smu_table *dummy_read_1_table = &smu_table->dummy_read_1_table;
1013
+
1014
+
if (pm_status_table->bo)
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+
pm_status_table->mc_address = amdgpu_bo_fb_aper_addr(pm_status_table->bo);
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+
if (driver_table->bo)
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+
driver_table->mc_address = amdgpu_bo_fb_aper_addr(driver_table->bo);
1018
+
if (dummy_read_1_table->bo)
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+
dummy_read_1_table->mc_address = amdgpu_bo_fb_aper_addr(dummy_read_1_table->bo);
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+
}
1021
+
1007
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/**
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* smu_alloc_memory_pool - allocate memory pool in the system memory
1009
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*
···
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{
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struct amdgpu_device *adev = smu->adev;
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int ret = 0;
1782
+
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+
if (amdgpu_virt_xgmi_migrate_enabled(adev))
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+
smu_update_gpu_addresses(smu);
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smu->smc_fw_state = SMU_FW_INIT;
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