Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'gpio/merge' of git://git.secretlab.ca/git/linux-2.6
* 'gpio/merge' of git://git.secretlab.ca/git/linux-2.6:
gpio: Fix DA9052 GPIO build errors.
gpio: mpc8xxx: don't allow input-only pins to be output for MPC5121
gpio-ml-ioh: Add the irq_disable/irq_enable hooks for ml-ioh irq chip
gpio-ml-ioh: fix a bug in the interrupt handler
gpio: pl061: drop extra check for NULL platform_data
+52
-23
+8
-13
drivers/gpio/gpio-da9052.c
+8
-13
drivers/gpio/gpio-da9052.c
···
22
22
#include <linux/mfd/da9052/da9052.h>
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23
#include <linux/mfd/da9052/reg.h>
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#include <linux/mfd/da9052/pdata.h>
25
-
#include <linux/mfd/da9052/gpio.h>
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#define DA9052_INPUT 1
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#define DA9052_OUTPUT_OPENDRAIN 2
···
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#define DA9052_GPIO_MASK_UPPER_NIBBLE 0xF0
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#define DA9052_GPIO_MASK_LOWER_NIBBLE 0x0F
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#define DA9052_GPIO_NIBBLE_SHIFT 4
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+
#define DA9052_IRQ_GPI0 16
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+
#define DA9052_GPIO_ODD_SHIFT 7
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+
#define DA9052_GPIO_EVEN_SHIFT 3
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struct da9052_gpio {
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struct da9052 *da9052;
···
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static void da9052_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
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{
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struct da9052_gpio *gpio = to_da9052_gpio(gc);
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-
unsigned char register_value = 0;
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int ret;
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108
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if (da9052_gpio_port_odd(offset)) {
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-
if (value) {
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-
register_value = DA9052_GPIO_ODD_PORT_MODE;
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ret = da9052_reg_update(gpio->da9052, (offset >> 1) +
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111
DA9052_GPIO_0_1_REG,
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DA9052_GPIO_ODD_PORT_MODE,
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-
register_value);
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+
value << DA9052_GPIO_ODD_SHIFT);
119
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if (ret != 0)
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dev_err(gpio->da9052->dev,
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"Failed to updated gpio odd reg,%d",
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ret);
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-
}
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} else {
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-
if (value) {
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-
register_value = DA9052_GPIO_EVEN_PORT_MODE;
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ret = da9052_reg_update(gpio->da9052, (offset >> 1) +
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DA9052_GPIO_0_1_REG,
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DA9052_GPIO_EVEN_PORT_MODE,
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-
register_value);
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+
value << DA9052_GPIO_EVEN_SHIFT);
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if (ret != 0)
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dev_err(gpio->da9052->dev,
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125
"Failed to updated gpio even reg,%d",
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126
ret);
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-
}
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127
}
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128
}
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129
···
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.direction_input = da9052_gpio_direction_input,
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.direction_output = da9052_gpio_direction_output,
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.to_irq = da9052_gpio_to_irq,
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-
.can_sleep = 1;
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-
.ngpio = 16;
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-
.base = -1;
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+
.can_sleep = 1,
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+
.ngpio = 16,
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+
.base = -1,
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};
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static int __devinit da9052_gpio_probe(struct platform_device *pdev)
+31
-1
drivers/gpio/gpio-ml-ioh.c
+31
-1
drivers/gpio/gpio-ml-ioh.c
···
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&chip->reg->regs[chip->ch].imask);
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}
334
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+
static void ioh_irq_disable(struct irq_data *d)
336
+
{
337
+
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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+
struct ioh_gpio *chip = gc->private;
339
+
unsigned long flags;
340
+
u32 ien;
341
+
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+
spin_lock_irqsave(&chip->spinlock, flags);
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+
ien = ioread32(&chip->reg->regs[chip->ch].ien);
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+
ien &= ~(1 << (d->irq - chip->irq_base));
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+
iowrite32(ien, &chip->reg->regs[chip->ch].ien);
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+
spin_unlock_irqrestore(&chip->spinlock, flags);
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+
}
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+
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+
static void ioh_irq_enable(struct irq_data *d)
350
+
{
351
+
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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+
struct ioh_gpio *chip = gc->private;
353
+
unsigned long flags;
354
+
u32 ien;
355
+
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+
spin_lock_irqsave(&chip->spinlock, flags);
357
+
ien = ioread32(&chip->reg->regs[chip->ch].ien);
358
+
ien |= 1 << (d->irq - chip->irq_base);
359
+
iowrite32(ien, &chip->reg->regs[chip->ch].ien);
360
+
spin_unlock_irqrestore(&chip->spinlock, flags);
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+
}
362
+
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static irqreturn_t ioh_gpio_handler(int irq, void *dev_id)
336
364
{
337
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struct ioh_gpio *chip = dev_id;
···
367
339
int i, j;
368
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int ret = IRQ_NONE;
369
341
370
-
for (i = 0; i < 8; i++) {
342
+
for (i = 0; i < 8; i++, chip++) {
371
343
reg_val = ioread32(&chip->reg->regs[i].istatus);
372
344
for (j = 0; j < num_ports[i]; j++) {
373
345
if (reg_val & BIT(j)) {
···
398
370
ct->chip.irq_mask = ioh_irq_mask;
399
371
ct->chip.irq_unmask = ioh_irq_unmask;
400
372
ct->chip.irq_set_type = ioh_irq_type;
373
+
ct->chip.irq_disable = ioh_irq_disable;
374
+
ct->chip.irq_enable = ioh_irq_enable;
401
375
402
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irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
403
377
IRQ_NOREQUEST | IRQ_NOPROBE, 0);
+13
-5
drivers/gpio/gpio-mpc8xxx.c
+13
-5
drivers/gpio/gpio-mpc8xxx.c
···
132
132
return 0;
133
133
}
134
134
135
+
static int mpc5121_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
136
+
{
137
+
/* GPIO 28..31 are input only on MPC5121 */
138
+
if (gpio >= 28)
139
+
return -EINVAL;
140
+
141
+
return mpc8xxx_gpio_dir_out(gc, gpio, val);
142
+
}
143
+
135
144
static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
136
145
{
137
146
struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
···
349
340
mm_gc->save_regs = mpc8xxx_gpio_save_regs;
350
341
gc->ngpio = MPC8XXX_GPIO_PINS;
351
342
gc->direction_input = mpc8xxx_gpio_dir_in;
352
-
gc->direction_output = mpc8xxx_gpio_dir_out;
353
-
if (of_device_is_compatible(np, "fsl,mpc8572-gpio"))
354
-
gc->get = mpc8572_gpio_get;
355
-
else
356
-
gc->get = mpc8xxx_gpio_get;
343
+
gc->direction_output = of_device_is_compatible(np, "fsl,mpc5121-gpio") ?
344
+
mpc5121_gpio_dir_out : mpc8xxx_gpio_dir_out;
345
+
gc->get = of_device_is_compatible(np, "fsl,mpc8572-gpio") ?
346
+
mpc8572_gpio_get : mpc8xxx_gpio_get;
357
347
gc->set = mpc8xxx_gpio_set;
358
348
gc->to_irq = mpc8xxx_gpio_to_irq;
359
349
-4
drivers/gpio/gpio-pl061.c
-4
drivers/gpio/gpio-pl061.c