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Merge tag 'perf-urgent-2024-08-04' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull x86 perf fixes from Thomas Gleixner:

- Move the smp_processor_id() invocation back into the non-preemtible
region, so that the result is valid to use

- Add the missing package C2 residency counters for Sierra Forest CPUs
to make the newly added support actually useful

* tag 'perf-urgent-2024-08-04' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
perf/x86: Fix smp_processor_id()-in-preemptible warnings
perf/x86/intel/cstate: Add pkg C2 residency counter for Sierra Forest

+15 -12
+12 -10
arch/x86/events/core.c
··· 1520 1520 void perf_event_print_debug(void) 1521 1521 { 1522 1522 u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; 1523 + unsigned long *cntr_mask, *fixed_cntr_mask; 1524 + struct event_constraint *pebs_constraints; 1525 + struct cpu_hw_events *cpuc; 1523 1526 u64 pebs, debugctl; 1524 - int cpu = smp_processor_id(); 1525 - struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); 1526 - unsigned long *cntr_mask = hybrid(cpuc->pmu, cntr_mask); 1527 - unsigned long *fixed_cntr_mask = hybrid(cpuc->pmu, fixed_cntr_mask); 1528 - struct event_constraint *pebs_constraints = hybrid(cpuc->pmu, pebs_constraints); 1529 - unsigned long flags; 1530 - int idx; 1527 + int cpu, idx; 1528 + 1529 + guard(irqsave)(); 1530 + 1531 + cpu = smp_processor_id(); 1532 + cpuc = &per_cpu(cpu_hw_events, cpu); 1533 + cntr_mask = hybrid(cpuc->pmu, cntr_mask); 1534 + fixed_cntr_mask = hybrid(cpuc->pmu, fixed_cntr_mask); 1535 + pebs_constraints = hybrid(cpuc->pmu, pebs_constraints); 1531 1536 1532 1537 if (!*(u64 *)cntr_mask) 1533 1538 return; 1534 - 1535 - local_irq_save(flags); 1536 1539 1537 1540 if (x86_pmu.version >= 2) { 1538 1541 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); ··· 1580 1577 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", 1581 1578 cpu, idx, pmc_count); 1582 1579 } 1583 - local_irq_restore(flags); 1584 1580 } 1585 1581 1586 1582 void x86_pmu_stop(struct perf_event *event, int flags)
+3 -2
arch/x86/events/intel/cstate.c
··· 64 64 * perf code: 0x00 65 65 * Available model: SNB,IVB,HSW,BDW,SKL,KNL,GLM,CNL, 66 66 * KBL,CML,ICL,ICX,TGL,TNT,RKL,ADL, 67 - * RPL,SPR,MTL,ARL,LNL 67 + * RPL,SPR,MTL,ARL,LNL,SRF 68 68 * Scope: Package (physical package) 69 69 * MSR_PKG_C3_RESIDENCY: Package C3 Residency Counter. 70 70 * perf code: 0x01 ··· 693 693 .core_events = BIT(PERF_CSTATE_CORE_C1_RES) | 694 694 BIT(PERF_CSTATE_CORE_C6_RES), 695 695 696 - .pkg_events = BIT(PERF_CSTATE_PKG_C6_RES), 696 + .pkg_events = BIT(PERF_CSTATE_PKG_C2_RES) | 697 + BIT(PERF_CSTATE_PKG_C6_RES), 697 698 698 699 .module_events = BIT(PERF_CSTATE_MODULE_C6_RES), 699 700 };