Merge tag 'tty-6.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty

+9 -6

Documentation/ABI/testing/sysfs-tty

··· 87 87 Date: October 2012 88 88 Contact: Alan Cox <alan@linux.intel.com> 89 89 Description: 90 - Show the closing delay time for this port in ms. 90 + Show the closing delay time for this port in centiseconds. 91 91 92 - These sysfs values expose the TIOCGSERIAL interface via 93 - sysfs rather than via ioctls. 92 + These sysfs values expose the TIOCGSERIAL interface via 93 + sysfs rather than via ioctls. 94 94 95 95 What: /sys/class/tty/ttyS<x>/closing_wait 96 96 Date: October 2012 97 97 Contact: Alan Cox <alan@linux.intel.com> 98 98 Description: 99 - Show the close wait time for this port in ms. 99 + Show the close wait time for this port in centiseconds. 100 100 101 - These sysfs values expose the TIOCGSERIAL interface via 102 - sysfs rather than via ioctls. 101 + Waiting forever is represented as 0. If waiting on close is 102 + disabled then the value is 65535. 103 + 104 + These sysfs values expose the TIOCGSERIAL interface via 105 + sysfs rather than via ioctls. 103 106 104 107 What: /sys/class/tty/ttyS<x>/custom_divisor 105 108 Date: October 2012

+42

Documentation/devicetree/bindings/serial/esp,esp32-acm.yaml

··· 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 + 3 + %YAML 1.2 4 + --- 5 + $id: http://devicetree.org/schemas/serial/esp,esp32-acm.yaml# 6 + $schema: http://devicetree.org/meta-schemas/core.yaml# 7 + 8 + title: ESP32S3 ACM gadget controller 9 + 10 + maintainers: 11 + - Max Filippov <jcmvbkbc@gmail.com> 12 + 13 + description: 14 + Fixed function USB CDC-ACM gadget controller of the Espressif ESP32S3 SoC. 15 + 16 + allOf: 17 + - $ref: serial.yaml# 18 + 19 + properties: 20 + compatible: 21 + const: esp,esp32s3-acm 22 + 23 + reg: 24 + maxItems: 1 25 + 26 + interrupts: 27 + maxItems: 1 28 + 29 + required: 30 + - compatible 31 + - reg 32 + - interrupts 33 + 34 + additionalProperties: false 35 + 36 + examples: 37 + - | 38 + serial@60038000 { 39 + compatible = "esp,esp32s3-acm"; 40 + reg = <0x60038000 0x1000>; 41 + interrupts = <96 3 0>; 42 + };

+51

Documentation/devicetree/bindings/serial/esp,esp32-uart.yaml

··· 1 + # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2 + 3 + %YAML 1.2 4 + --- 5 + $id: http://devicetree.org/schemas/serial/esp,esp32-uart.yaml# 6 + $schema: http://devicetree.org/meta-schemas/core.yaml# 7 + 8 + title: ESP32xx UART controllers 9 + 10 + maintainers: 11 + - Max Filippov <jcmvbkbc@gmail.com> 12 + 13 + description: 14 + ESP32 UART controller is a part of the ESP32 SoC. 15 + ESP32S3 UART controller is a part of the ESP32S3 SoC. 16 + Both SoCs are produced by Espressif Systems Co. Ltd. 17 + 18 + allOf: 19 + - $ref: serial.yaml# 20 + 21 + properties: 22 + compatible: 23 + enum: 24 + - esp,esp32-uart 25 + - esp,esp32s3-uart 26 + 27 + reg: 28 + maxItems: 1 29 + 30 + interrupts: 31 + maxItems: 1 32 + 33 + clocks: 34 + maxItems: 1 35 + 36 + required: 37 + - compatible 38 + - reg 39 + - interrupts 40 + - clocks 41 + 42 + additionalProperties: false 43 + 44 + examples: 45 + - | 46 + serial@60000000 { 47 + compatible = "esp,esp32s3-uart"; 48 + reg = <0x60000000 0x80>; 49 + interrupts = <27 1 0>; 50 + clocks = <&serial_clk>; 51 + };

+2

Documentation/devicetree/bindings/serial/fsl-imx-uart.yaml

··· 70 70 interrupts: 71 71 maxItems: 1 72 72 73 + wakeup-source: true 74 + 73 75 fsl,dte-mode: 74 76 $ref: /schemas/types.yaml#/definitions/flag 75 77 description: |

+8 -5

Documentation/devicetree/bindings/serial/fsl-mxs-auart.yaml

··· 14 14 15 15 properties: 16 16 compatible: 17 - enum: 18 - - fsl,imx23-auart 19 - - fsl,imx28-auart 20 - - alphascale,asm9260-auart 17 + oneOf: 18 + - const: fsl,imx23-auart 19 + - const: alphascale,asm9260-auart 20 + - items: 21 + - enum: 22 + - fsl,imx28-auart 23 + - const: fsl,imx23-auart 21 24 22 25 reg: 23 26 maxItems: 1 ··· 85 82 }; 86 83 87 84 auart0: serial@8006a000 { 88 - compatible = "fsl,imx28-auart"; 85 + compatible = "fsl,imx28-auart", "fsl,imx23-auart"; 89 86 reg = <0x8006a000 0x2000>; 90 87 interrupts = <112>; 91 88 dmas = <&dma_apbx 8>, <&dma_apbx 9>;

-48

Documentation/devicetree/bindings/serial/maxim,max310x.txt

··· 1 - * Maxim MAX310X advanced Universal Asynchronous Receiver-Transmitter (UART) 2 - 3 - Required properties: 4 - - compatible: Should be one of the following: 5 - - "maxim,max3107" for Maxim MAX3107, 6 - - "maxim,max3108" for Maxim MAX3108, 7 - - "maxim,max3109" for Maxim MAX3109, 8 - - "maxim,max14830" for Maxim MAX14830. 9 - - reg: SPI chip select number. 10 - - interrupts: Specifies the interrupt source of the parent interrupt 11 - controller. The format of the interrupt specifier depends on the 12 - parent interrupt controller. 13 - - clocks: phandle to the IC source clock. 14 - - clock-names: Should be "xtal" if clock is an external crystal or 15 - "osc" if an external clock source is used. 16 - 17 - Optional properties: 18 - - gpio-controller: Marks the device node as a GPIO controller. 19 - - #gpio-cells: Should be two. The first cell is the GPIO number and 20 - the second cell is used to specify the GPIO polarity: 21 - 0 = active high, 22 - 1 = active low. 23 - 24 - Example: 25 - 26 - / { 27 - clocks { 28 - spi_uart_clk: osc_max14830 { 29 - compatible = "fixed-clock"; 30 - #clock-cells = <0>; 31 - clock-frequency = <3686400>; 32 - }; 33 - 34 - }; 35 - }; 36 - 37 - &spi0 { 38 - max14830: max14830@0 { 39 - compatible = "maxim,max14830"; 40 - reg = <0>; 41 - clocks = <&spi_uart_clk>; 42 - clock-names = "osc"; 43 - interrupt-parent = <&gpio3>; 44 - interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 45 - gpio-controller; 46 - #gpio-cells = <2>; 47 - }; 48 - };

+74

Documentation/devicetree/bindings/serial/maxim,max310x.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/serial/maxim,max310x.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Maxim MAX310X Advanced Universal Asynchronous Receiver-Transmitter (UART) 8 + 9 + maintainers: 10 + - Hugo Villeneuve <hvilleneuve@dimonoff.com> 11 + 12 + properties: 13 + compatible: 14 + enum: 15 + - maxim,max3107 16 + - maxim,max3108 17 + - maxim,max3109 18 + - maxim,max14830 19 + 20 + reg: 21 + maxItems: 1 22 + 23 + interrupts: 24 + maxItems: 1 25 + 26 + clocks: 27 + maxItems: 1 28 + 29 + clock-names: 30 + enum: 31 + - xtal # External crystal 32 + - osc # External clock source 33 + 34 + gpio-controller: true 35 + 36 + "#gpio-cells": 37 + const: 2 38 + 39 + gpio-line-names: 40 + minItems: 1 41 + maxItems: 16 42 + 43 + required: 44 + - compatible 45 + - reg 46 + - interrupts 47 + - clocks 48 + - clock-names 49 + 50 + allOf: 51 + - $ref: /schemas/spi/spi-peripheral-props.yaml# 52 + - $ref: /schemas/serial/serial.yaml# 53 + - $ref: /schemas/serial/rs485.yaml# 54 + 55 + unevaluatedProperties: false 56 + 57 + examples: 58 + - | 59 + #include <dt-bindings/interrupt-controller/irq.h> 60 + i2c { 61 + #address-cells = <1>; 62 + #size-cells = <0>; 63 + 64 + serial@2c { 65 + compatible = "maxim,max3107"; 66 + reg = <0x2c>; 67 + clocks = <&xtal4m>; 68 + clock-names = "xtal"; 69 + interrupt-parent = <&gpio3>; 70 + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 71 + gpio-controller; 72 + #gpio-cells = <2>; 73 + }; 74 + };

+5 -5

Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.yaml

··· 91 91 - description: range upper bound 92 92 - description: adjustment (in permyriad, i.e. 0.01%) 93 93 94 - allOf: 95 - - $ref: serial.yaml 96 - 97 - unevaluatedProperties: false 98 - 99 94 required: 100 95 - compatible 101 96 - reg ··· 100 105 - reset-names 101 106 - dmas 102 107 - dma-names 108 + 109 + allOf: 110 + - $ref: serial.yaml 111 + 112 + unevaluatedProperties: false 103 113 104 114 examples: 105 115 - |

-118

Documentation/devicetree/bindings/serial/nxp,sc16is7xx.txt

··· 1 - * NXP SC16IS7xx advanced Universal Asynchronous Receiver-Transmitter (UART) 2 - * i2c as bus 3 - 4 - Required properties: 5 - - compatible: Should be one of the following: 6 - - "nxp,sc16is740" for NXP SC16IS740, 7 - - "nxp,sc16is741" for NXP SC16IS741, 8 - - "nxp,sc16is750" for NXP SC16IS750, 9 - - "nxp,sc16is752" for NXP SC16IS752, 10 - - "nxp,sc16is760" for NXP SC16IS760, 11 - - "nxp,sc16is762" for NXP SC16IS762. 12 - - reg: I2C address of the SC16IS7xx device. 13 - - interrupts: Should contain the UART interrupt 14 - - clocks: Reference to the IC source clock. 15 - OR (when there is no clock provider visible to the platform) 16 - - clock-frequency: The source clock frequency for the IC. 17 - 18 - Optional properties: 19 - - gpio-controller: Marks the device node as a GPIO controller. 20 - - #gpio-cells: Should be two. The first cell is the GPIO number and 21 - the second cell is used to specify the GPIO polarity: 22 - 0 = active high, 23 - 1 = active low. 24 - - irda-mode-ports: An array that lists the indices of the port that 25 - should operate in IrDA mode. 26 - - nxp,modem-control-line-ports: An array that lists the indices of the port that 27 - should have shared GPIO lines configured as 28 - modem control lines. 29 - 30 - Example: 31 - sc16is750: sc16is750@51 { 32 - compatible = "nxp,sc16is750"; 33 - reg = <0x51>; 34 - clocks = <&clk20m>; 35 - interrupt-parent = <&gpio3>; 36 - interrupts = <7 IRQ_TYPE_EDGE_FALLING>; 37 - gpio-controller; 38 - #gpio-cells = <2>; 39 - }; 40 - 41 - sc16is752: sc16is752@53 { 42 - compatible = "nxp,sc16is752"; 43 - reg = <0x53>; 44 - clocks = <&clk20m>; 45 - interrupt-parent = <&gpio3>; 46 - interrupts = <7 IRQ_TYPE_EDGE_FALLING>; 47 - nxp,modem-control-line-ports = <1>; /* Port 1 as modem control lines */ 48 - gpio-controller; /* Port 0 as GPIOs */ 49 - #gpio-cells = <2>; 50 - }; 51 - 52 - sc16is752: sc16is752@54 { 53 - compatible = "nxp,sc16is752"; 54 - reg = <0x54>; 55 - clocks = <&clk20m>; 56 - interrupt-parent = <&gpio3>; 57 - interrupts = <7 IRQ_TYPE_EDGE_FALLING>; 58 - nxp,modem-control-line-ports = <0 1>; /* Ports 0 and 1 as modem control lines */ 59 - }; 60 - 61 - * spi as bus 62 - 63 - Required properties: 64 - - compatible: Should be one of the following: 65 - - "nxp,sc16is740" for NXP SC16IS740, 66 - - "nxp,sc16is741" for NXP SC16IS741, 67 - - "nxp,sc16is750" for NXP SC16IS750, 68 - - "nxp,sc16is752" for NXP SC16IS752, 69 - - "nxp,sc16is760" for NXP SC16IS760, 70 - - "nxp,sc16is762" for NXP SC16IS762. 71 - - reg: SPI chip select number. 72 - - interrupts: Specifies the interrupt source of the parent interrupt 73 - controller. The format of the interrupt specifier depends on the 74 - parent interrupt controller. 75 - - clocks: phandle to the IC source clock. 76 - 77 - Optional properties: 78 - - gpio-controller: Marks the device node as a GPIO controller. 79 - - #gpio-cells: Should be two. The first cell is the GPIO number and 80 - the second cell is used to specify the GPIO polarity: 81 - 0 = active high, 82 - 1 = active low. 83 - - irda-mode-ports: An array that lists the indices of the port that 84 - should operate in IrDA mode. 85 - - nxp,modem-control-line-ports: An array that lists the indices of the port that 86 - should have shared GPIO lines configured as 87 - modem control lines. 88 - 89 - Example: 90 - sc16is750: sc16is750@0 { 91 - compatible = "nxp,sc16is750"; 92 - reg = <0>; 93 - clocks = <&clk20m>; 94 - interrupt-parent = <&gpio3>; 95 - interrupts = <7 IRQ_TYPE_EDGE_FALLING>; 96 - gpio-controller; 97 - #gpio-cells = <2>; 98 - }; 99 - 100 - sc16is752: sc16is752@1 { 101 - compatible = "nxp,sc16is752"; 102 - reg = <1>; 103 - clocks = <&clk20m>; 104 - interrupt-parent = <&gpio3>; 105 - interrupts = <7 IRQ_TYPE_EDGE_FALLING>; 106 - nxp,modem-control-line-ports = <1>; /* Port 1 as modem control lines */ 107 - gpio-controller; /* Port 0 as GPIOs */ 108 - #gpio-cells = <2>; 109 - }; 110 - 111 - sc16is752: sc16is752@2 { 112 - compatible = "nxp,sc16is752"; 113 - reg = <2>; 114 - clocks = <&clk20m>; 115 - interrupt-parent = <&gpio3>; 116 - interrupts = <7 IRQ_TYPE_EDGE_FALLING>; 117 - nxp,modem-control-line-ports = <0 1>; /* Ports 0 and 1 as modem control lines */ 118 - };

+127

Documentation/devicetree/bindings/serial/nxp,sc16is7xx.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/serial/nxp,sc16is7xx.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: NXP SC16IS7xx Advanced Universal Asynchronous Receiver-Transmitter (UART) 8 + 9 + maintainers: 10 + - Hugo Villeneuve <hvilleneuve@dimonoff.com> 11 + 12 + properties: 13 + compatible: 14 + enum: 15 + - nxp,sc16is740 16 + - nxp,sc16is741 17 + - nxp,sc16is750 18 + - nxp,sc16is752 19 + - nxp,sc16is760 20 + - nxp,sc16is762 21 + 22 + reg: 23 + maxItems: 1 24 + 25 + interrupts: 26 + maxItems: 1 27 + 28 + clocks: 29 + maxItems: 1 30 + 31 + clock-frequency: 32 + description: 33 + When there is no clock provider visible to the platform, this 34 + is the source crystal or external clock frequency for the IC in Hz. 35 + minimum: 1 36 + maximum: 80000000 37 + 38 + gpio-controller: true 39 + 40 + "#gpio-cells": 41 + const: 2 42 + 43 + gpio-line-names: 44 + minItems: 1 45 + maxItems: 8 46 + 47 + irda-mode-ports: 48 + description: | 49 + An array that lists the indices of the port that should operate in IrDA 50 + mode: 51 + 0: port A 52 + 1: port B 53 + $ref: /schemas/types.yaml#/definitions/uint32-array 54 + minItems: 1 55 + maxItems: 2 56 + items: 57 + minimum: 0 58 + maximum: 1 59 + 60 + nxp,modem-control-line-ports: 61 + description: | 62 + An array that lists the indices of the port that should have shared GPIO 63 + lines configured as modem control lines: 64 + 0: port A 65 + 1: port B 66 + $ref: /schemas/types.yaml#/definitions/uint32-array 67 + minItems: 1 68 + maxItems: 2 69 + items: 70 + minimum: 0 71 + maximum: 1 72 + 73 + required: 74 + - compatible 75 + - reg 76 + - interrupts 77 + 78 + allOf: 79 + - $ref: /schemas/spi/spi-peripheral-props.yaml# 80 + - $ref: /schemas/serial/serial.yaml# 81 + - $ref: /schemas/serial/rs485.yaml# 82 + 83 + oneOf: 84 + - required: 85 + - clocks 86 + - required: 87 + - clock-frequency 88 + 89 + unevaluatedProperties: false 90 + 91 + examples: 92 + - | 93 + #include <dt-bindings/interrupt-controller/irq.h> 94 + i2c { 95 + #address-cells = <1>; 96 + #size-cells = <0>; 97 + 98 + serial@51 { 99 + compatible = "nxp,sc16is750"; 100 + reg = <0x51>; 101 + clocks = <&clk20m>; 102 + interrupt-parent = <&gpio3>; 103 + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; 104 + gpio-controller; 105 + #gpio-cells = <2>; 106 + }; 107 + 108 + serial@53 { 109 + compatible = "nxp,sc16is752"; 110 + reg = <0x53>; 111 + clocks = <&clk20m>; 112 + interrupt-parent = <&gpio3>; 113 + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; 114 + nxp,modem-control-line-ports = <1>; /* Port 1 as modem control lines */ 115 + gpio-controller; /* Port 0 as GPIOs */ 116 + #gpio-cells = <2>; 117 + }; 118 + 119 + serial@54 { 120 + compatible = "nxp,sc16is752"; 121 + reg = <0x54>; 122 + clocks = <&clk20m>; 123 + interrupt-parent = <&gpio3>; 124 + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; 125 + nxp,modem-control-line-ports = <0 1>; /* Ports 0 and 1 as modem control lines */ 126 + }; 127 + };

+2 -2

Documentation/devicetree/bindings/serial/qcom,msm-uart.yaml

··· 40 40 - interrupts 41 41 - reg 42 42 43 - unevaluatedProperties: false 44 - 45 43 allOf: 46 44 - $ref: /schemas/serial/serial.yaml# 45 + 46 + unevaluatedProperties: false 47 47 48 48 examples: 49 49 - |

+2 -2

Documentation/devicetree/bindings/serial/qcom,msm-uartdm.yaml

··· 78 78 - interrupts 79 79 - reg 80 80 81 - unevaluatedProperties: false 82 - 83 81 allOf: 84 82 - $ref: /schemas/serial/serial.yaml# 85 83 ··· 94 96 properties: 95 97 reg: 96 98 maxItems: 1 99 + 100 + unevaluatedProperties: false 97 101 98 102 examples: 99 103 - |

+7 -7

Documentation/devicetree/bindings/serial/renesas,em-uart.yaml

··· 38 38 - const: sclk 39 39 - const: pclk 40 40 41 + required: 42 + - compatible 43 + - reg 44 + - interrupts 45 + - clocks 46 + - clock-names 47 + 41 48 allOf: 42 49 - $ref: serial.yaml# 43 50 ··· 59 52 minItems: 2 60 53 clock-names: 61 54 minItems: 2 62 - 63 - required: 64 - - compatible 65 - - reg 66 - - interrupts 67 - - clocks 68 - - clock-names 69 55 70 56 unevaluatedProperties: false 71 57

+2 -2

Documentation/devicetree/bindings/serial/renesas,hscif.yaml

··· 111 111 - clock-names 112 112 - power-domains 113 113 114 - unevaluatedProperties: false 115 - 116 114 if: 117 115 properties: 118 116 compatible: ··· 122 124 then: 123 125 required: 124 126 - resets 127 + 128 + unevaluatedProperties: false 125 129 126 130 examples: 127 131 - |

+1

Documentation/devicetree/bindings/serial/renesas,scif.yaml

··· 79 79 - enum: 80 80 - renesas,scif-r9a07g043 # RZ/G2UL and RZ/Five 81 81 - renesas,scif-r9a07g054 # RZ/V2L 82 + - renesas,scif-r9a08g045 # RZ/G3S 82 83 - const: renesas,scif-r9a07g044 # RZ/G2{L,LC} fallback 83 84 84 85 reg:

+2 -2

Documentation/devicetree/bindings/serial/renesas,scifa.yaml

··· 77 77 - clock-names 78 78 - power-domains 79 79 80 - unevaluatedProperties: false 81 - 82 80 if: 83 81 properties: 84 82 compatible: ··· 86 88 then: 87 89 required: 88 90 - resets 91 + 92 + unevaluatedProperties: false 89 93 90 94 examples: 91 95 - |

+2 -2

Documentation/devicetree/bindings/serial/renesas,scifb.yaml

··· 77 77 - clock-names 78 78 - power-domains 79 79 80 - unevaluatedProperties: false 81 - 82 80 if: 83 81 properties: 84 82 compatible: ··· 86 88 then: 87 89 required: 88 90 - resets 91 + 92 + unevaluatedProperties: false 89 93 90 94 examples: 91 95 - |

+4

Documentation/devicetree/bindings/serial/rs485.yaml

··· 29 29 default: 0 30 30 maximum: 100 31 31 32 + rs485-rts-active-high: 33 + description: drive RTS high when sending (this is the default). 34 + $ref: /schemas/types.yaml#/definitions/flag 35 + 32 36 rs485-rts-active-low: 33 37 description: drive RTS low when sending (default is high). 34 38 $ref: /schemas/types.yaml#/definitions/flag

+2 -6

Documentation/devicetree/bindings/serial/samsung_uart.yaml

··· 24 24 - enum: 25 25 - apple,s5l-uart 26 26 - axis,artpec8-uart 27 - - samsung,s3c2410-uart 28 - - samsung,s3c2412-uart 29 - - samsung,s3c2440-uart 30 27 - samsung,s3c6400-uart 31 28 - samsung,s5pv210-uart 32 29 - samsung,exynos4210-uart ··· 83 86 - interrupts 84 87 - reg 85 88 86 - unevaluatedProperties: false 87 - 88 89 allOf: 89 90 - $ref: serial.yaml# 90 91 ··· 91 96 compatible: 92 97 contains: 93 98 enum: 94 - - samsung,s3c2410-uart 95 99 - samsung,s5pv210-uart 96 100 then: 97 101 properties: ··· 121 127 items: 122 128 - const: uart 123 129 - const: clk_uart_baud0 130 + 131 + unevaluatedProperties: false 124 132 125 133 examples: 126 134 - |

+9 -9

Documentation/devicetree/bindings/serial/serial.yaml

··· 87 87 description: 88 88 TX FIFO threshold configuration (in bytes). 89 89 90 - if: 91 - required: 92 - - uart-has-rtscts 93 - then: 94 - properties: 95 - cts-gpios: false 96 - rts-gpios: false 97 - 98 90 patternProperties: 99 - "^bluetooth|gnss|gps|mcu$": 91 + "^(bluetooth|bluetooth-gnss|gnss|gps|mcu)$": 100 92 if: 101 93 type: object 102 94 then: ··· 127 135 128 136 required: 129 137 - compatible 138 + 139 + if: 140 + required: 141 + - uart-has-rtscts 142 + then: 143 + properties: 144 + cts-gpios: false 145 + rts-gpios: false 130 146 131 147 additionalProperties: true 132 148

+1

Documentation/driver-api/tty/index.rst

··· 36 36 tty_struct 37 37 tty_ldisc 38 38 tty_buffer 39 + tty_ioctl 39 40 tty_internals 40 41 41 42 Writing TTY Driver

+10

Documentation/driver-api/tty/tty_ioctl.rst

··· 1 + .. SPDX-License-Identifier: GPL-2.0 2 + 3 + ================= 4 + TTY IOCTL Helpers 5 + ================= 6 + 7 + .. kernel-doc:: drivers/tty/tty_ioctl.c 8 + 9 + .. kernel-doc:: include/linux/tty.h 10 + :identifiers: tty_get_baud_rate

+2

arch/alpha/kernel/proto.h

··· 1 1 /* SPDX-License-Identifier: GPL-2.0 */ 2 2 #include <linux/interrupt.h> 3 + #include <linux/screen_info.h> 3 4 #include <linux/io.h> 4 5 5 6 /* Prototypes of functions used across modules here in this directory. */ ··· 114 113 #ifdef CONFIG_VERBOSE_MCHECK 115 114 extern unsigned long alpha_verbose_mcheck; 116 115 #endif 116 + extern struct screen_info vgacon_screen_info; 117 117 118 118 /* srmcons.c */ 119 119 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_SRM)

+4 -4

arch/alpha/kernel/setup.c

··· 131 131 132 132 static char __initdata command_line[COMMAND_LINE_SIZE]; 133 133 134 + #ifdef CONFIG_VGA_CONSOLE 134 135 /* 135 136 * The format of "screen_info" is strange, and due to early 136 137 * i386-setup code. This is just enough to make the console 137 138 * code think we're on a VGA color display. 138 139 */ 139 140 140 - struct screen_info screen_info = { 141 + struct screen_info vgacon_screen_info = { 141 142 .orig_x = 0, 142 143 .orig_y = 25, 143 144 .orig_video_cols = 80, ··· 146 145 .orig_video_isVGA = 1, 147 146 .orig_video_points = 16 148 147 }; 149 - 150 - EXPORT_SYMBOL(screen_info); 148 + #endif 151 149 152 150 /* 153 151 * The direct map I/O window, if any. This should be the same ··· 652 652 653 653 #ifdef CONFIG_VT 654 654 #if defined(CONFIG_VGA_CONSOLE) 655 - conswitchp = &vga_con; 655 + vgacon_register_screen(&vgacon_screen_info); 656 656 #endif 657 657 #endif 658 658

+5 -3

arch/alpha/kernel/sys_sio.c

··· 57 57 static inline void __init 58 58 alphabook1_init_arch(void) 59 59 { 60 + #ifdef CONFIG_VGA_CONSOLE 60 61 /* The AlphaBook1 has LCD video fixed at 800x600, 61 62 37 rows and 100 cols. */ 62 - screen_info.orig_y = 37; 63 - screen_info.orig_video_cols = 100; 64 - screen_info.orig_video_lines = 37; 63 + vgacon_screen_info.orig_y = 37; 64 + vgacon_screen_info.orig_video_cols = 100; 65 + vgacon_screen_info.orig_video_lines = 37; 66 + #endif 65 67 66 68 lca_init_arch(); 67 69 }

+5

arch/arm/include/asm/setup.h

··· 11 11 #ifndef __ASMARM_SETUP_H 12 12 #define __ASMARM_SETUP_H 13 13 14 + #include <linux/screen_info.h> 14 15 #include <uapi/asm/setup.h> 15 16 16 17 ··· 35 34 void early_mm_init(const struct machine_desc *); 36 35 void adjust_lowmem_bounds(void); 37 36 void setup_dma_zone(const struct machine_desc *desc); 37 + 38 + #ifdef CONFIG_VGA_CONSOLE 39 + extern struct screen_info vgacon_screen_info; 40 + #endif 38 41 39 42 #endif

+1

arch/arm/include/asm/vga.h

··· 5 5 #include <linux/io.h> 6 6 7 7 extern unsigned long vga_base; 8 + extern struct screen_info vgacon_screen_info; 8 9 9 10 #define VGA_MAP_MEM(x,s) (vga_base + (x)) 10 11

+10 -10

arch/arm/kernel/atags_parse.c

··· 69 69 70 70 __tagtable(ATAG_MEM, parse_tag_mem32); 71 71 72 - #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE) 72 + #if defined(CONFIG_ARCH_FOOTBRIDGE) && defined(CONFIG_VGA_CONSOLE) 73 73 static int __init parse_tag_videotext(const struct tag *tag) 74 74 { 75 - screen_info.orig_x = tag->u.videotext.x; 76 - screen_info.orig_y = tag->u.videotext.y; 77 - screen_info.orig_video_page = tag->u.videotext.video_page; 78 - screen_info.orig_video_mode = tag->u.videotext.video_mode; 79 - screen_info.orig_video_cols = tag->u.videotext.video_cols; 80 - screen_info.orig_video_ega_bx = tag->u.videotext.video_ega_bx; 81 - screen_info.orig_video_lines = tag->u.videotext.video_lines; 82 - screen_info.orig_video_isVGA = tag->u.videotext.video_isvga; 83 - screen_info.orig_video_points = tag->u.videotext.video_points; 75 + vgacon_screen_info.orig_x = tag->u.videotext.x; 76 + vgacon_screen_info.orig_y = tag->u.videotext.y; 77 + vgacon_screen_info.orig_video_page = tag->u.videotext.video_page; 78 + vgacon_screen_info.orig_video_mode = tag->u.videotext.video_mode; 79 + vgacon_screen_info.orig_video_cols = tag->u.videotext.video_cols; 80 + vgacon_screen_info.orig_video_ega_bx = tag->u.videotext.video_ega_bx; 81 + vgacon_screen_info.orig_video_lines = tag->u.videotext.video_lines; 82 + vgacon_screen_info.orig_video_isVGA = tag->u.videotext.video_isvga; 83 + vgacon_screen_info.orig_video_points = tag->u.videotext.video_points; 84 84 return 0; 85 85 } 86 86

-6

arch/arm/kernel/efi.c

··· 123 123 { 124 124 efi_init(); 125 125 126 - if (screen_info.orig_video_isVGA == VIDEO_TYPE_EFI) { 127 - /* dummycon on ARM needs non-zero values for columns/lines */ 128 - screen_info.orig_video_cols = 80; 129 - screen_info.orig_video_lines = 25; 130 - } 131 - 132 126 /* ARM does not permit early mappings to persist across paging_init() */ 133 127 efi_memmap_unmap(); 134 128

+3 -4

arch/arm/kernel/setup.c

··· 928 928 request_resource(&ioport_resource, &lp2); 929 929 } 930 930 931 - #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE) || \ 932 - defined(CONFIG_EFI) 933 - struct screen_info screen_info = { 931 + #if defined(CONFIG_VGA_CONSOLE) 932 + struct screen_info vgacon_screen_info = { 934 933 .orig_video_lines = 30, 935 934 .orig_video_cols = 80, 936 935 .orig_video_mode = 0, ··· 1193 1194 1194 1195 #ifdef CONFIG_VT 1195 1196 #if defined(CONFIG_VGA_CONSOLE) 1196 - conswitchp = &vga_con; 1197 + vgacon_register_screen(&vgacon_screen_info); 1197 1198 #endif 1198 1199 #endif 1199 1200

-4

arch/arm64/kernel/efi.c

··· 71 71 return pgprot_val(PAGE_KERNEL_EXEC); 72 72 } 73 73 74 - /* we will fill this structure from the stub, so don't put it in .bss */ 75 - struct screen_info screen_info __section(".data"); 76 - EXPORT_SYMBOL(screen_info); 77 - 78 74 int __init efi_create_mapping(struct mm_struct *mm, efi_memory_desc_t *md) 79 75 { 80 76 pteval_t prot_val = create_mapping_protection(md);

+2

arch/arm64/kernel/image-vars.h

··· 27 27 PROVIDE(__efistub__end = _end); 28 28 PROVIDE(__efistub___inittext_end = __inittext_end); 29 29 PROVIDE(__efistub__edata = _edata); 30 + #if defined(CONFIG_EFI_EARLYCON) || defined(CONFIG_SYSFB) 30 31 PROVIDE(__efistub_screen_info = screen_info); 32 + #endif 31 33 PROVIDE(__efistub__ctype = _ctype); 32 34 33 35 PROVIDE(__pi___memcpy = __pi_memcpy);

-12

arch/csky/kernel/setup.c

··· 8 8 #include <linux/of_fdt.h> 9 9 #include <linux/start_kernel.h> 10 10 #include <linux/dma-map-ops.h> 11 - #include <linux/screen_info.h> 12 11 #include <asm/sections.h> 13 12 #include <asm/mmu_context.h> 14 13 #include <asm/pgalloc.h> 15 - 16 - #ifdef CONFIG_DUMMY_CONSOLE 17 - struct screen_info screen_info = { 18 - .orig_video_lines = 30, 19 - .orig_video_cols = 80, 20 - .orig_video_mode = 0, 21 - .orig_video_ega_bx = 0, 22 - .orig_video_isVGA = 1, 23 - .orig_video_points = 8 24 - }; 25 - #endif 26 14 27 15 static void __init csky_memblock_init(void) 28 16 {

-2

arch/hexagon/kernel/Makefile

··· 17 17 obj-$(CONFIG_HAS_DMA) += dma.o 18 18 19 19 obj-$(CONFIG_STACKTRACE) += stacktrace.o 20 - 21 - obj-$(CONFIG_VGA_CONSOLE) += screen_info.o

-3

arch/hexagon/kernel/screen_info.c

··· 1 - #include <linux/screen_info.h> 2 - 3 - struct screen_info screen_info;

+7 -1

arch/loongarch/kernel/efi.c

··· 68 68 69 69 unsigned long __initdata screen_info_table = EFI_INVALID_TABLE_ADDR; 70 70 71 + #if defined(CONFIG_SYSFB) || defined(CONFIG_EFI_EARLYCON) 72 + struct screen_info screen_info __section(".data"); 73 + EXPORT_SYMBOL_GPL(screen_info); 74 + #endif 75 + 71 76 static void __init init_screen_info(void) 72 77 { 73 78 struct screen_info *si; ··· 120 115 121 116 set_bit(EFI_CONFIG_TABLES, &efi.flags); 122 117 123 - init_screen_info(); 118 + if (IS_ENABLED(CONFIG_EFI_EARLYCON) || IS_ENABLED(CONFIG_SYSFB)) 119 + init_screen_info(); 124 120 125 121 if (boot_memmap == EFI_INVALID_TABLE_ADDR) 126 122 return;

+2

arch/loongarch/kernel/image-vars.h

··· 12 12 __efistub_kernel_asize = kernel_asize; 13 13 __efistub_kernel_fsize = kernel_fsize; 14 14 __efistub_kernel_offset = kernel_offset; 15 + #if defined(CONFIG_EFI_EARLYCON) || defined(CONFIG_SYSFB) 15 16 __efistub_screen_info = screen_info; 17 + #endif 16 18 17 19 #endif 18 20

-3

arch/loongarch/kernel/setup.c

··· 16 16 #include <linux/dmi.h> 17 17 #include <linux/efi.h> 18 18 #include <linux/export.h> 19 - #include <linux/screen_info.h> 20 19 #include <linux/memblock.h> 21 20 #include <linux/initrd.h> 22 21 #include <linux/ioport.h> ··· 55 56 #define SMBIOS_FREQLOW_MASK 0xFF 56 57 #define SMBIOS_CORE_PACKAGE_OFFSET 0x23 57 58 #define LOONGSON_EFI_ENABLE (1 << 3) 58 - 59 - struct screen_info screen_info __section(".data"); 60 59 61 60 unsigned long fw_arg0, fw_arg1, fw_arg2; 62 61 DEFINE_PER_CPU(unsigned long, kernelsp);

-9

arch/mips/jazz/setup.c

··· 13 13 #include <linux/init.h> 14 14 #include <linux/ioport.h> 15 15 #include <linux/console.h> 16 - #include <linux/screen_info.h> 17 16 #include <linux/platform_device.h> 18 17 #include <linux/serial_8250.h> 19 18 #include <linux/dma-mapping.h> ··· 74 75 /* The RTC is outside the port address space */ 75 76 76 77 _machine_restart = jazz_machine_restart; 77 - 78 - #ifdef CONFIG_VT 79 - screen_info = (struct screen_info) { 80 - .orig_video_cols = 160, 81 - .orig_video_lines = 64, 82 - .orig_video_points = 16, 83 - }; 84 - #endif 85 78 86 79 add_preferred_console("ttyS", 0, "9600"); 87 80 }

-11

arch/mips/kernel/setup.c

··· 15 15 #include <linux/delay.h> 16 16 #include <linux/ioport.h> 17 17 #include <linux/export.h> 18 - #include <linux/screen_info.h> 19 18 #include <linux/memblock.h> 20 19 #include <linux/initrd.h> 21 20 #include <linux/root_dev.h> ··· 52 53 struct cpuinfo_mips cpu_data[NR_CPUS] __read_mostly; 53 54 54 55 EXPORT_SYMBOL(cpu_data); 55 - 56 - #ifdef CONFIG_VT 57 - struct screen_info screen_info; 58 - #endif 59 56 60 57 /* 61 58 * Setup information ··· 787 792 cpu_report(); 788 793 if (IS_ENABLED(CONFIG_CPU_R4X00_BUGS64)) 789 794 check_bugs64_early(); 790 - 791 - #if defined(CONFIG_VT) 792 - #if defined(CONFIG_VGA_CONSOLE) 793 - conswitchp = &vga_con; 794 - #endif 795 - #endif 796 795 797 796 arch_mem_init(cmdline_p); 798 797 dmi_setup();

+3 -1

arch/mips/mti-malta/malta-setup.c

··· 161 161 #if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) 162 162 static void __init screen_info_setup(void) 163 163 { 164 - screen_info = (struct screen_info) { 164 + static struct screen_info si = { 165 165 .orig_x = 0, 166 166 .orig_y = 25, 167 167 .ext_mem_k = 0, ··· 175 175 .orig_video_isVGA = VIDEO_TYPE_VGAC, 176 176 .orig_video_points = 16 177 177 }; 178 + 179 + vgacon_register_screen(&si); 178 180 } 179 181 #endif 180 182

+16 -11

arch/mips/sibyte/swarm/setup.c

··· 13 13 #include <linux/memblock.h> 14 14 #include <linux/init.h> 15 15 #include <linux/kernel.h> 16 + #include <linux/console.h> 16 17 #include <linux/screen_info.h> 17 18 #include <linux/initrd.h> 18 19 ··· 113 112 } 114 113 } 115 114 115 + #ifdef CONFIG_VGA_CONSOLE 116 + static struct screen_info vgacon_screen_info = { 117 + .orig_video_page = 52, 118 + .orig_video_mode = 3, 119 + .orig_video_cols = 80, 120 + .flags = 12, 121 + .orig_video_ega_bx = 3, 122 + .orig_video_lines = 25, 123 + .orig_video_isVGA = 0x22, 124 + .orig_video_points = 16, 125 + }; 126 + #endif 127 + 116 128 void __init plat_mem_setup(void) 117 129 { 118 130 #ifdef CONFIG_SIBYTE_BCM1x80 ··· 143 129 if (m41t81_probe()) 144 130 swarm_rtc_type = RTC_M41T81; 145 131 146 - #ifdef CONFIG_VT 147 - screen_info = (struct screen_info) { 148 - .orig_video_page = 52, 149 - .orig_video_mode = 3, 150 - .orig_video_cols = 80, 151 - .flags = 12, 152 - .orig_video_ega_bx = 3, 153 - .orig_video_lines = 25, 154 - .orig_video_isVGA = 0x22, 155 - .orig_video_points = 16, 156 - }; 132 + #ifdef CONFIG_VGA_CONSOLE 133 + vgacon_register_screen(&vgacon_screen_info); 157 134 /* XXXKW for CFE, get lines/cols from environment */ 158 135 #endif 159 136 }

+10 -8

arch/mips/sni/setup.c

··· 38 38 39 39 static void __init sni_display_setup(void) 40 40 { 41 - #if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) && defined(CONFIG_FW_ARC) 42 - struct screen_info *si = &screen_info; 41 + #if defined(CONFIG_VGA_CONSOLE) && defined(CONFIG_FW_ARC) 42 + static struct screen_info si; 43 43 DISPLAY_STATUS *di; 44 44 45 45 di = ArcGetDisplayStatus(1); 46 46 47 47 if (di) { 48 - si->orig_x = di->CursorXPosition; 49 - si->orig_y = di->CursorYPosition; 50 - si->orig_video_cols = di->CursorMaxXPosition; 51 - si->orig_video_lines = di->CursorMaxYPosition; 52 - si->orig_video_isVGA = VIDEO_TYPE_VGAC; 53 - si->orig_video_points = 16; 48 + si.orig_x = di->CursorXPosition; 49 + si.orig_y = di->CursorYPosition; 50 + si.orig_video_cols = di->CursorMaxXPosition; 51 + si.orig_video_lines = di->CursorMaxYPosition; 52 + si.orig_video_isVGA = VIDEO_TYPE_VGAC; 53 + si.orig_video_points = 16; 54 + 55 + vgacon_register_screen(&si); 54 56 } 55 57 #endif 56 58 }

-5

arch/nios2/kernel/setup.c

··· 19 19 #include <linux/memblock.h> 20 20 #include <linux/initrd.h> 21 21 #include <linux/of_fdt.h> 22 - #include <linux/screen_info.h> 23 22 24 23 #include <asm/mmu_context.h> 25 24 #include <asm/sections.h> ··· 34 35 static struct pt_regs fake_regs = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 35 36 0, 0, 0, 0, 0, 0, 36 37 0}; 37 - 38 - #ifdef CONFIG_VT 39 - struct screen_info screen_info; 40 - #endif 41 38 42 39 /* Copy a short hook instruction sequence to the exception address */ 43 40 static inline void copy_exception_handler(unsigned int addr)

-16

arch/powerpc/kernel/setup-common.c

··· 22 22 #include <linux/seq_file.h> 23 23 #include <linux/ioport.h> 24 24 #include <linux/console.h> 25 - #include <linux/screen_info.h> 26 25 #include <linux/root_dev.h> 27 26 #include <linux/cpu.h> 28 27 #include <linux/unistd.h> ··· 96 97 */ 97 98 int dcache_bsize; 98 99 int icache_bsize; 99 - 100 - /* 101 - * This still seems to be needed... -- paulus 102 - */ 103 - struct screen_info screen_info = { 104 - .orig_x = 0, 105 - .orig_y = 25, 106 - .orig_video_cols = 80, 107 - .orig_video_lines = 25, 108 - .orig_video_isVGA = 1, 109 - .orig_video_points = 16 110 - }; 111 - #if defined(CONFIG_FB_VGA16_MODULE) 112 - EXPORT_SYMBOL(screen_info); 113 - #endif 114 100 115 101 /* Variables required to store legacy IO irq routing */ 116 102 int of_i8042_kbd_irq;

+2

arch/riscv/kernel/image-vars.h

··· 28 28 __efistub__end = _end; 29 29 __efistub__edata = _edata; 30 30 __efistub___init_text_end = __init_text_end; 31 + #if defined(CONFIG_EFI_EARLYCON) || defined(CONFIG_SYSFB) 31 32 __efistub_screen_info = screen_info; 33 + #endif 32 34 33 35 #endif 34 36

-12

arch/riscv/kernel/setup.c

··· 15 15 #include <linux/memblock.h> 16 16 #include <linux/sched.h> 17 17 #include <linux/console.h> 18 - #include <linux/screen_info.h> 19 18 #include <linux/of_fdt.h> 20 19 #include <linux/sched/task.h> 21 20 #include <linux/smp.h> ··· 38 39 #include <asm/efi.h> 39 40 40 41 #include "head.h" 41 - 42 - #if defined(CONFIG_DUMMY_CONSOLE) || defined(CONFIG_EFI) 43 - struct screen_info screen_info __section(".data") = { 44 - .orig_video_lines = 30, 45 - .orig_video_cols = 80, 46 - .orig_video_mode = 0, 47 - .orig_video_ega_bx = 0, 48 - .orig_video_isVGA = 1, 49 - .orig_video_points = 8 50 - }; 51 - #endif 52 42 53 43 /* 54 44 * The lucky hart to first increment this variable will boot the other cores.

-5

arch/sh/kernel/setup.c

··· 7 7 * Copyright (C) 1999 Niibe Yutaka 8 8 * Copyright (C) 2002 - 2010 Paul Mundt 9 9 */ 10 - #include <linux/screen_info.h> 11 10 #include <linux/ioport.h> 12 11 #include <linux/init.h> 13 12 #include <linux/initrd.h> ··· 67 68 */ 68 69 struct sh_machine_vector sh_mv = { .mv_name = "generic", }; 69 70 EXPORT_SYMBOL(sh_mv); 70 - 71 - #ifdef CONFIG_VT 72 - struct screen_info screen_info; 73 - #endif 74 71 75 72 extern int root_mountflags; 76 73

-13

arch/sparc/kernel/setup_32.c

··· 17 17 #include <linux/initrd.h> 18 18 #include <asm/smp.h> 19 19 #include <linux/user.h> 20 - #include <linux/screen_info.h> 21 20 #include <linux/delay.h> 22 21 #include <linux/fs.h> 23 22 #include <linux/seq_file.h> ··· 49 50 #include <asm/sections.h> 50 51 51 52 #include "kernel.h" 52 - 53 - struct screen_info screen_info = { 54 - 0, 0, /* orig-x, orig-y */ 55 - 0, /* unused */ 56 - 0, /* orig-video-page */ 57 - 0, /* orig-video-mode */ 58 - 128, /* orig-video-cols */ 59 - 0,0,0, /* ega_ax, ega_bx, ega_cx */ 60 - 54, /* orig-video-lines */ 61 - 0, /* orig-video-isVGA */ 62 - 16 /* orig-video-points */ 63 - }; 64 53 65 54 /* Typing sync at the prom prompt calls the function pointed to by 66 55 * romvec->pv_synchook which I set to the following function.

-13

arch/sparc/kernel/setup_64.c

··· 15 15 #include <linux/ptrace.h> 16 16 #include <asm/smp.h> 17 17 #include <linux/user.h> 18 - #include <linux/screen_info.h> 19 18 #include <linux/delay.h> 20 19 #include <linux/fs.h> 21 20 #include <linux/seq_file.h> ··· 66 67 */ 67 68 DEFINE_SPINLOCK(ns87303_lock); 68 69 EXPORT_SYMBOL(ns87303_lock); 69 - 70 - struct screen_info screen_info = { 71 - 0, 0, /* orig-x, orig-y */ 72 - 0, /* unused */ 73 - 0, /* orig-video-page */ 74 - 0, /* orig-video-mode */ 75 - 128, /* orig-video-cols */ 76 - 0, 0, 0, /* unused, ega_bx, unused */ 77 - 54, /* orig-video-lines */ 78 - 0, /* orig-video-isVGA */ 79 - 16 /* orig-video-points */ 80 - }; 81 70 82 71 static void 83 72 prom_console_write(struct console *con, const char *s, unsigned int n)

+1 -1

arch/x86/kernel/setup.c

··· 1167 1167 #ifdef CONFIG_VT 1168 1168 #if defined(CONFIG_VGA_CONSOLE) 1169 1169 if (!efi_enabled(EFI_BOOT) || (efi_mem_type(0xa0000) != EFI_CONVENTIONAL_MEMORY)) 1170 - conswitchp = &vga_con; 1170 + vgacon_register_screen(&screen_info); 1171 1171 #endif 1172 1172 #endif 1173 1173 x86_init.oem.banner();

-12

arch/xtensa/kernel/setup.c

··· 19 19 #include <linux/init.h> 20 20 #include <linux/mm.h> 21 21 #include <linux/proc_fs.h> 22 - #include <linux/screen_info.h> 23 22 #include <linux/kernel.h> 24 23 #include <linux/percpu.h> 25 24 #include <linux/reboot.h> ··· 47 48 #include <asm/sysmem.h> 48 49 #include <asm/timex.h> 49 50 #include <asm/traps.h> 50 - 51 - #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE) 52 - struct screen_info screen_info = { 53 - .orig_x = 0, 54 - .orig_y = 24, 55 - .orig_video_cols = 80, 56 - .orig_video_lines = 24, 57 - .orig_video_isVGA = 1, 58 - .orig_video_points = 16, 59 - }; 60 - #endif 61 51 62 52 #ifdef CONFIG_BLK_DEV_INITRD 63 53 extern unsigned long initrd_start;

+13 -1

drivers/firmware/efi/efi-init.c

··· 55 55 56 56 extern __weak const efi_config_table_type_t efi_arch_tables[]; 57 57 58 + /* 59 + * x86 defines its own screen_info and uses it even without EFI, 60 + * everything else can get it from here. 61 + */ 62 + #if !defined(CONFIG_X86) && (defined(CONFIG_SYSFB) || defined(CONFIG_EFI_EARLYCON)) 63 + struct screen_info screen_info __section(".data"); 64 + EXPORT_SYMBOL_GPL(screen_info); 65 + #endif 66 + 58 67 static void __init init_screen_info(void) 59 68 { 60 69 struct screen_info *si; ··· 249 240 memblock_reserve(data.phys_map & PAGE_MASK, 250 241 PAGE_ALIGN(data.size + (data.phys_map & ~PAGE_MASK))); 251 242 252 - init_screen_info(); 243 + if (IS_ENABLED(CONFIG_X86) || 244 + IS_ENABLED(CONFIG_SYSFB) || 245 + IS_ENABLED(CONFIG_EFI_EARLYCON)) 246 + init_screen_info(); 253 247 }

+7 -1

drivers/firmware/efi/libstub/efi-stub-entry.c

··· 13 13 { 14 14 if (IS_ENABLED(CONFIG_ARM)) 15 15 return __alloc_screen_info(); 16 - return (void *)&screen_info + screen_info_offset; 16 + 17 + if (IS_ENABLED(CONFIG_X86) || 18 + IS_ENABLED(CONFIG_EFI_EARLYCON) || 19 + IS_ENABLED(CONFIG_SYSFB)) 20 + return (void *)&screen_info + screen_info_offset; 21 + 22 + return NULL; 17 23 } 18 24 19 25 /*

+4 -3

drivers/gpu/drm/hyperv/hyperv_drm_drv.c

··· 73 73 struct drm_device *dev = &hv->dev; 74 74 int ret; 75 75 76 - drm_aperture_remove_conflicting_framebuffers(screen_info.lfb_base, 77 - screen_info.lfb_size, 78 - &hyperv_driver); 76 + if (IS_ENABLED(CONFIG_SYSFB)) 77 + drm_aperture_remove_conflicting_framebuffers(screen_info.lfb_base, 78 + screen_info.lfb_size, 79 + &hyperv_driver); 79 80 80 81 hv->fb_size = (unsigned long)hv->mmio_megabytes * 1024 * 1024; 81 82

+4 -2

drivers/hv/vmbus_drv.c

··· 2100 2100 2101 2101 if (efi_enabled(EFI_BOOT)) { 2102 2102 /* Gen2 VM: get FB base from EFI framebuffer */ 2103 - start = screen_info.lfb_base; 2104 - size = max_t(__u32, screen_info.lfb_size, 0x800000); 2103 + if (IS_ENABLED(CONFIG_SYSFB)) { 2104 + start = screen_info.lfb_base; 2105 + size = max_t(__u32, screen_info.lfb_size, 0x800000); 2106 + } 2105 2107 } else { 2106 2108 /* Gen1 VM: get FB base from PCI */ 2107 2109 pdev = pci_get_device(PCI_VENDOR_ID_MICROSOFT,

+28 -11

drivers/tty/hvc/hvc_xen.c

··· 377 377 #ifdef CONFIG_HVC_XEN_FRONTEND 378 378 static void xencons_disconnect_backend(struct xencons_info *info) 379 379 { 380 - if (info->irq > 0) 381 - unbind_from_irqhandler(info->irq, NULL); 382 - info->irq = 0; 380 + if (info->hvc != NULL) 381 + hvc_remove(info->hvc); 382 + info->hvc = NULL; 383 + if (info->irq > 0) { 384 + evtchn_put(info->evtchn); 385 + info->irq = 0; 386 + info->evtchn = 0; 387 + } 388 + /* evtchn_put() will also close it so this is only an error path */ 383 389 if (info->evtchn > 0) 384 390 xenbus_free_evtchn(info->xbdev, info->evtchn); 385 391 info->evtchn = 0; 386 392 if (info->gntref > 0) 387 393 gnttab_free_grant_references(info->gntref); 388 394 info->gntref = 0; 389 - if (info->hvc != NULL) 390 - hvc_remove(info->hvc); 391 - info->hvc = NULL; 392 395 } 393 396 394 397 static void xencons_free(struct xencons_info *info) ··· 436 433 if (ret) 437 434 return ret; 438 435 info->evtchn = evtchn; 439 - irq = bind_interdomain_evtchn_to_irq_lateeoi(dev, evtchn); 436 + irq = bind_evtchn_to_irq_lateeoi(evtchn); 440 437 if (irq < 0) 441 438 return irq; 442 439 info->irq = irq; ··· 556 553 if (dev->state == XenbusStateClosed) 557 554 break; 558 555 fallthrough; /* Missed the backend's CLOSING state */ 559 - case XenbusStateClosing: 556 + case XenbusStateClosing: { 557 + struct xencons_info *info = dev_get_drvdata(&dev->dev);; 558 + 559 + /* 560 + * Don't tear down the evtchn and grant ref before the other 561 + * end has disconnected, but do stop userspace from trying 562 + * to use the device before we allow the backend to close. 563 + */ 564 + if (info->hvc) { 565 + hvc_remove(info->hvc); 566 + info->hvc = NULL; 567 + } 568 + 560 569 xenbus_frontend_closed(dev); 561 570 break; 571 + } 562 572 } 563 573 } 564 574 ··· 604 588 ops = &dom0_hvc_ops; 605 589 r = xen_initial_domain_console_init(); 606 590 if (r < 0) 607 - return r; 591 + goto register_fe; 608 592 info = vtermno_to_xencons(HVC_COOKIE); 609 593 } else { 610 594 ops = &domU_hvc_ops; ··· 613 597 else 614 598 r = xen_pv_console_init(); 615 599 if (r < 0) 616 - return r; 600 + goto register_fe; 617 601 618 602 info = vtermno_to_xencons(HVC_COOKIE); 619 603 info->irq = bind_evtchn_to_irq_lateeoi(info->evtchn); ··· 632 616 list_del(&info->list); 633 617 spin_unlock_irqrestore(&xencons_lock, flags); 634 618 if (info->irq) 635 - unbind_from_irqhandler(info->irq, NULL); 619 + evtchn_put(info->evtchn); 636 620 kfree(info); 637 621 return r; 638 622 } 639 623 640 624 r = 0; 625 + register_fe: 641 626 #ifdef CONFIG_HVC_XEN_FRONTEND 642 627 r = xenbus_register_frontend(&xencons_driver); 643 628 #endif

-2

drivers/tty/hvc/hvcs.c

··· 664 664 static void hvcs_destruct_port(struct tty_port *p) 665 665 { 666 666 struct hvcs_struct *hvcsd = container_of(p, struct hvcs_struct, port); 667 - struct vio_dev *vdev; 668 667 struct completion *comp; 669 668 unsigned long flags; 670 669 ··· 685 686 printk(KERN_INFO "HVCS: Destroyed hvcs_struct for vty-server@%X.\n", 686 687 hvcsd->vdev->unit_address); 687 688 688 - vdev = hvcsd->vdev; 689 689 hvcsd->vdev = NULL; 690 690 691 691 hvcsd->p_unit_address = 0;

+1 -1

drivers/tty/mxser.c

··· 288 288 enum mxser_must_hwid must_hwid; 289 289 speed_t max_baud; 290 290 291 - struct mxser_port ports[]; 291 + struct mxser_port ports[] __counted_by(nports); 292 292 }; 293 293 294 294 static DECLARE_BITMAP(mxser_boards, MXSER_BOARDS);

+3

drivers/tty/n_gsm.c

··· 2 2 /* 3 3 * n_gsm.c GSM 0710 tty multiplexor 4 4 * Copyright (c) 2009/10 Intel Corporation 5 + * Copyright (c) 2022/23 Siemens Mobility GmbH 5 6 * 6 7 * * THIS IS A DEVELOPMENT SNAPSHOT IT IS NOT A FINAL RELEASE * 7 8 * ··· 4109 4108 4110 4109 static int gsm_modem_update(struct gsm_dlci *dlci, u8 brk) 4111 4110 { 4111 + if (dlci->gsm->dead) 4112 + return -EL2HLT; 4112 4113 if (dlci->adaption == 2) { 4113 4114 /* Send convergence layer type 2 empty data frame. */ 4114 4115 gsm_modem_upd_via_data(dlci, brk);

+35 -40

drivers/tty/n_tty.c

··· 249 249 if (ldata->icanon && ldata->canon_head == ldata->read_tail) 250 250 return; 251 251 252 - while (1) { 253 - int throttled; 252 + do { 254 253 tty_set_flow_change(tty, TTY_THROTTLE_SAFE); 255 254 if (N_TTY_BUF_SIZE - read_cnt(ldata) >= TTY_THRESHOLD_THROTTLE) 256 255 break; 257 - throttled = tty_throttle_safe(tty); 258 - if (!throttled) 259 - break; 260 - } 256 + } while (!tty_throttle_safe(tty)); 257 + 261 258 __tty_set_flow_change(tty, 0); 262 259 } 263 260 ··· 276 279 * we won't get any more characters. 277 280 */ 278 281 279 - while (1) { 280 - int unthrottled; 282 + do { 281 283 tty_set_flow_change(tty, TTY_UNTHROTTLE_SAFE); 282 284 if (chars_in_buffer(tty) > TTY_THRESHOLD_UNTHROTTLE) 283 285 break; 286 + 284 287 n_tty_kick_worker(tty); 285 - unthrottled = tty_unthrottle_safe(tty); 286 - if (!unthrottled) 287 - break; 288 - } 288 + } while (!tty_unthrottle_safe(tty)); 289 + 289 290 __tty_set_flow_change(tty, 0); 290 291 } 291 292 ··· 1960 1965 size_t head = smp_load_acquire(&ldata->commit_head); 1961 1966 size_t tail = MASK(ldata->read_tail); 1962 1967 1963 - n = min(head - ldata->read_tail, N_TTY_BUF_SIZE - tail); 1964 - n = min(*nr, n); 1965 - if (n) { 1966 - u8 *from = read_buf_addr(ldata, tail); 1967 - memcpy(*kbp, from, n); 1968 - is_eof = n == 1 && *from == EOF_CHAR(tty); 1969 - tty_audit_add_data(tty, from, n); 1970 - zero_buffer(tty, from, n); 1971 - smp_store_release(&ldata->read_tail, ldata->read_tail + n); 1972 - /* Turn single EOF into zero-length read */ 1973 - if (L_EXTPROC(tty) && ldata->icanon && is_eof && 1974 - (head == ldata->read_tail)) 1975 - return false; 1976 - *kbp += n; 1977 - *nr -= n; 1968 + n = min3(head - ldata->read_tail, N_TTY_BUF_SIZE - tail, *nr); 1969 + if (!n) 1970 + return false; 1978 1971 1979 - /* If we have more to copy, let the caller know */ 1980 - return head != ldata->read_tail; 1981 - } 1982 - return false; 1972 + u8 *from = read_buf_addr(ldata, tail); 1973 + memcpy(*kbp, from, n); 1974 + is_eof = n == 1 && *from == EOF_CHAR(tty); 1975 + tty_audit_add_data(tty, from, n); 1976 + zero_buffer(tty, from, n); 1977 + smp_store_release(&ldata->read_tail, ldata->read_tail + n); 1978 + 1979 + /* Turn single EOF into zero-length read */ 1980 + if (L_EXTPROC(tty) && ldata->icanon && is_eof && 1981 + head == ldata->read_tail) 1982 + return false; 1983 + 1984 + *kbp += n; 1985 + *nr -= n; 1986 + 1987 + /* If we have more to copy, let the caller know */ 1988 + return head != ldata->read_tail; 1983 1989 } 1984 1990 1985 1991 /** ··· 2150 2154 struct n_tty_data *ldata = tty->disc_data; 2151 2155 u8 *kb = kbuf; 2152 2156 DEFINE_WAIT_FUNC(wait, woken_wake_function); 2153 - int c; 2154 2157 int minimum, time; 2155 - ssize_t retval = 0; 2158 + ssize_t retval; 2156 2159 long timeout; 2157 2160 bool packet; 2158 2161 size_t old_tail; ··· 2187 2192 return kb - kbuf; 2188 2193 } 2189 2194 2190 - c = job_control(tty, file); 2191 - if (c < 0) 2192 - return c; 2195 + retval = job_control(tty, file); 2196 + if (retval < 0) 2197 + return retval; 2193 2198 2194 2199 /* 2195 2200 * Internal serialization of reads. ··· 2494 2499 unsigned long arg) 2495 2500 { 2496 2501 struct n_tty_data *ldata = tty->disc_data; 2497 - int retval; 2502 + unsigned int num; 2498 2503 2499 2504 switch (cmd) { 2500 2505 case TIOCOUTQ: ··· 2502 2507 case TIOCINQ: 2503 2508 down_write(&tty->termios_rwsem); 2504 2509 if (L_ICANON(tty) && !L_EXTPROC(tty)) 2505 - retval = inq_canon(ldata); 2510 + num = inq_canon(ldata); 2506 2511 else 2507 - retval = read_cnt(ldata); 2512 + num = read_cnt(ldata); 2508 2513 up_write(&tty->termios_rwsem); 2509 - return put_user(retval, (unsigned int __user *) arg); 2514 + return put_user(num, (unsigned int __user *) arg); 2510 2515 default: 2511 2516 return n_tty_ioctl_helper(tty, cmd, arg); 2512 2517 }

+8 -16

drivers/tty/serdev/core.c

··· 15 15 #include <linux/of_device.h> 16 16 #include <linux/pm_domain.h> 17 17 #include <linux/pm_runtime.h> 18 + #include <linux/property.h> 18 19 #include <linux/sched.h> 19 20 #include <linux/serdev.h> 20 21 #include <linux/slab.h> 22 + 21 23 #include <linux/platform_data/x86/apple.h> 22 24 23 25 static bool is_registered; ··· 187 185 } 188 186 EXPORT_SYMBOL_GPL(serdev_device_close); 189 187 190 - static void devm_serdev_device_release(struct device *dev, void *dr) 188 + static void devm_serdev_device_close(void *serdev) 191 189 { 192 - serdev_device_close(*(struct serdev_device **)dr); 190 + serdev_device_close(serdev); 193 191 } 194 192 195 193 int devm_serdev_device_open(struct device *dev, struct serdev_device *serdev) 196 194 { 197 - struct serdev_device **dr; 198 195 int ret; 199 196 200 - dr = devres_alloc(devm_serdev_device_release, sizeof(*dr), GFP_KERNEL); 201 - if (!dr) 202 - return -ENOMEM; 203 - 204 197 ret = serdev_device_open(serdev); 205 - if (ret) { 206 - devres_free(dr); 198 + if (ret) 207 199 return ret; 208 - } 209 200 210 - *dr = serdev; 211 - devres_add(dev, dr); 212 - 213 - return 0; 201 + return devm_add_action_or_reset(dev, devm_serdev_device_close, serdev); 214 202 } 215 203 EXPORT_SYMBOL_GPL(devm_serdev_device_open); 216 204 ··· 502 510 ctrl->dev.type = &serdev_ctrl_type; 503 511 ctrl->dev.bus = &serdev_bus_type; 504 512 ctrl->dev.parent = parent; 505 - ctrl->dev.of_node = parent->of_node; 513 + device_set_node(&ctrl->dev, dev_fwnode(parent)); 506 514 serdev_controller_set_drvdata(ctrl, &ctrl[1]); 507 515 508 516 dev_set_name(&ctrl->dev, "serial%d", id); ··· 665 673 acpi_get_parent(adev->handle, &lookup.controller_handle); 666 674 667 675 /* Make sure controller and ResourceSource handle match */ 668 - if (ACPI_HANDLE(ctrl->dev.parent) != lookup.controller_handle) 676 + if (!device_match_acpi_handle(ctrl->dev.parent, lookup.controller_handle)) 669 677 return -ENODEV; 670 678 671 679 return 0;

+4 -4

drivers/tty/serial/21285.c

··· 185 185 unsigned long flags; 186 186 unsigned int h_lcr; 187 187 188 - spin_lock_irqsave(&port->lock, flags); 188 + uart_port_lock_irqsave(port, &flags); 189 189 h_lcr = *CSR_H_UBRLCR; 190 190 if (break_state) 191 191 h_lcr |= H_UBRLCR_BREAK; 192 192 else 193 193 h_lcr &= ~H_UBRLCR_BREAK; 194 194 *CSR_H_UBRLCR = h_lcr; 195 - spin_unlock_irqrestore(&port->lock, flags); 195 + uart_port_unlock_irqrestore(port, flags); 196 196 } 197 197 198 198 static int serial21285_startup(struct uart_port *port) ··· 272 272 if (port->fifosize) 273 273 h_lcr |= H_UBRLCR_FIFO; 274 274 275 - spin_lock_irqsave(&port->lock, flags); 275 + uart_port_lock_irqsave(port, &flags); 276 276 277 277 /* 278 278 * Update the per-port timeout. ··· 309 309 *CSR_H_UBRLCR = h_lcr; 310 310 *CSR_UARTCON = 1; 311 311 312 - spin_unlock_irqrestore(&port->lock, flags); 312 + uart_port_unlock_irqrestore(port, flags); 313 313 } 314 314 315 315 static const char *serial21285_type(struct uart_port *port)

+13 -20

drivers/tty/serial/8250/8250_aspeed_vuart.c

··· 34 34 35 35 struct aspeed_vuart { 36 36 struct device *dev; 37 - struct clk *clk; 38 37 int line; 39 38 struct timer_list unthrottle_timer; 40 39 struct uart_8250_port *port; ··· 287 288 struct uart_8250_port *up = up_to_u8250p(port); 288 289 unsigned long flags; 289 290 290 - spin_lock_irqsave(&port->lock, flags); 291 + uart_port_lock_irqsave(port, &flags); 291 292 __aspeed_vuart_set_throttle(up, throttle); 292 - spin_unlock_irqrestore(&port->lock, flags); 293 + uart_port_unlock_irqrestore(port, flags); 293 294 } 294 295 295 296 static void aspeed_vuart_throttle(struct uart_port *port) ··· 339 340 if (iir & UART_IIR_NO_INT) 340 341 return 0; 341 342 342 - spin_lock_irqsave(&port->lock, flags); 343 + uart_port_lock_irqsave(port, &flags); 343 344 344 345 lsr = serial_port_in(port, UART_LSR); 345 346 ··· 414 415 static int aspeed_vuart_probe(struct platform_device *pdev) 415 416 { 416 417 struct of_phandle_args sirq_polarity_sense_args; 418 + struct device *dev = &pdev->dev; 417 419 struct uart_8250_port port; 418 420 struct aspeed_vuart *vuart; 419 421 struct device_node *np; 420 422 struct resource *res; 421 423 u32 clk, prop, sirq[2]; 422 424 int rc, sirq_polarity; 425 + struct clk *vclk; 423 426 424 427 np = pdev->dev.of_node; 425 428 ··· 454 453 return rc; 455 454 456 455 if (of_property_read_u32(np, "clock-frequency", &clk)) { 457 - vuart->clk = devm_clk_get(&pdev->dev, NULL); 458 - if (IS_ERR(vuart->clk)) { 459 - dev_warn(&pdev->dev, 460 - "clk or clock-frequency not defined\n"); 461 - rc = PTR_ERR(vuart->clk); 456 + vclk = devm_clk_get_enabled(dev, NULL); 457 + if (IS_ERR(vclk)) { 458 + rc = dev_err_probe(dev, PTR_ERR(vclk), "clk or clock-frequency not defined\n"); 462 459 goto err_sysfs_remove; 463 460 } 464 461 465 - rc = clk_prepare_enable(vuart->clk); 466 - if (rc < 0) 467 - goto err_sysfs_remove; 468 - 469 - clk = clk_get_rate(vuart->clk); 462 + clk = clk_get_rate(vclk); 470 463 } 471 464 472 465 /* If current-speed was set, then try not to change it. */ ··· 528 533 529 534 rc = aspeed_vuart_set_lpc_address(vuart, prop); 530 535 if (rc < 0) { 531 - dev_err(&pdev->dev, "invalid value in aspeed,lpc-io-reg property\n"); 536 + dev_err_probe(dev, rc, "invalid value in aspeed,lpc-io-reg property\n"); 532 537 goto err_clk_disable; 533 538 } 534 539 ··· 540 545 541 546 rc = aspeed_vuart_set_sirq(vuart, sirq[0]); 542 547 if (rc < 0) { 543 - dev_err(&pdev->dev, "invalid sirq number in aspeed,lpc-interrupts property\n"); 548 + dev_err_probe(dev, rc, "invalid sirq number in aspeed,lpc-interrupts property\n"); 544 549 goto err_clk_disable; 545 550 } 546 551 547 552 sirq_polarity = aspeed_vuart_map_irq_polarity(sirq[1]); 548 553 if (sirq_polarity < 0) { 549 - dev_err(&pdev->dev, "invalid sirq polarity in aspeed,lpc-interrupts property\n"); 550 - rc = sirq_polarity; 554 + rc = dev_err_probe(dev, sirq_polarity, 555 + "invalid sirq polarity in aspeed,lpc-interrupts property\n"); 551 556 goto err_clk_disable; 552 557 } 553 558 ··· 560 565 return 0; 561 566 562 567 err_clk_disable: 563 - clk_disable_unprepare(vuart->clk); 564 568 irq_dispose_mapping(port.port.irq); 565 569 err_sysfs_remove: 566 570 sysfs_remove_group(&vuart->dev->kobj, &aspeed_vuart_attr_group); ··· 574 580 aspeed_vuart_set_enabled(vuart, false); 575 581 serial8250_unregister_port(vuart->line); 576 582 sysfs_remove_group(&vuart->dev->kobj, &aspeed_vuart_attr_group); 577 - clk_disable_unprepare(vuart->clk); 578 583 579 584 return 0; 580 585 }

+30 -39

drivers/tty/serial/8250/8250_bcm7271.c

··· 567 567 if (interrupts == 0) 568 568 return IRQ_NONE; 569 569 570 - spin_lock_irqsave(&up->lock, flags); 570 + uart_port_lock_irqsave(up, &flags); 571 571 572 572 /* Clear all interrupts */ 573 573 udma_writel(priv, REGS_DMA_ISR, UDMA_INTR_CLEAR, interrupts); ··· 581 581 if ((rval | tval) == 0) 582 582 dev_warn(dev, "Spurious interrupt: 0x%x\n", interrupts); 583 583 584 - spin_unlock_irqrestore(&up->lock, flags); 584 + uart_port_unlock_irqrestore(up, flags); 585 585 return IRQ_HANDLED; 586 586 } 587 587 ··· 608 608 * 609 609 * Synchronize UART_IER access against the console. 610 610 */ 611 - spin_lock_irq(&port->lock); 611 + uart_port_lock_irq(port); 612 612 up->ier &= ~UART_IER_RDI; 613 613 serial_port_out(port, UART_IER, up->ier); 614 - spin_unlock_irq(&port->lock); 614 + uart_port_unlock_irq(port); 615 615 616 616 priv->tx_running = false; 617 617 priv->dma.rx_dma = NULL; ··· 629 629 struct brcmuart_priv *priv = up->port.private_data; 630 630 unsigned long flags; 631 631 632 - spin_lock_irqsave(&port->lock, flags); 632 + uart_port_lock_irqsave(port, &flags); 633 633 priv->shutdown = true; 634 634 if (priv->dma_enabled) { 635 635 stop_rx_dma(up); ··· 645 645 */ 646 646 up->dma = NULL; 647 647 648 - spin_unlock_irqrestore(&port->lock, flags); 648 + uart_port_unlock_irqrestore(port, flags); 649 649 serial8250_do_shutdown(port); 650 650 } 651 651 ··· 788 788 * interrupt but there is no data ready. 789 789 */ 790 790 if (((iir & UART_IIR_ID) == UART_IIR_RX_TIMEOUT) && !(priv->shutdown)) { 791 - spin_lock_irqsave(&p->lock, flags); 791 + uart_port_lock_irqsave(p, &flags); 792 792 status = serial_port_in(p, UART_LSR); 793 793 if ((status & UART_LSR_DR) == 0) { 794 794 ··· 813 813 814 814 handled = 1; 815 815 } 816 - spin_unlock_irqrestore(&p->lock, flags); 816 + uart_port_unlock_irqrestore(p, flags); 817 817 if (handled) 818 818 return 1; 819 819 } ··· 831 831 if (priv->shutdown) 832 832 return HRTIMER_NORESTART; 833 833 834 - spin_lock_irqsave(&p->lock, flags); 834 + uart_port_lock_irqsave(p, &flags); 835 835 status = serial_port_in(p, UART_LSR); 836 836 837 837 /* ··· 855 855 status |= UART_MCR_RTS; 856 856 serial_port_out(p, UART_MCR, status); 857 857 } 858 - spin_unlock_irqrestore(&p->lock, flags); 858 + uart_port_unlock_irqrestore(p, flags); 859 859 return HRTIMER_NORESTART; 860 860 } 861 861 ··· 984 984 } 985 985 986 986 /* We should have just the uart base registers or all the registers */ 987 - if (x != 1 && x != REGS_MAX) { 988 - dev_warn(dev, "%s registers not specified\n", reg_names[x]); 989 - return -EINVAL; 990 - } 987 + if (x != 1 && x != REGS_MAX) 988 + return dev_err_probe(dev, -EINVAL, "%s registers not specified\n", 989 + reg_names[x]); 991 990 992 991 /* if the DMA registers were specified, try to enable DMA */ 993 992 if (x > REGS_DMA_RX) { ··· 1015 1016 of_property_read_u32(np, "clock-frequency", &clk_rate); 1016 1017 1017 1018 /* See if a Baud clock has been specified */ 1018 - baud_mux_clk = devm_clk_get(dev, "sw_baud"); 1019 - if (IS_ERR(baud_mux_clk)) { 1020 - if (PTR_ERR(baud_mux_clk) == -EPROBE_DEFER) { 1021 - ret = -EPROBE_DEFER; 1022 - goto release_dma; 1023 - } 1024 - dev_dbg(dev, "BAUD MUX clock not specified\n"); 1025 - } else { 1019 + baud_mux_clk = devm_clk_get_optional_enabled(dev, "sw_baud"); 1020 + ret = PTR_ERR_OR_ZERO(baud_mux_clk); 1021 + if (ret) 1022 + goto release_dma; 1023 + if (baud_mux_clk) { 1026 1024 dev_dbg(dev, "BAUD MUX clock found\n"); 1027 - ret = clk_prepare_enable(baud_mux_clk); 1028 - if (ret) 1029 - goto release_dma; 1025 + 1030 1026 priv->baud_mux_clk = baud_mux_clk; 1031 1027 init_real_clk_rates(dev, priv); 1032 1028 clk_rate = priv->default_mux_rate; 1029 + } else { 1030 + dev_dbg(dev, "BAUD MUX clock not specified\n"); 1033 1031 } 1034 1032 1035 1033 if (clk_rate == 0) { 1036 - dev_err(dev, "clock-frequency or clk not defined\n"); 1037 - ret = -EINVAL; 1038 - goto err_clk_disable; 1034 + ret = dev_err_probe(dev, -EINVAL, "clock-frequency or clk not defined\n"); 1035 + goto release_dma; 1039 1036 } 1040 1037 1041 1038 dev_dbg(dev, "DMA is %senabled\n", priv->dma_enabled ? "" : "not "); ··· 1088 1093 1089 1094 ret = serial8250_register_8250_port(&up); 1090 1095 if (ret < 0) { 1091 - dev_err(dev, "unable to register 8250 port\n"); 1096 + dev_err_probe(dev, ret, "unable to register 8250 port\n"); 1092 1097 goto err; 1093 1098 } 1094 1099 priv->line = ret; ··· 1097 1102 if (priv->dma_enabled) { 1098 1103 dma_irq = platform_get_irq_byname(pdev, "dma"); 1099 1104 if (dma_irq < 0) { 1100 - ret = dma_irq; 1101 - dev_err(dev, "no IRQ resource info\n"); 1105 + ret = dev_err_probe(dev, dma_irq, "no IRQ resource info\n"); 1102 1106 goto err1; 1103 1107 } 1104 1108 ret = devm_request_irq(dev, dma_irq, brcmuart_isr, 1105 1109 IRQF_SHARED, "uart DMA irq", &new_port->port); 1106 1110 if (ret) { 1107 - dev_err(dev, "unable to register IRQ handler\n"); 1111 + dev_err_probe(dev, ret, "unable to register IRQ handler\n"); 1108 1112 goto err1; 1109 1113 } 1110 1114 } ··· 1115 1121 serial8250_unregister_port(priv->line); 1116 1122 err: 1117 1123 brcmuart_free_bufs(dev, priv); 1118 - err_clk_disable: 1119 - clk_disable_unprepare(baud_mux_clk); 1120 1124 release_dma: 1121 1125 if (priv->dma_enabled) 1122 1126 brcmuart_arbitration(priv, 0); ··· 1129 1137 hrtimer_cancel(&priv->hrt); 1130 1138 serial8250_unregister_port(priv->line); 1131 1139 brcmuart_free_bufs(&pdev->dev, priv); 1132 - clk_disable_unprepare(priv->baud_mux_clk); 1133 1140 if (priv->dma_enabled) 1134 1141 brcmuart_arbitration(priv, 0); 1135 1142 return 0; ··· 1145 1154 * This will prevent resume from enabling RTS before the 1146 1155 * baud rate has been restored. 1147 1156 */ 1148 - spin_lock_irqsave(&port->lock, flags); 1157 + uart_port_lock_irqsave(port, &flags); 1149 1158 priv->saved_mctrl = port->mctrl; 1150 1159 port->mctrl &= ~TIOCM_RTS; 1151 - spin_unlock_irqrestore(&port->lock, flags); 1160 + uart_port_unlock_irqrestore(port, flags); 1152 1161 1153 1162 serial8250_suspend_port(priv->line); 1154 1163 clk_disable_unprepare(priv->baud_mux_clk); ··· 1187 1196 1188 1197 if (priv->saved_mctrl & TIOCM_RTS) { 1189 1198 /* Restore RTS */ 1190 - spin_lock_irqsave(&port->lock, flags); 1199 + uart_port_lock_irqsave(port, &flags); 1191 1200 port->mctrl |= TIOCM_RTS; 1192 1201 port->ops->set_mctrl(port, port->mctrl); 1193 - spin_unlock_irqrestore(&port->lock, flags); 1202 + uart_port_unlock_irqrestore(port, flags); 1194 1203 } 1195 1204 1196 1205 return 0;

+7 -7

drivers/tty/serial/8250/8250_core.c

··· 259 259 unsigned int iir, ier = 0, lsr; 260 260 unsigned long flags; 261 261 262 - spin_lock_irqsave(&up->port.lock, flags); 262 + uart_port_lock_irqsave(&up->port, &flags); 263 263 264 264 /* 265 265 * Must disable interrupts or else we risk racing with the interrupt ··· 292 292 if (up->port.irq) 293 293 serial_out(up, UART_IER, ier); 294 294 295 - spin_unlock_irqrestore(&up->port.lock, flags); 295 + uart_port_unlock_irqrestore(&up->port, flags); 296 296 297 297 /* Standard timer interval plus 0.2s to keep the port running */ 298 298 mod_timer(&up->timer, ··· 611 611 * if so, search for the first available port that does have 612 612 * console support. 613 613 */ 614 - if (co->index >= UART_NR) 614 + if (co->index < 0 || co->index >= UART_NR) 615 615 co->index = 0; 616 616 617 617 /* ··· 992 992 struct uart_port *port = &up->port; 993 993 unsigned long flags; 994 994 995 - spin_lock_irqsave(&port->lock, flags); 995 + uart_port_lock_irqsave(port, &flags); 996 996 up->ier |= UART_IER_RLSI | UART_IER_RDI; 997 997 up->port.read_status_mask |= UART_LSR_DR; 998 998 serial_out(up, UART_IER, up->ier); 999 - spin_unlock_irqrestore(&port->lock, flags); 999 + uart_port_unlock_irqrestore(port, flags); 1000 1000 } 1001 1001 1002 1002 /** ··· 1194 1194 if (uart->em485) { 1195 1195 unsigned long flags; 1196 1196 1197 - spin_lock_irqsave(&uart->port.lock, flags); 1197 + uart_port_lock_irqsave(&uart->port, &flags); 1198 1198 serial8250_em485_destroy(uart); 1199 - spin_unlock_irqrestore(&uart->port.lock, flags); 1199 + uart_port_unlock_irqrestore(&uart->port, flags); 1200 1200 } 1201 1201 1202 1202 uart_remove_one_port(&serial8250_reg, &uart->port);

+4 -4

drivers/tty/serial/8250/8250_dma.c

··· 22 22 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr, 23 23 UART_XMIT_SIZE, DMA_TO_DEVICE); 24 24 25 - spin_lock_irqsave(&p->port.lock, flags); 25 + uart_port_lock_irqsave(&p->port, &flags); 26 26 27 27 dma->tx_running = 0; 28 28 ··· 35 35 if (ret || !dma->tx_running) 36 36 serial8250_set_THRI(p); 37 37 38 - spin_unlock_irqrestore(&p->port.lock, flags); 38 + uart_port_unlock_irqrestore(&p->port, flags); 39 39 } 40 40 41 41 static void __dma_rx_complete(struct uart_8250_port *p) ··· 70 70 struct uart_8250_dma *dma = p->dma; 71 71 unsigned long flags; 72 72 73 - spin_lock_irqsave(&p->port.lock, flags); 73 + uart_port_lock_irqsave(&p->port, &flags); 74 74 if (dma->rx_running) 75 75 __dma_rx_complete(p); 76 76 ··· 80 80 */ 81 81 if (!dma->rx_running && (serial_lsr_in(p) & UART_LSR_DR)) 82 82 p->dma->rx_dma(p); 83 - spin_unlock_irqrestore(&p->port.lock, flags); 83 + uart_port_unlock_irqrestore(&p->port, flags); 84 84 } 85 85 86 86 int serial8250_tx_dma(struct uart_8250_port *p)

+7 -28

drivers/tty/serial/8250/8250_dw.c

··· 263 263 * so we limit the workaround only to non-DMA mode. 264 264 */ 265 265 if (!up->dma && rx_timeout) { 266 - spin_lock_irqsave(&p->lock, flags); 266 + uart_port_lock_irqsave(p, &flags); 267 267 status = serial_lsr_in(up); 268 268 269 269 if (!(status & (UART_LSR_DR | UART_LSR_BI))) 270 270 (void) p->serial_in(p, UART_RX); 271 271 272 - spin_unlock_irqrestore(&p->lock, flags); 272 + uart_port_unlock_irqrestore(p, flags); 273 273 } 274 274 275 275 /* Manually stop the Rx DMA transfer when acting as flow controller */ 276 276 if (quirks & DW_UART_QUIRK_IS_DMA_FC && up->dma && up->dma->rx_running && rx_timeout) { 277 - spin_lock_irqsave(&p->lock, flags); 277 + uart_port_lock_irqsave(p, &flags); 278 278 status = serial_lsr_in(up); 279 - spin_unlock_irqrestore(&p->lock, flags); 279 + uart_port_unlock_irqrestore(p, flags); 280 280 281 281 if (status & (UART_LSR_DR | UART_LSR_BI)) { 282 282 dw8250_writel_ext(p, RZN1_UART_RDMACR, 0); ··· 498 498 } 499 499 } 500 500 501 - static void dw8250_clk_disable_unprepare(void *data) 502 - { 503 - clk_disable_unprepare(data); 504 - } 505 - 506 501 static void dw8250_reset_control_assert(void *data) 507 502 { 508 503 reset_control_assert(data); ··· 593 598 device_property_read_u32(dev, "clock-frequency", &p->uartclk); 594 599 595 600 /* If there is separate baudclk, get the rate from it. */ 596 - data->clk = devm_clk_get_optional(dev, "baudclk"); 601 + data->clk = devm_clk_get_optional_enabled(dev, "baudclk"); 597 602 if (data->clk == NULL) 598 - data->clk = devm_clk_get_optional(dev, NULL); 603 + data->clk = devm_clk_get_optional_enabled(dev, NULL); 599 604 if (IS_ERR(data->clk)) 600 605 return PTR_ERR(data->clk); 601 606 602 607 INIT_WORK(&data->clk_work, dw8250_clk_work_cb); 603 608 data->clk_notifier.notifier_call = dw8250_clk_notifier_cb; 604 - 605 - err = clk_prepare_enable(data->clk); 606 - if (err) 607 - return dev_err_probe(dev, err, "could not enable optional baudclk\n"); 608 - 609 - err = devm_add_action_or_reset(dev, dw8250_clk_disable_unprepare, data->clk); 610 - if (err) 611 - return err; 612 609 613 610 if (data->clk) 614 611 p->uartclk = clk_get_rate(data->clk); ··· 609 622 if (!p->uartclk) 610 623 return dev_err_probe(dev, -EINVAL, "clock rate not defined\n"); 611 624 612 - data->pclk = devm_clk_get_optional(dev, "apb_pclk"); 625 + data->pclk = devm_clk_get_optional_enabled(dev, "apb_pclk"); 613 626 if (IS_ERR(data->pclk)) 614 627 return PTR_ERR(data->pclk); 615 - 616 - err = clk_prepare_enable(data->pclk); 617 - if (err) 618 - return dev_err_probe(dev, err, "could not enable apb_pclk\n"); 619 - 620 - err = devm_add_action_or_reset(dev, dw8250_clk_disable_unprepare, data->pclk); 621 - if (err) 622 - return err; 623 628 624 629 data->rst = devm_reset_control_get_optional_exclusive(dev, NULL); 625 630 if (IS_ERR(data->rst))

+46 -17

drivers/tty/serial/8250/8250_exar.c

··· 18 18 #include <linux/slab.h> 19 19 #include <linux/string.h> 20 20 #include <linux/tty.h> 21 - #include <linux/8250_pci.h> 22 21 #include <linux/delay.h> 23 22 24 23 #include <asm/byteorder.h> ··· 45 46 46 47 #define PCI_SUBDEVICE_ID_USR_2980 0x0128 47 48 #define PCI_SUBDEVICE_ID_USR_2981 0x0129 48 - 49 - #define PCI_DEVICE_ID_SEALEVEL_710xC 0x1001 50 - #define PCI_DEVICE_ID_SEALEVEL_720xC 0x1002 51 - #define PCI_DEVICE_ID_SEALEVEL_740xC 0x1004 52 - #define PCI_DEVICE_ID_SEALEVEL_780xC 0x1008 53 - #define PCI_DEVICE_ID_SEALEVEL_716xC 0x1010 54 49 55 50 #define UART_EXAR_INT0 0x80 56 51 #define UART_EXAR_8XMODE 0x88 /* 8X sampling rate select */ ··· 76 83 #define UART_EXAR_MPIOOD_15_8 0x9a /* MPIOOD[15:8] */ 77 84 78 85 #define UART_EXAR_RS485_DLY(x) ((x) << 4) 86 + 87 + #define UART_EXAR_DLD 0x02 /* Divisor Fractional */ 88 + #define UART_EXAR_DLD_485_POLARITY 0x80 /* RS-485 Enable Signal Polarity */ 79 89 80 90 /* 81 91 * IOT2040 MPIO wiring semantics: ··· 197 201 * 198 202 * Synchronize UART_IER access against the console. 199 203 */ 200 - spin_lock_irq(&port->lock); 204 + uart_port_lock_irq(port); 201 205 serial_port_out(port, UART_IER, 0); 202 - spin_unlock_irq(&port->lock); 206 + uart_port_unlock_irq(port); 203 207 204 208 return serial8250_do_startup(port); 205 209 } ··· 441 445 return 0; 442 446 } 443 447 448 + static int sealevel_rs485_config(struct uart_port *port, struct ktermios *termios, 449 + struct serial_rs485 *rs485) 450 + { 451 + u8 __iomem *p = port->membase; 452 + u8 old_lcr; 453 + u8 efr; 454 + u8 dld; 455 + int ret; 456 + 457 + ret = generic_rs485_config(port, termios, rs485); 458 + if (ret) 459 + return ret; 460 + 461 + if (rs485->flags & SER_RS485_ENABLED) { 462 + old_lcr = readb(p + UART_LCR); 463 + 464 + /* Set EFR[4]=1 to enable enhanced feature registers */ 465 + efr = readb(p + UART_XR_EFR); 466 + efr |= UART_EFR_ECB; 467 + writeb(efr, p + UART_XR_EFR); 468 + 469 + /* Set MCR to use DTR as Auto-RS485 Enable signal */ 470 + writeb(UART_MCR_OUT1, p + UART_MCR); 471 + 472 + /* Set LCR[7]=1 to enable access to DLD register */ 473 + writeb(old_lcr | UART_LCR_DLAB, p + UART_LCR); 474 + 475 + /* Set DLD[7]=1 for inverted RS485 Enable logic */ 476 + dld = readb(p + UART_EXAR_DLD); 477 + dld |= UART_EXAR_DLD_485_POLARITY; 478 + writeb(dld, p + UART_EXAR_DLD); 479 + 480 + writeb(old_lcr, p + UART_LCR); 481 + } 482 + 483 + return 0; 484 + } 485 + 444 486 static const struct serial_rs485 generic_rs485_supported = { 445 487 .flags = SER_RS485_ENABLED, 446 488 }; ··· 600 566 port->port.rs485_config = platform->rs485_config; 601 567 port->port.rs485_supported = *(platform->rs485_supported); 602 568 569 + if (pcidev->subsystem_vendor == PCI_VENDOR_ID_SEALEVEL) 570 + port->port.rs485_config = sealevel_rs485_config; 571 + 603 572 /* 604 573 * Setup the UART clock for the devices on expansion slot to 605 574 * half the clock speed of the main chip (which is 125MHz) ··· 689 652 nr_ports = BIT(((pcidev->device & 0x38) >> 3) - 1); 690 653 else if (board->num_ports) 691 654 nr_ports = board->num_ports; 692 - else if (pcidev->vendor == PCI_VENDOR_ID_SEALEVEL) 693 - nr_ports = pcidev->device & 0xff; 694 655 else 695 656 nr_ports = pcidev->device & 0x0f; 696 657 ··· 928 893 EXAR_DEVICE(COMMTECH, 4224PCI335, pbn_fastcom335_4), 929 894 EXAR_DEVICE(COMMTECH, 2324PCI335, pbn_fastcom335_4), 930 895 EXAR_DEVICE(COMMTECH, 2328PCI335, pbn_fastcom335_8), 931 - 932 - EXAR_DEVICE(SEALEVEL, 710xC, pbn_exar_XR17V35x), 933 - EXAR_DEVICE(SEALEVEL, 720xC, pbn_exar_XR17V35x), 934 - EXAR_DEVICE(SEALEVEL, 740xC, pbn_exar_XR17V35x), 935 - EXAR_DEVICE(SEALEVEL, 780xC, pbn_exar_XR17V35x), 936 - EXAR_DEVICE(SEALEVEL, 716xC, pbn_exar_XR17V35x), 937 896 { 0, } 938 897 }; 939 898 MODULE_DEVICE_TABLE(pci, exar_pci_tbl);

+3 -3

drivers/tty/serial/8250/8250_fsl.c

··· 30 30 unsigned int iir; 31 31 struct uart_8250_port *up = up_to_u8250p(port); 32 32 33 - spin_lock_irqsave(&up->port.lock, flags); 33 + uart_port_lock_irqsave(&up->port, &flags); 34 34 35 35 iir = port->serial_in(port, UART_IIR); 36 36 if (iir & UART_IIR_NO_INT) { 37 - spin_unlock_irqrestore(&up->port.lock, flags); 37 + uart_port_unlock_irqrestore(&up->port, flags); 38 38 return 0; 39 39 } 40 40 ··· 54 54 if (unlikely(up->lsr_saved_flags & UART_LSR_BI)) { 55 55 up->lsr_saved_flags &= ~UART_LSR_BI; 56 56 port->serial_in(port, UART_RX); 57 - spin_unlock_irqrestore(&up->port.lock, flags); 57 + uart_port_unlock_irqrestore(&up->port, flags); 58 58 return 1; 59 59 } 60 60

+7 -11

drivers/tty/serial/8250/8250_mid.c

··· 12 12 #include <linux/rational.h> 13 13 14 14 #include <linux/dma/hsu.h> 15 - #include <linux/8250_pci.h> 16 15 17 16 #include "8250.h" 18 17 ··· 31 32 struct mid8250; 32 33 33 34 struct mid8250_board { 34 - unsigned int flags; 35 35 unsigned long freq; 36 36 unsigned int base_baud; 37 + unsigned int bar; 37 38 int (*setup)(struct mid8250 *, struct uart_port *p); 38 39 void (*exit)(struct mid8250 *); 39 40 }; ··· 168 169 { 169 170 struct hsu_dma_chip *chip = &mid->dma_chip; 170 171 struct pci_dev *pdev = to_pci_dev(p->dev); 171 - unsigned int bar = FL_GET_BASE(mid->board->flags); 172 172 int ret; 173 173 174 174 pci_set_master(pdev); ··· 181 183 chip->dev = &pdev->dev; 182 184 chip->irq = pci_irq_vector(pdev, 0); 183 185 chip->regs = p->membase; 184 - chip->length = pci_resource_len(pdev, bar); 186 + chip->length = pci_resource_len(pdev, mid->board->bar); 185 187 chip->offset = DNV_DMA_CHAN_OFFSET; 186 188 187 189 /* Falling back to PIO mode if DMA probing fails */ ··· 289 291 { 290 292 struct uart_8250_port uart; 291 293 struct mid8250 *mid; 292 - unsigned int bar; 293 294 int ret; 294 295 295 296 ret = pcim_enable_device(pdev); ··· 300 303 return -ENOMEM; 301 304 302 305 mid->board = (struct mid8250_board *)id->driver_data; 303 - bar = FL_GET_BASE(mid->board->flags); 304 306 305 307 memset(&uart, 0, sizeof(struct uart_8250_port)); 306 308 ··· 312 316 uart.port.flags = UPF_SHARE_IRQ | UPF_FIXED_PORT | UPF_FIXED_TYPE; 313 317 uart.port.set_termios = mid8250_set_termios; 314 318 315 - uart.port.mapbase = pci_resource_start(pdev, bar); 316 - uart.port.membase = pcim_iomap(pdev, bar, 0); 319 + uart.port.mapbase = pci_resource_start(pdev, mid->board->bar); 320 + uart.port.membase = pcim_iomap(pdev, mid->board->bar, 0); 317 321 if (!uart.port.membase) 318 322 return -ENOMEM; 319 323 ··· 349 353 } 350 354 351 355 static const struct mid8250_board pnw_board = { 352 - .flags = FL_BASE0, 353 356 .freq = 50000000, 354 357 .base_baud = 115200, 358 + .bar = 0, 355 359 .setup = pnw_setup, 356 360 .exit = pnw_exit, 357 361 }; 358 362 359 363 static const struct mid8250_board tng_board = { 360 - .flags = FL_BASE0, 361 364 .freq = 38400000, 362 365 .base_baud = 1843200, 366 + .bar = 0, 363 367 .setup = tng_setup, 364 368 .exit = tng_exit, 365 369 }; 366 370 367 371 static const struct mid8250_board dnv_board = { 368 - .flags = FL_BASE1, 369 372 .freq = 133333333, 370 373 .base_baud = 115200, 374 + .bar = 1, 371 375 .setup = dnv_setup, 372 376 .exit = dnv_exit, 373 377 };

+4 -4

drivers/tty/serial/8250/8250_mtk.c

··· 102 102 if (data->rx_status == DMA_RX_SHUTDOWN) 103 103 return; 104 104 105 - spin_lock_irqsave(&up->port.lock, flags); 105 + uart_port_lock_irqsave(&up->port, &flags); 106 106 107 107 dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state); 108 108 total = dma->rx_size - state.residue; ··· 128 128 129 129 mtk8250_rx_dma(up); 130 130 131 - spin_unlock_irqrestore(&up->port.lock, flags); 131 + uart_port_unlock_irqrestore(&up->port, flags); 132 132 } 133 133 134 134 static void mtk8250_rx_dma(struct uart_8250_port *up) ··· 368 368 * Ok, we're now changing the port state. Do it with 369 369 * interrupts disabled. 370 370 */ 371 - spin_lock_irqsave(&port->lock, flags); 371 + uart_port_lock_irqsave(port, &flags); 372 372 373 373 /* 374 374 * Update the per-port timeout. ··· 416 416 if (uart_console(port)) 417 417 up->port.cons->cflag = termios->c_cflag; 418 418 419 - spin_unlock_irqrestore(&port->lock, flags); 419 + uart_port_unlock_irqrestore(port, flags); 420 420 /* Don't rewrite B0 */ 421 421 if (tty_termios_baud_rate(termios)) 422 422 tty_termios_encode_baud_rate(termios, baud, baud);

+16 -28

drivers/tty/serial/8250/8250_of.c

··· 33 33 struct of_serial_info *info) 34 34 { 35 35 struct resource resource; 36 - struct device_node *np = ofdev->dev.of_node; 36 + struct device *dev = &ofdev->dev; 37 + struct device_node *np = dev->of_node; 37 38 struct uart_port *port = &up->port; 38 39 u32 clk, spd, prop; 39 40 int ret, irq; ··· 47 46 if (of_property_read_u32(np, "clock-frequency", &clk)) { 48 47 49 48 /* Get clk rate through clk driver if present */ 50 - info->clk = devm_clk_get(&ofdev->dev, NULL); 49 + info->clk = devm_clk_get_enabled(dev, NULL); 51 50 if (IS_ERR(info->clk)) { 52 - ret = PTR_ERR(info->clk); 53 - if (ret != -EPROBE_DEFER) 54 - dev_warn(&ofdev->dev, 55 - "failed to get clock: %d\n", ret); 51 + ret = dev_err_probe(dev, PTR_ERR(info->clk), "failed to get clock\n"); 56 52 goto err_pmruntime; 57 53 } 58 - 59 - ret = clk_prepare_enable(info->clk); 60 - if (ret < 0) 61 - goto err_pmruntime; 62 54 63 55 clk = clk_get_rate(info->clk); 64 56 } ··· 61 67 62 68 ret = of_address_to_resource(np, 0, &resource); 63 69 if (ret) { 64 - dev_warn(&ofdev->dev, "invalid address\n"); 65 - goto err_unprepare; 70 + dev_err_probe(dev, ret, "invalid address\n"); 71 + goto err_pmruntime; 66 72 } 67 73 68 74 port->flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT | ··· 79 85 /* Check for shifted address mapping */ 80 86 if (of_property_read_u32(np, "reg-offset", &prop) == 0) { 81 87 if (prop >= port->mapsize) { 82 - dev_warn(&ofdev->dev, "reg-offset %u exceeds region size %pa\n", 83 - prop, &port->mapsize); 84 - ret = -EINVAL; 85 - goto err_unprepare; 88 + ret = dev_err_probe(dev, -EINVAL, "reg-offset %u exceeds region size %pa\n", 89 + prop, &port->mapsize); 90 + goto err_pmruntime; 86 91 } 87 92 88 93 port->mapbase += prop; ··· 102 109 UPIO_MEM32BE : UPIO_MEM32; 103 110 break; 104 111 default: 105 - dev_warn(&ofdev->dev, "unsupported reg-io-width (%d)\n", 106 - prop); 107 - ret = -EINVAL; 108 - goto err_unprepare; 112 + ret = dev_err_probe(dev, -EINVAL, "unsupported reg-io-width (%u)\n", 113 + prop); 114 + goto err_pmruntime; 109 115 } 110 116 } 111 117 port->flags |= UPF_IOREMAP; ··· 131 139 if (irq < 0) { 132 140 if (irq == -EPROBE_DEFER) { 133 141 ret = -EPROBE_DEFER; 134 - goto err_unprepare; 142 + goto err_pmruntime; 135 143 } 136 144 /* IRQ support not mandatory */ 137 145 irq = 0; ··· 142 150 info->rst = devm_reset_control_get_optional_shared(&ofdev->dev, NULL); 143 151 if (IS_ERR(info->rst)) { 144 152 ret = PTR_ERR(info->rst); 145 - goto err_unprepare; 153 + goto err_pmruntime; 146 154 } 147 155 148 156 ret = reset_control_deassert(info->rst); 149 157 if (ret) 150 - goto err_unprepare; 158 + goto err_pmruntime; 151 159 152 160 port->type = type; 153 161 port->uartclk = clk; ··· 165 173 case PORT_RT2880: 166 174 ret = rt288x_setup(port); 167 175 if (ret) 168 - goto err_unprepare; 176 + goto err_pmruntime; 169 177 break; 170 178 } 171 179 ··· 177 185 } 178 186 179 187 return 0; 180 - err_unprepare: 181 - clk_disable_unprepare(info->clk); 182 188 err_pmruntime: 183 189 pm_runtime_put_sync(&ofdev->dev); 184 190 pm_runtime_disable(&ofdev->dev); ··· 243 253 irq_dispose_mapping(port8250.port.irq); 244 254 pm_runtime_put_sync(&ofdev->dev); 245 255 pm_runtime_disable(&ofdev->dev); 246 - clk_disable_unprepare(info->clk); 247 256 err_free: 248 257 kfree(info); 249 258 return ret; ··· 260 271 reset_control_assert(info->rst); 261 272 pm_runtime_put_sync(&ofdev->dev); 262 273 pm_runtime_disable(&ofdev->dev); 263 - clk_disable_unprepare(info->clk); 264 274 kfree(info); 265 275 return 0; 266 276 }

+75 -39

drivers/tty/serial/8250/8250_omap.c

··· 8 8 * 9 9 */ 10 10 11 + #include <linux/atomic.h> 11 12 #include <linux/clk.h> 12 13 #include <linux/device.h> 13 14 #include <linux/io.h> ··· 28 27 #include <linux/pm_wakeirq.h> 29 28 #include <linux/dma-mapping.h> 30 29 #include <linux/sys_soc.h> 30 + #include <linux/pm_domain.h> 31 31 32 32 #include "8250.h" 33 33 ··· 116 114 /* RX FIFO occupancy indicator */ 117 115 #define UART_OMAP_RX_LVL 0x19 118 116 117 + /* 118 + * Copy of the genpd flags for the console. 119 + * Only used if console suspend is disabled 120 + */ 121 + static unsigned int genpd_flags_console; 122 + 119 123 struct omap8250_priv { 120 124 void __iomem *membase; 121 125 int line; ··· 138 130 139 131 u8 tx_trigger; 140 132 u8 rx_trigger; 133 + atomic_t active; 141 134 bool is_suspending; 142 135 int wakeirq; 143 136 int wakeups_enabled; ··· 410 401 * interrupts disabled. 411 402 */ 412 403 pm_runtime_get_sync(port->dev); 413 - spin_lock_irq(&port->lock); 404 + uart_port_lock_irq(port); 414 405 415 406 /* 416 407 * Update the per-port timeout. ··· 513 504 } 514 505 omap8250_restore_regs(up); 515 506 516 - spin_unlock_irq(&up->port.lock); 507 + uart_port_unlock_irq(&up->port); 517 508 pm_runtime_mark_last_busy(port->dev); 518 509 pm_runtime_put_autosuspend(port->dev); 519 510 ··· 538 529 pm_runtime_get_sync(port->dev); 539 530 540 531 /* Synchronize UART_IER access against the console. */ 541 - spin_lock_irq(&port->lock); 532 + uart_port_lock_irq(port); 542 533 543 534 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 544 535 efr = serial_in(up, UART_EFR); ··· 550 541 serial_out(up, UART_EFR, efr); 551 542 serial_out(up, UART_LCR, 0); 552 543 553 - spin_unlock_irq(&port->lock); 544 + uart_port_unlock_irq(port); 554 545 555 546 pm_runtime_mark_last_busy(port->dev); 556 547 pm_runtime_put_autosuspend(port->dev); ··· 641 632 unsigned int iir, lsr; 642 633 int ret; 643 634 635 + pm_runtime_get_noresume(port->dev); 636 + 637 + /* Shallow idle state wake-up to an IO interrupt? */ 638 + if (atomic_add_unless(&priv->active, 1, 1)) { 639 + priv->latency = priv->calc_latency; 640 + schedule_work(&priv->qos_work); 641 + } 642 + 644 643 #ifdef CONFIG_SERIAL_8250_DMA 645 644 if (up->dma) { 646 645 ret = omap_8250_dma_handle_irq(port); 646 + pm_runtime_mark_last_busy(port->dev); 647 + pm_runtime_put(port->dev); 647 648 return IRQ_RETVAL(ret); 648 649 } 649 650 #endif 650 651 651 - serial8250_rpm_get(up); 652 652 lsr = serial_port_in(port, UART_LSR); 653 653 iir = serial_port_in(port, UART_IIR); 654 654 ret = serial8250_handle_irq(port, iir); ··· 678 660 unsigned long delay; 679 661 680 662 /* Synchronize UART_IER access against the console. */ 681 - spin_lock(&port->lock); 663 + uart_port_lock(port); 682 664 up->ier = port->serial_in(port, UART_IER); 683 665 if (up->ier & (UART_IER_RLSI | UART_IER_RDI)) { 684 666 port->ops->stop_rx(port); ··· 688 670 */ 689 671 cancel_delayed_work(&up->overrun_backoff); 690 672 } 691 - spin_unlock(&port->lock); 673 + uart_port_unlock(port); 692 674 693 675 delay = msecs_to_jiffies(up->overrun_backoff_time_ms); 694 676 schedule_delayed_work(&up->overrun_backoff, delay); 695 677 } 696 678 697 - serial8250_rpm_put(up); 679 + pm_runtime_mark_last_busy(port->dev); 680 + pm_runtime_put(port->dev); 698 681 699 682 return IRQ_RETVAL(ret); 700 683 } ··· 736 717 } 737 718 738 719 /* Synchronize UART_IER access against the console. */ 739 - spin_lock_irq(&port->lock); 720 + uart_port_lock_irq(port); 740 721 up->ier = UART_IER_RLSI | UART_IER_RDI; 741 722 serial_out(up, UART_IER, up->ier); 742 - spin_unlock_irq(&port->lock); 723 + uart_port_unlock_irq(port); 743 724 744 725 #ifdef CONFIG_PM 745 726 up->capabilities |= UART_CAP_RPM; ··· 752 733 serial_out(up, UART_OMAP_WER, priv->wer); 753 734 754 735 if (up->dma && !(priv->habit & UART_HAS_EFR2)) { 755 - spin_lock_irq(&port->lock); 736 + uart_port_lock_irq(port); 756 737 up->dma->rx_dma(up); 757 - spin_unlock_irq(&port->lock); 738 + uart_port_unlock_irq(port); 758 739 } 759 740 760 741 enable_irq(up->port.irq); ··· 780 761 serial_out(up, UART_OMAP_EFR2, 0x0); 781 762 782 763 /* Synchronize UART_IER access against the console. */ 783 - spin_lock_irq(&port->lock); 764 + uart_port_lock_irq(port); 784 765 up->ier = 0; 785 766 serial_out(up, UART_IER, 0); 786 - spin_unlock_irq(&port->lock); 767 + uart_port_unlock_irq(port); 787 768 disable_irq_nosync(up->port.irq); 788 769 dev_pm_clear_wake_irq(port->dev); 789 770 ··· 808 789 809 790 pm_runtime_get_sync(port->dev); 810 791 811 - spin_lock_irqsave(&port->lock, flags); 792 + uart_port_lock_irqsave(port, &flags); 812 793 port->ops->stop_rx(port); 813 794 priv->throttled = true; 814 - spin_unlock_irqrestore(&port->lock, flags); 795 + uart_port_unlock_irqrestore(port, flags); 815 796 816 797 pm_runtime_mark_last_busy(port->dev); 817 798 pm_runtime_put_autosuspend(port->dev); ··· 826 807 pm_runtime_get_sync(port->dev); 827 808 828 809 /* Synchronize UART_IER access against the console. */ 829 - spin_lock_irqsave(&port->lock, flags); 810 + uart_port_lock_irqsave(port, &flags); 830 811 priv->throttled = false; 831 812 if (up->dma) 832 813 up->dma->rx_dma(up); 833 814 up->ier |= UART_IER_RLSI | UART_IER_RDI; 834 815 port->read_status_mask |= UART_LSR_DR; 835 816 serial_out(up, UART_IER, up->ier); 836 - spin_unlock_irqrestore(&port->lock, flags); 817 + uart_port_unlock_irqrestore(port, flags); 837 818 838 819 pm_runtime_mark_last_busy(port->dev); 839 820 pm_runtime_put_autosuspend(port->dev); ··· 977 958 unsigned long flags; 978 959 979 960 /* Synchronize UART_IER access against the console. */ 980 - spin_lock_irqsave(&p->port.lock, flags); 961 + uart_port_lock_irqsave(&p->port, &flags); 981 962 982 963 /* 983 964 * If the tx status is not DMA_COMPLETE, then this is a delayed ··· 986 967 */ 987 968 if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) != 988 969 DMA_COMPLETE) { 989 - spin_unlock_irqrestore(&p->port.lock, flags); 970 + uart_port_unlock_irqrestore(&p->port, flags); 990 971 return; 991 972 } 992 973 __dma_rx_do_complete(p); ··· 997 978 omap_8250_rx_dma(p); 998 979 } 999 980 1000 - spin_unlock_irqrestore(&p->port.lock, flags); 981 + uart_port_unlock_irqrestore(&p->port, flags); 1001 982 } 1002 983 1003 984 static void omap_8250_rx_dma_flush(struct uart_8250_port *p) ··· 1102 1083 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr, 1103 1084 UART_XMIT_SIZE, DMA_TO_DEVICE); 1104 1085 1105 - spin_lock_irqsave(&p->port.lock, flags); 1086 + uart_port_lock_irqsave(&p->port, &flags); 1106 1087 1107 1088 dma->tx_running = 0; 1108 1089 ··· 1131 1112 serial8250_set_THRI(p); 1132 1113 } 1133 1114 1134 - spin_unlock_irqrestore(&p->port.lock, flags); 1115 + uart_port_unlock_irqrestore(&p->port, flags); 1135 1116 } 1136 1117 1137 1118 static int omap_8250_tx_dma(struct uart_8250_port *p) ··· 1289 1270 u16 status; 1290 1271 u8 iir; 1291 1272 1292 - serial8250_rpm_get(up); 1293 - 1294 1273 iir = serial_port_in(port, UART_IIR); 1295 1274 if (iir & UART_IIR_NO_INT) { 1296 - serial8250_rpm_put(up); 1297 1275 return IRQ_HANDLED; 1298 1276 } 1299 1277 1300 - spin_lock(&port->lock); 1278 + uart_port_lock(port); 1301 1279 1302 1280 status = serial_port_in(port, UART_LSR); 1303 1281 ··· 1321 1305 1322 1306 uart_unlock_and_check_sysrq(port); 1323 1307 1324 - serial8250_rpm_put(up); 1325 1308 return 1; 1326 1309 } 1327 1310 ··· 1518 1503 if (!of_get_available_child_count(pdev->dev.of_node)) 1519 1504 pm_runtime_set_autosuspend_delay(&pdev->dev, -1); 1520 1505 1521 - pm_runtime_irq_safe(&pdev->dev); 1522 - 1523 1506 pm_runtime_get_sync(&pdev->dev); 1524 1507 1525 1508 omap_serial_fill_features_erratas(&up, priv); ··· 1630 1617 { 1631 1618 struct omap8250_priv *priv = dev_get_drvdata(dev); 1632 1619 struct uart_8250_port *up = serial8250_get_port(priv->line); 1620 + struct generic_pm_domain *genpd = pd_to_genpd(dev->pm_domain); 1633 1621 int err = 0; 1634 1622 1635 1623 serial8250_suspend_port(priv->line); ··· 1641 1627 if (!device_may_wakeup(dev)) 1642 1628 priv->wer = 0; 1643 1629 serial_out(up, UART_OMAP_WER, priv->wer); 1644 - if (uart_console(&up->port) && console_suspend_enabled) 1645 - err = pm_runtime_force_suspend(dev); 1630 + if (uart_console(&up->port)) { 1631 + if (console_suspend_enabled) 1632 + err = pm_runtime_force_suspend(dev); 1633 + else { 1634 + /* 1635 + * The pd shall not be powered-off (no console suspend). 1636 + * Make copy of genpd flags before to set it always on. 1637 + * The original value is restored during the resume. 1638 + */ 1639 + genpd_flags_console = genpd->flags; 1640 + genpd->flags |= GENPD_FLAG_ALWAYS_ON; 1641 + } 1642 + } 1646 1643 flush_work(&priv->qos_work); 1647 1644 1648 1645 return err; ··· 1663 1638 { 1664 1639 struct omap8250_priv *priv = dev_get_drvdata(dev); 1665 1640 struct uart_8250_port *up = serial8250_get_port(priv->line); 1641 + struct generic_pm_domain *genpd = pd_to_genpd(dev->pm_domain); 1666 1642 int err; 1667 1643 1668 1644 if (uart_console(&up->port) && console_suspend_enabled) { 1669 - err = pm_runtime_force_resume(dev); 1670 - if (err) 1671 - return err; 1645 + if (console_suspend_enabled) { 1646 + err = pm_runtime_force_resume(dev); 1647 + if (err) 1648 + return err; 1649 + } else 1650 + genpd->flags = genpd_flags_console; 1672 1651 } 1673 1652 1674 1653 serial8250_resume_port(priv->line); ··· 1772 1743 1773 1744 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1774 1745 schedule_work(&priv->qos_work); 1746 + atomic_set(&priv->active, 0); 1775 1747 1776 1748 return 0; 1777 1749 } ··· 1782 1752 struct omap8250_priv *priv = dev_get_drvdata(dev); 1783 1753 struct uart_8250_port *up = NULL; 1784 1754 1755 + /* Did the hardware wake to a device IO interrupt before a wakeirq? */ 1756 + if (atomic_read(&priv->active)) 1757 + return 0; 1758 + 1785 1759 if (priv->line >= 0) 1786 1760 up = serial8250_get_port(priv->line); 1787 1761 1788 1762 if (up && omap8250_lost_context(up)) { 1789 - spin_lock_irq(&up->port.lock); 1763 + uart_port_lock_irq(&up->port); 1790 1764 omap8250_restore_regs(up); 1791 - spin_unlock_irq(&up->port.lock); 1765 + uart_port_unlock_irq(&up->port); 1792 1766 } 1793 1767 1794 1768 if (up && up->dma && up->dma->rxchan && !(priv->habit & UART_HAS_EFR2)) { 1795 - spin_lock_irq(&up->port.lock); 1769 + uart_port_lock_irq(&up->port); 1796 1770 omap_8250_rx_dma(up); 1797 - spin_unlock_irq(&up->port.lock); 1771 + uart_port_unlock_irq(&up->port); 1798 1772 } 1799 1773 1774 + atomic_set(&priv->active, 1); 1800 1775 priv->latency = priv->calc_latency; 1801 1776 schedule_work(&priv->qos_work); 1777 + 1802 1778 return 0; 1803 1779 } 1804 1780

+471 -126

drivers/tty/serial/8250/8250_pci.c

··· 26 26 #include "8250.h" 27 27 #include "8250_pcilib.h" 28 28 29 + #define PCI_VENDOR_ID_SBSMODULARIO 0x124B 30 + #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B 31 + #define PCI_DEVICE_ID_OCTPRO 0x0001 32 + #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108 33 + #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208 34 + #define PCI_SUBDEVICE_ID_POCTAL232 0x0308 35 + #define PCI_SUBDEVICE_ID_POCTAL422 0x0408 36 + #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500 37 + #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530 38 + #define PCI_VENDOR_ID_ADVANTECH 0x13fe 39 + #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66 40 + #define PCI_DEVICE_ID_ADVANTECH_PCI1600 0x1600 41 + #define PCI_DEVICE_ID_ADVANTECH_PCI1600_1611 0x1611 42 + #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620 43 + #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618 44 + #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618 45 + #define PCI_DEVICE_ID_TITAN_200I 0x8028 46 + #define PCI_DEVICE_ID_TITAN_400I 0x8048 47 + #define PCI_DEVICE_ID_TITAN_800I 0x8088 48 + #define PCI_DEVICE_ID_TITAN_800EH 0xA007 49 + #define PCI_DEVICE_ID_TITAN_800EHB 0xA008 50 + #define PCI_DEVICE_ID_TITAN_400EH 0xA009 51 + #define PCI_DEVICE_ID_TITAN_100E 0xA010 52 + #define PCI_DEVICE_ID_TITAN_200E 0xA012 53 + #define PCI_DEVICE_ID_TITAN_400E 0xA013 54 + #define PCI_DEVICE_ID_TITAN_800E 0xA014 55 + #define PCI_DEVICE_ID_TITAN_200EI 0xA016 56 + #define PCI_DEVICE_ID_TITAN_200EISI 0xA017 57 + #define PCI_DEVICE_ID_TITAN_200V3 0xA306 58 + #define PCI_DEVICE_ID_TITAN_400V3 0xA310 59 + #define PCI_DEVICE_ID_TITAN_410V3 0xA312 60 + #define PCI_DEVICE_ID_TITAN_800V3 0xA314 61 + #define PCI_DEVICE_ID_TITAN_800V3B 0xA315 62 + #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538 63 + #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6 64 + #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001 65 + #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d 66 + #define PCI_VENDOR_ID_WCH 0x4348 67 + #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253 68 + #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453 69 + #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046 70 + #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053 71 + #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053 72 + #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173 73 + #define PCI_VENDOR_ID_AGESTAR 0x5372 74 + #define PCI_DEVICE_ID_AGESTAR_9375 0x6872 75 + #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a 76 + #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e 77 + 78 + #define PCIE_VENDOR_ID_WCH 0x1c00 79 + #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250 80 + #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470 81 + #define PCIE_DEVICE_ID_WCH_CH384_8S 0x3853 82 + #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253 83 + 84 + #define PCI_DEVICE_ID_MOXA_CP102E 0x1024 85 + #define PCI_DEVICE_ID_MOXA_CP102EL 0x1025 86 + #define PCI_DEVICE_ID_MOXA_CP102N 0x1027 87 + #define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045 88 + #define PCI_DEVICE_ID_MOXA_CP104N 0x1046 89 + #define PCI_DEVICE_ID_MOXA_CP112N 0x1121 90 + #define PCI_DEVICE_ID_MOXA_CP114EL 0x1144 91 + #define PCI_DEVICE_ID_MOXA_CP114N 0x1145 92 + #define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160 93 + #define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161 94 + #define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182 95 + #define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183 96 + #define PCI_DEVICE_ID_MOXA_CP132EL 0x1322 97 + #define PCI_DEVICE_ID_MOXA_CP132N 0x1323 98 + #define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342 99 + #define PCI_DEVICE_ID_MOXA_CP134N 0x1343 100 + #define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381 101 + #define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683 102 + 103 + /* Unknown vendors/cards - this should not be in linux/pci_ids.h */ 104 + #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584 105 + #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588 106 + 29 107 /* 30 108 * init function returns: 31 109 * > 0 - number of ports ··· 1965 1887 return setup_port(priv, port, bar, offset, 0); 1966 1888 } 1967 1889 1890 + #define MOXA_PUART_GPIO_EN 0x09 1891 + #define MOXA_PUART_GPIO_OUT 0x0A 1892 + 1893 + #define MOXA_GPIO_PIN2 BIT(2) 1894 + 1895 + static bool pci_moxa_is_mini_pcie(unsigned short device) 1896 + { 1897 + if (device == PCI_DEVICE_ID_MOXA_CP102N || 1898 + device == PCI_DEVICE_ID_MOXA_CP104N || 1899 + device == PCI_DEVICE_ID_MOXA_CP112N || 1900 + device == PCI_DEVICE_ID_MOXA_CP114N || 1901 + device == PCI_DEVICE_ID_MOXA_CP132N || 1902 + device == PCI_DEVICE_ID_MOXA_CP134N) 1903 + return true; 1904 + 1905 + return false; 1906 + } 1907 + 1908 + static int pci_moxa_init(struct pci_dev *dev) 1909 + { 1910 + unsigned short device = dev->device; 1911 + resource_size_t iobar_addr = pci_resource_start(dev, 2); 1912 + unsigned int num_ports = (device & 0x00F0) >> 4; 1913 + u8 val; 1914 + 1915 + /* 1916 + * Enable hardware buffer to prevent break signal output when system boots up. 1917 + * This hardware buffer is only supported on Mini PCIe series. 1918 + */ 1919 + if (pci_moxa_is_mini_pcie(device)) { 1920 + /* Set GPIO direction */ 1921 + val = inb(iobar_addr + MOXA_PUART_GPIO_EN); 1922 + val |= MOXA_GPIO_PIN2; 1923 + outb(val, iobar_addr + MOXA_PUART_GPIO_EN); 1924 + /* Enable low GPIO */ 1925 + val = inb(iobar_addr + MOXA_PUART_GPIO_OUT); 1926 + val &= ~MOXA_GPIO_PIN2; 1927 + outb(val, iobar_addr + MOXA_PUART_GPIO_OUT); 1928 + } 1929 + 1930 + return num_ports; 1931 + } 1932 + 1968 1933 static int 1969 1934 pci_moxa_setup(struct serial_private *priv, 1970 1935 const struct pciserial_board *board, ··· 2023 1902 2024 1903 return setup_port(priv, port, bar, offset, 0); 2025 1904 } 2026 - 2027 - #define PCI_VENDOR_ID_SBSMODULARIO 0x124B 2028 - #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B 2029 - #define PCI_DEVICE_ID_OCTPRO 0x0001 2030 - #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108 2031 - #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208 2032 - #define PCI_SUBDEVICE_ID_POCTAL232 0x0308 2033 - #define PCI_SUBDEVICE_ID_POCTAL422 0x0408 2034 - #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500 2035 - #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530 2036 - #define PCI_VENDOR_ID_ADVANTECH 0x13fe 2037 - #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66 2038 - #define PCI_DEVICE_ID_ADVANTECH_PCI1600 0x1600 2039 - #define PCI_DEVICE_ID_ADVANTECH_PCI1600_1611 0x1611 2040 - #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620 2041 - #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618 2042 - #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618 2043 - #define PCI_DEVICE_ID_TITAN_200I 0x8028 2044 - #define PCI_DEVICE_ID_TITAN_400I 0x8048 2045 - #define PCI_DEVICE_ID_TITAN_800I 0x8088 2046 - #define PCI_DEVICE_ID_TITAN_800EH 0xA007 2047 - #define PCI_DEVICE_ID_TITAN_800EHB 0xA008 2048 - #define PCI_DEVICE_ID_TITAN_400EH 0xA009 2049 - #define PCI_DEVICE_ID_TITAN_100E 0xA010 2050 - #define PCI_DEVICE_ID_TITAN_200E 0xA012 2051 - #define PCI_DEVICE_ID_TITAN_400E 0xA013 2052 - #define PCI_DEVICE_ID_TITAN_800E 0xA014 2053 - #define PCI_DEVICE_ID_TITAN_200EI 0xA016 2054 - #define PCI_DEVICE_ID_TITAN_200EISI 0xA017 2055 - #define PCI_DEVICE_ID_TITAN_200V3 0xA306 2056 - #define PCI_DEVICE_ID_TITAN_400V3 0xA310 2057 - #define PCI_DEVICE_ID_TITAN_410V3 0xA312 2058 - #define PCI_DEVICE_ID_TITAN_800V3 0xA314 2059 - #define PCI_DEVICE_ID_TITAN_800V3B 0xA315 2060 - #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538 2061 - #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6 2062 - #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001 2063 - #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d 2064 - #define PCI_VENDOR_ID_WCH 0x4348 2065 - #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253 2066 - #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453 2067 - #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046 2068 - #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053 2069 - #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053 2070 - #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173 2071 - #define PCI_VENDOR_ID_AGESTAR 0x5372 2072 - #define PCI_DEVICE_ID_AGESTAR_9375 0x6872 2073 - #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a 2074 - #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e 2075 - 2076 - #define PCIE_VENDOR_ID_WCH 0x1c00 2077 - #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250 2078 - #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470 2079 - #define PCIE_DEVICE_ID_WCH_CH384_8S 0x3853 2080 - #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253 2081 - 2082 - #define PCI_DEVICE_ID_MOXA_CP102E 0x1024 2083 - #define PCI_DEVICE_ID_MOXA_CP102EL 0x1025 2084 - #define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045 2085 - #define PCI_DEVICE_ID_MOXA_CP114EL 0x1144 2086 - #define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160 2087 - #define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161 2088 - #define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182 2089 - #define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183 2090 - #define PCI_DEVICE_ID_MOXA_CP132EL 0x1322 2091 - #define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342 2092 - #define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381 2093 - #define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683 2094 - 2095 - /* Unknown vendors/cards - this should not be in linux/pci_ids.h */ 2096 - #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584 2097 - #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588 2098 1905 2099 1906 /* 2100 1907 * Master list of serial port init/setup/exit quirks. ··· 2478 2429 .init = pci_oxsemi_tornado_init, 2479 2430 .setup = pci_oxsemi_tornado_setup, 2480 2431 }, 2432 + /* 2433 + * Brainboxes devices - all Oxsemi based 2434 + */ 2435 + { 2436 + .vendor = PCI_VENDOR_ID_INTASHIELD, 2437 + .device = 0x4027, 2438 + .subvendor = PCI_ANY_ID, 2439 + .subdevice = PCI_ANY_ID, 2440 + .init = pci_oxsemi_tornado_init, 2441 + .setup = pci_oxsemi_tornado_setup, 2442 + }, 2443 + { 2444 + .vendor = PCI_VENDOR_ID_INTASHIELD, 2445 + .device = 0x4028, 2446 + .subvendor = PCI_ANY_ID, 2447 + .subdevice = PCI_ANY_ID, 2448 + .init = pci_oxsemi_tornado_init, 2449 + .setup = pci_oxsemi_tornado_setup, 2450 + }, 2451 + { 2452 + .vendor = PCI_VENDOR_ID_INTASHIELD, 2453 + .device = 0x4029, 2454 + .subvendor = PCI_ANY_ID, 2455 + .subdevice = PCI_ANY_ID, 2456 + .init = pci_oxsemi_tornado_init, 2457 + .setup = pci_oxsemi_tornado_setup, 2458 + }, 2459 + { 2460 + .vendor = PCI_VENDOR_ID_INTASHIELD, 2461 + .device = 0x4019, 2462 + .subvendor = PCI_ANY_ID, 2463 + .subdevice = PCI_ANY_ID, 2464 + .init = pci_oxsemi_tornado_init, 2465 + .setup = pci_oxsemi_tornado_setup, 2466 + }, 2467 + { 2468 + .vendor = PCI_VENDOR_ID_INTASHIELD, 2469 + .device = 0x4016, 2470 + .subvendor = PCI_ANY_ID, 2471 + .subdevice = PCI_ANY_ID, 2472 + .init = pci_oxsemi_tornado_init, 2473 + .setup = pci_oxsemi_tornado_setup, 2474 + }, 2475 + { 2476 + .vendor = PCI_VENDOR_ID_INTASHIELD, 2477 + .device = 0x4015, 2478 + .subvendor = PCI_ANY_ID, 2479 + .subdevice = PCI_ANY_ID, 2480 + .init = pci_oxsemi_tornado_init, 2481 + .setup = pci_oxsemi_tornado_setup, 2482 + }, 2483 + { 2484 + .vendor = PCI_VENDOR_ID_INTASHIELD, 2485 + .device = 0x400A, 2486 + .subvendor = PCI_ANY_ID, 2487 + .subdevice = PCI_ANY_ID, 2488 + .init = pci_oxsemi_tornado_init, 2489 + .setup = pci_oxsemi_tornado_setup, 2490 + }, 2491 + { 2492 + .vendor = PCI_VENDOR_ID_INTASHIELD, 2493 + .device = 0x400E, 2494 + .subvendor = PCI_ANY_ID, 2495 + .subdevice = PCI_ANY_ID, 2496 + .init = pci_oxsemi_tornado_init, 2497 + .setup = pci_oxsemi_tornado_setup, 2498 + }, 2499 + { 2500 + .vendor = PCI_VENDOR_ID_INTASHIELD, 2501 + .device = 0x400C, 2502 + .subvendor = PCI_ANY_ID, 2503 + .subdevice = PCI_ANY_ID, 2504 + .init = pci_oxsemi_tornado_init, 2505 + .setup = pci_oxsemi_tornado_setup, 2506 + }, 2507 + { 2508 + .vendor = PCI_VENDOR_ID_INTASHIELD, 2509 + .device = 0x400B, 2510 + .subvendor = PCI_ANY_ID, 2511 + .subdevice = PCI_ANY_ID, 2512 + .init = pci_oxsemi_tornado_init, 2513 + .setup = pci_oxsemi_tornado_setup, 2514 + }, 2515 + { 2516 + .vendor = PCI_VENDOR_ID_INTASHIELD, 2517 + .device = 0x400F, 2518 + .subvendor = PCI_ANY_ID, 2519 + .subdevice = PCI_ANY_ID, 2520 + .init = pci_oxsemi_tornado_init, 2521 + .setup = pci_oxsemi_tornado_setup, 2522 + }, 2523 + { 2524 + .vendor = PCI_VENDOR_ID_INTASHIELD, 2525 + .device = 0x4010, 2526 + .subvendor = PCI_ANY_ID, 2527 + .subdevice = PCI_ANY_ID, 2528 + .init = pci_oxsemi_tornado_init, 2529 + .setup = pci_oxsemi_tornado_setup, 2530 + }, 2531 + { 2532 + .vendor = PCI_VENDOR_ID_INTASHIELD, 2533 + .device = 0x4011, 2534 + .subvendor = PCI_ANY_ID, 2535 + .subdevice = PCI_ANY_ID, 2536 + .init = pci_oxsemi_tornado_init, 2537 + .setup = pci_oxsemi_tornado_setup, 2538 + }, 2539 + { 2540 + .vendor = PCI_VENDOR_ID_INTASHIELD, 2541 + .device = 0x401D, 2542 + .subvendor = PCI_ANY_ID, 2543 + .subdevice = PCI_ANY_ID, 2544 + .init = pci_oxsemi_tornado_init, 2545 + .setup = pci_oxsemi_tornado_setup, 2546 + }, 2547 + { 2548 + .vendor = PCI_VENDOR_ID_INTASHIELD, 2549 + .device = 0x401E, 2550 + .subvendor = PCI_ANY_ID, 2551 + .subdevice = PCI_ANY_ID, 2552 + .init = pci_oxsemi_tornado_init, 2553 + .setup = pci_oxsemi_tornado_setup, 2554 + }, 2555 + { 2556 + .vendor = PCI_VENDOR_ID_INTASHIELD, 2557 + .device = 0x4013, 2558 + .subvendor = PCI_ANY_ID, 2559 + .subdevice = PCI_ANY_ID, 2560 + .init = pci_oxsemi_tornado_init, 2561 + .setup = pci_oxsemi_tornado_setup, 2562 + }, 2563 + { 2564 + .vendor = PCI_VENDOR_ID_INTASHIELD, 2565 + .device = 0x4017, 2566 + .subvendor = PCI_ANY_ID, 2567 + .subdevice = PCI_ANY_ID, 2568 + .init = pci_oxsemi_tornado_init, 2569 + .setup = pci_oxsemi_tornado_setup, 2570 + }, 2571 + { 2572 + .vendor = PCI_VENDOR_ID_INTASHIELD, 2573 + .device = 0x4018, 2574 + .subvendor = PCI_ANY_ID, 2575 + .subdevice = PCI_ANY_ID, 2576 + .init = pci_oxsemi_tornado_init, 2577 + .setup = pci_oxsemi_tornado_setup, 2578 + }, 2481 2579 { 2482 2580 .vendor = PCI_VENDOR_ID_INTEL, 2483 2581 .device = 0x8811, ··· 2831 2635 .device = PCI_ANY_ID, 2832 2636 .subvendor = PCI_ANY_ID, 2833 2637 .subdevice = PCI_ANY_ID, 2638 + .init = pci_moxa_init, 2834 2639 .setup = pci_moxa_setup, 2835 2640 }, 2836 2641 { ··· 3051 2854 pbn_titan_2_4000000, 3052 2855 pbn_titan_4_4000000, 3053 2856 pbn_titan_8_4000000, 3054 - pbn_moxa8250_2p, 3055 - pbn_moxa8250_4p, 3056 - pbn_moxa8250_8p, 2857 + pbn_moxa_2, 2858 + pbn_moxa_4, 2859 + pbn_moxa_8, 3057 2860 }; 3058 2861 3059 2862 /* ··· 3825 3628 .uart_offset = 0x200, 3826 3629 .first_offset = 0x1000, 3827 3630 }, 3828 - [pbn_moxa8250_2p] = { 3631 + [pbn_moxa_2] = { 3829 3632 .flags = FL_BASE1, 3830 3633 .num_ports = 2, 3831 3634 .base_baud = 921600, 3832 3635 .uart_offset = 0x200, 3833 3636 }, 3834 - [pbn_moxa8250_4p] = { 3637 + [pbn_moxa_4] = { 3835 3638 .flags = FL_BASE1, 3836 3639 .num_ports = 4, 3837 3640 .base_baud = 921600, 3838 3641 .uart_offset = 0x200, 3839 3642 }, 3840 - [pbn_moxa8250_8p] = { 3643 + [pbn_moxa_8] = { 3841 3644 .flags = FL_BASE1, 3842 3645 .num_ports = 8, 3843 3646 .base_baud = 921600, ··· 5111 4914 pbn_b1_bt_1_115200 }, 5112 4915 5113 4916 /* 4917 + * IntaShield IS-100 4918 + */ 4919 + { PCI_VENDOR_ID_INTASHIELD, 0x0D60, 4920 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4921 + pbn_b2_1_115200 }, 4922 + /* 5114 4923 * IntaShield IS-200 5115 4924 */ 5116 4925 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200, 5117 - PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */ 4926 + PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0d80 */ 5118 4927 pbn_b2_2_115200 }, 5119 4928 /* 5120 4929 * IntaShield IS-400 ··· 5128 4925 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400, 5129 4926 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */ 5130 4927 pbn_b2_4_115200 }, 4928 + /* 4929 + * IntaShield IX-100 4930 + */ 4931 + { PCI_VENDOR_ID_INTASHIELD, 0x4027, 4932 + PCI_ANY_ID, PCI_ANY_ID, 4933 + 0, 0, 4934 + pbn_oxsemi_1_15625000 }, 4935 + /* 4936 + * IntaShield IX-200 4937 + */ 4938 + { PCI_VENDOR_ID_INTASHIELD, 0x4028, 4939 + PCI_ANY_ID, PCI_ANY_ID, 4940 + 0, 0, 4941 + pbn_oxsemi_2_15625000 }, 4942 + /* 4943 + * IntaShield IX-400 4944 + */ 4945 + { PCI_VENDOR_ID_INTASHIELD, 0x4029, 4946 + PCI_ANY_ID, PCI_ANY_ID, 4947 + 0, 0, 4948 + pbn_oxsemi_4_15625000 }, 5131 4949 /* Brainboxes Devices */ 5132 4950 /* 5133 4951 * Brainboxes UC-101 ··· 5164 4940 PCI_ANY_ID, PCI_ANY_ID, 5165 4941 0, 0, 5166 4942 pbn_b2_1_115200 }, 4943 + { PCI_VENDOR_ID_INTASHIELD, 0x0AA2, 4944 + PCI_ANY_ID, PCI_ANY_ID, 4945 + 0, 0, 4946 + pbn_b2_1_115200 }, 5167 4947 /* 5168 - * Brainboxes UC-257 4948 + * Brainboxes UC-253/UC-734 5169 4949 */ 5170 - { PCI_VENDOR_ID_INTASHIELD, 0x0861, 4950 + { PCI_VENDOR_ID_INTASHIELD, 0x0CA1, 5171 4951 PCI_ANY_ID, PCI_ANY_ID, 5172 4952 0, 0, 5173 4953 pbn_b2_2_115200 }, ··· 5207 4979 PCI_ANY_ID, PCI_ANY_ID, 5208 4980 0, 0, 5209 4981 pbn_b2_2_115200 }, 4982 + { PCI_VENDOR_ID_INTASHIELD, 0x08E2, 4983 + PCI_ANY_ID, PCI_ANY_ID, 4984 + 0, 0, 4985 + pbn_b2_2_115200 }, 4986 + { PCI_VENDOR_ID_INTASHIELD, 0x08E3, 4987 + PCI_ANY_ID, PCI_ANY_ID, 4988 + 0, 0, 4989 + pbn_b2_2_115200 }, 5210 4990 /* 5211 4991 * Brainboxes UC-310 5212 4992 */ ··· 5225 4989 /* 5226 4990 * Brainboxes UC-313 5227 4991 */ 4992 + { PCI_VENDOR_ID_INTASHIELD, 0x08A1, 4993 + PCI_ANY_ID, PCI_ANY_ID, 4994 + 0, 0, 4995 + pbn_b2_2_115200 }, 4996 + { PCI_VENDOR_ID_INTASHIELD, 0x08A2, 4997 + PCI_ANY_ID, PCI_ANY_ID, 4998 + 0, 0, 4999 + pbn_b2_2_115200 }, 5228 5000 { PCI_VENDOR_ID_INTASHIELD, 0x08A3, 5229 5001 PCI_ANY_ID, PCI_ANY_ID, 5230 5002 0, 0, ··· 5247 5003 /* 5248 5004 * Brainboxes UC-346 5249 5005 */ 5006 + { PCI_VENDOR_ID_INTASHIELD, 0x0B01, 5007 + PCI_ANY_ID, PCI_ANY_ID, 5008 + 0, 0, 5009 + pbn_b2_4_115200 }, 5250 5010 { PCI_VENDOR_ID_INTASHIELD, 0x0B02, 5251 5011 PCI_ANY_ID, PCI_ANY_ID, 5252 5012 0, 0, ··· 5259 5011 * Brainboxes UC-357 5260 5012 */ 5261 5013 { PCI_VENDOR_ID_INTASHIELD, 0x0A81, 5014 + PCI_ANY_ID, PCI_ANY_ID, 5015 + 0, 0, 5016 + pbn_b2_2_115200 }, 5017 + { PCI_VENDOR_ID_INTASHIELD, 0x0A82, 5262 5018 PCI_ANY_ID, PCI_ANY_ID, 5263 5019 0, 0, 5264 5020 pbn_b2_2_115200 }, ··· 5278 5026 0, 0, 5279 5027 pbn_b2_4_115200 }, 5280 5028 /* 5281 - * Brainboxes UC-420/431 5029 + * Brainboxes UC-420 5282 5030 */ 5283 5031 { PCI_VENDOR_ID_INTASHIELD, 0x0921, 5284 5032 PCI_ANY_ID, PCI_ANY_ID, 5285 5033 0, 0, 5286 5034 pbn_b2_4_115200 }, 5035 + /* 5036 + * Brainboxes UC-607 5037 + */ 5038 + { PCI_VENDOR_ID_INTASHIELD, 0x09A1, 5039 + PCI_ANY_ID, PCI_ANY_ID, 5040 + 0, 0, 5041 + pbn_b2_2_115200 }, 5042 + { PCI_VENDOR_ID_INTASHIELD, 0x09A2, 5043 + PCI_ANY_ID, PCI_ANY_ID, 5044 + 0, 0, 5045 + pbn_b2_2_115200 }, 5046 + { PCI_VENDOR_ID_INTASHIELD, 0x09A3, 5047 + PCI_ANY_ID, PCI_ANY_ID, 5048 + 0, 0, 5049 + pbn_b2_2_115200 }, 5050 + /* 5051 + * Brainboxes UC-836 5052 + */ 5053 + { PCI_VENDOR_ID_INTASHIELD, 0x0D41, 5054 + PCI_ANY_ID, PCI_ANY_ID, 5055 + 0, 0, 5056 + pbn_b2_4_115200 }, 5057 + /* 5058 + * Brainboxes UP-189 5059 + */ 5060 + { PCI_VENDOR_ID_INTASHIELD, 0x0AC1, 5061 + PCI_ANY_ID, PCI_ANY_ID, 5062 + 0, 0, 5063 + pbn_b2_2_115200 }, 5064 + { PCI_VENDOR_ID_INTASHIELD, 0x0AC2, 5065 + PCI_ANY_ID, PCI_ANY_ID, 5066 + 0, 0, 5067 + pbn_b2_2_115200 }, 5068 + { PCI_VENDOR_ID_INTASHIELD, 0x0AC3, 5069 + PCI_ANY_ID, PCI_ANY_ID, 5070 + 0, 0, 5071 + pbn_b2_2_115200 }, 5072 + /* 5073 + * Brainboxes UP-200 5074 + */ 5075 + { PCI_VENDOR_ID_INTASHIELD, 0x0B21, 5076 + PCI_ANY_ID, PCI_ANY_ID, 5077 + 0, 0, 5078 + pbn_b2_2_115200 }, 5079 + { PCI_VENDOR_ID_INTASHIELD, 0x0B22, 5080 + PCI_ANY_ID, PCI_ANY_ID, 5081 + 0, 0, 5082 + pbn_b2_2_115200 }, 5083 + { PCI_VENDOR_ID_INTASHIELD, 0x0B23, 5084 + PCI_ANY_ID, PCI_ANY_ID, 5085 + 0, 0, 5086 + pbn_b2_2_115200 }, 5087 + /* 5088 + * Brainboxes UP-869 5089 + */ 5090 + { PCI_VENDOR_ID_INTASHIELD, 0x0C01, 5091 + PCI_ANY_ID, PCI_ANY_ID, 5092 + 0, 0, 5093 + pbn_b2_2_115200 }, 5094 + { PCI_VENDOR_ID_INTASHIELD, 0x0C02, 5095 + PCI_ANY_ID, PCI_ANY_ID, 5096 + 0, 0, 5097 + pbn_b2_2_115200 }, 5098 + { PCI_VENDOR_ID_INTASHIELD, 0x0C03, 5099 + PCI_ANY_ID, PCI_ANY_ID, 5100 + 0, 0, 5101 + pbn_b2_2_115200 }, 5102 + /* 5103 + * Brainboxes UP-880 5104 + */ 5105 + { PCI_VENDOR_ID_INTASHIELD, 0x0C21, 5106 + PCI_ANY_ID, PCI_ANY_ID, 5107 + 0, 0, 5108 + pbn_b2_2_115200 }, 5109 + { PCI_VENDOR_ID_INTASHIELD, 0x0C22, 5110 + PCI_ANY_ID, PCI_ANY_ID, 5111 + 0, 0, 5112 + pbn_b2_2_115200 }, 5113 + { PCI_VENDOR_ID_INTASHIELD, 0x0C23, 5114 + PCI_ANY_ID, PCI_ANY_ID, 5115 + 0, 0, 5116 + pbn_b2_2_115200 }, 5287 5117 /* 5288 5118 * Brainboxes PX-101 5289 5119 */ ··· 5398 5064 { PCI_VENDOR_ID_INTASHIELD, 0x4015, 5399 5065 PCI_ANY_ID, PCI_ANY_ID, 5400 5066 0, 0, 5401 - pbn_oxsemi_4_15625000 }, 5067 + pbn_oxsemi_2_15625000 }, 5402 5068 /* 5403 5069 * Brainboxes PX-260/PX-701 5404 5070 */ ··· 5406 5072 PCI_ANY_ID, PCI_ANY_ID, 5407 5073 0, 0, 5408 5074 pbn_oxsemi_4_15625000 }, 5075 + /* 5076 + * Brainboxes PX-275/279 5077 + */ 5078 + { PCI_VENDOR_ID_INTASHIELD, 0x0E41, 5079 + PCI_ANY_ID, PCI_ANY_ID, 5080 + 0, 0, 5081 + pbn_b2_8_115200 }, 5409 5082 /* 5410 5083 * Brainboxes PX-310 5411 5084 */ ··· 5460 5119 0, 0, 5461 5120 pbn_oxsemi_4_15625000 }, 5462 5121 /* 5463 - * Brainboxes PX-803 5122 + * Brainboxes PX-475 5464 5123 */ 5465 - { PCI_VENDOR_ID_INTASHIELD, 0x4009, 5466 - PCI_ANY_ID, PCI_ANY_ID, 5467 - 0, 0, 5468 - pbn_b0_1_115200 }, 5469 - { PCI_VENDOR_ID_INTASHIELD, 0x401E, 5124 + { PCI_VENDOR_ID_INTASHIELD, 0x401D, 5470 5125 PCI_ANY_ID, PCI_ANY_ID, 5471 5126 0, 0, 5472 5127 pbn_oxsemi_1_15625000 }, 5473 5128 /* 5474 - * Brainboxes PX-846 5129 + * Brainboxes PX-803/PX-857 5130 + */ 5131 + { PCI_VENDOR_ID_INTASHIELD, 0x4009, 5132 + PCI_ANY_ID, PCI_ANY_ID, 5133 + 0, 0, 5134 + pbn_b0_2_115200 }, 5135 + { PCI_VENDOR_ID_INTASHIELD, 0x4018, 5136 + PCI_ANY_ID, PCI_ANY_ID, 5137 + 0, 0, 5138 + pbn_oxsemi_2_15625000 }, 5139 + { PCI_VENDOR_ID_INTASHIELD, 0x401E, 5140 + PCI_ANY_ID, PCI_ANY_ID, 5141 + 0, 0, 5142 + pbn_oxsemi_2_15625000 }, 5143 + /* 5144 + * Brainboxes PX-820 5145 + */ 5146 + { PCI_VENDOR_ID_INTASHIELD, 0x4002, 5147 + PCI_ANY_ID, PCI_ANY_ID, 5148 + 0, 0, 5149 + pbn_b0_4_115200 }, 5150 + { PCI_VENDOR_ID_INTASHIELD, 0x4013, 5151 + PCI_ANY_ID, PCI_ANY_ID, 5152 + 0, 0, 5153 + pbn_oxsemi_4_15625000 }, 5154 + /* 5155 + * Brainboxes PX-835/PX-846 5475 5156 */ 5476 5157 { PCI_VENDOR_ID_INTASHIELD, 0x4008, 5477 5158 PCI_ANY_ID, PCI_ANY_ID, ··· 5712 5349 /* 5713 5350 * MOXA 5714 5351 */ 5715 - { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102E, 5716 - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5717 - pbn_moxa8250_2p }, 5718 - { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102EL, 5719 - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5720 - pbn_moxa8250_2p }, 5721 - { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A, 5722 - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5723 - pbn_moxa8250_4p }, 5724 - { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP114EL, 5725 - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5726 - pbn_moxa8250_4p }, 5727 - { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A, 5728 - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5729 - pbn_moxa8250_8p }, 5730 - { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B, 5731 - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5732 - pbn_moxa8250_8p }, 5733 - { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A, 5734 - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5735 - pbn_moxa8250_8p }, 5736 - { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I, 5737 - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5738 - pbn_moxa8250_8p }, 5739 - { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP132EL, 5740 - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5741 - pbn_moxa8250_2p }, 5742 - { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A, 5743 - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5744 - pbn_moxa8250_4p }, 5745 - { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP138E_A, 5746 - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5747 - pbn_moxa8250_8p }, 5748 - { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A, 5749 - PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5750 - pbn_moxa8250_8p }, 5352 + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102E), pbn_moxa_2 }, 5353 + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102EL), pbn_moxa_2 }, 5354 + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102N), pbn_moxa_2 }, 5355 + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A), pbn_moxa_4 }, 5356 + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104N), pbn_moxa_4 }, 5357 + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP112N), pbn_moxa_2 }, 5358 + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114EL), pbn_moxa_4 }, 5359 + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114N), pbn_moxa_4 }, 5360 + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A), pbn_moxa_8 }, 5361 + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B), pbn_moxa_8 }, 5362 + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A), pbn_moxa_8 }, 5363 + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I), pbn_moxa_8 }, 5364 + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132EL), pbn_moxa_2 }, 5365 + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132N), pbn_moxa_2 }, 5366 + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A), pbn_moxa_4 }, 5367 + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134N), pbn_moxa_4 }, 5368 + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP138E_A), pbn_moxa_8 }, 5369 + { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A), pbn_moxa_8 }, 5751 5370 5752 5371 /* 5753 5372 * ADDI-DATA GmbH communication cards <info@addi-data.com>

+5 -5

drivers/tty/serial/8250/8250_pci1xxxx.c

··· 107 107 struct pci1xxxx_8250 { 108 108 unsigned int nr; 109 109 void __iomem *membase; 110 - int line[]; 110 + int line[] __counted_by(nr); 111 111 }; 112 112 113 113 static int pci1xxxx_get_num_ports(struct pci_dev *dev) ··· 225 225 if (port->suspended == 0 && port->dev) { 226 226 wakeup_mask = readb(up->port.membase + UART_WAKE_MASK_REG); 227 227 228 - spin_lock_irqsave(&port->lock, flags); 228 + uart_port_lock_irqsave(port, &flags); 229 229 port->mctrl &= ~TIOCM_OUT2; 230 230 port->ops->set_mctrl(port, port->mctrl); 231 - spin_unlock_irqrestore(&port->lock, flags); 231 + uart_port_unlock_irqrestore(port, flags); 232 232 233 233 ret = (wakeup_mask & UART_WAKE_SRCS) != UART_WAKE_SRCS; 234 234 } ··· 251 251 writeb(UART_WAKE_SRCS, port->membase + UART_WAKE_REG); 252 252 253 253 if (port->suspended == 0) { 254 - spin_lock_irqsave(&port->lock, flags); 254 + uart_port_lock_irqsave(port, &flags); 255 255 port->mctrl |= TIOCM_OUT2; 256 256 port->ops->set_mctrl(port, port->mctrl); 257 - spin_unlock_irqrestore(&port->lock, flags); 257 + uart_port_unlock_irqrestore(port, flags); 258 258 } 259 259 mutex_unlock(&tport->mutex); 260 260 }

+55 -56

drivers/tty/serial/8250/8250_port.c

··· 689 689 690 690 if (p->capabilities & UART_CAP_SLEEP) { 691 691 /* Synchronize UART_IER access against the console. */ 692 - spin_lock_irq(&p->port.lock); 692 + uart_port_lock_irq(&p->port); 693 693 if (p->capabilities & UART_CAP_EFR) { 694 694 lcr = serial_in(p, UART_LCR); 695 695 efr = serial_in(p, UART_EFR); ··· 703 703 serial_out(p, UART_EFR, efr); 704 704 serial_out(p, UART_LCR, lcr); 705 705 } 706 - spin_unlock_irq(&p->port.lock); 706 + uart_port_unlock_irq(&p->port); 707 707 } 708 708 709 709 serial8250_rpm_put(p); ··· 746 746 { 747 747 if (up->port.type == PORT_RSA) { 748 748 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) { 749 - spin_lock_irq(&up->port.lock); 749 + uart_port_lock_irq(&up->port); 750 750 __enable_rsa(up); 751 - spin_unlock_irq(&up->port.lock); 751 + uart_port_unlock_irq(&up->port); 752 752 } 753 753 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) 754 754 serial_out(up, UART_RSA_FRR, 0); ··· 768 768 769 769 if (up->port.type == PORT_RSA && 770 770 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) { 771 - spin_lock_irq(&up->port.lock); 771 + uart_port_lock_irq(&up->port); 772 772 773 773 mode = serial_in(up, UART_RSA_MSR); 774 774 result = !(mode & UART_RSA_MSR_FIFO); ··· 781 781 782 782 if (result) 783 783 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16; 784 - spin_unlock_irq(&up->port.lock); 784 + uart_port_unlock_irq(&up->port); 785 785 } 786 786 } 787 787 #endif /* CONFIG_SERIAL_8250_RSA */ ··· 1008 1008 serial_out(up, UART_LCR, 0); 1009 1009 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | 1010 1010 UART_FCR7_64BYTE); 1011 - status1 = serial_in(up, UART_IIR) & (UART_IIR_64BYTE_FIFO | 1012 - UART_IIR_FIFO_ENABLED); 1011 + status1 = serial_in(up, UART_IIR) & UART_IIR_FIFO_ENABLED_16750; 1013 1012 serial_out(up, UART_FCR, 0); 1014 1013 serial_out(up, UART_LCR, 0); 1015 1014 1016 - if (status1 == (UART_IIR_64BYTE_FIFO | UART_IIR_FIFO_ENABLED)) 1015 + if (status1 == UART_IIR_FIFO_ENABLED_16750) 1017 1016 up->port.type = PORT_16550A_FSL64; 1018 1017 else 1019 1018 DEBUG_AUTOCONF("Motorola 8xxx DUART "); ··· 1080 1081 */ 1081 1082 serial_out(up, UART_LCR, 0); 1082 1083 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); 1083 - status1 = serial_in(up, UART_IIR) & (UART_IIR_64BYTE_FIFO | UART_IIR_FIFO_ENABLED); 1084 + status1 = serial_in(up, UART_IIR) & UART_IIR_FIFO_ENABLED_16750; 1084 1085 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); 1085 1086 1086 1087 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 1087 1088 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); 1088 - status2 = serial_in(up, UART_IIR) & (UART_IIR_64BYTE_FIFO | UART_IIR_FIFO_ENABLED); 1089 + status2 = serial_in(up, UART_IIR) & UART_IIR_FIFO_ENABLED_16750; 1089 1090 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); 1090 1091 1091 1092 serial_out(up, UART_LCR, 0); ··· 1093 1094 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2); 1094 1095 1095 1096 if (status1 == UART_IIR_FIFO_ENABLED_16550A && 1096 - status2 == (UART_IIR_64BYTE_FIFO | UART_IIR_FIFO_ENABLED_16550A)) { 1097 + status2 == UART_IIR_FIFO_ENABLED_16750) { 1097 1098 up->port.type = PORT_16750; 1098 1099 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP; 1099 1100 return; ··· 1171 1172 * 1172 1173 * Synchronize UART_IER access against the console. 1173 1174 */ 1174 - spin_lock_irqsave(&port->lock, flags); 1175 + uart_port_lock_irqsave(port, &flags); 1175 1176 1176 1177 up->capabilities = 0; 1177 1178 up->bugs = 0; ··· 1210 1211 /* 1211 1212 * We failed; there's nothing here 1212 1213 */ 1213 - spin_unlock_irqrestore(&port->lock, flags); 1214 + uart_port_unlock_irqrestore(port, flags); 1214 1215 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ", 1215 1216 scratch2, scratch3); 1216 1217 goto out; ··· 1234 1235 status1 = serial_in(up, UART_MSR) & UART_MSR_STATUS_BITS; 1235 1236 serial8250_out_MCR(up, save_mcr); 1236 1237 if (status1 != (UART_MSR_DCD | UART_MSR_CTS)) { 1237 - spin_unlock_irqrestore(&port->lock, flags); 1238 + uart_port_unlock_irqrestore(port, flags); 1238 1239 DEBUG_AUTOCONF("LOOP test failed (%02x) ", 1239 1240 status1); 1240 1241 goto out; ··· 1303 1304 serial8250_clear_IER(up); 1304 1305 1305 1306 out_unlock: 1306 - spin_unlock_irqrestore(&port->lock, flags); 1307 + uart_port_unlock_irqrestore(port, flags); 1307 1308 1308 1309 /* 1309 1310 * Check if the device is a Fintek F81216A ··· 1343 1344 probe_irq_off(probe_irq_on()); 1344 1345 save_mcr = serial8250_in_MCR(up); 1345 1346 /* Synchronize UART_IER access against the console. */ 1346 - spin_lock_irq(&port->lock); 1347 + uart_port_lock_irq(port); 1347 1348 save_ier = serial_in(up, UART_IER); 1348 - spin_unlock_irq(&port->lock); 1349 + uart_port_unlock_irq(port); 1349 1350 serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2); 1350 1351 1351 1352 irqs = probe_irq_on(); ··· 1358 1359 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2); 1359 1360 } 1360 1361 /* Synchronize UART_IER access against the console. */ 1361 - spin_lock_irq(&port->lock); 1362 + uart_port_lock_irq(port); 1362 1363 serial_out(up, UART_IER, UART_IER_ALL_INTR); 1363 - spin_unlock_irq(&port->lock); 1364 + uart_port_unlock_irq(port); 1364 1365 serial_in(up, UART_LSR); 1365 1366 serial_in(up, UART_RX); 1366 1367 serial_in(up, UART_IIR); ··· 1371 1372 1372 1373 serial8250_out_MCR(up, save_mcr); 1373 1374 /* Synchronize UART_IER access against the console. */ 1374 - spin_lock_irq(&port->lock); 1375 + uart_port_lock_irq(port); 1375 1376 serial_out(up, UART_IER, save_ier); 1376 - spin_unlock_irq(&port->lock); 1377 + uart_port_unlock_irq(port); 1377 1378 1378 1379 if (port->flags & UPF_FOURPORT) 1379 1380 outb_p(save_ICP, ICP); ··· 1441 1442 unsigned long flags; 1442 1443 1443 1444 serial8250_rpm_get(p); 1444 - spin_lock_irqsave(&p->port.lock, flags); 1445 + uart_port_lock_irqsave(&p->port, &flags); 1445 1446 if (em485->active_timer == &em485->stop_tx_timer) { 1446 1447 p->rs485_stop_tx(p); 1447 1448 em485->active_timer = NULL; 1448 1449 em485->tx_stopped = true; 1449 1450 } 1450 - spin_unlock_irqrestore(&p->port.lock, flags); 1451 + uart_port_unlock_irqrestore(&p->port, flags); 1451 1452 serial8250_rpm_put(p); 1452 1453 1453 1454 return HRTIMER_NORESTART; ··· 1629 1630 struct uart_8250_port *p = em485->port; 1630 1631 unsigned long flags; 1631 1632 1632 - spin_lock_irqsave(&p->port.lock, flags); 1633 + uart_port_lock_irqsave(&p->port, &flags); 1633 1634 if (em485->active_timer == &em485->start_tx_timer) { 1634 1635 __start_tx(&p->port); 1635 1636 em485->active_timer = NULL; 1636 1637 } 1637 - spin_unlock_irqrestore(&p->port.lock, flags); 1638 + uart_port_unlock_irqrestore(&p->port, flags); 1638 1639 1639 1640 return HRTIMER_NORESTART; 1640 1641 } ··· 1917 1918 if (iir & UART_IIR_NO_INT) 1918 1919 return 0; 1919 1920 1920 - spin_lock_irqsave(&port->lock, flags); 1921 + uart_port_lock_irqsave(port, &flags); 1921 1922 1922 1923 status = serial_lsr_in(up); 1923 1924 ··· 1987 1988 if ((iir & UART_IIR_ID) == UART_IIR_THRI) { 1988 1989 struct uart_8250_port *up = up_to_u8250p(port); 1989 1990 1990 - spin_lock_irqsave(&port->lock, flags); 1991 + uart_port_lock_irqsave(port, &flags); 1991 1992 serial8250_tx_chars(up); 1992 - spin_unlock_irqrestore(&port->lock, flags); 1993 + uart_port_unlock_irqrestore(port, flags); 1993 1994 } 1994 1995 1995 1996 iir = serial_port_in(port, UART_IIR); ··· 2004 2005 2005 2006 serial8250_rpm_get(up); 2006 2007 2007 - spin_lock_irqsave(&port->lock, flags); 2008 + uart_port_lock_irqsave(port, &flags); 2008 2009 if (!serial8250_tx_dma_running(up) && uart_lsr_tx_empty(serial_lsr_in(up))) 2009 2010 result = TIOCSER_TEMT; 2010 - spin_unlock_irqrestore(&port->lock, flags); 2011 + uart_port_unlock_irqrestore(port, flags); 2011 2012 2012 2013 serial8250_rpm_put(up); 2013 2014 ··· 2069 2070 unsigned long flags; 2070 2071 2071 2072 serial8250_rpm_get(up); 2072 - spin_lock_irqsave(&port->lock, flags); 2073 + uart_port_lock_irqsave(port, &flags); 2073 2074 if (break_state == -1) 2074 2075 up->lcr |= UART_LCR_SBC; 2075 2076 else 2076 2077 up->lcr &= ~UART_LCR_SBC; 2077 2078 serial_port_out(port, UART_LCR, up->lcr); 2078 - spin_unlock_irqrestore(&port->lock, flags); 2079 + uart_port_unlock_irqrestore(port, flags); 2079 2080 serial8250_rpm_put(up); 2080 2081 } 2081 2082 ··· 2210 2211 * 2211 2212 * Synchronize UART_IER access against the console. 2212 2213 */ 2213 - spin_lock_irqsave(&port->lock, flags); 2214 + uart_port_lock_irqsave(port, &flags); 2214 2215 up->acr = 0; 2215 2216 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B); 2216 2217 serial_port_out(port, UART_EFR, UART_EFR_ECB); ··· 2220 2221 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B); 2221 2222 serial_port_out(port, UART_EFR, UART_EFR_ECB); 2222 2223 serial_port_out(port, UART_LCR, 0); 2223 - spin_unlock_irqrestore(&port->lock, flags); 2224 + uart_port_unlock_irqrestore(port, flags); 2224 2225 } 2225 2226 2226 2227 if (port->type == PORT_DA830) { ··· 2229 2230 * 2230 2231 * Synchronize UART_IER access against the console. 2231 2232 */ 2232 - spin_lock_irqsave(&port->lock, flags); 2233 + uart_port_lock_irqsave(port, &flags); 2233 2234 serial_port_out(port, UART_IER, 0); 2234 2235 serial_port_out(port, UART_DA830_PWREMU_MGMT, 0); 2235 - spin_unlock_irqrestore(&port->lock, flags); 2236 + uart_port_unlock_irqrestore(port, flags); 2236 2237 mdelay(10); 2237 2238 2238 2239 /* Enable Tx, Rx and free run mode */ ··· 2346 2347 * 2347 2348 * Synchronize UART_IER access against the console. 2348 2349 */ 2349 - spin_lock_irqsave(&port->lock, flags); 2350 + uart_port_lock_irqsave(port, &flags); 2350 2351 2351 2352 wait_for_xmitr(up, UART_LSR_THRE); 2352 2353 serial_port_out_sync(port, UART_IER, UART_IER_THRI); ··· 2358 2359 iir = serial_port_in(port, UART_IIR); 2359 2360 serial_port_out(port, UART_IER, 0); 2360 2361 2361 - spin_unlock_irqrestore(&port->lock, flags); 2362 + uart_port_unlock_irqrestore(port, flags); 2362 2363 2363 2364 if (port->irqflags & IRQF_SHARED) 2364 2365 enable_irq(port->irq); ··· 2381 2382 */ 2382 2383 serial_port_out(port, UART_LCR, UART_LCR_WLEN8); 2383 2384 2384 - spin_lock_irqsave(&port->lock, flags); 2385 + uart_port_lock_irqsave(port, &flags); 2385 2386 if (up->port.flags & UPF_FOURPORT) { 2386 2387 if (!up->port.irq) 2387 2388 up->port.mctrl |= TIOCM_OUT1; ··· 2427 2428 } 2428 2429 2429 2430 dont_test_tx_en: 2430 - spin_unlock_irqrestore(&port->lock, flags); 2431 + uart_port_unlock_irqrestore(port, flags); 2431 2432 2432 2433 /* 2433 2434 * Clear the interrupt registers again for luck, and clear the ··· 2498 2499 * 2499 2500 * Synchronize UART_IER access against the console. 2500 2501 */ 2501 - spin_lock_irqsave(&port->lock, flags); 2502 + uart_port_lock_irqsave(port, &flags); 2502 2503 up->ier = 0; 2503 2504 serial_port_out(port, UART_IER, 0); 2504 - spin_unlock_irqrestore(&port->lock, flags); 2505 + uart_port_unlock_irqrestore(port, flags); 2505 2506 2506 2507 synchronize_irq(port->irq); 2507 2508 2508 2509 if (up->dma) 2509 2510 serial8250_release_dma(up); 2510 2511 2511 - spin_lock_irqsave(&port->lock, flags); 2512 + uart_port_lock_irqsave(port, &flags); 2512 2513 if (port->flags & UPF_FOURPORT) { 2513 2514 /* reset interrupts on the AST Fourport board */ 2514 2515 inb((port->iobase & 0xfe0) | 0x1f); ··· 2517 2518 port->mctrl &= ~TIOCM_OUT2; 2518 2519 2519 2520 serial8250_set_mctrl(port, port->mctrl); 2520 - spin_unlock_irqrestore(&port->lock, flags); 2521 + uart_port_unlock_irqrestore(port, flags); 2521 2522 2522 2523 /* 2523 2524 * Disable break condition and FIFOs ··· 2753 2754 quot = serial8250_get_divisor(port, baud, &frac); 2754 2755 2755 2756 serial8250_rpm_get(up); 2756 - spin_lock_irqsave(&port->lock, flags); 2757 + uart_port_lock_irqsave(port, &flags); 2757 2758 2758 2759 uart_update_timeout(port, termios->c_cflag, baud); 2759 2760 2760 2761 serial8250_set_divisor(port, baud, quot, frac); 2761 2762 serial_port_out(port, UART_LCR, up->lcr); 2762 2763 2763 - spin_unlock_irqrestore(&port->lock, flags); 2764 + uart_port_unlock_irqrestore(port, flags); 2764 2765 serial8250_rpm_put(up); 2765 2766 2766 2767 out_unlock: ··· 2797 2798 * Synchronize UART_IER access against the console. 2798 2799 */ 2799 2800 serial8250_rpm_get(up); 2800 - spin_lock_irqsave(&port->lock, flags); 2801 + uart_port_lock_irqsave(port, &flags); 2801 2802 2802 2803 up->lcr = cval; /* Save computed LCR */ 2803 2804 ··· 2900 2901 serial_port_out(port, UART_FCR, up->fcr); /* set fcr */ 2901 2902 } 2902 2903 serial8250_set_mctrl(port, port->mctrl); 2903 - spin_unlock_irqrestore(&port->lock, flags); 2904 + uart_port_unlock_irqrestore(port, flags); 2904 2905 serial8250_rpm_put(up); 2905 2906 2906 2907 /* Don't rewrite B0 */ ··· 2923 2924 { 2924 2925 if (termios->c_line == N_PPS) { 2925 2926 port->flags |= UPF_HARDPPS_CD; 2926 - spin_lock_irq(&port->lock); 2927 + uart_port_lock_irq(port); 2927 2928 serial8250_enable_ms(port); 2928 - spin_unlock_irq(&port->lock); 2929 + uart_port_unlock_irq(port); 2929 2930 } else { 2930 2931 port->flags &= ~UPF_HARDPPS_CD; 2931 2932 if (!UART_ENABLE_MS(port, termios->c_cflag)) { 2932 - spin_lock_irq(&port->lock); 2933 + uart_port_lock_irq(port); 2933 2934 serial8250_disable_ms(port); 2934 - spin_unlock_irq(&port->lock); 2935 + uart_port_unlock_irq(port); 2935 2936 } 2936 2937 } 2937 2938 } ··· 3405 3406 touch_nmi_watchdog(); 3406 3407 3407 3408 if (oops_in_progress) 3408 - locked = spin_trylock_irqsave(&port->lock, flags); 3409 + locked = uart_port_trylock_irqsave(port, &flags); 3409 3410 else 3410 - spin_lock_irqsave(&port->lock, flags); 3411 + uart_port_lock_irqsave(port, &flags); 3411 3412 3412 3413 /* 3413 3414 * First save the IER then disable the interrupts ··· 3477 3478 serial8250_modem_status(up); 3478 3479 3479 3480 if (locked) 3480 - spin_unlock_irqrestore(&port->lock, flags); 3481 + uart_port_unlock_irqrestore(port, flags); 3481 3482 } 3482 3483 3483 3484 static unsigned int probe_baud(struct uart_port *port)

+1 -1

drivers/tty/serial/8250/Kconfig

··· 148 148 149 149 config SERIAL_8250_EXAR 150 150 tristate "8250/16550 Exar/Commtech PCI/PCIe device support" 151 - depends on SERIAL_8250_PCI 151 + depends on SERIAL_8250 && PCI 152 152 default SERIAL_8250 153 153 help 154 154 This builds support for XR17C1xx, XR17V3xx and some Commtech

+23 -21

drivers/tty/serial/8250/Makefile

··· 13 13 8250_base-$(CONFIG_SERIAL_8250_DWLIB) += 8250_dwlib.o 14 14 8250_base-$(CONFIG_SERIAL_8250_FINTEK) += 8250_fintek.o 15 15 8250_base-$(CONFIG_SERIAL_8250_PCILIB) += 8250_pcilib.o 16 - obj-$(CONFIG_SERIAL_8250_PARISC) += 8250_parisc.o 17 - obj-$(CONFIG_SERIAL_8250_PCI) += 8250_pci.o 18 - obj-$(CONFIG_SERIAL_8250_EXAR) += 8250_exar.o 19 - obj-$(CONFIG_SERIAL_8250_HP300) += 8250_hp300.o 20 - obj-$(CONFIG_SERIAL_8250_CS) += serial_cs.o 16 + 17 + obj-$(CONFIG_SERIAL_8250_CONSOLE) += 8250_early.o 18 + 19 + obj-$(CONFIG_SERIAL_8250_ACCENT) += 8250_accent.o 21 20 obj-$(CONFIG_SERIAL_8250_ACORN) += 8250_acorn.o 22 21 obj-$(CONFIG_SERIAL_8250_ASPEED_VUART) += 8250_aspeed_vuart.o 23 22 obj-$(CONFIG_SERIAL_8250_BCM2835AUX) += 8250_bcm2835aux.o 24 - obj-$(CONFIG_SERIAL_8250_CONSOLE) += 8250_early.o 25 - obj-$(CONFIG_SERIAL_8250_FOURPORT) += 8250_fourport.o 26 - obj-$(CONFIG_SERIAL_8250_ACCENT) += 8250_accent.o 23 + obj-$(CONFIG_SERIAL_8250_BCM7271) += 8250_bcm7271.o 27 24 obj-$(CONFIG_SERIAL_8250_BOCA) += 8250_boca.o 28 - obj-$(CONFIG_SERIAL_8250_EXAR_ST16C554) += 8250_exar_st16c554.o 29 - obj-$(CONFIG_SERIAL_8250_HUB6) += 8250_hub6.o 30 - obj-$(CONFIG_SERIAL_8250_PCI1XXXX) += 8250_pci1xxxx.o 31 - obj-$(CONFIG_SERIAL_8250_FSL) += 8250_fsl.o 32 - obj-$(CONFIG_SERIAL_8250_MEN_MCB) += 8250_men_mcb.o 33 25 obj-$(CONFIG_SERIAL_8250_DFL) += 8250_dfl.o 34 26 obj-$(CONFIG_SERIAL_8250_DW) += 8250_dw.o 35 27 obj-$(CONFIG_SERIAL_8250_EM) += 8250_em.o 36 - obj-$(CONFIG_SERIAL_8250_IOC3) += 8250_ioc3.o 37 - obj-$(CONFIG_SERIAL_8250_OMAP) += 8250_omap.o 38 - obj-$(CONFIG_SERIAL_8250_RT288X) += 8250_rt288x.o 39 - obj-$(CONFIG_SERIAL_8250_LPC18XX) += 8250_lpc18xx.o 40 - obj-$(CONFIG_SERIAL_8250_MT6577) += 8250_mtk.o 41 - obj-$(CONFIG_SERIAL_8250_UNIPHIER) += 8250_uniphier.o 28 + obj-$(CONFIG_SERIAL_8250_EXAR) += 8250_exar.o 29 + obj-$(CONFIG_SERIAL_8250_EXAR_ST16C554) += 8250_exar_st16c554.o 30 + obj-$(CONFIG_SERIAL_8250_FOURPORT) += 8250_fourport.o 31 + obj-$(CONFIG_SERIAL_8250_FSL) += 8250_fsl.o 32 + obj-$(CONFIG_SERIAL_8250_HP300) += 8250_hp300.o 33 + obj-$(CONFIG_SERIAL_8250_HUB6) += 8250_hub6.o 42 34 obj-$(CONFIG_SERIAL_8250_INGENIC) += 8250_ingenic.o 35 + obj-$(CONFIG_SERIAL_8250_IOC3) += 8250_ioc3.o 36 + obj-$(CONFIG_SERIAL_8250_LPC18XX) += 8250_lpc18xx.o 43 37 obj-$(CONFIG_SERIAL_8250_LPSS) += 8250_lpss.o 38 + obj-$(CONFIG_SERIAL_8250_MEN_MCB) += 8250_men_mcb.o 44 39 obj-$(CONFIG_SERIAL_8250_MID) += 8250_mid.o 40 + obj-$(CONFIG_SERIAL_8250_MT6577) += 8250_mtk.o 41 + obj-$(CONFIG_SERIAL_OF_PLATFORM) += 8250_of.o 42 + obj-$(CONFIG_SERIAL_8250_OMAP) += 8250_omap.o 43 + obj-$(CONFIG_SERIAL_8250_PARISC) += 8250_parisc.o 44 + obj-$(CONFIG_SERIAL_8250_PCI) += 8250_pci.o 45 + obj-$(CONFIG_SERIAL_8250_PCI1XXXX) += 8250_pci1xxxx.o 45 46 obj-$(CONFIG_SERIAL_8250_PERICOM) += 8250_pericom.o 46 47 obj-$(CONFIG_SERIAL_8250_PXA) += 8250_pxa.o 48 + obj-$(CONFIG_SERIAL_8250_RT288X) += 8250_rt288x.o 49 + obj-$(CONFIG_SERIAL_8250_CS) += serial_cs.o 50 + obj-$(CONFIG_SERIAL_8250_UNIPHIER) += 8250_uniphier.o 47 51 obj-$(CONFIG_SERIAL_8250_TEGRA) += 8250_tegra.o 48 - obj-$(CONFIG_SERIAL_8250_BCM7271) += 8250_bcm7271.o 49 - obj-$(CONFIG_SERIAL_OF_PLATFORM) += 8250_of.o 50 52 51 53 CFLAGS_8250_ingenic.o += -I$(srctree)/scripts/dtc/libfdt

+26

drivers/tty/serial/Kconfig

··· 1578 1578 but you can alter that using a kernel command line option such as 1579 1579 "console=ttyNVTx". 1580 1580 1581 + config SERIAL_ESP32 1582 + tristate "Espressif ESP32 UART support" 1583 + depends on XTENSA_PLATFORM_ESP32 || (COMPILE_TEST && OF) 1584 + select SERIAL_CORE 1585 + select SERIAL_CORE_CONSOLE 1586 + select SERIAL_EARLYCON 1587 + help 1588 + Driver for the UART controllers of the Espressif ESP32xx SoCs. 1589 + When earlycon option is enabled the following kernel command line 1590 + snippets may be used: 1591 + earlycon=esp32s3uart,mmio32,0x60000000,115200n8,40000000 1592 + earlycon=esp32uart,mmio32,0x3ff40000,115200n8 1593 + 1594 + config SERIAL_ESP32_ACM 1595 + tristate "Espressif ESP32 USB ACM gadget support" 1596 + depends on XTENSA_PLATFORM_ESP32 || (COMPILE_TEST && OF) 1597 + select SERIAL_CORE 1598 + select SERIAL_CORE_CONSOLE 1599 + select SERIAL_EARLYCON 1600 + help 1601 + Driver for the CDC ACM gadget controller of the Espressif ESP32S3 1602 + SoCs that share separate USB controller with the JTAG adapter. 1603 + When earlycon option is enabled the following kernel command line 1604 + snippet may be used: 1605 + earlycon=esp32s3acm,mmio32,0x60038000 1606 + 1581 1607 endmenu 1582 1608 1583 1609 config SERIAL_MCTRL_GPIO

+64 -62

drivers/tty/serial/Makefile

··· 24 24 # Now bring in any enabled 8250/16450/16550 type drivers. 25 25 obj-y += 8250/ 26 26 27 - obj-$(CONFIG_SERIAL_AMBA_PL010) += amba-pl010.o 28 - obj-$(CONFIG_SERIAL_AMBA_PL011) += amba-pl011.o 29 - obj-$(CONFIG_SERIAL_CLPS711X) += clps711x.o 30 - obj-$(CONFIG_SERIAL_PXA_NON8250) += pxa.o 31 - obj-$(CONFIG_SERIAL_SA1100) += sa1100.o 32 - obj-$(CONFIG_SERIAL_BCM63XX) += bcm63xx_uart.o 33 - obj-$(CONFIG_SERIAL_SAMSUNG) += samsung_tty.o 34 - obj-$(CONFIG_SERIAL_MAX3100) += max3100.o 35 - obj-$(CONFIG_SERIAL_MAX310X) += max310x.o 36 - obj-$(CONFIG_SERIAL_IP22_ZILOG) += ip22zilog.o 37 - obj-$(CONFIG_SERIAL_MUX) += mux.o 38 - obj-$(CONFIG_SERIAL_MCF) += mcf.o 39 - obj-$(CONFIG_SERIAL_PMACZILOG) += pmac_zilog.o 40 - obj-$(CONFIG_SERIAL_HS_LPC32XX) += lpc32xx_hs.o 41 - obj-$(CONFIG_SERIAL_DZ) += dz.o 42 - obj-$(CONFIG_SERIAL_ZS) += zs.o 43 - obj-$(CONFIG_SERIAL_SH_SCI) += sh-sci.o 44 - obj-$(CONFIG_SERIAL_CPM) += cpm_uart.o 45 - obj-$(CONFIG_SERIAL_IMX) += imx.o 46 - obj-$(CONFIG_SERIAL_IMX_EARLYCON) += imx_earlycon.o 47 - obj-$(CONFIG_SERIAL_MPC52xx) += mpc52xx_uart.o 48 - obj-$(CONFIG_SERIAL_ICOM) += icom.o 49 - obj-$(CONFIG_SERIAL_MESON) += meson_uart.o 50 - obj-$(CONFIG_SERIAL_SB1250_DUART) += sb1250-duart.o 51 - obj-$(CONFIG_SERIAL_SCCNXP) += sccnxp.o 52 - obj-$(CONFIG_SERIAL_SC16IS7XX_CORE) += sc16is7xx.o 53 - obj-$(CONFIG_SERIAL_JSM) += jsm/ 54 - obj-$(CONFIG_SERIAL_TXX9) += serial_txx9.o 55 - obj-$(CONFIG_SERIAL_ATMEL) += atmel_serial.o 56 - obj-$(CONFIG_SERIAL_UARTLITE) += uartlite.o 57 - obj-$(CONFIG_SERIAL_MSM) += msm_serial.o 58 - obj-$(CONFIG_SERIAL_QCOM_GENI) += qcom_geni_serial.o 59 - obj-$(CONFIG_SERIAL_OMAP) += omap-serial.o 60 - obj-$(CONFIG_SERIAL_ALTERA_UART) += altera_uart.o 61 - obj-$(CONFIG_SERIAL_ST_ASC) += st-asc.o 62 - obj-$(CONFIG_SERIAL_QE) += ucc_uart.o 63 - obj-$(CONFIG_SERIAL_TIMBERDALE) += timbuart.o 27 + obj-$(CONFIG_SERIAL_ALTERA_JTAGUART) += altera_jtaguart.o 28 + obj-$(CONFIG_SERIAL_ALTERA_UART) += altera_uart.o 29 + obj-$(CONFIG_SERIAL_AMBA_PL010) += amba-pl010.o 30 + obj-$(CONFIG_SERIAL_AMBA_PL011) += amba-pl011.o 64 31 obj-$(CONFIG_SERIAL_GRLIB_GAISLER_APBUART) += apbuart.o 65 - obj-$(CONFIG_SERIAL_ALTERA_JTAGUART) += altera_jtaguart.o 66 - obj-$(CONFIG_SERIAL_VT8500) += vt8500_serial.o 67 - obj-$(CONFIG_SERIAL_PCH_UART) += pch_uart.o 68 - obj-$(CONFIG_SERIAL_MXS_AUART) += mxs-auart.o 69 - obj-$(CONFIG_SERIAL_LANTIQ) += lantiq.o 70 - obj-$(CONFIG_SERIAL_XILINX_PS_UART) += xilinx_uartps.o 71 - obj-$(CONFIG_SERIAL_TEGRA) += serial-tegra.o 72 - obj-$(CONFIG_SERIAL_TEGRA_TCU) += tegra-tcu.o 73 - obj-$(CONFIG_SERIAL_AR933X) += ar933x_uart.o 74 - obj-$(CONFIG_SERIAL_ARC) += arc_uart.o 75 - obj-$(CONFIG_SERIAL_RP2) += rp2.o 76 - obj-$(CONFIG_SERIAL_FSL_LPUART) += fsl_lpuart.o 77 - obj-$(CONFIG_SERIAL_FSL_LINFLEXUART) += fsl_linflexuart.o 32 + obj-$(CONFIG_SERIAL_AR933X) += ar933x_uart.o 33 + obj-$(CONFIG_SERIAL_ARC) += arc_uart.o 34 + obj-$(CONFIG_SERIAL_ATMEL) += atmel_serial.o 35 + obj-$(CONFIG_SERIAL_BCM63XX) += bcm63xx_uart.o 36 + obj-$(CONFIG_SERIAL_CLPS711X) += clps711x.o 37 + obj-$(CONFIG_SERIAL_CPM) += cpm_uart.o 78 38 obj-$(CONFIG_SERIAL_CONEXANT_DIGICOLOR) += digicolor-usart.o 79 - obj-$(CONFIG_SERIAL_MEN_Z135) += men_z135_uart.o 80 - obj-$(CONFIG_SERIAL_SPRD) += sprd_serial.o 81 - obj-$(CONFIG_SERIAL_STM32) += stm32-usart.o 82 - obj-$(CONFIG_SERIAL_MVEBU_UART) += mvebu-uart.o 83 - obj-$(CONFIG_SERIAL_PIC32) += pic32_uart.o 84 - obj-$(CONFIG_SERIAL_MPS2_UART) += mps2-uart.o 85 - obj-$(CONFIG_SERIAL_OWL) += owl-uart.o 86 - obj-$(CONFIG_SERIAL_RDA) += rda-uart.o 87 - obj-$(CONFIG_SERIAL_MILBEAUT_USIO) += milbeaut_usio.o 88 - obj-$(CONFIG_SERIAL_SIFIVE) += sifive.o 89 - obj-$(CONFIG_SERIAL_LITEUART) += liteuart.o 90 - obj-$(CONFIG_SERIAL_SUNPLUS) += sunplus-uart.o 39 + obj-$(CONFIG_SERIAL_DZ) += dz.o 40 + obj-$(CONFIG_SERIAL_ESP32) += esp32_uart.o 41 + obj-$(CONFIG_SERIAL_ESP32_ACM) += esp32_acm.o 42 + obj-$(CONFIG_SERIAL_FSL_LINFLEXUART) += fsl_linflexuart.o 43 + obj-$(CONFIG_SERIAL_FSL_LPUART) += fsl_lpuart.o 44 + obj-$(CONFIG_SERIAL_ICOM) += icom.o 45 + obj-$(CONFIG_SERIAL_IMX) += imx.o 46 + obj-$(CONFIG_SERIAL_IMX_EARLYCON) += imx_earlycon.o 47 + obj-$(CONFIG_SERIAL_IP22_ZILOG) += ip22zilog.o 48 + obj-$(CONFIG_SERIAL_JSM) += jsm/ 49 + obj-$(CONFIG_SERIAL_LANTIQ) += lantiq.o 50 + obj-$(CONFIG_SERIAL_LITEUART) += liteuart.o 51 + obj-$(CONFIG_SERIAL_HS_LPC32XX) += lpc32xx_hs.o 52 + obj-$(CONFIG_SERIAL_MAX3100) += max3100.o 53 + obj-$(CONFIG_SERIAL_MAX310X) += max310x.o 54 + obj-$(CONFIG_SERIAL_MCF) += mcf.o 55 + obj-$(CONFIG_SERIAL_MEN_Z135) += men_z135_uart.o 56 + obj-$(CONFIG_SERIAL_MILBEAUT_USIO) += milbeaut_usio.o 57 + obj-$(CONFIG_SERIAL_MESON) += meson_uart.o 58 + obj-$(CONFIG_SERIAL_MPC52xx) += mpc52xx_uart.o 59 + obj-$(CONFIG_SERIAL_MPS2_UART) += mps2-uart.o 60 + obj-$(CONFIG_SERIAL_MSM) += msm_serial.o 61 + obj-$(CONFIG_SERIAL_MUX) += mux.o 62 + obj-$(CONFIG_SERIAL_MVEBU_UART) += mvebu-uart.o 63 + obj-$(CONFIG_SERIAL_MXS_AUART) += mxs-auart.o 64 + obj-$(CONFIG_SERIAL_OMAP) += omap-serial.o 65 + obj-$(CONFIG_SERIAL_OWL) += owl-uart.o 66 + obj-$(CONFIG_SERIAL_PCH_UART) += pch_uart.o 67 + obj-$(CONFIG_SERIAL_PIC32) += pic32_uart.o 68 + obj-$(CONFIG_SERIAL_PXA_NON8250) += pxa.o 69 + obj-$(CONFIG_SERIAL_PMACZILOG) += pmac_zilog.o 70 + obj-$(CONFIG_SERIAL_QCOM_GENI) += qcom_geni_serial.o 71 + obj-$(CONFIG_SERIAL_QE) += ucc_uart.o 72 + obj-$(CONFIG_SERIAL_RDA) += rda-uart.o 73 + obj-$(CONFIG_SERIAL_RP2) += rp2.o 74 + obj-$(CONFIG_SERIAL_SA1100) += sa1100.o 75 + obj-$(CONFIG_SERIAL_SAMSUNG) += samsung_tty.o 76 + obj-$(CONFIG_SERIAL_SB1250_DUART) += sb1250-duart.o 77 + obj-$(CONFIG_SERIAL_SCCNXP) += sccnxp.o 78 + obj-$(CONFIG_SERIAL_SC16IS7XX_CORE) += sc16is7xx.o 79 + obj-$(CONFIG_SERIAL_SH_SCI) += sh-sci.o 80 + obj-$(CONFIG_SERIAL_SIFIVE) += sifive.o 81 + obj-$(CONFIG_SERIAL_SPRD) += sprd_serial.o 82 + obj-$(CONFIG_SERIAL_ST_ASC) += st-asc.o 83 + obj-$(CONFIG_SERIAL_STM32) += stm32-usart.o 84 + obj-$(CONFIG_SERIAL_SUNPLUS) += sunplus-uart.o 85 + obj-$(CONFIG_SERIAL_TEGRA) += serial-tegra.o 86 + obj-$(CONFIG_SERIAL_TEGRA_TCU) += tegra-tcu.o 87 + obj-$(CONFIG_SERIAL_TIMBERDALE) += timbuart.o 88 + obj-$(CONFIG_SERIAL_TXX9) += serial_txx9.o 89 + obj-$(CONFIG_SERIAL_UARTLITE) += uartlite.o 90 + obj-$(CONFIG_SERIAL_VT8500) += vt8500_serial.o 91 + obj-$(CONFIG_SERIAL_XILINX_PS_UART) += xilinx_uartps.o 92 + obj-$(CONFIG_SERIAL_ZS) += zs.o 91 93 92 94 # GPIOLIB helpers for modem control lines 93 95 obj-$(CONFIG_SERIAL_MCTRL_GPIO) += serial_mctrl_gpio.o

+14 -14

drivers/tty/serial/altera_jtaguart.c

··· 147 147 isr = (readl(port->membase + ALTERA_JTAGUART_CONTROL_REG) >> 148 148 ALTERA_JTAGUART_CONTROL_RI_OFF) & port->read_status_mask; 149 149 150 - spin_lock(&port->lock); 150 + uart_port_lock(port); 151 151 152 152 if (isr & ALTERA_JTAGUART_CONTROL_RE_MSK) 153 153 altera_jtaguart_rx_chars(port); 154 154 if (isr & ALTERA_JTAGUART_CONTROL_WE_MSK) 155 155 altera_jtaguart_tx_chars(port); 156 156 157 - spin_unlock(&port->lock); 157 + uart_port_unlock(port); 158 158 159 159 return IRQ_RETVAL(isr); 160 160 } ··· 180 180 return ret; 181 181 } 182 182 183 - spin_lock_irqsave(&port->lock, flags); 183 + uart_port_lock_irqsave(port, &flags); 184 184 185 185 /* Enable RX interrupts now */ 186 186 port->read_status_mask = ALTERA_JTAGUART_CONTROL_RE_MSK; 187 187 writel(port->read_status_mask, 188 188 port->membase + ALTERA_JTAGUART_CONTROL_REG); 189 189 190 - spin_unlock_irqrestore(&port->lock, flags); 190 + uart_port_unlock_irqrestore(port, flags); 191 191 192 192 return 0; 193 193 } ··· 196 196 { 197 197 unsigned long flags; 198 198 199 - spin_lock_irqsave(&port->lock, flags); 199 + uart_port_lock_irqsave(port, &flags); 200 200 201 201 /* Disable all interrupts now */ 202 202 port->read_status_mask = 0; 203 203 writel(port->read_status_mask, 204 204 port->membase + ALTERA_JTAGUART_CONTROL_REG); 205 205 206 - spin_unlock_irqrestore(&port->lock, flags); 206 + uart_port_unlock_irqrestore(port, flags); 207 207 208 208 free_irq(port->irq, port); 209 209 } ··· 264 264 unsigned long flags; 265 265 u32 status; 266 266 267 - spin_lock_irqsave(&port->lock, flags); 267 + uart_port_lock_irqsave(port, &flags); 268 268 while (!altera_jtaguart_tx_space(port, &status)) { 269 - spin_unlock_irqrestore(&port->lock, flags); 269 + uart_port_unlock_irqrestore(port, flags); 270 270 271 271 if ((status & ALTERA_JTAGUART_CONTROL_AC_MSK) == 0) { 272 272 return; /* no connection activity */ 273 273 } 274 274 275 275 cpu_relax(); 276 - spin_lock_irqsave(&port->lock, flags); 276 + uart_port_lock_irqsave(port, &flags); 277 277 } 278 278 writel(c, port->membase + ALTERA_JTAGUART_DATA_REG); 279 - spin_unlock_irqrestore(&port->lock, flags); 279 + uart_port_unlock_irqrestore(port, flags); 280 280 } 281 281 #else 282 282 static void altera_jtaguart_console_putc(struct uart_port *port, unsigned char c) 283 283 { 284 284 unsigned long flags; 285 285 286 - spin_lock_irqsave(&port->lock, flags); 286 + uart_port_lock_irqsave(port, &flags); 287 287 while (!altera_jtaguart_tx_space(port, NULL)) { 288 - spin_unlock_irqrestore(&port->lock, flags); 288 + uart_port_unlock_irqrestore(port, flags); 289 289 cpu_relax(); 290 - spin_lock_irqsave(&port->lock, flags); 290 + uart_port_lock_irqsave(port, &flags); 291 291 } 292 292 writel(c, port->membase + ALTERA_JTAGUART_DATA_REG); 293 - spin_unlock_irqrestore(&port->lock, flags); 293 + uart_port_unlock_irqrestore(port, flags); 294 294 } 295 295 #endif 296 296

+10 -10

drivers/tty/serial/altera_uart.c

··· 164 164 struct altera_uart *pp = container_of(port, struct altera_uart, port); 165 165 unsigned long flags; 166 166 167 - spin_lock_irqsave(&port->lock, flags); 167 + uart_port_lock_irqsave(port, &flags); 168 168 if (break_state == -1) 169 169 pp->imr |= ALTERA_UART_CONTROL_TRBK_MSK; 170 170 else 171 171 pp->imr &= ~ALTERA_UART_CONTROL_TRBK_MSK; 172 172 altera_uart_update_ctrl_reg(pp); 173 - spin_unlock_irqrestore(&port->lock, flags); 173 + uart_port_unlock_irqrestore(port, flags); 174 174 } 175 175 176 176 static void altera_uart_set_termios(struct uart_port *port, ··· 187 187 tty_termios_copy_hw(termios, old); 188 188 tty_termios_encode_baud_rate(termios, baud, baud); 189 189 190 - spin_lock_irqsave(&port->lock, flags); 190 + uart_port_lock_irqsave(port, &flags); 191 191 uart_update_timeout(port, termios->c_cflag, baud); 192 192 altera_uart_writel(port, baudclk, ALTERA_UART_DIVISOR_REG); 193 - spin_unlock_irqrestore(&port->lock, flags); 193 + uart_port_unlock_irqrestore(port, flags); 194 194 195 195 /* 196 196 * FIXME: port->read_status_mask and port->ignore_status_mask ··· 264 264 265 265 isr = altera_uart_readl(port, ALTERA_UART_STATUS_REG) & pp->imr; 266 266 267 - spin_lock_irqsave(&port->lock, flags); 267 + uart_port_lock_irqsave(port, &flags); 268 268 if (isr & ALTERA_UART_STATUS_RRDY_MSK) 269 269 altera_uart_rx_chars(port); 270 270 if (isr & ALTERA_UART_STATUS_TRDY_MSK) 271 271 altera_uart_tx_chars(port); 272 - spin_unlock_irqrestore(&port->lock, flags); 272 + uart_port_unlock_irqrestore(port, flags); 273 273 274 274 return IRQ_RETVAL(isr); 275 275 } ··· 313 313 } 314 314 } 315 315 316 - spin_lock_irqsave(&port->lock, flags); 316 + uart_port_lock_irqsave(port, &flags); 317 317 318 318 /* Enable RX interrupts now */ 319 319 pp->imr = ALTERA_UART_CONTROL_RRDY_MSK; 320 320 altera_uart_update_ctrl_reg(pp); 321 321 322 - spin_unlock_irqrestore(&port->lock, flags); 322 + uart_port_unlock_irqrestore(port, flags); 323 323 324 324 return 0; 325 325 } ··· 329 329 struct altera_uart *pp = container_of(port, struct altera_uart, port); 330 330 unsigned long flags; 331 331 332 - spin_lock_irqsave(&port->lock, flags); 332 + uart_port_lock_irqsave(port, &flags); 333 333 334 334 /* Disable all interrupts now */ 335 335 pp->imr = 0; 336 336 altera_uart_update_ctrl_reg(pp); 337 337 338 - spin_unlock_irqrestore(&port->lock, flags); 338 + uart_port_unlock_irqrestore(port, flags); 339 339 340 340 if (port->irq) 341 341 free_irq(port->irq, port);

+10 -10

drivers/tty/serial/amba-pl010.c

··· 207 207 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; 208 208 int handled = 0; 209 209 210 - spin_lock(&port->lock); 210 + uart_port_lock(port); 211 211 212 212 status = readb(port->membase + UART010_IIR); 213 213 if (status) { ··· 228 228 handled = 1; 229 229 } 230 230 231 - spin_unlock(&port->lock); 231 + uart_port_unlock(port); 232 232 233 233 return IRQ_RETVAL(handled); 234 234 } ··· 270 270 unsigned long flags; 271 271 unsigned int lcr_h; 272 272 273 - spin_lock_irqsave(&port->lock, flags); 273 + uart_port_lock_irqsave(port, &flags); 274 274 lcr_h = readb(port->membase + UART010_LCRH); 275 275 if (break_state == -1) 276 276 lcr_h |= UART01x_LCRH_BRK; 277 277 else 278 278 lcr_h &= ~UART01x_LCRH_BRK; 279 279 writel(lcr_h, port->membase + UART010_LCRH); 280 - spin_unlock_irqrestore(&port->lock, flags); 280 + uart_port_unlock_irqrestore(port, flags); 281 281 } 282 282 283 283 static int pl010_startup(struct uart_port *port) ··· 385 385 if (port->fifosize > 1) 386 386 lcr_h |= UART01x_LCRH_FEN; 387 387 388 - spin_lock_irqsave(&port->lock, flags); 388 + uart_port_lock_irqsave(port, &flags); 389 389 390 390 /* 391 391 * Update the per-port timeout. ··· 438 438 writel(lcr_h, port->membase + UART010_LCRH); 439 439 writel(old_cr, port->membase + UART010_CR); 440 440 441 - spin_unlock_irqrestore(&port->lock, flags); 441 + uart_port_unlock_irqrestore(port, flags); 442 442 } 443 443 444 444 static void pl010_set_ldisc(struct uart_port *port, struct ktermios *termios) 445 445 { 446 446 if (termios->c_line == N_PPS) { 447 447 port->flags |= UPF_HARDPPS_CD; 448 - spin_lock_irq(&port->lock); 448 + uart_port_lock_irq(port); 449 449 pl010_enable_ms(port); 450 - spin_unlock_irq(&port->lock); 450 + uart_port_unlock_irq(port); 451 451 } else { 452 452 port->flags &= ~UPF_HARDPPS_CD; 453 453 if (!UART_ENABLE_MS(port, termios->c_cflag)) { 454 - spin_lock_irq(&port->lock); 454 + uart_port_lock_irq(port); 455 455 pl010_disable_ms(port); 456 - spin_unlock_irq(&port->lock); 456 + uart_port_unlock_irq(port); 457 457 } 458 458 } 459 459 }

+37 -37

drivers/tty/serial/amba-pl011.c

··· 345 345 flag = TTY_FRAME; 346 346 } 347 347 348 - spin_unlock(&uap->port.lock); 348 + uart_port_unlock(&uap->port); 349 349 sysrq = uart_handle_sysrq_char(&uap->port, ch & 255); 350 - spin_lock(&uap->port.lock); 350 + uart_port_lock(&uap->port); 351 351 352 352 if (!sysrq) 353 353 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag); ··· 421 421 422 422 /* We need platform data */ 423 423 if (!plat || !plat->dma_filter) { 424 - dev_info(uap->port.dev, "no DMA platform data\n"); 424 + dev_dbg(uap->port.dev, "no DMA platform data\n"); 425 425 return; 426 426 } 427 427 ··· 550 550 unsigned long flags; 551 551 u16 dmacr; 552 552 553 - spin_lock_irqsave(&uap->port.lock, flags); 553 + uart_port_lock_irqsave(&uap->port, &flags); 554 554 if (uap->dmatx.queued) 555 555 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1, 556 556 DMA_TO_DEVICE); ··· 571 571 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) || 572 572 uart_circ_empty(&uap->port.state->xmit)) { 573 573 uap->dmatx.queued = false; 574 - spin_unlock_irqrestore(&uap->port.lock, flags); 574 + uart_port_unlock_irqrestore(&uap->port, flags); 575 575 return; 576 576 } 577 577 ··· 582 582 */ 583 583 pl011_start_tx_pio(uap); 584 584 585 - spin_unlock_irqrestore(&uap->port.lock, flags); 585 + uart_port_unlock_irqrestore(&uap->port, flags); 586 586 } 587 587 588 588 /* ··· 1009 1009 * routine to flush out the secondary DMA buffer while 1010 1010 * we immediately trigger the next DMA job. 1011 1011 */ 1012 - spin_lock_irq(&uap->port.lock); 1012 + uart_port_lock_irq(&uap->port); 1013 1013 /* 1014 1014 * Rx data can be taken by the UART interrupts during 1015 1015 * the DMA irq handler. So we check the residue here. ··· 1025 1025 ret = pl011_dma_rx_trigger_dma(uap); 1026 1026 1027 1027 pl011_dma_rx_chars(uap, pending, lastbuf, false); 1028 - spin_unlock_irq(&uap->port.lock); 1028 + uart_port_unlock_irq(&uap->port); 1029 1029 /* 1030 1030 * Do this check after we picked the DMA chars so we don't 1031 1031 * get some IRQ immediately from RX. ··· 1091 1091 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies) 1092 1092 > uap->dmarx.poll_timeout) { 1093 1093 1094 - spin_lock_irqsave(&uap->port.lock, flags); 1094 + uart_port_lock_irqsave(&uap->port, &flags); 1095 1095 pl011_dma_rx_stop(uap); 1096 1096 uap->im |= UART011_RXIM; 1097 1097 pl011_write(uap->im, uap, REG_IMSC); 1098 - spin_unlock_irqrestore(&uap->port.lock, flags); 1098 + uart_port_unlock_irqrestore(&uap->port, flags); 1099 1099 1100 1100 uap->dmarx.running = false; 1101 1101 dmaengine_terminate_all(rxchan); ··· 1191 1191 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy) 1192 1192 cpu_relax(); 1193 1193 1194 - spin_lock_irq(&uap->port.lock); 1194 + uart_port_lock_irq(&uap->port); 1195 1195 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE); 1196 1196 pl011_write(uap->dmacr, uap, REG_DMACR); 1197 - spin_unlock_irq(&uap->port.lock); 1197 + uart_port_unlock_irq(&uap->port); 1198 1198 1199 1199 if (uap->using_tx_dma) { 1200 1200 /* In theory, this should already be done by pl011_dma_flush_buffer */ ··· 1374 1374 { 1375 1375 unsigned long flags; 1376 1376 1377 - spin_lock_irqsave(&port->lock, flags); 1377 + uart_port_lock_irqsave(port, &flags); 1378 1378 pl011_stop_rx(port); 1379 - spin_unlock_irqrestore(&port->lock, flags); 1379 + uart_port_unlock_irqrestore(port, flags); 1380 1380 } 1381 1381 1382 1382 static void pl011_enable_ms(struct uart_port *port) ··· 1394 1394 { 1395 1395 pl011_fifo_to_tty(uap); 1396 1396 1397 - spin_unlock(&uap->port.lock); 1397 + uart_port_unlock(&uap->port); 1398 1398 tty_flip_buffer_push(&uap->port.state->port); 1399 1399 /* 1400 1400 * If we were temporarily out of DMA mode for a while, ··· 1419 1419 #endif 1420 1420 } 1421 1421 } 1422 - spin_lock(&uap->port.lock); 1422 + uart_port_lock(&uap->port); 1423 1423 } 1424 1424 1425 1425 static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c, ··· 1555 1555 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; 1556 1556 int handled = 0; 1557 1557 1558 - spin_lock_irqsave(&uap->port.lock, flags); 1558 + uart_port_lock_irqsave(&uap->port, &flags); 1559 1559 status = pl011_read(uap, REG_RIS) & uap->im; 1560 1560 if (status) { 1561 1561 do { ··· 1585 1585 handled = 1; 1586 1586 } 1587 1587 1588 - spin_unlock_irqrestore(&uap->port.lock, flags); 1588 + uart_port_unlock_irqrestore(&uap->port, flags); 1589 1589 1590 1590 return IRQ_RETVAL(handled); 1591 1591 } ··· 1657 1657 unsigned long flags; 1658 1658 unsigned int lcr_h; 1659 1659 1660 - spin_lock_irqsave(&uap->port.lock, flags); 1660 + uart_port_lock_irqsave(&uap->port, &flags); 1661 1661 lcr_h = pl011_read(uap, REG_LCRH_TX); 1662 1662 if (break_state == -1) 1663 1663 lcr_h |= UART01x_LCRH_BRK; 1664 1664 else 1665 1665 lcr_h &= ~UART01x_LCRH_BRK; 1666 1666 pl011_write(lcr_h, uap, REG_LCRH_TX); 1667 - spin_unlock_irqrestore(&uap->port.lock, flags); 1667 + uart_port_unlock_irqrestore(&uap->port, flags); 1668 1668 } 1669 1669 1670 1670 #ifdef CONFIG_CONSOLE_POLL ··· 1803 1803 unsigned long flags; 1804 1804 unsigned int i; 1805 1805 1806 - spin_lock_irqsave(&uap->port.lock, flags); 1806 + uart_port_lock_irqsave(&uap->port, &flags); 1807 1807 1808 1808 /* Clear out any spuriously appearing RX interrupts */ 1809 1809 pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR); ··· 1825 1825 if (!pl011_dma_rx_running(uap)) 1826 1826 uap->im |= UART011_RXIM; 1827 1827 pl011_write(uap->im, uap, REG_IMSC); 1828 - spin_unlock_irqrestore(&uap->port.lock, flags); 1828 + uart_port_unlock_irqrestore(&uap->port, flags); 1829 1829 } 1830 1830 1831 1831 static void pl011_unthrottle_rx(struct uart_port *port) ··· 1833 1833 struct uart_amba_port *uap = container_of(port, struct uart_amba_port, port); 1834 1834 unsigned long flags; 1835 1835 1836 - spin_lock_irqsave(&uap->port.lock, flags); 1836 + uart_port_lock_irqsave(&uap->port, &flags); 1837 1837 1838 1838 uap->im = UART011_RTIM; 1839 1839 if (!pl011_dma_rx_running(uap)) ··· 1841 1841 1842 1842 pl011_write(uap->im, uap, REG_IMSC); 1843 1843 1844 - spin_unlock_irqrestore(&uap->port.lock, flags); 1844 + uart_port_unlock_irqrestore(&uap->port, flags); 1845 1845 } 1846 1846 1847 1847 static int pl011_startup(struct uart_port *port) ··· 1861 1861 1862 1862 pl011_write(uap->vendor->ifls, uap, REG_IFLS); 1863 1863 1864 - spin_lock_irq(&uap->port.lock); 1864 + uart_port_lock_irq(&uap->port); 1865 1865 1866 1866 cr = pl011_read(uap, REG_CR); 1867 1867 cr &= UART011_CR_RTS | UART011_CR_DTR; ··· 1872 1872 1873 1873 pl011_write(cr, uap, REG_CR); 1874 1874 1875 - spin_unlock_irq(&uap->port.lock); 1875 + uart_port_unlock_irq(&uap->port); 1876 1876 1877 1877 /* 1878 1878 * initialise the old status of the modem signals ··· 1933 1933 unsigned int cr; 1934 1934 1935 1935 uap->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); 1936 - spin_lock_irq(&uap->port.lock); 1936 + uart_port_lock_irq(&uap->port); 1937 1937 cr = pl011_read(uap, REG_CR); 1938 1938 cr &= UART011_CR_RTS | UART011_CR_DTR; 1939 1939 cr |= UART01x_CR_UARTEN | UART011_CR_TXE; 1940 1940 pl011_write(cr, uap, REG_CR); 1941 - spin_unlock_irq(&uap->port.lock); 1941 + uart_port_unlock_irq(&uap->port); 1942 1942 1943 1943 /* 1944 1944 * disable break condition and fifos ··· 1950 1950 1951 1951 static void pl011_disable_interrupts(struct uart_amba_port *uap) 1952 1952 { 1953 - spin_lock_irq(&uap->port.lock); 1953 + uart_port_lock_irq(&uap->port); 1954 1954 1955 1955 /* mask all interrupts and clear all pending ones */ 1956 1956 uap->im = 0; 1957 1957 pl011_write(uap->im, uap, REG_IMSC); 1958 1958 pl011_write(0xffff, uap, REG_ICR); 1959 1959 1960 - spin_unlock_irq(&uap->port.lock); 1960 + uart_port_unlock_irq(&uap->port); 1961 1961 } 1962 1962 1963 1963 static void pl011_shutdown(struct uart_port *port) ··· 2102 2102 2103 2103 bits = tty_get_frame_size(termios->c_cflag); 2104 2104 2105 - spin_lock_irqsave(&port->lock, flags); 2105 + uart_port_lock_irqsave(port, &flags); 2106 2106 2107 2107 /* 2108 2108 * Update the per-port timeout. ··· 2176 2176 old_cr |= UART011_CR_RXE; 2177 2177 pl011_write(old_cr, uap, REG_CR); 2178 2178 2179 - spin_unlock_irqrestore(&port->lock, flags); 2179 + uart_port_unlock_irqrestore(port, flags); 2180 2180 } 2181 2181 2182 2182 static void ··· 2194 2194 termios->c_cflag &= ~(CMSPAR | CRTSCTS); 2195 2195 termios->c_cflag |= CS8 | CLOCAL; 2196 2196 2197 - spin_lock_irqsave(&port->lock, flags); 2197 + uart_port_lock_irqsave(port, &flags); 2198 2198 uart_update_timeout(port, CS8, uap->fixed_baud); 2199 2199 pl011_setup_status_masks(port, termios); 2200 - spin_unlock_irqrestore(&port->lock, flags); 2200 + uart_port_unlock_irqrestore(port, flags); 2201 2201 } 2202 2202 2203 2203 static const char *pl011_type(struct uart_port *port) ··· 2336 2336 if (uap->port.sysrq) 2337 2337 locked = 0; 2338 2338 else if (oops_in_progress) 2339 - locked = spin_trylock(&uap->port.lock); 2339 + locked = uart_port_trylock(&uap->port); 2340 2340 else 2341 - spin_lock(&uap->port.lock); 2341 + uart_port_lock(&uap->port); 2342 2342 2343 2343 /* 2344 2344 * First save the CR then disable the interrupts ··· 2364 2364 pl011_write(old_cr, uap, REG_CR); 2365 2365 2366 2366 if (locked) 2367 - spin_unlock(&uap->port.lock); 2367 + uart_port_unlock(&uap->port); 2368 2368 local_irq_restore(flags); 2369 2369 2370 2370 clk_disable(uap->clk);

+4 -4

drivers/tty/serial/apbuart.c

··· 133 133 struct uart_port *port = dev_id; 134 134 unsigned int status; 135 135 136 - spin_lock(&port->lock); 136 + uart_port_lock(port); 137 137 138 138 status = UART_GET_STATUS(port); 139 139 if (status & UART_STATUS_DR) ··· 141 141 if (status & UART_STATUS_THE) 142 142 apbuart_tx_chars(port); 143 143 144 - spin_unlock(&port->lock); 144 + uart_port_unlock(port); 145 145 146 146 return IRQ_HANDLED; 147 147 } ··· 228 228 if (termios->c_cflag & CRTSCTS) 229 229 cr |= UART_CTRL_FL; 230 230 231 - spin_lock_irqsave(&port->lock, flags); 231 + uart_port_lock_irqsave(port, &flags); 232 232 233 233 /* Update the per-port timeout. */ 234 234 uart_update_timeout(port, termios->c_cflag, baud); ··· 251 251 UART_PUT_SCAL(port, quot); 252 252 UART_PUT_CTRL(port, cr); 253 253 254 - spin_unlock_irqrestore(&port->lock, flags); 254 + uart_port_unlock_irqrestore(port, flags); 255 255 } 256 256 257 257 static const char *apbuart_type(struct uart_port *port)

+13 -13

drivers/tty/serial/ar933x_uart.c

··· 133 133 unsigned long flags; 134 134 unsigned int rdata; 135 135 136 - spin_lock_irqsave(&up->port.lock, flags); 136 + uart_port_lock_irqsave(&up->port, &flags); 137 137 rdata = ar933x_uart_read(up, AR933X_UART_DATA_REG); 138 - spin_unlock_irqrestore(&up->port.lock, flags); 138 + uart_port_unlock_irqrestore(&up->port, flags); 139 139 140 140 return (rdata & AR933X_UART_DATA_TX_CSR) ? 0 : TIOCSER_TEMT; 141 141 } ··· 220 220 container_of(port, struct ar933x_uart_port, port); 221 221 unsigned long flags; 222 222 223 - spin_lock_irqsave(&up->port.lock, flags); 223 + uart_port_lock_irqsave(&up->port, &flags); 224 224 if (break_state == -1) 225 225 ar933x_uart_rmw_set(up, AR933X_UART_CS_REG, 226 226 AR933X_UART_CS_TX_BREAK); 227 227 else 228 228 ar933x_uart_rmw_clear(up, AR933X_UART_CS_REG, 229 229 AR933X_UART_CS_TX_BREAK); 230 - spin_unlock_irqrestore(&up->port.lock, flags); 230 + uart_port_unlock_irqrestore(&up->port, flags); 231 231 } 232 232 233 233 /* ··· 318 318 * Ok, we're now changing the port state. Do it with 319 319 * interrupts disabled. 320 320 */ 321 - spin_lock_irqsave(&up->port.lock, flags); 321 + uart_port_lock_irqsave(&up->port, &flags); 322 322 323 323 /* disable the UART */ 324 324 ar933x_uart_rmw_clear(up, AR933X_UART_CS_REG, ··· 352 352 AR933X_UART_CS_IF_MODE_M << AR933X_UART_CS_IF_MODE_S, 353 353 AR933X_UART_CS_IF_MODE_DCE << AR933X_UART_CS_IF_MODE_S); 354 354 355 - spin_unlock_irqrestore(&up->port.lock, flags); 355 + uart_port_unlock_irqrestore(&up->port, flags); 356 356 357 357 if (tty_termios_baud_rate(new)) 358 358 tty_termios_encode_baud_rate(new, baud, baud); ··· 450 450 if ((status & AR933X_UART_CS_HOST_INT) == 0) 451 451 return IRQ_NONE; 452 452 453 - spin_lock(&up->port.lock); 453 + uart_port_lock(&up->port); 454 454 455 455 status = ar933x_uart_read(up, AR933X_UART_INT_REG); 456 456 status &= ar933x_uart_read(up, AR933X_UART_INT_EN_REG); ··· 468 468 ar933x_uart_tx_chars(up); 469 469 } 470 470 471 - spin_unlock(&up->port.lock); 471 + uart_port_unlock(&up->port); 472 472 473 473 return IRQ_HANDLED; 474 474 } ··· 485 485 if (ret) 486 486 return ret; 487 487 488 - spin_lock_irqsave(&up->port.lock, flags); 488 + uart_port_lock_irqsave(&up->port, &flags); 489 489 490 490 /* Enable HOST interrupts */ 491 491 ar933x_uart_rmw_set(up, AR933X_UART_CS_REG, ··· 498 498 /* Enable RX interrupts */ 499 499 ar933x_uart_start_rx_interrupt(up); 500 500 501 - spin_unlock_irqrestore(&up->port.lock, flags); 501 + uart_port_unlock_irqrestore(&up->port, flags); 502 502 503 503 return 0; 504 504 } ··· 632 632 if (up->port.sysrq) 633 633 locked = 0; 634 634 else if (oops_in_progress) 635 - locked = spin_trylock(&up->port.lock); 635 + locked = uart_port_trylock(&up->port); 636 636 else 637 - spin_lock(&up->port.lock); 637 + uart_port_lock(&up->port); 638 638 639 639 /* 640 640 * First save the IER then disable the interrupts ··· 654 654 ar933x_uart_write(up, AR933X_UART_INT_REG, AR933X_UART_INT_ALLINTS); 655 655 656 656 if (locked) 657 - spin_unlock(&up->port.lock); 657 + uart_port_unlock(&up->port); 658 658 659 659 local_irq_restore(flags); 660 660 }

+8 -8

drivers/tty/serial/arc_uart.c

··· 279 279 if (status & RXIENB) { 280 280 281 281 /* already in ISR, no need of xx_irqsave */ 282 - spin_lock(&port->lock); 282 + uart_port_lock(port); 283 283 arc_serial_rx_chars(port, status); 284 - spin_unlock(&port->lock); 284 + uart_port_unlock(port); 285 285 } 286 286 287 287 if ((status & TXIENB) && (status & TXEMPTY)) { ··· 291 291 */ 292 292 UART_TX_IRQ_DISABLE(port); 293 293 294 - spin_lock(&port->lock); 294 + uart_port_lock(port); 295 295 296 296 if (!uart_tx_stopped(port)) 297 297 arc_serial_tx_chars(port); 298 298 299 - spin_unlock(&port->lock); 299 + uart_port_unlock(port); 300 300 } 301 301 302 302 return IRQ_HANDLED; ··· 366 366 uartl = hw_val & 0xFF; 367 367 uarth = (hw_val >> 8) & 0xFF; 368 368 369 - spin_lock_irqsave(&port->lock, flags); 369 + uart_port_lock_irqsave(port, &flags); 370 370 371 371 UART_ALL_IRQ_DISABLE(port); 372 372 ··· 391 391 392 392 uart_update_timeout(port, new->c_cflag, baud); 393 393 394 - spin_unlock_irqrestore(&port->lock, flags); 394 + uart_port_unlock_irqrestore(port, flags); 395 395 } 396 396 397 397 static const char *arc_serial_type(struct uart_port *port) ··· 521 521 struct uart_port *port = &arc_uart_ports[co->index].port; 522 522 unsigned long flags; 523 523 524 - spin_lock_irqsave(&port->lock, flags); 524 + uart_port_lock_irqsave(port, &flags); 525 525 uart_console_write(port, s, count, arc_serial_console_putchar); 526 - spin_unlock_irqrestore(&port->lock, flags); 526 + uart_port_unlock_irqrestore(port, flags); 527 527 } 528 528 529 529 static struct console arc_console = {

+12 -12

drivers/tty/serial/atmel_serial.c

··· 861 861 struct dma_chan *chan = atmel_port->chan_tx; 862 862 unsigned long flags; 863 863 864 - spin_lock_irqsave(&port->lock, flags); 864 + uart_port_lock_irqsave(port, &flags); 865 865 866 866 if (chan) 867 867 dmaengine_terminate_all(chan); ··· 893 893 atmel_port->tx_done_mask); 894 894 } 895 895 896 - spin_unlock_irqrestore(&port->lock, flags); 896 + uart_port_unlock_irqrestore(port, flags); 897 897 } 898 898 899 899 static void atmel_release_tx_dma(struct uart_port *port) ··· 1711 1711 struct uart_port *port = &atmel_port->uart; 1712 1712 1713 1713 /* The interrupt handler does not take the lock */ 1714 - spin_lock(&port->lock); 1714 + uart_port_lock(port); 1715 1715 atmel_port->schedule_rx(port); 1716 - spin_unlock(&port->lock); 1716 + uart_port_unlock(port); 1717 1717 } 1718 1718 1719 1719 static void atmel_tasklet_tx_func(struct tasklet_struct *t) ··· 1723 1723 struct uart_port *port = &atmel_port->uart; 1724 1724 1725 1725 /* The interrupt handler does not take the lock */ 1726 - spin_lock(&port->lock); 1726 + uart_port_lock(port); 1727 1727 atmel_port->schedule_tx(port); 1728 - spin_unlock(&port->lock); 1728 + uart_port_unlock(port); 1729 1729 } 1730 1730 1731 1731 static void atmel_init_property(struct atmel_uart_port *atmel_port, ··· 2175 2175 } else 2176 2176 mode |= ATMEL_US_PAR_NONE; 2177 2177 2178 - spin_lock_irqsave(&port->lock, flags); 2178 + uart_port_lock_irqsave(port, &flags); 2179 2179 2180 2180 port->read_status_mask = ATMEL_US_OVRE; 2181 2181 if (termios->c_iflag & INPCK) ··· 2377 2377 else 2378 2378 atmel_disable_ms(port); 2379 2379 2380 - spin_unlock_irqrestore(&port->lock, flags); 2380 + uart_port_unlock_irqrestore(port, flags); 2381 2381 } 2382 2382 2383 2383 static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios) 2384 2384 { 2385 2385 if (termios->c_line == N_PPS) { 2386 2386 port->flags |= UPF_HARDPPS_CD; 2387 - spin_lock_irq(&port->lock); 2387 + uart_port_lock_irq(port); 2388 2388 atmel_enable_ms(port); 2389 - spin_unlock_irq(&port->lock); 2389 + uart_port_unlock_irq(port); 2390 2390 } else { 2391 2391 port->flags &= ~UPF_HARDPPS_CD; 2392 2392 if (!UART_ENABLE_MS(port, termios->c_cflag)) { 2393 - spin_lock_irq(&port->lock); 2393 + uart_port_lock_irq(port); 2394 2394 atmel_disable_ms(port); 2395 - spin_unlock_irq(&port->lock); 2395 + uart_port_unlock_irq(port); 2396 2396 } 2397 2397 } 2398 2398 }

+11 -11

drivers/tty/serial/bcm63xx_uart.c

··· 201 201 unsigned long flags; 202 202 unsigned int val; 203 203 204 - spin_lock_irqsave(&port->lock, flags); 204 + uart_port_lock_irqsave(port, &flags); 205 205 206 206 val = bcm_uart_readl(port, UART_CTL_REG); 207 207 if (ctl) ··· 210 210 val &= ~UART_CTL_XMITBRK_MASK; 211 211 bcm_uart_writel(port, val, UART_CTL_REG); 212 212 213 - spin_unlock_irqrestore(&port->lock, flags); 213 + uart_port_unlock_irqrestore(port, flags); 214 214 } 215 215 216 216 /* ··· 332 332 unsigned int irqstat; 333 333 334 334 port = dev_id; 335 - spin_lock(&port->lock); 335 + uart_port_lock(port); 336 336 337 337 irqstat = bcm_uart_readl(port, UART_IR_REG); 338 338 if (irqstat & UART_RX_INT_STAT) ··· 353 353 estat & UART_EXTINP_DCD_MASK); 354 354 } 355 355 356 - spin_unlock(&port->lock); 356 + uart_port_unlock(port); 357 357 return IRQ_HANDLED; 358 358 } 359 359 ··· 451 451 { 452 452 unsigned long flags; 453 453 454 - spin_lock_irqsave(&port->lock, flags); 454 + uart_port_lock_irqsave(port, &flags); 455 455 bcm_uart_writel(port, 0, UART_IR_REG); 456 - spin_unlock_irqrestore(&port->lock, flags); 456 + uart_port_unlock_irqrestore(port, flags); 457 457 458 458 bcm_uart_disable(port); 459 459 bcm_uart_flush(port); ··· 470 470 unsigned long flags; 471 471 int tries; 472 472 473 - spin_lock_irqsave(&port->lock, flags); 473 + uart_port_lock_irqsave(port, &flags); 474 474 475 475 /* Drain the hot tub fully before we power it off for the winter. */ 476 476 for (tries = 3; !bcm_uart_tx_empty(port) && tries; tries--) ··· 546 546 547 547 uart_update_timeout(port, new->c_cflag, baud); 548 548 bcm_uart_enable(port); 549 - spin_unlock_irqrestore(&port->lock, flags); 549 + uart_port_unlock_irqrestore(port, flags); 550 550 } 551 551 552 552 /* ··· 712 712 /* bcm_uart_interrupt() already took the lock */ 713 713 locked = 0; 714 714 } else if (oops_in_progress) { 715 - locked = spin_trylock(&port->lock); 715 + locked = uart_port_trylock(port); 716 716 } else { 717 - spin_lock(&port->lock); 717 + uart_port_lock(port); 718 718 locked = 1; 719 719 } 720 720 ··· 725 725 wait_for_xmitr(port); 726 726 727 727 if (locked) 728 - spin_unlock(&port->lock); 728 + uart_port_unlock(port); 729 729 local_irq_restore(flags); 730 730 } 731 731

+4 -4

drivers/tty/serial/cpm_uart.c

··· 569 569 if ((termios->c_cflag & CREAD) == 0) 570 570 port->read_status_mask &= ~BD_SC_EMPTY; 571 571 572 - spin_lock_irqsave(&port->lock, flags); 572 + uart_port_lock_irqsave(port, &flags); 573 573 574 574 if (IS_SMC(pinfo)) { 575 575 unsigned int bits = tty_get_frame_size(termios->c_cflag); ··· 609 609 clk_set_rate(pinfo->clk, baud); 610 610 else 611 611 cpm_setbrg(pinfo->brg - 1, baud); 612 - spin_unlock_irqrestore(&port->lock, flags); 612 + uart_port_unlock_irqrestore(port, flags); 613 613 } 614 614 615 615 static const char *cpm_uart_type(struct uart_port *port) ··· 1386 1386 cpm_uart_early_write(pinfo, s, count, true); 1387 1387 local_irq_restore(flags); 1388 1388 } else { 1389 - spin_lock_irqsave(&pinfo->port.lock, flags); 1389 + uart_port_lock_irqsave(&pinfo->port, &flags); 1390 1390 cpm_uart_early_write(pinfo, s, count, true); 1391 - spin_unlock_irqrestore(&pinfo->port.lock, flags); 1391 + uart_port_unlock_irqrestore(&pinfo->port, flags); 1392 1392 } 1393 1393 } 1394 1394

+9 -9

drivers/tty/serial/digicolor-usart.c

··· 133 133 { 134 134 unsigned long flags; 135 135 136 - spin_lock_irqsave(&port->lock, flags); 136 + uart_port_lock_irqsave(port, &flags); 137 137 138 138 while (1) { 139 139 u8 status, ch, ch_flag; ··· 172 172 ch_flag); 173 173 } 174 174 175 - spin_unlock_irqrestore(&port->lock, flags); 175 + uart_port_unlock_irqrestore(port, flags); 176 176 177 177 tty_flip_buffer_push(&port->state->port); 178 178 } ··· 185 185 if (digicolor_uart_tx_full(port)) 186 186 return; 187 187 188 - spin_lock_irqsave(&port->lock, flags); 188 + uart_port_lock_irqsave(port, &flags); 189 189 190 190 if (port->x_char) { 191 191 writeb_relaxed(port->x_char, port->membase + UA_EMI_REC); ··· 211 211 uart_write_wakeup(port); 212 212 213 213 out: 214 - spin_unlock_irqrestore(&port->lock, flags); 214 + uart_port_unlock_irqrestore(port, flags); 215 215 } 216 216 217 217 static irqreturn_t digicolor_uart_int(int irq, void *dev_id) ··· 333 333 port->ignore_status_mask |= UA_STATUS_OVERRUN_ERR 334 334 | UA_STATUS_PARITY_ERR | UA_STATUS_FRAME_ERR; 335 335 336 - spin_lock_irqsave(&port->lock, flags); 336 + uart_port_lock_irqsave(port, &flags); 337 337 338 338 uart_update_timeout(port, termios->c_cflag, baud); 339 339 ··· 341 341 writeb_relaxed(divisor & 0xff, port->membase + UA_HBAUD_LO); 342 342 writeb_relaxed(divisor >> 8, port->membase + UA_HBAUD_HI); 343 343 344 - spin_unlock_irqrestore(&port->lock, flags); 344 + uart_port_unlock_irqrestore(port, flags); 345 345 } 346 346 347 347 static const char *digicolor_uart_type(struct uart_port *port) ··· 398 398 int locked = 1; 399 399 400 400 if (oops_in_progress) 401 - locked = spin_trylock_irqsave(&port->lock, flags); 401 + locked = uart_port_trylock_irqsave(port, &flags); 402 402 else 403 - spin_lock_irqsave(&port->lock, flags); 403 + uart_port_lock_irqsave(port, &flags); 404 404 405 405 uart_console_write(port, c, n, digicolor_uart_console_putchar); 406 406 407 407 if (locked) 408 - spin_unlock_irqrestore(&port->lock, flags); 408 + uart_port_unlock_irqrestore(port, flags); 409 409 410 410 /* Wait for transmitter to become empty */ 411 411 do {

+16 -16

drivers/tty/serial/dz.c

··· 268 268 } 269 269 /* If nothing to do or stopped or hardware stopped. */ 270 270 if (uart_circ_empty(xmit) || uart_tx_stopped(&dport->port)) { 271 - spin_lock(&dport->port.lock); 271 + uart_port_lock(&dport->port); 272 272 dz_stop_tx(&dport->port); 273 - spin_unlock(&dport->port.lock); 273 + uart_port_unlock(&dport->port); 274 274 return; 275 275 } 276 276 ··· 287 287 288 288 /* Are we are done. */ 289 289 if (uart_circ_empty(xmit)) { 290 - spin_lock(&dport->port.lock); 290 + uart_port_lock(&dport->port); 291 291 dz_stop_tx(&dport->port); 292 - spin_unlock(&dport->port.lock); 292 + uart_port_unlock(&dport->port); 293 293 } 294 294 } 295 295 ··· 415 415 return ret; 416 416 } 417 417 418 - spin_lock_irqsave(&dport->port.lock, flags); 418 + uart_port_lock_irqsave(&dport->port, &flags); 419 419 420 420 /* Enable interrupts. */ 421 421 tmp = dz_in(dport, DZ_CSR); 422 422 tmp |= DZ_RIE | DZ_TIE; 423 423 dz_out(dport, DZ_CSR, tmp); 424 424 425 - spin_unlock_irqrestore(&dport->port.lock, flags); 425 + uart_port_unlock_irqrestore(&dport->port, flags); 426 426 427 427 return 0; 428 428 } ··· 443 443 int irq_guard; 444 444 u16 tmp; 445 445 446 - spin_lock_irqsave(&dport->port.lock, flags); 446 + uart_port_lock_irqsave(&dport->port, &flags); 447 447 dz_stop_tx(&dport->port); 448 - spin_unlock_irqrestore(&dport->port.lock, flags); 448 + uart_port_unlock_irqrestore(&dport->port, flags); 449 449 450 450 irq_guard = atomic_add_return(-1, &mux->irq_guard); 451 451 if (!irq_guard) { ··· 491 491 unsigned long flags; 492 492 unsigned short tmp, mask = 1 << dport->port.line; 493 493 494 - spin_lock_irqsave(&uport->lock, flags); 494 + uart_port_lock_irqsave(uport, &flags); 495 495 tmp = dz_in(dport, DZ_TCR); 496 496 if (break_state) 497 497 tmp |= mask; 498 498 else 499 499 tmp &= ~mask; 500 500 dz_out(dport, DZ_TCR, tmp); 501 - spin_unlock_irqrestore(&uport->lock, flags); 501 + uart_port_unlock_irqrestore(uport, flags); 502 502 } 503 503 504 504 static int dz_encode_baud_rate(unsigned int baud) ··· 608 608 if (termios->c_cflag & CREAD) 609 609 cflag |= DZ_RXENAB; 610 610 611 - spin_lock_irqsave(&dport->port.lock, flags); 611 + uart_port_lock_irqsave(&dport->port, &flags); 612 612 613 613 uart_update_timeout(uport, termios->c_cflag, baud); 614 614 ··· 631 631 if (termios->c_iflag & IGNBRK) 632 632 dport->port.ignore_status_mask |= DZ_BREAK; 633 633 634 - spin_unlock_irqrestore(&dport->port.lock, flags); 634 + uart_port_unlock_irqrestore(&dport->port, flags); 635 635 } 636 636 637 637 /* ··· 645 645 struct dz_port *dport = to_dport(uport); 646 646 unsigned long flags; 647 647 648 - spin_lock_irqsave(&dport->port.lock, flags); 648 + uart_port_lock_irqsave(&dport->port, &flags); 649 649 if (state < 3) 650 650 dz_start_tx(&dport->port); 651 651 else 652 652 dz_stop_tx(&dport->port); 653 - spin_unlock_irqrestore(&dport->port.lock, flags); 653 + uart_port_unlock_irqrestore(&dport->port, flags); 654 654 } 655 655 656 656 ··· 811 811 unsigned short csr, tcr, trdy, mask; 812 812 int loops = 10000; 813 813 814 - spin_lock_irqsave(&dport->port.lock, flags); 814 + uart_port_lock_irqsave(&dport->port, &flags); 815 815 csr = dz_in(dport, DZ_CSR); 816 816 dz_out(dport, DZ_CSR, csr & ~DZ_TIE); 817 817 tcr = dz_in(dport, DZ_TCR); ··· 819 819 mask = tcr; 820 820 dz_out(dport, DZ_TCR, mask); 821 821 iob(); 822 - spin_unlock_irqrestore(&dport->port.lock, flags); 822 + uart_port_unlock_irqrestore(&dport->port, flags); 823 823 824 824 do { 825 825 trdy = dz_in(dport, DZ_CSR);

+459

drivers/tty/serial/esp32_acm.c

··· 1 + // SPDX-License-Identifier: GPL-2.0-or-later 2 + 3 + #include <linux/bitfield.h> 4 + #include <linux/bits.h> 5 + #include <linux/console.h> 6 + #include <linux/delay.h> 7 + #include <linux/io.h> 8 + #include <linux/irq.h> 9 + #include <linux/module.h> 10 + #include <linux/of.h> 11 + #include <linux/of_device.h> 12 + #include <linux/serial_core.h> 13 + #include <linux/slab.h> 14 + #include <linux/tty_flip.h> 15 + #include <asm/serial.h> 16 + 17 + #define DRIVER_NAME "esp32s3-acm" 18 + #define DEV_NAME "ttyGS" 19 + #define UART_NR 4 20 + 21 + #define ESP32S3_ACM_TX_FIFO_SIZE 64 22 + 23 + #define USB_SERIAL_JTAG_EP1_REG 0x00 24 + #define USB_SERIAL_JTAG_EP1_CONF_REG 0x04 25 + #define USB_SERIAL_JTAG_WR_DONE BIT(0) 26 + #define USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE BIT(1) 27 + #define USB_SERIAL_JTAG_INT_ST_REG 0x0c 28 + #define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST BIT(2) 29 + #define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST BIT(3) 30 + #define USB_SERIAL_JTAG_INT_ENA_REG 0x10 31 + #define USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA BIT(2) 32 + #define USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA BIT(3) 33 + #define USB_SERIAL_JTAG_INT_CLR_REG 0x14 34 + #define USB_SERIAL_JTAG_IN_EP1_ST_REG 0x2c 35 + #define USB_SERIAL_JTAG_IN_EP1_WR_ADDR GENMASK(8, 2) 36 + #define USB_SERIAL_JTAG_OUT_EP1_ST_REG 0x3c 37 + #define USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT GENMASK(22, 16) 38 + 39 + static const struct of_device_id esp32s3_acm_dt_ids[] = { 40 + { 41 + .compatible = "esp,esp32s3-acm", 42 + }, { /* sentinel */ } 43 + }; 44 + MODULE_DEVICE_TABLE(of, esp32s3_acm_dt_ids); 45 + 46 + static struct uart_port *esp32s3_acm_ports[UART_NR]; 47 + 48 + static void esp32s3_acm_write(struct uart_port *port, unsigned long reg, u32 v) 49 + { 50 + writel(v, port->membase + reg); 51 + } 52 + 53 + static u32 esp32s3_acm_read(struct uart_port *port, unsigned long reg) 54 + { 55 + return readl(port->membase + reg); 56 + } 57 + 58 + static u32 esp32s3_acm_tx_fifo_free(struct uart_port *port) 59 + { 60 + u32 status = esp32s3_acm_read(port, USB_SERIAL_JTAG_EP1_CONF_REG); 61 + 62 + return status & USB_SERIAL_JTAG_SERIAL_IN_EP_DATA_FREE; 63 + } 64 + 65 + static u32 esp32s3_acm_tx_fifo_cnt(struct uart_port *port) 66 + { 67 + u32 status = esp32s3_acm_read(port, USB_SERIAL_JTAG_IN_EP1_ST_REG); 68 + 69 + return FIELD_GET(USB_SERIAL_JTAG_IN_EP1_WR_ADDR, status); 70 + } 71 + 72 + static u32 esp32s3_acm_rx_fifo_cnt(struct uart_port *port) 73 + { 74 + u32 status = esp32s3_acm_read(port, USB_SERIAL_JTAG_OUT_EP1_ST_REG); 75 + 76 + return FIELD_GET(USB_SERIAL_JTAG_OUT_EP1_REC_DATA_CNT, status); 77 + } 78 + 79 + /* return TIOCSER_TEMT when transmitter is not busy */ 80 + static unsigned int esp32s3_acm_tx_empty(struct uart_port *port) 81 + { 82 + return esp32s3_acm_tx_fifo_cnt(port) == 0 ? TIOCSER_TEMT : 0; 83 + } 84 + 85 + static void esp32s3_acm_set_mctrl(struct uart_port *port, unsigned int mctrl) 86 + { 87 + } 88 + 89 + static unsigned int esp32s3_acm_get_mctrl(struct uart_port *port) 90 + { 91 + return TIOCM_CAR; 92 + } 93 + 94 + static void esp32s3_acm_stop_tx(struct uart_port *port) 95 + { 96 + u32 int_ena; 97 + 98 + int_ena = esp32s3_acm_read(port, USB_SERIAL_JTAG_INT_ENA_REG); 99 + int_ena &= ~USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA; 100 + esp32s3_acm_write(port, USB_SERIAL_JTAG_INT_ENA_REG, int_ena); 101 + } 102 + 103 + static void esp32s3_acm_rxint(struct uart_port *port) 104 + { 105 + struct tty_port *tty_port = &port->state->port; 106 + u32 rx_fifo_cnt = esp32s3_acm_rx_fifo_cnt(port); 107 + unsigned long flags; 108 + u32 i; 109 + 110 + if (!rx_fifo_cnt) 111 + return; 112 + 113 + spin_lock_irqsave(&port->lock, flags); 114 + 115 + for (i = 0; i < rx_fifo_cnt; ++i) { 116 + u32 rx = esp32s3_acm_read(port, USB_SERIAL_JTAG_EP1_REG); 117 + 118 + ++port->icount.rx; 119 + tty_insert_flip_char(tty_port, rx, TTY_NORMAL); 120 + } 121 + spin_unlock_irqrestore(&port->lock, flags); 122 + 123 + tty_flip_buffer_push(tty_port); 124 + } 125 + 126 + static void esp32s3_acm_push(struct uart_port *port) 127 + { 128 + if (esp32s3_acm_tx_fifo_free(port)) 129 + esp32s3_acm_write(port, USB_SERIAL_JTAG_EP1_CONF_REG, 130 + USB_SERIAL_JTAG_WR_DONE); 131 + } 132 + 133 + static void esp32s3_acm_put_char(struct uart_port *port, u8 c) 134 + { 135 + esp32s3_acm_write(port, USB_SERIAL_JTAG_EP1_REG, c); 136 + } 137 + 138 + static void esp32s3_acm_put_char_sync(struct uart_port *port, u8 c) 139 + { 140 + unsigned long timeout = jiffies + HZ; 141 + 142 + while (!esp32s3_acm_tx_fifo_free(port)) { 143 + if (time_after(jiffies, timeout)) { 144 + dev_warn(port->dev, "timeout waiting for TX FIFO\n"); 145 + return; 146 + } 147 + cpu_relax(); 148 + } 149 + esp32s3_acm_put_char(port, c); 150 + esp32s3_acm_push(port); 151 + } 152 + 153 + static void esp32s3_acm_transmit_buffer(struct uart_port *port) 154 + { 155 + u32 tx_fifo_used; 156 + unsigned int pending; 157 + u8 ch; 158 + 159 + if (!esp32s3_acm_tx_fifo_free(port)) 160 + return; 161 + 162 + tx_fifo_used = esp32s3_acm_tx_fifo_cnt(port); 163 + pending = uart_port_tx_limited(port, ch, 164 + ESP32S3_ACM_TX_FIFO_SIZE - tx_fifo_used, 165 + true, esp32s3_acm_put_char(port, ch), 166 + ({})); 167 + if (pending) { 168 + u32 int_ena; 169 + 170 + int_ena = esp32s3_acm_read(port, USB_SERIAL_JTAG_INT_ENA_REG); 171 + int_ena |= USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ENA; 172 + esp32s3_acm_write(port, USB_SERIAL_JTAG_INT_ENA_REG, int_ena); 173 + } 174 + esp32s3_acm_push(port); 175 + } 176 + 177 + static void esp32s3_acm_txint(struct uart_port *port) 178 + { 179 + esp32s3_acm_transmit_buffer(port); 180 + } 181 + 182 + static irqreturn_t esp32s3_acm_int(int irq, void *dev_id) 183 + { 184 + struct uart_port *port = dev_id; 185 + u32 status; 186 + 187 + status = esp32s3_acm_read(port, USB_SERIAL_JTAG_INT_ST_REG); 188 + esp32s3_acm_write(port, USB_SERIAL_JTAG_INT_CLR_REG, status); 189 + 190 + if (status & USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ST) 191 + esp32s3_acm_rxint(port); 192 + if (status & USB_SERIAL_JTAG_SERIAL_IN_EMPTY_INT_ST) 193 + esp32s3_acm_txint(port); 194 + 195 + return IRQ_RETVAL(status); 196 + } 197 + 198 + static void esp32s3_acm_start_tx(struct uart_port *port) 199 + { 200 + esp32s3_acm_transmit_buffer(port); 201 + } 202 + 203 + static void esp32s3_acm_stop_rx(struct uart_port *port) 204 + { 205 + u32 int_ena; 206 + 207 + int_ena = esp32s3_acm_read(port, USB_SERIAL_JTAG_INT_ENA_REG); 208 + int_ena &= ~USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA; 209 + esp32s3_acm_write(port, USB_SERIAL_JTAG_INT_ENA_REG, int_ena); 210 + } 211 + 212 + static int esp32s3_acm_startup(struct uart_port *port) 213 + { 214 + int ret; 215 + 216 + ret = request_irq(port->irq, esp32s3_acm_int, 0, DRIVER_NAME, port); 217 + if (ret) 218 + return ret; 219 + esp32s3_acm_write(port, USB_SERIAL_JTAG_INT_ENA_REG, 220 + USB_SERIAL_JTAG_SERIAL_OUT_RECV_PKT_INT_ENA); 221 + 222 + return 0; 223 + } 224 + 225 + static void esp32s3_acm_shutdown(struct uart_port *port) 226 + { 227 + esp32s3_acm_write(port, USB_SERIAL_JTAG_INT_ENA_REG, 0); 228 + free_irq(port->irq, port); 229 + } 230 + 231 + static void esp32s3_acm_set_termios(struct uart_port *port, 232 + struct ktermios *termios, 233 + const struct ktermios *old) 234 + { 235 + } 236 + 237 + static const char *esp32s3_acm_type(struct uart_port *port) 238 + { 239 + return "ESP32S3 ACM"; 240 + } 241 + 242 + /* configure/auto-configure the port */ 243 + static void esp32s3_acm_config_port(struct uart_port *port, int flags) 244 + { 245 + if (flags & UART_CONFIG_TYPE) 246 + port->type = PORT_GENERIC; 247 + } 248 + 249 + #ifdef CONFIG_CONSOLE_POLL 250 + static void esp32s3_acm_poll_put_char(struct uart_port *port, unsigned char c) 251 + { 252 + esp32s3_acm_put_char_sync(port, c); 253 + } 254 + 255 + static int esp32s3_acm_poll_get_char(struct uart_port *port) 256 + { 257 + if (esp32s3_acm_rx_fifo_cnt(port)) 258 + return esp32s3_acm_read(port, USB_SERIAL_JTAG_EP1_REG); 259 + else 260 + return NO_POLL_CHAR; 261 + } 262 + #endif 263 + 264 + static const struct uart_ops esp32s3_acm_pops = { 265 + .tx_empty = esp32s3_acm_tx_empty, 266 + .set_mctrl = esp32s3_acm_set_mctrl, 267 + .get_mctrl = esp32s3_acm_get_mctrl, 268 + .stop_tx = esp32s3_acm_stop_tx, 269 + .start_tx = esp32s3_acm_start_tx, 270 + .stop_rx = esp32s3_acm_stop_rx, 271 + .startup = esp32s3_acm_startup, 272 + .shutdown = esp32s3_acm_shutdown, 273 + .set_termios = esp32s3_acm_set_termios, 274 + .type = esp32s3_acm_type, 275 + .config_port = esp32s3_acm_config_port, 276 + #ifdef CONFIG_CONSOLE_POLL 277 + .poll_put_char = esp32s3_acm_poll_put_char, 278 + .poll_get_char = esp32s3_acm_poll_get_char, 279 + #endif 280 + }; 281 + 282 + static void esp32s3_acm_string_write(struct uart_port *port, const char *s, 283 + unsigned int count) 284 + { 285 + uart_console_write(port, s, count, esp32s3_acm_put_char_sync); 286 + } 287 + 288 + static void 289 + esp32s3_acm_console_write(struct console *co, const char *s, unsigned int count) 290 + { 291 + struct uart_port *port = esp32s3_acm_ports[co->index]; 292 + unsigned long flags; 293 + bool locked = true; 294 + 295 + if (port->sysrq) 296 + locked = false; 297 + else if (oops_in_progress) 298 + locked = spin_trylock_irqsave(&port->lock, flags); 299 + else 300 + spin_lock_irqsave(&port->lock, flags); 301 + 302 + esp32s3_acm_string_write(port, s, count); 303 + 304 + if (locked) 305 + spin_unlock_irqrestore(&port->lock, flags); 306 + } 307 + 308 + static struct uart_driver esp32s3_acm_reg; 309 + static struct console esp32s3_acm_console = { 310 + .name = DEV_NAME, 311 + .write = esp32s3_acm_console_write, 312 + .device = uart_console_device, 313 + .flags = CON_PRINTBUFFER, 314 + .index = -1, 315 + .data = &esp32s3_acm_reg, 316 + }; 317 + 318 + static void esp32s3_acm_earlycon_write(struct console *con, const char *s, 319 + unsigned int n) 320 + { 321 + struct earlycon_device *dev = con->data; 322 + 323 + uart_console_write(&dev->port, s, n, esp32s3_acm_put_char_sync); 324 + } 325 + 326 + #ifdef CONFIG_CONSOLE_POLL 327 + static int esp32s3_acm_earlycon_read(struct console *con, char *s, unsigned int n) 328 + { 329 + struct earlycon_device *dev = con->data; 330 + unsigned int num_read = 0; 331 + 332 + while (num_read < n) { 333 + int c = esp32s3_acm_poll_get_char(&dev->port); 334 + 335 + if (c == NO_POLL_CHAR) 336 + break; 337 + s[num_read++] = c; 338 + } 339 + return num_read; 340 + } 341 + #endif 342 + 343 + static int __init esp32s3_acm_early_console_setup(struct earlycon_device *device, 344 + const char *options) 345 + { 346 + if (!device->port.membase) 347 + return -ENODEV; 348 + 349 + device->con->write = esp32s3_acm_earlycon_write; 350 + #ifdef CONFIG_CONSOLE_POLL 351 + device->con->read = esp32s3_acm_earlycon_read; 352 + #endif 353 + return 0; 354 + } 355 + 356 + OF_EARLYCON_DECLARE(esp32s3acm, "esp,esp32s3-acm", 357 + esp32s3_acm_early_console_setup); 358 + 359 + static struct uart_driver esp32s3_acm_reg = { 360 + .owner = THIS_MODULE, 361 + .driver_name = DRIVER_NAME, 362 + .dev_name = DEV_NAME, 363 + .nr = ARRAY_SIZE(esp32s3_acm_ports), 364 + .cons = &esp32s3_acm_console, 365 + }; 366 + 367 + static int esp32s3_acm_probe(struct platform_device *pdev) 368 + { 369 + struct device_node *np = pdev->dev.of_node; 370 + struct uart_port *port; 371 + struct resource *res; 372 + int ret; 373 + 374 + port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL); 375 + if (!port) 376 + return -ENOMEM; 377 + 378 + ret = of_alias_get_id(np, "serial"); 379 + if (ret < 0) { 380 + dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 381 + return ret; 382 + } 383 + if (ret >= UART_NR) { 384 + dev_err(&pdev->dev, "driver limited to %d serial ports\n", 385 + UART_NR); 386 + return -ENOMEM; 387 + } 388 + 389 + port->line = ret; 390 + 391 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 392 + if (!res) 393 + return -ENODEV; 394 + 395 + port->mapbase = res->start; 396 + port->membase = devm_ioremap_resource(&pdev->dev, res); 397 + if (IS_ERR(port->membase)) 398 + return PTR_ERR(port->membase); 399 + 400 + port->dev = &pdev->dev; 401 + port->type = PORT_GENERIC; 402 + port->iotype = UPIO_MEM; 403 + port->irq = platform_get_irq(pdev, 0); 404 + port->ops = &esp32s3_acm_pops; 405 + port->flags = UPF_BOOT_AUTOCONF; 406 + port->has_sysrq = 1; 407 + port->fifosize = ESP32S3_ACM_TX_FIFO_SIZE; 408 + 409 + esp32s3_acm_ports[port->line] = port; 410 + 411 + platform_set_drvdata(pdev, port); 412 + 413 + return uart_add_one_port(&esp32s3_acm_reg, port); 414 + } 415 + 416 + static int esp32s3_acm_remove(struct platform_device *pdev) 417 + { 418 + struct uart_port *port = platform_get_drvdata(pdev); 419 + 420 + uart_remove_one_port(&esp32s3_acm_reg, port); 421 + return 0; 422 + } 423 + 424 + 425 + static struct platform_driver esp32s3_acm_driver = { 426 + .probe = esp32s3_acm_probe, 427 + .remove = esp32s3_acm_remove, 428 + .driver = { 429 + .name = DRIVER_NAME, 430 + .of_match_table = esp32s3_acm_dt_ids, 431 + }, 432 + }; 433 + 434 + static int __init esp32s3_acm_init(void) 435 + { 436 + int ret; 437 + 438 + ret = uart_register_driver(&esp32s3_acm_reg); 439 + if (ret) 440 + return ret; 441 + 442 + ret = platform_driver_register(&esp32s3_acm_driver); 443 + if (ret) 444 + uart_unregister_driver(&esp32s3_acm_reg); 445 + 446 + return ret; 447 + } 448 + 449 + static void __exit esp32s3_acm_exit(void) 450 + { 451 + platform_driver_unregister(&esp32s3_acm_driver); 452 + uart_unregister_driver(&esp32s3_acm_reg); 453 + } 454 + 455 + module_init(esp32s3_acm_init); 456 + module_exit(esp32s3_acm_exit); 457 + 458 + MODULE_AUTHOR("Max Filippov <jcmvbkbc@gmail.com>"); 459 + MODULE_LICENSE("GPL");

+784

drivers/tty/serial/esp32_uart.c

··· 1 + // SPDX-License-Identifier: GPL-2.0-or-later 2 + 3 + #include <linux/bitfield.h> 4 + #include <linux/bits.h> 5 + #include <linux/clk.h> 6 + #include <linux/console.h> 7 + #include <linux/delay.h> 8 + #include <linux/io.h> 9 + #include <linux/irq.h> 10 + #include <linux/module.h> 11 + #include <linux/of.h> 12 + #include <linux/of_device.h> 13 + #include <linux/serial_core.h> 14 + #include <linux/slab.h> 15 + #include <linux/tty_flip.h> 16 + #include <asm/serial.h> 17 + 18 + #define DRIVER_NAME "esp32-uart" 19 + #define DEV_NAME "ttyS" 20 + #define UART_NR 3 21 + 22 + #define ESP32_UART_TX_FIFO_SIZE 127 23 + #define ESP32_UART_RX_FIFO_SIZE 127 24 + 25 + #define UART_FIFO_REG 0x00 26 + #define UART_INT_RAW_REG 0x04 27 + #define UART_INT_ST_REG 0x08 28 + #define UART_INT_ENA_REG 0x0c 29 + #define UART_INT_CLR_REG 0x10 30 + #define UART_RXFIFO_FULL_INT BIT(0) 31 + #define UART_TXFIFO_EMPTY_INT BIT(1) 32 + #define UART_BRK_DET_INT BIT(7) 33 + #define UART_CLKDIV_REG 0x14 34 + #define ESP32_UART_CLKDIV GENMASK(19, 0) 35 + #define ESP32S3_UART_CLKDIV GENMASK(11, 0) 36 + #define UART_CLKDIV_SHIFT 0 37 + #define UART_CLKDIV_FRAG GENMASK(23, 20) 38 + #define UART_STATUS_REG 0x1c 39 + #define ESP32_UART_RXFIFO_CNT GENMASK(7, 0) 40 + #define ESP32S3_UART_RXFIFO_CNT GENMASK(9, 0) 41 + #define UART_RXFIFO_CNT_SHIFT 0 42 + #define UART_DSRN BIT(13) 43 + #define UART_CTSN BIT(14) 44 + #define ESP32_UART_TXFIFO_CNT GENMASK(23, 16) 45 + #define ESP32S3_UART_TXFIFO_CNT GENMASK(25, 16) 46 + #define UART_TXFIFO_CNT_SHIFT 16 47 + #define UART_CONF0_REG 0x20 48 + #define UART_PARITY BIT(0) 49 + #define UART_PARITY_EN BIT(1) 50 + #define UART_BIT_NUM GENMASK(3, 2) 51 + #define UART_BIT_NUM_5 0 52 + #define UART_BIT_NUM_6 1 53 + #define UART_BIT_NUM_7 2 54 + #define UART_BIT_NUM_8 3 55 + #define UART_STOP_BIT_NUM GENMASK(5, 4) 56 + #define UART_STOP_BIT_NUM_1 1 57 + #define UART_STOP_BIT_NUM_2 3 58 + #define UART_SW_RTS BIT(6) 59 + #define UART_SW_DTR BIT(7) 60 + #define UART_LOOPBACK BIT(14) 61 + #define UART_TX_FLOW_EN BIT(15) 62 + #define UART_RTS_INV BIT(23) 63 + #define UART_DTR_INV BIT(24) 64 + #define UART_CONF1_REG 0x24 65 + #define UART_RXFIFO_FULL_THRHD_SHIFT 0 66 + #define ESP32_UART_TXFIFO_EMPTY_THRHD_SHIFT 8 67 + #define ESP32S3_UART_TXFIFO_EMPTY_THRHD_SHIFT 10 68 + #define ESP32_UART_RX_FLOW_EN BIT(23) 69 + #define ESP32S3_UART_RX_FLOW_EN BIT(22) 70 + #define ESP32S3_UART_CLK_CONF_REG 0x78 71 + #define ESP32S3_UART_SCLK_DIV_B GENMASK(5, 0) 72 + #define ESP32S3_UART_SCLK_DIV_A GENMASK(11, 6) 73 + #define ESP32S3_UART_SCLK_DIV_NUM GENMASK(19, 12) 74 + #define ESP32S3_UART_SCLK_SEL GENMASK(21, 20) 75 + #define APB_CLK 1 76 + #define RC_FAST_CLK 2 77 + #define XTAL_CLK 3 78 + #define ESP32S3_UART_SCLK_EN BIT(22) 79 + #define ESP32S3_UART_RST_CORE BIT(23) 80 + #define ESP32S3_UART_TX_SCLK_EN BIT(24) 81 + #define ESP32S3_UART_RX_SCLK_EN BIT(25) 82 + #define ESP32S3_UART_TX_RST_CORE BIT(26) 83 + #define ESP32S3_UART_RX_RST_CORE BIT(27) 84 + 85 + #define ESP32S3_UART_CLK_CONF_DEFAULT \ 86 + (ESP32S3_UART_RX_SCLK_EN | \ 87 + ESP32S3_UART_TX_SCLK_EN | \ 88 + ESP32S3_UART_SCLK_EN | \ 89 + FIELD_PREP(ESP32S3_UART_SCLK_SEL, XTAL_CLK)) 90 + 91 + struct esp32_port { 92 + struct uart_port port; 93 + struct clk *clk; 94 + }; 95 + 96 + struct esp32_uart_variant { 97 + u32 clkdiv_mask; 98 + u32 rxfifo_cnt_mask; 99 + u32 txfifo_cnt_mask; 100 + u32 txfifo_empty_thrhd_shift; 101 + u32 rx_flow_en; 102 + const char *type; 103 + bool has_clkconf; 104 + }; 105 + 106 + static const struct esp32_uart_variant esp32_variant = { 107 + .clkdiv_mask = ESP32_UART_CLKDIV, 108 + .rxfifo_cnt_mask = ESP32_UART_RXFIFO_CNT, 109 + .txfifo_cnt_mask = ESP32_UART_TXFIFO_CNT, 110 + .txfifo_empty_thrhd_shift = ESP32_UART_TXFIFO_EMPTY_THRHD_SHIFT, 111 + .rx_flow_en = ESP32_UART_RX_FLOW_EN, 112 + .type = "ESP32 UART", 113 + }; 114 + 115 + static const struct esp32_uart_variant esp32s3_variant = { 116 + .clkdiv_mask = ESP32S3_UART_CLKDIV, 117 + .rxfifo_cnt_mask = ESP32S3_UART_RXFIFO_CNT, 118 + .txfifo_cnt_mask = ESP32S3_UART_TXFIFO_CNT, 119 + .txfifo_empty_thrhd_shift = ESP32S3_UART_TXFIFO_EMPTY_THRHD_SHIFT, 120 + .rx_flow_en = ESP32S3_UART_RX_FLOW_EN, 121 + .type = "ESP32S3 UART", 122 + .has_clkconf = true, 123 + }; 124 + 125 + static const struct of_device_id esp32_uart_dt_ids[] = { 126 + { 127 + .compatible = "esp,esp32-uart", 128 + .data = &esp32_variant, 129 + }, { 130 + .compatible = "esp,esp32s3-uart", 131 + .data = &esp32s3_variant, 132 + }, { /* sentinel */ } 133 + }; 134 + MODULE_DEVICE_TABLE(of, esp32_uart_dt_ids); 135 + 136 + static struct esp32_port *esp32_uart_ports[UART_NR]; 137 + 138 + static const struct esp32_uart_variant *port_variant(struct uart_port *port) 139 + { 140 + return port->private_data; 141 + } 142 + 143 + static void esp32_uart_write(struct uart_port *port, unsigned long reg, u32 v) 144 + { 145 + writel(v, port->membase + reg); 146 + } 147 + 148 + static u32 esp32_uart_read(struct uart_port *port, unsigned long reg) 149 + { 150 + return readl(port->membase + reg); 151 + } 152 + 153 + static u32 esp32_uart_tx_fifo_cnt(struct uart_port *port) 154 + { 155 + u32 status = esp32_uart_read(port, UART_STATUS_REG); 156 + 157 + return (status & port_variant(port)->txfifo_cnt_mask) >> UART_TXFIFO_CNT_SHIFT; 158 + } 159 + 160 + static u32 esp32_uart_rx_fifo_cnt(struct uart_port *port) 161 + { 162 + u32 status = esp32_uart_read(port, UART_STATUS_REG); 163 + 164 + return (status & port_variant(port)->rxfifo_cnt_mask) >> UART_RXFIFO_CNT_SHIFT; 165 + } 166 + 167 + /* return TIOCSER_TEMT when transmitter is not busy */ 168 + static unsigned int esp32_uart_tx_empty(struct uart_port *port) 169 + { 170 + return esp32_uart_tx_fifo_cnt(port) ? 0 : TIOCSER_TEMT; 171 + } 172 + 173 + static void esp32_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 174 + { 175 + u32 conf0 = esp32_uart_read(port, UART_CONF0_REG); 176 + 177 + conf0 &= ~(UART_LOOPBACK | 178 + UART_SW_RTS | UART_RTS_INV | 179 + UART_SW_DTR | UART_DTR_INV); 180 + 181 + if (mctrl & TIOCM_RTS) 182 + conf0 |= UART_SW_RTS; 183 + if (mctrl & TIOCM_DTR) 184 + conf0 |= UART_SW_DTR; 185 + if (mctrl & TIOCM_LOOP) 186 + conf0 |= UART_LOOPBACK; 187 + 188 + esp32_uart_write(port, UART_CONF0_REG, conf0); 189 + } 190 + 191 + static unsigned int esp32_uart_get_mctrl(struct uart_port *port) 192 + { 193 + u32 status = esp32_uart_read(port, UART_STATUS_REG); 194 + unsigned int ret = TIOCM_CAR; 195 + 196 + if (status & UART_DSRN) 197 + ret |= TIOCM_DSR; 198 + if (status & UART_CTSN) 199 + ret |= TIOCM_CTS; 200 + 201 + return ret; 202 + } 203 + 204 + static void esp32_uart_stop_tx(struct uart_port *port) 205 + { 206 + u32 int_ena; 207 + 208 + int_ena = esp32_uart_read(port, UART_INT_ENA_REG); 209 + int_ena &= ~UART_TXFIFO_EMPTY_INT; 210 + esp32_uart_write(port, UART_INT_ENA_REG, int_ena); 211 + } 212 + 213 + static void esp32_uart_rxint(struct uart_port *port) 214 + { 215 + struct tty_port *tty_port = &port->state->port; 216 + u32 rx_fifo_cnt = esp32_uart_rx_fifo_cnt(port); 217 + unsigned long flags; 218 + u32 i; 219 + 220 + if (!rx_fifo_cnt) 221 + return; 222 + 223 + spin_lock_irqsave(&port->lock, flags); 224 + 225 + for (i = 0; i < rx_fifo_cnt; ++i) { 226 + u32 rx = esp32_uart_read(port, UART_FIFO_REG); 227 + 228 + if (!rx && 229 + (esp32_uart_read(port, UART_INT_ST_REG) & UART_BRK_DET_INT)) { 230 + esp32_uart_write(port, UART_INT_CLR_REG, UART_BRK_DET_INT); 231 + ++port->icount.brk; 232 + uart_handle_break(port); 233 + } else { 234 + if (uart_handle_sysrq_char(port, (unsigned char)rx)) 235 + continue; 236 + tty_insert_flip_char(tty_port, rx, TTY_NORMAL); 237 + ++port->icount.rx; 238 + } 239 + } 240 + spin_unlock_irqrestore(&port->lock, flags); 241 + 242 + tty_flip_buffer_push(tty_port); 243 + } 244 + 245 + static void esp32_uart_put_char(struct uart_port *port, u8 c) 246 + { 247 + esp32_uart_write(port, UART_FIFO_REG, c); 248 + } 249 + 250 + static void esp32_uart_put_char_sync(struct uart_port *port, u8 c) 251 + { 252 + unsigned long timeout = jiffies + HZ; 253 + 254 + while (esp32_uart_tx_fifo_cnt(port) >= ESP32_UART_TX_FIFO_SIZE) { 255 + if (time_after(jiffies, timeout)) { 256 + dev_warn(port->dev, "timeout waiting for TX FIFO\n"); 257 + return; 258 + } 259 + cpu_relax(); 260 + } 261 + esp32_uart_put_char(port, c); 262 + } 263 + 264 + static void esp32_uart_transmit_buffer(struct uart_port *port) 265 + { 266 + u32 tx_fifo_used = esp32_uart_tx_fifo_cnt(port); 267 + unsigned int pending; 268 + u8 ch; 269 + 270 + if (tx_fifo_used >= ESP32_UART_TX_FIFO_SIZE) 271 + return; 272 + 273 + pending = uart_port_tx_limited(port, ch, 274 + ESP32_UART_TX_FIFO_SIZE - tx_fifo_used, 275 + true, esp32_uart_put_char(port, ch), 276 + ({})); 277 + if (pending) { 278 + u32 int_ena; 279 + 280 + int_ena = esp32_uart_read(port, UART_INT_ENA_REG); 281 + int_ena |= UART_TXFIFO_EMPTY_INT; 282 + esp32_uart_write(port, UART_INT_ENA_REG, int_ena); 283 + } 284 + } 285 + 286 + static void esp32_uart_txint(struct uart_port *port) 287 + { 288 + esp32_uart_transmit_buffer(port); 289 + } 290 + 291 + static irqreturn_t esp32_uart_int(int irq, void *dev_id) 292 + { 293 + struct uart_port *port = dev_id; 294 + u32 status; 295 + 296 + status = esp32_uart_read(port, UART_INT_ST_REG); 297 + 298 + if (status & (UART_RXFIFO_FULL_INT | UART_BRK_DET_INT)) 299 + esp32_uart_rxint(port); 300 + if (status & UART_TXFIFO_EMPTY_INT) 301 + esp32_uart_txint(port); 302 + 303 + esp32_uart_write(port, UART_INT_CLR_REG, status); 304 + 305 + return IRQ_RETVAL(status); 306 + } 307 + 308 + static void esp32_uart_start_tx(struct uart_port *port) 309 + { 310 + esp32_uart_transmit_buffer(port); 311 + } 312 + 313 + static void esp32_uart_stop_rx(struct uart_port *port) 314 + { 315 + u32 int_ena; 316 + 317 + int_ena = esp32_uart_read(port, UART_INT_ENA_REG); 318 + int_ena &= ~UART_RXFIFO_FULL_INT; 319 + esp32_uart_write(port, UART_INT_ENA_REG, int_ena); 320 + } 321 + 322 + static int esp32_uart_startup(struct uart_port *port) 323 + { 324 + int ret = 0; 325 + unsigned long flags; 326 + struct esp32_port *sport = container_of(port, struct esp32_port, port); 327 + 328 + ret = clk_prepare_enable(sport->clk); 329 + if (ret) 330 + return ret; 331 + 332 + ret = request_irq(port->irq, esp32_uart_int, 0, DRIVER_NAME, port); 333 + if (ret) { 334 + clk_disable_unprepare(sport->clk); 335 + return ret; 336 + } 337 + 338 + spin_lock_irqsave(&port->lock, flags); 339 + if (port_variant(port)->has_clkconf) 340 + esp32_uart_write(port, ESP32S3_UART_CLK_CONF_REG, 341 + ESP32S3_UART_CLK_CONF_DEFAULT); 342 + esp32_uart_write(port, UART_CONF1_REG, 343 + (1 << UART_RXFIFO_FULL_THRHD_SHIFT) | 344 + (1 << port_variant(port)->txfifo_empty_thrhd_shift)); 345 + esp32_uart_write(port, UART_INT_CLR_REG, UART_RXFIFO_FULL_INT | UART_BRK_DET_INT); 346 + esp32_uart_write(port, UART_INT_ENA_REG, UART_RXFIFO_FULL_INT | UART_BRK_DET_INT); 347 + spin_unlock_irqrestore(&port->lock, flags); 348 + 349 + return ret; 350 + } 351 + 352 + static void esp32_uart_shutdown(struct uart_port *port) 353 + { 354 + struct esp32_port *sport = container_of(port, struct esp32_port, port); 355 + 356 + esp32_uart_write(port, UART_INT_ENA_REG, 0); 357 + free_irq(port->irq, port); 358 + clk_disable_unprepare(sport->clk); 359 + } 360 + 361 + static bool esp32_uart_set_baud(struct uart_port *port, u32 baud) 362 + { 363 + u32 sclk = port->uartclk; 364 + u32 div = sclk / baud; 365 + 366 + if (port_variant(port)->has_clkconf) { 367 + u32 sclk_div = div / port_variant(port)->clkdiv_mask; 368 + 369 + if (div > port_variant(port)->clkdiv_mask) { 370 + sclk /= (sclk_div + 1); 371 + div = sclk / baud; 372 + } 373 + esp32_uart_write(port, ESP32S3_UART_CLK_CONF_REG, 374 + FIELD_PREP(ESP32S3_UART_SCLK_DIV_NUM, sclk_div) | 375 + ESP32S3_UART_CLK_CONF_DEFAULT); 376 + } 377 + 378 + if (div <= port_variant(port)->clkdiv_mask) { 379 + u32 frag = (sclk * 16) / baud - div * 16; 380 + 381 + esp32_uart_write(port, UART_CLKDIV_REG, 382 + div | FIELD_PREP(UART_CLKDIV_FRAG, frag)); 383 + return true; 384 + } 385 + 386 + return false; 387 + } 388 + 389 + static void esp32_uart_set_termios(struct uart_port *port, 390 + struct ktermios *termios, 391 + const struct ktermios *old) 392 + { 393 + unsigned long flags; 394 + u32 conf0, conf1; 395 + u32 baud; 396 + const u32 rx_flow_en = port_variant(port)->rx_flow_en; 397 + u32 max_div = port_variant(port)->clkdiv_mask; 398 + 399 + termios->c_cflag &= ~CMSPAR; 400 + 401 + if (port_variant(port)->has_clkconf) 402 + max_div *= FIELD_MAX(ESP32S3_UART_SCLK_DIV_NUM); 403 + 404 + baud = uart_get_baud_rate(port, termios, old, 405 + port->uartclk / max_div, 406 + port->uartclk / 16); 407 + 408 + spin_lock_irqsave(&port->lock, flags); 409 + 410 + conf0 = esp32_uart_read(port, UART_CONF0_REG); 411 + conf0 &= ~(UART_PARITY_EN | UART_PARITY | UART_BIT_NUM | UART_STOP_BIT_NUM); 412 + 413 + conf1 = esp32_uart_read(port, UART_CONF1_REG); 414 + conf1 &= ~rx_flow_en; 415 + 416 + if (termios->c_cflag & PARENB) { 417 + conf0 |= UART_PARITY_EN; 418 + if (termios->c_cflag & PARODD) 419 + conf0 |= UART_PARITY; 420 + } 421 + 422 + switch (termios->c_cflag & CSIZE) { 423 + case CS5: 424 + conf0 |= FIELD_PREP(UART_BIT_NUM, UART_BIT_NUM_5); 425 + break; 426 + case CS6: 427 + conf0 |= FIELD_PREP(UART_BIT_NUM, UART_BIT_NUM_6); 428 + break; 429 + case CS7: 430 + conf0 |= FIELD_PREP(UART_BIT_NUM, UART_BIT_NUM_7); 431 + break; 432 + case CS8: 433 + conf0 |= FIELD_PREP(UART_BIT_NUM, UART_BIT_NUM_8); 434 + break; 435 + } 436 + 437 + if (termios->c_cflag & CSTOPB) 438 + conf0 |= FIELD_PREP(UART_STOP_BIT_NUM, UART_STOP_BIT_NUM_2); 439 + else 440 + conf0 |= FIELD_PREP(UART_STOP_BIT_NUM, UART_STOP_BIT_NUM_1); 441 + 442 + if (termios->c_cflag & CRTSCTS) 443 + conf1 |= rx_flow_en; 444 + 445 + esp32_uart_write(port, UART_CONF0_REG, conf0); 446 + esp32_uart_write(port, UART_CONF1_REG, conf1); 447 + 448 + if (baud) { 449 + esp32_uart_set_baud(port, baud); 450 + uart_update_timeout(port, termios->c_cflag, baud); 451 + } else { 452 + if (esp32_uart_set_baud(port, 115200)) { 453 + baud = 115200; 454 + tty_termios_encode_baud_rate(termios, baud, baud); 455 + uart_update_timeout(port, termios->c_cflag, baud); 456 + } else { 457 + dev_warn(port->dev, 458 + "unable to set speed to %d baud or the default 115200\n", 459 + baud); 460 + } 461 + } 462 + spin_unlock_irqrestore(&port->lock, flags); 463 + } 464 + 465 + static const char *esp32_uart_type(struct uart_port *port) 466 + { 467 + return port_variant(port)->type; 468 + } 469 + 470 + /* configure/auto-configure the port */ 471 + static void esp32_uart_config_port(struct uart_port *port, int flags) 472 + { 473 + if (flags & UART_CONFIG_TYPE) 474 + port->type = PORT_GENERIC; 475 + } 476 + 477 + #ifdef CONFIG_CONSOLE_POLL 478 + static int esp32_uart_poll_init(struct uart_port *port) 479 + { 480 + struct esp32_port *sport = container_of(port, struct esp32_port, port); 481 + 482 + return clk_prepare_enable(sport->clk); 483 + } 484 + 485 + static void esp32_uart_poll_put_char(struct uart_port *port, unsigned char c) 486 + { 487 + esp32_uart_put_char_sync(port, c); 488 + } 489 + 490 + static int esp32_uart_poll_get_char(struct uart_port *port) 491 + { 492 + if (esp32_uart_rx_fifo_cnt(port)) 493 + return esp32_uart_read(port, UART_FIFO_REG); 494 + else 495 + return NO_POLL_CHAR; 496 + 497 + } 498 + #endif 499 + 500 + static const struct uart_ops esp32_uart_pops = { 501 + .tx_empty = esp32_uart_tx_empty, 502 + .set_mctrl = esp32_uart_set_mctrl, 503 + .get_mctrl = esp32_uart_get_mctrl, 504 + .stop_tx = esp32_uart_stop_tx, 505 + .start_tx = esp32_uart_start_tx, 506 + .stop_rx = esp32_uart_stop_rx, 507 + .startup = esp32_uart_startup, 508 + .shutdown = esp32_uart_shutdown, 509 + .set_termios = esp32_uart_set_termios, 510 + .type = esp32_uart_type, 511 + .config_port = esp32_uart_config_port, 512 + #ifdef CONFIG_CONSOLE_POLL 513 + .poll_init = esp32_uart_poll_init, 514 + .poll_put_char = esp32_uart_poll_put_char, 515 + .poll_get_char = esp32_uart_poll_get_char, 516 + #endif 517 + }; 518 + 519 + static void esp32_uart_console_putchar(struct uart_port *port, u8 c) 520 + { 521 + esp32_uart_put_char_sync(port, c); 522 + } 523 + 524 + static void esp32_uart_string_write(struct uart_port *port, const char *s, 525 + unsigned int count) 526 + { 527 + uart_console_write(port, s, count, esp32_uart_console_putchar); 528 + } 529 + 530 + static void 531 + esp32_uart_console_write(struct console *co, const char *s, unsigned int count) 532 + { 533 + struct esp32_port *sport = esp32_uart_ports[co->index]; 534 + struct uart_port *port = &sport->port; 535 + unsigned long flags; 536 + bool locked = true; 537 + 538 + if (port->sysrq) 539 + locked = false; 540 + else if (oops_in_progress) 541 + locked = spin_trylock_irqsave(&port->lock, flags); 542 + else 543 + spin_lock_irqsave(&port->lock, flags); 544 + 545 + esp32_uart_string_write(port, s, count); 546 + 547 + if (locked) 548 + spin_unlock_irqrestore(&port->lock, flags); 549 + } 550 + 551 + static int __init esp32_uart_console_setup(struct console *co, char *options) 552 + { 553 + struct esp32_port *sport; 554 + int baud = 115200; 555 + int bits = 8; 556 + int parity = 'n'; 557 + int flow = 'n'; 558 + int ret; 559 + 560 + /* 561 + * check whether an invalid uart number has been specified, and 562 + * if so, search for the first available port that does have 563 + * console support. 564 + */ 565 + if (co->index == -1 || co->index >= ARRAY_SIZE(esp32_uart_ports)) 566 + co->index = 0; 567 + 568 + sport = esp32_uart_ports[co->index]; 569 + if (!sport) 570 + return -ENODEV; 571 + 572 + ret = clk_prepare_enable(sport->clk); 573 + if (ret) 574 + return ret; 575 + 576 + if (options) 577 + uart_parse_options(options, &baud, &parity, &bits, &flow); 578 + 579 + return uart_set_options(&sport->port, co, baud, parity, bits, flow); 580 + } 581 + 582 + static int esp32_uart_console_exit(struct console *co) 583 + { 584 + struct esp32_port *sport = esp32_uart_ports[co->index]; 585 + 586 + clk_disable_unprepare(sport->clk); 587 + return 0; 588 + } 589 + 590 + static struct uart_driver esp32_uart_reg; 591 + static struct console esp32_uart_console = { 592 + .name = DEV_NAME, 593 + .write = esp32_uart_console_write, 594 + .device = uart_console_device, 595 + .setup = esp32_uart_console_setup, 596 + .exit = esp32_uart_console_exit, 597 + .flags = CON_PRINTBUFFER, 598 + .index = -1, 599 + .data = &esp32_uart_reg, 600 + }; 601 + 602 + static void esp32_uart_earlycon_putchar(struct uart_port *port, u8 c) 603 + { 604 + esp32_uart_put_char_sync(port, c); 605 + } 606 + 607 + static void esp32_uart_earlycon_write(struct console *con, const char *s, 608 + unsigned int n) 609 + { 610 + struct earlycon_device *dev = con->data; 611 + 612 + uart_console_write(&dev->port, s, n, esp32_uart_earlycon_putchar); 613 + } 614 + 615 + #ifdef CONFIG_CONSOLE_POLL 616 + static int esp32_uart_earlycon_read(struct console *con, char *s, unsigned int n) 617 + { 618 + struct earlycon_device *dev = con->data; 619 + unsigned int num_read = 0; 620 + 621 + while (num_read < n) { 622 + int c = esp32_uart_poll_get_char(&dev->port); 623 + 624 + if (c == NO_POLL_CHAR) 625 + break; 626 + s[num_read++] = c; 627 + } 628 + return num_read; 629 + } 630 + #endif 631 + 632 + static int __init esp32xx_uart_early_console_setup(struct earlycon_device *device, 633 + const char *options) 634 + { 635 + if (!device->port.membase) 636 + return -ENODEV; 637 + 638 + device->con->write = esp32_uart_earlycon_write; 639 + #ifdef CONFIG_CONSOLE_POLL 640 + device->con->read = esp32_uart_earlycon_read; 641 + #endif 642 + if (device->port.uartclk != BASE_BAUD * 16) 643 + esp32_uart_set_baud(&device->port, device->baud); 644 + 645 + return 0; 646 + } 647 + 648 + static int __init esp32_uart_early_console_setup(struct earlycon_device *device, 649 + const char *options) 650 + { 651 + device->port.private_data = (void *)&esp32_variant; 652 + 653 + return esp32xx_uart_early_console_setup(device, options); 654 + } 655 + 656 + OF_EARLYCON_DECLARE(esp32uart, "esp,esp32-uart", 657 + esp32_uart_early_console_setup); 658 + 659 + static int __init esp32s3_uart_early_console_setup(struct earlycon_device *device, 660 + const char *options) 661 + { 662 + device->port.private_data = (void *)&esp32s3_variant; 663 + 664 + return esp32xx_uart_early_console_setup(device, options); 665 + } 666 + 667 + OF_EARLYCON_DECLARE(esp32s3uart, "esp,esp32s3-uart", 668 + esp32s3_uart_early_console_setup); 669 + 670 + static struct uart_driver esp32_uart_reg = { 671 + .owner = THIS_MODULE, 672 + .driver_name = DRIVER_NAME, 673 + .dev_name = DEV_NAME, 674 + .nr = ARRAY_SIZE(esp32_uart_ports), 675 + .cons = &esp32_uart_console, 676 + }; 677 + 678 + static int esp32_uart_probe(struct platform_device *pdev) 679 + { 680 + struct device_node *np = pdev->dev.of_node; 681 + static const struct of_device_id *match; 682 + struct uart_port *port; 683 + struct esp32_port *sport; 684 + struct resource *res; 685 + int ret; 686 + 687 + match = of_match_device(esp32_uart_dt_ids, &pdev->dev); 688 + if (!match) 689 + return -ENODEV; 690 + 691 + sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 692 + if (!sport) 693 + return -ENOMEM; 694 + 695 + port = &sport->port; 696 + 697 + ret = of_alias_get_id(np, "serial"); 698 + if (ret < 0) { 699 + dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 700 + return ret; 701 + } 702 + if (ret >= UART_NR) { 703 + dev_err(&pdev->dev, "driver limited to %d serial ports\n", UART_NR); 704 + return -ENOMEM; 705 + } 706 + 707 + port->line = ret; 708 + 709 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 710 + if (!res) 711 + return -ENODEV; 712 + 713 + port->mapbase = res->start; 714 + port->membase = devm_ioremap_resource(&pdev->dev, res); 715 + if (IS_ERR(port->membase)) 716 + return PTR_ERR(port->membase); 717 + 718 + sport->clk = devm_clk_get(&pdev->dev, NULL); 719 + if (IS_ERR(sport->clk)) 720 + return PTR_ERR(sport->clk); 721 + 722 + port->uartclk = clk_get_rate(sport->clk); 723 + port->dev = &pdev->dev; 724 + port->type = PORT_GENERIC; 725 + port->iotype = UPIO_MEM; 726 + port->irq = platform_get_irq(pdev, 0); 727 + port->ops = &esp32_uart_pops; 728 + port->flags = UPF_BOOT_AUTOCONF; 729 + port->has_sysrq = 1; 730 + port->fifosize = ESP32_UART_TX_FIFO_SIZE; 731 + port->private_data = (void *)match->data; 732 + 733 + esp32_uart_ports[port->line] = sport; 734 + 735 + platform_set_drvdata(pdev, port); 736 + 737 + return uart_add_one_port(&esp32_uart_reg, port); 738 + } 739 + 740 + static int esp32_uart_remove(struct platform_device *pdev) 741 + { 742 + struct uart_port *port = platform_get_drvdata(pdev); 743 + 744 + uart_remove_one_port(&esp32_uart_reg, port); 745 + 746 + return 0; 747 + } 748 + 749 + 750 + static struct platform_driver esp32_uart_driver = { 751 + .probe = esp32_uart_probe, 752 + .remove = esp32_uart_remove, 753 + .driver = { 754 + .name = DRIVER_NAME, 755 + .of_match_table = esp32_uart_dt_ids, 756 + }, 757 + }; 758 + 759 + static int __init esp32_uart_init(void) 760 + { 761 + int ret; 762 + 763 + ret = uart_register_driver(&esp32_uart_reg); 764 + if (ret) 765 + return ret; 766 + 767 + ret = platform_driver_register(&esp32_uart_driver); 768 + if (ret) 769 + uart_unregister_driver(&esp32_uart_reg); 770 + 771 + return ret; 772 + } 773 + 774 + static void __exit esp32_uart_exit(void) 775 + { 776 + platform_driver_unregister(&esp32_uart_driver); 777 + uart_unregister_driver(&esp32_uart_reg); 778 + } 779 + 780 + module_init(esp32_uart_init); 781 + module_exit(esp32_uart_exit); 782 + 783 + MODULE_AUTHOR("Max Filippov <jcmvbkbc@gmail.com>"); 784 + MODULE_LICENSE("GPL");

+18 -14

drivers/tty/serial/fsl_linflexuart.c

··· 203 203 struct circ_buf *xmit = &sport->state->xmit; 204 204 unsigned long flags; 205 205 206 - spin_lock_irqsave(&sport->lock, flags); 206 + uart_port_lock_irqsave(sport, &flags); 207 207 208 208 if (sport->x_char) { 209 209 linflex_put_char(sport, sport->x_char); ··· 217 217 218 218 linflex_transmit_buffer(sport); 219 219 out: 220 - spin_unlock_irqrestore(&sport->lock, flags); 220 + uart_port_unlock_irqrestore(sport, flags); 221 221 return IRQ_HANDLED; 222 222 } 223 223 ··· 230 230 unsigned char rx; 231 231 bool brk; 232 232 233 - spin_lock_irqsave(&sport->lock, flags); 233 + uart_port_lock_irqsave(sport, &flags); 234 234 235 235 status = readl(sport->membase + UARTSR); 236 236 while (status & LINFLEXD_UARTSR_RMB) { ··· 266 266 } 267 267 } 268 268 269 - spin_unlock_irqrestore(&sport->lock, flags); 269 + uart_port_unlock_irqrestore(sport, flags); 270 270 271 271 tty_flip_buffer_push(port); 272 272 ··· 369 369 int ret = 0; 370 370 unsigned long flags; 371 371 372 - spin_lock_irqsave(&port->lock, flags); 372 + uart_port_lock_irqsave(port, &flags); 373 373 374 374 linflex_setup_watermark(port); 375 375 376 - spin_unlock_irqrestore(&port->lock, flags); 376 + uart_port_unlock_irqrestore(port, flags); 377 377 378 378 ret = devm_request_irq(port->dev, port->irq, linflex_int, 0, 379 379 DRIVER_NAME, port); ··· 386 386 unsigned long ier; 387 387 unsigned long flags; 388 388 389 - spin_lock_irqsave(&port->lock, flags); 389 + uart_port_lock_irqsave(port, &flags); 390 390 391 391 /* disable interrupts */ 392 392 ier = readl(port->membase + LINIER); 393 393 ier &= ~(LINFLEXD_LINIER_DRIE | LINFLEXD_LINIER_DTIE); 394 394 writel(ier, port->membase + LINIER); 395 395 396 - spin_unlock_irqrestore(&port->lock, flags); 396 + uart_port_unlock_irqrestore(port, flags); 397 397 398 398 devm_free_irq(port->dev, port->irq, port); 399 399 } ··· 474 474 cr &= ~LINFLEXD_UARTCR_PCE; 475 475 } 476 476 477 - spin_lock_irqsave(&port->lock, flags); 477 + uart_port_lock_irqsave(port, &flags); 478 478 479 479 port->read_status_mask = 0; 480 480 ··· 507 507 508 508 writel(cr1, port->membase + LINCR1); 509 509 510 - spin_unlock_irqrestore(&port->lock, flags); 510 + uart_port_unlock_irqrestore(port, flags); 511 511 } 512 512 513 513 static const char *linflex_type(struct uart_port *port) ··· 646 646 if (sport->sysrq) 647 647 locked = 0; 648 648 else if (oops_in_progress) 649 - locked = spin_trylock_irqsave(&sport->lock, flags); 649 + locked = uart_port_trylock_irqsave(sport, &flags); 650 650 else 651 - spin_lock_irqsave(&sport->lock, flags); 651 + uart_port_lock_irqsave(sport, &flags); 652 652 653 653 linflex_string_write(sport, s, count); 654 654 655 655 if (locked) 656 - spin_unlock_irqrestore(&sport->lock, flags); 656 + uart_port_unlock_irqrestore(sport, flags); 657 657 } 658 658 659 659 /* ··· 832 832 return PTR_ERR(sport->membase); 833 833 sport->mapbase = res->start; 834 834 835 + ret = platform_get_irq(pdev, 0); 836 + if (ret < 0) 837 + return ret; 838 + 835 839 sport->dev = &pdev->dev; 836 840 sport->type = PORT_LINFLEXUART; 837 841 sport->iotype = UPIO_MEM; 838 - sport->irq = platform_get_irq(pdev, 0); 842 + sport->irq = ret; 839 843 sport->ops = &linflex_pops; 840 844 sport->flags = UPF_BOOT_AUTOCONF; 841 845 sport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LINFLEXUART_CONSOLE);

+44 -44

drivers/tty/serial/fsl_lpuart.c

··· 532 532 struct dma_chan *chan = sport->dma_tx_chan; 533 533 unsigned long flags; 534 534 535 - spin_lock_irqsave(&sport->port.lock, flags); 535 + uart_port_lock_irqsave(&sport->port, &flags); 536 536 if (!sport->dma_tx_in_progress) { 537 - spin_unlock_irqrestore(&sport->port.lock, flags); 537 + uart_port_unlock_irqrestore(&sport->port, flags); 538 538 return; 539 539 } 540 540 ··· 543 543 544 544 uart_xmit_advance(&sport->port, sport->dma_tx_bytes); 545 545 sport->dma_tx_in_progress = false; 546 - spin_unlock_irqrestore(&sport->port.lock, flags); 546 + uart_port_unlock_irqrestore(&sport->port, flags); 547 547 548 548 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 549 549 uart_write_wakeup(&sport->port); ··· 553 553 return; 554 554 } 555 555 556 - spin_lock_irqsave(&sport->port.lock, flags); 556 + uart_port_lock_irqsave(&sport->port, &flags); 557 557 558 558 if (!lpuart_stopped_or_empty(&sport->port)) 559 559 lpuart_dma_tx(sport); 560 560 561 - spin_unlock_irqrestore(&sport->port.lock, flags); 561 + uart_port_unlock_irqrestore(&sport->port, flags); 562 562 } 563 563 564 564 static dma_addr_t lpuart_dma_datareg_addr(struct lpuart_port *sport) ··· 651 651 652 652 sport->port.fifosize = 0; 653 653 654 - spin_lock_irqsave(&sport->port.lock, flags); 654 + uart_port_lock_irqsave(&sport->port, &flags); 655 655 /* Disable Rx & Tx */ 656 656 writeb(0, sport->port.membase + UARTCR2); 657 657 ··· 675 675 676 676 /* Enable Rx and Tx */ 677 677 writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2); 678 - spin_unlock_irqrestore(&sport->port.lock, flags); 678 + uart_port_unlock_irqrestore(&sport->port, flags); 679 679 680 680 return 0; 681 681 } ··· 703 703 704 704 sport->port.fifosize = 0; 705 705 706 - spin_lock_irqsave(&sport->port.lock, flags); 706 + uart_port_lock_irqsave(&sport->port, &flags); 707 707 708 708 /* Disable Rx & Tx */ 709 709 lpuart32_write(&sport->port, 0, UARTCTRL); ··· 724 724 725 725 /* Enable Rx and Tx */ 726 726 lpuart32_write(&sport->port, UARTCTRL_RE | UARTCTRL_TE, UARTCTRL); 727 - spin_unlock_irqrestore(&sport->port.lock, flags); 727 + uart_port_unlock_irqrestore(&sport->port, flags); 728 728 729 729 return 0; 730 730 } ··· 879 879 880 880 static void lpuart_txint(struct lpuart_port *sport) 881 881 { 882 - spin_lock(&sport->port.lock); 882 + uart_port_lock(&sport->port); 883 883 lpuart_transmit_buffer(sport); 884 - spin_unlock(&sport->port.lock); 884 + uart_port_unlock(&sport->port); 885 885 } 886 886 887 887 static void lpuart_rxint(struct lpuart_port *sport) ··· 890 890 struct tty_port *port = &sport->port.state->port; 891 891 unsigned char rx, sr; 892 892 893 - spin_lock(&sport->port.lock); 893 + uart_port_lock(&sport->port); 894 894 895 895 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) { 896 896 flg = TTY_NORMAL; ··· 956 956 957 957 static void lpuart32_txint(struct lpuart_port *sport) 958 958 { 959 - spin_lock(&sport->port.lock); 959 + uart_port_lock(&sport->port); 960 960 lpuart32_transmit_buffer(sport); 961 - spin_unlock(&sport->port.lock); 961 + uart_port_unlock(&sport->port); 962 962 } 963 963 964 964 static void lpuart32_rxint(struct lpuart_port *sport) ··· 968 968 unsigned long rx, sr; 969 969 bool is_break; 970 970 971 - spin_lock(&sport->port.lock); 971 + uart_port_lock(&sport->port); 972 972 973 973 while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) { 974 974 flg = TTY_NORMAL; ··· 1170 1170 1171 1171 async_tx_ack(sport->dma_rx_desc); 1172 1172 1173 - spin_lock_irqsave(&sport->port.lock, flags); 1173 + uart_port_lock_irqsave(&sport->port, &flags); 1174 1174 1175 1175 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state); 1176 1176 if (dmastat == DMA_ERROR) { 1177 1177 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); 1178 - spin_unlock_irqrestore(&sport->port.lock, flags); 1178 + uart_port_unlock_irqrestore(&sport->port, flags); 1179 1179 return; 1180 1180 } 1181 1181 ··· 1244 1244 dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1, 1245 1245 DMA_FROM_DEVICE); 1246 1246 1247 - spin_unlock_irqrestore(&sport->port.lock, flags); 1247 + uart_port_unlock_irqrestore(&sport->port, flags); 1248 1248 1249 1249 tty_flip_buffer_push(port); 1250 1250 if (!sport->dma_idle_int) ··· 1335 1335 mod_timer(&sport->lpuart_timer, 1336 1336 jiffies + sport->dma_rx_timeout); 1337 1337 1338 - if (spin_trylock_irqsave(&sport->port.lock, flags)) { 1338 + if (uart_port_trylock_irqsave(&sport->port, &flags)) { 1339 1339 sport->last_residue = state.residue; 1340 - spin_unlock_irqrestore(&sport->port.lock, flags); 1340 + uart_port_unlock_irqrestore(&sport->port, flags); 1341 1341 } 1342 1342 } 1343 1343 ··· 1802 1802 { 1803 1803 unsigned long flags; 1804 1804 1805 - spin_lock_irqsave(&sport->port.lock, flags); 1805 + uart_port_lock_irqsave(&sport->port, &flags); 1806 1806 1807 1807 lpuart_setup_watermark_enable(sport); 1808 1808 1809 1809 lpuart_rx_dma_startup(sport); 1810 1810 lpuart_tx_dma_startup(sport); 1811 1811 1812 - spin_unlock_irqrestore(&sport->port.lock, flags); 1812 + uart_port_unlock_irqrestore(&sport->port, flags); 1813 1813 } 1814 1814 1815 1815 static int lpuart_startup(struct uart_port *port) ··· 1859 1859 { 1860 1860 unsigned long flags; 1861 1861 1862 - spin_lock_irqsave(&sport->port.lock, flags); 1862 + uart_port_lock_irqsave(&sport->port, &flags); 1863 1863 1864 1864 lpuart32_hw_disable(sport); 1865 1865 ··· 1869 1869 lpuart32_setup_watermark_enable(sport); 1870 1870 lpuart32_configure(sport); 1871 1871 1872 - spin_unlock_irqrestore(&sport->port.lock, flags); 1872 + uart_port_unlock_irqrestore(&sport->port, flags); 1873 1873 } 1874 1874 1875 1875 static int lpuart32_startup(struct uart_port *port) ··· 1932 1932 unsigned char temp; 1933 1933 unsigned long flags; 1934 1934 1935 - spin_lock_irqsave(&port->lock, flags); 1935 + uart_port_lock_irqsave(port, &flags); 1936 1936 1937 1937 /* disable Rx/Tx and interrupts */ 1938 1938 temp = readb(port->membase + UARTCR2); ··· 1940 1940 UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); 1941 1941 writeb(temp, port->membase + UARTCR2); 1942 1942 1943 - spin_unlock_irqrestore(&port->lock, flags); 1943 + uart_port_unlock_irqrestore(port, flags); 1944 1944 1945 1945 lpuart_dma_shutdown(sport); 1946 1946 } ··· 1952 1952 unsigned long temp; 1953 1953 unsigned long flags; 1954 1954 1955 - spin_lock_irqsave(&port->lock, flags); 1955 + uart_port_lock_irqsave(port, &flags); 1956 1956 1957 1957 /* clear status */ 1958 1958 temp = lpuart32_read(&sport->port, UARTSTAT); ··· 1969 1969 UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE | UARTCTRL_SBK); 1970 1970 lpuart32_write(port, temp, UARTCTRL); 1971 1971 1972 - spin_unlock_irqrestore(&port->lock, flags); 1972 + uart_port_unlock_irqrestore(port, flags); 1973 1973 1974 1974 lpuart_dma_shutdown(sport); 1975 1975 } ··· 2069 2069 if (old && sport->lpuart_dma_rx_use) 2070 2070 lpuart_dma_rx_free(&sport->port); 2071 2071 2072 - spin_lock_irqsave(&sport->port.lock, flags); 2072 + uart_port_lock_irqsave(&sport->port, &flags); 2073 2073 2074 2074 sport->port.read_status_mask = 0; 2075 2075 if (termios->c_iflag & INPCK) ··· 2124 2124 sport->lpuart_dma_rx_use = false; 2125 2125 } 2126 2126 2127 - spin_unlock_irqrestore(&sport->port.lock, flags); 2127 + uart_port_unlock_irqrestore(&sport->port, flags); 2128 2128 } 2129 2129 2130 2130 static void __lpuart32_serial_setbrg(struct uart_port *port, ··· 2304 2304 if (old && sport->lpuart_dma_rx_use) 2305 2305 lpuart_dma_rx_free(&sport->port); 2306 2306 2307 - spin_lock_irqsave(&sport->port.lock, flags); 2307 + uart_port_lock_irqsave(&sport->port, &flags); 2308 2308 2309 2309 sport->port.read_status_mask = 0; 2310 2310 if (termios->c_iflag & INPCK) ··· 2359 2359 sport->lpuart_dma_rx_use = false; 2360 2360 } 2361 2361 2362 - spin_unlock_irqrestore(&sport->port.lock, flags); 2362 + uart_port_unlock_irqrestore(&sport->port, flags); 2363 2363 } 2364 2364 2365 2365 static const char *lpuart_type(struct uart_port *port) ··· 2477 2477 int locked = 1; 2478 2478 2479 2479 if (oops_in_progress) 2480 - locked = spin_trylock_irqsave(&sport->port.lock, flags); 2480 + locked = uart_port_trylock_irqsave(&sport->port, &flags); 2481 2481 else 2482 - spin_lock_irqsave(&sport->port.lock, flags); 2482 + uart_port_lock_irqsave(&sport->port, &flags); 2483 2483 2484 2484 /* first save CR2 and then disable interrupts */ 2485 2485 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2); ··· 2495 2495 writeb(old_cr2, sport->port.membase + UARTCR2); 2496 2496 2497 2497 if (locked) 2498 - spin_unlock_irqrestore(&sport->port.lock, flags); 2498 + uart_port_unlock_irqrestore(&sport->port, flags); 2499 2499 } 2500 2500 2501 2501 static void ··· 2507 2507 int locked = 1; 2508 2508 2509 2509 if (oops_in_progress) 2510 - locked = spin_trylock_irqsave(&sport->port.lock, flags); 2510 + locked = uart_port_trylock_irqsave(&sport->port, &flags); 2511 2511 else 2512 - spin_lock_irqsave(&sport->port.lock, flags); 2512 + uart_port_lock_irqsave(&sport->port, &flags); 2513 2513 2514 2514 /* first save CR2 and then disable interrupts */ 2515 2515 cr = old_cr = lpuart32_read(&sport->port, UARTCTRL); ··· 2525 2525 lpuart32_write(&sport->port, old_cr, UARTCTRL); 2526 2526 2527 2527 if (locked) 2528 - spin_unlock_irqrestore(&sport->port.lock, flags); 2528 + uart_port_unlock_irqrestore(&sport->port, flags); 2529 2529 } 2530 2530 2531 2531 /* ··· 3089 3089 uart_suspend_port(&lpuart_reg, &sport->port); 3090 3090 3091 3091 if (lpuart_uport_is_active(sport)) { 3092 - spin_lock_irqsave(&sport->port.lock, flags); 3092 + uart_port_lock_irqsave(&sport->port, &flags); 3093 3093 if (lpuart_is_32(sport)) { 3094 3094 /* disable Rx/Tx and interrupts */ 3095 3095 temp = lpuart32_read(&sport->port, UARTCTRL); ··· 3101 3101 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE); 3102 3102 writeb(temp, sport->port.membase + UARTCR2); 3103 3103 } 3104 - spin_unlock_irqrestore(&sport->port.lock, flags); 3104 + uart_port_unlock_irqrestore(&sport->port, flags); 3105 3105 3106 3106 if (sport->lpuart_dma_rx_use) { 3107 3107 /* ··· 3114 3114 lpuart_dma_rx_free(&sport->port); 3115 3115 3116 3116 /* Disable Rx DMA to use UART port as wakeup source */ 3117 - spin_lock_irqsave(&sport->port.lock, flags); 3117 + uart_port_lock_irqsave(&sport->port, &flags); 3118 3118 if (lpuart_is_32(sport)) { 3119 3119 temp = lpuart32_read(&sport->port, UARTBAUD); 3120 3120 lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE, ··· 3123 3123 writeb(readb(sport->port.membase + UARTCR5) & 3124 3124 ~UARTCR5_RDMAS, sport->port.membase + UARTCR5); 3125 3125 } 3126 - spin_unlock_irqrestore(&sport->port.lock, flags); 3126 + uart_port_unlock_irqrestore(&sport->port, flags); 3127 3127 } 3128 3128 3129 3129 if (sport->lpuart_dma_tx_use) { 3130 - spin_lock_irqsave(&sport->port.lock, flags); 3130 + uart_port_lock_irqsave(&sport->port, &flags); 3131 3131 if (lpuart_is_32(sport)) { 3132 3132 temp = lpuart32_read(&sport->port, UARTBAUD); 3133 3133 temp &= ~UARTBAUD_TDMAE; ··· 3137 3137 temp &= ~UARTCR5_TDMAS; 3138 3138 writeb(temp, sport->port.membase + UARTCR5); 3139 3139 } 3140 - spin_unlock_irqrestore(&sport->port.lock, flags); 3140 + uart_port_unlock_irqrestore(&sport->port, flags); 3141 3141 sport->dma_tx_in_progress = false; 3142 3142 dmaengine_terminate_sync(sport->dma_tx_chan); 3143 3143 }

+13 -13

drivers/tty/serial/icom.c

··· 929 929 char delta_status; 930 930 unsigned char status; 931 931 932 - spin_lock(&icom_port->uart_port.lock); 932 + uart_port_lock(&icom_port->uart_port); 933 933 934 934 /*modem input register */ 935 935 status = readb(&icom_port->dram->isr); ··· 951 951 port.delta_msr_wait); 952 952 old_status = status; 953 953 } 954 - spin_unlock(&icom_port->uart_port.lock); 954 + uart_port_unlock(&icom_port->uart_port); 955 955 } 956 956 957 957 static void xmit_interrupt(u16 port_int_reg, struct icom_port *icom_port) ··· 1093 1093 struct icom_port *icom_port) 1094 1094 { 1095 1095 1096 - spin_lock(&icom_port->uart_port.lock); 1096 + uart_port_lock(&icom_port->uart_port); 1097 1097 trace(icom_port, "INTERRUPT", port_int_reg); 1098 1098 1099 1099 if (port_int_reg & (INT_XMIT_COMPLETED | INT_XMIT_DISABLED)) ··· 1102 1102 if (port_int_reg & INT_RCV_COMPLETED) 1103 1103 recv_interrupt(port_int_reg, icom_port); 1104 1104 1105 - spin_unlock(&icom_port->uart_port.lock); 1105 + uart_port_unlock(&icom_port->uart_port); 1106 1106 } 1107 1107 1108 1108 static irqreturn_t icom_interrupt(int irq, void *dev_id) ··· 1186 1186 int ret; 1187 1187 unsigned long flags; 1188 1188 1189 - spin_lock_irqsave(&port->lock, flags); 1189 + uart_port_lock_irqsave(port, &flags); 1190 1190 if (le16_to_cpu(icom_port->statStg->xmit[0].flags) & 1191 1191 SA_FLAGS_READY_TO_XMIT) 1192 1192 ret = TIOCSER_TEMT; 1193 1193 else 1194 1194 ret = 0; 1195 1195 1196 - spin_unlock_irqrestore(&port->lock, flags); 1196 + uart_port_unlock_irqrestore(port, flags); 1197 1197 return ret; 1198 1198 } 1199 1199 ··· 1276 1276 1277 1277 /* wait .1 sec to send char */ 1278 1278 for (index = 0; index < 10; index++) { 1279 - spin_lock_irqsave(&port->lock, flags); 1279 + uart_port_lock_irqsave(port, &flags); 1280 1280 xdata = readb(&icom_port->dram->xchar); 1281 1281 if (xdata == 0x00) { 1282 1282 trace(icom_port, "QUICK_WRITE", 0); ··· 1284 1284 1285 1285 /* flush write operation */ 1286 1286 xdata = readb(&icom_port->dram->xchar); 1287 - spin_unlock_irqrestore(&port->lock, flags); 1287 + uart_port_unlock_irqrestore(port, flags); 1288 1288 break; 1289 1289 } 1290 - spin_unlock_irqrestore(&port->lock, flags); 1290 + uart_port_unlock_irqrestore(port, flags); 1291 1291 msleep(10); 1292 1292 } 1293 1293 } ··· 1307 1307 unsigned char cmdReg; 1308 1308 unsigned long flags; 1309 1309 1310 - spin_lock_irqsave(&port->lock, flags); 1310 + uart_port_lock_irqsave(port, &flags); 1311 1311 trace(icom_port, "BREAK", 0); 1312 1312 cmdReg = readb(&icom_port->dram->CmdReg); 1313 1313 if (break_state == -1) { ··· 1315 1315 } else { 1316 1316 writeb(cmdReg & ~CMD_SND_BREAK, &icom_port->dram->CmdReg); 1317 1317 } 1318 - spin_unlock_irqrestore(&port->lock, flags); 1318 + uart_port_unlock_irqrestore(port, flags); 1319 1319 } 1320 1320 1321 1321 static int icom_open(struct uart_port *port) ··· 1365 1365 unsigned long offset; 1366 1366 unsigned long flags; 1367 1367 1368 - spin_lock_irqsave(&port->lock, flags); 1368 + uart_port_lock_irqsave(port, &flags); 1369 1369 trace(icom_port, "CHANGE_SPEED", 0); 1370 1370 1371 1371 cflag = termios->c_cflag; ··· 1516 1516 trace(icom_port, "XR_ENAB", 0); 1517 1517 writeb(CMD_XMIT_RCV_ENABLE, &icom_port->dram->CmdReg); 1518 1518 1519 - spin_unlock_irqrestore(&port->lock, flags); 1519 + uart_port_unlock_irqrestore(port, flags); 1520 1520 } 1521 1521 1522 1522 static const char *icom_type(struct uart_port *port)

+62 -66

drivers/tty/serial/imx.c

··· 177 177 enum imx_uart_type { 178 178 IMX1_UART, 179 179 IMX21_UART, 180 - IMX53_UART, 181 - IMX6Q_UART, 182 180 }; 183 181 184 182 /* device type dependent stuff */ ··· 238 240 unsigned int ucr3; 239 241 }; 240 242 241 - static struct imx_uart_data imx_uart_devdata[] = { 242 - [IMX1_UART] = { 243 - .uts_reg = IMX1_UTS, 244 - .devtype = IMX1_UART, 245 - }, 246 - [IMX21_UART] = { 247 - .uts_reg = IMX21_UTS, 248 - .devtype = IMX21_UART, 249 - }, 250 - [IMX53_UART] = { 251 - .uts_reg = IMX21_UTS, 252 - .devtype = IMX53_UART, 253 - }, 254 - [IMX6Q_UART] = { 255 - .uts_reg = IMX21_UTS, 256 - .devtype = IMX6Q_UART, 257 - }, 243 + static const struct imx_uart_data imx_uart_imx1_devdata = { 244 + .uts_reg = IMX1_UTS, 245 + .devtype = IMX1_UART, 246 + }; 247 + 248 + static const struct imx_uart_data imx_uart_imx21_devdata = { 249 + .uts_reg = IMX21_UTS, 250 + .devtype = IMX21_UART, 258 251 }; 259 252 260 253 static const struct of_device_id imx_uart_dt_ids[] = { 261 - { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], }, 262 - { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], }, 263 - { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], }, 264 - { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], }, 254 + /* 255 + * For reasons unknown to me, some UART devices (e.g. imx6ul's) are 256 + * compatible to fsl,imx6q-uart, but not fsl,imx21-uart, while the 257 + * original imx6q's UART is compatible to fsl,imx21-uart. This driver 258 + * doesn't make any distinction between these two variants. 259 + */ 260 + { .compatible = "fsl,imx6q-uart", .data = &imx_uart_imx21_devdata, }, 261 + { .compatible = "fsl,imx1-uart", .data = &imx_uart_imx1_devdata, }, 262 + { .compatible = "fsl,imx21-uart", .data = &imx_uart_imx21_devdata, }, 265 263 { /* sentinel */ } 266 264 }; 267 265 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); ··· 569 575 unsigned long flags; 570 576 u32 ucr1; 571 577 572 - spin_lock_irqsave(&sport->port.lock, flags); 578 + uart_port_lock_irqsave(&sport->port, &flags); 573 579 574 580 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE); 575 581 ··· 594 600 imx_uart_writel(sport, ucr4, UCR4); 595 601 } 596 602 597 - spin_unlock_irqrestore(&sport->port.lock, flags); 603 + uart_port_unlock_irqrestore(&sport->port, flags); 598 604 } 599 605 600 606 /* called with port.lock taken and irqs off */ ··· 760 766 struct imx_port *sport = dev_id; 761 767 irqreturn_t ret; 762 768 763 - spin_lock(&sport->port.lock); 769 + uart_port_lock(&sport->port); 764 770 765 771 ret = __imx_uart_rtsint(irq, dev_id); 766 772 767 - spin_unlock(&sport->port.lock); 773 + uart_port_unlock(&sport->port); 768 774 769 775 return ret; 770 776 } ··· 773 779 { 774 780 struct imx_port *sport = dev_id; 775 781 776 - spin_lock(&sport->port.lock); 782 + uart_port_lock(&sport->port); 777 783 imx_uart_transmit_buffer(sport); 778 - spin_unlock(&sport->port.lock); 784 + uart_port_unlock(&sport->port); 779 785 return IRQ_HANDLED; 780 786 } 781 787 ··· 889 895 struct imx_port *sport = dev_id; 890 896 irqreturn_t ret; 891 897 892 - spin_lock(&sport->port.lock); 898 + uart_port_lock(&sport->port); 893 899 894 900 ret = __imx_uart_rxint(irq, dev_id); 895 901 896 - spin_unlock(&sport->port.lock); 902 + uart_port_unlock(&sport->port); 897 903 898 904 return ret; 899 905 } ··· 956 962 unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4; 957 963 irqreturn_t ret = IRQ_NONE; 958 964 959 - spin_lock(&sport->port.lock); 965 + uart_port_lock(&sport->port); 960 966 961 967 usr1 = imx_uart_readl(sport, USR1); 962 968 usr2 = imx_uart_readl(sport, USR2); ··· 1026 1032 ret = IRQ_HANDLED; 1027 1033 } 1028 1034 1029 - spin_unlock(&sport->port.lock); 1035 + uart_port_unlock(&sport->port); 1030 1036 1031 1037 return ret; 1032 1038 } ··· 1109 1115 unsigned long flags; 1110 1116 u32 ucr1; 1111 1117 1112 - spin_lock_irqsave(&sport->port.lock, flags); 1118 + uart_port_lock_irqsave(&sport->port, &flags); 1113 1119 1114 1120 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK; 1115 1121 ··· 1118 1124 1119 1125 imx_uart_writel(sport, ucr1, UCR1); 1120 1126 1121 - spin_unlock_irqrestore(&sport->port.lock, flags); 1127 + uart_port_unlock_irqrestore(&sport->port, flags); 1122 1128 } 1123 1129 1124 1130 /* ··· 1131 1137 unsigned long flags; 1132 1138 1133 1139 if (sport->port.state) { 1134 - spin_lock_irqsave(&sport->port.lock, flags); 1140 + uart_port_lock_irqsave(&sport->port, &flags); 1135 1141 imx_uart_mctrl_check(sport); 1136 - spin_unlock_irqrestore(&sport->port.lock, flags); 1142 + uart_port_unlock_irqrestore(&sport->port, flags); 1137 1143 1138 1144 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 1139 1145 } ··· 1163 1169 status = dmaengine_tx_status(chan, sport->rx_cookie, &state); 1164 1170 1165 1171 if (status == DMA_ERROR) { 1166 - spin_lock(&sport->port.lock); 1172 + uart_port_lock(&sport->port); 1167 1173 imx_uart_clear_rx_errors(sport); 1168 - spin_unlock(&sport->port.lock); 1174 + uart_port_unlock(&sport->port); 1169 1175 return; 1170 1176 } 1171 1177 ··· 1194 1200 r_bytes = rx_ring->head - rx_ring->tail; 1195 1201 1196 1202 /* If we received something, check for 0xff flood */ 1197 - spin_lock(&sport->port.lock); 1203 + uart_port_lock(&sport->port); 1198 1204 imx_uart_check_flood(sport, imx_uart_readl(sport, USR2)); 1199 - spin_unlock(&sport->port.lock); 1205 + uart_port_unlock(&sport->port); 1200 1206 1201 1207 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) { 1202 1208 ··· 1451 1457 imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4); 1452 1458 1453 1459 /* Can we enable the DMA support? */ 1454 - if (!uart_console(port) && imx_uart_dma_init(sport) == 0) 1460 + if (!uart_console(port) && imx_uart_dma_init(sport) == 0) { 1461 + lockdep_set_subclass(&port->lock, 1); 1455 1462 dma_is_inited = 1; 1463 + } 1456 1464 1457 - spin_lock_irqsave(&sport->port.lock, flags); 1465 + uart_port_lock_irqsave(&sport->port, &flags); 1458 1466 1459 1467 /* Reset fifo's and state machines */ 1460 1468 imx_uart_soft_reset(sport); ··· 1529 1533 1530 1534 imx_uart_disable_loopback_rs485(sport); 1531 1535 1532 - spin_unlock_irqrestore(&sport->port.lock, flags); 1536 + uart_port_unlock_irqrestore(&sport->port, flags); 1533 1537 1534 1538 return 0; 1535 1539 } ··· 1554 1558 sport->dma_is_rxing = 0; 1555 1559 } 1556 1560 1557 - spin_lock_irqsave(&sport->port.lock, flags); 1561 + uart_port_lock_irqsave(&sport->port, &flags); 1558 1562 imx_uart_stop_tx(port); 1559 1563 imx_uart_stop_rx(port); 1560 1564 imx_uart_disable_dma(sport); 1561 - spin_unlock_irqrestore(&sport->port.lock, flags); 1565 + uart_port_unlock_irqrestore(&sport->port, flags); 1562 1566 imx_uart_dma_exit(sport); 1563 1567 } 1564 1568 1565 1569 mctrl_gpio_disable_ms(sport->gpios); 1566 1570 1567 - spin_lock_irqsave(&sport->port.lock, flags); 1571 + uart_port_lock_irqsave(&sport->port, &flags); 1568 1572 ucr2 = imx_uart_readl(sport, UCR2); 1569 1573 ucr2 &= ~(UCR2_TXEN | UCR2_ATEN); 1570 1574 imx_uart_writel(sport, ucr2, UCR2); 1571 - spin_unlock_irqrestore(&sport->port.lock, flags); 1575 + uart_port_unlock_irqrestore(&sport->port, flags); 1572 1576 1573 1577 /* 1574 1578 * Stop our timer. ··· 1579 1583 * Disable all interrupts, port and break condition. 1580 1584 */ 1581 1585 1582 - spin_lock_irqsave(&sport->port.lock, flags); 1586 + uart_port_lock_irqsave(&sport->port, &flags); 1583 1587 1584 1588 ucr1 = imx_uart_readl(sport, UCR1); 1585 1589 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_RXDMAEN | ··· 1601 1605 ucr4 &= ~UCR4_TCEN; 1602 1606 imx_uart_writel(sport, ucr4, UCR4); 1603 1607 1604 - spin_unlock_irqrestore(&sport->port.lock, flags); 1608 + uart_port_unlock_irqrestore(&sport->port, flags); 1605 1609 1606 1610 clk_disable_unprepare(sport->clk_per); 1607 1611 clk_disable_unprepare(sport->clk_ipg); ··· 1664 1668 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1665 1669 quot = uart_get_divisor(port, baud); 1666 1670 1667 - spin_lock_irqsave(&sport->port.lock, flags); 1671 + uart_port_lock_irqsave(&sport->port, &flags); 1668 1672 1669 1673 /* 1670 1674 * Read current UCR2 and save it for future use, then clear all the bits ··· 1792 1796 if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 1793 1797 imx_uart_enable_ms(&sport->port); 1794 1798 1795 - spin_unlock_irqrestore(&sport->port.lock, flags); 1799 + uart_port_unlock_irqrestore(&sport->port, flags); 1796 1800 } 1797 1801 1798 1802 static const char *imx_uart_type(struct uart_port *port) ··· 1854 1858 1855 1859 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT); 1856 1860 1857 - spin_lock_irqsave(&sport->port.lock, flags); 1861 + uart_port_lock_irqsave(&sport->port, &flags); 1858 1862 1859 1863 /* 1860 1864 * Be careful about the order of enabling bits here. First enable the ··· 1882 1886 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1); 1883 1887 imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2); 1884 1888 1885 - spin_unlock_irqrestore(&sport->port.lock, flags); 1889 + uart_port_unlock_irqrestore(&sport->port, flags); 1886 1890 1887 1891 return 0; 1888 1892 } ··· 2001 2005 if (sport->port.sysrq) 2002 2006 locked = 0; 2003 2007 else if (oops_in_progress) 2004 - locked = spin_trylock_irqsave(&sport->port.lock, flags); 2008 + locked = uart_port_trylock_irqsave(&sport->port, &flags); 2005 2009 else 2006 - spin_lock_irqsave(&sport->port.lock, flags); 2010 + uart_port_lock_irqsave(&sport->port, &flags); 2007 2011 2008 2012 /* 2009 2013 * First, save UCR1/2/3 and then disable interrupts ··· 2031 2035 imx_uart_ucrs_restore(sport, &old_ucr); 2032 2036 2033 2037 if (locked) 2034 - spin_unlock_irqrestore(&sport->port.lock, flags); 2038 + uart_port_unlock_irqrestore(&sport->port, flags); 2035 2039 } 2036 2040 2037 2041 /* ··· 2189 2193 struct imx_port *sport = container_of(t, struct imx_port, trigger_start_tx); 2190 2194 unsigned long flags; 2191 2195 2192 - spin_lock_irqsave(&sport->port.lock, flags); 2196 + uart_port_lock_irqsave(&sport->port, &flags); 2193 2197 if (sport->tx_state == WAIT_AFTER_RTS) 2194 2198 imx_uart_start_tx(&sport->port); 2195 - spin_unlock_irqrestore(&sport->port.lock, flags); 2199 + uart_port_unlock_irqrestore(&sport->port, flags); 2196 2200 2197 2201 return HRTIMER_NORESTART; 2198 2202 } ··· 2202 2206 struct imx_port *sport = container_of(t, struct imx_port, trigger_stop_tx); 2203 2207 unsigned long flags; 2204 2208 2205 - spin_lock_irqsave(&sport->port.lock, flags); 2209 + uart_port_lock_irqsave(&sport->port, &flags); 2206 2210 if (sport->tx_state == WAIT_AFTER_SEND) 2207 2211 imx_uart_stop_tx(&sport->port); 2208 - spin_unlock_irqrestore(&sport->port.lock, flags); 2212 + uart_port_unlock_irqrestore(&sport->port, flags); 2209 2213 2210 2214 return HRTIMER_NORESTART; 2211 2215 } ··· 2478 2482 { 2479 2483 unsigned long flags; 2480 2484 2481 - spin_lock_irqsave(&sport->port.lock, flags); 2485 + uart_port_lock_irqsave(&sport->port, &flags); 2482 2486 if (!sport->context_saved) { 2483 - spin_unlock_irqrestore(&sport->port.lock, flags); 2487 + uart_port_unlock_irqrestore(&sport->port, flags); 2484 2488 return; 2485 2489 } 2486 2490 ··· 2495 2499 imx_uart_writel(sport, sport->saved_reg[2], UCR3); 2496 2500 imx_uart_writel(sport, sport->saved_reg[3], UCR4); 2497 2501 sport->context_saved = false; 2498 - spin_unlock_irqrestore(&sport->port.lock, flags); 2502 + uart_port_unlock_irqrestore(&sport->port, flags); 2499 2503 } 2500 2504 2501 2505 static void imx_uart_save_context(struct imx_port *sport) ··· 2503 2507 unsigned long flags; 2504 2508 2505 2509 /* Save necessary regs */ 2506 - spin_lock_irqsave(&sport->port.lock, flags); 2510 + uart_port_lock_irqsave(&sport->port, &flags); 2507 2511 sport->saved_reg[0] = imx_uart_readl(sport, UCR1); 2508 2512 sport->saved_reg[1] = imx_uart_readl(sport, UCR2); 2509 2513 sport->saved_reg[2] = imx_uart_readl(sport, UCR3); ··· 2515 2519 sport->saved_reg[8] = imx_uart_readl(sport, UBMR); 2516 2520 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS); 2517 2521 sport->context_saved = true; 2518 - spin_unlock_irqrestore(&sport->port.lock, flags); 2522 + uart_port_unlock_irqrestore(&sport->port, flags); 2519 2523 } 2520 2524 2521 2525 static void imx_uart_enable_wakeup(struct imx_port *sport, bool on)

+18 -18

drivers/tty/serial/ip22zilog.c

··· 432 432 unsigned char r3; 433 433 bool push = false; 434 434 435 - spin_lock(&up->port.lock); 435 + uart_port_lock(&up->port); 436 436 r3 = read_zsreg(channel, R3); 437 437 438 438 /* Channel A */ ··· 448 448 if (r3 & CHATxIP) 449 449 ip22zilog_transmit_chars(up, channel); 450 450 } 451 - spin_unlock(&up->port.lock); 451 + uart_port_unlock(&up->port); 452 452 453 453 if (push) 454 454 tty_flip_buffer_push(&up->port.state->port); ··· 458 458 channel = ZILOG_CHANNEL_FROM_PORT(&up->port); 459 459 push = false; 460 460 461 - spin_lock(&up->port.lock); 461 + uart_port_lock(&up->port); 462 462 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) { 463 463 writeb(RES_H_IUS, &channel->control); 464 464 ZSDELAY(); ··· 471 471 if (r3 & CHBTxIP) 472 472 ip22zilog_transmit_chars(up, channel); 473 473 } 474 - spin_unlock(&up->port.lock); 474 + uart_port_unlock(&up->port); 475 475 476 476 if (push) 477 477 tty_flip_buffer_push(&up->port.state->port); ··· 504 504 unsigned char status; 505 505 unsigned int ret; 506 506 507 - spin_lock_irqsave(&port->lock, flags); 507 + uart_port_lock_irqsave(port, &flags); 508 508 509 509 status = ip22zilog_read_channel_status(port); 510 510 511 - spin_unlock_irqrestore(&port->lock, flags); 511 + uart_port_unlock_irqrestore(port, flags); 512 512 513 513 if (status & Tx_BUF_EMP) 514 514 ret = TIOCSER_TEMT; ··· 664 664 else 665 665 clear_bits |= SND_BRK; 666 666 667 - spin_lock_irqsave(&port->lock, flags); 667 + uart_port_lock_irqsave(port, &flags); 668 668 669 669 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits; 670 670 if (new_reg != up->curregs[R5]) { ··· 674 674 write_zsreg(channel, R5, up->curregs[R5]); 675 675 } 676 676 677 - spin_unlock_irqrestore(&port->lock, flags); 677 + uart_port_unlock_irqrestore(port, flags); 678 678 } 679 679 680 680 static void __ip22zilog_reset(struct uart_ip22zilog_port *up) ··· 735 735 if (ZS_IS_CONS(up)) 736 736 return 0; 737 737 738 - spin_lock_irqsave(&port->lock, flags); 738 + uart_port_lock_irqsave(port, &flags); 739 739 __ip22zilog_startup(up); 740 - spin_unlock_irqrestore(&port->lock, flags); 740 + uart_port_unlock_irqrestore(port, flags); 741 741 return 0; 742 742 } 743 743 ··· 775 775 if (ZS_IS_CONS(up)) 776 776 return; 777 777 778 - spin_lock_irqsave(&port->lock, flags); 778 + uart_port_lock_irqsave(port, &flags); 779 779 780 780 channel = ZILOG_CHANNEL_FROM_PORT(port); 781 781 ··· 788 788 up->curregs[R5] &= ~SND_BRK; 789 789 ip22zilog_maybe_update_regs(up, channel); 790 790 791 - spin_unlock_irqrestore(&port->lock, flags); 791 + uart_port_unlock_irqrestore(port, flags); 792 792 } 793 793 794 794 /* Shared by TTY driver and serial console setup. The port lock is held ··· 880 880 881 881 baud = uart_get_baud_rate(port, termios, old, 1200, 76800); 882 882 883 - spin_lock_irqsave(&up->port.lock, flags); 883 + uart_port_lock_irqsave(&up->port, &flags); 884 884 885 885 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR); 886 886 ··· 894 894 ip22zilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port)); 895 895 uart_update_timeout(port, termios->c_cflag, baud); 896 896 897 - spin_unlock_irqrestore(&up->port.lock, flags); 897 + uart_port_unlock_irqrestore(&up->port, flags); 898 898 } 899 899 900 900 static const char *ip22zilog_type(struct uart_port *port) ··· 1016 1016 struct uart_ip22zilog_port *up = &ip22zilog_port_table[con->index]; 1017 1017 unsigned long flags; 1018 1018 1019 - spin_lock_irqsave(&up->port.lock, flags); 1019 + uart_port_lock_irqsave(&up->port, &flags); 1020 1020 uart_console_write(&up->port, s, count, ip22zilog_put_char); 1021 1021 udelay(2); 1022 - spin_unlock_irqrestore(&up->port.lock, flags); 1022 + uart_port_unlock_irqrestore(&up->port, flags); 1023 1023 } 1024 1024 1025 1025 static int __init ip22zilog_console_setup(struct console *con, char *options) ··· 1034 1034 1035 1035 printk(KERN_INFO "Console: ttyS%d (IP22-Zilog)\n", con->index); 1036 1036 1037 - spin_lock_irqsave(&up->port.lock, flags); 1037 + uart_port_lock_irqsave(&up->port, &flags); 1038 1038 1039 1039 up->curregs[R15] |= BRKIE; 1040 1040 1041 1041 __ip22zilog_startup(up); 1042 1042 1043 - spin_unlock_irqrestore(&up->port.lock, flags); 1043 + uart_port_unlock_irqrestore(&up->port, flags); 1044 1044 1045 1045 if (options) 1046 1046 uart_parse_options(options, &baud, &parity, &bits, &flow);

+2 -2

drivers/tty/serial/jsm/jsm_neo.c

··· 816 816 /* Parse any modem signal changes */ 817 817 jsm_dbg(INTR, &ch->ch_bd->pci_dev, 818 818 "MOD_STAT: sending to parse_modem_sigs\n"); 819 - spin_lock_irqsave(&ch->uart_port.lock, lock_flags); 819 + uart_port_lock_irqsave(&ch->uart_port, &lock_flags); 820 820 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr)); 821 - spin_unlock_irqrestore(&ch->uart_port.lock, lock_flags); 821 + uart_port_unlock_irqrestore(&ch->uart_port, lock_flags); 822 822 } 823 823 } 824 824

+8 -8

drivers/tty/serial/jsm/jsm_tty.c

··· 152 152 container_of(port, struct jsm_channel, uart_port); 153 153 struct ktermios *termios; 154 154 155 - spin_lock_irqsave(&port->lock, lock_flags); 155 + uart_port_lock_irqsave(port, &lock_flags); 156 156 termios = &port->state->port.tty->termios; 157 157 if (ch == termios->c_cc[VSTART]) 158 158 channel->ch_bd->bd_ops->send_start_character(channel); 159 159 160 160 if (ch == termios->c_cc[VSTOP]) 161 161 channel->ch_bd->bd_ops->send_stop_character(channel); 162 - spin_unlock_irqrestore(&port->lock, lock_flags); 162 + uart_port_unlock_irqrestore(port, lock_flags); 163 163 } 164 164 165 165 static void jsm_tty_stop_rx(struct uart_port *port) ··· 176 176 struct jsm_channel *channel = 177 177 container_of(port, struct jsm_channel, uart_port); 178 178 179 - spin_lock_irqsave(&port->lock, lock_flags); 179 + uart_port_lock_irqsave(port, &lock_flags); 180 180 if (break_state == -1) 181 181 channel->ch_bd->bd_ops->send_break(channel); 182 182 else 183 183 channel->ch_bd->bd_ops->clear_break(channel); 184 184 185 - spin_unlock_irqrestore(&port->lock, lock_flags); 185 + uart_port_unlock_irqrestore(port, lock_flags); 186 186 } 187 187 188 188 static int jsm_tty_open(struct uart_port *port) ··· 241 241 channel->ch_cached_lsr = 0; 242 242 channel->ch_stops_sent = 0; 243 243 244 - spin_lock_irqsave(&port->lock, lock_flags); 244 + uart_port_lock_irqsave(port, &lock_flags); 245 245 termios = &port->state->port.tty->termios; 246 246 channel->ch_c_cflag = termios->c_cflag; 247 247 channel->ch_c_iflag = termios->c_iflag; ··· 261 261 jsm_carrier(channel); 262 262 263 263 channel->ch_open_count++; 264 - spin_unlock_irqrestore(&port->lock, lock_flags); 264 + uart_port_unlock_irqrestore(port, lock_flags); 265 265 266 266 jsm_dbg(OPEN, &channel->ch_bd->pci_dev, "finish\n"); 267 267 return 0; ··· 307 307 struct jsm_channel *channel = 308 308 container_of(port, struct jsm_channel, uart_port); 309 309 310 - spin_lock_irqsave(&port->lock, lock_flags); 310 + uart_port_lock_irqsave(port, &lock_flags); 311 311 channel->ch_c_cflag = termios->c_cflag; 312 312 channel->ch_c_iflag = termios->c_iflag; 313 313 channel->ch_c_oflag = termios->c_oflag; ··· 317 317 318 318 channel->ch_bd->bd_ops->param(channel); 319 319 jsm_carrier(channel); 320 - spin_unlock_irqrestore(&port->lock, lock_flags); 320 + uart_port_unlock_irqrestore(port, lock_flags); 321 321 } 322 322 323 323 static const char *jsm_tty_type(struct uart_port *port)

+10 -10

drivers/tty/serial/liteuart.c

··· 139 139 * if polling, the context would be "in_serving_softirq", so use 140 140 * irq[save|restore] spin_lock variants to cover all possibilities 141 141 */ 142 - spin_lock_irqsave(&port->lock, flags); 142 + uart_port_lock_irqsave(port, &flags); 143 143 isr = litex_read8(port->membase + OFF_EV_PENDING) & uart->irq_reg; 144 144 if (isr & EV_RX) 145 145 liteuart_rx_chars(port); 146 146 if (isr & EV_TX) 147 147 liteuart_tx_chars(port); 148 - spin_unlock_irqrestore(&port->lock, flags); 148 + uart_port_unlock_irqrestore(port, flags); 149 149 150 150 return IRQ_RETVAL(isr); 151 151 } ··· 195 195 } 196 196 } 197 197 198 - spin_lock_irqsave(&port->lock, flags); 198 + uart_port_lock_irqsave(port, &flags); 199 199 /* only enabling rx irqs during startup */ 200 200 liteuart_update_irq_reg(port, true, EV_RX); 201 - spin_unlock_irqrestore(&port->lock, flags); 201 + uart_port_unlock_irqrestore(port, flags); 202 202 203 203 if (!port->irq) { 204 204 timer_setup(&uart->timer, liteuart_timer, 0); ··· 213 213 struct liteuart_port *uart = to_liteuart_port(port); 214 214 unsigned long flags; 215 215 216 - spin_lock_irqsave(&port->lock, flags); 216 + uart_port_lock_irqsave(port, &flags); 217 217 liteuart_update_irq_reg(port, false, EV_RX | EV_TX); 218 - spin_unlock_irqrestore(&port->lock, flags); 218 + uart_port_unlock_irqrestore(port, flags); 219 219 220 220 if (port->irq) 221 221 free_irq(port->irq, port); ··· 229 229 unsigned int baud; 230 230 unsigned long flags; 231 231 232 - spin_lock_irqsave(&port->lock, flags); 232 + uart_port_lock_irqsave(port, &flags); 233 233 234 234 /* update baudrate */ 235 235 baud = uart_get_baud_rate(port, new, old, 0, 460800); 236 236 uart_update_timeout(port, new->c_cflag, baud); 237 237 238 - spin_unlock_irqrestore(&port->lock, flags); 238 + uart_port_unlock_irqrestore(port, flags); 239 239 } 240 240 241 241 static const char *liteuart_type(struct uart_port *port) ··· 382 382 uart = (struct liteuart_port *)xa_load(&liteuart_array, co->index); 383 383 port = &uart->port; 384 384 385 - spin_lock_irqsave(&port->lock, flags); 385 + uart_port_lock_irqsave(port, &flags); 386 386 uart_console_write(port, s, count, liteuart_putchar); 387 - spin_unlock_irqrestore(&port->lock, flags); 387 + uart_port_unlock_irqrestore(port, flags); 388 388 } 389 389 390 390 static int liteuart_console_setup(struct console *co, char *options)

+13 -13

drivers/tty/serial/lpc32xx_hs.c

··· 140 140 if (up->port.sysrq) 141 141 locked = 0; 142 142 else if (oops_in_progress) 143 - locked = spin_trylock(&up->port.lock); 143 + locked = uart_port_trylock(&up->port); 144 144 else 145 - spin_lock(&up->port.lock); 145 + uart_port_lock(&up->port); 146 146 147 147 uart_console_write(&up->port, s, count, lpc32xx_hsuart_console_putchar); 148 148 wait_for_xmit_empty(&up->port); 149 149 150 150 if (locked) 151 - spin_unlock(&up->port.lock); 151 + uart_port_unlock(&up->port); 152 152 local_irq_restore(flags); 153 153 } 154 154 ··· 298 298 struct tty_port *tport = &port->state->port; 299 299 u32 status; 300 300 301 - spin_lock(&port->lock); 301 + uart_port_lock(port); 302 302 303 303 /* Read UART status and clear latched interrupts */ 304 304 status = readl(LPC32XX_HSUART_IIR(port->membase)); ··· 333 333 __serial_lpc32xx_tx(port); 334 334 } 335 335 336 - spin_unlock(&port->lock); 336 + uart_port_unlock(port); 337 337 338 338 return IRQ_HANDLED; 339 339 } ··· 404 404 unsigned long flags; 405 405 u32 tmp; 406 406 407 - spin_lock_irqsave(&port->lock, flags); 407 + uart_port_lock_irqsave(port, &flags); 408 408 tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); 409 409 if (break_state != 0) 410 410 tmp |= LPC32XX_HSU_BREAK; 411 411 else 412 412 tmp &= ~LPC32XX_HSU_BREAK; 413 413 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 414 - spin_unlock_irqrestore(&port->lock, flags); 414 + uart_port_unlock_irqrestore(port, flags); 415 415 } 416 416 417 417 /* port->lock is not held. */ ··· 421 421 unsigned long flags; 422 422 u32 tmp; 423 423 424 - spin_lock_irqsave(&port->lock, flags); 424 + uart_port_lock_irqsave(port, &flags); 425 425 426 426 __serial_uart_flush(port); 427 427 ··· 441 441 442 442 lpc32xx_loopback_set(port->mapbase, 0); /* get out of loopback mode */ 443 443 444 - spin_unlock_irqrestore(&port->lock, flags); 444 + uart_port_unlock_irqrestore(port, flags); 445 445 446 446 retval = request_irq(port->irq, serial_lpc32xx_interrupt, 447 447 0, MODNAME, port); ··· 458 458 u32 tmp; 459 459 unsigned long flags; 460 460 461 - spin_lock_irqsave(&port->lock, flags); 461 + uart_port_lock_irqsave(port, &flags); 462 462 463 463 tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B | 464 464 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B; ··· 466 466 467 467 lpc32xx_loopback_set(port->mapbase, 1); /* go to loopback mode */ 468 468 469 - spin_unlock_irqrestore(&port->lock, flags); 469 + uart_port_unlock_irqrestore(port, flags); 470 470 471 471 free_irq(port->irq, port); 472 472 } ··· 491 491 492 492 quot = __serial_get_clock_div(port->uartclk, baud); 493 493 494 - spin_lock_irqsave(&port->lock, flags); 494 + uart_port_lock_irqsave(port, &flags); 495 495 496 496 /* Ignore characters? */ 497 497 tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); ··· 505 505 506 506 uart_update_timeout(port, termios->c_cflag, baud); 507 507 508 - spin_unlock_irqrestore(&port->lock, flags); 508 + uart_port_unlock_irqrestore(port, flags); 509 509 510 510 /* Don't rewrite B0 */ 511 511 if (tty_termios_baud_rate(termios))

+14 -11

drivers/tty/serial/ma35d1_serial.c

··· 269 269 if (uart_handle_sysrq_char(&up->port, ch)) 270 270 continue; 271 271 272 - spin_lock(&up->port.lock); 272 + uart_port_lock(&up->port); 273 273 uart_insert_char(&up->port, fsr, MA35_FSR_RX_OVER_IF, ch, flag); 274 - spin_unlock(&up->port.lock); 274 + uart_port_unlock(&up->port); 275 275 276 276 fsr = serial_in(up, MA35_FSR_REG); 277 277 } while (!(fsr & MA35_FSR_RX_EMPTY) && (max_count-- > 0)); 278 278 279 - spin_lock(&up->port.lock); 279 + uart_port_lock(&up->port); 280 280 tty_flip_buffer_push(&up->port.state->port); 281 - spin_unlock(&up->port.lock); 281 + uart_port_unlock(&up->port); 282 282 } 283 283 284 284 static irqreturn_t ma35d1serial_interrupt(int irq, void *dev_id) ··· 364 364 unsigned long flags; 365 365 u32 lcr; 366 366 367 - spin_lock_irqsave(&up->port.lock, flags); 367 + uart_port_lock_irqsave(&up->port, &flags); 368 368 lcr = serial_in(up, MA35_LCR_REG); 369 369 if (break_state != 0) 370 370 lcr |= MA35_LCR_BREAK; 371 371 else 372 372 lcr &= ~MA35_LCR_BREAK; 373 373 serial_out(up, MA35_LCR_REG, lcr); 374 - spin_unlock_irqrestore(&up->port.lock, flags); 374 + uart_port_unlock_irqrestore(&up->port, flags); 375 375 } 376 376 377 377 static int ma35d1serial_startup(struct uart_port *port) ··· 441 441 * Ok, we're now changing the port state. Do it with 442 442 * interrupts disabled. 443 443 */ 444 - spin_lock_irqsave(&up->port.lock, flags); 444 + uart_port_lock_irqsave(&up->port, &flags); 445 445 446 446 up->port.read_status_mask = MA35_FSR_RX_OVER_IF; 447 447 if (termios->c_iflag & INPCK) ··· 475 475 476 476 serial_out(up, MA35_LCR_REG, lcr); 477 477 478 - spin_unlock_irqrestore(&up->port.lock, flags); 478 + uart_port_unlock_irqrestore(&up->port, flags); 479 479 } 480 480 481 481 static const char *ma35d1serial_type(struct uart_port *port) ··· 560 560 if (up->port.sysrq) 561 561 locked = 0; 562 562 else if (oops_in_progress) 563 - locked = spin_trylock_irqsave(&up->port.lock, flags); 563 + locked = uart_port_trylock_irqsave(&up->port, &flags); 564 564 else 565 - spin_lock_irqsave(&up->port.lock, flags); 565 + uart_port_lock_irqsave(&up->port, &flags); 566 566 567 567 /* 568 568 * First save the IER then disable the interrupts ··· 576 576 serial_out(up, MA35_IER_REG, ier); 577 577 578 578 if (locked) 579 - spin_unlock_irqrestore(&up->port.lock, flags); 579 + uart_port_unlock_irqrestore(&up->port, flags); 580 580 } 581 581 582 582 static int __init ma35d1serial_console_setup(struct console *co, char *options) ··· 695 695 696 696 up->port.iobase = res_mem->start; 697 697 up->port.membase = ioremap(up->port.iobase, MA35_UART_REG_SIZE); 698 + if (!up->port.membase) 699 + return -ENOMEM; 700 + 698 701 up->port.ops = &ma35d1serial_ops; 699 702 700 703 spin_lock_init(&up->port.lock);

+1 -1

drivers/tty/serial/max310x.c

··· 402 402 ret = s->if_cfg->extended_reg_enable(dev, true); 403 403 if (ret) 404 404 return ret; 405 - 405 + 406 406 regmap_read(s->regmap, s->if_cfg->rev_id_reg, &val); 407 407 s->if_cfg->extended_reg_enable(dev, false); 408 408 if (((val & MAX310x_REV_MASK) != MAX14830_REV_ID)) {

+10 -10

drivers/tty/serial/mcf.c

··· 135 135 { 136 136 unsigned long flags; 137 137 138 - spin_lock_irqsave(&port->lock, flags); 138 + uart_port_lock_irqsave(port, &flags); 139 139 if (break_state == -1) 140 140 writeb(MCFUART_UCR_CMDBREAKSTART, port->membase + MCFUART_UCR); 141 141 else 142 142 writeb(MCFUART_UCR_CMDBREAKSTOP, port->membase + MCFUART_UCR); 143 - spin_unlock_irqrestore(&port->lock, flags); 143 + uart_port_unlock_irqrestore(port, flags); 144 144 } 145 145 146 146 /****************************************************************************/ ··· 150 150 struct mcf_uart *pp = container_of(port, struct mcf_uart, port); 151 151 unsigned long flags; 152 152 153 - spin_lock_irqsave(&port->lock, flags); 153 + uart_port_lock_irqsave(port, &flags); 154 154 155 155 /* Reset UART, get it into known state... */ 156 156 writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR); ··· 164 164 pp->imr = MCFUART_UIR_RXREADY; 165 165 writeb(pp->imr, port->membase + MCFUART_UIMR); 166 166 167 - spin_unlock_irqrestore(&port->lock, flags); 167 + uart_port_unlock_irqrestore(port, flags); 168 168 169 169 return 0; 170 170 } ··· 176 176 struct mcf_uart *pp = container_of(port, struct mcf_uart, port); 177 177 unsigned long flags; 178 178 179 - spin_lock_irqsave(&port->lock, flags); 179 + uart_port_lock_irqsave(port, &flags); 180 180 181 181 /* Disable all interrupts now */ 182 182 pp->imr = 0; ··· 186 186 writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR); 187 187 writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR); 188 188 189 - spin_unlock_irqrestore(&port->lock, flags); 189 + uart_port_unlock_irqrestore(port, flags); 190 190 } 191 191 192 192 /****************************************************************************/ ··· 252 252 mr2 |= MCFUART_MR2_TXCTS; 253 253 } 254 254 255 - spin_lock_irqsave(&port->lock, flags); 255 + uart_port_lock_irqsave(port, &flags); 256 256 if (port->rs485.flags & SER_RS485_ENABLED) { 257 257 dev_dbg(port->dev, "Setting UART to RS485\n"); 258 258 mr2 |= MCFUART_MR2_TXRTS; ··· 273 273 port->membase + MCFUART_UCSR); 274 274 writeb(MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE, 275 275 port->membase + MCFUART_UCR); 276 - spin_unlock_irqrestore(&port->lock, flags); 276 + uart_port_unlock_irqrestore(port, flags); 277 277 } 278 278 279 279 /****************************************************************************/ ··· 350 350 351 351 isr = readb(port->membase + MCFUART_UISR) & pp->imr; 352 352 353 - spin_lock(&port->lock); 353 + uart_port_lock(port); 354 354 if (isr & MCFUART_UIR_RXREADY) { 355 355 mcf_rx_chars(pp); 356 356 ret = IRQ_HANDLED; ··· 359 359 mcf_tx_chars(pp); 360 360 ret = IRQ_HANDLED; 361 361 } 362 - spin_unlock(&port->lock); 362 + uart_port_unlock(port); 363 363 364 364 return ret; 365 365 }

+4 -4

drivers/tty/serial/men_z135_uart.c

··· 392 392 if (!irq_id) 393 393 goto out; 394 394 395 - spin_lock(&port->lock); 395 + uart_port_lock(port); 396 396 /* It's save to write to IIR[7:6] RXC[9:8] */ 397 397 iowrite8(irq_id, port->membase + MEN_Z135_STAT_REG); 398 398 ··· 418 418 handled = true; 419 419 } 420 420 421 - spin_unlock(&port->lock); 421 + uart_port_unlock(port); 422 422 out: 423 423 return IRQ_RETVAL(handled); 424 424 } ··· 708 708 709 709 baud = uart_get_baud_rate(port, termios, old, 0, uart_freq / 16); 710 710 711 - spin_lock_irq(&port->lock); 711 + uart_port_lock_irq(port); 712 712 if (tty_termios_baud_rate(termios)) 713 713 tty_termios_encode_baud_rate(termios, baud, baud); 714 714 ··· 716 716 iowrite32(bd_reg, port->membase + MEN_Z135_BAUD_REG); 717 717 718 718 uart_update_timeout(port, termios->c_cflag, baud); 719 - spin_unlock_irq(&port->lock); 719 + uart_port_unlock_irq(port); 720 720 } 721 721 722 722 static const char *men_z135_type(struct uart_port *port)

+28 -20

drivers/tty/serial/meson_uart.c

··· 129 129 130 130 free_irq(port->irq, port); 131 131 132 - spin_lock_irqsave(&port->lock, flags); 132 + uart_port_lock_irqsave(port, &flags); 133 133 134 134 val = readl(port->membase + AML_UART_CONTROL); 135 135 val &= ~AML_UART_RX_EN; 136 136 val &= ~(AML_UART_RX_INT_EN | AML_UART_TX_INT_EN); 137 137 writel(val, port->membase + AML_UART_CONTROL); 138 138 139 - spin_unlock_irqrestore(&port->lock, flags); 139 + uart_port_unlock_irqrestore(port, flags); 140 140 } 141 141 142 142 static void meson_uart_start_tx(struct uart_port *port) ··· 238 238 { 239 239 struct uart_port *port = (struct uart_port *)dev_id; 240 240 241 - spin_lock(&port->lock); 241 + uart_port_lock(port); 242 242 243 243 if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY)) 244 244 meson_receive_chars(port); ··· 248 248 meson_uart_start_tx(port); 249 249 } 250 250 251 - spin_unlock(&port->lock); 251 + uart_port_unlock(port); 252 252 253 253 return IRQ_HANDLED; 254 254 } ··· 284 284 u32 val; 285 285 int ret = 0; 286 286 287 - spin_lock_irqsave(&port->lock, flags); 287 + uart_port_lock_irqsave(port, &flags); 288 288 289 289 val = readl(port->membase + AML_UART_CONTROL); 290 290 val |= AML_UART_CLEAR_ERR; ··· 301 301 val = (AML_UART_RECV_IRQ(1) | AML_UART_XMIT_IRQ(port->fifosize / 2)); 302 302 writel(val, port->membase + AML_UART_MISC); 303 303 304 - spin_unlock_irqrestore(&port->lock, flags); 304 + uart_port_unlock_irqrestore(port, flags); 305 305 306 306 ret = request_irq(port->irq, meson_uart_interrupt, 0, 307 307 port->name, port); ··· 341 341 unsigned long flags; 342 342 u32 val; 343 343 344 - spin_lock_irqsave(&port->lock, flags); 344 + uart_port_lock_irqsave(port, &flags); 345 345 346 346 cflags = termios->c_cflag; 347 347 iflags = termios->c_iflag; ··· 380 380 else 381 381 val |= AML_UART_STOP_BIT_1SB; 382 382 383 - if (cflags & CRTSCTS) 384 - val &= ~AML_UART_TWO_WIRE_EN; 385 - else 383 + if (cflags & CRTSCTS) { 384 + if (port->flags & UPF_HARD_FLOW) 385 + val &= ~AML_UART_TWO_WIRE_EN; 386 + else 387 + termios->c_cflag &= ~CRTSCTS; 388 + } else { 386 389 val |= AML_UART_TWO_WIRE_EN; 390 + } 387 391 388 392 writel(val, port->membase + AML_UART_CONTROL); 389 393 ··· 405 401 AML_UART_FRAME_ERR; 406 402 407 403 uart_update_timeout(port, termios->c_cflag, baud); 408 - spin_unlock_irqrestore(&port->lock, flags); 404 + uart_port_unlock_irqrestore(port, flags); 409 405 } 410 406 411 407 static int meson_uart_verify_port(struct uart_port *port, ··· 464 460 u32 c; 465 461 unsigned long flags; 466 462 467 - spin_lock_irqsave(&port->lock, flags); 463 + uart_port_lock_irqsave(port, &flags); 468 464 469 465 if (readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY) 470 466 c = NO_POLL_CHAR; 471 467 else 472 468 c = readl(port->membase + AML_UART_RFIFO); 473 469 474 - spin_unlock_irqrestore(&port->lock, flags); 470 + uart_port_unlock_irqrestore(port, flags); 475 471 476 472 return c; 477 473 } ··· 482 478 u32 reg; 483 479 int ret; 484 480 485 - spin_lock_irqsave(&port->lock, flags); 481 + uart_port_lock_irqsave(port, &flags); 486 482 487 483 /* Wait until FIFO is empty or timeout */ 488 484 ret = readl_poll_timeout_atomic(port->membase + AML_UART_STATUS, reg, ··· 506 502 dev_err(port->dev, "Timeout waiting for UART TX EMPTY\n"); 507 503 508 504 out: 509 - spin_unlock_irqrestore(&port->lock, flags); 505 + uart_port_unlock_irqrestore(port, flags); 510 506 } 511 507 512 508 #endif /* CONFIG_CONSOLE_POLL */ ··· 563 559 if (port->sysrq) { 564 560 locked = 0; 565 561 } else if (oops_in_progress) { 566 - locked = spin_trylock(&port->lock); 562 + locked = uart_port_trylock(port); 567 563 } else { 568 - spin_lock(&port->lock); 564 + uart_port_lock(port); 569 565 locked = 1; 570 566 } 571 567 ··· 577 573 writel(val, port->membase + AML_UART_CONTROL); 578 574 579 575 if (locked) 580 - spin_unlock(&port->lock); 576 + uart_port_unlock(port); 581 577 local_irq_restore(flags); 582 578 } 583 579 ··· 650 646 return 0; 651 647 } 652 648 653 - OF_EARLYCON_DECLARE(meson, "amlogic,meson-ao-uart", 654 - meson_serial_early_console_setup); 649 + OF_EARLYCON_DECLARE(meson, "amlogic,meson-ao-uart", meson_serial_early_console_setup); 650 + OF_EARLYCON_DECLARE(meson, "amlogic,meson-s4-uart", meson_serial_early_console_setup); 655 651 656 652 #define MESON_SERIAL_CONSOLE_PTR(_devname) (&meson_serial_console_##_devname) 657 653 #else ··· 709 705 u32 fifosize = 64; /* Default is 64, 128 for EE UART_0 */ 710 706 int ret = 0; 711 707 int irq; 708 + bool has_rtscts; 712 709 713 710 if (pdev->dev.of_node) 714 711 pdev->id = of_alias_get_id(pdev->dev.of_node, "serial"); ··· 737 732 return irq; 738 733 739 734 of_property_read_u32(pdev->dev.of_node, "fifo-size", &fifosize); 735 + has_rtscts = of_property_read_bool(pdev->dev.of_node, "uart-has-rtscts"); 740 736 741 737 if (meson_ports[pdev->id]) { 742 738 return dev_err_probe(&pdev->dev, -EBUSY, ··· 768 762 port->mapsize = resource_size(res_mem); 769 763 port->irq = irq; 770 764 port->flags = UPF_BOOT_AUTOCONF | UPF_LOW_LATENCY; 765 + if (has_rtscts) 766 + port->flags |= UPF_HARD_FLOW; 771 767 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_MESON_CONSOLE); 772 768 port->dev = &pdev->dev; 773 769 port->line = pdev->id;

+8 -8

drivers/tty/serial/milbeaut_usio.c

··· 207 207 { 208 208 struct uart_port *port = dev_id; 209 209 210 - spin_lock(&port->lock); 210 + uart_port_lock(port); 211 211 mlb_usio_rx_chars(port); 212 - spin_unlock(&port->lock); 212 + uart_port_unlock(port); 213 213 214 214 return IRQ_HANDLED; 215 215 } ··· 218 218 { 219 219 struct uart_port *port = dev_id; 220 220 221 - spin_lock(&port->lock); 221 + uart_port_lock(port); 222 222 if (readb(port->membase + MLB_USIO_REG_SSR) & MLB_USIO_SSR_TBI) 223 223 mlb_usio_tx_chars(port); 224 - spin_unlock(&port->lock); 224 + uart_port_unlock(port); 225 225 226 226 return IRQ_HANDLED; 227 227 } ··· 267 267 escr = readb(port->membase + MLB_USIO_REG_ESCR); 268 268 if (of_property_read_bool(port->dev->of_node, "auto-flow-control")) 269 269 escr |= MLB_USIO_ESCR_FLWEN; 270 - spin_lock_irqsave(&port->lock, flags); 270 + uart_port_lock_irqsave(port, &flags); 271 271 writeb(0, port->membase + MLB_USIO_REG_SCR); 272 272 writeb(escr, port->membase + MLB_USIO_REG_ESCR); 273 273 writeb(MLB_USIO_SCR_UPCL, port->membase + MLB_USIO_REG_SCR); ··· 282 282 283 283 writeb(MLB_USIO_SCR_TXE | MLB_USIO_SCR_RIE | MLB_USIO_SCR_TBIE | 284 284 MLB_USIO_SCR_RXE, port->membase + MLB_USIO_REG_SCR); 285 - spin_unlock_irqrestore(&port->lock, flags); 285 + uart_port_unlock_irqrestore(port, flags); 286 286 287 287 return 0; 288 288 } ··· 337 337 else 338 338 quot = 0; 339 339 340 - spin_lock_irqsave(&port->lock, flags); 340 + uart_port_lock_irqsave(port, &flags); 341 341 uart_update_timeout(port, termios->c_cflag, baud); 342 342 port->read_status_mask = MLB_USIO_SSR_ORE | MLB_USIO_SSR_RDRF | 343 343 MLB_USIO_SSR_TDRE; ··· 367 367 writew(BIT(12), port->membase + MLB_USIO_REG_FBYTE); 368 368 writeb(MLB_USIO_SCR_RIE | MLB_USIO_SCR_RXE | MLB_USIO_SCR_TBIE | 369 369 MLB_USIO_SCR_TXE, port->membase + MLB_USIO_REG_SCR); 370 - spin_unlock_irqrestore(&port->lock, flags); 370 + uart_port_unlock_irqrestore(port, flags); 371 371 } 372 372 373 373 static const char *mlb_usio_type(struct uart_port *port)

+6 -6

drivers/tty/serial/mpc52xx_uart.c

··· 1096 1096 mpc52xx_uart_break_ctl(struct uart_port *port, int ctl) 1097 1097 { 1098 1098 unsigned long flags; 1099 - spin_lock_irqsave(&port->lock, flags); 1099 + uart_port_lock_irqsave(port, &flags); 1100 1100 1101 1101 if (ctl == -1) 1102 1102 psc_ops->command(port, MPC52xx_PSC_START_BRK); 1103 1103 else 1104 1104 psc_ops->command(port, MPC52xx_PSC_STOP_BRK); 1105 1105 1106 - spin_unlock_irqrestore(&port->lock, flags); 1106 + uart_port_unlock_irqrestore(port, flags); 1107 1107 } 1108 1108 1109 1109 static int ··· 1214 1214 } 1215 1215 1216 1216 /* Get the lock */ 1217 - spin_lock_irqsave(&port->lock, flags); 1217 + uart_port_lock_irqsave(port, &flags); 1218 1218 1219 1219 /* Do our best to flush TX & RX, so we don't lose anything */ 1220 1220 /* But we don't wait indefinitely ! */ ··· 1250 1250 psc_ops->command(port, MPC52xx_PSC_RX_ENABLE); 1251 1251 1252 1252 /* We're all set, release the lock */ 1253 - spin_unlock_irqrestore(&port->lock, flags); 1253 + uart_port_unlock_irqrestore(port, flags); 1254 1254 } 1255 1255 1256 1256 static const char * ··· 1477 1477 struct uart_port *port = dev_id; 1478 1478 irqreturn_t ret; 1479 1479 1480 - spin_lock(&port->lock); 1480 + uart_port_lock(port); 1481 1481 1482 1482 ret = psc_ops->handle_irq(port); 1483 1483 1484 - spin_unlock(&port->lock); 1484 + uart_port_unlock(port); 1485 1485 1486 1486 return ret; 1487 1487 }

+8 -8

drivers/tty/serial/mps2-uart.c

··· 188 188 if (unlikely(!(irqflag & UARTn_INT_RX))) 189 189 return IRQ_NONE; 190 190 191 - spin_lock(&port->lock); 191 + uart_port_lock(port); 192 192 193 193 mps2_uart_write8(port, UARTn_INT_RX, UARTn_INT); 194 194 mps2_uart_rx_chars(port); 195 195 196 - spin_unlock(&port->lock); 196 + uart_port_unlock(port); 197 197 198 198 return IRQ_HANDLED; 199 199 } ··· 206 206 if (unlikely(!(irqflag & UARTn_INT_TX))) 207 207 return IRQ_NONE; 208 208 209 - spin_lock(&port->lock); 209 + uart_port_lock(port); 210 210 211 211 mps2_uart_write8(port, UARTn_INT_TX, UARTn_INT); 212 212 mps2_uart_tx_chars(port); 213 213 214 - spin_unlock(&port->lock); 214 + uart_port_unlock(port); 215 215 216 216 return IRQ_HANDLED; 217 217 } ··· 222 222 struct uart_port *port = data; 223 223 u8 irqflag = mps2_uart_read8(port, UARTn_INT); 224 224 225 - spin_lock(&port->lock); 225 + uart_port_lock(port); 226 226 227 227 if (irqflag & UARTn_INT_RX_OVERRUN) { 228 228 struct tty_port *tport = &port->state->port; ··· 244 244 handled = IRQ_HANDLED; 245 245 } 246 246 247 - spin_unlock(&port->lock); 247 + uart_port_unlock(port); 248 248 249 249 return handled; 250 250 } ··· 356 356 357 357 bauddiv = DIV_ROUND_CLOSEST(port->uartclk, baud); 358 358 359 - spin_lock_irqsave(&port->lock, flags); 359 + uart_port_lock_irqsave(port, &flags); 360 360 361 361 uart_update_timeout(port, termios->c_cflag, baud); 362 362 mps2_uart_write32(port, bauddiv, UARTn_BAUDDIV); 363 363 364 - spin_unlock_irqrestore(&port->lock, flags); 364 + uart_port_unlock_irqrestore(port, flags); 365 365 366 366 if (tty_termios_baud_rate(termios)) 367 367 tty_termios_encode_baud_rate(termios, baud, baud);

+19 -19

drivers/tty/serial/msm_serial.c

··· 444 444 unsigned int count; 445 445 u32 val; 446 446 447 - spin_lock_irqsave(&port->lock, flags); 447 + uart_port_lock_irqsave(port, &flags); 448 448 449 449 /* Already stopped */ 450 450 if (!dma->count) ··· 476 476 477 477 msm_handle_tx(port); 478 478 done: 479 - spin_unlock_irqrestore(&port->lock, flags); 479 + uart_port_unlock_irqrestore(port, flags); 480 480 } 481 481 482 482 static int msm_handle_tx_dma(struct msm_port *msm_port, unsigned int count) ··· 549 549 unsigned long flags; 550 550 u32 val; 551 551 552 - spin_lock_irqsave(&port->lock, flags); 552 + uart_port_lock_irqsave(port, &flags); 553 553 554 554 /* Already stopped */ 555 555 if (!dma->count) ··· 587 587 if (!(port->read_status_mask & MSM_UART_SR_RX_BREAK)) 588 588 flag = TTY_NORMAL; 589 589 590 - spin_unlock_irqrestore(&port->lock, flags); 590 + uart_port_unlock_irqrestore(port, flags); 591 591 sysrq = uart_handle_sysrq_char(port, dma->virt[i]); 592 - spin_lock_irqsave(&port->lock, flags); 592 + uart_port_lock_irqsave(port, &flags); 593 593 if (!sysrq) 594 594 tty_insert_flip_char(tport, dma->virt[i], flag); 595 595 } 596 596 597 597 msm_start_rx_dma(msm_port); 598 598 done: 599 - spin_unlock_irqrestore(&port->lock, flags); 599 + uart_port_unlock_irqrestore(port, flags); 600 600 601 601 if (count) 602 602 tty_flip_buffer_push(tport); ··· 762 762 if (!(port->read_status_mask & MSM_UART_SR_RX_BREAK)) 763 763 flag = TTY_NORMAL; 764 764 765 - spin_unlock(&port->lock); 765 + uart_port_unlock(port); 766 766 sysrq = uart_handle_sysrq_char(port, buf[i]); 767 - spin_lock(&port->lock); 767 + uart_port_lock(port); 768 768 if (!sysrq) 769 769 tty_insert_flip_char(tport, buf[i], flag); 770 770 } ··· 824 824 else if (sr & MSM_UART_SR_PAR_FRAME_ERR) 825 825 flag = TTY_FRAME; 826 826 827 - spin_unlock(&port->lock); 827 + uart_port_unlock(port); 828 828 sysrq = uart_handle_sysrq_char(port, c); 829 - spin_lock(&port->lock); 829 + uart_port_lock(port); 830 830 if (!sysrq) 831 831 tty_insert_flip_char(tport, c, flag); 832 832 } ··· 951 951 unsigned int misr; 952 952 u32 val; 953 953 954 - spin_lock_irqsave(&port->lock, flags); 954 + uart_port_lock_irqsave(port, &flags); 955 955 misr = msm_read(port, MSM_UART_MISR); 956 956 msm_write(port, 0, MSM_UART_IMR); /* disable interrupt */ 957 957 ··· 983 983 msm_handle_delta_cts(port); 984 984 985 985 msm_write(port, msm_port->imr, MSM_UART_IMR); /* restore interrupt */ 986 - spin_unlock_irqrestore(&port->lock, flags); 986 + uart_port_unlock_irqrestore(port, flags); 987 987 988 988 return IRQ_HANDLED; 989 989 } ··· 1128 1128 unsigned long flags, rate; 1129 1129 1130 1130 flags = *saved_flags; 1131 - spin_unlock_irqrestore(&port->lock, flags); 1131 + uart_port_unlock_irqrestore(port, flags); 1132 1132 1133 1133 entry = msm_find_best_baud(port, baud, &rate); 1134 1134 clk_set_rate(msm_port->clk, rate); 1135 1135 baud = rate / 16 / entry->divisor; 1136 1136 1137 - spin_lock_irqsave(&port->lock, flags); 1137 + uart_port_lock_irqsave(port, &flags); 1138 1138 *saved_flags = flags; 1139 1139 port->uartclk = rate; 1140 1140 ··· 1266 1266 unsigned long flags; 1267 1267 unsigned int baud, mr; 1268 1268 1269 - spin_lock_irqsave(&port->lock, flags); 1269 + uart_port_lock_irqsave(port, &flags); 1270 1270 1271 1271 if (dma->chan) /* Terminate if any */ 1272 1272 msm_stop_dma(port, dma); ··· 1338 1338 /* Try to use DMA */ 1339 1339 msm_start_rx_dma(msm_port); 1340 1340 1341 - spin_unlock_irqrestore(&port->lock, flags); 1341 + uart_port_unlock_irqrestore(port, flags); 1342 1342 } 1343 1343 1344 1344 static const char *msm_type(struct uart_port *port) ··· 1620 1620 if (port->sysrq) 1621 1621 locked = 0; 1622 1622 else if (oops_in_progress) 1623 - locked = spin_trylock(&port->lock); 1623 + locked = uart_port_trylock(port); 1624 1624 else 1625 - spin_lock(&port->lock); 1625 + uart_port_lock(port); 1626 1626 1627 1627 if (is_uartdm) 1628 1628 msm_reset_dm_count(port, count); ··· 1661 1661 } 1662 1662 1663 1663 if (locked) 1664 - spin_unlock(&port->lock); 1664 + uart_port_unlock(port); 1665 1665 1666 1666 local_irq_restore(flags); 1667 1667 }

+9 -9

drivers/tty/serial/mvebu-uart.c

··· 187 187 unsigned long flags; 188 188 unsigned int st; 189 189 190 - spin_lock_irqsave(&port->lock, flags); 190 + uart_port_lock_irqsave(port, &flags); 191 191 st = readl(port->membase + UART_STAT); 192 - spin_unlock_irqrestore(&port->lock, flags); 192 + uart_port_unlock_irqrestore(port, flags); 193 193 194 194 return (st & STAT_TX_EMP) ? TIOCSER_TEMT : 0; 195 195 } ··· 249 249 unsigned int ctl; 250 250 unsigned long flags; 251 251 252 - spin_lock_irqsave(&port->lock, flags); 252 + uart_port_lock_irqsave(port, &flags); 253 253 ctl = readl(port->membase + UART_CTRL(port)); 254 254 if (brk == -1) 255 255 ctl |= CTRL_SND_BRK_SEQ; 256 256 else 257 257 ctl &= ~CTRL_SND_BRK_SEQ; 258 258 writel(ctl, port->membase + UART_CTRL(port)); 259 - spin_unlock_irqrestore(&port->lock, flags); 259 + uart_port_unlock_irqrestore(port, flags); 260 260 } 261 261 262 262 static void mvebu_uart_rx_chars(struct uart_port *port, unsigned int status) ··· 540 540 unsigned long flags; 541 541 unsigned int baud, min_baud, max_baud; 542 542 543 - spin_lock_irqsave(&port->lock, flags); 543 + uart_port_lock_irqsave(port, &flags); 544 544 545 545 port->read_status_mask = STAT_RX_RDY(port) | STAT_OVR_ERR | 546 546 STAT_TX_RDY(port) | STAT_TX_FIFO_FUL; ··· 589 589 uart_update_timeout(port, termios->c_cflag, baud); 590 590 } 591 591 592 - spin_unlock_irqrestore(&port->lock, flags); 592 + uart_port_unlock_irqrestore(port, flags); 593 593 } 594 594 595 595 static const char *mvebu_uart_type(struct uart_port *port) ··· 735 735 int locked = 1; 736 736 737 737 if (oops_in_progress) 738 - locked = spin_trylock_irqsave(&port->lock, flags); 738 + locked = uart_port_trylock_irqsave(port, &flags); 739 739 else 740 - spin_lock_irqsave(&port->lock, flags); 740 + uart_port_lock_irqsave(port, &flags); 741 741 742 742 ier = readl(port->membase + UART_CTRL(port)) & CTRL_BRK_INT; 743 743 intr = readl(port->membase + UART_INTR(port)) & ··· 758 758 } 759 759 760 760 if (locked) 761 - spin_unlock_irqrestore(&port->lock, flags); 761 + uart_port_unlock_irqrestore(port, flags); 762 762 } 763 763 764 764 static int mvebu_uart_console_setup(struct console *co, char *options)

+19 -19

drivers/tty/serial/omap-serial.c

··· 390 390 struct uart_omap_port *up = to_uart_omap_port(port); 391 391 unsigned long flags; 392 392 393 - spin_lock_irqsave(&up->port.lock, flags); 393 + uart_port_lock_irqsave(&up->port, &flags); 394 394 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 395 395 serial_out(up, UART_IER, up->ier); 396 - spin_unlock_irqrestore(&up->port.lock, flags); 396 + uart_port_unlock_irqrestore(&up->port, flags); 397 397 } 398 398 399 399 static void serial_omap_unthrottle(struct uart_port *port) ··· 401 401 struct uart_omap_port *up = to_uart_omap_port(port); 402 402 unsigned long flags; 403 403 404 - spin_lock_irqsave(&up->port.lock, flags); 404 + uart_port_lock_irqsave(&up->port, &flags); 405 405 up->ier |= UART_IER_RLSI | UART_IER_RDI; 406 406 serial_out(up, UART_IER, up->ier); 407 - spin_unlock_irqrestore(&up->port.lock, flags); 407 + uart_port_unlock_irqrestore(&up->port, flags); 408 408 } 409 409 410 410 static unsigned int check_modem_status(struct uart_omap_port *up) ··· 527 527 irqreturn_t ret = IRQ_NONE; 528 528 int max_count = 256; 529 529 530 - spin_lock(&up->port.lock); 530 + uart_port_lock(&up->port); 531 531 532 532 do { 533 533 iir = serial_in(up, UART_IIR); ··· 563 563 } 564 564 } while (max_count--); 565 565 566 - spin_unlock(&up->port.lock); 566 + uart_port_unlock(&up->port); 567 567 568 568 tty_flip_buffer_push(&up->port.state->port); 569 569 ··· 579 579 unsigned int ret = 0; 580 580 581 581 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line); 582 - spin_lock_irqsave(&up->port.lock, flags); 582 + uart_port_lock_irqsave(&up->port, &flags); 583 583 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; 584 - spin_unlock_irqrestore(&up->port.lock, flags); 584 + uart_port_unlock_irqrestore(&up->port, flags); 585 585 586 586 return ret; 587 587 } ··· 647 647 unsigned long flags; 648 648 649 649 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line); 650 - spin_lock_irqsave(&up->port.lock, flags); 650 + uart_port_lock_irqsave(&up->port, &flags); 651 651 if (break_state == -1) 652 652 up->lcr |= UART_LCR_SBC; 653 653 else 654 654 up->lcr &= ~UART_LCR_SBC; 655 655 serial_out(up, UART_LCR, up->lcr); 656 - spin_unlock_irqrestore(&up->port.lock, flags); 656 + uart_port_unlock_irqrestore(&up->port, flags); 657 657 } 658 658 659 659 static int serial_omap_startup(struct uart_port *port) ··· 701 701 * Now, initialize the UART 702 702 */ 703 703 serial_out(up, UART_LCR, UART_LCR_WLEN8); 704 - spin_lock_irqsave(&up->port.lock, flags); 704 + uart_port_lock_irqsave(&up->port, &flags); 705 705 /* 706 706 * Most PC uarts need OUT2 raised to enable interrupts. 707 707 */ 708 708 up->port.mctrl |= TIOCM_OUT2; 709 709 serial_omap_set_mctrl(&up->port, up->port.mctrl); 710 - spin_unlock_irqrestore(&up->port.lock, flags); 710 + uart_port_unlock_irqrestore(&up->port, flags); 711 711 712 712 up->msr_saved_flags = 0; 713 713 /* ··· 742 742 up->ier = 0; 743 743 serial_out(up, UART_IER, 0); 744 744 745 - spin_lock_irqsave(&up->port.lock, flags); 745 + uart_port_lock_irqsave(&up->port, &flags); 746 746 up->port.mctrl &= ~TIOCM_OUT2; 747 747 serial_omap_set_mctrl(&up->port, up->port.mctrl); 748 - spin_unlock_irqrestore(&up->port.lock, flags); 748 + uart_port_unlock_irqrestore(&up->port, flags); 749 749 750 750 /* 751 751 * Disable break condition and FIFOs ··· 815 815 * Ok, we're now changing the port state. Do it with 816 816 * interrupts disabled. 817 817 */ 818 - spin_lock_irqsave(&up->port.lock, flags); 818 + uart_port_lock_irqsave(&up->port, &flags); 819 819 820 820 /* 821 821 * Update the per-port timeout. ··· 1013 1013 1014 1014 serial_omap_set_mctrl(&up->port, up->port.mctrl); 1015 1015 1016 - spin_unlock_irqrestore(&up->port.lock, flags); 1016 + uart_port_unlock_irqrestore(&up->port, flags); 1017 1017 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line); 1018 1018 } 1019 1019 ··· 1216 1216 if (up->port.sysrq) 1217 1217 locked = 0; 1218 1218 else if (oops_in_progress) 1219 - locked = spin_trylock(&up->port.lock); 1219 + locked = uart_port_trylock(&up->port); 1220 1220 else 1221 - spin_lock(&up->port.lock); 1221 + uart_port_lock(&up->port); 1222 1222 1223 1223 /* 1224 1224 * First save the IER then disable the interrupts ··· 1245 1245 check_modem_status(up); 1246 1246 1247 1247 if (locked) 1248 - spin_unlock(&up->port.lock); 1248 + uart_port_unlock(&up->port); 1249 1249 local_irq_restore(flags); 1250 1250 } 1251 1251

+13 -13

drivers/tty/serial/owl-uart.c

··· 125 125 u32 val; 126 126 unsigned int ret; 127 127 128 - spin_lock_irqsave(&port->lock, flags); 128 + uart_port_lock_irqsave(port, &flags); 129 129 130 130 val = owl_uart_read(port, OWL_UART_STAT); 131 131 ret = (val & OWL_UART_STAT_TFES) ? TIOCSER_TEMT : 0; 132 132 133 - spin_unlock_irqrestore(&port->lock, flags); 133 + uart_port_unlock_irqrestore(port, flags); 134 134 135 135 return ret; 136 136 } ··· 232 232 unsigned long flags; 233 233 u32 stat; 234 234 235 - spin_lock_irqsave(&port->lock, flags); 235 + uart_port_lock_irqsave(port, &flags); 236 236 237 237 stat = owl_uart_read(port, OWL_UART_STAT); 238 238 ··· 246 246 stat |= OWL_UART_STAT_RIP | OWL_UART_STAT_TIP; 247 247 owl_uart_write(port, stat, OWL_UART_STAT); 248 248 249 - spin_unlock_irqrestore(&port->lock, flags); 249 + uart_port_unlock_irqrestore(port, flags); 250 250 251 251 return IRQ_HANDLED; 252 252 } ··· 256 256 u32 val; 257 257 unsigned long flags; 258 258 259 - spin_lock_irqsave(&port->lock, flags); 259 + uart_port_lock_irqsave(port, &flags); 260 260 261 261 val = owl_uart_read(port, OWL_UART_CTL); 262 262 val &= ~(OWL_UART_CTL_TXIE | OWL_UART_CTL_RXIE 263 263 | OWL_UART_CTL_TXDE | OWL_UART_CTL_RXDE | OWL_UART_CTL_EN); 264 264 owl_uart_write(port, val, OWL_UART_CTL); 265 265 266 - spin_unlock_irqrestore(&port->lock, flags); 266 + uart_port_unlock_irqrestore(port, flags); 267 267 268 268 free_irq(port->irq, port); 269 269 } ··· 279 279 if (ret) 280 280 return ret; 281 281 282 - spin_lock_irqsave(&port->lock, flags); 282 + uart_port_lock_irqsave(port, &flags); 283 283 284 284 val = owl_uart_read(port, OWL_UART_STAT); 285 285 val |= OWL_UART_STAT_RIP | OWL_UART_STAT_TIP ··· 291 291 val |= OWL_UART_CTL_EN; 292 292 owl_uart_write(port, val, OWL_UART_CTL); 293 293 294 - spin_unlock_irqrestore(&port->lock, flags); 294 + uart_port_unlock_irqrestore(port, flags); 295 295 296 296 return 0; 297 297 } ··· 311 311 u32 ctl; 312 312 unsigned long flags; 313 313 314 - spin_lock_irqsave(&port->lock, flags); 314 + uart_port_lock_irqsave(port, &flags); 315 315 316 316 ctl = owl_uart_read(port, OWL_UART_CTL); 317 317 ··· 371 371 372 372 uart_update_timeout(port, termios->c_cflag, baud); 373 373 374 - spin_unlock_irqrestore(&port->lock, flags); 374 + uart_port_unlock_irqrestore(port, flags); 375 375 } 376 376 377 377 static void owl_uart_release_port(struct uart_port *port) ··· 515 515 if (port->sysrq) 516 516 locked = 0; 517 517 else if (oops_in_progress) 518 - locked = spin_trylock(&port->lock); 518 + locked = uart_port_trylock(port); 519 519 else { 520 - spin_lock(&port->lock); 520 + uart_port_lock(port); 521 521 locked = 1; 522 522 } 523 523 ··· 541 541 owl_uart_write(port, old_ctl, OWL_UART_CTL); 542 542 543 543 if (locked) 544 - spin_unlock(&port->lock); 544 + uart_port_unlock(port); 545 545 546 546 local_irq_restore(flags); 547 547 }

+5 -5

drivers/tty/serial/pch_uart.c

··· 1347 1347 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); 1348 1348 1349 1349 spin_lock_irqsave(&priv->lock, flags); 1350 - spin_lock(&port->lock); 1350 + uart_port_lock(port); 1351 1351 1352 1352 uart_update_timeout(port, termios->c_cflag, baud); 1353 1353 rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb); ··· 1360 1360 tty_termios_encode_baud_rate(termios, baud, baud); 1361 1361 1362 1362 out: 1363 - spin_unlock(&port->lock); 1363 + uart_port_unlock(port); 1364 1364 spin_unlock_irqrestore(&priv->lock, flags); 1365 1365 } 1366 1366 ··· 1581 1581 port_locked = 0; 1582 1582 } else if (oops_in_progress) { 1583 1583 priv_locked = spin_trylock(&priv->lock); 1584 - port_locked = spin_trylock(&priv->port.lock); 1584 + port_locked = uart_port_trylock(&priv->port); 1585 1585 } else { 1586 1586 spin_lock(&priv->lock); 1587 - spin_lock(&priv->port.lock); 1587 + uart_port_lock(&priv->port); 1588 1588 } 1589 1589 1590 1590 /* ··· 1604 1604 iowrite8(ier, priv->membase + UART_IER); 1605 1605 1606 1606 if (port_locked) 1607 - spin_unlock(&priv->port.lock); 1607 + uart_port_unlock(&priv->port); 1608 1608 if (priv_locked) 1609 1609 spin_unlock(&priv->lock); 1610 1610 local_irq_restore(flags);

+10 -10

drivers/tty/serial/pic32_uart.c

··· 243 243 struct pic32_sport *sport = to_pic32_sport(port); 244 244 unsigned long flags; 245 245 246 - spin_lock_irqsave(&port->lock, flags); 246 + uart_port_lock_irqsave(port, &flags); 247 247 248 248 if (ctl) 249 249 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA), ··· 252 252 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), 253 253 PIC32_UART_STA_UTXBRK); 254 254 255 - spin_unlock_irqrestore(&port->lock, flags); 255 + uart_port_unlock_irqrestore(port, flags); 256 256 } 257 257 258 258 /* get port type in string format */ ··· 274 274 */ 275 275 max_count = PIC32_UART_RX_FIFO_DEPTH; 276 276 277 - spin_lock(&port->lock); 277 + uart_port_lock(port); 278 278 279 279 tty = &port->state->port; 280 280 ··· 331 331 332 332 } while (--max_count); 333 333 334 - spin_unlock(&port->lock); 334 + uart_port_unlock(port); 335 335 336 336 tty_flip_buffer_push(tty); 337 337 } ··· 410 410 struct uart_port *port = dev_id; 411 411 unsigned long flags; 412 412 413 - spin_lock_irqsave(&port->lock, flags); 413 + uart_port_lock_irqsave(port, &flags); 414 414 pic32_uart_do_tx(port); 415 - spin_unlock_irqrestore(&port->lock, flags); 415 + uart_port_unlock_irqrestore(port, flags); 416 416 417 417 return IRQ_HANDLED; 418 418 } ··· 580 580 unsigned long flags; 581 581 582 582 /* disable uart */ 583 - spin_lock_irqsave(&port->lock, flags); 583 + uart_port_lock_irqsave(port, &flags); 584 584 pic32_uart_dsbl_and_mask(port); 585 - spin_unlock_irqrestore(&port->lock, flags); 585 + uart_port_unlock_irqrestore(port, flags); 586 586 clk_disable_unprepare(sport->clk); 587 587 588 588 /* free all 3 interrupts for this UART */ ··· 604 604 unsigned int quot; 605 605 unsigned long flags; 606 606 607 - spin_lock_irqsave(&port->lock, flags); 607 + uart_port_lock_irqsave(port, &flags); 608 608 609 609 /* disable uart and mask all interrupts while changing speed */ 610 610 pic32_uart_dsbl_and_mask(port); ··· 672 672 /* enable uart */ 673 673 pic32_uart_en_and_unmask(port); 674 674 675 - spin_unlock_irqrestore(&port->lock, flags); 675 + uart_port_unlock_irqrestore(port, flags); 676 676 } 677 677 678 678 /* serial core request to claim uart iomem */

+26 -26

drivers/tty/serial/pmac_zilog.c

··· 246 246 #endif /* USE_CTRL_O_SYSRQ */ 247 247 if (uap->port.sysrq) { 248 248 int swallow; 249 - spin_unlock(&uap->port.lock); 249 + uart_port_unlock(&uap->port); 250 250 swallow = uart_handle_sysrq_char(&uap->port, ch); 251 - spin_lock(&uap->port.lock); 251 + uart_port_lock(&uap->port); 252 252 if (swallow) 253 253 goto next_char; 254 254 } ··· 435 435 uap_a = pmz_get_port_A(uap); 436 436 uap_b = uap_a->mate; 437 437 438 - spin_lock(&uap_a->port.lock); 438 + uart_port_lock(&uap_a->port); 439 439 r3 = read_zsreg(uap_a, R3); 440 440 441 441 /* Channel A */ ··· 456 456 rc = IRQ_HANDLED; 457 457 } 458 458 skip_a: 459 - spin_unlock(&uap_a->port.lock); 459 + uart_port_unlock(&uap_a->port); 460 460 if (push) 461 461 tty_flip_buffer_push(&uap->port.state->port); 462 462 463 463 if (!uap_b) 464 464 goto out; 465 465 466 - spin_lock(&uap_b->port.lock); 466 + uart_port_lock(&uap_b->port); 467 467 push = false; 468 468 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) { 469 469 if (!ZS_IS_OPEN(uap_b)) { ··· 481 481 rc = IRQ_HANDLED; 482 482 } 483 483 skip_b: 484 - spin_unlock(&uap_b->port.lock); 484 + uart_port_unlock(&uap_b->port); 485 485 if (push) 486 486 tty_flip_buffer_push(&uap->port.state->port); 487 487 ··· 497 497 unsigned long flags; 498 498 u8 status; 499 499 500 - spin_lock_irqsave(&uap->port.lock, flags); 500 + uart_port_lock_irqsave(&uap->port, &flags); 501 501 status = read_zsreg(uap, R0); 502 - spin_unlock_irqrestore(&uap->port.lock, flags); 502 + uart_port_unlock_irqrestore(&uap->port, flags); 503 503 504 504 return status; 505 505 } ··· 685 685 else 686 686 clear_bits |= SND_BRK; 687 687 688 - spin_lock_irqsave(&port->lock, flags); 688 + uart_port_lock_irqsave(port, &flags); 689 689 690 690 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits; 691 691 if (new_reg != uap->curregs[R5]) { ··· 693 693 write_zsreg(uap, R5, uap->curregs[R5]); 694 694 } 695 695 696 - spin_unlock_irqrestore(&port->lock, flags); 696 + uart_port_unlock_irqrestore(port, flags); 697 697 } 698 698 699 699 #ifdef CONFIG_PPC_PMAC ··· 865 865 { 866 866 unsigned long flags; 867 867 868 - spin_lock_irqsave(&uap->port.lock, flags); 868 + uart_port_lock_irqsave(&uap->port, &flags); 869 869 uap->curregs[R5] |= DTR; 870 870 write_zsreg(uap, R5, uap->curregs[R5]); 871 871 zssync(uap); 872 - spin_unlock_irqrestore(&uap->port.lock, flags); 872 + uart_port_unlock_irqrestore(&uap->port, flags); 873 873 msleep(110); 874 874 875 - spin_lock_irqsave(&uap->port.lock, flags); 875 + uart_port_lock_irqsave(&uap->port, &flags); 876 876 uap->curregs[R5] &= ~DTR; 877 877 write_zsreg(uap, R5, uap->curregs[R5]); 878 878 zssync(uap); 879 - spin_unlock_irqrestore(&uap->port.lock, flags); 879 + uart_port_unlock_irqrestore(&uap->port, flags); 880 880 msleep(10); 881 881 } 882 882 ··· 896 896 * initialize the chip 897 897 */ 898 898 if (!ZS_IS_CONS(uap)) { 899 - spin_lock_irqsave(&port->lock, flags); 899 + uart_port_lock_irqsave(port, &flags); 900 900 pwr_delay = __pmz_startup(uap); 901 - spin_unlock_irqrestore(&port->lock, flags); 901 + uart_port_unlock_irqrestore(port, flags); 902 902 } 903 903 sprintf(uap->irq_name, PMACZILOG_NAME"%d", uap->port.line); 904 904 if (request_irq(uap->port.irq, pmz_interrupt, IRQF_SHARED, ··· 921 921 pmz_irda_reset(uap); 922 922 923 923 /* Enable interrupt requests for the channel */ 924 - spin_lock_irqsave(&port->lock, flags); 924 + uart_port_lock_irqsave(port, &flags); 925 925 pmz_interrupt_control(uap, 1); 926 - spin_unlock_irqrestore(&port->lock, flags); 926 + uart_port_unlock_irqrestore(port, flags); 927 927 928 928 return 0; 929 929 } ··· 933 933 struct uart_pmac_port *uap = to_pmz(port); 934 934 unsigned long flags; 935 935 936 - spin_lock_irqsave(&port->lock, flags); 936 + uart_port_lock_irqsave(port, &flags); 937 937 938 938 /* Disable interrupt requests for the channel */ 939 939 pmz_interrupt_control(uap, 0); ··· 948 948 pmz_maybe_update_regs(uap); 949 949 } 950 950 951 - spin_unlock_irqrestore(&port->lock, flags); 951 + uart_port_unlock_irqrestore(port, flags); 952 952 953 953 /* Release interrupt handler */ 954 954 free_irq(uap->port.irq, uap); 955 955 956 - spin_lock_irqsave(&port->lock, flags); 956 + uart_port_lock_irqsave(port, &flags); 957 957 958 958 uap->flags &= ~PMACZILOG_FLAG_IS_OPEN; 959 959 960 960 if (!ZS_IS_CONS(uap)) 961 961 pmz_set_scc_power(uap, 0); /* Shut the chip down */ 962 962 963 - spin_unlock_irqrestore(&port->lock, flags); 963 + uart_port_unlock_irqrestore(port, flags); 964 964 } 965 965 966 966 /* Shared by TTY driver and serial console setup. The port lock is held ··· 1247 1247 struct uart_pmac_port *uap = to_pmz(port); 1248 1248 unsigned long flags; 1249 1249 1250 - spin_lock_irqsave(&port->lock, flags); 1250 + uart_port_lock_irqsave(port, &flags); 1251 1251 1252 1252 /* Disable IRQs on the port */ 1253 1253 pmz_interrupt_control(uap, 0); ··· 1259 1259 if (ZS_IS_OPEN(uap)) 1260 1260 pmz_interrupt_control(uap, 1); 1261 1261 1262 - spin_unlock_irqrestore(&port->lock, flags); 1262 + uart_port_unlock_irqrestore(port, flags); 1263 1263 } 1264 1264 1265 1265 static const char *pmz_type(struct uart_port *port) ··· 1896 1896 struct uart_pmac_port *uap = &pmz_ports[con->index]; 1897 1897 unsigned long flags; 1898 1898 1899 - spin_lock_irqsave(&uap->port.lock, flags); 1899 + uart_port_lock_irqsave(&uap->port, &flags); 1900 1900 1901 1901 /* Turn of interrupts and enable the transmitter. */ 1902 1902 write_zsreg(uap, R1, uap->curregs[1] & ~TxINT_ENAB); ··· 1908 1908 write_zsreg(uap, R1, uap->curregs[1]); 1909 1909 /* Don't disable the transmitter. */ 1910 1910 1911 - spin_unlock_irqrestore(&uap->port.lock, flags); 1911 + uart_port_unlock_irqrestore(&uap->port, flags); 1912 1912 } 1913 1913 1914 1914 /*

+15 -15

drivers/tty/serial/pxa.c

··· 225 225 iir = serial_in(up, UART_IIR); 226 226 if (iir & UART_IIR_NO_INT) 227 227 return IRQ_NONE; 228 - spin_lock(&up->port.lock); 228 + uart_port_lock(&up->port); 229 229 lsr = serial_in(up, UART_LSR); 230 230 if (lsr & UART_LSR_DR) 231 231 receive_chars(up, &lsr); 232 232 check_modem_status(up); 233 233 if (lsr & UART_LSR_THRE) 234 234 transmit_chars(up); 235 - spin_unlock(&up->port.lock); 235 + uart_port_unlock(&up->port); 236 236 return IRQ_HANDLED; 237 237 } 238 238 ··· 242 242 unsigned long flags; 243 243 unsigned int ret; 244 244 245 - spin_lock_irqsave(&up->port.lock, flags); 245 + uart_port_lock_irqsave(&up->port, &flags); 246 246 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; 247 - spin_unlock_irqrestore(&up->port.lock, flags); 247 + uart_port_unlock_irqrestore(&up->port, flags); 248 248 249 249 return ret; 250 250 } ··· 295 295 struct uart_pxa_port *up = (struct uart_pxa_port *)port; 296 296 unsigned long flags; 297 297 298 - spin_lock_irqsave(&up->port.lock, flags); 298 + uart_port_lock_irqsave(&up->port, &flags); 299 299 if (break_state == -1) 300 300 up->lcr |= UART_LCR_SBC; 301 301 else 302 302 up->lcr &= ~UART_LCR_SBC; 303 303 serial_out(up, UART_LCR, up->lcr); 304 - spin_unlock_irqrestore(&up->port.lock, flags); 304 + uart_port_unlock_irqrestore(&up->port, flags); 305 305 } 306 306 307 307 static int serial_pxa_startup(struct uart_port *port) ··· 346 346 */ 347 347 serial_out(up, UART_LCR, UART_LCR_WLEN8); 348 348 349 - spin_lock_irqsave(&up->port.lock, flags); 349 + uart_port_lock_irqsave(&up->port, &flags); 350 350 up->port.mctrl |= TIOCM_OUT2; 351 351 serial_pxa_set_mctrl(&up->port, up->port.mctrl); 352 - spin_unlock_irqrestore(&up->port.lock, flags); 352 + uart_port_unlock_irqrestore(&up->port, flags); 353 353 354 354 /* 355 355 * Finally, enable interrupts. Note: Modem status interrupts ··· 383 383 up->ier = 0; 384 384 serial_out(up, UART_IER, 0); 385 385 386 - spin_lock_irqsave(&up->port.lock, flags); 386 + uart_port_lock_irqsave(&up->port, &flags); 387 387 up->port.mctrl &= ~TIOCM_OUT2; 388 388 serial_pxa_set_mctrl(&up->port, up->port.mctrl); 389 - spin_unlock_irqrestore(&up->port.lock, flags); 389 + uart_port_unlock_irqrestore(&up->port, flags); 390 390 391 391 /* 392 392 * Disable break condition and FIFOs ··· 434 434 * Ok, we're now changing the port state. Do it with 435 435 * interrupts disabled. 436 436 */ 437 - spin_lock_irqsave(&up->port.lock, flags); 437 + uart_port_lock_irqsave(&up->port, &flags); 438 438 439 439 /* 440 440 * Ensure the port will be enabled. ··· 504 504 up->lcr = cval; /* Save LCR */ 505 505 serial_pxa_set_mctrl(&up->port, up->port.mctrl); 506 506 serial_out(up, UART_FCR, fcr); 507 - spin_unlock_irqrestore(&up->port.lock, flags); 507 + uart_port_unlock_irqrestore(&up->port, flags); 508 508 } 509 509 510 510 static void ··· 608 608 if (up->port.sysrq) 609 609 locked = 0; 610 610 else if (oops_in_progress) 611 - locked = spin_trylock(&up->port.lock); 611 + locked = uart_port_trylock(&up->port); 612 612 else 613 - spin_lock(&up->port.lock); 613 + uart_port_lock(&up->port); 614 614 615 615 /* 616 616 * First save the IER then disable the interrupts ··· 628 628 serial_out(up, UART_IER, ier); 629 629 630 630 if (locked) 631 - spin_unlock(&up->port.lock); 631 + uart_port_unlock(&up->port); 632 632 local_irq_restore(flags); 633 633 clk_disable(up->clk); 634 634

+4 -4

drivers/tty/serial/qcom_geni_serial.c

··· 482 482 483 483 uport = &port->uport; 484 484 if (oops_in_progress) 485 - locked = spin_trylock_irqsave(&uport->lock, flags); 485 + locked = uart_port_trylock_irqsave(uport, &flags); 486 486 else 487 - spin_lock_irqsave(&uport->lock, flags); 487 + uart_port_lock_irqsave(uport, &flags); 488 488 489 489 geni_status = readl(uport->membase + SE_GENI_STATUS); 490 490 ··· 520 520 qcom_geni_serial_setup_tx(uport, port->tx_remaining); 521 521 522 522 if (locked) 523 - spin_unlock_irqrestore(&uport->lock, flags); 523 + uart_port_unlock_irqrestore(uport, flags); 524 524 } 525 525 526 526 static void handle_rx_console(struct uart_port *uport, u32 bytes, bool drop) ··· 970 970 if (uport->suspended) 971 971 return IRQ_NONE; 972 972 973 - spin_lock(&uport->lock); 973 + uart_port_lock(uport); 974 974 975 975 m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS); 976 976 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);

+17 -17

drivers/tty/serial/rda-uart.c

··· 139 139 unsigned int ret; 140 140 u32 val; 141 141 142 - spin_lock_irqsave(&port->lock, flags); 142 + uart_port_lock_irqsave(port, &flags); 143 143 144 144 val = rda_uart_read(port, RDA_UART_STATUS); 145 145 ret = (val & RDA_UART_TX_FIFO_MASK) ? TIOCSER_TEMT : 0; 146 146 147 - spin_unlock_irqrestore(&port->lock, flags); 147 + uart_port_unlock_irqrestore(port, flags); 148 148 149 149 return ret; 150 150 } ··· 246 246 unsigned int baud; 247 247 u32 irq_mask; 248 248 249 - spin_lock_irqsave(&port->lock, flags); 249 + uart_port_lock_irqsave(port, &flags); 250 250 251 251 baud = uart_get_baud_rate(port, termios, old, 9600, port->uartclk / 4); 252 252 rda_uart_change_baudrate(rda_port, baud); ··· 325 325 /* update the per-port timeout */ 326 326 uart_update_timeout(port, termios->c_cflag, baud); 327 327 328 - spin_unlock_irqrestore(&port->lock, flags); 328 + uart_port_unlock_irqrestore(port, flags); 329 329 } 330 330 331 331 static void rda_uart_send_chars(struct uart_port *port) ··· 408 408 unsigned long flags; 409 409 u32 val, irq_mask; 410 410 411 - spin_lock_irqsave(&port->lock, flags); 411 + uart_port_lock_irqsave(port, &flags); 412 412 413 413 /* Clear IRQ cause */ 414 414 val = rda_uart_read(port, RDA_UART_IRQ_CAUSE); ··· 425 425 rda_uart_send_chars(port); 426 426 } 427 427 428 - spin_unlock_irqrestore(&port->lock, flags); 428 + uart_port_unlock_irqrestore(port, flags); 429 429 430 430 return IRQ_HANDLED; 431 431 } ··· 436 436 int ret; 437 437 u32 val; 438 438 439 - spin_lock_irqsave(&port->lock, flags); 439 + uart_port_lock_irqsave(port, &flags); 440 440 rda_uart_write(port, 0, RDA_UART_IRQ_MASK); 441 - spin_unlock_irqrestore(&port->lock, flags); 441 + uart_port_unlock_irqrestore(port, flags); 442 442 443 443 ret = request_irq(port->irq, rda_interrupt, IRQF_NO_SUSPEND, 444 444 "rda-uart", port); 445 445 if (ret) 446 446 return ret; 447 447 448 - spin_lock_irqsave(&port->lock, flags); 448 + uart_port_lock_irqsave(port, &flags); 449 449 450 450 val = rda_uart_read(port, RDA_UART_CTRL); 451 451 val |= RDA_UART_ENABLE; ··· 456 456 val |= (RDA_UART_RX_DATA_AVAILABLE | RDA_UART_RX_TIMEOUT); 457 457 rda_uart_write(port, val, RDA_UART_IRQ_MASK); 458 458 459 - spin_unlock_irqrestore(&port->lock, flags); 459 + uart_port_unlock_irqrestore(port, flags); 460 460 461 461 return 0; 462 462 } ··· 466 466 unsigned long flags; 467 467 u32 val; 468 468 469 - spin_lock_irqsave(&port->lock, flags); 469 + uart_port_lock_irqsave(port, &flags); 470 470 471 471 rda_uart_stop_tx(port); 472 472 rda_uart_stop_rx(port); ··· 475 475 val &= ~RDA_UART_ENABLE; 476 476 rda_uart_write(port, val, RDA_UART_CTRL); 477 477 478 - spin_unlock_irqrestore(&port->lock, flags); 478 + uart_port_unlock_irqrestore(port, flags); 479 479 } 480 480 481 481 static const char *rda_uart_type(struct uart_port *port) ··· 515 515 rda_uart_request_port(port); 516 516 } 517 517 518 - spin_lock_irqsave(&port->lock, irq_flags); 518 + uart_port_lock_irqsave(port, &irq_flags); 519 519 520 520 /* Clear mask, so no surprise interrupts. */ 521 521 rda_uart_write(port, 0, RDA_UART_IRQ_MASK); ··· 523 523 /* Clear status register */ 524 524 rda_uart_write(port, 0, RDA_UART_STATUS); 525 525 526 - spin_unlock_irqrestore(&port->lock, irq_flags); 526 + uart_port_unlock_irqrestore(port, irq_flags); 527 527 } 528 528 529 529 static void rda_uart_release_port(struct uart_port *port) ··· 597 597 if (port->sysrq) { 598 598 locked = 0; 599 599 } else if (oops_in_progress) { 600 - locked = spin_trylock(&port->lock); 600 + locked = uart_port_trylock(port); 601 601 } else { 602 - spin_lock(&port->lock); 602 + uart_port_lock(port); 603 603 locked = 1; 604 604 } 605 605 ··· 615 615 rda_uart_write(port, old_irq_mask, RDA_UART_IRQ_MASK); 616 616 617 617 if (locked) 618 - spin_unlock(&port->lock); 618 + uart_port_unlock(port); 619 619 620 620 local_irq_restore(flags); 621 621 }

+10 -10

drivers/tty/serial/rp2.c

··· 276 276 * But the TXEMPTY bit doesn't seem to work unless the TX IRQ is 277 277 * enabled. 278 278 */ 279 - spin_lock_irqsave(&up->port.lock, flags); 279 + uart_port_lock_irqsave(&up->port, &flags); 280 280 tx_fifo_bytes = readw(up->base + RP2_TX_FIFO_COUNT); 281 - spin_unlock_irqrestore(&up->port.lock, flags); 281 + uart_port_unlock_irqrestore(&up->port, flags); 282 282 283 283 return tx_fifo_bytes ? 0 : TIOCSER_TEMT; 284 284 } ··· 323 323 { 324 324 unsigned long flags; 325 325 326 - spin_lock_irqsave(&port->lock, flags); 326 + uart_port_lock_irqsave(port, &flags); 327 327 rp2_rmw(port_to_up(port), RP2_TXRX_CTL, RP2_TXRX_CTL_BREAK_m, 328 328 break_state ? RP2_TXRX_CTL_BREAK_m : 0); 329 - spin_unlock_irqrestore(&port->lock, flags); 329 + uart_port_unlock_irqrestore(port, flags); 330 330 } 331 331 332 332 static void rp2_uart_enable_ms(struct uart_port *port) ··· 383 383 if (tty_termios_baud_rate(new)) 384 384 tty_termios_encode_baud_rate(new, baud, baud); 385 385 386 - spin_lock_irqsave(&port->lock, flags); 386 + uart_port_lock_irqsave(port, &flags); 387 387 388 388 /* ignore all characters if CREAD is not set */ 389 389 port->ignore_status_mask = (new->c_cflag & CREAD) ? 0 : RP2_DUMMY_READ; ··· 391 391 __rp2_uart_set_termios(up, new->c_cflag, new->c_iflag, baud_div); 392 392 uart_update_timeout(port, new->c_cflag, baud); 393 393 394 - spin_unlock_irqrestore(&port->lock, flags); 394 + uart_port_unlock_irqrestore(port, flags); 395 395 } 396 396 397 397 static void rp2_rx_chars(struct rp2_uart_port *up) ··· 440 440 { 441 441 u32 status; 442 442 443 - spin_lock(&up->port.lock); 443 + uart_port_lock(&up->port); 444 444 445 445 /* 446 446 * The IRQ status bits are clear-on-write. Other status bits in ··· 456 456 if (status & RP2_CHAN_STAT_MS_CHANGED_MASK) 457 457 wake_up_interruptible(&up->port.state->port.delta_msr_wait); 458 458 459 - spin_unlock(&up->port.lock); 459 + uart_port_unlock(&up->port); 460 460 } 461 461 462 462 static int rp2_asic_interrupt(struct rp2_card *card, unsigned int asic_id) ··· 516 516 517 517 rp2_uart_break_ctl(port, 0); 518 518 519 - spin_lock_irqsave(&port->lock, flags); 519 + uart_port_lock_irqsave(port, &flags); 520 520 rp2_mask_ch_irq(up, up->idx, 0); 521 521 rp2_rmw(up, RP2_CHAN_STAT, 0, 0); 522 - spin_unlock_irqrestore(&port->lock, flags); 522 + uart_port_unlock_irqrestore(port, flags); 523 523 } 524 524 525 525 static const char *rp2_uart_type(struct uart_port *port)

+10 -10

drivers/tty/serial/sa1100.c

··· 115 115 unsigned long flags; 116 116 117 117 if (sport->port.state) { 118 - spin_lock_irqsave(&sport->port.lock, flags); 118 + uart_port_lock_irqsave(&sport->port, &flags); 119 119 sa1100_mctrl_check(sport); 120 - spin_unlock_irqrestore(&sport->port.lock, flags); 120 + uart_port_unlock_irqrestore(&sport->port, flags); 121 121 122 122 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT); 123 123 } ··· 247 247 struct sa1100_port *sport = dev_id; 248 248 unsigned int status, pass_counter = 0; 249 249 250 - spin_lock(&sport->port.lock); 250 + uart_port_lock(&sport->port); 251 251 status = UART_GET_UTSR0(sport); 252 252 status &= SM_TO_UTSR0(sport->port.read_status_mask) | ~UTSR0_TFS; 253 253 do { ··· 276 276 status &= SM_TO_UTSR0(sport->port.read_status_mask) | 277 277 ~UTSR0_TFS; 278 278 } while (status & (UTSR0_TFS | UTSR0_RFS | UTSR0_RID)); 279 - spin_unlock(&sport->port.lock); 279 + uart_port_unlock(&sport->port); 280 280 281 281 return IRQ_HANDLED; 282 282 } ··· 321 321 unsigned long flags; 322 322 unsigned int utcr3; 323 323 324 - spin_lock_irqsave(&sport->port.lock, flags); 324 + uart_port_lock_irqsave(&sport->port, &flags); 325 325 utcr3 = UART_GET_UTCR3(sport); 326 326 if (break_state == -1) 327 327 utcr3 |= UTCR3_BRK; 328 328 else 329 329 utcr3 &= ~UTCR3_BRK; 330 330 UART_PUT_UTCR3(sport, utcr3); 331 - spin_unlock_irqrestore(&sport->port.lock, flags); 331 + uart_port_unlock_irqrestore(&sport->port, flags); 332 332 } 333 333 334 334 static int sa1100_startup(struct uart_port *port) ··· 354 354 /* 355 355 * Enable modem status interrupts 356 356 */ 357 - spin_lock_irq(&sport->port.lock); 357 + uart_port_lock_irq(&sport->port); 358 358 sa1100_enable_ms(&sport->port); 359 - spin_unlock_irq(&sport->port.lock); 359 + uart_port_unlock_irq(&sport->port); 360 360 361 361 return 0; 362 362 } ··· 423 423 424 424 del_timer_sync(&sport->timer); 425 425 426 - spin_lock_irqsave(&sport->port.lock, flags); 426 + uart_port_lock_irqsave(&sport->port, &flags); 427 427 428 428 sport->port.read_status_mask &= UTSR0_TO_SM(UTSR0_TFS); 429 429 sport->port.read_status_mask |= UTSR1_TO_SM(UTSR1_ROR); ··· 485 485 if (UART_ENABLE_MS(&sport->port, termios->c_cflag)) 486 486 sa1100_enable_ms(&sport->port); 487 487 488 - spin_unlock_irqrestore(&sport->port.lock, flags); 488 + uart_port_unlock_irqrestore(&sport->port, flags); 489 489 } 490 490 491 491 static const char *sa1100_type(struct uart_port *port)

+26 -145

drivers/tty/serial/samsung_tty.c

··· 64 64 #define RXSTAT_DUMMY_READ (0x10000000) 65 65 66 66 enum s3c24xx_port_type { 67 - TYPE_S3C24XX, 68 67 TYPE_S3C6400, 69 68 TYPE_APPLE_S5L, 70 69 }; ··· 127 128 }; 128 129 129 130 struct s3c24xx_uart_port { 130 - unsigned char rx_claimed; 131 - unsigned char tx_claimed; 132 131 unsigned char rx_enabled; 133 132 unsigned char tx_enabled; 134 133 unsigned int pm_level; ··· 245 248 unsigned int ucon, ufcon; 246 249 int count = 10000; 247 250 248 - spin_lock_irqsave(&port->lock, flags); 251 + uart_port_lock_irqsave(port, &flags); 249 252 250 253 while (--count && !s3c24xx_serial_txempty_nofifo(port)) 251 254 udelay(100); ··· 259 262 wr_regl(port, S3C2410_UCON, ucon); 260 263 261 264 ourport->rx_enabled = 1; 262 - spin_unlock_irqrestore(&port->lock, flags); 265 + uart_port_unlock_irqrestore(port, flags); 263 266 } 264 267 265 268 static void s3c24xx_serial_rx_disable(struct uart_port *port) ··· 268 271 unsigned long flags; 269 272 unsigned int ucon; 270 273 271 - spin_lock_irqsave(&port->lock, flags); 274 + uart_port_lock_irqsave(port, &flags); 272 275 273 276 ucon = rd_regl(port, S3C2410_UCON); 274 277 ucon &= ~S3C2410_UCON_RXIRQMODE; 275 278 wr_regl(port, S3C2410_UCON, ucon); 276 279 277 280 ourport->rx_enabled = 0; 278 - spin_unlock_irqrestore(&port->lock, flags); 281 + uart_port_unlock_irqrestore(port, flags); 279 282 } 280 283 281 284 static void s3c24xx_serial_stop_tx(struct uart_port *port) ··· 341 344 dma->tx_transfer_addr, dma->tx_size, 342 345 DMA_TO_DEVICE); 343 346 344 - spin_lock_irqsave(&port->lock, flags); 347 + uart_port_lock_irqsave(port, &flags); 345 348 346 349 uart_xmit_advance(port, count); 347 350 ourport->tx_in_progress = 0; ··· 350 353 uart_write_wakeup(port); 351 354 352 355 s3c24xx_serial_start_next_tx(ourport); 353 - spin_unlock_irqrestore(&port->lock, flags); 356 + uart_port_unlock_irqrestore(port, flags); 354 357 } 355 358 356 359 static void enable_tx_dma(struct s3c24xx_uart_port *ourport) ··· 616 619 received = dma->rx_bytes_requested - state.residue; 617 620 async_tx_ack(dma->rx_desc); 618 621 619 - spin_lock_irqsave(&port->lock, flags); 622 + uart_port_lock_irqsave(port, &flags); 620 623 621 624 if (received) 622 625 s3c24xx_uart_copy_rx_to_tty(ourport, t, received); ··· 628 631 629 632 s3c64xx_start_rx_dma(ourport); 630 633 631 - spin_unlock_irqrestore(&port->lock, flags); 634 + uart_port_unlock_irqrestore(port, flags); 632 635 } 633 636 634 637 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport) ··· 719 722 utrstat = rd_regl(port, S3C2410_UTRSTAT); 720 723 rd_regl(port, S3C2410_UFSTAT); 721 724 722 - spin_lock(&port->lock); 725 + uart_port_lock(port); 723 726 724 727 if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) { 725 728 s3c64xx_start_rx_dma(ourport); ··· 748 751 wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT); 749 752 750 753 finish: 751 - spin_unlock(&port->lock); 754 + uart_port_unlock(port); 752 755 753 756 return IRQ_HANDLED; 754 757 } ··· 846 849 struct s3c24xx_uart_port *ourport = dev_id; 847 850 struct uart_port *port = &ourport->port; 848 851 849 - spin_lock(&port->lock); 852 + uart_port_lock(port); 850 853 s3c24xx_serial_rx_drain_fifo(ourport); 851 - spin_unlock(&port->lock); 854 + uart_port_unlock(port); 852 855 853 856 return IRQ_HANDLED; 854 857 } ··· 929 932 struct s3c24xx_uart_port *ourport = id; 930 933 struct uart_port *port = &ourport->port; 931 934 932 - spin_lock(&port->lock); 935 + uart_port_lock(port); 933 936 934 937 s3c24xx_serial_tx_chars(ourport); 935 938 936 - spin_unlock(&port->lock); 939 + uart_port_unlock(port); 937 940 return IRQ_HANDLED; 938 941 } 939 942 ··· 1030 1033 unsigned long flags; 1031 1034 unsigned int ucon; 1032 1035 1033 - spin_lock_irqsave(&port->lock, flags); 1036 + uart_port_lock_irqsave(port, &flags); 1034 1037 1035 1038 ucon = rd_regl(port, S3C2410_UCON); 1036 1039 ··· 1041 1044 1042 1045 wr_regl(port, S3C2410_UCON, ucon); 1043 1046 1044 - spin_unlock_irqrestore(&port->lock, flags); 1047 + uart_port_unlock_irqrestore(port, flags); 1045 1048 } 1046 1049 1047 1050 static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p) ··· 1163 1166 } 1164 1167 } 1165 1168 1166 - static void s3c24xx_serial_shutdown(struct uart_port *port) 1167 - { 1168 - struct s3c24xx_uart_port *ourport = to_ourport(port); 1169 - 1170 - if (ourport->tx_claimed) { 1171 - free_irq(ourport->tx_irq, ourport); 1172 - ourport->tx_enabled = 0; 1173 - ourport->tx_claimed = 0; 1174 - ourport->tx_mode = 0; 1175 - } 1176 - 1177 - if (ourport->rx_claimed) { 1178 - free_irq(ourport->rx_irq, ourport); 1179 - ourport->rx_claimed = 0; 1180 - ourport->rx_enabled = 0; 1181 - } 1182 - 1183 - if (ourport->dma) 1184 - s3c24xx_serial_release_dma(ourport); 1185 - 1186 - ourport->tx_in_progress = 0; 1187 - } 1188 - 1189 1169 static void s3c64xx_serial_shutdown(struct uart_port *port) 1190 1170 { 1191 1171 struct s3c24xx_uart_port *ourport = to_ourport(port); ··· 1208 1234 ourport->tx_in_progress = 0; 1209 1235 } 1210 1236 1211 - static int s3c24xx_serial_startup(struct uart_port *port) 1212 - { 1213 - struct s3c24xx_uart_port *ourport = to_ourport(port); 1214 - int ret; 1215 - 1216 - ourport->rx_enabled = 1; 1217 - 1218 - ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_irq, 0, 1219 - s3c24xx_serial_portname(port), ourport); 1220 - 1221 - if (ret != 0) { 1222 - dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq); 1223 - return ret; 1224 - } 1225 - 1226 - ourport->rx_claimed = 1; 1227 - 1228 - dev_dbg(port->dev, "requesting tx irq...\n"); 1229 - 1230 - ourport->tx_enabled = 1; 1231 - 1232 - ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_irq, 0, 1233 - s3c24xx_serial_portname(port), ourport); 1234 - 1235 - if (ret) { 1236 - dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq); 1237 - goto err; 1238 - } 1239 - 1240 - ourport->tx_claimed = 1; 1241 - 1242 - /* the port reset code should have done the correct 1243 - * register setup for the port controls 1244 - */ 1245 - 1246 - return ret; 1247 - 1248 - err: 1249 - s3c24xx_serial_shutdown(port); 1250 - return ret; 1251 - } 1252 - 1253 1237 static int s3c64xx_serial_startup(struct uart_port *port) 1254 1238 { 1255 1239 struct s3c24xx_uart_port *ourport = to_ourport(port); ··· 1235 1303 ourport->rx_enabled = 1; 1236 1304 ourport->tx_enabled = 0; 1237 1305 1238 - spin_lock_irqsave(&port->lock, flags); 1306 + uart_port_lock_irqsave(port, &flags); 1239 1307 1240 1308 ufcon = rd_regl(port, S3C2410_UFCON); 1241 1309 ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8; ··· 1245 1313 1246 1314 enable_rx_pio(ourport); 1247 1315 1248 - spin_unlock_irqrestore(&port->lock, flags); 1316 + uart_port_unlock_irqrestore(port, flags); 1249 1317 1250 1318 /* Enable Rx Interrupt */ 1251 1319 s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM); ··· 1273 1341 ourport->rx_enabled = 1; 1274 1342 ourport->tx_enabled = 0; 1275 1343 1276 - spin_lock_irqsave(&port->lock, flags); 1344 + uart_port_lock_irqsave(port, &flags); 1277 1345 1278 1346 ufcon = rd_regl(port, S3C2410_UFCON); 1279 1347 ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8; ··· 1283 1351 1284 1352 enable_rx_pio(ourport); 1285 1353 1286 - spin_unlock_irqrestore(&port->lock, flags); 1354 + uart_port_unlock_irqrestore(port, flags); 1287 1355 1288 1356 /* Enable Rx Interrupt */ 1289 1357 s3c24xx_set_bit(port, APPLE_S5L_UCON_RXTHRESH_ENA, S3C2410_UCON); ··· 1558 1626 ulcon |= S3C2410_LCON_PNONE; 1559 1627 } 1560 1628 1561 - spin_lock_irqsave(&port->lock, flags); 1629 + uart_port_lock_irqsave(port, &flags); 1562 1630 1563 1631 dev_dbg(port->dev, 1564 1632 "setting ulcon to %08x, brddiv to %d, udivslot %08x\n", ··· 1616 1684 if ((termios->c_cflag & CREAD) == 0) 1617 1685 port->ignore_status_mask |= RXSTAT_DUMMY_READ; 1618 1686 1619 - spin_unlock_irqrestore(&port->lock, flags); 1687 + uart_port_unlock_irqrestore(port, flags); 1620 1688 } 1621 1689 1622 1690 static const char *s3c24xx_serial_type(struct uart_port *port) ··· 1624 1692 const struct s3c24xx_uart_port *ourport = to_ourport(port); 1625 1693 1626 1694 switch (ourport->info->type) { 1627 - case TYPE_S3C24XX: 1628 - return "S3C24XX"; 1629 1695 case TYPE_S3C6400: 1630 1696 return "S3C6400/10"; 1631 1697 case TYPE_APPLE_S5L: ··· 1682 1752 static void s3c24xx_serial_put_poll_char(struct uart_port *port, 1683 1753 unsigned char c); 1684 1754 #endif 1685 - 1686 - static const struct uart_ops s3c24xx_serial_ops = { 1687 - .pm = s3c24xx_serial_pm, 1688 - .tx_empty = s3c24xx_serial_tx_empty, 1689 - .get_mctrl = s3c24xx_serial_get_mctrl, 1690 - .set_mctrl = s3c24xx_serial_set_mctrl, 1691 - .stop_tx = s3c24xx_serial_stop_tx, 1692 - .start_tx = s3c24xx_serial_start_tx, 1693 - .stop_rx = s3c24xx_serial_stop_rx, 1694 - .break_ctl = s3c24xx_serial_break_ctl, 1695 - .startup = s3c24xx_serial_startup, 1696 - .shutdown = s3c24xx_serial_shutdown, 1697 - .set_termios = s3c24xx_serial_set_termios, 1698 - .type = s3c24xx_serial_type, 1699 - .config_port = s3c24xx_serial_config_port, 1700 - .verify_port = s3c24xx_serial_verify_port, 1701 - #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL) 1702 - .poll_get_char = s3c24xx_serial_get_poll_char, 1703 - .poll_put_char = s3c24xx_serial_put_poll_char, 1704 - #endif 1705 - }; 1706 1755 1707 1756 static const struct uart_ops s3c64xx_serial_ops = { 1708 1757 .pm = s3c24xx_serial_pm, ··· 1745 1836 port->iotype = UPIO_MEM; 1746 1837 port->uartclk = 0; 1747 1838 port->fifosize = 16; 1748 - port->ops = &s3c24xx_serial_ops; 1749 1839 port->flags = UPF_BOOT_AUTOCONF; 1750 1840 port->line = index; 1751 1841 } ··· 1860 1952 port->irq = ret; 1861 1953 ourport->rx_irq = ret; 1862 1954 ourport->tx_irq = ret + 1; 1863 - } 1864 - 1865 - switch (ourport->info->type) { 1866 - case TYPE_S3C24XX: 1867 - ret = platform_get_irq(platdev, 1); 1868 - if (ret > 0) 1869 - ourport->tx_irq = ret; 1870 - break; 1871 - default: 1872 - break; 1873 1955 } 1874 1956 1875 1957 /* ··· 1981 2083 &ourport->drv_data->def_cfg; 1982 2084 1983 2085 switch (ourport->info->type) { 1984 - case TYPE_S3C24XX: 1985 - ourport->port.ops = &s3c24xx_serial_ops; 1986 - break; 1987 2086 case TYPE_S3C6400: 1988 2087 ourport->port.ops = &s3c64xx_serial_ops; 1989 2088 break; ··· 2271 2376 if (cons_uart->sysrq) 2272 2377 locked = false; 2273 2378 else if (oops_in_progress) 2274 - locked = spin_trylock_irqsave(&cons_uart->lock, flags); 2379 + locked = uart_port_trylock_irqsave(cons_uart, &flags); 2275 2380 else 2276 - spin_lock_irqsave(&cons_uart->lock, flags); 2381 + uart_port_lock_irqsave(cons_uart, &flags); 2277 2382 2278 2383 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar); 2279 2384 2280 2385 if (locked) 2281 - spin_unlock_irqrestore(&cons_uart->lock, flags); 2386 + uart_port_unlock_irqrestore(cons_uart, flags); 2282 2387 } 2283 2388 2284 2389 /* Shouldn't be __init, as it can be instantiated from other module */ ··· 2735 2840 .rxfifo_mask = S3C2410_UFSTAT_RXFULL | S3C2410_UFSTAT_RXMASK, 2736 2841 }; 2737 2842 2738 - static int __init s3c2410_early_console_setup(struct earlycon_device *device, 2739 - const char *opt) 2740 - { 2741 - device->port.private_data = &s3c2410_early_console_data; 2742 - return samsung_early_console_setup(device, opt); 2743 - } 2744 - 2745 - OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart", 2746 - s3c2410_early_console_setup); 2747 - 2748 - /* S3C2412, S3C2440, S3C64xx */ 2843 + /* S3C64xx */ 2749 2844 static struct samsung_early_console_data s3c2440_early_console_data = { 2750 2845 .txfull_mask = S3C2440_UFSTAT_TXFULL, 2751 2846 .rxfifo_mask = S3C2440_UFSTAT_RXFULL | S3C2440_UFSTAT_RXMASK, ··· 2748 2863 return samsung_early_console_setup(device, opt); 2749 2864 } 2750 2865 2751 - OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart", 2752 - s3c2440_early_console_setup); 2753 - OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart", 2754 - s3c2440_early_console_setup); 2755 2866 OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart", 2756 2867 s3c2440_early_console_setup); 2757 2868

+6 -6

drivers/tty/serial/sb1250-duart.c

··· 610 610 else 611 611 aux &= ~M_DUART_CTS_CHNG_ENA; 612 612 613 - spin_lock(&uport->lock); 613 + uart_port_lock(uport); 614 614 615 615 if (sport->tx_stopped) 616 616 command |= M_DUART_TX_DIS; ··· 632 632 633 633 write_sbdchn(sport, R_DUART_CMD, command); 634 634 635 - spin_unlock(&uport->lock); 635 + uart_port_unlock(uport); 636 636 } 637 637 638 638 ··· 839 839 unsigned int mask; 840 840 841 841 /* Disable transmit interrupts and enable the transmitter. */ 842 - spin_lock_irqsave(&uport->lock, flags); 842 + uart_port_lock_irqsave(uport, &flags); 843 843 mask = read_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2)); 844 844 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), 845 845 mask & ~M_DUART_IMR_TX); 846 846 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_EN); 847 - spin_unlock_irqrestore(&uport->lock, flags); 847 + uart_port_unlock_irqrestore(uport, flags); 848 848 849 849 uart_console_write(&sport->port, s, count, sbd_console_putchar); 850 850 851 851 /* Restore transmit interrupts and the transmitter enable. */ 852 - spin_lock_irqsave(&uport->lock, flags); 852 + uart_port_lock_irqsave(uport, &flags); 853 853 sbd_line_drain(sport); 854 854 if (sport->tx_stopped) 855 855 write_sbdchn(sport, R_DUART_CMD, M_DUART_TX_DIS); 856 856 write_sbdshr(sport, R_DUART_IMRREG((uport->line) % 2), mask); 857 - spin_unlock_irqrestore(&uport->lock, flags); 857 + uart_port_unlock_irqrestore(uport, flags); 858 858 } 859 859 860 860 static int __init sbd_console_setup(struct console *co, char *options)

+48 -35

drivers/tty/serial/sc16is7xx.c

··· 223 223 * trigger levels. Trigger levels from 4 characters to 60 characters are 224 224 * available with a granularity of four. 225 225 * 226 - * When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the 226 + * When the trigger level setting in TLR is zero, the SC16IS74x/75x/76x uses the 227 227 * trigger level setting defined in FCR. If TLR has non-zero trigger level value 228 228 * the trigger level defined in FCR is discarded. This applies to both transmit 229 229 * FIFO and receive FIFO trigger level setting. ··· 234 234 #define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0) 235 235 #define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4) 236 236 237 - /* IOControl register bits (Only 750/760) */ 237 + /* IOControl register bits (Only 75x/76x) */ 238 238 #define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */ 239 239 #define SC16IS7XX_IOCONTROL_MODEM_A_BIT (1 << 1) /* Enable GPIO[7:4] as modem A pins */ 240 240 #define SC16IS7XX_IOCONTROL_MODEM_B_BIT (1 << 2) /* Enable GPIO[3:0] as modem B pins */ ··· 249 249 #define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5) /* RTS output inversion */ 250 250 #define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7) /* IrDA mode 251 251 * 0 = rate upto 115.2 kbit/s 252 - * - Only 750/760 252 + * - Only 75x/76x 253 253 * 1 = rate upto 1.152 Mbit/s 254 - * - Only 760 254 + * - Only 76x 255 255 */ 256 256 257 257 /* EFR register bits */ ··· 358 358 static void sc16is7xx_ier_set(struct uart_port *port, u8 bit); 359 359 static void sc16is7xx_stop_tx(struct uart_port *port); 360 360 361 - #define to_sc16is7xx_port(p,e) ((container_of((p), struct sc16is7xx_port, e))) 362 361 #define to_sc16is7xx_one(p,e) ((container_of((p), struct sc16is7xx_one, e))) 363 362 364 363 static int sc16is7xx_line(struct uart_port *port) ··· 666 667 } 667 668 668 669 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 669 - spin_lock_irqsave(&port->lock, flags); 670 + uart_port_lock_irqsave(port, &flags); 670 671 sc16is7xx_stop_tx(port); 671 - spin_unlock_irqrestore(&port->lock, flags); 672 + uart_port_unlock_irqrestore(port, flags); 672 673 return; 673 674 } 674 675 ··· 694 695 sc16is7xx_fifo_write(port, to_send); 695 696 } 696 697 697 - spin_lock_irqsave(&port->lock, flags); 698 + uart_port_lock_irqsave(port, &flags); 698 699 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 699 700 uart_write_wakeup(port); 700 701 701 702 if (uart_circ_empty(xmit)) 702 703 sc16is7xx_stop_tx(port); 703 - spin_unlock_irqrestore(&port->lock, flags); 704 + uart_port_unlock_irqrestore(port, flags); 704 705 } 705 706 706 707 static unsigned int sc16is7xx_get_hwmctrl(struct uart_port *port) ··· 732 733 733 734 one->old_mctrl = status; 734 735 735 - spin_lock_irqsave(&port->lock, flags); 736 + uart_port_lock_irqsave(port, &flags); 736 737 if ((changed & TIOCM_RNG) && (status & TIOCM_RNG)) 737 738 port->icount.rng++; 738 739 if (changed & TIOCM_DSR) ··· 743 744 uart_handle_cts_change(port, status & TIOCM_CTS); 744 745 745 746 wake_up_interruptible(&port->state->port.delta_msr_wait); 746 - spin_unlock_irqrestore(&port->lock, flags); 747 + uart_port_unlock_irqrestore(port, flags); 747 748 } 748 749 749 750 static bool sc16is7xx_port_irq(struct sc16is7xx_port *s, int portno) ··· 822 823 sc16is7xx_handle_tx(port); 823 824 mutex_unlock(&s->efr_lock); 824 825 825 - spin_lock_irqsave(&port->lock, flags); 826 + uart_port_lock_irqsave(port, &flags); 826 827 sc16is7xx_ier_set(port, SC16IS7XX_IER_THRI_BIT); 827 - spin_unlock_irqrestore(&port->lock, flags); 828 + uart_port_unlock_irqrestore(port, flags); 828 829 } 829 830 830 831 static void sc16is7xx_reconf_rs485(struct uart_port *port) ··· 835 836 struct serial_rs485 *rs485 = &port->rs485; 836 837 unsigned long irqflags; 837 838 838 - spin_lock_irqsave(&port->lock, irqflags); 839 + uart_port_lock_irqsave(port, &irqflags); 839 840 if (rs485->flags & SER_RS485_ENABLED) { 840 841 efcr |= SC16IS7XX_EFCR_AUTO_RS485_BIT; 841 842 842 843 if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 843 844 efcr |= SC16IS7XX_EFCR_RTS_INVERT_BIT; 844 845 } 845 - spin_unlock_irqrestore(&port->lock, irqflags); 846 + uart_port_unlock_irqrestore(port, irqflags); 846 847 847 848 sc16is7xx_port_update(port, SC16IS7XX_EFCR_REG, mask, efcr); 848 849 } ··· 853 854 struct sc16is7xx_one_config config; 854 855 unsigned long irqflags; 855 856 856 - spin_lock_irqsave(&one->port.lock, irqflags); 857 + uart_port_lock_irqsave(&one->port, &irqflags); 857 858 config = one->config; 858 859 memset(&one->config, 0, sizeof(one->config)); 859 - spin_unlock_irqrestore(&one->port.lock, irqflags); 860 + uart_port_unlock_irqrestore(&one->port, irqflags); 860 861 861 862 if (config.flags & SC16IS7XX_RECONF_MD) { 862 863 u8 mcr = 0; ··· 962 963 * value set in MCR register. Stop reading data from RX FIFO so the 963 964 * AutoRTS feature will de-activate RTS output. 964 965 */ 965 - spin_lock_irqsave(&port->lock, flags); 966 + uart_port_lock_irqsave(port, &flags); 966 967 sc16is7xx_ier_clear(port, SC16IS7XX_IER_RDI_BIT); 967 - spin_unlock_irqrestore(&port->lock, flags); 968 + uart_port_unlock_irqrestore(port, flags); 968 969 } 969 970 970 971 static void sc16is7xx_unthrottle(struct uart_port *port) 971 972 { 972 973 unsigned long flags; 973 974 974 - spin_lock_irqsave(&port->lock, flags); 975 + uart_port_lock_irqsave(port, &flags); 975 976 sc16is7xx_ier_set(port, SC16IS7XX_IER_RDI_BIT); 976 - spin_unlock_irqrestore(&port->lock, flags); 977 + uart_port_unlock_irqrestore(port, flags); 977 978 } 978 979 979 980 static unsigned int sc16is7xx_tx_empty(struct uart_port *port) ··· 1112 1113 /* Setup baudrate generator */ 1113 1114 baud = sc16is7xx_set_baud(port, baud); 1114 1115 1115 - spin_lock_irqsave(&port->lock, flags); 1116 + uart_port_lock_irqsave(port, &flags); 1116 1117 1117 1118 /* Update timeout according to new baud rate */ 1118 1119 uart_update_timeout(port, termios->c_cflag, baud); ··· 1120 1121 if (UART_ENABLE_MS(port, termios->c_cflag)) 1121 1122 sc16is7xx_enable_ms(port); 1122 1123 1123 - spin_unlock_irqrestore(&port->lock, flags); 1124 + uart_port_unlock_irqrestore(port, flags); 1124 1125 } 1125 1126 1126 1127 static int sc16is7xx_config_rs485(struct uart_port *port, struct ktermios *termios, ··· 1207 1208 sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val); 1208 1209 1209 1210 /* Enable modem status polling */ 1210 - spin_lock_irqsave(&port->lock, flags); 1211 + uart_port_lock_irqsave(port, &flags); 1211 1212 sc16is7xx_enable_ms(port); 1212 - spin_unlock_irqrestore(&port->lock, flags); 1213 + uart_port_unlock_irqrestore(port, flags); 1213 1214 1214 1215 return 0; 1215 1216 } ··· 1408 1409 } 1409 1410 #endif 1410 1411 1412 + static void sc16is7xx_setup_irda_ports(struct sc16is7xx_port *s) 1413 + { 1414 + int i; 1415 + int ret; 1416 + int count; 1417 + u32 irda_port[2]; 1418 + struct device *dev = s->p[0].port.dev; 1419 + 1420 + count = device_property_count_u32(dev, "irda-mode-ports"); 1421 + if (count < 0 || count > ARRAY_SIZE(irda_port)) 1422 + return; 1423 + 1424 + ret = device_property_read_u32_array(dev, "irda-mode-ports", 1425 + irda_port, count); 1426 + if (ret) 1427 + return; 1428 + 1429 + for (i = 0; i < count; i++) { 1430 + if (irda_port[i] < s->devtype->nr_uart) 1431 + s->p[irda_port[i]].irda_mode = true; 1432 + } 1433 + } 1434 + 1411 1435 /* 1412 1436 * Configure ports designated to operate as modem control lines. 1413 1437 */ ··· 1613 1591 sc16is7xx_power(&s->p[i].port, 0); 1614 1592 } 1615 1593 1616 - if (dev->of_node) { 1617 - struct property *prop; 1618 - const __be32 *p; 1619 - u32 u; 1620 - 1621 - of_property_for_each_u32(dev->of_node, "irda-mode-ports", 1622 - prop, p, u) 1623 - if (u < devtype->nr_uart) 1624 - s->p[u].irda_mode = true; 1625 - } 1594 + sc16is7xx_setup_irda_ports(s); 1626 1595 1627 1596 ret = sc16is7xx_setup_mctrl_ports(s); 1628 1597 if (ret)

+16 -16

drivers/tty/serial/serial-tegra.c

··· 411 411 divisor = DIV_ROUND_CLOSEST(rate, baud * 16); 412 412 } 413 413 414 - spin_lock_irqsave(&tup->uport.lock, flags); 414 + uart_port_lock_irqsave(&tup->uport, &flags); 415 415 lcr = tup->lcr_shadow; 416 416 lcr |= UART_LCR_DLAB; 417 417 tegra_uart_write(tup, lcr, UART_LCR); ··· 424 424 425 425 /* Dummy read to ensure the write is posted */ 426 426 tegra_uart_read(tup, UART_SCR); 427 - spin_unlock_irqrestore(&tup->uport.lock, flags); 427 + uart_port_unlock_irqrestore(&tup->uport, flags); 428 428 429 429 tup->current_baud = baud; 430 430 ··· 522 522 dmaengine_tx_status(tup->tx_dma_chan, tup->tx_cookie, &state); 523 523 count = tup->tx_bytes_requested - state.residue; 524 524 async_tx_ack(tup->tx_dma_desc); 525 - spin_lock_irqsave(&tup->uport.lock, flags); 525 + uart_port_lock_irqsave(&tup->uport, &flags); 526 526 uart_xmit_advance(&tup->uport, count); 527 527 tup->tx_in_progress = 0; 528 528 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 529 529 uart_write_wakeup(&tup->uport); 530 530 tegra_uart_start_next_tx(tup); 531 - spin_unlock_irqrestore(&tup->uport.lock, flags); 531 + uart_port_unlock_irqrestore(&tup->uport, flags); 532 532 } 533 533 534 534 static int tegra_uart_start_tx_dma(struct tegra_uart_port *tup, ··· 598 598 unsigned int ret = 0; 599 599 unsigned long flags; 600 600 601 - spin_lock_irqsave(&u->lock, flags); 601 + uart_port_lock_irqsave(u, &flags); 602 602 if (!tup->tx_in_progress) { 603 603 unsigned long lsr = tegra_uart_read(tup, UART_LSR); 604 604 if ((lsr & TX_EMPTY_STATUS) == TX_EMPTY_STATUS) 605 605 ret = TIOCSER_TEMT; 606 606 } 607 - spin_unlock_irqrestore(&u->lock, flags); 607 + uart_port_unlock_irqrestore(u, flags); 608 608 return ret; 609 609 } 610 610 ··· 727 727 struct dma_tx_state state; 728 728 enum dma_status status; 729 729 730 - spin_lock_irqsave(&u->lock, flags); 730 + uart_port_lock_irqsave(u, &flags); 731 731 732 732 status = dmaengine_tx_status(tup->rx_dma_chan, tup->rx_cookie, &state); 733 733 ··· 749 749 set_rts(tup, true); 750 750 751 751 done: 752 - spin_unlock_irqrestore(&u->lock, flags); 752 + uart_port_unlock_irqrestore(u, flags); 753 753 } 754 754 755 755 static void tegra_uart_terminate_rx_dma(struct tegra_uart_port *tup) ··· 836 836 bool is_rx_int = false; 837 837 unsigned long flags; 838 838 839 - spin_lock_irqsave(&u->lock, flags); 839 + uart_port_lock_irqsave(u, &flags); 840 840 while (1) { 841 841 iir = tegra_uart_read(tup, UART_IIR); 842 842 if (iir & UART_IIR_NO_INT) { ··· 852 852 } else if (is_rx_start) { 853 853 tegra_uart_start_rx_dma(tup); 854 854 } 855 - spin_unlock_irqrestore(&u->lock, flags); 855 + uart_port_unlock_irqrestore(u, flags); 856 856 return IRQ_HANDLED; 857 857 } 858 858 ··· 969 969 } 970 970 } 971 971 972 - spin_lock_irqsave(&tup->uport.lock, flags); 972 + uart_port_lock_irqsave(&tup->uport, &flags); 973 973 /* Reset the Rx and Tx FIFOs */ 974 974 tegra_uart_fifo_reset(tup, UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR); 975 975 tup->current_baud = 0; 976 - spin_unlock_irqrestore(&tup->uport.lock, flags); 976 + uart_port_unlock_irqrestore(&tup->uport, flags); 977 977 978 978 tup->rx_in_progress = 0; 979 979 tup->tx_in_progress = 0; ··· 1292 1292 int ret; 1293 1293 1294 1294 max_divider *= 16; 1295 - spin_lock_irqsave(&u->lock, flags); 1295 + uart_port_lock_irqsave(u, &flags); 1296 1296 1297 1297 /* Changing configuration, it is safe to stop any rx now */ 1298 1298 if (tup->rts_active) ··· 1341 1341 baud = uart_get_baud_rate(u, termios, oldtermios, 1342 1342 parent_clk_rate/max_divider, 1343 1343 parent_clk_rate/16); 1344 - spin_unlock_irqrestore(&u->lock, flags); 1344 + uart_port_unlock_irqrestore(u, flags); 1345 1345 ret = tegra_set_baudrate(tup, baud); 1346 1346 if (ret < 0) { 1347 1347 dev_err(tup->uport.dev, "Failed to set baud rate\n"); ··· 1349 1349 } 1350 1350 if (tty_termios_baud_rate(termios)) 1351 1351 tty_termios_encode_baud_rate(termios, baud, baud); 1352 - spin_lock_irqsave(&u->lock, flags); 1352 + uart_port_lock_irqsave(u, &flags); 1353 1353 1354 1354 /* Flow control */ 1355 1355 if (termios->c_cflag & CRTSCTS) { ··· 1382 1382 if (termios->c_iflag & IGNBRK) 1383 1383 tup->uport.ignore_status_mask |= UART_LSR_BI; 1384 1384 1385 - spin_unlock_irqrestore(&u->lock, flags); 1385 + uart_port_unlock_irqrestore(u, flags); 1386 1386 } 1387 1387 1388 1388 static const char *tegra_uart_type(struct uart_port *u)

+63 -68

drivers/tty/serial/serial_core.c

··· 79 79 ({ \ 80 80 struct uart_port *__uport = uart_port_ref(state); \ 81 81 if (__uport) \ 82 - spin_lock_irqsave(&__uport->lock, flags); \ 82 + uart_port_lock_irqsave(__uport, &flags); \ 83 83 __uport; \ 84 84 }) 85 85 ··· 87 87 ({ \ 88 88 struct uart_port *__uport = uport; \ 89 89 if (__uport) { \ 90 - spin_unlock_irqrestore(&__uport->lock, flags); \ 90 + uart_port_unlock_irqrestore(__uport, flags); \ 91 91 uart_port_deref(__uport); \ 92 92 } \ 93 93 }) ··· 146 146 147 147 /* Increment the runtime PM usage count for the active check below */ 148 148 err = pm_runtime_get(&port_dev->dev); 149 - if (err < 0) { 149 + if (err < 0 && err != -EINPROGRESS) { 150 150 pm_runtime_put_noidle(&port_dev->dev); 151 151 return; 152 152 } ··· 179 179 unsigned long flags; 180 180 unsigned int old; 181 181 182 - spin_lock_irqsave(&port->lock, flags); 182 + uart_port_lock_irqsave(port, &flags); 183 183 old = port->mctrl; 184 184 port->mctrl = (old & ~clear) | set; 185 185 if (old != port->mctrl && !(port->rs485.flags & SER_RS485_ENABLED)) 186 186 port->ops->set_mctrl(port, port->mctrl); 187 - spin_unlock_irqrestore(&port->lock, flags); 187 + uart_port_unlock_irqrestore(port, flags); 188 188 } 189 189 190 190 #define uart_set_mctrl(port, set) uart_update_mctrl(port, set, 0) ··· 219 219 /* 220 220 * Set modem status enables based on termios cflag 221 221 */ 222 - spin_lock_irq(&uport->lock); 222 + uart_port_lock_irq(uport); 223 223 if (termios->c_cflag & CRTSCTS) 224 224 uport->status |= UPSTAT_CTS_ENABLE; 225 225 else ··· 240 240 else 241 241 __uart_start(state); 242 242 } 243 - spin_unlock_irq(&uport->lock); 243 + uart_port_unlock_irq(uport); 244 244 } 245 245 246 246 /* ··· 431 431 * baud. 432 432 * 433 433 * If the new baud rate is invalid, try the @old termios setting. If it's still 434 - * invalid, we try 9600 baud. 434 + * invalid, we try 9600 baud. If that is also invalid 0 is returned. 435 435 * 436 436 * The @termios structure is updated to reflect the baud rate we're actually 437 437 * going to be using. Don't do this for the case where B0 is requested ("hang ··· 515 515 max - 1, max - 1); 516 516 } 517 517 } 518 - /* Should never happen */ 519 - WARN_ON(1); 520 518 return 0; 521 519 } 522 520 EXPORT_SYMBOL(uart_get_baud_rate); ··· 700 702 if (port->ops->send_xchar) 701 703 port->ops->send_xchar(port, ch); 702 704 else { 703 - spin_lock_irqsave(&port->lock, flags); 705 + uart_port_lock_irqsave(port, &flags); 704 706 port->x_char = ch; 705 707 if (ch) 706 708 port->ops->start_tx(port); 707 - spin_unlock_irqrestore(&port->lock, flags); 709 + uart_port_unlock_irqrestore(port, flags); 708 710 } 709 711 uart_port_deref(port); 710 712 } ··· 772 774 struct uart_state *state = container_of(port, struct uart_state, port); 773 775 struct uart_port *uport; 774 776 int ret = -ENODEV; 777 + 778 + /* Initialize structure in case we error out later to prevent any stack info leakage. */ 779 + *retinfo = (struct serial_struct){}; 775 780 776 781 /* 777 782 * Ensure the state we copy is consistent and no hardware changes ··· 1086 1085 1087 1086 if (!tty_io_error(tty)) { 1088 1087 result = uport->mctrl; 1089 - spin_lock_irq(&uport->lock); 1088 + uart_port_lock_irq(uport); 1090 1089 result |= uport->ops->get_mctrl(uport); 1091 - spin_unlock_irq(&uport->lock); 1090 + uart_port_unlock_irq(uport); 1092 1091 } 1093 1092 out: 1094 1093 mutex_unlock(&port->mutex); ··· 1224 1223 uport = uart_port_ref(state); 1225 1224 if (!uport) 1226 1225 return -EIO; 1227 - spin_lock_irq(&uport->lock); 1226 + uart_port_lock_irq(uport); 1228 1227 memcpy(&cprev, &uport->icount, sizeof(struct uart_icount)); 1229 1228 uart_enable_ms(uport); 1230 - spin_unlock_irq(&uport->lock); 1229 + uart_port_unlock_irq(uport); 1231 1230 1232 1231 add_wait_queue(&port->delta_msr_wait, &wait); 1233 1232 for (;;) { 1234 - spin_lock_irq(&uport->lock); 1233 + uart_port_lock_irq(uport); 1235 1234 memcpy(&cnow, &uport->icount, sizeof(struct uart_icount)); 1236 - spin_unlock_irq(&uport->lock); 1235 + uart_port_unlock_irq(uport); 1237 1236 1238 1237 set_current_state(TASK_INTERRUPTIBLE); 1239 1238 ··· 1278 1277 uport = uart_port_ref(state); 1279 1278 if (!uport) 1280 1279 return -EIO; 1281 - spin_lock_irq(&uport->lock); 1280 + uart_port_lock_irq(uport); 1282 1281 memcpy(&cnow, &uport->icount, sizeof(struct uart_icount)); 1283 - spin_unlock_irq(&uport->lock); 1282 + uart_port_unlock_irq(uport); 1284 1283 uart_port_deref(uport); 1285 1284 1286 1285 icount->cts = cnow.cts; ··· 1414 1413 uart_sanitize_serial_rs485(port, rs485); 1415 1414 uart_set_rs485_termination(port, rs485); 1416 1415 1417 - spin_lock_irqsave(&port->lock, flags); 1416 + uart_port_lock_irqsave(port, &flags); 1418 1417 ret = port->rs485_config(port, NULL, rs485); 1419 - spin_unlock_irqrestore(&port->lock, flags); 1418 + uart_port_unlock_irqrestore(port, flags); 1420 1419 if (ret) 1421 1420 memset(rs485, 0, sizeof(*rs485)); 1422 1421 ··· 1429 1428 unsigned long flags; 1430 1429 struct serial_rs485 aux; 1431 1430 1432 - spin_lock_irqsave(&port->lock, flags); 1431 + uart_port_lock_irqsave(port, &flags); 1433 1432 aux = port->rs485; 1434 - spin_unlock_irqrestore(&port->lock, flags); 1433 + uart_port_unlock_irqrestore(port, flags); 1435 1434 1436 1435 if (copy_to_user(rs485, &aux, sizeof(aux))) 1437 1436 return -EFAULT; ··· 1458 1457 uart_sanitize_serial_rs485(port, &rs485); 1459 1458 uart_set_rs485_termination(port, &rs485); 1460 1459 1461 - spin_lock_irqsave(&port->lock, flags); 1460 + uart_port_lock_irqsave(port, &flags); 1462 1461 ret = port->rs485_config(port, &tty->termios, &rs485); 1463 1462 if (!ret) { 1464 1463 port->rs485 = rs485; ··· 1467 1466 if (!(rs485.flags & SER_RS485_ENABLED)) 1468 1467 port->ops->set_mctrl(port, port->mctrl); 1469 1468 } 1470 - spin_unlock_irqrestore(&port->lock, flags); 1469 + uart_port_unlock_irqrestore(port, flags); 1471 1470 if (ret) 1472 1471 return ret; 1473 1472 ··· 1486 1485 if (!port->iso7816_config) 1487 1486 return -ENOTTY; 1488 1487 1489 - spin_lock_irqsave(&port->lock, flags); 1488 + uart_port_lock_irqsave(port, &flags); 1490 1489 aux = port->iso7816; 1491 - spin_unlock_irqrestore(&port->lock, flags); 1490 + uart_port_unlock_irqrestore(port, flags); 1492 1491 1493 1492 if (copy_to_user(iso7816, &aux, sizeof(aux))) 1494 1493 return -EFAULT; ··· 1517 1516 if (iso7816.reserved[i]) 1518 1517 return -EINVAL; 1519 1518 1520 - spin_lock_irqsave(&port->lock, flags); 1519 + uart_port_lock_irqsave(port, &flags); 1521 1520 ret = port->iso7816_config(port, &iso7816); 1522 - spin_unlock_irqrestore(&port->lock, flags); 1521 + uart_port_unlock_irqrestore(port, flags); 1523 1522 if (ret) 1524 1523 return ret; 1525 1524 ··· 1736 1735 if (WARN(!uport, "detached port still initialized!\n")) 1737 1736 return; 1738 1737 1739 - spin_lock_irq(&uport->lock); 1738 + uart_port_lock_irq(uport); 1740 1739 uport->ops->stop_rx(uport); 1741 - spin_unlock_irq(&uport->lock); 1740 + uart_port_unlock_irq(uport); 1742 1741 1743 1742 uart_port_shutdown(port); 1744 1743 ··· 1752 1751 /* 1753 1752 * Free the transmit buffer. 1754 1753 */ 1755 - spin_lock_irq(&uport->lock); 1754 + uart_port_lock_irq(uport); 1756 1755 buf = state->xmit.buf; 1757 1756 state->xmit.buf = NULL; 1758 - spin_unlock_irq(&uport->lock); 1757 + uart_port_unlock_irq(uport); 1759 1758 1760 1759 free_page((unsigned long)buf); 1761 1760 ··· 1898 1897 */ 1899 1898 if (WARN_ON(!uport)) 1900 1899 return true; 1901 - spin_lock_irq(&uport->lock); 1900 + uart_port_lock_irq(uport); 1902 1901 uart_enable_ms(uport); 1903 1902 mctrl = uport->ops->get_mctrl(uport); 1904 - spin_unlock_irq(&uport->lock); 1903 + uart_port_unlock_irq(uport); 1905 1904 uart_port_deref(uport); 1906 1905 1907 1906 return mctrl & TIOCM_CAR; ··· 2018 2017 pm_state = state->pm_state; 2019 2018 if (pm_state != UART_PM_STATE_ON) 2020 2019 uart_change_pm(state, UART_PM_STATE_ON); 2021 - spin_lock_irq(&uport->lock); 2020 + uart_port_lock_irq(uport); 2022 2021 status = uport->ops->get_mctrl(uport); 2023 - spin_unlock_irq(&uport->lock); 2022 + uart_port_unlock_irq(uport); 2024 2023 if (pm_state != UART_PM_STATE_ON) 2025 2024 uart_change_pm(state, pm_state); 2026 2025 ··· 2359 2358 */ 2360 2359 if (!console_suspend_enabled && uart_console(uport)) { 2361 2360 if (uport->ops->start_rx) { 2362 - spin_lock_irq(&uport->lock); 2361 + uart_port_lock_irq(uport); 2363 2362 uport->ops->stop_rx(uport); 2364 - spin_unlock_irq(&uport->lock); 2363 + uart_port_unlock_irq(uport); 2365 2364 } 2366 2365 goto unlock; 2367 2366 } ··· 2376 2375 tty_port_set_suspended(port, true); 2377 2376 tty_port_set_initialized(port, false); 2378 2377 2379 - spin_lock_irq(&uport->lock); 2378 + uart_port_lock_irq(uport); 2380 2379 ops->stop_tx(uport); 2381 2380 if (!(uport->rs485.flags & SER_RS485_ENABLED)) 2382 2381 ops->set_mctrl(uport, 0); ··· 2384 2383 mctrl = uport->mctrl; 2385 2384 uport->mctrl = 0; 2386 2385 ops->stop_rx(uport); 2387 - spin_unlock_irq(&uport->lock); 2386 + uart_port_unlock_irq(uport); 2388 2387 2389 2388 /* 2390 2389 * Wait for the transmitter to empty. ··· 2456 2455 uart_change_pm(state, UART_PM_STATE_ON); 2457 2456 uport->ops->set_termios(uport, &termios, NULL); 2458 2457 if (!console_suspend_enabled && uport->ops->start_rx) { 2459 - spin_lock_irq(&uport->lock); 2458 + uart_port_lock_irq(uport); 2460 2459 uport->ops->start_rx(uport); 2461 - spin_unlock_irq(&uport->lock); 2460 + uart_port_unlock_irq(uport); 2462 2461 } 2463 2462 if (console_suspend_enabled) 2464 2463 console_start(uport->cons); ··· 2469 2468 int ret; 2470 2469 2471 2470 uart_change_pm(state, UART_PM_STATE_ON); 2472 - spin_lock_irq(&uport->lock); 2471 + uart_port_lock_irq(uport); 2473 2472 if (!(uport->rs485.flags & SER_RS485_ENABLED)) 2474 2473 ops->set_mctrl(uport, 0); 2475 - spin_unlock_irq(&uport->lock); 2474 + uart_port_unlock_irq(uport); 2476 2475 if (console_suspend_enabled || !uart_console(uport)) { 2477 2476 /* Protected by port mutex for now */ 2478 2477 struct tty_struct *tty = port->tty; ··· 2482 2481 if (tty) 2483 2482 uart_change_line_settings(tty, state, NULL); 2484 2483 uart_rs485_config(uport); 2485 - spin_lock_irq(&uport->lock); 2484 + uart_port_lock_irq(uport); 2486 2485 if (!(uport->rs485.flags & SER_RS485_ENABLED)) 2487 2486 ops->set_mctrl(uport, uport->mctrl); 2488 2487 ops->start_tx(uport); 2489 - spin_unlock_irq(&uport->lock); 2488 + uart_port_unlock_irq(uport); 2490 2489 tty_port_set_initialized(port, true); 2491 2490 } else { 2492 2491 /* ··· 2589 2588 * keep the DTR setting that is set in uart_set_options() 2590 2589 * We probably don't need a spinlock around this, but 2591 2590 */ 2592 - spin_lock_irqsave(&port->lock, flags); 2591 + uart_port_lock_irqsave(port, &flags); 2593 2592 port->mctrl &= TIOCM_DTR; 2594 2593 if (!(port->rs485.flags & SER_RS485_ENABLED)) 2595 2594 port->ops->set_mctrl(port, port->mctrl); 2596 - spin_unlock_irqrestore(&port->lock, flags); 2595 + uart_port_unlock_irqrestore(port, flags); 2597 2596 2598 2597 uart_rs485_config(port); 2599 2598 ··· 3565 3564 { 3566 3565 struct serial_rs485 *rs485conf = &port->rs485; 3567 3566 struct device *dev = port->dev; 3567 + enum gpiod_flags dflags; 3568 + struct gpio_desc *desc; 3568 3569 u32 rs485_delay[2]; 3569 3570 int ret; 3570 - int rx_during_tx_gpio_flag; 3571 3571 3572 3572 ret = device_property_read_u32_array(dev, "rs485-rts-delay", 3573 3573 rs485_delay, 2); ··· 3607 3605 * bus participants enable it, no communication is possible at all. 3608 3606 * Works fine for short cables and users may enable for longer cables. 3609 3607 */ 3610 - port->rs485_term_gpio = devm_gpiod_get_optional(dev, "rs485-term", 3611 - GPIOD_OUT_LOW); 3612 - if (IS_ERR(port->rs485_term_gpio)) { 3613 - ret = PTR_ERR(port->rs485_term_gpio); 3614 - port->rs485_term_gpio = NULL; 3615 - return dev_err_probe(dev, ret, "Cannot get rs485-term-gpios\n"); 3616 - } 3608 + desc = devm_gpiod_get_optional(dev, "rs485-term", GPIOD_OUT_LOW); 3609 + if (IS_ERR(desc)) 3610 + return dev_err_probe(dev, PTR_ERR(desc), "Cannot get rs485-term-gpios\n"); 3611 + port->rs485_term_gpio = desc; 3617 3612 if (port->rs485_term_gpio) 3618 3613 port->rs485_supported.flags |= SER_RS485_TERMINATE_BUS; 3619 3614 3620 - rx_during_tx_gpio_flag = (rs485conf->flags & SER_RS485_RX_DURING_TX) ? 3621 - GPIOD_OUT_HIGH : GPIOD_OUT_LOW; 3622 - port->rs485_rx_during_tx_gpio = devm_gpiod_get_optional(dev, 3623 - "rs485-rx-during-tx", 3624 - rx_during_tx_gpio_flag); 3625 - if (IS_ERR(port->rs485_rx_during_tx_gpio)) { 3626 - ret = PTR_ERR(port->rs485_rx_during_tx_gpio); 3627 - port->rs485_rx_during_tx_gpio = NULL; 3628 - return dev_err_probe(dev, ret, "Cannot get rs485-rx-during-tx-gpios\n"); 3629 - } 3615 + dflags = (rs485conf->flags & SER_RS485_RX_DURING_TX) ? 3616 + GPIOD_OUT_HIGH : GPIOD_OUT_LOW; 3617 + desc = devm_gpiod_get_optional(dev, "rs485-rx-during-tx", dflags); 3618 + if (IS_ERR(desc)) 3619 + return dev_err_probe(dev, PTR_ERR(desc), "Cannot get rs485-rx-during-tx-gpios\n"); 3620 + port->rs485_rx_during_tx_gpio = desc; 3630 3621 3631 3622 return 0; 3632 3623 }

+2 -2

drivers/tty/serial/serial_mctrl_gpio.c

··· 184 184 185 185 mctrl_gpio_get(gpios, &mctrl); 186 186 187 - spin_lock_irqsave(&port->lock, flags); 187 + uart_port_lock_irqsave(port, &flags); 188 188 189 189 mctrl_diff = mctrl ^ gpios->mctrl_prev; 190 190 gpios->mctrl_prev = mctrl; ··· 205 205 wake_up_interruptible(&port->state->port.delta_msr_wait); 206 206 } 207 207 208 - spin_unlock_irqrestore(&port->lock, flags); 208 + uart_port_unlock_irqrestore(port, flags); 209 209 210 210 return IRQ_HANDLED; 211 211 }

+2 -2

drivers/tty/serial/serial_port.c

··· 35 35 goto out; 36 36 37 37 /* Flush any pending TX for the port */ 38 - spin_lock_irqsave(&port->lock, flags); 38 + uart_port_lock_irqsave(port, &flags); 39 39 if (__serial_port_busy(port)) 40 40 port->ops->start_tx(port); 41 - spin_unlock_irqrestore(&port->lock, flags); 41 + uart_port_unlock_irqrestore(port, flags); 42 42 43 43 out: 44 44 pm_runtime_mark_last_busy(dev);

+13 -13

drivers/tty/serial/serial_txx9.c

··· 335 335 unsigned int status; 336 336 337 337 while (1) { 338 - spin_lock(&up->lock); 338 + uart_port_lock(up); 339 339 status = sio_in(up, TXX9_SIDISR); 340 340 if (!(sio_in(up, TXX9_SIDICR) & TXX9_SIDICR_TIE)) 341 341 status &= ~TXX9_SIDISR_TDIS; 342 342 if (!(status & (TXX9_SIDISR_TDIS | TXX9_SIDISR_RDIS | 343 343 TXX9_SIDISR_TOUT))) { 344 - spin_unlock(&up->lock); 344 + uart_port_unlock(up); 345 345 break; 346 346 } 347 347 ··· 353 353 sio_mask(up, TXX9_SIDISR, 354 354 TXX9_SIDISR_TDIS | TXX9_SIDISR_RDIS | 355 355 TXX9_SIDISR_TOUT); 356 - spin_unlock(&up->lock); 356 + uart_port_unlock(up); 357 357 358 358 if (pass_counter++ > PASS_LIMIT) 359 359 break; ··· 367 367 unsigned long flags; 368 368 unsigned int ret; 369 369 370 - spin_lock_irqsave(&up->lock, flags); 370 + uart_port_lock_irqsave(up, &flags); 371 371 ret = (sio_in(up, TXX9_SICISR) & TXX9_SICISR_TXALS) ? TIOCSER_TEMT : 0; 372 - spin_unlock_irqrestore(&up->lock, flags); 372 + uart_port_unlock_irqrestore(up, flags); 373 373 374 374 return ret; 375 375 } ··· 399 399 { 400 400 unsigned long flags; 401 401 402 - spin_lock_irqsave(&up->lock, flags); 402 + uart_port_lock_irqsave(up, &flags); 403 403 if (break_state == -1) 404 404 sio_set(up, TXX9_SIFLCR, TXX9_SIFLCR_TBRK); 405 405 else 406 406 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_TBRK); 407 - spin_unlock_irqrestore(&up->lock, flags); 407 + uart_port_unlock_irqrestore(up, flags); 408 408 } 409 409 410 410 #if defined(CONFIG_SERIAL_TXX9_CONSOLE) || defined(CONFIG_CONSOLE_POLL) ··· 517 517 /* 518 518 * Now, initialize the UART 519 519 */ 520 - spin_lock_irqsave(&up->lock, flags); 520 + uart_port_lock_irqsave(up, &flags); 521 521 serial_txx9_set_mctrl(up, up->mctrl); 522 - spin_unlock_irqrestore(&up->lock, flags); 522 + uart_port_unlock_irqrestore(up, flags); 523 523 524 524 /* Enable RX/TX */ 525 525 sio_mask(up, TXX9_SIFLCR, TXX9_SIFLCR_RSDE | TXX9_SIFLCR_TSDE); ··· 541 541 */ 542 542 sio_out(up, TXX9_SIDICR, 0); /* disable all intrs */ 543 543 544 - spin_lock_irqsave(&up->lock, flags); 544 + uart_port_lock_irqsave(up, &flags); 545 545 serial_txx9_set_mctrl(up, up->mctrl); 546 - spin_unlock_irqrestore(&up->lock, flags); 546 + uart_port_unlock_irqrestore(up, flags); 547 547 548 548 /* 549 549 * Disable break condition ··· 625 625 * Ok, we're now changing the port state. Do it with 626 626 * interrupts disabled. 627 627 */ 628 - spin_lock_irqsave(&up->lock, flags); 628 + uart_port_lock_irqsave(up, &flags); 629 629 630 630 /* 631 631 * Update the per-port timeout. ··· 676 676 sio_out(up, TXX9_SIFCR, fcr); 677 677 678 678 serial_txx9_set_mctrl(up, up->mctrl); 679 - spin_unlock_irqrestore(&up->lock, flags); 679 + uart_port_unlock_irqrestore(up, flags); 680 680 } 681 681 682 682 static void

+34 -34

drivers/tty/serial/sh-sci.c

··· 1205 1205 1206 1206 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line); 1207 1207 1208 - spin_lock_irqsave(&port->lock, flags); 1208 + uart_port_lock_irqsave(port, &flags); 1209 1209 1210 1210 uart_xmit_advance(port, s->tx_dma_len); 1211 1211 ··· 1229 1229 } 1230 1230 } 1231 1231 1232 - spin_unlock_irqrestore(&port->lock, flags); 1232 + uart_port_unlock_irqrestore(port, flags); 1233 1233 } 1234 1234 1235 1235 /* Locking: called with port lock held */ ··· 1320 1320 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line, 1321 1321 s->active_rx); 1322 1322 1323 - spin_lock_irqsave(&port->lock, flags); 1323 + uart_port_lock_irqsave(port, &flags); 1324 1324 1325 1325 active = sci_dma_rx_find_active(s); 1326 1326 if (active >= 0) ··· 1347 1347 1348 1348 dma_async_issue_pending(chan); 1349 1349 1350 - spin_unlock_irqrestore(&port->lock, flags); 1350 + uart_port_unlock_irqrestore(port, flags); 1351 1351 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n", 1352 1352 __func__, s->cookie_rx[active], active, s->active_rx); 1353 1353 return; 1354 1354 1355 1355 fail: 1356 - spin_unlock_irqrestore(&port->lock, flags); 1356 + uart_port_unlock_irqrestore(port, flags); 1357 1357 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n"); 1358 1358 /* Switch to PIO */ 1359 - spin_lock_irqsave(&port->lock, flags); 1359 + uart_port_lock_irqsave(port, &flags); 1360 1360 dmaengine_terminate_async(chan); 1361 1361 sci_dma_rx_chan_invalidate(s); 1362 1362 sci_dma_rx_reenable_irq(s); 1363 - spin_unlock_irqrestore(&port->lock, flags); 1363 + uart_port_unlock_irqrestore(port, flags); 1364 1364 } 1365 1365 1366 1366 static void sci_dma_tx_release(struct sci_port *s) ··· 1409 1409 fail: 1410 1410 /* Switch to PIO */ 1411 1411 if (!port_lock_held) 1412 - spin_lock_irqsave(&port->lock, flags); 1412 + uart_port_lock_irqsave(port, &flags); 1413 1413 if (i) 1414 1414 dmaengine_terminate_async(chan); 1415 1415 sci_dma_rx_chan_invalidate(s); 1416 1416 sci_start_rx(port); 1417 1417 if (!port_lock_held) 1418 - spin_unlock_irqrestore(&port->lock, flags); 1418 + uart_port_unlock_irqrestore(port, flags); 1419 1419 return -EAGAIN; 1420 1420 } 1421 1421 ··· 1437 1437 * transmit till the end, and then the rest. Take the port lock to get a 1438 1438 * consistent xmit buffer state. 1439 1439 */ 1440 - spin_lock_irq(&port->lock); 1440 + uart_port_lock_irq(port); 1441 1441 head = xmit->head; 1442 1442 tail = xmit->tail; 1443 1443 buf = s->tx_dma_addr + tail; 1444 1444 s->tx_dma_len = CIRC_CNT_TO_END(head, tail, UART_XMIT_SIZE); 1445 1445 if (!s->tx_dma_len) { 1446 1446 /* Transmit buffer has been flushed */ 1447 - spin_unlock_irq(&port->lock); 1447 + uart_port_unlock_irq(port); 1448 1448 return; 1449 1449 } 1450 1450 ··· 1452 1452 DMA_MEM_TO_DEV, 1453 1453 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1454 1454 if (!desc) { 1455 - spin_unlock_irq(&port->lock); 1455 + uart_port_unlock_irq(port); 1456 1456 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n"); 1457 1457 goto switch_to_pio; 1458 1458 } ··· 1464 1464 desc->callback_param = s; 1465 1465 s->cookie_tx = dmaengine_submit(desc); 1466 1466 if (dma_submit_error(s->cookie_tx)) { 1467 - spin_unlock_irq(&port->lock); 1467 + uart_port_unlock_irq(port); 1468 1468 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n"); 1469 1469 goto switch_to_pio; 1470 1470 } 1471 1471 1472 - spin_unlock_irq(&port->lock); 1472 + uart_port_unlock_irq(port); 1473 1473 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", 1474 1474 __func__, xmit->buf, tail, head, s->cookie_tx); 1475 1475 ··· 1477 1477 return; 1478 1478 1479 1479 switch_to_pio: 1480 - spin_lock_irqsave(&port->lock, flags); 1480 + uart_port_lock_irqsave(port, &flags); 1481 1481 s->chan_tx = NULL; 1482 1482 sci_start_tx(port); 1483 - spin_unlock_irqrestore(&port->lock, flags); 1483 + uart_port_unlock_irqrestore(port, flags); 1484 1484 return; 1485 1485 } 1486 1486 ··· 1497 1497 1498 1498 dev_dbg(port->dev, "DMA Rx timed out\n"); 1499 1499 1500 - spin_lock_irqsave(&port->lock, flags); 1500 + uart_port_lock_irqsave(port, &flags); 1501 1501 1502 1502 active = sci_dma_rx_find_active(s); 1503 1503 if (active < 0) { 1504 - spin_unlock_irqrestore(&port->lock, flags); 1504 + uart_port_unlock_irqrestore(port, flags); 1505 1505 return HRTIMER_NORESTART; 1506 1506 } 1507 1507 1508 1508 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1509 1509 if (status == DMA_COMPLETE) { 1510 - spin_unlock_irqrestore(&port->lock, flags); 1510 + uart_port_unlock_irqrestore(port, flags); 1511 1511 dev_dbg(port->dev, "Cookie %d #%d has already completed\n", 1512 1512 s->active_rx, active); 1513 1513 ··· 1525 1525 */ 1526 1526 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state); 1527 1527 if (status == DMA_COMPLETE) { 1528 - spin_unlock_irqrestore(&port->lock, flags); 1528 + uart_port_unlock_irqrestore(port, flags); 1529 1529 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped"); 1530 1530 return HRTIMER_NORESTART; 1531 1531 } ··· 1546 1546 1547 1547 sci_dma_rx_reenable_irq(s); 1548 1548 1549 - spin_unlock_irqrestore(&port->lock, flags); 1549 + uart_port_unlock_irqrestore(port, flags); 1550 1550 1551 1551 return HRTIMER_NORESTART; 1552 1552 } ··· 1770 1770 struct uart_port *port = ptr; 1771 1771 unsigned long flags; 1772 1772 1773 - spin_lock_irqsave(&port->lock, flags); 1773 + uart_port_lock_irqsave(port, &flags); 1774 1774 sci_transmit_chars(port); 1775 - spin_unlock_irqrestore(&port->lock, flags); 1775 + uart_port_unlock_irqrestore(port, flags); 1776 1776 1777 1777 return IRQ_HANDLED; 1778 1778 } ··· 1786 1786 if (port->type != PORT_SCI) 1787 1787 return sci_tx_interrupt(irq, ptr); 1788 1788 1789 - spin_lock_irqsave(&port->lock, flags); 1789 + uart_port_lock_irqsave(port, &flags); 1790 1790 ctrl = serial_port_in(port, SCSCR); 1791 1791 ctrl &= ~(SCSCR_TE | SCSCR_TEIE); 1792 1792 serial_port_out(port, SCSCR, ctrl); 1793 - spin_unlock_irqrestore(&port->lock, flags); 1793 + uart_port_unlock_irqrestore(port, flags); 1794 1794 1795 1795 return IRQ_HANDLED; 1796 1796 } ··· 2187 2187 return; 2188 2188 } 2189 2189 2190 - spin_lock_irqsave(&port->lock, flags); 2190 + uart_port_lock_irqsave(port, &flags); 2191 2191 scsptr = serial_port_in(port, SCSPTR); 2192 2192 scscr = serial_port_in(port, SCSCR); 2193 2193 ··· 2201 2201 2202 2202 serial_port_out(port, SCSPTR, scsptr); 2203 2203 serial_port_out(port, SCSCR, scscr); 2204 - spin_unlock_irqrestore(&port->lock, flags); 2204 + uart_port_unlock_irqrestore(port, flags); 2205 2205 } 2206 2206 2207 2207 static int sci_startup(struct uart_port *port) ··· 2233 2233 s->autorts = false; 2234 2234 mctrl_gpio_disable_ms(to_sci_port(port)->gpios); 2235 2235 2236 - spin_lock_irqsave(&port->lock, flags); 2236 + uart_port_lock_irqsave(port, &flags); 2237 2237 sci_stop_rx(port); 2238 2238 sci_stop_tx(port); 2239 2239 /* ··· 2243 2243 scr = serial_port_in(port, SCSCR); 2244 2244 serial_port_out(port, SCSCR, scr & 2245 2245 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot)); 2246 - spin_unlock_irqrestore(&port->lock, flags); 2246 + uart_port_unlock_irqrestore(port, flags); 2247 2247 2248 2248 #ifdef CONFIG_SERIAL_SH_SCI_DMA 2249 2249 if (s->chan_rx_saved) { ··· 2545 2545 serial_port_out(port, SCCKS, sccks); 2546 2546 } 2547 2547 2548 - spin_lock_irqsave(&port->lock, flags); 2548 + uart_port_lock_irqsave(port, &flags); 2549 2549 2550 2550 sci_reset(port); 2551 2551 ··· 2667 2667 if ((termios->c_cflag & CREAD) != 0) 2668 2668 sci_start_rx(port); 2669 2669 2670 - spin_unlock_irqrestore(&port->lock, flags); 2670 + uart_port_unlock_irqrestore(port, flags); 2671 2671 2672 2672 sci_port_disable(s); 2673 2673 ··· 3052 3052 if (port->sysrq) 3053 3053 locked = 0; 3054 3054 else if (oops_in_progress) 3055 - locked = spin_trylock_irqsave(&port->lock, flags); 3055 + locked = uart_port_trylock_irqsave(port, &flags); 3056 3056 else 3057 - spin_lock_irqsave(&port->lock, flags); 3057 + uart_port_lock_irqsave(port, &flags); 3058 3058 3059 3059 /* first save SCSCR then disable interrupts, keep clock source */ 3060 3060 ctrl = serial_port_in(port, SCSCR); ··· 3074 3074 serial_port_out(port, SCSCR, ctrl); 3075 3075 3076 3076 if (locked) 3077 - spin_unlock_irqrestore(&port->lock, flags); 3077 + uart_port_unlock_irqrestore(port, flags); 3078 3078 } 3079 3079 3080 3080 static int serial_console_setup(struct console *co, char *options)

+8 -8

drivers/tty/serial/sifive.c

··· 521 521 struct sifive_serial_port *ssp = dev_id; 522 522 u32 ip; 523 523 524 - spin_lock(&ssp->port.lock); 524 + uart_port_lock(&ssp->port); 525 525 526 526 ip = __ssp_readl(ssp, SIFIVE_SERIAL_IP_OFFS); 527 527 if (!ip) { 528 - spin_unlock(&ssp->port.lock); 528 + uart_port_unlock(&ssp->port); 529 529 return IRQ_NONE; 530 530 } 531 531 ··· 534 534 if (ip & SIFIVE_SERIAL_IP_TXWM_MASK) 535 535 __ssp_transmit_chars(ssp); 536 536 537 - spin_unlock(&ssp->port.lock); 537 + uart_port_unlock(&ssp->port); 538 538 539 539 return IRQ_HANDLED; 540 540 } ··· 653 653 ssp->port.uartclk / 16); 654 654 __ssp_update_baud_rate(ssp, rate); 655 655 656 - spin_lock_irqsave(&ssp->port.lock, flags); 656 + uart_port_lock_irqsave(&ssp->port, &flags); 657 657 658 658 /* Update the per-port timeout */ 659 659 uart_update_timeout(port, termios->c_cflag, rate); ··· 670 670 if (v != old_v) 671 671 __ssp_writel(v, SIFIVE_SERIAL_RXCTRL_OFFS, ssp); 672 672 673 - spin_unlock_irqrestore(&ssp->port.lock, flags); 673 + uart_port_unlock_irqrestore(&ssp->port, flags); 674 674 } 675 675 676 676 static void sifive_serial_release_port(struct uart_port *port) ··· 795 795 if (ssp->port.sysrq) 796 796 locked = 0; 797 797 else if (oops_in_progress) 798 - locked = spin_trylock(&ssp->port.lock); 798 + locked = uart_port_trylock(&ssp->port); 799 799 else 800 - spin_lock(&ssp->port.lock); 800 + uart_port_lock(&ssp->port); 801 801 802 802 ier = __ssp_readl(ssp, SIFIVE_SERIAL_IE_OFFS); 803 803 __ssp_writel(0, SIFIVE_SERIAL_IE_OFFS, ssp); ··· 807 807 __ssp_writel(ier, SIFIVE_SERIAL_IE_OFFS, ssp); 808 808 809 809 if (locked) 810 - spin_unlock(&ssp->port.lock); 810 + uart_port_unlock(&ssp->port); 811 811 local_irq_restore(flags); 812 812 } 813 813

+15 -15

drivers/tty/serial/sprd_serial.c

··· 247 247 struct circ_buf *xmit = &port->state->xmit; 248 248 unsigned long flags; 249 249 250 - spin_lock_irqsave(&port->lock, flags); 250 + uart_port_lock_irqsave(port, &flags); 251 251 dma_unmap_single(port->dev, sp->tx_dma.phys_addr, 252 252 sp->tx_dma.trans_len, DMA_TO_DEVICE); 253 253 ··· 260 260 sprd_tx_dma_config(port)) 261 261 sp->tx_dma.trans_len = 0; 262 262 263 - spin_unlock_irqrestore(&port->lock, flags); 263 + uart_port_unlock_irqrestore(port, flags); 264 264 } 265 265 266 266 static int sprd_uart_dma_submit(struct uart_port *port, ··· 429 429 enum dma_status status; 430 430 unsigned long flags; 431 431 432 - spin_lock_irqsave(&port->lock, flags); 432 + uart_port_lock_irqsave(port, &flags); 433 433 434 434 status = dmaengine_tx_status(sp->rx_dma.chn, 435 435 sp->rx_dma.cookie, &state); 436 436 if (status != DMA_COMPLETE) { 437 437 sprd_stop_rx(port); 438 - spin_unlock_irqrestore(&port->lock, flags); 438 + uart_port_unlock_irqrestore(port, flags); 439 439 return; 440 440 } 441 441 ··· 449 449 if (sprd_start_dma_rx(port)) 450 450 sprd_stop_rx(port); 451 451 452 - spin_unlock_irqrestore(&port->lock, flags); 452 + uart_port_unlock_irqrestore(port, flags); 453 453 } 454 454 455 455 static int sprd_start_dma_rx(struct uart_port *port) ··· 638 638 struct uart_port *port = dev_id; 639 639 unsigned int ims; 640 640 641 - spin_lock(&port->lock); 641 + uart_port_lock(port); 642 642 643 643 ims = serial_in(port, SPRD_IMSR); 644 644 645 645 if (!ims) { 646 - spin_unlock(&port->lock); 646 + uart_port_unlock(port); 647 647 return IRQ_NONE; 648 648 } 649 649 ··· 660 660 if (ims & SPRD_IMSR_TX_FIFO_EMPTY) 661 661 sprd_tx(port); 662 662 663 - spin_unlock(&port->lock); 663 + uart_port_unlock(port); 664 664 665 665 return IRQ_HANDLED; 666 666 } ··· 727 727 serial_out(port, SPRD_CTL1, fc); 728 728 729 729 /* enable interrupt */ 730 - spin_lock_irqsave(&port->lock, flags); 730 + uart_port_lock_irqsave(port, &flags); 731 731 ien = serial_in(port, SPRD_IEN); 732 732 ien |= SPRD_IEN_BREAK_DETECT | SPRD_IEN_TIMEOUT; 733 733 if (!sp->rx_dma.enable) 734 734 ien |= SPRD_IEN_RX_FULL; 735 735 serial_out(port, SPRD_IEN, ien); 736 - spin_unlock_irqrestore(&port->lock, flags); 736 + uart_port_unlock_irqrestore(port, flags); 737 737 738 738 return 0; 739 739 } ··· 793 793 lcr |= SPRD_LCR_EVEN_PAR; 794 794 } 795 795 796 - spin_lock_irqsave(&port->lock, flags); 796 + uart_port_lock_irqsave(port, &flags); 797 797 798 798 /* update the per-port timeout */ 799 799 uart_update_timeout(port, termios->c_cflag, baud); ··· 837 837 fc |= RX_TOUT_THLD_DEF | RX_HFC_THLD_DEF; 838 838 serial_out(port, SPRD_CTL1, fc); 839 839 840 - spin_unlock_irqrestore(&port->lock, flags); 840 + uart_port_unlock_irqrestore(port, flags); 841 841 842 842 /* Don't rewrite B0 */ 843 843 if (tty_termios_baud_rate(termios)) ··· 974 974 if (port->sysrq) 975 975 locked = 0; 976 976 else if (oops_in_progress) 977 - locked = spin_trylock_irqsave(&port->lock, flags); 977 + locked = uart_port_trylock_irqsave(port, &flags); 978 978 else 979 - spin_lock_irqsave(&port->lock, flags); 979 + uart_port_lock_irqsave(port, &flags); 980 980 981 981 uart_console_write(port, s, count, sprd_console_putchar); 982 982 ··· 984 984 wait_for_xmitr(port); 985 985 986 986 if (locked) 987 - spin_unlock_irqrestore(&port->lock, flags); 987 + uart_port_unlock_irqrestore(port, flags); 988 988 } 989 989 990 990 static int sprd_console_setup(struct console *co, char *options)

+9 -9

drivers/tty/serial/st-asc.c

··· 319 319 struct uart_port *port = ptr; 320 320 u32 status; 321 321 322 - spin_lock(&port->lock); 322 + uart_port_lock(port); 323 323 324 324 status = asc_in(port, ASC_STA); 325 325 ··· 334 334 asc_transmit_chars(port); 335 335 } 336 336 337 - spin_unlock(&port->lock); 337 + uart_port_unlock(port); 338 338 339 339 return IRQ_HANDLED; 340 340 } ··· 452 452 * we can come to turning it off. Note this is not called with 453 453 * the port spinlock held. 454 454 */ 455 - spin_lock_irqsave(&port->lock, flags); 455 + uart_port_lock_irqsave(port, &flags); 456 456 ctl = asc_in(port, ASC_CTL) & ~ASC_CTL_RUN; 457 457 asc_out(port, ASC_CTL, ctl); 458 - spin_unlock_irqrestore(&port->lock, flags); 458 + uart_port_unlock_irqrestore(port, flags); 459 459 clk_disable_unprepare(ascport->clk); 460 460 break; 461 461 } ··· 480 480 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); 481 481 cflag = termios->c_cflag; 482 482 483 - spin_lock_irqsave(&port->lock, flags); 483 + uart_port_lock_irqsave(port, &flags); 484 484 485 485 /* read control register */ 486 486 ctrl_val = asc_in(port, ASC_CTL); ··· 594 594 /* write final value and enable port */ 595 595 asc_out(port, ASC_CTL, (ctrl_val | ASC_CTL_RUN)); 596 596 597 - spin_unlock_irqrestore(&port->lock, flags); 597 + uart_port_unlock_irqrestore(port, flags); 598 598 } 599 599 600 600 static const char *asc_type(struct uart_port *port) ··· 849 849 if (port->sysrq) 850 850 locked = 0; /* asc_interrupt has already claimed the lock */ 851 851 else if (oops_in_progress) 852 - locked = spin_trylock_irqsave(&port->lock, flags); 852 + locked = uart_port_trylock_irqsave(port, &flags); 853 853 else 854 - spin_lock_irqsave(&port->lock, flags); 854 + uart_port_lock_irqsave(port, &flags); 855 855 856 856 /* 857 857 * Disable interrupts so we don't get the IRQ line bouncing ··· 869 869 asc_out(port, ASC_INTEN, intenable); 870 870 871 871 if (locked) 872 - spin_unlock_irqrestore(&port->lock, flags); 872 + uart_port_unlock_irqrestore(port, flags); 873 873 } 874 874 875 875 static int asc_console_setup(struct console *co, char *options)

+31 -20

drivers/tty/serial/stm32-usart.c

··· 537 537 unsigned int size; 538 538 unsigned long flags; 539 539 540 - spin_lock_irqsave(&port->lock, flags); 540 + uart_port_lock_irqsave(port, &flags); 541 541 size = stm32_usart_receive_chars(port, false); 542 542 uart_unlock_and_check_sysrq_irqrestore(port, flags); 543 543 if (size) ··· 643 643 stm32_usart_tx_dma_terminate(stm32port); 644 644 645 645 /* Let's see if we have pending data to send */ 646 - spin_lock_irqsave(&port->lock, flags); 646 + uart_port_lock_irqsave(port, &flags); 647 647 stm32_usart_transmit_chars(port); 648 - spin_unlock_irqrestore(&port->lock, flags); 648 + uart_port_unlock_irqrestore(port, flags); 649 649 } 650 650 651 651 static void stm32_usart_tx_interrupt_enable(struct uart_port *port) ··· 889 889 if (!stm32_port->throttled) { 890 890 if (((sr & USART_SR_RXNE) && !stm32_usart_rx_dma_started(stm32_port)) || 891 891 ((sr & USART_SR_ERR_MASK) && stm32_usart_rx_dma_started(stm32_port))) { 892 - spin_lock(&port->lock); 892 + uart_port_lock(port); 893 893 size = stm32_usart_receive_chars(port, false); 894 894 uart_unlock_and_check_sysrq(port); 895 895 if (size) ··· 898 898 } 899 899 900 900 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) { 901 - spin_lock(&port->lock); 901 + uart_port_lock(port); 902 902 stm32_usart_transmit_chars(port); 903 - spin_unlock(&port->lock); 903 + uart_port_unlock(port); 904 904 } 905 905 906 906 /* Receiver timeout irq for DMA RX */ 907 907 if (stm32_usart_rx_dma_started(stm32_port) && !stm32_port->throttled) { 908 - spin_lock(&port->lock); 908 + uart_port_lock(port); 909 909 size = stm32_usart_receive_chars(port, false); 910 910 uart_unlock_and_check_sysrq(port); 911 911 if (size) ··· 993 993 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 994 994 unsigned long flags; 995 995 996 - spin_lock_irqsave(&port->lock, flags); 996 + uart_port_lock_irqsave(port, &flags); 997 997 998 998 /* 999 999 * Pause DMA transfer, so the RX data gets queued into the FIFO. ··· 1006 1006 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); 1007 1007 1008 1008 stm32_port->throttled = true; 1009 - spin_unlock_irqrestore(&port->lock, flags); 1009 + uart_port_unlock_irqrestore(port, flags); 1010 1010 } 1011 1011 1012 1012 /* Unthrottle the remote, the input buffer can now accept data. */ ··· 1016 1016 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1017 1017 unsigned long flags; 1018 1018 1019 - spin_lock_irqsave(&port->lock, flags); 1019 + uart_port_lock_irqsave(port, &flags); 1020 1020 stm32_usart_set_bits(port, ofs->cr1, stm32_port->cr1_irq); 1021 1021 if (stm32_port->cr3_irq) 1022 1022 stm32_usart_set_bits(port, ofs->cr3, stm32_port->cr3_irq); ··· 1030 1030 if (stm32_port->rx_ch) 1031 1031 stm32_usart_rx_dma_start_or_resume(port); 1032 1032 1033 - spin_unlock_irqrestore(&port->lock, flags); 1033 + uart_port_unlock_irqrestore(port, flags); 1034 1034 } 1035 1035 1036 1036 /* Receive stop */ ··· 1047 1047 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); 1048 1048 } 1049 1049 1050 - /* Handle breaks - ignored by us */ 1051 1050 static void stm32_usart_break_ctl(struct uart_port *port, int break_state) 1052 1051 { 1052 + struct stm32_port *stm32_port = to_stm32_port(port); 1053 + const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; 1054 + unsigned long flags; 1055 + 1056 + spin_lock_irqsave(&port->lock, flags); 1057 + 1058 + if (break_state) 1059 + stm32_usart_set_bits(port, ofs->rqr, USART_RQR_SBKRQ); 1060 + else 1061 + stm32_usart_clr_bits(port, ofs->rqr, USART_RQR_SBKRQ); 1062 + 1063 + spin_unlock_irqrestore(&port->lock, flags); 1053 1064 } 1054 1065 1055 1066 static int stm32_usart_startup(struct uart_port *port) ··· 1169 1158 1170 1159 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8); 1171 1160 1172 - spin_lock_irqsave(&port->lock, flags); 1161 + uart_port_lock_irqsave(port, &flags); 1173 1162 1174 1163 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, 1175 1164 isr, ··· 1360 1349 writel_relaxed(cr1, port->membase + ofs->cr1); 1361 1350 1362 1351 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 1363 - spin_unlock_irqrestore(&port->lock, flags); 1352 + uart_port_unlock_irqrestore(port, flags); 1364 1353 1365 1354 /* Handle modem control interrupts */ 1366 1355 if (UART_ENABLE_MS(port, termios->c_cflag)) ··· 1410 1399 pm_runtime_get_sync(port->dev); 1411 1400 break; 1412 1401 case UART_PM_STATE_OFF: 1413 - spin_lock_irqsave(&port->lock, flags); 1402 + uart_port_lock_irqsave(port, &flags); 1414 1403 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); 1415 - spin_unlock_irqrestore(&port->lock, flags); 1404 + uart_port_unlock_irqrestore(port, flags); 1416 1405 pm_runtime_put_sync(port->dev); 1417 1406 break; 1418 1407 } ··· 1895 1884 int locked = 1; 1896 1885 1897 1886 if (oops_in_progress) 1898 - locked = spin_trylock_irqsave(&port->lock, flags); 1887 + locked = uart_port_trylock_irqsave(port, &flags); 1899 1888 else 1900 - spin_lock_irqsave(&port->lock, flags); 1889 + uart_port_lock_irqsave(port, &flags); 1901 1890 1902 1891 /* Save and disable interrupts, enable the transmitter */ 1903 1892 old_cr1 = readl_relaxed(port->membase + ofs->cr1); ··· 1911 1900 writel_relaxed(old_cr1, port->membase + ofs->cr1); 1912 1901 1913 1902 if (locked) 1914 - spin_unlock_irqrestore(&port->lock, flags); 1903 + uart_port_unlock_irqrestore(port, flags); 1915 1904 } 1916 1905 1917 1906 static int stm32_usart_console_setup(struct console *co, char *options) ··· 2046 2035 * low-power mode. 2047 2036 */ 2048 2037 if (stm32_port->rx_ch) { 2049 - spin_lock_irqsave(&port->lock, flags); 2038 + uart_port_lock_irqsave(port, &flags); 2050 2039 /* Poll data from DMA RX buffer if any */ 2051 2040 if (!stm32_usart_rx_dma_pause(stm32_port)) 2052 2041 size += stm32_usart_receive_chars(port, true);

+14 -14

drivers/tty/serial/sunhv.c

··· 217 217 struct tty_port *tport; 218 218 unsigned long flags; 219 219 220 - spin_lock_irqsave(&port->lock, flags); 220 + uart_port_lock_irqsave(port, &flags); 221 221 tport = receive_chars(port); 222 222 transmit_chars(port); 223 - spin_unlock_irqrestore(&port->lock, flags); 223 + uart_port_unlock_irqrestore(port, flags); 224 224 225 225 if (tport) 226 226 tty_flip_buffer_push(tport); ··· 271 271 if (ch == __DISABLED_CHAR) 272 272 return; 273 273 274 - spin_lock_irqsave(&port->lock, flags); 274 + uart_port_lock_irqsave(port, &flags); 275 275 276 276 while (limit-- > 0) { 277 277 long status = sun4v_con_putchar(ch); ··· 280 280 udelay(1); 281 281 } 282 282 283 - spin_unlock_irqrestore(&port->lock, flags); 283 + uart_port_unlock_irqrestore(port, flags); 284 284 } 285 285 286 286 /* port->lock held by caller. */ ··· 295 295 unsigned long flags; 296 296 int limit = 10000; 297 297 298 - spin_lock_irqsave(&port->lock, flags); 298 + uart_port_lock_irqsave(port, &flags); 299 299 300 300 while (limit-- > 0) { 301 301 long status = sun4v_con_putchar(CON_BREAK); ··· 304 304 udelay(1); 305 305 } 306 306 307 - spin_unlock_irqrestore(&port->lock, flags); 307 + uart_port_unlock_irqrestore(port, flags); 308 308 } 309 309 } 310 310 ··· 328 328 unsigned int iflag, cflag; 329 329 unsigned long flags; 330 330 331 - spin_lock_irqsave(&port->lock, flags); 331 + uart_port_lock_irqsave(port, &flags); 332 332 333 333 iflag = termios->c_iflag; 334 334 cflag = termios->c_cflag; ··· 343 343 uart_update_timeout(port, cflag, 344 344 (port->uartclk / (16 * quot))); 345 345 346 - spin_unlock_irqrestore(&port->lock, flags); 346 + uart_port_unlock_irqrestore(port, flags); 347 347 } 348 348 349 349 static const char *sunhv_type(struct uart_port *port) ··· 437 437 int locked = 1; 438 438 439 439 if (port->sysrq || oops_in_progress) 440 - locked = spin_trylock_irqsave(&port->lock, flags); 440 + locked = uart_port_trylock_irqsave(port, &flags); 441 441 else 442 - spin_lock_irqsave(&port->lock, flags); 442 + uart_port_lock_irqsave(port, &flags); 443 443 444 444 while (n > 0) { 445 445 unsigned long ra = __pa(con_write_page); ··· 470 470 } 471 471 472 472 if (locked) 473 - spin_unlock_irqrestore(&port->lock, flags); 473 + uart_port_unlock_irqrestore(port, flags); 474 474 } 475 475 476 476 static inline void sunhv_console_putchar(struct uart_port *port, char c) ··· 492 492 int i, locked = 1; 493 493 494 494 if (port->sysrq || oops_in_progress) 495 - locked = spin_trylock_irqsave(&port->lock, flags); 495 + locked = uart_port_trylock_irqsave(port, &flags); 496 496 else 497 - spin_lock_irqsave(&port->lock, flags); 497 + uart_port_lock_irqsave(port, &flags); 498 498 499 499 for (i = 0; i < n; i++) { 500 500 if (*s == '\n') ··· 503 503 } 504 504 505 505 if (locked) 506 - spin_unlock_irqrestore(&port->lock, flags); 506 + uart_port_unlock_irqrestore(port, flags); 507 507 } 508 508 509 509 static struct console sunhv_console = {

+13 -13

drivers/tty/serial/sunplus-uart.c

··· 184 184 unsigned long flags; 185 185 unsigned int lcr; 186 186 187 - spin_lock_irqsave(&port->lock, flags); 187 + uart_port_lock_irqsave(port, &flags); 188 188 189 189 lcr = readl(port->membase + SUP_UART_LCR); 190 190 ··· 195 195 196 196 writel(lcr, port->membase + SUP_UART_LCR); 197 197 198 - spin_unlock_irqrestore(&port->lock, flags); 198 + uart_port_unlock_irqrestore(port, flags); 199 199 } 200 200 201 201 static void transmit_chars(struct uart_port *port) ··· 277 277 struct uart_port *port = args; 278 278 unsigned int isc; 279 279 280 - spin_lock(&port->lock); 280 + uart_port_lock(port); 281 281 282 282 isc = readl(port->membase + SUP_UART_ISC); 283 283 ··· 287 287 if (isc & SUP_UART_ISC_TX) 288 288 transmit_chars(port); 289 289 290 - spin_unlock(&port->lock); 290 + uart_port_unlock(port); 291 291 292 292 return IRQ_HANDLED; 293 293 } ··· 302 302 if (ret) 303 303 return ret; 304 304 305 - spin_lock_irqsave(&port->lock, flags); 305 + uart_port_lock_irqsave(port, &flags); 306 306 /* isc define Bit[7:4] int setting, Bit[3:0] int status 307 307 * isc register will clean Bit[3:0] int status after read 308 308 * only do a write to Bit[7:4] int setting 309 309 */ 310 310 isc |= SUP_UART_ISC_RXM; 311 311 writel(isc, port->membase + SUP_UART_ISC); 312 - spin_unlock_irqrestore(&port->lock, flags); 312 + uart_port_unlock_irqrestore(port, flags); 313 313 314 314 return 0; 315 315 } ··· 318 318 { 319 319 unsigned long flags; 320 320 321 - spin_lock_irqsave(&port->lock, flags); 321 + uart_port_lock_irqsave(port, &flags); 322 322 /* isc define Bit[7:4] int setting, Bit[3:0] int status 323 323 * isc register will clean Bit[3:0] int status after read 324 324 * only do a write to Bit[7:4] int setting 325 325 */ 326 326 writel(0, port->membase + SUP_UART_ISC); /* disable all interrupt */ 327 - spin_unlock_irqrestore(&port->lock, flags); 327 + uart_port_unlock_irqrestore(port, flags); 328 328 329 329 free_irq(port->irq, port); 330 330 } ··· 372 372 lcr |= UART_LCR_EPAR; 373 373 } 374 374 375 - spin_lock_irqsave(&port->lock, flags); 375 + uart_port_lock_irqsave(port, &flags); 376 376 377 377 uart_update_timeout(port, termios->c_cflag, baud); 378 378 ··· 407 407 writel(div_l, port->membase + SUP_UART_DIV_L); 408 408 writel(lcr, port->membase + SUP_UART_LCR); 409 409 410 - spin_unlock_irqrestore(&port->lock, flags); 410 + uart_port_unlock_irqrestore(port, flags); 411 411 } 412 412 413 413 static void sunplus_set_ldisc(struct uart_port *port, struct ktermios *termios) ··· 517 517 if (sunplus_console_ports[co->index]->port.sysrq) 518 518 locked = 0; 519 519 else if (oops_in_progress) 520 - locked = spin_trylock(&sunplus_console_ports[co->index]->port.lock); 520 + locked = uart_port_trylock(&sunplus_console_ports[co->index]->port); 521 521 else 522 - spin_lock(&sunplus_console_ports[co->index]->port.lock); 522 + uart_port_lock(&sunplus_console_ports[co->index]->port); 523 523 524 524 uart_console_write(&sunplus_console_ports[co->index]->port, s, count, 525 525 sunplus_uart_console_putchar); 526 526 527 527 if (locked) 528 - spin_unlock(&sunplus_console_ports[co->index]->port.lock); 528 + uart_port_unlock(&sunplus_console_ports[co->index]->port); 529 529 530 530 local_irq_restore(flags); 531 531 }

+17 -17

drivers/tty/serial/sunsab.c

··· 310 310 unsigned long flags; 311 311 unsigned char gis; 312 312 313 - spin_lock_irqsave(&up->port.lock, flags); 313 + uart_port_lock_irqsave(&up->port, &flags); 314 314 315 315 status.stat = 0; 316 316 gis = readb(&up->regs->r.gis) >> up->gis_shift; ··· 331 331 transmit_chars(up, &status); 332 332 } 333 333 334 - spin_unlock_irqrestore(&up->port.lock, flags); 334 + uart_port_unlock_irqrestore(&up->port, flags); 335 335 336 336 if (port) 337 337 tty_flip_buffer_push(port); ··· 473 473 if (ch == __DISABLED_CHAR) 474 474 return; 475 475 476 - spin_lock_irqsave(&up->port.lock, flags); 476 + uart_port_lock_irqsave(&up->port, &flags); 477 477 478 478 sunsab_tec_wait(up); 479 479 writeb(ch, &up->regs->w.tic); 480 480 481 - spin_unlock_irqrestore(&up->port.lock, flags); 481 + uart_port_unlock_irqrestore(&up->port, flags); 482 482 } 483 483 484 484 /* port->lock held by caller. */ ··· 499 499 unsigned long flags; 500 500 unsigned char val; 501 501 502 - spin_lock_irqsave(&up->port.lock, flags); 502 + uart_port_lock_irqsave(&up->port, &flags); 503 503 504 504 val = up->cached_dafo; 505 505 if (break_state) ··· 512 512 if (test_bit(SAB82532_XPR, &up->irqflags)) 513 513 sunsab_tx_idle(up); 514 514 515 - spin_unlock_irqrestore(&up->port.lock, flags); 515 + uart_port_unlock_irqrestore(&up->port, flags); 516 516 } 517 517 518 518 /* port->lock is not held. */ ··· 527 527 if (err) 528 528 return err; 529 529 530 - spin_lock_irqsave(&up->port.lock, flags); 530 + uart_port_lock_irqsave(&up->port, &flags); 531 531 532 532 /* 533 533 * Wait for any commands or immediate characters ··· 582 582 set_bit(SAB82532_ALLS, &up->irqflags); 583 583 set_bit(SAB82532_XPR, &up->irqflags); 584 584 585 - spin_unlock_irqrestore(&up->port.lock, flags); 585 + uart_port_unlock_irqrestore(&up->port, flags); 586 586 587 587 return 0; 588 588 } ··· 594 594 container_of(port, struct uart_sunsab_port, port); 595 595 unsigned long flags; 596 596 597 - spin_lock_irqsave(&up->port.lock, flags); 597 + uart_port_lock_irqsave(&up->port, &flags); 598 598 599 599 /* Disable Interrupts */ 600 600 up->interrupt_mask0 = 0xff; ··· 628 628 writeb(tmp, &up->regs->rw.ccr0); 629 629 #endif 630 630 631 - spin_unlock_irqrestore(&up->port.lock, flags); 631 + uart_port_unlock_irqrestore(&up->port, flags); 632 632 free_irq(up->port.irq, up); 633 633 } 634 634 ··· 779 779 unsigned int baud = uart_get_baud_rate(port, termios, old, 0, 4000000); 780 780 unsigned int quot = uart_get_divisor(port, baud); 781 781 782 - spin_lock_irqsave(&up->port.lock, flags); 782 + uart_port_lock_irqsave(&up->port, &flags); 783 783 sunsab_convert_to_sab(up, termios->c_cflag, termios->c_iflag, baud, quot); 784 - spin_unlock_irqrestore(&up->port.lock, flags); 784 + uart_port_unlock_irqrestore(&up->port, flags); 785 785 } 786 786 787 787 static const char *sunsab_type(struct uart_port *port) ··· 857 857 int locked = 1; 858 858 859 859 if (up->port.sysrq || oops_in_progress) 860 - locked = spin_trylock_irqsave(&up->port.lock, flags); 860 + locked = uart_port_trylock_irqsave(&up->port, &flags); 861 861 else 862 - spin_lock_irqsave(&up->port.lock, flags); 862 + uart_port_lock_irqsave(&up->port, &flags); 863 863 864 864 uart_console_write(&up->port, s, n, sunsab_console_putchar); 865 865 sunsab_tec_wait(up); 866 866 867 867 if (locked) 868 - spin_unlock_irqrestore(&up->port.lock, flags); 868 + uart_port_unlock_irqrestore(&up->port, flags); 869 869 } 870 870 871 871 static int sunsab_console_setup(struct console *con, char *options) ··· 914 914 */ 915 915 sunsab_startup(&up->port); 916 916 917 - spin_lock_irqsave(&up->port.lock, flags); 917 + uart_port_lock_irqsave(&up->port, &flags); 918 918 919 919 /* 920 920 * Finally, enable interrupts ··· 932 932 sunsab_convert_to_sab(up, con->cflag, 0, baud, quot); 933 933 sunsab_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS); 934 934 935 - spin_unlock_irqrestore(&up->port.lock, flags); 935 + uart_port_unlock_irqrestore(&up->port, flags); 936 936 937 937 return 0; 938 938 }

+23 -23

drivers/tty/serial/sunsu.c

··· 212 212 { 213 213 if (up->port.type == PORT_RSA) { 214 214 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) { 215 - spin_lock_irq(&up->port.lock); 215 + uart_port_lock_irq(&up->port); 216 216 __enable_rsa(up); 217 - spin_unlock_irq(&up->port.lock); 217 + uart_port_unlock_irq(&up->port); 218 218 } 219 219 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) 220 220 serial_outp(up, UART_RSA_FRR, 0); ··· 234 234 235 235 if (up->port.type == PORT_RSA && 236 236 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) { 237 - spin_lock_irq(&up->port.lock); 237 + uart_port_lock_irq(&up->port); 238 238 239 239 mode = serial_inp(up, UART_RSA_MSR); 240 240 result = !(mode & UART_RSA_MSR_FIFO); ··· 247 247 248 248 if (result) 249 249 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16; 250 - spin_unlock_irq(&up->port.lock); 250 + uart_port_unlock_irq(&up->port); 251 251 } 252 252 } 253 253 #endif /* CONFIG_SERIAL_8250_RSA */ ··· 311 311 container_of(port, struct uart_sunsu_port, port); 312 312 unsigned long flags; 313 313 314 - spin_lock_irqsave(&up->port.lock, flags); 314 + uart_port_lock_irqsave(&up->port, &flags); 315 315 up->ier |= UART_IER_MSI; 316 316 serial_out(up, UART_IER, up->ier); 317 - spin_unlock_irqrestore(&up->port.lock, flags); 317 + uart_port_unlock_irqrestore(&up->port, flags); 318 318 } 319 319 320 320 static void ··· 456 456 unsigned long flags; 457 457 unsigned char status; 458 458 459 - spin_lock_irqsave(&up->port.lock, flags); 459 + uart_port_lock_irqsave(&up->port, &flags); 460 460 461 461 do { 462 462 status = serial_inp(up, UART_LSR); ··· 470 470 471 471 } while (!(serial_in(up, UART_IIR) & UART_IIR_NO_INT)); 472 472 473 - spin_unlock_irqrestore(&up->port.lock, flags); 473 + uart_port_unlock_irqrestore(&up->port, flags); 474 474 475 475 return IRQ_HANDLED; 476 476 } ··· 545 545 unsigned long flags; 546 546 unsigned int ret; 547 547 548 - spin_lock_irqsave(&up->port.lock, flags); 548 + uart_port_lock_irqsave(&up->port, &flags); 549 549 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; 550 - spin_unlock_irqrestore(&up->port.lock, flags); 550 + uart_port_unlock_irqrestore(&up->port, flags); 551 551 552 552 return ret; 553 553 } ··· 599 599 container_of(port, struct uart_sunsu_port, port); 600 600 unsigned long flags; 601 601 602 - spin_lock_irqsave(&up->port.lock, flags); 602 + uart_port_lock_irqsave(&up->port, &flags); 603 603 if (break_state == -1) 604 604 up->lcr |= UART_LCR_SBC; 605 605 else 606 606 up->lcr &= ~UART_LCR_SBC; 607 607 serial_out(up, UART_LCR, up->lcr); 608 - spin_unlock_irqrestore(&up->port.lock, flags); 608 + uart_port_unlock_irqrestore(&up->port, flags); 609 609 } 610 610 611 611 static int sunsu_startup(struct uart_port *port) ··· 683 683 */ 684 684 serial_outp(up, UART_LCR, UART_LCR_WLEN8); 685 685 686 - spin_lock_irqsave(&up->port.lock, flags); 686 + uart_port_lock_irqsave(&up->port, &flags); 687 687 688 688 up->port.mctrl |= TIOCM_OUT2; 689 689 690 690 sunsu_set_mctrl(&up->port, up->port.mctrl); 691 - spin_unlock_irqrestore(&up->port.lock, flags); 691 + uart_port_unlock_irqrestore(&up->port, flags); 692 692 693 693 /* 694 694 * Finally, enable interrupts. Note: Modem status interrupts ··· 731 731 up->ier = 0; 732 732 serial_outp(up, UART_IER, 0); 733 733 734 - spin_lock_irqsave(&up->port.lock, flags); 734 + uart_port_lock_irqsave(&up->port, &flags); 735 735 if (up->port.flags & UPF_FOURPORT) { 736 736 /* reset interrupts on the AST Fourport board */ 737 737 inb((up->port.iobase & 0xfe0) | 0x1f); ··· 740 740 up->port.mctrl &= ~TIOCM_OUT2; 741 741 742 742 sunsu_set_mctrl(&up->port, up->port.mctrl); 743 - spin_unlock_irqrestore(&up->port.lock, flags); 743 + uart_port_unlock_irqrestore(&up->port, flags); 744 744 745 745 /* 746 746 * Disable break condition and FIFOs ··· 826 826 * Ok, we're now changing the port state. Do it with 827 827 * interrupts disabled. 828 828 */ 829 - spin_lock_irqsave(&up->port.lock, flags); 829 + uart_port_lock_irqsave(&up->port, &flags); 830 830 831 831 /* 832 832 * Update the per-port timeout. ··· 891 891 892 892 up->cflag = cflag; 893 893 894 - spin_unlock_irqrestore(&up->port.lock, flags); 894 + uart_port_unlock_irqrestore(&up->port, flags); 895 895 } 896 896 897 897 static void ··· 1038 1038 up->type_probed = PORT_UNKNOWN; 1039 1039 up->port.iotype = UPIO_MEM; 1040 1040 1041 - spin_lock_irqsave(&up->port.lock, flags); 1041 + uart_port_lock_irqsave(&up->port, &flags); 1042 1042 1043 1043 if (!(up->port.flags & UPF_BUGGY_UART)) { 1044 1044 /* ··· 1173 1173 serial_outp(up, UART_IER, 0); 1174 1174 1175 1175 out: 1176 - spin_unlock_irqrestore(&up->port.lock, flags); 1176 + uart_port_unlock_irqrestore(&up->port, flags); 1177 1177 } 1178 1178 1179 1179 static struct uart_driver sunsu_reg = { ··· 1298 1298 int locked = 1; 1299 1299 1300 1300 if (up->port.sysrq || oops_in_progress) 1301 - locked = spin_trylock_irqsave(&up->port.lock, flags); 1301 + locked = uart_port_trylock_irqsave(&up->port, &flags); 1302 1302 else 1303 - spin_lock_irqsave(&up->port.lock, flags); 1303 + uart_port_lock_irqsave(&up->port, &flags); 1304 1304 1305 1305 /* 1306 1306 * First save the UER then disable the interrupts ··· 1318 1318 serial_out(up, UART_IER, ier); 1319 1319 1320 1320 if (locked) 1321 - spin_unlock_irqrestore(&up->port.lock, flags); 1321 + uart_port_unlock_irqrestore(&up->port, flags); 1322 1322 } 1323 1323 1324 1324 /*

+21 -21

drivers/tty/serial/sunzilog.c

··· 531 531 struct tty_port *port; 532 532 unsigned char r3; 533 533 534 - spin_lock(&up->port.lock); 534 + uart_port_lock(&up->port); 535 535 r3 = read_zsreg(channel, R3); 536 536 537 537 /* Channel A */ ··· 548 548 if (r3 & CHATxIP) 549 549 sunzilog_transmit_chars(up, channel); 550 550 } 551 - spin_unlock(&up->port.lock); 551 + uart_port_unlock(&up->port); 552 552 553 553 if (port) 554 554 tty_flip_buffer_push(port); ··· 557 557 up = up->next; 558 558 channel = ZILOG_CHANNEL_FROM_PORT(&up->port); 559 559 560 - spin_lock(&up->port.lock); 560 + uart_port_lock(&up->port); 561 561 port = NULL; 562 562 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) { 563 563 writeb(RES_H_IUS, &channel->control); ··· 571 571 if (r3 & CHBTxIP) 572 572 sunzilog_transmit_chars(up, channel); 573 573 } 574 - spin_unlock(&up->port.lock); 574 + uart_port_unlock(&up->port); 575 575 576 576 if (port) 577 577 tty_flip_buffer_push(port); ··· 604 604 unsigned char status; 605 605 unsigned int ret; 606 606 607 - spin_lock_irqsave(&port->lock, flags); 607 + uart_port_lock_irqsave(port, &flags); 608 608 609 609 status = sunzilog_read_channel_status(port); 610 610 611 - spin_unlock_irqrestore(&port->lock, flags); 611 + uart_port_unlock_irqrestore(port, flags); 612 612 613 613 if (status & Tx_BUF_EMP) 614 614 ret = TIOCSER_TEMT; ··· 764 764 else 765 765 clear_bits |= SND_BRK; 766 766 767 - spin_lock_irqsave(&port->lock, flags); 767 + uart_port_lock_irqsave(port, &flags); 768 768 769 769 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits; 770 770 if (new_reg != up->curregs[R5]) { ··· 774 774 write_zsreg(channel, R5, up->curregs[R5]); 775 775 } 776 776 777 - spin_unlock_irqrestore(&port->lock, flags); 777 + uart_port_unlock_irqrestore(port, flags); 778 778 } 779 779 780 780 static void __sunzilog_startup(struct uart_sunzilog_port *up) ··· 800 800 if (ZS_IS_CONS(up)) 801 801 return 0; 802 802 803 - spin_lock_irqsave(&port->lock, flags); 803 + uart_port_lock_irqsave(port, &flags); 804 804 __sunzilog_startup(up); 805 - spin_unlock_irqrestore(&port->lock, flags); 805 + uart_port_unlock_irqrestore(port, flags); 806 806 return 0; 807 807 } 808 808 ··· 840 840 if (ZS_IS_CONS(up)) 841 841 return; 842 842 843 - spin_lock_irqsave(&port->lock, flags); 843 + uart_port_lock_irqsave(port, &flags); 844 844 845 845 channel = ZILOG_CHANNEL_FROM_PORT(port); 846 846 ··· 853 853 up->curregs[R5] &= ~SND_BRK; 854 854 sunzilog_maybe_update_regs(up, channel); 855 855 856 - spin_unlock_irqrestore(&port->lock, flags); 856 + uart_port_unlock_irqrestore(port, flags); 857 857 } 858 858 859 859 /* Shared by TTY driver and serial console setup. The port lock is held ··· 945 945 946 946 baud = uart_get_baud_rate(port, termios, old, 1200, 76800); 947 947 948 - spin_lock_irqsave(&up->port.lock, flags); 948 + uart_port_lock_irqsave(&up->port, &flags); 949 949 950 950 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR); 951 951 ··· 962 962 963 963 uart_update_timeout(port, termios->c_cflag, baud); 964 964 965 - spin_unlock_irqrestore(&up->port.lock, flags); 965 + uart_port_unlock_irqrestore(&up->port, flags); 966 966 } 967 967 968 968 static const char *sunzilog_type(struct uart_port *port) ··· 1201 1201 int locked = 1; 1202 1202 1203 1203 if (up->port.sysrq || oops_in_progress) 1204 - locked = spin_trylock_irqsave(&up->port.lock, flags); 1204 + locked = uart_port_trylock_irqsave(&up->port, &flags); 1205 1205 else 1206 - spin_lock_irqsave(&up->port.lock, flags); 1206 + uart_port_lock_irqsave(&up->port, &flags); 1207 1207 1208 1208 uart_console_write(&up->port, s, count, sunzilog_putchar); 1209 1209 udelay(2); 1210 1210 1211 1211 if (locked) 1212 - spin_unlock_irqrestore(&up->port.lock, flags); 1212 + uart_port_unlock_irqrestore(&up->port, flags); 1213 1213 } 1214 1214 1215 1215 static int __init sunzilog_console_setup(struct console *con, char *options) ··· 1244 1244 1245 1245 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR); 1246 1246 1247 - spin_lock_irqsave(&up->port.lock, flags); 1247 + uart_port_lock_irqsave(&up->port, &flags); 1248 1248 1249 1249 up->curregs[R15] |= BRKIE; 1250 1250 sunzilog_convert_to_zs(up, con->cflag, 0, brg); ··· 1252 1252 sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS); 1253 1253 __sunzilog_startup(up); 1254 1254 1255 - spin_unlock_irqrestore(&up->port.lock, flags); 1255 + uart_port_unlock_irqrestore(&up->port, flags); 1256 1256 1257 1257 return 0; 1258 1258 } ··· 1333 1333 1334 1334 channel = ZILOG_CHANNEL_FROM_PORT(&up->port); 1335 1335 1336 - spin_lock_irqsave(&up->port.lock, flags); 1336 + uart_port_lock_irqsave(&up->port, &flags); 1337 1337 if (ZS_IS_CHANNEL_A(up)) { 1338 1338 write_zsreg(channel, R9, FHWRES); 1339 1339 ZSDELAY_LONG(); ··· 1383 1383 write_zsreg(channel, R9, up->curregs[R9]); 1384 1384 } 1385 1385 1386 - spin_unlock_irqrestore(&up->port.lock, flags); 1386 + uart_port_unlock_irqrestore(&up->port, flags); 1387 1387 1388 1388 #ifdef CONFIG_SERIO 1389 1389 if (up->flags & (SUNZILOG_FLAG_CONS_KEYB |

+4 -4

drivers/tty/serial/timbuart.c

··· 174 174 struct timbuart_port *uart = from_tasklet(uart, t, tasklet); 175 175 u32 isr, ier = 0; 176 176 177 - spin_lock(&uart->port.lock); 177 + uart_port_lock(&uart->port); 178 178 179 179 isr = ioread32(uart->port.membase + TIMBUART_ISR); 180 180 dev_dbg(uart->port.dev, "%s ISR: %x\n", __func__, isr); ··· 189 189 190 190 iowrite32(ier, uart->port.membase + TIMBUART_IER); 191 191 192 - spin_unlock(&uart->port.lock); 192 + uart_port_unlock(&uart->port); 193 193 dev_dbg(uart->port.dev, "%s leaving\n", __func__); 194 194 } 195 195 ··· 295 295 tty_termios_copy_hw(termios, old); 296 296 tty_termios_encode_baud_rate(termios, baud, baud); 297 297 298 - spin_lock_irqsave(&port->lock, flags); 298 + uart_port_lock_irqsave(port, &flags); 299 299 iowrite8((u8)bindex, port->membase + TIMBUART_BAUDRATE); 300 300 uart_update_timeout(port, termios->c_cflag, baud); 301 - spin_unlock_irqrestore(&port->lock, flags); 301 + uart_port_unlock_irqrestore(port, flags); 302 302 } 303 303 304 304 static const char *timbuart_type(struct uart_port *port)

+9 -9

drivers/tty/serial/uartlite.c

··· 216 216 unsigned long flags; 217 217 218 218 do { 219 - spin_lock_irqsave(&port->lock, flags); 219 + uart_port_lock_irqsave(port, &flags); 220 220 stat = uart_in32(ULITE_STATUS, port); 221 221 busy = ulite_receive(port, stat); 222 222 busy |= ulite_transmit(port, stat); 223 - spin_unlock_irqrestore(&port->lock, flags); 223 + uart_port_unlock_irqrestore(port, flags); 224 224 n++; 225 225 } while (busy); 226 226 ··· 238 238 unsigned long flags; 239 239 unsigned int ret; 240 240 241 - spin_lock_irqsave(&port->lock, flags); 241 + uart_port_lock_irqsave(port, &flags); 242 242 ret = uart_in32(ULITE_STATUS, port); 243 - spin_unlock_irqrestore(&port->lock, flags); 243 + uart_port_unlock_irqrestore(port, flags); 244 244 245 245 return ret & ULITE_STATUS_TXEMPTY ? TIOCSER_TEMT : 0; 246 246 } ··· 323 323 termios->c_cflag |= pdata->cflags & (PARENB | PARODD | CSIZE); 324 324 tty_termios_encode_baud_rate(termios, pdata->baud, pdata->baud); 325 325 326 - spin_lock_irqsave(&port->lock, flags); 326 + uart_port_lock_irqsave(port, &flags); 327 327 328 328 port->read_status_mask = ULITE_STATUS_RXVALID | ULITE_STATUS_OVERRUN 329 329 | ULITE_STATUS_TXFULL; ··· 346 346 /* update timeout */ 347 347 uart_update_timeout(port, termios->c_cflag, pdata->baud); 348 348 349 - spin_unlock_irqrestore(&port->lock, flags); 349 + uart_port_unlock_irqrestore(port, flags); 350 350 } 351 351 352 352 static const char *ulite_type(struct uart_port *port) ··· 495 495 int locked = 1; 496 496 497 497 if (oops_in_progress) { 498 - locked = spin_trylock_irqsave(&port->lock, flags); 498 + locked = uart_port_trylock_irqsave(port, &flags); 499 499 } else 500 - spin_lock_irqsave(&port->lock, flags); 500 + uart_port_lock_irqsave(port, &flags); 501 501 502 502 /* save and disable interrupt */ 503 503 ier = uart_in32(ULITE_STATUS, port) & ULITE_STATUS_IE; ··· 512 512 uart_out32(ULITE_CONTROL_IE, ULITE_CONTROL, port); 513 513 514 514 if (locked) 515 - spin_unlock_irqrestore(&port->lock, flags); 515 + uart_port_unlock_irqrestore(port, flags); 516 516 } 517 517 518 518 static int ulite_console_setup(struct console *co, char *options)

+2 -2

drivers/tty/serial/ucc_uart.c

··· 931 931 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); 932 932 933 933 /* Do we really need a spinlock here? */ 934 - spin_lock_irqsave(&port->lock, flags); 934 + uart_port_lock_irqsave(port, &flags); 935 935 936 936 /* Update the per-port timeout. */ 937 937 uart_update_timeout(port, termios->c_cflag, baud); ··· 949 949 qe_setbrg(qe_port->us_info.tx_clock, baud, 16); 950 950 } 951 951 952 - spin_unlock_irqrestore(&port->lock, flags); 952 + uart_port_unlock_irqrestore(port, flags); 953 953 } 954 954 955 955 /*

+4 -4

drivers/tty/serial/vt8500_serial.c

··· 227 227 struct uart_port *port = dev_id; 228 228 unsigned long isr; 229 229 230 - spin_lock(&port->lock); 230 + uart_port_lock(port); 231 231 isr = vt8500_read(port, VT8500_URISR); 232 232 233 233 /* Acknowledge active status bits */ ··· 240 240 if (isr & TCTS) 241 241 handle_delta_cts(port); 242 242 243 - spin_unlock(&port->lock); 243 + uart_port_unlock(port); 244 244 245 245 return IRQ_HANDLED; 246 246 } ··· 342 342 unsigned int baud, lcr; 343 343 unsigned int loops = 1000; 344 344 345 - spin_lock_irqsave(&port->lock, flags); 345 + uart_port_lock_irqsave(port, &flags); 346 346 347 347 /* calculate and set baud rate */ 348 348 baud = uart_get_baud_rate(port, termios, old, 900, 921600); ··· 410 410 vt8500_write(&vt8500_port->uart, 0x881, VT8500_URFCR); 411 411 vt8500_write(&vt8500_port->uart, vt8500_port->ier, VT8500_URIER); 412 412 413 - spin_unlock_irqrestore(&port->lock, flags); 413 + uart_port_unlock_irqrestore(port, flags); 414 414 } 415 415 416 416 static const char *vt8500_type(struct uart_port *port)

+29 -29

drivers/tty/serial/xilinx_uartps.c

··· 346 346 struct uart_port *port = (struct uart_port *)dev_id; 347 347 unsigned int isrstatus; 348 348 349 - spin_lock(&port->lock); 349 + uart_port_lock(port); 350 350 351 351 /* Read the interrupt status register to determine which 352 352 * interrupt(s) is/are active and clear them. ··· 369 369 !(readl(port->membase + CDNS_UART_CR) & CDNS_UART_CR_RX_DIS)) 370 370 cdns_uart_handle_rx(dev_id, isrstatus); 371 371 372 - spin_unlock(&port->lock); 372 + uart_port_unlock(port); 373 373 return IRQ_HANDLED; 374 374 } 375 375 ··· 506 506 return NOTIFY_BAD; 507 507 } 508 508 509 - spin_lock_irqsave(&cdns_uart->port->lock, flags); 509 + uart_port_lock_irqsave(cdns_uart->port, &flags); 510 510 511 511 /* Disable the TX and RX to set baud rate */ 512 512 ctrl_reg = readl(port->membase + CDNS_UART_CR); 513 513 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS; 514 514 writel(ctrl_reg, port->membase + CDNS_UART_CR); 515 515 516 - spin_unlock_irqrestore(&cdns_uart->port->lock, flags); 516 + uart_port_unlock_irqrestore(cdns_uart->port, flags); 517 517 518 518 return NOTIFY_OK; 519 519 } ··· 523 523 * frequency. 524 524 */ 525 525 526 - spin_lock_irqsave(&cdns_uart->port->lock, flags); 526 + uart_port_lock_irqsave(cdns_uart->port, &flags); 527 527 528 528 locked = 1; 529 529 port->uartclk = ndata->new_rate; ··· 533 533 fallthrough; 534 534 case ABORT_RATE_CHANGE: 535 535 if (!locked) 536 - spin_lock_irqsave(&cdns_uart->port->lock, flags); 536 + uart_port_lock_irqsave(cdns_uart->port, &flags); 537 537 538 538 /* Set TX/RX Reset */ 539 539 ctrl_reg = readl(port->membase + CDNS_UART_CR); ··· 555 555 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN; 556 556 writel(ctrl_reg, port->membase + CDNS_UART_CR); 557 557 558 - spin_unlock_irqrestore(&cdns_uart->port->lock, flags); 558 + uart_port_unlock_irqrestore(cdns_uart->port, flags); 559 559 560 560 return NOTIFY_OK; 561 561 default: ··· 652 652 unsigned int status; 653 653 unsigned long flags; 654 654 655 - spin_lock_irqsave(&port->lock, flags); 655 + uart_port_lock_irqsave(port, &flags); 656 656 657 657 status = readl(port->membase + CDNS_UART_CR); 658 658 659 659 if (ctl == -1) 660 - writel(CDNS_UART_CR_STARTBRK | status, 660 + writel(CDNS_UART_CR_STARTBRK | (~CDNS_UART_CR_STOPBRK & status), 661 661 port->membase + CDNS_UART_CR); 662 662 else { 663 663 if ((status & CDNS_UART_CR_STOPBRK) == 0) 664 664 writel(CDNS_UART_CR_STOPBRK | status, 665 665 port->membase + CDNS_UART_CR); 666 666 } 667 - spin_unlock_irqrestore(&port->lock, flags); 667 + uart_port_unlock_irqrestore(port, flags); 668 668 } 669 669 670 670 /** ··· 683 683 unsigned long flags; 684 684 unsigned int ctrl_reg, mode_reg; 685 685 686 - spin_lock_irqsave(&port->lock, flags); 686 + uart_port_lock_irqsave(port, &flags); 687 687 688 688 /* Disable the TX and RX to set baud rate */ 689 689 ctrl_reg = readl(port->membase + CDNS_UART_CR); ··· 794 794 cval &= ~CDNS_UART_MODEMCR_FCM; 795 795 writel(cval, port->membase + CDNS_UART_MODEMCR); 796 796 797 - spin_unlock_irqrestore(&port->lock, flags); 797 + uart_port_unlock_irqrestore(port, flags); 798 798 } 799 799 800 800 /** ··· 813 813 814 814 is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT; 815 815 816 - spin_lock_irqsave(&port->lock, flags); 816 + uart_port_lock_irqsave(port, &flags); 817 817 818 818 /* Disable the TX and RX */ 819 819 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS, ··· 861 861 writel(readl(port->membase + CDNS_UART_ISR), 862 862 port->membase + CDNS_UART_ISR); 863 863 864 - spin_unlock_irqrestore(&port->lock, flags); 864 + uart_port_unlock_irqrestore(port, flags); 865 865 866 866 ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port); 867 867 if (ret) { ··· 889 889 int status; 890 890 unsigned long flags; 891 891 892 - spin_lock_irqsave(&port->lock, flags); 892 + uart_port_lock_irqsave(port, &flags); 893 893 894 894 /* Disable interrupts */ 895 895 status = readl(port->membase + CDNS_UART_IMR); ··· 900 900 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS, 901 901 port->membase + CDNS_UART_CR); 902 902 903 - spin_unlock_irqrestore(&port->lock, flags); 903 + uart_port_unlock_irqrestore(port, flags); 904 904 905 905 free_irq(port->irq, port); 906 906 } ··· 1050 1050 int c; 1051 1051 unsigned long flags; 1052 1052 1053 - spin_lock_irqsave(&port->lock, flags); 1053 + uart_port_lock_irqsave(port, &flags); 1054 1054 1055 1055 /* Check if FIFO is empty */ 1056 1056 if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY) ··· 1058 1058 else /* Read a character */ 1059 1059 c = (unsigned char) readl(port->membase + CDNS_UART_FIFO); 1060 1060 1061 - spin_unlock_irqrestore(&port->lock, flags); 1061 + uart_port_unlock_irqrestore(port, flags); 1062 1062 1063 1063 return c; 1064 1064 } ··· 1067 1067 { 1068 1068 unsigned long flags; 1069 1069 1070 - spin_lock_irqsave(&port->lock, flags); 1070 + uart_port_lock_irqsave(port, &flags); 1071 1071 1072 1072 /* Wait until FIFO is empty */ 1073 1073 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY)) ··· 1080 1080 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY)) 1081 1081 cpu_relax(); 1082 1082 1083 - spin_unlock_irqrestore(&port->lock, flags); 1083 + uart_port_unlock_irqrestore(port, flags); 1084 1084 } 1085 1085 #endif 1086 1086 ··· 1232 1232 if (port->sysrq) 1233 1233 locked = 0; 1234 1234 else if (oops_in_progress) 1235 - locked = spin_trylock_irqsave(&port->lock, flags); 1235 + locked = uart_port_trylock_irqsave(port, &flags); 1236 1236 else 1237 - spin_lock_irqsave(&port->lock, flags); 1237 + uart_port_lock_irqsave(port, &flags); 1238 1238 1239 1239 /* save and disable interrupt */ 1240 1240 imr = readl(port->membase + CDNS_UART_IMR); ··· 1257 1257 writel(imr, port->membase + CDNS_UART_IER); 1258 1258 1259 1259 if (locked) 1260 - spin_unlock_irqrestore(&port->lock, flags); 1260 + uart_port_unlock_irqrestore(port, flags); 1261 1261 } 1262 1262 1263 1263 /** ··· 1325 1325 if (console_suspend_enabled && uart_console(port) && may_wake) { 1326 1326 unsigned long flags; 1327 1327 1328 - spin_lock_irqsave(&port->lock, flags); 1328 + uart_port_lock_irqsave(port, &flags); 1329 1329 /* Empty the receive FIFO 1st before making changes */ 1330 1330 while (!(readl(port->membase + CDNS_UART_SR) & 1331 1331 CDNS_UART_SR_RXEMPTY)) ··· 1334 1334 writel(1, port->membase + CDNS_UART_RXWM); 1335 1335 /* disable RX timeout interrups */ 1336 1336 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR); 1337 - spin_unlock_irqrestore(&port->lock, flags); 1337 + uart_port_unlock_irqrestore(port, flags); 1338 1338 } 1339 1339 1340 1340 /* ··· 1372 1372 return ret; 1373 1373 } 1374 1374 1375 - spin_lock_irqsave(&port->lock, flags); 1375 + uart_port_lock_irqsave(port, &flags); 1376 1376 1377 1377 /* Set TX/RX Reset */ 1378 1378 ctrl_reg = readl(port->membase + CDNS_UART_CR); ··· 1392 1392 1393 1393 clk_disable(cdns_uart->uartclk); 1394 1394 clk_disable(cdns_uart->pclk); 1395 - spin_unlock_irqrestore(&port->lock, flags); 1395 + uart_port_unlock_irqrestore(port, flags); 1396 1396 } else { 1397 - spin_lock_irqsave(&port->lock, flags); 1397 + uart_port_lock_irqsave(port, &flags); 1398 1398 /* restore original rx trigger level */ 1399 1399 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM); 1400 1400 /* enable RX timeout interrupt */ 1401 1401 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER); 1402 - spin_unlock_irqrestore(&port->lock, flags); 1402 + uart_port_unlock_irqrestore(port, flags); 1403 1403 } 1404 1404 1405 1405 return uart_resume_port(cdns_uart->cdns_uart_driver, port);

+2 -1

drivers/tty/sysrq.c

··· 262 262 if (in_hardirq()) 263 263 regs = get_irq_regs(); 264 264 265 - pr_info("CPU%d:\n", smp_processor_id()); 265 + pr_info("CPU%d:\n", get_cpu()); 266 266 if (regs) 267 267 show_regs(regs); 268 268 else 269 269 show_stack(NULL, NULL, KERN_INFO); 270 270 271 271 schedule_work(&sysrq_showallcpus); 272 + put_cpu(); 272 273 } 273 274 } 274 275

+9 -4

drivers/tty/tty.h

··· 41 41 }; 42 42 43 43 /* Values for tty->flow_change */ 44 - #define TTY_THROTTLE_SAFE 1 45 - #define TTY_UNTHROTTLE_SAFE 2 44 + enum tty_flow_change { 45 + TTY_FLOW_NO_CHANGE, 46 + TTY_THROTTLE_SAFE, 47 + TTY_UNTHROTTLE_SAFE, 48 + }; 46 49 47 - static inline void __tty_set_flow_change(struct tty_struct *tty, int val) 50 + static inline void __tty_set_flow_change(struct tty_struct *tty, 51 + enum tty_flow_change val) 48 52 { 49 53 tty->flow_change = val; 50 54 } 51 55 52 - static inline void tty_set_flow_change(struct tty_struct *tty, int val) 56 + static inline void tty_set_flow_change(struct tty_struct *tty, 57 + enum tty_flow_change val) 53 58 { 54 59 tty->flow_change = val; 55 60 smp_mb();

+2 -3

drivers/tty/tty_buffer.c

··· 69 69 void tty_buffer_unlock_exclusive(struct tty_port *port) 70 70 { 71 71 struct tty_bufhead *buf = &port->buf; 72 - int restart; 73 - 74 - restart = buf->head->commit != buf->head->read; 72 + bool restart = buf->head->commit != buf->head->read; 75 73 76 74 atomic_dec(&buf->priority); 77 75 mutex_unlock(&buf->lock); 76 + 78 77 if (restart) 79 78 queue_work(system_unbound_wq, &buf->work); 80 79 }

+65 -65

drivers/tty/tty_io.c

··· 159 159 static void release_tty(struct tty_struct *tty, int idx); 160 160 161 161 /** 162 - * free_tty_struct - free a disused tty 162 + * free_tty_struct - free a disused tty 163 163 * @tty: tty struct to free 164 164 * 165 165 * Free the write buffers, tty queue and tty memory itself. ··· 233 233 } 234 234 235 235 /** 236 - * tty_name - return tty naming 236 + * tty_name - return tty naming 237 237 * @tty: tty structure 238 238 * 239 239 * Convert a tty structure into a name. The name reflects the kernel naming ··· 295 295 } 296 296 297 297 /** 298 - * get_tty_driver - find device of a tty 298 + * get_tty_driver - find device of a tty 299 299 * @device: device identifier 300 300 * @index: returns the index of the tty 301 301 * ··· 320 320 } 321 321 322 322 /** 323 - * tty_dev_name_to_number - return dev_t for device name 323 + * tty_dev_name_to_number - return dev_t for device name 324 324 * @name: user space name of device under /dev 325 325 * @number: pointer to dev_t that this function will populate 326 326 * ··· 372 372 #ifdef CONFIG_CONSOLE_POLL 373 373 374 374 /** 375 - * tty_find_polling_driver - find device of a polled tty 375 + * tty_find_polling_driver - find device of a polled tty 376 376 * @name: name string to match 377 377 * @line: pointer to resulting tty line nr 378 378 * ··· 505 505 static struct file *redirect; 506 506 507 507 /** 508 - * tty_wakeup - request more data 508 + * tty_wakeup - request more data 509 509 * @tty: terminal 510 510 * 511 511 * Internal and external helper for wakeups of tty. This function informs the ··· 529 529 EXPORT_SYMBOL_GPL(tty_wakeup); 530 530 531 531 /** 532 - * tty_release_redirect - Release a redirect on a pty if present 532 + * tty_release_redirect - Release a redirect on a pty if present 533 533 * @tty: tty device 534 534 * 535 535 * This is available to the pty code so if the master closes, if the slave is a ··· 550 550 } 551 551 552 552 /** 553 - * __tty_hangup - actual handler for hangup events 553 + * __tty_hangup - actual handler for hangup events 554 554 * @tty: tty device 555 555 * @exit_session: if non-zero, signal all foreground group processes 556 556 * ··· 673 673 } 674 674 675 675 /** 676 - * tty_hangup - trigger a hangup event 676 + * tty_hangup - trigger a hangup event 677 677 * @tty: tty to hangup 678 678 * 679 679 * A carrier loss (virtual or otherwise) has occurred on @tty. Schedule a ··· 687 687 EXPORT_SYMBOL(tty_hangup); 688 688 689 689 /** 690 - * tty_vhangup - process vhangup 690 + * tty_vhangup - process vhangup 691 691 * @tty: tty to hangup 692 692 * 693 693 * The user has asked via system call for the terminal to be hung up. We do ··· 703 703 704 704 705 705 /** 706 - * tty_vhangup_self - process vhangup for own ctty 706 + * tty_vhangup_self - process vhangup for own ctty 707 707 * 708 708 * Perform a vhangup on the current controlling tty 709 709 */ ··· 719 719 } 720 720 721 721 /** 722 - * tty_vhangup_session - hangup session leader exit 722 + * tty_vhangup_session - hangup session leader exit 723 723 * @tty: tty to hangup 724 724 * 725 725 * The session leader is exiting and hanging up its controlling terminal. ··· 735 735 } 736 736 737 737 /** 738 - * tty_hung_up_p - was tty hung up 738 + * tty_hung_up_p - was tty hung up 739 739 * @filp: file pointer of tty 740 740 * 741 741 * Return: true if the tty has been subject to a vhangup or a carrier loss ··· 756 756 } 757 757 758 758 /** 759 - * stop_tty - propagate flow control 759 + * stop_tty - propagate flow control 760 760 * @tty: tty to stop 761 761 * 762 762 * Perform flow control to the driver. May be called on an already stopped ··· 790 790 } 791 791 792 792 /** 793 - * start_tty - propagate flow control 793 + * start_tty - propagate flow control 794 794 * @tty: tty to start 795 795 * 796 796 * Start a tty that has been stopped if at all possible. If @tty was previously ··· 902 902 903 903 904 904 /** 905 - * tty_read - read method for tty device files 905 + * tty_read - read method for tty device files 906 906 * @iocb: kernel I/O control block 907 907 * @to: destination for the data read 908 908 * ··· 1095 1095 } 1096 1096 1097 1097 /** 1098 - * tty_write - write method for tty device file 1098 + * tty_write - write method for tty device file 1099 1099 * @iocb: kernel I/O control block 1100 1100 * @from: iov_iter with data to write 1101 1101 * ··· 1137 1137 } 1138 1138 1139 1139 /** 1140 - * tty_send_xchar - send priority character 1140 + * tty_send_xchar - send priority character 1141 1141 * @tty: the tty to send to 1142 1142 * @ch: xchar to send 1143 1143 * ··· 1171 1171 } 1172 1172 1173 1173 /** 1174 - * pty_line_name - generate name for a pty 1174 + * pty_line_name - generate name for a pty 1175 1175 * @driver: the tty driver in use 1176 1176 * @index: the minor number 1177 1177 * @p: output buffer of at least 6 bytes ··· 1192 1192 } 1193 1193 1194 1194 /** 1195 - * tty_line_name - generate name for a tty 1195 + * tty_line_name - generate name for a tty 1196 1196 * @driver: the tty driver in use 1197 1197 * @index: the minor number 1198 1198 * @p: output buffer of at least 7 bytes ··· 1243 1243 } 1244 1244 1245 1245 /** 1246 - * tty_init_termios - helper for termios setup 1246 + * tty_init_termios - helper for termios setup 1247 1247 * @tty: the tty to set up 1248 1248 * 1249 1249 * Initialise the termios structure for this tty. This runs under the ··· 1326 1326 } 1327 1327 1328 1328 /** 1329 - * tty_reopen() - fast re-open of an open tty 1329 + * tty_reopen() - fast re-open of an open tty 1330 1330 * @tty: the tty to open 1331 1331 * 1332 1332 * Re-opens on master ptys are not allowed and return -%EIO. ··· 1370 1370 } 1371 1371 1372 1372 /** 1373 - * tty_init_dev - initialise a tty device 1373 + * tty_init_dev - initialise a tty device 1374 1374 * @driver: tty driver we are opening a device on 1375 1375 * @idx: device index 1376 1376 * ··· 1492 1492 EXPORT_SYMBOL_GPL(tty_save_termios); 1493 1493 1494 1494 /** 1495 - * tty_flush_works - flush all works of a tty/pty pair 1495 + * tty_flush_works - flush all works of a tty/pty pair 1496 1496 * @tty: tty device to flush works for (or either end of a pty pair) 1497 1497 * 1498 1498 * Sync flush all works belonging to @tty (and the 'other' tty). ··· 1508 1508 } 1509 1509 1510 1510 /** 1511 - * release_one_tty - release tty structure memory 1511 + * release_one_tty - release tty structure memory 1512 1512 * @work: work of tty we are obliterating 1513 1513 * 1514 1514 * Releases memory associated with a tty structure, and clears out the ··· 1556 1556 } 1557 1557 1558 1558 /** 1559 - * tty_kref_put - release a tty kref 1559 + * tty_kref_put - release a tty kref 1560 1560 * @tty: tty device 1561 1561 * 1562 1562 * Release a reference to the @tty device and if need be let the kref layer ··· 1570 1570 EXPORT_SYMBOL(tty_kref_put); 1571 1571 1572 1572 /** 1573 - * release_tty - release tty structure memory 1573 + * release_tty - release tty structure memory 1574 1574 * @tty: tty device release 1575 1575 * @idx: index of the tty device release 1576 1576 * ··· 1647 1647 } 1648 1648 1649 1649 /** 1650 - * tty_kclose - closes tty opened by tty_kopen 1650 + * tty_kclose - closes tty opened by tty_kopen 1651 1651 * @tty: tty device 1652 1652 * 1653 1653 * Performs the final steps to release and free a tty device. It is the same as ··· 1677 1677 EXPORT_SYMBOL_GPL(tty_kclose); 1678 1678 1679 1679 /** 1680 - * tty_release_struct - release a tty struct 1680 + * tty_release_struct - release a tty struct 1681 1681 * @tty: tty device 1682 1682 * @idx: index of the tty 1683 1683 * ··· 1706 1706 EXPORT_SYMBOL_GPL(tty_release_struct); 1707 1707 1708 1708 /** 1709 - * tty_release - vfs callback for close 1709 + * tty_release - vfs callback for close 1710 1710 * @inode: inode of tty 1711 1711 * @filp: file pointer for handle to tty 1712 1712 * ··· 1987 1987 } 1988 1988 1989 1989 /** 1990 - * tty_kopen_exclusive - open a tty device for kernel 1990 + * tty_kopen_exclusive - open a tty device for kernel 1991 1991 * @device: dev_t of device to open 1992 1992 * 1993 1993 * Opens tty exclusively for kernel. Performs the driver lookup, makes sure ··· 2007 2007 EXPORT_SYMBOL_GPL(tty_kopen_exclusive); 2008 2008 2009 2009 /** 2010 - * tty_kopen_shared - open a tty device for shared in-kernel use 2010 + * tty_kopen_shared - open a tty device for shared in-kernel use 2011 2011 * @device: dev_t of device to open 2012 2012 * 2013 2013 * Opens an already existing tty for in-kernel use. Compared to ··· 2022 2022 EXPORT_SYMBOL_GPL(tty_kopen_shared); 2023 2023 2024 2024 /** 2025 - * tty_open_by_driver - open a tty device 2025 + * tty_open_by_driver - open a tty device 2026 2026 * @device: dev_t of device to open 2027 2027 * @filp: file pointer to tty 2028 2028 * ··· 2090 2090 } 2091 2091 2092 2092 /** 2093 - * tty_open - open a tty device 2093 + * tty_open - open a tty device 2094 2094 * @inode: inode of device file 2095 2095 * @filp: file pointer to tty 2096 2096 * ··· 2184 2184 2185 2185 2186 2186 /** 2187 - * tty_poll - check tty status 2187 + * tty_poll - check tty status 2188 2188 * @filp: file being polled 2189 2189 * @wait: poll wait structures to update 2190 2190 * ··· 2262 2262 2263 2263 static bool tty_legacy_tiocsti __read_mostly = IS_ENABLED(CONFIG_LEGACY_TIOCSTI); 2264 2264 /** 2265 - * tiocsti - fake input character 2265 + * tiocsti - fake input character 2266 2266 * @tty: tty to fake input into 2267 2267 * @p: pointer to character 2268 2268 * ··· 2299 2299 } 2300 2300 2301 2301 /** 2302 - * tiocgwinsz - implement window query ioctl 2302 + * tiocgwinsz - implement window query ioctl 2303 2303 * @tty: tty 2304 2304 * @arg: user buffer for result 2305 2305 * ··· 2320 2320 } 2321 2321 2322 2322 /** 2323 - * tty_do_resize - resize event 2323 + * tty_do_resize - resize event 2324 2324 * @tty: tty being resized 2325 2325 * @ws: new dimensions 2326 2326 * ··· 2350 2350 EXPORT_SYMBOL(tty_do_resize); 2351 2351 2352 2352 /** 2353 - * tiocswinsz - implement window size set ioctl 2353 + * tiocswinsz - implement window size set ioctl 2354 2354 * @tty: tty side of tty 2355 2355 * @arg: user buffer for result 2356 2356 * ··· 2377 2377 } 2378 2378 2379 2379 /** 2380 - * tioccons - allow admin to move logical console 2380 + * tioccons - allow admin to move logical console 2381 2381 * @file: the file to become console 2382 2382 * 2383 2383 * Allow the administrator to move the redirected console device. ··· 2416 2416 } 2417 2417 2418 2418 /** 2419 - * tiocsetd - set line discipline 2419 + * tiocsetd - set line discipline 2420 2420 * @tty: tty device 2421 2421 * @p: pointer to user data 2422 2422 * ··· 2438 2438 } 2439 2439 2440 2440 /** 2441 - * tiocgetd - get line discipline 2441 + * tiocgetd - get line discipline 2442 2442 * @tty: tty device 2443 2443 * @p: pointer to user data 2444 2444 * ··· 2461 2461 } 2462 2462 2463 2463 /** 2464 - * send_break - performed time break 2464 + * send_break - performed time break 2465 2465 * @tty: device to break on 2466 2466 * @duration: timeout in mS 2467 2467 * ··· 2479 2479 return 0; 2480 2480 2481 2481 if (tty->driver->flags & TTY_DRIVER_HARDWARE_BREAK) 2482 - retval = tty->ops->break_ctl(tty, duration); 2483 - else { 2484 - /* Do the work ourselves */ 2485 - if (tty_write_lock(tty, false) < 0) 2486 - return -EINTR; 2487 - retval = tty->ops->break_ctl(tty, -1); 2488 - if (retval) 2489 - goto out; 2490 - if (!signal_pending(current)) 2491 - msleep_interruptible(duration); 2482 + return tty->ops->break_ctl(tty, duration); 2483 + 2484 + /* Do the work ourselves */ 2485 + if (tty_write_lock(tty, false) < 0) 2486 + return -EINTR; 2487 + 2488 + retval = tty->ops->break_ctl(tty, -1); 2489 + if (!retval) { 2490 + msleep_interruptible(duration); 2492 2491 retval = tty->ops->break_ctl(tty, 0); 2493 - out: 2494 - tty_write_unlock(tty); 2495 - if (signal_pending(current)) 2496 - retval = -EINTR; 2497 2492 } 2493 + tty_write_unlock(tty); 2494 + 2495 + if (signal_pending(current)) 2496 + retval = -EINTR; 2497 + 2498 2498 return retval; 2499 2499 } 2500 2500 2501 2501 /** 2502 - * tty_tiocmget - get modem status 2502 + * tty_tiocmget - get modem status 2503 2503 * @tty: tty device 2504 2504 * @p: pointer to result 2505 2505 * ··· 2522 2522 } 2523 2523 2524 2524 /** 2525 - * tty_tiocmset - set modem status 2525 + * tty_tiocmset - set modem status 2526 2526 * @tty: tty device 2527 2527 * @cmd: command - clear bits, set bits or set all 2528 2528 * @p: pointer to desired bits ··· 2563 2563 } 2564 2564 2565 2565 /** 2566 - * tty_get_icount - get tty statistics 2566 + * tty_get_icount - get tty statistics 2567 2567 * @tty: tty device 2568 2568 * @icount: output parameter 2569 2569 * ··· 3126 3126 } 3127 3127 3128 3128 /** 3129 - * tty_put_char - write one character to a tty 3129 + * tty_put_char - write one character to a tty 3130 3130 * @tty: tty 3131 3131 * @ch: character to write 3132 3132 * ··· 3304 3304 EXPORT_SYMBOL(tty_unregister_device); 3305 3305 3306 3306 /** 3307 - * __tty_alloc_driver -- allocate tty driver 3307 + * __tty_alloc_driver - allocate tty driver 3308 3308 * @lines: count of lines this driver can handle at most 3309 3309 * @owner: module which is responsible for this driver 3310 3310 * @flags: some of %TTY_DRIVER_ flags, will be set in driver->flags ··· 3397 3397 } 3398 3398 3399 3399 /** 3400 - * tty_driver_kref_put -- drop a reference to a tty driver 3400 + * tty_driver_kref_put - drop a reference to a tty driver 3401 3401 * @driver: driver of which to drop the reference 3402 3402 * 3403 3403 * The final put will destroy and free up the driver. ··· 3409 3409 EXPORT_SYMBOL(tty_driver_kref_put); 3410 3410 3411 3411 /** 3412 - * tty_register_driver -- register a tty driver 3412 + * tty_register_driver - register a tty driver 3413 3413 * @driver: driver to register 3414 3414 * 3415 3415 * Called by a tty driver to register itself. ··· 3474 3474 EXPORT_SYMBOL(tty_register_driver); 3475 3475 3476 3476 /** 3477 - * tty_unregister_driver -- unregister a tty driver 3477 + * tty_unregister_driver - unregister a tty driver 3478 3478 * @driver: driver to unregister 3479 3479 * 3480 3480 * Called by a tty driver to unregister itself.

+114 -120

drivers/tty/tty_ioctl.c

··· 38 38 #define TERMIOS_TERMIO BIT(2) 39 39 #define TERMIOS_OLD BIT(3) 40 40 41 - 42 41 /** 43 - * tty_chars_in_buffer - characters pending 44 - * @tty: terminal 42 + * tty_chars_in_buffer - characters pending 43 + * @tty: terminal 45 44 * 46 - * Return the number of bytes of data in the device private 47 - * output queue. If no private method is supplied there is assumed 48 - * to be no queue on the device. 45 + * Returns: the number of bytes of data in the device private output queue. If 46 + * no private method is supplied there is assumed to be no queue on the device. 49 47 */ 50 - 51 48 unsigned int tty_chars_in_buffer(struct tty_struct *tty) 52 49 { 53 50 if (tty->ops->chars_in_buffer) ··· 54 57 EXPORT_SYMBOL(tty_chars_in_buffer); 55 58 56 59 /** 57 - * tty_write_room - write queue space 58 - * @tty: terminal 60 + * tty_write_room - write queue space 61 + * @tty: terminal 59 62 * 60 - * Return the number of bytes that can be queued to this device 61 - * at the present time. The result should be treated as a guarantee 62 - * and the driver cannot offer a value it later shrinks by more than 63 - * the number of bytes written. If no method is provided 2K is always 64 - * returned and data may be lost as there will be no flow control. 63 + * Returns: the number of bytes that can be queued to this device at the present 64 + * time. The result should be treated as a guarantee and the driver cannot 65 + * offer a value it later shrinks by more than the number of bytes written. If 66 + * no method is provided, 2K is always returned and data may be lost as there 67 + * will be no flow control. 65 68 */ 66 - 67 69 unsigned int tty_write_room(struct tty_struct *tty) 68 70 { 69 71 if (tty->ops->write_room) ··· 72 76 EXPORT_SYMBOL(tty_write_room); 73 77 74 78 /** 75 - * tty_driver_flush_buffer - discard internal buffer 76 - * @tty: terminal 79 + * tty_driver_flush_buffer - discard internal buffer 80 + * @tty: terminal 77 81 * 78 - * Discard the internal output buffer for this device. If no method 79 - * is provided then either the buffer cannot be hardware flushed or 80 - * there is no buffer driver side. 82 + * Discard the internal output buffer for this device. If no method is provided, 83 + * then either the buffer cannot be hardware flushed or there is no buffer 84 + * driver side. 81 85 */ 82 86 void tty_driver_flush_buffer(struct tty_struct *tty) 83 87 { ··· 87 91 EXPORT_SYMBOL(tty_driver_flush_buffer); 88 92 89 93 /** 90 - * tty_unthrottle - flow control 91 - * @tty: terminal 94 + * tty_unthrottle - flow control 95 + * @tty: terminal 92 96 * 93 - * Indicate that a tty may continue transmitting data down the stack. 94 - * Takes the termios rwsem to protect against parallel throttle/unthrottle 95 - * and also to ensure the driver can consistently reference its own 96 - * termios data at this point when implementing software flow control. 97 + * Indicate that a @tty may continue transmitting data down the stack. Takes 98 + * the &tty_struct->termios_rwsem to protect against parallel 99 + * throttle/unthrottle and also to ensure the driver can consistently reference 100 + * its own termios data at this point when implementing software flow control. 97 101 * 98 - * Drivers should however remember that the stack can issue a throttle, 99 - * then change flow control method, then unthrottle. 102 + * Drivers should however remember that the stack can issue a throttle, then 103 + * change flow control method, then unthrottle. 100 104 */ 101 - 102 105 void tty_unthrottle(struct tty_struct *tty) 103 106 { 104 107 down_write(&tty->termios_rwsem); 105 108 if (test_and_clear_bit(TTY_THROTTLED, &tty->flags) && 106 109 tty->ops->unthrottle) 107 110 tty->ops->unthrottle(tty); 108 - tty->flow_change = 0; 111 + tty->flow_change = TTY_FLOW_NO_CHANGE; 109 112 up_write(&tty->termios_rwsem); 110 113 } 111 114 EXPORT_SYMBOL(tty_unthrottle); 112 115 113 116 /** 114 - * tty_throttle_safe - flow control 115 - * @tty: terminal 117 + * tty_throttle_safe - flow control 118 + * @tty: terminal 116 119 * 117 - * Indicate that a tty should stop transmitting data down the stack. 118 - * tty_throttle_safe will only attempt throttle if tty->flow_change is 119 - * TTY_THROTTLE_SAFE. Prevents an accidental throttle due to race 120 - * conditions when throttling is conditional on factors evaluated prior to 121 - * throttling. 120 + * Indicate that a @tty should stop transmitting data down the stack. 121 + * tty_throttle_safe() will only attempt throttle if @tty->flow_change is 122 + * %TTY_THROTTLE_SAFE. Prevents an accidental throttle due to race conditions 123 + * when throttling is conditional on factors evaluated prior to throttling. 122 124 * 123 - * Returns 0 if tty is throttled (or was already throttled) 125 + * Returns: %true if @tty is throttled (or was already throttled) 124 126 */ 125 - 126 - int tty_throttle_safe(struct tty_struct *tty) 127 + bool tty_throttle_safe(struct tty_struct *tty) 127 128 { 128 - int ret = 0; 129 + bool ret = true; 129 130 130 131 mutex_lock(&tty->throttle_mutex); 131 132 if (!tty_throttled(tty)) { 132 133 if (tty->flow_change != TTY_THROTTLE_SAFE) 133 - ret = 1; 134 + ret = false; 134 135 else { 135 136 set_bit(TTY_THROTTLED, &tty->flags); 136 137 if (tty->ops->throttle) ··· 140 147 } 141 148 142 149 /** 143 - * tty_unthrottle_safe - flow control 144 - * @tty: terminal 150 + * tty_unthrottle_safe - flow control 151 + * @tty: terminal 145 152 * 146 - * Similar to tty_unthrottle() but will only attempt unthrottle 147 - * if tty->flow_change is TTY_UNTHROTTLE_SAFE. Prevents an accidental 148 - * unthrottle due to race conditions when unthrottling is conditional 149 - * on factors evaluated prior to unthrottling. 153 + * Similar to tty_unthrottle() but will only attempt unthrottle if 154 + * @tty->flow_change is %TTY_UNTHROTTLE_SAFE. Prevents an accidental unthrottle 155 + * due to race conditions when unthrottling is conditional on factors evaluated 156 + * prior to unthrottling. 150 157 * 151 - * Returns 0 if tty is unthrottled (or was already unthrottled) 158 + * Returns: %true if @tty is unthrottled (or was already unthrottled) 152 159 */ 153 - 154 - int tty_unthrottle_safe(struct tty_struct *tty) 160 + bool tty_unthrottle_safe(struct tty_struct *tty) 155 161 { 156 - int ret = 0; 162 + bool ret = true; 157 163 158 164 mutex_lock(&tty->throttle_mutex); 159 165 if (tty_throttled(tty)) { 160 166 if (tty->flow_change != TTY_UNTHROTTLE_SAFE) 161 - ret = 1; 167 + ret = false; 162 168 else { 163 169 clear_bit(TTY_THROTTLED, &tty->flags); 164 170 if (tty->ops->unthrottle) ··· 170 178 } 171 179 172 180 /** 173 - * tty_wait_until_sent - wait for I/O to finish 174 - * @tty: tty we are waiting for 175 - * @timeout: how long we will wait 181 + * tty_wait_until_sent - wait for I/O to finish 182 + * @tty: tty we are waiting for 183 + * @timeout: how long we will wait 176 184 * 177 - * Wait for characters pending in a tty driver to hit the wire, or 178 - * for a timeout to occur (eg due to flow control) 185 + * Wait for characters pending in a tty driver to hit the wire, or for a 186 + * timeout to occur (eg due to flow control). 179 187 * 180 - * Locking: none 188 + * Locking: none 181 189 */ 182 190 183 191 void tty_wait_until_sent(struct tty_struct *tty, long timeout) ··· 223 231 } 224 232 225 233 /** 226 - * tty_termios_copy_hw - copy hardware settings 227 - * @new: New termios 228 - * @old: Old termios 234 + * tty_termios_copy_hw - copy hardware settings 235 + * @new: new termios 236 + * @old: old termios 229 237 * 230 - * Propagate the hardware specific terminal setting bits from 231 - * the old termios structure to the new one. This is used in cases 232 - * where the hardware does not support reconfiguration or as a helper 233 - * in some cases where only minimal reconfiguration is supported 238 + * Propagate the hardware specific terminal setting bits from the @old termios 239 + * structure to the @new one. This is used in cases where the hardware does not 240 + * support reconfiguration or as a helper in some cases where only minimal 241 + * reconfiguration is supported. 234 242 */ 235 - 236 243 void tty_termios_copy_hw(struct ktermios *new, const struct ktermios *old) 237 244 { 238 245 /* The bits a dumb device handles in software. Smart devices need ··· 244 253 EXPORT_SYMBOL(tty_termios_copy_hw); 245 254 246 255 /** 247 - * tty_termios_hw_change - check for setting change 248 - * @a: termios 249 - * @b: termios to compare 256 + * tty_termios_hw_change - check for setting change 257 + * @a: termios 258 + * @b: termios to compare 250 259 * 251 - * Check if any of the bits that affect a dumb device have changed 252 - * between the two termios structures, or a speed change is needed. 260 + * Check if any of the bits that affect a dumb device have changed between the 261 + * two termios structures, or a speed change is needed. 262 + * 263 + * Returns: %true if change is needed 253 264 */ 254 - 255 265 bool tty_termios_hw_change(const struct ktermios *a, const struct ktermios *b) 256 266 { 257 267 if (a->c_ispeed != b->c_ispeed || a->c_ospeed != b->c_ospeed) ··· 264 272 EXPORT_SYMBOL(tty_termios_hw_change); 265 273 266 274 /** 267 - * tty_get_char_size - get size of a character 268 - * @cflag: termios cflag value 275 + * tty_get_char_size - get size of a character 276 + * @cflag: termios cflag value 269 277 * 270 - * Get the size (in bits) of a character depending on @cflag's %CSIZE 271 - * setting. 278 + * Returns: size (in bits) of a character depending on @cflag's %CSIZE setting 272 279 */ 273 280 unsigned char tty_get_char_size(unsigned int cflag) 274 281 { ··· 286 295 EXPORT_SYMBOL_GPL(tty_get_char_size); 287 296 288 297 /** 289 - * tty_get_frame_size - get size of a frame 290 - * @cflag: termios cflag value 298 + * tty_get_frame_size - get size of a frame 299 + * @cflag: termios cflag value 291 300 * 292 - * Get the size (in bits) of a frame depending on @cflag's %CSIZE, %CSTOPB, 293 - * and %PARENB setting. The result is a sum of character size, start and 294 - * stop bits -- one bit each -- second stop bit (if set), and parity bit 295 - * (if set). 301 + * Get the size (in bits) of a frame depending on @cflag's %CSIZE, %CSTOPB, and 302 + * %PARENB setting. The result is a sum of character size, start and stop bits 303 + * -- one bit each -- second stop bit (if set), and parity bit (if set). 304 + * 305 + * Returns: size (in bits) of a frame depending on @cflag's setting. 296 306 */ 297 307 unsigned char tty_get_frame_size(unsigned int cflag) 298 308 { ··· 311 319 EXPORT_SYMBOL_GPL(tty_get_frame_size); 312 320 313 321 /** 314 - * tty_set_termios - update termios values 315 - * @tty: tty to update 316 - * @new_termios: desired new value 322 + * tty_set_termios - update termios values 323 + * @tty: tty to update 324 + * @new_termios: desired new value 317 325 * 318 - * Perform updates to the termios values set on this terminal. 319 - * A master pty's termios should never be set. 326 + * Perform updates to the termios values set on this @tty. A master pty's 327 + * termios should never be set. 320 328 * 321 - * Locking: termios_rwsem 329 + * Locking: &tty_struct->termios_rwsem 322 330 */ 323 - 324 331 int tty_set_termios(struct tty_struct *tty, struct ktermios *new_termios) 325 332 { 326 333 struct ktermios old_termios; ··· 432 441 #endif /* TCGETS2 */ 433 442 434 443 /** 435 - * set_termios - set termios values for a tty 436 - * @tty: terminal device 437 - * @arg: user data 438 - * @opt: option information 444 + * set_termios - set termios values for a tty 445 + * @tty: terminal device 446 + * @arg: user data 447 + * @opt: option information 439 448 * 440 - * Helper function to prepare termios data and run necessary other 441 - * functions before using tty_set_termios to do the actual changes. 449 + * Helper function to prepare termios data and run necessary other functions 450 + * before using tty_set_termios() to do the actual changes. 442 451 * 443 - * Locking: 444 - * Called functions take ldisc and termios_rwsem locks 452 + * Locking: called functions take &tty_struct->ldisc_sem and 453 + * &tty_struct->termios_rwsem locks 454 + * 455 + * Returns: 0 on success, an error otherwise 445 456 */ 446 - 447 457 static int set_termios(struct tty_struct *tty, void __user *arg, int opt) 448 458 { 449 459 struct ktermios tmp_termios; ··· 616 624 } 617 625 618 626 /** 619 - * set_sgttyb - set legacy terminal values 620 - * @tty: tty structure 621 - * @sgttyb: pointer to old style terminal structure 627 + * set_sgttyb - set legacy terminal values 628 + * @tty: tty structure 629 + * @sgttyb: pointer to old style terminal structure 622 630 * 623 - * Updates a terminal from the legacy BSD style terminal information 624 - * structure. 631 + * Updates a terminal from the legacy BSD style terminal information structure. 625 632 * 626 - * Locking: termios_rwsem 633 + * Locking: &tty_struct->termios_rwsem 634 + * 635 + * Returns: 0 on success, an error otherwise 627 636 */ 628 - 629 637 static int set_sgttyb(struct tty_struct *tty, struct sgttyb __user *sgttyb) 630 638 { 631 639 int retval; ··· 727 735 #endif 728 736 729 737 /** 730 - * tty_change_softcar - carrier change ioctl helper 731 - * @tty: tty to update 732 - * @enable: enable/disable CLOCAL 738 + * tty_change_softcar - carrier change ioctl helper 739 + * @tty: tty to update 740 + * @enable: enable/disable %CLOCAL 733 741 * 734 - * Perform a change to the CLOCAL state and call into the driver 735 - * layer to make it visible. All done with the termios rwsem 742 + * Perform a change to the %CLOCAL state and call into the driver layer to make 743 + * it visible. 744 + * 745 + * Locking: &tty_struct->termios_rwsem. 746 + * 747 + * Returns: 0 on success, an error otherwise 736 748 */ 737 - 738 749 static int tty_change_softcar(struct tty_struct *tty, bool enable) 739 750 { 740 751 int ret = 0; ··· 757 762 } 758 763 759 764 /** 760 - * tty_mode_ioctl - mode related ioctls 761 - * @tty: tty for the ioctl 762 - * @cmd: command 763 - * @arg: ioctl argument 765 + * tty_mode_ioctl - mode related ioctls 766 + * @tty: tty for the ioctl 767 + * @cmd: command 768 + * @arg: ioctl argument 764 769 * 765 - * Perform non line discipline specific mode control ioctls. This 766 - * is designed to be called by line disciplines to ensure they provide 767 - * consistent mode setting. 770 + * Perform non-line discipline specific mode control ioctls. This is designed 771 + * to be called by line disciplines to ensure they provide consistent mode 772 + * setting. 768 773 */ 769 - 770 774 int tty_mode_ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg) 771 775 { 772 776 struct tty_struct *real_tty;

+11 -6

drivers/tty/tty_jobctrl.c

··· 300 300 return; 301 301 } 302 302 303 - spin_lock_irq(&current->sighand->siglock); 304 - put_pid(current->signal->tty_old_pgrp); 305 - current->signal->tty_old_pgrp = NULL; 306 - tty = tty_kref_get(current->signal->tty); 307 - spin_unlock_irq(&current->sighand->siglock); 308 - 303 + tty = get_current_tty(); 309 304 if (tty) { 310 305 unsigned long flags; 311 306 ··· 314 319 tty_unlock(tty); 315 320 tty_kref_put(tty); 316 321 } 322 + 323 + /* If tty->ctrl.pgrp is not NULL, it may be assigned to 324 + * current->signal->tty_old_pgrp in a race condition, and 325 + * cause pid memleak. Release current->signal->tty_old_pgrp 326 + * after tty->ctrl.pgrp set to NULL. 327 + */ 328 + spin_lock_irq(&current->sighand->siglock); 329 + put_pid(current->signal->tty_old_pgrp); 330 + current->signal->tty_old_pgrp = NULL; 331 + spin_unlock_irq(&current->sighand->siglock); 317 332 318 333 /* Now clear signal->tty under the lock */ 319 334 read_lock(&tasklist_lock);

+3 -3

drivers/tty/tty_port.c

··· 79 79 EXPORT_SYMBOL_GPL(tty_port_default_client_ops); 80 80 81 81 /** 82 - * tty_port_init -- initialize tty_port 82 + * tty_port_init - initialize tty_port 83 83 * @port: tty_port to initialize 84 84 * 85 85 * Initializes the state of struct tty_port. When a port was initialized using ··· 267 267 EXPORT_SYMBOL(tty_port_free_xmit_buf); 268 268 269 269 /** 270 - * tty_port_destroy -- destroy inited port 270 + * tty_port_destroy - destroy inited port 271 271 * @port: tty port to be destroyed 272 272 * 273 273 * When a port was initialized using tty_port_init(), one has to destroy the ··· 297 297 } 298 298 299 299 /** 300 - * tty_port_put -- drop a reference to tty_port 300 + * tty_port_put - drop a reference to tty_port 301 301 * @port: port to drop a reference of (can be NULL) 302 302 * 303 303 * The final put will destroy and free up the @port using

+13 -3

drivers/tty/vcc.c

··· 579 579 return -ENOMEM; 580 580 581 581 name = kstrdup(dev_name(&vdev->dev), GFP_KERNEL); 582 + if (!name) { 583 + rv = -ENOMEM; 584 + goto free_port; 585 + } 582 586 583 587 rv = vio_driver_init(&port->vio, vdev, VDEV_CONSOLE_CON, vcc_versions, 584 588 ARRAY_SIZE(vcc_versions), NULL, name); 585 589 if (rv) 586 - goto free_port; 590 + goto free_name; 587 591 588 592 port->vio.debug = vcc_dbg_vio; 589 593 vcc_ldc_cfg.debug = vcc_dbg_ldc; 590 594 591 595 rv = vio_ldc_alloc(&port->vio, &vcc_ldc_cfg, port); 592 596 if (rv) 593 - goto free_port; 597 + goto free_name; 594 598 595 599 spin_lock_init(&port->lock); 596 600 ··· 628 624 goto unreg_tty; 629 625 } 630 626 port->domain = kstrdup(domain, GFP_KERNEL); 627 + if (!port->domain) { 628 + rv = -ENOMEM; 629 + goto unreg_tty; 630 + } 631 + 631 632 632 633 mdesc_release(hp); 633 634 ··· 662 653 vcc_table_remove(port->index); 663 654 free_ldc: 664 655 vio_ldc_free(&port->vio); 665 - free_port: 656 + free_name: 666 657 kfree(name); 658 + free_port: 667 659 kfree(port); 668 660 669 661 return rv;

+1 -1

drivers/tty/vt/consolemap.c

··· 205 205 FIELD_PREP(UNI_GLYPH_BITS, (glyph))) 206 206 207 207 /** 208 - * struct uni_pagedict -- unicode directory 208 + * struct uni_pagedict - unicode directory 209 209 * 210 210 * @uni_pgdir: 32*32*64 table with glyphs 211 211 * @refcount: reference count of this structure

+5 -2

drivers/tty/vt/keyboard.c

··· 2079 2079 return -ENOMEM; 2080 2080 2081 2081 spin_lock_irqsave(&func_buf_lock, flags); 2082 - len = strlcpy(kbs, func_table[kb_func] ? : "", len); 2082 + len = strscpy(kbs, func_table[kb_func] ? : "", len); 2083 2083 spin_unlock_irqrestore(&func_buf_lock, flags); 2084 2084 2085 + if (len < 0) { 2086 + ret = -ENOSPC; 2087 + break; 2088 + } 2085 2089 ret = copy_to_user(user_kdgkb->kb_string, kbs, len + 1) ? 2086 2090 -EFAULT : 0; 2087 - 2088 2091 break; 2089 2092 } 2090 2093 case KDSKBSENT:

+16 -16

drivers/tty/vt/vc_screen.c

··· 174 174 } 175 175 176 176 /** 177 - * vcs_vc -- return VC for @inode 177 + * vcs_vc - return VC for @inode 178 178 * @inode: inode for which to return a VC 179 179 * @viewed: returns whether this console is currently foreground (viewed) 180 180 * ··· 199 199 } 200 200 201 201 /** 202 - * vcs_size -- return size for a VC in @vc 202 + * vcs_size - return size for a VC in @vc 203 203 * @vc: which VC 204 204 * @attr: does it use attributes? 205 205 * @unicode: is it unicode? ··· 786 786 .release = vcs_release, 787 787 }; 788 788 789 - static struct class *vc_class; 789 + static const struct class vc_class = { 790 + .name = "vc", 791 + }; 790 792 791 793 void vcs_make_sysfs(int index) 792 794 { 793 - device_create(vc_class, NULL, MKDEV(VCS_MAJOR, index + 1), NULL, 794 - "vcs%u", index + 1); 795 - device_create(vc_class, NULL, MKDEV(VCS_MAJOR, index + 65), NULL, 796 - "vcsu%u", index + 1); 797 - device_create(vc_class, NULL, MKDEV(VCS_MAJOR, index + 129), NULL, 798 - "vcsa%u", index + 1); 795 + device_create(&vc_class, NULL, MKDEV(VCS_MAJOR, index + 1), NULL, "vcs%u", index + 1); 796 + device_create(&vc_class, NULL, MKDEV(VCS_MAJOR, index + 65), NULL, "vcsu%u", index + 1); 797 + device_create(&vc_class, NULL, MKDEV(VCS_MAJOR, index + 129), NULL, "vcsa%u", index + 1); 799 798 } 800 799 801 800 void vcs_remove_sysfs(int index) 802 801 { 803 - device_destroy(vc_class, MKDEV(VCS_MAJOR, index + 1)); 804 - device_destroy(vc_class, MKDEV(VCS_MAJOR, index + 65)); 805 - device_destroy(vc_class, MKDEV(VCS_MAJOR, index + 129)); 802 + device_destroy(&vc_class, MKDEV(VCS_MAJOR, index + 1)); 803 + device_destroy(&vc_class, MKDEV(VCS_MAJOR, index + 65)); 804 + device_destroy(&vc_class, MKDEV(VCS_MAJOR, index + 129)); 806 805 } 807 806 808 807 int __init vcs_init(void) ··· 810 811 811 812 if (register_chrdev(VCS_MAJOR, "vcs", &vcs_fops)) 812 813 panic("unable to get major %d for vcs device", VCS_MAJOR); 813 - vc_class = class_create("vc"); 814 + if (class_register(&vc_class)) 815 + panic("unable to create vc_class"); 814 816 815 - device_create(vc_class, NULL, MKDEV(VCS_MAJOR, 0), NULL, "vcs"); 816 - device_create(vc_class, NULL, MKDEV(VCS_MAJOR, 64), NULL, "vcsu"); 817 - device_create(vc_class, NULL, MKDEV(VCS_MAJOR, 128), NULL, "vcsa"); 817 + device_create(&vc_class, NULL, MKDEV(VCS_MAJOR, 0), NULL, "vcs"); 818 + device_create(&vc_class, NULL, MKDEV(VCS_MAJOR, 64), NULL, "vcsu"); 819 + device_create(&vc_class, NULL, MKDEV(VCS_MAJOR, 128), NULL, "vcsa"); 818 820 for (i = 0; i < MIN_NR_CONSOLES; i++) 819 821 vcs_make_sysfs(i); 820 822 return 0;

+17 -12

drivers/tty/vt/vt.c

··· 2588 2588 2589 2589 2590 2590 /** 2591 - * vc_sanitize_unicode -- Replace invalid Unicode code points with U+FFFD 2591 + * vc_sanitize_unicode - Replace invalid Unicode code points with U+FFFD 2592 2592 * @c: the received character, or U+FFFD for invalid sequences. 2593 2593 */ 2594 2594 static inline int vc_sanitize_unicode(const int c) ··· 2600 2600 } 2601 2601 2602 2602 /** 2603 - * vc_translate_unicode -- Combine UTF-8 into Unicode in @vc_utf_char 2603 + * vc_translate_unicode - Combine UTF-8 into Unicode in @vc_utf_char 2604 2604 * @vc: virtual console 2605 2605 * @c: character to translate 2606 2606 * @rescan: we return true if we need more (continuation) data ··· 3155 3155 3156 3156 switch (type) { 3157 3157 case TIOCL_SETSEL: 3158 + if (!capable(CAP_SYS_ADMIN)) 3159 + return -EPERM; 3158 3160 return set_selection_user((struct tiocl_selection 3159 3161 __user *)(p+1), tty); 3160 3162 case TIOCL_PASTESEL: 3163 + if (!capable(CAP_SYS_ADMIN)) 3164 + return -EPERM; 3161 3165 return paste_selection(tty); 3162 3166 case TIOCL_UNBLANKSCREEN: 3163 3167 console_lock(); ··· 3169 3165 console_unlock(); 3170 3166 break; 3171 3167 case TIOCL_SELLOADLUT: 3168 + if (!capable(CAP_SYS_ADMIN)) 3169 + return -EPERM; 3172 3170 console_lock(); 3173 3171 ret = sel_loadlut(p); 3174 3172 console_unlock(); ··· 3571 3565 return 0; 3572 3566 } 3573 3567 3574 - static struct class *vtconsole_class; 3568 + static const struct class vtconsole_class = { 3569 + .name = "vtconsole", 3570 + }; 3575 3571 3576 3572 static int do_bind_con_driver(const struct consw *csw, int first, int last, 3577 3573 int deflt) ··· 4100 4092 goto err; 4101 4093 4102 4094 con_driver->dev = 4103 - device_create_with_groups(vtconsole_class, NULL, 4095 + device_create_with_groups(&vtconsole_class, NULL, 4104 4096 MKDEV(0, con_driver->node), 4105 4097 con_driver, con_dev_groups, 4106 4098 "vtcon%i", con_driver->node); ··· 4181 4173 console_unlock(); 4182 4174 4183 4175 vtconsole_deinit_device(con_driver); 4184 - device_destroy(vtconsole_class, MKDEV(0, con_driver->node)); 4176 + device_destroy(&vtconsole_class, MKDEV(0, con_driver->node)); 4185 4177 4186 4178 console_lock(); 4187 4179 ··· 4242 4234 { 4243 4235 int i; 4244 4236 4245 - vtconsole_class = class_create("vtconsole"); 4246 - if (IS_ERR(vtconsole_class)) { 4247 - pr_warn("Unable to create vt console class; errno = %ld\n", 4248 - PTR_ERR(vtconsole_class)); 4249 - vtconsole_class = NULL; 4250 - } 4237 + i = class_register(&vtconsole_class); 4238 + if (i) 4239 + pr_warn("Unable to create vt console class; errno = %d\n", i); 4251 4240 4252 4241 /* Add system drivers to sysfs */ 4253 4242 for (i = 0; i < MAX_NR_CON_DRIVER; i++) { ··· 4252 4247 4253 4248 if (con->con && !con->dev) { 4254 4249 con->dev = 4255 - device_create_with_groups(vtconsole_class, NULL, 4250 + device_create_with_groups(&vtconsole_class, NULL, 4256 4251 MKDEV(0, con->node), 4257 4252 con, con_dev_groups, 4258 4253 "vtcon%i", con->node);

+6 -5

drivers/video/console/Kconfig

··· 7 7 8 8 config VGA_CONSOLE 9 9 bool "VGA text console" if EXPERT || !X86 10 - depends on !4xx && !PPC_8xx && !SPARC && !M68K && !PARISC && !SUPERH && \ 11 - (!ARM || ARCH_FOOTBRIDGE || ARCH_INTEGRATOR || ARCH_NETWINDER) && \ 12 - !ARM64 && !ARC && !MICROBLAZE && !OPENRISC && !S390 && !UML 10 + depends on ALPHA || IA64 || X86 || \ 11 + (ARM && ARCH_FOOTBRIDGE) || \ 12 + (MIPS && (MIPS_MALTA || SIBYTE_BCM112X || SIBYTE_SB1250 || SIBYTE_BCM1x80 || SNI_RM)) 13 13 select APERTURE_HELPERS if (DRM || FB || VFIO_PCI_CORE) 14 14 default y 15 15 help ··· 52 52 53 53 config DUMMY_CONSOLE_COLUMNS 54 54 int "Initial number of console screen columns" 55 - depends on DUMMY_CONSOLE && !ARM 55 + depends on DUMMY_CONSOLE && !ARCH_FOOTBRIDGE 56 56 default 160 if PARISC 57 57 default 80 58 58 help ··· 62 62 63 63 config DUMMY_CONSOLE_ROWS 64 64 int "Initial number of console screen rows" 65 - depends on DUMMY_CONSOLE && !ARM 65 + depends on DUMMY_CONSOLE && !ARCH_FOOTBRIDGE 66 66 default 64 if PARISC 67 + default 30 if ARM 67 68 default 25 68 69 help 69 70 On PA-RISC, the default value is 64, which should fit a 1280x1024

+4 -3

drivers/video/console/dummycon.c

··· 18 18 * Dummy console driver 19 19 */ 20 20 21 - #if defined(__arm__) 22 - #define DUMMY_COLUMNS screen_info.orig_video_cols 23 - #define DUMMY_ROWS screen_info.orig_video_lines 21 + #if defined(CONFIG_ARCH_FOOTBRIDGE) && defined(CONFIG_VGA_CONSOLE) 22 + #include <asm/vga.h> 23 + #define DUMMY_COLUMNS vgacon_screen_info.orig_video_cols 24 + #define DUMMY_ROWS vgacon_screen_info.orig_video_lines 24 25 #else 25 26 /* set by Kconfig. Use 80x25 for 640x480 and 160x64 for 1280x1024 */ 26 27 #define DUMMY_COLUMNS CONFIG_DUMMY_CONSOLE_COLUMNS

+40 -28

drivers/video/console/vgacon.c

··· 89 89 static int vga_scan_lines __read_mostly; 90 90 static unsigned int vga_rolled_over; /* last vc_origin offset before wrap */ 91 91 92 + static struct screen_info *vga_si; 93 + 92 94 static bool vga_hardscroll_enabled; 93 95 static bool vga_hardscroll_user_enable = true; 94 96 ··· 155 153 u16 saved1, saved2; 156 154 volatile u16 *p; 157 155 158 - if (screen_info.orig_video_isVGA == VIDEO_TYPE_VLFB || 159 - screen_info.orig_video_isVGA == VIDEO_TYPE_EFI) { 156 + if (!vga_si || 157 + vga_si->orig_video_isVGA == VIDEO_TYPE_VLFB || 158 + vga_si->orig_video_isVGA == VIDEO_TYPE_EFI) { 160 159 no_vga: 161 160 #ifdef CONFIG_DUMMY_CONSOLE 162 161 conswitchp = &dummy_con; ··· 167 164 #endif 168 165 } 169 166 170 - /* boot_params.screen_info reasonably initialized? */ 171 - if ((screen_info.orig_video_lines == 0) || 172 - (screen_info.orig_video_cols == 0)) 167 + /* vga_si reasonably initialized? */ 168 + if ((vga_si->orig_video_lines == 0) || 169 + (vga_si->orig_video_cols == 0)) 173 170 goto no_vga; 174 171 175 172 /* VGA16 modes are not handled by VGACON */ 176 - if ((screen_info.orig_video_mode == 0x0D) || /* 320x200/4 */ 177 - (screen_info.orig_video_mode == 0x0E) || /* 640x200/4 */ 178 - (screen_info.orig_video_mode == 0x10) || /* 640x350/4 */ 179 - (screen_info.orig_video_mode == 0x12) || /* 640x480/4 */ 180 - (screen_info.orig_video_mode == 0x6A)) /* 800x600/4 (VESA) */ 173 + if ((vga_si->orig_video_mode == 0x0D) || /* 320x200/4 */ 174 + (vga_si->orig_video_mode == 0x0E) || /* 640x200/4 */ 175 + (vga_si->orig_video_mode == 0x10) || /* 640x350/4 */ 176 + (vga_si->orig_video_mode == 0x12) || /* 640x480/4 */ 177 + (vga_si->orig_video_mode == 0x6A)) /* 800x600/4 (VESA) */ 181 178 goto no_vga; 182 179 183 - vga_video_num_lines = screen_info.orig_video_lines; 184 - vga_video_num_columns = screen_info.orig_video_cols; 180 + vga_video_num_lines = vga_si->orig_video_lines; 181 + vga_video_num_columns = vga_si->orig_video_cols; 185 182 vgastate.vgabase = NULL; 186 183 187 - if (screen_info.orig_video_mode == 7) { 184 + if (vga_si->orig_video_mode == 7) { 188 185 /* Monochrome display */ 189 186 vga_vram_base = 0xb0000; 190 187 vga_video_port_reg = VGA_CRT_IM; 191 188 vga_video_port_val = VGA_CRT_DM; 192 - if ((screen_info.orig_video_ega_bx & 0xff) != 0x10) { 189 + if ((vga_si->orig_video_ega_bx & 0xff) != 0x10) { 193 190 static struct resource ega_console_resource = 194 191 { .name = "ega", 195 192 .flags = IORESOURCE_IO, ··· 226 223 vga_vram_base = 0xb8000; 227 224 vga_video_port_reg = VGA_CRT_IC; 228 225 vga_video_port_val = VGA_CRT_DC; 229 - if ((screen_info.orig_video_ega_bx & 0xff) != 0x10) { 226 + if ((vga_si->orig_video_ega_bx & 0xff) != 0x10) { 230 227 int i; 231 228 232 229 vga_vram_size = 0x8000; 233 230 234 - if (!screen_info.orig_video_isVGA) { 231 + if (!vga_si->orig_video_isVGA) { 235 232 static struct resource ega_console_resource = 236 233 { .name = "ega", 237 234 .flags = IORESOURCE_IO, ··· 322 319 || vga_video_type == VIDEO_TYPE_VGAC 323 320 || vga_video_type == VIDEO_TYPE_EGAM) { 324 321 vga_hardscroll_enabled = vga_hardscroll_user_enable; 325 - vga_default_font_height = screen_info.orig_video_points; 326 - vga_video_font_height = screen_info.orig_video_points; 322 + vga_default_font_height = vga_si->orig_video_points; 323 + vga_video_font_height = vga_si->orig_video_points; 327 324 /* This may be suboptimal but is a safe bet - go with it */ 328 325 vga_scan_lines = 329 326 vga_video_font_height * vga_video_num_lines; 330 327 } 331 328 332 - vgacon_xres = screen_info.orig_video_cols * VGA_FONTWIDTH; 329 + vgacon_xres = vga_si->orig_video_cols * VGA_FONTWIDTH; 333 330 vgacon_yres = vga_scan_lines; 334 331 335 332 return display_desc; ··· 374 371 /* Only set the default if the user didn't deliberately override it */ 375 372 if (global_cursor_default == -1) 376 373 global_cursor_default = 377 - !(screen_info.flags & VIDEO_FLAGS_NOCURSOR); 374 + !(vga_si->flags & VIDEO_FLAGS_NOCURSOR); 378 375 } 379 376 380 377 static void vgacon_deinit(struct vc_data *c) ··· 592 589 { 593 590 int x = c->vc_cols * VGA_FONTWIDTH; 594 591 int y = c->vc_rows * c->vc_cell_height; 595 - int rows = screen_info.orig_video_lines * vga_default_font_height/ 592 + int rows = vga_si->orig_video_lines * vga_default_font_height/ 596 593 c->vc_cell_height; 597 594 /* 598 595 * We need to save screen size here as it's the only way ··· 612 609 613 610 if ((vgacon_xres != x || vgacon_yres != y) && 614 611 (!(vga_video_num_columns % 2) && 615 - vga_video_num_columns <= screen_info.orig_video_cols && 612 + vga_video_num_columns <= vga_si->orig_video_cols && 616 613 vga_video_num_lines <= rows)) 617 614 vgacon_doresize(c, c->vc_cols, c->vc_rows); 618 615 } ··· 1059 1056 * Ho ho! Someone (svgatextmode, eh?) may have reprogrammed 1060 1057 * the video mode! Set the new defaults then and go away. 1061 1058 */ 1062 - screen_info.orig_video_cols = width; 1063 - screen_info.orig_video_lines = height; 1059 + vga_si->orig_video_cols = width; 1060 + vga_si->orig_video_lines = height; 1064 1061 vga_default_font_height = c->vc_cell_height; 1065 1062 return 0; 1066 1063 } 1067 - if (width % 2 || width > screen_info.orig_video_cols || 1068 - height > (screen_info.orig_video_lines * vga_default_font_height)/ 1064 + if (width % 2 || width > vga_si->orig_video_cols || 1065 + height > (vga_si->orig_video_lines * vga_default_font_height)/ 1069 1066 c->vc_cell_height) 1070 1067 return -EINVAL; 1071 1068 ··· 1095 1092 * console initialization routines. 1096 1093 */ 1097 1094 vga_bootup_console = 1; 1098 - c->state.x = screen_info.orig_x; 1099 - c->state.y = screen_info.orig_y; 1095 + c->state.x = vga_si->orig_x; 1096 + c->state.y = vga_si->orig_y; 1100 1097 } 1101 1098 1102 1099 /* We can't copy in more than the size of the video buffer, ··· 1188 1185 .con_invert_region = vgacon_invert_region, 1189 1186 }; 1190 1187 EXPORT_SYMBOL(vga_con); 1188 + 1189 + void vgacon_register_screen(struct screen_info *si) 1190 + { 1191 + if (!si || vga_si) 1192 + return; 1193 + 1194 + conswitchp = &vga_con; 1195 + vga_si = si; 1196 + } 1191 1197 1192 1198 MODULE_LICENSE("GPL");

+1 -1

drivers/video/fbdev/Kconfig

··· 364 364 365 365 config FB_VGA16 366 366 tristate "VGA 16-color graphics support" 367 - depends on FB && (X86 || PPC) 367 + depends on FB && X86 368 368 select APERTURE_HELPERS 369 369 select FB_CFB_FILLRECT 370 370 select FB_CFB_COPYAREA

+4 -4

drivers/video/fbdev/hyperv_fb.c

··· 1010 1010 goto getmem_done; 1011 1011 } 1012 1012 pr_info("Unable to allocate enough contiguous physical memory on Gen 1 VM. Using MMIO instead.\n"); 1013 - } else { 1013 + } else if (IS_ENABLED(CONFIG_SYSFB)) { 1014 1014 base = screen_info.lfb_base; 1015 1015 size = screen_info.lfb_size; 1016 1016 } ··· 1056 1056 getmem_done: 1057 1057 aperture_remove_conflicting_devices(base, size, KBUILD_MODNAME); 1058 1058 1059 - if (gen2vm) { 1059 + if (!gen2vm) { 1060 + pci_dev_put(pdev); 1061 + } else if (IS_ENABLED(CONFIG_SYSFB)) { 1060 1062 /* framebuffer is reallocated, clear screen_info to avoid misuse from kexec */ 1061 1063 screen_info.lfb_size = 0; 1062 1064 screen_info.lfb_base = 0; 1063 1065 screen_info.orig_video_isVGA = 0; 1064 - } else { 1065 - pci_dev_put(pdev); 1066 1066 } 1067 1067 1068 1068 return 0;

+1 -8

drivers/video/fbdev/vga16fb.c

··· 185 185 /* Check if the video mode is supported by the driver */ 186 186 static inline int check_mode_supported(const struct screen_info *si) 187 187 { 188 - /* non-x86 architectures treat orig_video_isVGA as a boolean flag */ 189 - #if defined(CONFIG_X86) 190 188 /* only EGA and VGA in 16 color graphic mode are supported */ 191 189 if (si->orig_video_isVGA != VIDEO_TYPE_EGAC && 192 190 si->orig_video_isVGA != VIDEO_TYPE_VGAC) ··· 195 197 si->orig_video_mode != 0x10 && /* 640x350/4 (EGA) */ 196 198 si->orig_video_mode != 0x12) /* 640x480/4 (VGA) */ 197 199 return -ENODEV; 198 - #endif 200 + 199 201 return 0; 200 202 } 201 203 ··· 1338 1340 printk(KERN_INFO "vga16fb: mapped to 0x%p\n", info->screen_base); 1339 1341 par = info->par; 1340 1342 1341 - #if defined(CONFIG_X86) 1342 1343 par->isVGA = si->orig_video_isVGA == VIDEO_TYPE_VGAC; 1343 - #else 1344 - /* non-x86 architectures treat orig_video_isVGA as a boolean flag */ 1345 - par->isVGA = si->orig_video_isVGA; 1346 - #endif 1347 1344 par->palette_blanked = 0; 1348 1345 par->vesa_blanked = 0; 1349 1346

+8 -1

include/linux/console.h

··· 101 101 extern const struct consw vga_con; /* VGA text console */ 102 102 extern const struct consw newport_con; /* SGI Newport console */ 103 103 104 + struct screen_info; 105 + #ifdef CONFIG_VGA_CONSOLE 106 + void vgacon_register_screen(struct screen_info *si); 107 + #else 108 + static inline void vgacon_register_screen(struct screen_info *si) { } 109 + #endif 110 + 104 111 int con_is_bound(const struct consw *csw); 105 112 int do_unregister_con_driver(const struct consw *csw); 106 113 int do_take_over_console(const struct consw *sw, int first, int last, int deflt); ··· 476 469 CONSOLE_REPLAY_ALL, 477 470 }; 478 471 479 - extern int add_preferred_console(char *name, int idx, char *options); 472 + extern int add_preferred_console(const char *name, const short idx, char *options); 480 473 extern void console_force_preferred_locked(struct console *con); 481 474 extern void register_console(struct console *); 482 475 extern int unregister_console(struct console *);

+85 -6

include/linux/serial_core.h

··· 588 588 void *private_data; /* generic platform data pointer */ 589 589 }; 590 590 591 + /** 592 + * uart_port_lock - Lock the UART port 593 + * @up: Pointer to UART port structure 594 + */ 595 + static inline void uart_port_lock(struct uart_port *up) 596 + { 597 + spin_lock(&up->lock); 598 + } 599 + 600 + /** 601 + * uart_port_lock_irq - Lock the UART port and disable interrupts 602 + * @up: Pointer to UART port structure 603 + */ 604 + static inline void uart_port_lock_irq(struct uart_port *up) 605 + { 606 + spin_lock_irq(&up->lock); 607 + } 608 + 609 + /** 610 + * uart_port_lock_irqsave - Lock the UART port, save and disable interrupts 611 + * @up: Pointer to UART port structure 612 + * @flags: Pointer to interrupt flags storage 613 + */ 614 + static inline void uart_port_lock_irqsave(struct uart_port *up, unsigned long *flags) 615 + { 616 + spin_lock_irqsave(&up->lock, *flags); 617 + } 618 + 619 + /** 620 + * uart_port_trylock - Try to lock the UART port 621 + * @up: Pointer to UART port structure 622 + * 623 + * Returns: True if lock was acquired, false otherwise 624 + */ 625 + static inline bool uart_port_trylock(struct uart_port *up) 626 + { 627 + return spin_trylock(&up->lock); 628 + } 629 + 630 + /** 631 + * uart_port_trylock_irqsave - Try to lock the UART port, save and disable interrupts 632 + * @up: Pointer to UART port structure 633 + * @flags: Pointer to interrupt flags storage 634 + * 635 + * Returns: True if lock was acquired, false otherwise 636 + */ 637 + static inline bool uart_port_trylock_irqsave(struct uart_port *up, unsigned long *flags) 638 + { 639 + return spin_trylock_irqsave(&up->lock, *flags); 640 + } 641 + 642 + /** 643 + * uart_port_unlock - Unlock the UART port 644 + * @up: Pointer to UART port structure 645 + */ 646 + static inline void uart_port_unlock(struct uart_port *up) 647 + { 648 + spin_unlock(&up->lock); 649 + } 650 + 651 + /** 652 + * uart_port_unlock_irq - Unlock the UART port and re-enable interrupts 653 + * @up: Pointer to UART port structure 654 + */ 655 + static inline void uart_port_unlock_irq(struct uart_port *up) 656 + { 657 + spin_unlock_irq(&up->lock); 658 + } 659 + 660 + /** 661 + * uart_port_unlock_irqrestore - Unlock the UART port, restore interrupts 662 + * @up: Pointer to UART port structure 663 + * @flags: The saved interrupt flags for restore 664 + */ 665 + static inline void uart_port_unlock_irqrestore(struct uart_port *up, unsigned long flags) 666 + { 667 + spin_unlock_irqrestore(&up->lock, flags); 668 + } 669 + 591 670 static inline int serial_port_in(struct uart_port *up, int offset) 592 671 { 593 672 return up->serial_in(up, offset); ··· 1035 956 u8 sysrq_ch; 1036 957 1037 958 if (!port->has_sysrq) { 1038 - spin_unlock(&port->lock); 959 + uart_port_unlock(port); 1039 960 return; 1040 961 } 1041 962 1042 963 sysrq_ch = port->sysrq_ch; 1043 964 port->sysrq_ch = 0; 1044 965 1045 - spin_unlock(&port->lock); 966 + uart_port_unlock(port); 1046 967 1047 968 if (sysrq_ch) 1048 969 handle_sysrq(sysrq_ch); ··· 1054 975 u8 sysrq_ch; 1055 976 1056 977 if (!port->has_sysrq) { 1057 - spin_unlock_irqrestore(&port->lock, flags); 978 + uart_port_unlock_irqrestore(port, flags); 1058 979 return; 1059 980 } 1060 981 1061 982 sysrq_ch = port->sysrq_ch; 1062 983 port->sysrq_ch = 0; 1063 984 1064 - spin_unlock_irqrestore(&port->lock, flags); 985 + uart_port_unlock_irqrestore(port, flags); 1065 986 1066 987 if (sysrq_ch) 1067 988 handle_sysrq(sysrq_ch); ··· 1077 998 } 1078 999 static inline void uart_unlock_and_check_sysrq(struct uart_port *port) 1079 1000 { 1080 - spin_unlock(&port->lock); 1001 + uart_port_unlock(port); 1081 1002 } 1082 1003 static inline void uart_unlock_and_check_sysrq_irqrestore(struct uart_port *port, 1083 1004 unsigned long flags) 1084 1005 { 1085 - spin_unlock_irqrestore(&port->lock, flags); 1006 + uart_port_unlock_irqrestore(port, flags); 1086 1007 } 1087 1008 #endif /* CONFIG_MAGIC_SYSRQ_SERIAL */ 1088 1009

+11 -14

include/linux/tty.h

··· 390 390 extern const struct class tty_class; 391 391 392 392 /** 393 - * tty_kref_get - get a tty reference 394 - * @tty: tty device 393 + * tty_kref_get - get a tty reference 394 + * @tty: tty device 395 395 * 396 - * Return a new reference to a tty object. The caller must hold 397 - * sufficient locks/counts to ensure that their existing reference cannot 398 - * go away 396 + * Returns: a new reference to a tty object. The caller must hold sufficient 397 + * locks/counts to ensure that their existing reference cannot go away 399 398 */ 400 - 401 399 static inline struct tty_struct *tty_kref_get(struct tty_struct *tty) 402 400 { 403 401 if (tty) ··· 414 416 unsigned int tty_write_room(struct tty_struct *tty); 415 417 void tty_driver_flush_buffer(struct tty_struct *tty); 416 418 void tty_unthrottle(struct tty_struct *tty); 417 - int tty_throttle_safe(struct tty_struct *tty); 418 - int tty_unthrottle_safe(struct tty_struct *tty); 419 + bool tty_throttle_safe(struct tty_struct *tty); 420 + bool tty_unthrottle_safe(struct tty_struct *tty); 419 421 int tty_do_resize(struct tty_struct *tty, struct winsize *ws); 420 422 int tty_get_icount(struct tty_struct *tty, 421 423 struct serial_icounter_struct *icount); ··· 433 435 speed_t obaud); 434 436 435 437 /** 436 - * tty_get_baud_rate - get tty bit rates 437 - * @tty: tty to query 438 + * tty_get_baud_rate - get tty bit rates 439 + * @tty: tty to query 438 440 * 439 - * Returns the baud rate as an integer for this terminal. The 440 - * termios lock must be held by the caller and the terminal bit 441 - * flags may be updated. 441 + * Returns: the baud rate as an integer for this terminal. The termios lock 442 + * must be held by the caller and the terminal bit flags may be updated. 442 443 * 443 - * Locking: none 444 + * Locking: none 444 445 */ 445 446 static inline speed_t tty_get_baud_rate(struct tty_struct *tty) 446 447 {

+1

include/uapi/linux/gsmmux.h

+5 -16

include/uapi/linux/serial_core.h

··· 1 1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ 2 2 /* 3 - * linux/drivers/char/serial_core.h 4 - * 5 3 * Copyright (C) 2000 Deep Blue Solutions Ltd. 6 - * 7 - * This program is free software; you can redistribute it and/or modify 8 - * it under the terms of the GNU General Public License as published by 9 - * the Free Software Foundation; either version 2 of the License, or 10 - * (at your option) any later version. 11 - * 12 - * This program is distributed in the hope that it will be useful, 13 - * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 - * GNU General Public License for more details. 16 - * 17 - * You should have received a copy of the GNU General Public License 18 - * along with this program; if not, write to the Free Software 19 - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 4 */ 21 5 #ifndef _UAPILINUX_SERIAL_CORE_H 22 6 #define _UAPILINUX_SERIAL_CORE_H ··· 11 27 * The type definitions. These are from Ted Ts'o's serial.h 12 28 * By historical reasons the values from 0 to 13 are defined 13 29 * in the include/uapi/linux/serial.h, do not define them here. 30 + * Values 0 to 19 are used by setserial from busybox and must never 31 + * be modified. 14 32 */ 15 33 #define PORT_NS16550A 14 16 34 #define PORT_XSCALE 15 ··· 230 244 231 245 /* Sunplus UART */ 232 246 #define PORT_SUNPLUS 123 247 + 248 + /* Generic type identifier for ports which type is not important to userspace. */ 249 + #define PORT_GENERIC (-1) 233 250 234 251 #endif /* _UAPILINUX_SERIAL_CORE_H */

+1

include/uapi/linux/serial_reg.h

··· 49 49 #define UART_IIR_FIFO_ENABLED_8250 0x00 /* 8250: no FIFO */ 50 50 #define UART_IIR_FIFO_ENABLED_16550 0x80 /* 16550: (broken/unusable) FIFO */ 51 51 #define UART_IIR_FIFO_ENABLED_16550A 0xc0 /* 16550A: FIFO enabled */ 52 + #define UART_IIR_FIFO_ENABLED_16750 0xe0 /* 16750: 64 bytes FIFO enabled */ 52 53 53 54 #define UART_FCR 2 /* Out: FIFO Control Register */ 54 55 #define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */

+10 -2

kernel/printk/printk.c

··· 2384 2384 console_set_on_cmdline = 1; 2385 2385 } 2386 2386 2387 - static int __add_preferred_console(char *name, int idx, char *options, 2387 + static int __add_preferred_console(const char *name, const short idx, char *options, 2388 2388 char *brl_options, bool user_specified) 2389 2389 { 2390 2390 struct console_cmdline *c; 2391 2391 int i; 2392 + 2393 + /* 2394 + * We use a signed short index for struct console for device drivers to 2395 + * indicate a not yet assigned index or port. However, a negative index 2396 + * value is not valid for preferred console. 2397 + */ 2398 + if (idx < 0) 2399 + return -EINVAL; 2392 2400 2393 2401 /* 2394 2402 * See if this tty is not yet registered, and ··· 2501 2493 * commonly to provide a default console (ie from PROM variables) when 2502 2494 * the user has not supplied one. 2503 2495 */ 2504 - int add_preferred_console(char *name, int idx, char *options) 2496 + int add_preferred_console(const char *name, const short idx, char *options) 2505 2497 { 2506 2498 return __add_preferred_console(name, idx, options, NULL, false); 2507 2499 }

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