mips: pci-mt7620: rework initialization procedure

Move the reset operation to the common part to reduce the code
redundancy. They are actually the same and needed for all SoCs.
Disabling power and clock are unnecessary for MT7620 and will be
removed. In vendor SDK, it's used to save the power when the PCI
driver is not selected. The MT7628 GPIO pinctrl has been removed
because this should be done in device-tree. Some delay intervals
have also been increased to follow the recommendations of the SoC
SDK and datasheet. Tested on both MT7620 and MT7628.

Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

authored by

Shiji Yang and committed by

Thomas Bogendoerfer 2 months ago 2300d68e c2631cc4

+13 -25

1 changed file

expand all

arch

mips

pci

pci-mt7620.c

+13 -25

arch/mips/pci/pci-mt7620.c

··· 29 29 #define RALINK_SYSCFG0 0x10 30 30 #define RALINK_SYSCFG0_XTAL40 BIT(6) 31 31 #define RALINK_CLKCFG1 0x30 32 - #define RALINK_GPIOMODE 0x60 33 32 34 33 #define PPLL_CFG1 0x9c 35 34 #define PPLL_LD BIT(23) ··· 245 246 /* Elastic buffer control */ 246 247 pcie_phy(0x68, 0xB4); 247 248 248 - /* put core into reset */ 249 - bridge_m32(PCIRST, PCIRST, RALINK_PCI_PCICFG_ADDR); 250 - reset_control_assert(rstpcie0); 251 - 252 - /* disable power and all clocks */ 253 - rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1); 254 - rt_sysc_m32(LC_CKDRVPD, PDRV_SW_SET, PPLL_DRV); 255 - 256 - /* bring core out of reset */ 257 - reset_control_deassert(rstpcie0); 258 - rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1); 259 - mdelay(100); 260 - 261 249 if (!(rt_sysc_r32(PPLL_CFG1) & PPLL_LD)) { 262 250 dev_err(&pdev->dev, "pcie PLL not locked, aborting init\n"); 263 251 reset_control_assert(rstpcie0); ··· 261 275 262 276 static void mt7628_pci_hw_init(struct platform_device *pdev) 263 277 { 264 - /* bring the core out of reset */ 265 - rt_sysc_m32(BIT(16), 0, RALINK_GPIOMODE); 266 - reset_control_deassert(rstpcie0); 267 - 268 - /* enable the pci clk */ 269 - rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1); 270 - mdelay(100); 271 - 272 278 /* voodoo from the SDK driver */ 273 279 pcie_phyctrl_set(0x400, 8, 1, 0x1); 274 280 pcie_phyctrl_set(0x400, 9, 2, 0x0); ··· 312 334 ioport_resource.start = 0; 313 335 ioport_resource.end = ~0; 314 336 337 + /* reset PCIe controller */ 338 + reset_control_assert(rstpcie0); 339 + msleep(100); 340 + reset_control_deassert(rstpcie0); 341 + rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1); 342 + msleep(100); 343 + 344 + /* assert PERST_N pin */ 345 + bridge_m32(PCIRST, PCIRST, RALINK_PCI_PCICFG_ADDR); 346 + 315 347 /* bring up the pci core */ 316 348 switch (ralink_soc) { 317 349 case MT762X_SOC_MT7620A: ··· 338 350 dev_err(&pdev->dev, "pcie is not supported on this hardware\n"); 339 351 return -1; 340 352 } 341 - mdelay(50); 353 + msleep(500); 342 354 343 - /* enable write access */ 355 + /* deassert PERST_N pin and wait PCIe peripheral init */ 344 356 bridge_m32(PCIRST, 0, RALINK_PCI_PCICFG_ADDR); 345 - mdelay(100); 357 + msleep(1000); 346 358 347 359 /* check if there is a card present */ 348 360 if ((pcie_r32(RALINK_PCI0_STATUS) & PCIE_LINK_UP_ST) == 0) {

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