Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
x86/apic: Avoid the PVOPS indirection for the TSC deadline timer
XEN PV does not emulate the TSC deadline timer, so the PVOPS indirection
for writing the deadline MSR can be avoided completely.
Use native_wrmsrq() instead.
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://patch.msgid.link/20260224163429.877429827@kernel.org
authored by
Thomas Gleixner
and committed by
Peter Zijlstra
23028286
92d0e753
+10
-3
+10
-3
arch/x86/kernel/apic/apic.c
+10
-3
arch/x86/kernel/apic/apic.c
···
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*/
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u64 tsc = rdtsc();
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-
wrmsrq(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR));
429
+
native_wrmsrq(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR));
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return 0;
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}
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···
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* the timer _and_ zero the counter registers:
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*/
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if (v & APIC_LVT_TIMER_TSCDEADLINE)
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-
wrmsrq(MSR_IA32_TSC_DEADLINE, 0);
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+
native_wrmsrq(MSR_IA32_TSC_DEADLINE, 0);
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else
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apic_write(APIC_TMICT, 0);
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456
···
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if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
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return false;
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+
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+
/* XEN_PV does not support it, but be paranoia about it */
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+
if (boot_cpu_has(X86_FEATURE_XENPV))
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+
goto clear;
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+
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if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
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return true;
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···
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if (boot_cpu_data.microcode >= rev)
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return true;
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-
setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
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pr_err(FW_BUG "TSC_DEADLINE disabled due to Errata; "
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"please update microcode to version: 0x%x (or later)\n", rev);
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+
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+
clear:
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+
setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
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return false;
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}
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569