Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/i915: move and rename reg_in_range_table
reg_in_range_table is a useful function that is used in multiple places,
and will be needed for WA_BB implementation later.
Let's move this function and i915_range struct to its own file, as we are
trying to move away from i915_utils files.
v2: move functions to their own file
v3: use correct naming convention
Suggested-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
Link:
https://lore.kernel.org/r/20251009215210.41000-1-matthew.s.atwood@intel.com
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
authored by
Matt Atwood
and committed by
Rodrigo Vivi
27e21516
08c54f3c
+82
-59
+1
drivers/gpu/drm/i915/Makefile
+1
drivers/gpu/drm/i915/Makefile
+5
-4
drivers/gpu/drm/i915/gt/intel_workarounds.c
+5
-4
drivers/gpu/drm/i915/gt/intel_workarounds.c
···
5
5
6
6
#include "i915_drv.h"
7
7
#include "i915_reg.h"
8
+
#include "i915_mmio_range.h"
8
9
#include "intel_context.h"
9
10
#include "intel_engine_pm.h"
10
11
#include "intel_engine_regs.h"
···
2924
2923
wa_list_apply(&engine->wa_list);
2925
2924
}
2926
2925
2927
-
static const struct i915_range mcr_ranges_gen8[] = {
2926
+
static const struct i915_mmio_range mcr_ranges_gen8[] = {
2928
2927
{ .start = 0x5500, .end = 0x55ff },
2929
2928
{ .start = 0x7000, .end = 0x7fff },
2930
2929
{ .start = 0x9400, .end = 0x97ff },
···
2933
2932
{},
2934
2933
};
2935
2934
2936
-
static const struct i915_range mcr_ranges_gen12[] = {
2935
+
static const struct i915_mmio_range mcr_ranges_gen12[] = {
2937
2936
{ .start = 0x8150, .end = 0x815f },
2938
2937
{ .start = 0x9520, .end = 0x955f },
2939
2938
{ .start = 0xb100, .end = 0xb3ff },
···
2942
2941
{},
2943
2942
};
2944
2943
2945
-
static const struct i915_range mcr_ranges_xehp[] = {
2944
+
static const struct i915_mmio_range mcr_ranges_xehp[] = {
2946
2945
{ .start = 0x4000, .end = 0x4aff },
2947
2946
{ .start = 0x5200, .end = 0x52ff },
2948
2947
{ .start = 0x5400, .end = 0x7fff },
···
2961
2960
2962
2961
static bool mcr_range(struct drm_i915_private *i915, u32 offset)
2963
2962
{
2964
-
const struct i915_range *mcr_ranges;
2963
+
const struct i915_mmio_range *mcr_ranges;
2965
2964
int i;
2966
2965
2967
2966
if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55))
+18
drivers/gpu/drm/i915/i915_mmio_range.c
+18
drivers/gpu/drm/i915/i915_mmio_range.c
···
1
+
// SPDX-License-Identifier: MIT
2
+
/*
3
+
* Copyright © 2025 Intel Corporation
4
+
*/
5
+
6
+
#include "i915_mmio_range.h"
7
+
8
+
bool i915_mmio_range_table_contains(u32 addr, const struct i915_mmio_range *table)
9
+
{
10
+
while (table->start || table->end) {
11
+
if (addr >= table->start && addr <= table->end)
12
+
return true;
13
+
14
+
table++;
15
+
}
16
+
17
+
return false;
18
+
}
+19
drivers/gpu/drm/i915/i915_mmio_range.h
+19
drivers/gpu/drm/i915/i915_mmio_range.h
···
1
+
/* SPDX-License-Identifier: MIT */
2
+
/*
3
+
* Copyright © 2025 Intel Corporation
4
+
*/
5
+
6
+
#ifndef __I915_MMIO_RANGE_H__
7
+
#define __I915_MMIO_RANGE_H__
8
+
9
+
#include <linux/types.h>
10
+
11
+
/* Other register ranges (e.g., shadow tables, MCR tables, etc.) */
12
+
struct i915_mmio_range {
13
+
u32 start;
14
+
u32 end;
15
+
};
16
+
17
+
bool i915_mmio_range_table_contains(u32 addr, const struct i915_mmio_range *table);
18
+
19
+
#endif /* __I915_MMIO_RANGE_H__ */
+28
-39
drivers/gpu/drm/i915/i915_perf.c
+28
-39
drivers/gpu/drm/i915/i915_perf.c
···
219
219
#include "i915_perf.h"
220
220
#include "i915_perf_oa_regs.h"
221
221
#include "i915_reg.h"
222
+
#include "i915_mmio_range.h"
222
223
223
224
/* HW requires this to be a power of two, between 128k and 16M, though driver
224
225
* is currently generally designed assuming the largest 16M size is used such
···
4321
4320
return false;
4322
4321
}
4323
4322
4324
-
static bool reg_in_range_table(u32 addr, const struct i915_range *table)
4325
-
{
4326
-
while (table->start || table->end) {
4327
-
if (addr >= table->start && addr <= table->end)
4328
-
return true;
4329
-
4330
-
table++;
4331
-
}
4332
-
4333
-
return false;
4334
-
}
4335
-
4336
4323
#define REG_EQUAL(addr, mmio) \
4337
4324
((addr) == i915_mmio_reg_offset(mmio))
4338
4325
4339
-
static const struct i915_range gen7_oa_b_counters[] = {
4326
+
static const struct i915_mmio_range gen7_oa_b_counters[] = {
4340
4327
{ .start = 0x2710, .end = 0x272c }, /* OASTARTTRIG[1-8] */
4341
4328
{ .start = 0x2740, .end = 0x275c }, /* OAREPORTTRIG[1-8] */
4342
4329
{ .start = 0x2770, .end = 0x27ac }, /* OACEC[0-7][0-1] */
4343
4330
{}
4344
4331
};
4345
4332
4346
-
static const struct i915_range gen12_oa_b_counters[] = {
4333
+
static const struct i915_mmio_range gen12_oa_b_counters[] = {
4347
4334
{ .start = 0x2b2c, .end = 0x2b2c }, /* GEN12_OAG_OA_PESS */
4348
4335
{ .start = 0xd900, .end = 0xd91c }, /* GEN12_OAG_OASTARTTRIG[1-8] */
4349
4336
{ .start = 0xd920, .end = 0xd93c }, /* GEN12_OAG_OAREPORTTRIG1[1-8] */
···
4342
4353
{}
4343
4354
};
4344
4355
4345
-
static const struct i915_range mtl_oam_b_counters[] = {
4356
+
static const struct i915_mmio_range mtl_oam_b_counters[] = {
4346
4357
{ .start = 0x393000, .end = 0x39301c }, /* GEN12_OAM_STARTTRIG1[1-8] */
4347
4358
{ .start = 0x393020, .end = 0x39303c }, /* GEN12_OAM_REPORTTRIG1[1-8] */
4348
4359
{ .start = 0x393040, .end = 0x39307c }, /* GEN12_OAM_CEC[0-7][0-1] */
···
4350
4361
{}
4351
4362
};
4352
4363
4353
-
static const struct i915_range xehp_oa_b_counters[] = {
4364
+
static const struct i915_mmio_range xehp_oa_b_counters[] = {
4354
4365
{ .start = 0xdc48, .end = 0xdc48 }, /* OAA_ENABLE_REG */
4355
4366
{ .start = 0xdd00, .end = 0xdd48 }, /* OAG_LCE0_0 - OAA_LENABLE_REG */
4356
4367
{}
4357
4368
};
4358
4369
4359
-
static const struct i915_range gen7_oa_mux_regs[] = {
4370
+
static const struct i915_mmio_range gen7_oa_mux_regs[] = {
4360
4371
{ .start = 0x91b8, .end = 0x91cc }, /* OA_PERFCNT[1-2], OA_PERFMATRIX */
4361
4372
{ .start = 0x9800, .end = 0x9888 }, /* MICRO_BP0_0 - NOA_WRITE */
4362
4373
{ .start = 0xe180, .end = 0xe180 }, /* HALF_SLICE_CHICKEN2 */
4363
4374
{}
4364
4375
};
4365
4376
4366
-
static const struct i915_range hsw_oa_mux_regs[] = {
4377
+
static const struct i915_mmio_range hsw_oa_mux_regs[] = {
4367
4378
{ .start = 0x09e80, .end = 0x09ea4 }, /* HSW_MBVID2_NOA[0-9] */
4368
4379
{ .start = 0x09ec0, .end = 0x09ec0 }, /* HSW_MBVID2_MISR0 */
4369
4380
{ .start = 0x25100, .end = 0x2ff90 },
4370
4381
{}
4371
4382
};
4372
4383
4373
-
static const struct i915_range chv_oa_mux_regs[] = {
4384
+
static const struct i915_mmio_range chv_oa_mux_regs[] = {
4374
4385
{ .start = 0x182300, .end = 0x1823a4 },
4375
4386
{}
4376
4387
};
4377
4388
4378
-
static const struct i915_range gen8_oa_mux_regs[] = {
4389
+
static const struct i915_mmio_range gen8_oa_mux_regs[] = {
4379
4390
{ .start = 0x0d00, .end = 0x0d2c }, /* RPM_CONFIG[0-1], NOA_CONFIG[0-8] */
4380
4391
{ .start = 0x20cc, .end = 0x20cc }, /* WAIT_FOR_RC6_EXIT */
4381
4392
{}
4382
4393
};
4383
4394
4384
-
static const struct i915_range gen11_oa_mux_regs[] = {
4395
+
static const struct i915_mmio_range gen11_oa_mux_regs[] = {
4385
4396
{ .start = 0x91c8, .end = 0x91dc }, /* OA_PERFCNT[3-4] */
4386
4397
{}
4387
4398
};
4388
4399
4389
-
static const struct i915_range gen12_oa_mux_regs[] = {
4400
+
static const struct i915_mmio_range gen12_oa_mux_regs[] = {
4390
4401
{ .start = 0x0d00, .end = 0x0d04 }, /* RPM_CONFIG[0-1] */
4391
4402
{ .start = 0x0d0c, .end = 0x0d2c }, /* NOA_CONFIG[0-8] */
4392
4403
{ .start = 0x9840, .end = 0x9840 }, /* GDT_CHICKEN_BITS */
···
4399
4410
* Ref: 14010536224:
4400
4411
* 0x20cc is repurposed on MTL, so use a separate array for MTL.
4401
4412
*/
4402
-
static const struct i915_range mtl_oa_mux_regs[] = {
4413
+
static const struct i915_mmio_range mtl_oa_mux_regs[] = {
4403
4414
{ .start = 0x0d00, .end = 0x0d04 }, /* RPM_CONFIG[0-1] */
4404
4415
{ .start = 0x0d0c, .end = 0x0d2c }, /* NOA_CONFIG[0-8] */
4405
4416
{ .start = 0x9840, .end = 0x9840 }, /* GDT_CHICKEN_BITS */
···
4410
4421
4411
4422
static bool gen7_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
4412
4423
{
4413
-
return reg_in_range_table(addr, gen7_oa_b_counters);
4424
+
return i915_mmio_range_table_contains(addr, gen7_oa_b_counters);
4414
4425
}
4415
4426
4416
4427
static bool gen8_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
4417
4428
{
4418
-
return reg_in_range_table(addr, gen7_oa_mux_regs) ||
4419
-
reg_in_range_table(addr, gen8_oa_mux_regs);
4429
+
return i915_mmio_range_table_contains(addr, gen7_oa_mux_regs) ||
4430
+
i915_mmio_range_table_contains(addr, gen8_oa_mux_regs);
4420
4431
}
4421
4432
4422
4433
static bool gen11_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
4423
4434
{
4424
-
return reg_in_range_table(addr, gen7_oa_mux_regs) ||
4425
-
reg_in_range_table(addr, gen8_oa_mux_regs) ||
4426
-
reg_in_range_table(addr, gen11_oa_mux_regs);
4435
+
return i915_mmio_range_table_contains(addr, gen7_oa_mux_regs) ||
4436
+
i915_mmio_range_table_contains(addr, gen8_oa_mux_regs) ||
4437
+
i915_mmio_range_table_contains(addr, gen11_oa_mux_regs);
4427
4438
}
4428
4439
4429
4440
static bool hsw_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
4430
4441
{
4431
-
return reg_in_range_table(addr, gen7_oa_mux_regs) ||
4432
-
reg_in_range_table(addr, hsw_oa_mux_regs);
4442
+
return i915_mmio_range_table_contains(addr, gen7_oa_mux_regs) ||
4443
+
i915_mmio_range_table_contains(addr, hsw_oa_mux_regs);
4433
4444
}
4434
4445
4435
4446
static bool chv_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
4436
4447
{
4437
-
return reg_in_range_table(addr, gen7_oa_mux_regs) ||
4438
-
reg_in_range_table(addr, chv_oa_mux_regs);
4448
+
return i915_mmio_range_table_contains(addr, gen7_oa_mux_regs) ||
4449
+
i915_mmio_range_table_contains(addr, chv_oa_mux_regs);
4439
4450
}
4440
4451
4441
4452
static bool gen12_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
4442
4453
{
4443
-
return reg_in_range_table(addr, gen12_oa_b_counters);
4454
+
return i915_mmio_range_table_contains(addr, gen12_oa_b_counters);
4444
4455
}
4445
4456
4446
4457
static bool mtl_is_valid_oam_b_counter_addr(struct i915_perf *perf, u32 addr)
4447
4458
{
4448
4459
if (HAS_OAM(perf->i915) &&
4449
4460
GRAPHICS_VER_FULL(perf->i915) >= IP_VER(12, 70))
4450
-
return reg_in_range_table(addr, mtl_oam_b_counters);
4461
+
return i915_mmio_range_table_contains(addr, mtl_oam_b_counters);
4451
4462
4452
4463
return false;
4453
4464
}
4454
4465
4455
4466
static bool xehp_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
4456
4467
{
4457
-
return reg_in_range_table(addr, xehp_oa_b_counters) ||
4458
-
reg_in_range_table(addr, gen12_oa_b_counters) ||
4468
+
return i915_mmio_range_table_contains(addr, xehp_oa_b_counters) ||
4469
+
i915_mmio_range_table_contains(addr, gen12_oa_b_counters) ||
4459
4470
mtl_is_valid_oam_b_counter_addr(perf, addr);
4460
4471
}
4461
4472
4462
4473
static bool gen12_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
4463
4474
{
4464
4475
if (GRAPHICS_VER_FULL(perf->i915) >= IP_VER(12, 70))
4465
-
return reg_in_range_table(addr, mtl_oa_mux_regs);
4476
+
return i915_mmio_range_table_contains(addr, mtl_oa_mux_regs);
4466
4477
else
4467
-
return reg_in_range_table(addr, gen12_oa_mux_regs);
4478
+
return i915_mmio_range_table_contains(addr, gen12_oa_mux_regs);
4468
4479
}
4469
4480
4470
4481
static u32 mask_reg_value(u32 reg, u32 val)
+8
-7
drivers/gpu/drm/i915/intel_uncore.c
+8
-7
drivers/gpu/drm/i915/intel_uncore.c
···
35
35
#include "i915_reg.h"
36
36
#include "i915_vgpu.h"
37
37
#include "i915_wait_util.h"
38
+
#include "i915_mmio_range.h"
38
39
#include "intel_uncore_trace.h"
39
40
40
41
#define FORCEWAKE_ACK_TIMEOUT_MS 50
···
1000
999
* scanned for obvious mistakes or typos by the selftests.
1001
1000
*/
1002
1001
1003
-
static const struct i915_range gen8_shadowed_regs[] = {
1002
+
static const struct i915_mmio_range gen8_shadowed_regs[] = {
1004
1003
{ .start = 0x2030, .end = 0x2030 },
1005
1004
{ .start = 0xA008, .end = 0xA00C },
1006
1005
{ .start = 0x12030, .end = 0x12030 },
···
1008
1007
{ .start = 0x22030, .end = 0x22030 },
1009
1008
};
1010
1009
1011
-
static const struct i915_range gen11_shadowed_regs[] = {
1010
+
static const struct i915_mmio_range gen11_shadowed_regs[] = {
1012
1011
{ .start = 0x2030, .end = 0x2030 },
1013
1012
{ .start = 0x2550, .end = 0x2550 },
1014
1013
{ .start = 0xA008, .end = 0xA00C },
···
1035
1034
{ .start = 0x1D8510, .end = 0x1D8550 },
1036
1035
};
1037
1036
1038
-
static const struct i915_range gen12_shadowed_regs[] = {
1037
+
static const struct i915_mmio_range gen12_shadowed_regs[] = {
1039
1038
{ .start = 0x2030, .end = 0x2030 },
1040
1039
{ .start = 0x2510, .end = 0x2550 },
1041
1040
{ .start = 0xA008, .end = 0xA00C },
···
1079
1078
{ .start = 0x1F8510, .end = 0x1F8550 },
1080
1079
};
1081
1080
1082
-
static const struct i915_range dg2_shadowed_regs[] = {
1081
+
static const struct i915_mmio_range dg2_shadowed_regs[] = {
1083
1082
{ .start = 0x2030, .end = 0x2030 },
1084
1083
{ .start = 0x2510, .end = 0x2550 },
1085
1084
{ .start = 0xA008, .end = 0xA00C },
···
1118
1117
{ .start = 0x1F8510, .end = 0x1F8550 },
1119
1118
};
1120
1119
1121
-
static const struct i915_range mtl_shadowed_regs[] = {
1120
+
static const struct i915_mmio_range mtl_shadowed_regs[] = {
1122
1121
{ .start = 0x2030, .end = 0x2030 },
1123
1122
{ .start = 0x2510, .end = 0x2550 },
1124
1123
{ .start = 0xA008, .end = 0xA00C },
···
1136
1135
{ .start = 0x22510, .end = 0x22550 },
1137
1136
};
1138
1137
1139
-
static const struct i915_range xelpmp_shadowed_regs[] = {
1138
+
static const struct i915_mmio_range xelpmp_shadowed_regs[] = {
1140
1139
{ .start = 0x1C0030, .end = 0x1C0030 },
1141
1140
{ .start = 0x1C0510, .end = 0x1C0550 },
1142
1141
{ .start = 0x1C8030, .end = 0x1C8030 },
···
1157
1156
{ .start = 0x38CFD4, .end = 0x38CFDC },
1158
1157
};
1159
1158
1160
-
static int mmio_range_cmp(u32 key, const struct i915_range *range)
1159
+
static int mmio_range_cmp(u32 key, const struct i915_mmio_range *range)
1161
1160
{
1162
1161
if (key < range->start)
1163
1162
return -1;
+1
-7
drivers/gpu/drm/i915/intel_uncore.h
+1
-7
drivers/gpu/drm/i915/intel_uncore.h
···
123
123
enum forcewake_domains domains;
124
124
};
125
125
126
-
/* Other register ranges (e.g., shadow tables, MCR tables, etc.) */
127
-
struct i915_range {
128
-
u32 start;
129
-
u32 end;
130
-
};
131
-
132
126
struct intel_uncore {
133
127
void __iomem *regs;
134
128
···
156
162
* Shadowed registers are special cases where we can safely write
157
163
* to the register *without* grabbing forcewake.
158
164
*/
159
-
const struct i915_range *shadowed_reg_table;
165
+
const struct i915_mmio_range *shadowed_reg_table;
160
166
unsigned int shadowed_reg_table_entries;
161
167
162
168
struct notifier_block pmic_bus_access_nb;
+2
-2
drivers/gpu/drm/i915/selftests/intel_uncore.c
+2
-2
drivers/gpu/drm/i915/selftests/intel_uncore.c
···
64
64
static int intel_shadow_table_check(void)
65
65
{
66
66
struct {
67
-
const struct i915_range *regs;
67
+
const struct i915_mmio_range *regs;
68
68
unsigned int size;
69
69
} range_lists[] = {
70
70
{ gen8_shadowed_regs, ARRAY_SIZE(gen8_shadowed_regs) },
···
74
74
{ mtl_shadowed_regs, ARRAY_SIZE(mtl_shadowed_regs) },
75
75
{ xelpmp_shadowed_regs, ARRAY_SIZE(xelpmp_shadowed_regs) },
76
76
};
77
-
const struct i915_range *range;
77
+
const struct i915_mmio_range *range;
78
78
unsigned int i, j;
79
79
s32 prev;
80
80