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clk: imx: remove clk_count of imx_register_uart_clocks

The clk count has been get with of_clk_get_parent_count, there is
no need to pass clk_count from users.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20230104110032.1220721-4-peng.fan@oss.nxp.com

authored by

Peng Fan and committed by
Abel Vesa
2d5513bf 8658f0ac

+21 -21
+1 -1
drivers/clk/imx/clk-imx25.c
··· 218 218 */ 219 219 clk_set_parent(clk[cko_sel], clk[ipg]); 220 220 221 - imx_register_uart_clocks(6); 221 + imx_register_uart_clocks(); 222 222 223 223 return 0; 224 224 }
+1 -1
drivers/clk/imx/clk-imx27.c
··· 165 165 166 166 clk_prepare_enable(clk[IMX27_CLK_EMI_AHB_GATE]); 167 167 168 - imx_register_uart_clocks(7); 168 + imx_register_uart_clocks(); 169 169 170 170 imx_print_silicon_rev("i.MX27", mx27_revision()); 171 171 }
+1 -1
drivers/clk/imx/clk-imx35.c
··· 235 235 */ 236 236 clk_prepare_enable(clk[scc_gate]); 237 237 238 - imx_register_uart_clocks(4); 238 + imx_register_uart_clocks(); 239 239 240 240 imx_print_silicon_rev("i.MX35", mx35_revision()); 241 241 }
+3 -3
drivers/clk/imx/clk-imx5.c
··· 358 358 r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000); 359 359 clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r); 360 360 361 - imx_register_uart_clocks(5); 361 + imx_register_uart_clocks(); 362 362 } 363 363 CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init); 364 364 ··· 464 464 val |= 1 << 23; 465 465 writel(val, MXC_CCM_CLPCR); 466 466 467 - imx_register_uart_clocks(3); 467 + imx_register_uart_clocks(); 468 468 } 469 469 CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init); 470 470 ··· 609 609 r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000); 610 610 clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r); 611 611 612 - imx_register_uart_clocks(5); 612 + imx_register_uart_clocks(); 613 613 } 614 614 CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init);
+1 -1
drivers/clk/imx/clk-imx6q.c
··· 974 974 hws[IMX6QDL_CLK_PLL3_USB_OTG]->clk); 975 975 } 976 976 977 - imx_register_uart_clocks(2); 977 + imx_register_uart_clocks(); 978 978 } 979 979 CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init);
+1 -1
drivers/clk/imx/clk-imx6sl.c
··· 440 440 clk_set_parent(hws[IMX6SL_CLK_LCDIF_AXI_SEL]->clk, 441 441 hws[IMX6SL_CLK_PLL2_PFD2]->clk); 442 442 443 - imx_register_uart_clocks(2); 443 + imx_register_uart_clocks(); 444 444 } 445 445 CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init);
+1 -1
drivers/clk/imx/clk-imx6sll.c
··· 340 340 341 341 of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data); 342 342 343 - imx_register_uart_clocks(5); 343 + imx_register_uart_clocks(); 344 344 345 345 /* Lower the AHB clock rate before changing the clock source. */ 346 346 clk_set_rate(hws[IMX6SLL_CLK_AHB]->clk, 99000000);
+1 -1
drivers/clk/imx/clk-imx6sx.c
··· 548 548 clk_set_parent(hws[IMX6SX_CLK_QSPI1_SEL]->clk, hws[IMX6SX_CLK_PLL2_BUS]->clk); 549 549 clk_set_parent(hws[IMX6SX_CLK_QSPI2_SEL]->clk, hws[IMX6SX_CLK_PLL2_BUS]->clk); 550 550 551 - imx_register_uart_clocks(2); 551 + imx_register_uart_clocks(); 552 552 } 553 553 CLK_OF_DECLARE(imx6sx, "fsl,imx6sx-ccm", imx6sx_clocks_init);
+1 -1
drivers/clk/imx/clk-imx7d.c
··· 882 882 hws[IMX7D_USB1_MAIN_480M_CLK] = imx_clk_hw_fixed_factor("pll_usb1_main_clk", "osc", 20, 1); 883 883 hws[IMX7D_USB_MAIN_480M_CLK] = imx_clk_hw_fixed_factor("pll_usb_main_clk", "osc", 20, 1); 884 884 885 - imx_register_uart_clocks(7); 885 + imx_register_uart_clocks(); 886 886 887 887 } 888 888 CLK_OF_DECLARE(imx7d, "fsl,imx7d-ccm", imx7d_clocks_init);
+2 -2
drivers/clk/imx/clk-imx7ulp.c
··· 176 176 177 177 of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data); 178 178 179 - imx_register_uart_clocks(2); 179 + imx_register_uart_clocks(); 180 180 } 181 181 CLK_OF_DECLARE(imx7ulp_clk_pcc2, "fsl,imx7ulp-pcc2", imx7ulp_clk_pcc2_init); 182 182 ··· 223 223 224 224 of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data); 225 225 226 - imx_register_uart_clocks(7); 226 + imx_register_uart_clocks(); 227 227 } 228 228 CLK_OF_DECLARE(imx7ulp_clk_pcc3, "fsl,imx7ulp-pcc3", imx7ulp_clk_pcc3_init); 229 229
+1 -1
drivers/clk/imx/clk-imx8mm.c
··· 609 609 goto unregister_hws; 610 610 } 611 611 612 - imx_register_uart_clocks(4); 612 + imx_register_uart_clocks(); 613 613 614 614 return 0; 615 615
+1 -1
drivers/clk/imx/clk-imx8mn.c
··· 602 602 goto unregister_hws; 603 603 } 604 604 605 - imx_register_uart_clocks(4); 605 + imx_register_uart_clocks(); 606 606 607 607 return 0; 608 608
+1 -1
drivers/clk/imx/clk-imx8mp.c
··· 723 723 724 724 of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data); 725 725 726 - imx_register_uart_clocks(4); 726 + imx_register_uart_clocks(); 727 727 728 728 return 0; 729 729 }
+1 -1
drivers/clk/imx/clk-imx8mq.c
··· 601 601 goto unregister_hws; 602 602 } 603 603 604 - imx_register_uart_clocks(4); 604 + imx_register_uart_clocks(); 605 605 606 606 return 0; 607 607
+1 -1
drivers/clk/imx/clk-imx8ulp.c
··· 385 385 if (ret) 386 386 return ret; 387 387 388 - imx_register_uart_clocks(1); 388 + imx_register_uart_clocks(); 389 389 390 390 /* register the pcc3 reset controller */ 391 391 return imx8ulp_pcc_reset_init(pdev, base, pcc3_resets, ARRAY_SIZE(pcc3_resets));
+1 -1
drivers/clk/imx/clk.c
··· 165 165 __setup_param("earlyprintk", imx_keep_uart_earlyprintk, 166 166 imx_keep_uart_clocks_param, 0); 167 167 168 - void imx_register_uart_clocks(unsigned int clk_count) 168 + void imx_register_uart_clocks(void) 169 169 { 170 170 unsigned int num __maybe_unused; 171 171
+2 -2
drivers/clk/imx/clk.h
··· 12 12 void imx_check_clocks(struct clk *clks[], unsigned int count); 13 13 void imx_check_clk_hws(struct clk_hw *clks[], unsigned int count); 14 14 #ifndef MODULE 15 - void imx_register_uart_clocks(unsigned int clk_count); 15 + void imx_register_uart_clocks(void); 16 16 #else 17 - static inline void imx_register_uart_clocks(unsigned int clk_count) 17 + static inline void imx_register_uart_clocks(void) 18 18 { 19 19 } 20 20 #endif