Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'amd-xgbe-add-hardware-ptp-timestamping'
Raju Rangoju says:
====================
amd-xgbe: add hardware PTP timestamping
Remove the hwptp abstraction and associated callbacks from the
struct xgbe_hw_if {} and move them to separate file after cleanup.
Adds complete support for hardware-based PTP (IEEE 1588)
timestamping to the AMD XGBE driver.
====================
Link: https://patch.msgid.link/20250718185628.4038779-1-Raju.Rangoju@amd.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+487
-380
+1
-1
drivers/net/ethernet/amd/xgbe/Makefile
+1
-1
drivers/net/ethernet/amd/xgbe/Makefile
+10
drivers/net/ethernet/amd/xgbe/xgbe-common.h
+10
drivers/net/ethernet/amd/xgbe/xgbe-common.h
···
223
223
#define MAC_TSSR 0x0d20
224
224
#define MAC_TXSNR 0x0d30
225
225
#define MAC_TXSSR 0x0d34
226
+
#define MAC_TICNR 0x0d58
227
+
#define MAC_TICSNR 0x0d5C
228
+
#define MAC_TECNR 0x0d60
229
+
#define MAC_TECSNR 0x0d64
226
230
227
231
#define MAC_QTFCR_INC 4
228
232
#define MAC_MACA_INC 4
···
432
428
#define MAC_TSCR_SNAPTYPSEL_WIDTH 2
433
429
#define MAC_TSCR_TSADDREG_INDEX 5
434
430
#define MAC_TSCR_TSADDREG_WIDTH 1
431
+
#define MAC_TSCR_TSUPDT_INDEX 3
432
+
#define MAC_TSCR_TSUPDT_WIDTH 1
435
433
#define MAC_TSCR_TSCFUPDT_INDEX 1
436
434
#define MAC_TSCR_TSCFUPDT_WIDTH 1
437
435
#define MAC_TSCR_TSCTRLSSR_INDEX 9
···
462
456
#define MAC_TSSR_TXTSC_WIDTH 1
463
457
#define MAC_TXSNR_TXTSSTSMIS_INDEX 31
464
458
#define MAC_TXSNR_TXTSSTSMIS_WIDTH 1
459
+
#define MAC_TICSNR_TSICSNS_INDEX 8
460
+
#define MAC_TICSNR_TSICSNS_WIDTH 8
461
+
#define MAC_TECSNR_TSECSNS_INDEX 8
462
+
#define MAC_TECSNR_TSECSNS_WIDTH 8
465
463
#define MAC_VLANHTR_VLHT_INDEX 0
466
464
#define MAC_VLANHTR_VLHT_WIDTH 16
467
465
#define MAC_VLANIR_VLTI_INDEX 20
-126
drivers/net/ethernet/amd/xgbe/xgbe-dev.c
-126
drivers/net/ethernet/amd/xgbe/xgbe-dev.c
···
1558
1558
DBGPR("<--rx_desc_init\n");
1559
1559
}
1560
1560
1561
-
static void xgbe_update_tstamp_addend(struct xgbe_prv_data *pdata,
1562
-
unsigned int addend)
1563
-
{
1564
-
unsigned int count = 10000;
1565
-
1566
-
/* Set the addend register value and tell the device */
1567
-
XGMAC_IOWRITE(pdata, MAC_TSAR, addend);
1568
-
XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 1);
1569
-
1570
-
/* Wait for addend update to complete */
1571
-
while (--count && XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG))
1572
-
udelay(5);
1573
-
1574
-
if (!count)
1575
-
netdev_err(pdata->netdev,
1576
-
"timed out updating timestamp addend register\n");
1577
-
}
1578
-
1579
-
static void xgbe_set_tstamp_time(struct xgbe_prv_data *pdata, unsigned int sec,
1580
-
unsigned int nsec)
1581
-
{
1582
-
unsigned int count = 10000;
1583
-
1584
-
/* Set the time values and tell the device */
1585
-
XGMAC_IOWRITE(pdata, MAC_STSUR, sec);
1586
-
XGMAC_IOWRITE(pdata, MAC_STNUR, nsec);
1587
-
XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSINIT, 1);
1588
-
1589
-
/* Wait for time update to complete */
1590
-
while (--count && XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT))
1591
-
udelay(5);
1592
-
1593
-
if (!count)
1594
-
netdev_err(pdata->netdev, "timed out initializing timestamp\n");
1595
-
}
1596
-
1597
-
static u64 xgbe_get_tstamp_time(struct xgbe_prv_data *pdata)
1598
-
{
1599
-
u64 nsec;
1600
-
1601
-
nsec = XGMAC_IOREAD(pdata, MAC_STSR);
1602
-
nsec *= NSEC_PER_SEC;
1603
-
nsec += XGMAC_IOREAD(pdata, MAC_STNR);
1604
-
1605
-
return nsec;
1606
-
}
1607
-
1608
-
static u64 xgbe_get_tx_tstamp(struct xgbe_prv_data *pdata)
1609
-
{
1610
-
unsigned int tx_snr, tx_ssr;
1611
-
u64 nsec;
1612
-
1613
-
if (pdata->vdata->tx_tstamp_workaround) {
1614
-
tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR);
1615
-
tx_ssr = XGMAC_IOREAD(pdata, MAC_TXSSR);
1616
-
} else {
1617
-
tx_ssr = XGMAC_IOREAD(pdata, MAC_TXSSR);
1618
-
tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR);
1619
-
}
1620
-
1621
-
if (XGMAC_GET_BITS(tx_snr, MAC_TXSNR, TXTSSTSMIS))
1622
-
return 0;
1623
-
1624
-
nsec = tx_ssr;
1625
-
nsec *= NSEC_PER_SEC;
1626
-
nsec += tx_snr;
1627
-
1628
-
return nsec;
1629
-
}
1630
-
1631
-
static void xgbe_get_rx_tstamp(struct xgbe_packet_data *packet,
1632
-
struct xgbe_ring_desc *rdesc)
1633
-
{
1634
-
u64 nsec;
1635
-
1636
-
if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSA) &&
1637
-
!XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSD)) {
1638
-
nsec = le32_to_cpu(rdesc->desc1);
1639
-
nsec <<= 32;
1640
-
nsec |= le32_to_cpu(rdesc->desc0);
1641
-
if (nsec != 0xffffffffffffffffULL) {
1642
-
packet->rx_tstamp = nsec;
1643
-
XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
1644
-
RX_TSTAMP, 1);
1645
-
}
1646
-
}
1647
-
}
1648
-
1649
-
static int xgbe_config_tstamp(struct xgbe_prv_data *pdata,
1650
-
unsigned int mac_tscr)
1651
-
{
1652
-
/* Set one nano-second accuracy */
1653
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCTRLSSR, 1);
1654
-
1655
-
/* Set fine timestamp update */
1656
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 1);
1657
-
1658
-
/* Overwrite earlier timestamps */
1659
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TXTSSTSM, 1);
1660
-
1661
-
XGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr);
1662
-
1663
-
/* Exit if timestamping is not enabled */
1664
-
if (!XGMAC_GET_BITS(mac_tscr, MAC_TSCR, TSENA))
1665
-
return 0;
1666
-
1667
-
/* Initialize time registers */
1668
-
XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC, XGBE_TSTAMP_SSINC);
1669
-
XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC, XGBE_TSTAMP_SNSINC);
1670
-
xgbe_update_tstamp_addend(pdata, pdata->tstamp_addend);
1671
-
xgbe_set_tstamp_time(pdata, 0, 0);
1672
-
1673
-
/* Initialize the timecounter */
1674
-
timecounter_init(&pdata->tstamp_tc, &pdata->tstamp_cc,
1675
-
ktime_to_ns(ktime_get_real()));
1676
-
1677
-
return 0;
1678
-
}
1679
-
1680
1561
static void xgbe_tx_start_xmit(struct xgbe_channel *channel,
1681
1562
struct xgbe_ring *ring)
1682
1563
{
···
3551
3670
hw_if->tx_mmc_int = xgbe_tx_mmc_int;
3552
3671
hw_if->rx_mmc_int = xgbe_rx_mmc_int;
3553
3672
hw_if->read_mmc_stats = xgbe_read_mmc_stats;
3554
-
3555
-
/* For PTP config */
3556
-
hw_if->config_tstamp = xgbe_config_tstamp;
3557
-
hw_if->update_tstamp_addend = xgbe_update_tstamp_addend;
3558
-
hw_if->set_tstamp_time = xgbe_set_tstamp_time;
3559
-
hw_if->get_tstamp_time = xgbe_get_tstamp_time;
3560
-
hw_if->get_tx_tstamp = xgbe_get_tx_tstamp;
3561
3673
3562
3674
/* For Data Center Bridging config */
3563
3675
hw_if->config_tc = xgbe_config_tc;
+5
-199
drivers/net/ethernet/amd/xgbe/xgbe-drv.c
+5
-199
drivers/net/ethernet/amd/xgbe/xgbe-drv.c
···
448
448
if (XGMAC_GET_BITS(mac_tssr, MAC_TSSR, TXTSC)) {
449
449
/* Read Tx Timestamp to clear interrupt */
450
450
pdata->tx_tstamp =
451
-
hw_if->get_tx_tstamp(pdata);
451
+
xgbe_get_tx_tstamp(pdata);
452
452
queue_work(pdata->dev_workqueue,
453
453
&pdata->tx_tstamp_work);
454
454
}
···
1371
1371
rtnl_unlock();
1372
1372
}
1373
1373
1374
-
static void xgbe_tx_tstamp(struct work_struct *work)
1375
-
{
1376
-
struct xgbe_prv_data *pdata = container_of(work,
1377
-
struct xgbe_prv_data,
1378
-
tx_tstamp_work);
1379
-
struct skb_shared_hwtstamps hwtstamps;
1380
-
u64 nsec;
1381
-
unsigned long flags;
1382
-
1383
-
spin_lock_irqsave(&pdata->tstamp_lock, flags);
1384
-
if (!pdata->tx_tstamp_skb)
1385
-
goto unlock;
1386
-
1387
-
if (pdata->tx_tstamp) {
1388
-
nsec = timecounter_cyc2time(&pdata->tstamp_tc,
1389
-
pdata->tx_tstamp);
1390
-
1391
-
memset(&hwtstamps, 0, sizeof(hwtstamps));
1392
-
hwtstamps.hwtstamp = ns_to_ktime(nsec);
1393
-
skb_tstamp_tx(pdata->tx_tstamp_skb, &hwtstamps);
1394
-
}
1395
-
1396
-
dev_kfree_skb_any(pdata->tx_tstamp_skb);
1397
-
1398
-
pdata->tx_tstamp_skb = NULL;
1399
-
1400
-
unlock:
1401
-
spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
1402
-
}
1403
-
1404
-
static int xgbe_get_hwtstamp_settings(struct xgbe_prv_data *pdata,
1405
-
struct ifreq *ifreq)
1406
-
{
1407
-
if (copy_to_user(ifreq->ifr_data, &pdata->tstamp_config,
1408
-
sizeof(pdata->tstamp_config)))
1409
-
return -EFAULT;
1410
-
1411
-
return 0;
1412
-
}
1413
-
1414
-
static int xgbe_set_hwtstamp_settings(struct xgbe_prv_data *pdata,
1415
-
struct ifreq *ifreq)
1416
-
{
1417
-
struct hwtstamp_config config;
1418
-
unsigned int mac_tscr;
1419
-
1420
-
if (copy_from_user(&config, ifreq->ifr_data, sizeof(config)))
1421
-
return -EFAULT;
1422
-
1423
-
mac_tscr = 0;
1424
-
1425
-
switch (config.tx_type) {
1426
-
case HWTSTAMP_TX_OFF:
1427
-
break;
1428
-
1429
-
case HWTSTAMP_TX_ON:
1430
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1431
-
break;
1432
-
1433
-
default:
1434
-
return -ERANGE;
1435
-
}
1436
-
1437
-
switch (config.rx_filter) {
1438
-
case HWTSTAMP_FILTER_NONE:
1439
-
break;
1440
-
1441
-
case HWTSTAMP_FILTER_NTP_ALL:
1442
-
case HWTSTAMP_FILTER_ALL:
1443
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1);
1444
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1445
-
break;
1446
-
1447
-
/* PTP v2, UDP, any kind of event packet */
1448
-
case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1449
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1450
-
fallthrough; /* to PTP v1, UDP, any kind of event packet */
1451
-
case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1452
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1453
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1454
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1455
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1456
-
break;
1457
-
1458
-
/* PTP v2, UDP, Sync packet */
1459
-
case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1460
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1461
-
fallthrough; /* to PTP v1, UDP, Sync packet */
1462
-
case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1463
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1464
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1465
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1466
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1467
-
break;
1468
-
1469
-
/* PTP v2, UDP, Delay_req packet */
1470
-
case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1471
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1472
-
fallthrough; /* to PTP v1, UDP, Delay_req packet */
1473
-
case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1474
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1475
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1476
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1477
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1478
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1479
-
break;
1480
-
1481
-
/* 802.AS1, Ethernet, any kind of event packet */
1482
-
case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1483
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1484
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1485
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1486
-
break;
1487
-
1488
-
/* 802.AS1, Ethernet, Sync packet */
1489
-
case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1490
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1491
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1492
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1493
-
break;
1494
-
1495
-
/* 802.AS1, Ethernet, Delay_req packet */
1496
-
case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1497
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
1498
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1499
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1500
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1501
-
break;
1502
-
1503
-
/* PTP v2/802.AS1, any layer, any kind of event packet */
1504
-
case HWTSTAMP_FILTER_PTP_V2_EVENT:
1505
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1506
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1507
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1508
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1509
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
1510
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1511
-
break;
1512
-
1513
-
/* PTP v2/802.AS1, any layer, Sync packet */
1514
-
case HWTSTAMP_FILTER_PTP_V2_SYNC:
1515
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1516
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1517
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1518
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1519
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1520
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1521
-
break;
1522
-
1523
-
/* PTP v2/802.AS1, any layer, Delay_req packet */
1524
-
case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1525
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
1526
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
1527
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
1528
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
1529
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
1530
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
1531
-
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
1532
-
break;
1533
-
1534
-
default:
1535
-
return -ERANGE;
1536
-
}
1537
-
1538
-
pdata->hw_if.config_tstamp(pdata, mac_tscr);
1539
-
1540
-
memcpy(&pdata->tstamp_config, &config, sizeof(config));
1541
-
1542
-
return 0;
1543
-
}
1544
-
1545
-
static void xgbe_prep_tx_tstamp(struct xgbe_prv_data *pdata,
1546
-
struct sk_buff *skb,
1547
-
struct xgbe_packet_data *packet)
1548
-
{
1549
-
unsigned long flags;
1550
-
1551
-
if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) {
1552
-
spin_lock_irqsave(&pdata->tstamp_lock, flags);
1553
-
if (pdata->tx_tstamp_skb) {
1554
-
/* Another timestamp in progress, ignore this one */
1555
-
XGMAC_SET_BITS(packet->attributes,
1556
-
TX_PACKET_ATTRIBUTES, PTP, 0);
1557
-
} else {
1558
-
pdata->tx_tstamp_skb = skb_get(skb);
1559
-
skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1560
-
}
1561
-
spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
1562
-
}
1563
-
1564
-
skb_tx_timestamp(skb);
1565
-
}
1566
-
1567
1374
static void xgbe_prep_vlan(struct sk_buff *skb, struct xgbe_packet_data *packet)
1568
1375
{
1569
1376
if (skb_vlan_tag_present(skb))
···
1582
1775
INIT_WORK(&pdata->restart_work, xgbe_restart);
1583
1776
INIT_WORK(&pdata->stopdev_work, xgbe_stopdev);
1584
1777
INIT_WORK(&pdata->tx_tstamp_work, xgbe_tx_tstamp);
1778
+
1779
+
/* Initialize PTP timestamping and clock. */
1780
+
xgbe_init_ptp(pdata);
1585
1781
1586
1782
ret = xgbe_alloc_memory(pdata);
1587
1783
if (ret)
···
2356
2546
2357
2547
if (XGMAC_GET_BITS(packet->attributes,
2358
2548
RX_PACKET_ATTRIBUTES, RX_TSTAMP)) {
2359
-
u64 nsec;
2360
-
2361
-
nsec = timecounter_cyc2time(&pdata->tstamp_tc,
2362
-
packet->rx_tstamp);
2363
2549
hwtstamps = skb_hwtstamps(skb);
2364
-
hwtstamps->hwtstamp = ns_to_ktime(nsec);
2550
+
hwtstamps->hwtstamp = ns_to_ktime(packet->rx_tstamp);
2365
2551
}
2366
2552
2367
2553
if (XGMAC_GET_BITS(packet->attributes,
+401
drivers/net/ethernet/amd/xgbe/xgbe-hwtstamp.c
+401
drivers/net/ethernet/amd/xgbe/xgbe-hwtstamp.c
···
1
+
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
2
+
/*
3
+
* Copyright (c) 2014-2025, Advanced Micro Devices, Inc.
4
+
* Copyright (c) 2014, Synopsys, Inc.
5
+
* All rights reserved
6
+
*
7
+
* Author: Raju Rangoju <Raju.Rangoju@amd.com>
8
+
*/
9
+
10
+
#include "xgbe.h"
11
+
#include "xgbe-common.h"
12
+
13
+
void xgbe_update_tstamp_time(struct xgbe_prv_data *pdata,
14
+
unsigned int sec, unsigned int nsec)
15
+
{
16
+
int count;
17
+
18
+
/* Set the time values and tell the device */
19
+
XGMAC_IOWRITE(pdata, MAC_STSUR, sec);
20
+
XGMAC_IOWRITE(pdata, MAC_STNUR, nsec);
21
+
22
+
/* issue command to update the system time value */
23
+
XGMAC_IOWRITE(pdata, MAC_TSCR,
24
+
XGMAC_IOREAD(pdata, MAC_TSCR) |
25
+
(1 << MAC_TSCR_TSUPDT_INDEX));
26
+
27
+
/* Wait for the time adjust/update to complete */
28
+
count = 10000;
29
+
while (--count && XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSUPDT))
30
+
udelay(5);
31
+
32
+
if (count < 0)
33
+
netdev_err(pdata->netdev,
34
+
"timed out updating system timestamp\n");
35
+
}
36
+
37
+
void xgbe_update_tstamp_addend(struct xgbe_prv_data *pdata,
38
+
unsigned int addend)
39
+
{
40
+
unsigned int count = 10000;
41
+
42
+
/* Set the addend register value and tell the device */
43
+
XGMAC_IOWRITE(pdata, MAC_TSAR, addend);
44
+
XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 1);
45
+
46
+
/* Wait for addend update to complete */
47
+
while (--count && XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG))
48
+
udelay(5);
49
+
50
+
if (!count)
51
+
netdev_err(pdata->netdev,
52
+
"timed out updating timestamp addend register\n");
53
+
}
54
+
55
+
void xgbe_set_tstamp_time(struct xgbe_prv_data *pdata, unsigned int sec,
56
+
unsigned int nsec)
57
+
{
58
+
unsigned int count = 10000;
59
+
60
+
/* Set the time values and tell the device */
61
+
XGMAC_IOWRITE(pdata, MAC_STSUR, sec);
62
+
XGMAC_IOWRITE(pdata, MAC_STNUR, nsec);
63
+
XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSINIT, 1);
64
+
65
+
/* Wait for time update to complete */
66
+
while (--count && XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT))
67
+
udelay(5);
68
+
69
+
if (!count)
70
+
netdev_err(pdata->netdev, "timed out initializing timestamp\n");
71
+
}
72
+
73
+
u64 xgbe_get_tstamp_time(struct xgbe_prv_data *pdata)
74
+
{
75
+
u64 nsec;
76
+
77
+
nsec = XGMAC_IOREAD(pdata, MAC_STSR);
78
+
nsec *= NSEC_PER_SEC;
79
+
nsec += XGMAC_IOREAD(pdata, MAC_STNR);
80
+
81
+
return nsec;
82
+
}
83
+
84
+
u64 xgbe_get_tx_tstamp(struct xgbe_prv_data *pdata)
85
+
{
86
+
unsigned int tx_snr, tx_ssr;
87
+
u64 nsec;
88
+
89
+
if (pdata->vdata->tx_tstamp_workaround) {
90
+
tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR);
91
+
tx_ssr = XGMAC_IOREAD(pdata, MAC_TXSSR);
92
+
} else {
93
+
tx_ssr = XGMAC_IOREAD(pdata, MAC_TXSSR);
94
+
tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR);
95
+
}
96
+
97
+
if (XGMAC_GET_BITS(tx_snr, MAC_TXSNR, TXTSSTSMIS))
98
+
return 0;
99
+
100
+
nsec = tx_ssr;
101
+
nsec *= NSEC_PER_SEC;
102
+
nsec += tx_snr;
103
+
104
+
return nsec;
105
+
}
106
+
107
+
void xgbe_get_rx_tstamp(struct xgbe_packet_data *packet,
108
+
struct xgbe_ring_desc *rdesc)
109
+
{
110
+
u64 nsec;
111
+
112
+
if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSA) &&
113
+
!XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSD)) {
114
+
nsec = le32_to_cpu(rdesc->desc1);
115
+
nsec *= NSEC_PER_SEC;
116
+
nsec += le32_to_cpu(rdesc->desc0);
117
+
if (nsec != 0xffffffffffffffffULL) {
118
+
packet->rx_tstamp = nsec;
119
+
XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
120
+
RX_TSTAMP, 1);
121
+
}
122
+
}
123
+
}
124
+
125
+
void xgbe_config_tstamp(struct xgbe_prv_data *pdata, unsigned int mac_tscr)
126
+
{
127
+
unsigned int value = 0;
128
+
129
+
value = XGMAC_IOREAD(pdata, MAC_TSCR);
130
+
value |= mac_tscr;
131
+
XGMAC_IOWRITE(pdata, MAC_TSCR, value);
132
+
}
133
+
134
+
void xgbe_tx_tstamp(struct work_struct *work)
135
+
{
136
+
struct xgbe_prv_data *pdata = container_of(work,
137
+
struct xgbe_prv_data,
138
+
tx_tstamp_work);
139
+
struct skb_shared_hwtstamps hwtstamps;
140
+
unsigned long flags;
141
+
142
+
spin_lock_irqsave(&pdata->tstamp_lock, flags);
143
+
if (!pdata->tx_tstamp_skb)
144
+
goto unlock;
145
+
146
+
if (pdata->tx_tstamp) {
147
+
memset(&hwtstamps, 0, sizeof(hwtstamps));
148
+
hwtstamps.hwtstamp = ns_to_ktime(pdata->tx_tstamp);
149
+
skb_tstamp_tx(pdata->tx_tstamp_skb, &hwtstamps);
150
+
}
151
+
152
+
dev_kfree_skb_any(pdata->tx_tstamp_skb);
153
+
154
+
pdata->tx_tstamp_skb = NULL;
155
+
156
+
unlock:
157
+
spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
158
+
}
159
+
160
+
int xgbe_get_hwtstamp_settings(struct xgbe_prv_data *pdata, struct ifreq *ifreq)
161
+
{
162
+
if (copy_to_user(ifreq->ifr_data, &pdata->tstamp_config,
163
+
sizeof(pdata->tstamp_config)))
164
+
return -EFAULT;
165
+
166
+
return 0;
167
+
}
168
+
169
+
int xgbe_set_hwtstamp_settings(struct xgbe_prv_data *pdata, struct ifreq *ifreq)
170
+
{
171
+
struct hwtstamp_config config;
172
+
unsigned int mac_tscr;
173
+
174
+
if (copy_from_user(&config, ifreq->ifr_data, sizeof(config)))
175
+
return -EFAULT;
176
+
177
+
mac_tscr = 0;
178
+
179
+
switch (config.tx_type) {
180
+
case HWTSTAMP_TX_OFF:
181
+
break;
182
+
183
+
case HWTSTAMP_TX_ON:
184
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
185
+
break;
186
+
187
+
default:
188
+
return -ERANGE;
189
+
}
190
+
191
+
switch (config.rx_filter) {
192
+
case HWTSTAMP_FILTER_NONE:
193
+
break;
194
+
195
+
case HWTSTAMP_FILTER_NTP_ALL:
196
+
case HWTSTAMP_FILTER_ALL:
197
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1);
198
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
199
+
break;
200
+
201
+
/* PTP v2, UDP, any kind of event packet */
202
+
case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
203
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
204
+
fallthrough; /* to PTP v1, UDP, any kind of event packet */
205
+
case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
206
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
207
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
208
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
209
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
210
+
break;
211
+
/* PTP v2, UDP, Sync packet */
212
+
case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
213
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
214
+
fallthrough; /* to PTP v1, UDP, Sync packet */
215
+
case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
216
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
217
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
218
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
219
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
220
+
break;
221
+
222
+
/* PTP v2, UDP, Delay_req packet */
223
+
case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
224
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
225
+
fallthrough; /* to PTP v1, UDP, Delay_req packet */
226
+
case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
227
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
228
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
229
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
230
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
231
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
232
+
break;
233
+
234
+
/* 802.AS1, Ethernet, any kind of event packet */
235
+
case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
236
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
237
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
238
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
239
+
break;
240
+
241
+
/* 802.AS1, Ethernet, Sync packet */
242
+
case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
243
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
244
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
245
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
246
+
break;
247
+
248
+
/* 802.AS1, Ethernet, Delay_req packet */
249
+
case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
250
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
251
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
252
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
253
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
254
+
break;
255
+
256
+
/* PTP v2/802.AS1, any layer, any kind of event packet */
257
+
case HWTSTAMP_FILTER_PTP_V2_EVENT:
258
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
259
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
260
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
261
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
262
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
263
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
264
+
break;
265
+
266
+
/* PTP v2/802.AS1, any layer, Sync packet */
267
+
case HWTSTAMP_FILTER_PTP_V2_SYNC:
268
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
269
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
270
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
271
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
272
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
273
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
274
+
break;
275
+
276
+
/* PTP v2/802.AS1, any layer, Delay_req packet */
277
+
case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
278
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
279
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
280
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
281
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
282
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
283
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
284
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
285
+
break;
286
+
287
+
default:
288
+
return -ERANGE;
289
+
}
290
+
291
+
xgbe_config_tstamp(pdata, mac_tscr);
292
+
293
+
memcpy(&pdata->tstamp_config, &config, sizeof(config));
294
+
295
+
return 0;
296
+
}
297
+
298
+
void xgbe_prep_tx_tstamp(struct xgbe_prv_data *pdata,
299
+
struct sk_buff *skb,
300
+
struct xgbe_packet_data *packet)
301
+
{
302
+
unsigned long flags;
303
+
304
+
if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) {
305
+
spin_lock_irqsave(&pdata->tstamp_lock, flags);
306
+
if (pdata->tx_tstamp_skb) {
307
+
/* Another timestamp in progress, ignore this one */
308
+
XGMAC_SET_BITS(packet->attributes,
309
+
TX_PACKET_ATTRIBUTES, PTP, 0);
310
+
} else {
311
+
pdata->tx_tstamp_skb = skb_get(skb);
312
+
skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
313
+
}
314
+
spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
315
+
}
316
+
317
+
skb_tx_timestamp(skb);
318
+
}
319
+
320
+
int xgbe_init_ptp(struct xgbe_prv_data *pdata)
321
+
{
322
+
unsigned int mac_tscr = 0;
323
+
struct timespec64 now;
324
+
u64 dividend;
325
+
326
+
/* Register Settings to be done based on the link speed. */
327
+
switch (pdata->phy.speed) {
328
+
case SPEED_1000:
329
+
XGMAC_IOWRITE(pdata, MAC_TICNR, MAC_TICNR_1G_INITVAL);
330
+
XGMAC_IOWRITE(pdata, MAC_TECNR, MAC_TECNR_1G_INITVAL);
331
+
break;
332
+
case SPEED_2500:
333
+
case SPEED_10000:
334
+
XGMAC_IOWRITE_BITS(pdata, MAC_TICSNR, TSICSNS,
335
+
MAC_TICSNR_10G_INITVAL);
336
+
XGMAC_IOWRITE(pdata, MAC_TECNR, MAC_TECNR_10G_INITVAL);
337
+
XGMAC_IOWRITE_BITS(pdata, MAC_TECSNR, TSECSNS,
338
+
MAC_TECSNR_10G_INITVAL);
339
+
break;
340
+
case SPEED_UNKNOWN:
341
+
default:
342
+
break;
343
+
}
344
+
345
+
/* Enable IEEE1588 PTP clock. */
346
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
347
+
348
+
/* Overwrite earlier timestamps */
349
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TXTSSTSM, 1);
350
+
351
+
/* Set one nano-second accuracy */
352
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCTRLSSR, 1);
353
+
354
+
/* Set fine timestamp update */
355
+
XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 1);
356
+
357
+
xgbe_config_tstamp(pdata, mac_tscr);
358
+
359
+
/* Exit if timestamping is not enabled */
360
+
if (!XGMAC_GET_BITS(mac_tscr, MAC_TSCR, TSENA))
361
+
return -EOPNOTSUPP;
362
+
363
+
if (pdata->vdata->tstamp_ptp_clock_freq) {
364
+
/* Initialize time registers based on
365
+
* 125MHz PTP Clock Frequency
366
+
*/
367
+
XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC,
368
+
XGBE_V2_TSTAMP_SSINC);
369
+
XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC,
370
+
XGBE_V2_TSTAMP_SNSINC);
371
+
} else {
372
+
/* Initialize time registers based on
373
+
* 50MHz PTP Clock Frequency
374
+
*/
375
+
XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC, XGBE_TSTAMP_SSINC);
376
+
XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC, XGBE_TSTAMP_SNSINC);
377
+
}
378
+
379
+
/* Calculate the addend:
380
+
* addend = 2^32 / (PTP ref clock / (PTP clock based on SSINC))
381
+
* = (2^32 * (PTP clock based on SSINC)) / PTP ref clock
382
+
*/
383
+
if (pdata->vdata->tstamp_ptp_clock_freq)
384
+
dividend = XGBE_V2_PTP_ACT_CLK_FREQ;
385
+
else
386
+
dividend = XGBE_PTP_ACT_CLK_FREQ;
387
+
388
+
dividend = (u64)(dividend << 32);
389
+
pdata->tstamp_addend = div_u64(dividend, pdata->ptpclk_rate);
390
+
391
+
xgbe_update_tstamp_addend(pdata, pdata->tstamp_addend);
392
+
393
+
dma_wmb();
394
+
/* initialize system time */
395
+
ktime_get_real_ts64(&now);
396
+
397
+
/* lower 32 bits of tv_sec are safe until y2106 */
398
+
xgbe_set_tstamp_time(pdata, (u32)now.tv_sec, now.tv_nsec);
399
+
400
+
return 0;
401
+
}
+2
drivers/net/ethernet/amd/xgbe/xgbe-pci.c
+2
drivers/net/ethernet/amd/xgbe/xgbe-pci.c
···
414
414
.tx_max_fifo_size = 229376,
415
415
.rx_max_fifo_size = 229376,
416
416
.tx_tstamp_workaround = 1,
417
+
.tstamp_ptp_clock_freq = 1,
417
418
.ecc_support = 1,
418
419
.i2c_support = 1,
419
420
.irq_reissue_support = 1,
···
431
430
.tx_max_fifo_size = 65536,
432
431
.rx_max_fifo_size = 65536,
433
432
.tx_tstamp_workaround = 1,
433
+
.tstamp_ptp_clock_freq = 1,
434
434
.ecc_support = 1,
435
435
.i2c_support = 1,
436
436
.irq_reissue_support = 1,
+31
-44
drivers/net/ethernet/amd/xgbe/xgbe-ptp.c
+31
-44
drivers/net/ethernet/amd/xgbe/xgbe-ptp.c
···
13
13
#include "xgbe.h"
14
14
#include "xgbe-common.h"
15
15
16
-
static u64 xgbe_cc_read(const struct cyclecounter *cc)
17
-
{
18
-
struct xgbe_prv_data *pdata = container_of(cc,
19
-
struct xgbe_prv_data,
20
-
tstamp_cc);
21
-
u64 nsec;
22
-
23
-
nsec = pdata->hw_if.get_tstamp_time(pdata);
24
-
25
-
return nsec;
26
-
}
27
-
28
16
static int xgbe_adjfine(struct ptp_clock_info *info, long scaled_ppm)
29
17
{
30
18
struct xgbe_prv_data *pdata = container_of(info,
···
25
37
26
38
spin_lock_irqsave(&pdata->tstamp_lock, flags);
27
39
28
-
pdata->hw_if.update_tstamp_addend(pdata, addend);
40
+
xgbe_update_tstamp_addend(pdata, addend);
29
41
30
42
spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
31
43
···
37
49
struct xgbe_prv_data *pdata = container_of(info,
38
50
struct xgbe_prv_data,
39
51
ptp_clock_info);
52
+
unsigned int neg_adjust = 0;
53
+
unsigned int sec, nsec;
54
+
u32 quotient, reminder;
40
55
unsigned long flags;
41
56
57
+
if (delta < 0) {
58
+
neg_adjust = 1;
59
+
delta = -delta;
60
+
}
61
+
62
+
quotient = div_u64_rem(delta, 1000000000ULL, &reminder);
63
+
sec = quotient;
64
+
nsec = reminder;
65
+
66
+
/* Negative adjustment for Hw timer register. */
67
+
if (neg_adjust) {
68
+
sec = -sec;
69
+
if (XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSCTRLSSR))
70
+
nsec = (1000000000UL - nsec);
71
+
else
72
+
nsec = (0x80000000UL - nsec);
73
+
}
74
+
nsec = (neg_adjust << 31) | nsec;
75
+
42
76
spin_lock_irqsave(&pdata->tstamp_lock, flags);
43
-
timecounter_adjtime(&pdata->tstamp_tc, delta);
77
+
xgbe_update_tstamp_time(pdata, sec, nsec);
44
78
spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
45
79
46
80
return 0;
47
81
}
48
82
49
-
static int xgbe_gettime(struct ptp_clock_info *info, struct timespec64 *ts)
83
+
static int xgbe_gettimex(struct ptp_clock_info *info, struct timespec64 *ts,
84
+
struct ptp_system_timestamp *sts)
50
85
{
51
86
struct xgbe_prv_data *pdata = container_of(info,
52
87
struct xgbe_prv_data,
···
78
67
u64 nsec;
79
68
80
69
spin_lock_irqsave(&pdata->tstamp_lock, flags);
81
-
82
-
nsec = timecounter_read(&pdata->tstamp_tc);
83
-
70
+
ptp_read_system_prets(sts);
71
+
nsec = xgbe_get_tstamp_time(pdata);
72
+
ptp_read_system_postts(sts);
84
73
spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
85
74
86
75
*ts = ns_to_timespec64(nsec);
···
95
84
struct xgbe_prv_data,
96
85
ptp_clock_info);
97
86
unsigned long flags;
98
-
u64 nsec;
99
-
100
-
nsec = timespec64_to_ns(ts);
101
87
102
88
spin_lock_irqsave(&pdata->tstamp_lock, flags);
103
-
104
-
timecounter_init(&pdata->tstamp_tc, &pdata->tstamp_cc, nsec);
105
-
89
+
xgbe_set_tstamp_time(pdata, ts->tv_sec, ts->tv_nsec);
106
90
spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
107
91
108
92
return 0;
···
113
107
{
114
108
struct ptp_clock_info *info = &pdata->ptp_clock_info;
115
109
struct ptp_clock *clock;
116
-
struct cyclecounter *cc = &pdata->tstamp_cc;
117
-
u64 dividend;
118
110
119
111
snprintf(info->name, sizeof(info->name), "%s",
120
112
netdev_name(pdata->netdev));
···
120
116
info->max_adj = pdata->ptpclk_rate;
121
117
info->adjfine = xgbe_adjfine;
122
118
info->adjtime = xgbe_adjtime;
123
-
info->gettime64 = xgbe_gettime;
119
+
info->gettimex64 = xgbe_gettimex;
124
120
info->settime64 = xgbe_settime;
125
121
info->enable = xgbe_enable;
126
122
···
131
127
}
132
128
133
129
pdata->ptp_clock = clock;
134
-
135
-
/* Calculate the addend:
136
-
* addend = 2^32 / (PTP ref clock / 50Mhz)
137
-
* = (2^32 * 50Mhz) / PTP ref clock
138
-
*/
139
-
dividend = 50000000;
140
-
dividend <<= 32;
141
-
pdata->tstamp_addend = div_u64(dividend, pdata->ptpclk_rate);
142
-
143
-
/* Setup the timecounter */
144
-
cc->read = xgbe_cc_read;
145
-
cc->mask = CLOCKSOURCE_MASK(64);
146
-
cc->mult = 1;
147
-
cc->shift = 0;
148
-
149
-
timecounter_init(&pdata->tstamp_tc, &pdata->tstamp_cc,
150
-
ktime_to_ns(ktime_get_real()));
151
130
152
131
/* Disable all timestamping to start */
153
132
XGMAC_IOWRITE(pdata, MAC_TSCR, 0);
+37
-10
drivers/net/ethernet/amd/xgbe/xgbe.h
+37
-10
drivers/net/ethernet/amd/xgbe/xgbe.h
···
119
119
#define XGBE_MSI_BASE_COUNT 4
120
120
#define XGBE_MSI_MIN_COUNT (XGBE_MSI_BASE_COUNT + 1)
121
121
122
+
/* Initial PTP register values based on Link Speed. */
123
+
#define MAC_TICNR_1G_INITVAL 0x10
124
+
#define MAC_TECNR_1G_INITVAL 0x28
125
+
126
+
#define MAC_TICSNR_10G_INITVAL 0x33
127
+
#define MAC_TECNR_10G_INITVAL 0x14
128
+
#define MAC_TECSNR_10G_INITVAL 0xCC
129
+
122
130
/* PCI clock frequencies */
123
131
#define XGBE_V2_DMA_CLOCK_FREQ 500000000 /* 500 MHz */
124
132
#define XGBE_V2_PTP_CLOCK_FREQ 125000000 /* 125 MHz */
···
136
128
*/
137
129
#define XGBE_TSTAMP_SSINC 20
138
130
#define XGBE_TSTAMP_SNSINC 0
131
+
#define XGBE_PTP_ACT_CLK_FREQ 500000000
132
+
133
+
#define XGBE_V2_TSTAMP_SSINC 0xA
134
+
#define XGBE_V2_TSTAMP_SNSINC 0
135
+
#define XGBE_V2_PTP_ACT_CLK_FREQ 1000000000
139
136
140
137
/* Driver PMT macros */
141
138
#define XGMAC_DRIVER_CONTEXT 1
···
754
741
void (*tx_mmc_int)(struct xgbe_prv_data *);
755
742
void (*read_mmc_stats)(struct xgbe_prv_data *);
756
743
757
-
/* For Timestamp config */
758
-
int (*config_tstamp)(struct xgbe_prv_data *, unsigned int);
759
-
void (*update_tstamp_addend)(struct xgbe_prv_data *, unsigned int);
760
-
void (*set_tstamp_time)(struct xgbe_prv_data *, unsigned int sec,
761
-
unsigned int nsec);
762
-
u64 (*get_tstamp_time)(struct xgbe_prv_data *);
763
-
u64 (*get_tx_tstamp)(struct xgbe_prv_data *);
764
-
765
744
/* For Data Center Bridging config */
766
745
void (*config_tc)(struct xgbe_prv_data *);
767
746
void (*config_dcb_tc)(struct xgbe_prv_data *);
···
951
946
unsigned int tx_max_fifo_size;
952
947
unsigned int rx_max_fifo_size;
953
948
unsigned int tx_tstamp_workaround;
949
+
unsigned int tstamp_ptp_clock_freq;
954
950
unsigned int ecc_support;
955
951
unsigned int i2c_support;
956
952
unsigned int irq_reissue_support;
···
1137
1131
struct ptp_clock_info ptp_clock_info;
1138
1132
struct ptp_clock *ptp_clock;
1139
1133
struct hwtstamp_config tstamp_config;
1140
-
struct cyclecounter tstamp_cc;
1141
-
struct timecounter tstamp_tc;
1142
1134
unsigned int tstamp_addend;
1143
1135
struct work_struct tx_tstamp_work;
1144
1136
struct sk_buff *tx_tstamp_skb;
···
1281
1277
void xgbe_restart_dev(struct xgbe_prv_data *pdata);
1282
1278
void xgbe_full_restart_dev(struct xgbe_prv_data *pdata);
1283
1279
1280
+
/* For Timestamp config */
1281
+
void xgbe_config_tstamp(struct xgbe_prv_data *pdata, unsigned int mac_tscr);
1282
+
u64 xgbe_get_tstamp_time(struct xgbe_prv_data *pdata);
1283
+
u64 xgbe_get_tx_tstamp(struct xgbe_prv_data *pdata);
1284
+
void xgbe_get_rx_tstamp(struct xgbe_packet_data *packet,
1285
+
struct xgbe_ring_desc *rdesc);
1286
+
void xgbe_get_rx_tstamp(struct xgbe_packet_data *packet,
1287
+
struct xgbe_ring_desc *rdesc);
1288
+
void xgbe_update_tstamp_addend(struct xgbe_prv_data *pdata,
1289
+
unsigned int addend);
1290
+
void xgbe_set_tstamp_time(struct xgbe_prv_data *pdata, unsigned int sec,
1291
+
unsigned int nsec);
1292
+
void xgbe_tx_tstamp(struct work_struct *work);
1293
+
int xgbe_get_hwtstamp_settings(struct xgbe_prv_data *pdata,
1294
+
struct ifreq *ifreq);
1295
+
int xgbe_set_hwtstamp_settings(struct xgbe_prv_data *pdata,
1296
+
struct ifreq *ifreq);
1297
+
void xgbe_prep_tx_tstamp(struct xgbe_prv_data *pdata,
1298
+
struct sk_buff *skb,
1299
+
struct xgbe_packet_data *packet);
1300
+
int xgbe_init_ptp(struct xgbe_prv_data *pdata);
1301
+
void xgbe_update_tstamp_time(struct xgbe_prv_data *pdata, unsigned int sec,
1302
+
unsigned int nsec);
1284
1303
#ifdef CONFIG_DEBUG_FS
1285
1304
void xgbe_debugfs_init(struct xgbe_prv_data *);
1286
1305
void xgbe_debugfs_exit(struct xgbe_prv_data *);