Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"The clk core gains a new set of APIs that allow drivers to both
acquire clks and prepare and enable them at the same time. This also
comes with devm support so that drivers can make a single call to get
and prepare and enable the clk and have that all undone when their
driver is removed.
Many folks have requested this feature over the years, but we've had
disagreements about how to implement it and if it was worthwhile to
encourage drivers to use such an API.
Now it's here, so let's see how it goes.
I hope that by introducing this API we can identify drivers that would
benefit from further consolidation of clk API usage, possibly by
moving such logic to the bus layer and out of drivers altogether.
Outside of that major API update, we have the usual collection of
driver updates. A few new SoCs are supported, mostly Qualcomm and
Renesas this time around. Then we have the long tail of non-critical
fixes and minor feature additions to various clk drivers.
And finally more clk provider migration to struct clk_parent_data,
reducing boot times in the process.
Summary:
Core:
- devm helpers for clk_get() + clk_prepare() and clk_enable()
New Drivers:
- Support for the camera clock controller in Qualcomm SM8450 and the
display and gpu clock controllers in Qualcomm SM8350
- Add support for the Renesas RZ/Five SoC
Updates:
- Various fixes, new clocks and USB GDSCs are introduced for Qualcomm
IPQ8074
- Fixes to Qualcomm MSM8939 for issues introduced by inheriting the
MSM8916 GCC driver
- Support for a new type of voteable GDSCs used by Qualcomm SC8280XP
PCIe GDSCs
- Qualcomm SC8280XP pipe clocks transitioned to the new phy-mux
implementation
- Qualcomm MSM8996 GCC, RPM clock driver and some clocks in MSM8994
GCC are migrated to use clk_parent_data
- Corrected the topology for Titan (camera) GDSCs on Qualcomm SDM845
and SM8250
- Qualcomm MSM8916 gains more possible frequencies for its GP clocks.
- The GCC and tsens handling on Qualcomm MSM8960 is reworked to mimic
the design in IPQ8074 to allow the GCC driver to probe earlier.
- The regulator based mmcx supply for Qualcomm dispcc and videocc is
dropped, as the only upstream target that adapted this interface
was transitioned several kernel versions ago
- Qualcomm GDSCs found to be enabled at boot will now reflect in the
enable count of the supply, as was done with the regulator supplies
previously
- Correct adc1, nic_media and edma1's parents for NXP i.MX93
- rdiv, mfd values, the return rate in recalc_rate and add more
frequencies in the table for fracn-gppll on i.MX
- Remove Allwinner workaround logic/compatible in fixed factor code
- MediaTek clk driver cleanups
- Add reset support to more MediaTek clk drivers
- deduplicate Allwinner ccu_clks arrays
- Allwinner H6 GPU DFS support
- Adjust Allwinner Kconfig to limit choice
- Fix initconst confusion on Renesas R-Car Gen4
- Add GPT/POEG (PWM) clocks and resets on Renesas RZ/G2L
- Add PFC and WDT clocks and resets on Renesas RZ/V2M
- Add thermal, SDHI, Z (CPU core), PCIe, and HSCIF (serial) clocks on
Renesas R-Car S4-8"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (124 commits)
clk: fixed-factor: Introduce *clk_hw_register_fixed_factor_parent_hw()
clk: mux: Introduce devm_clk_hw_register_mux_parent_hws()
clk: divider: Introduce devm_clk_hw_register_divider_parent_hw()
clk: qcom: gcc-msm8994: use parent_hws for gpll0/4
clk: qcom: clk-rpm: convert to parent_data API
dt-bindings: clock: fix wrong clock documentation for qcom,rpmcc
clk: qcom: gcc-msm8939: Add missing USB HS system clock frequencies
clk: qcom: gcc-msm8939: Add missing MDSS MDP clock frequencies
clk: qcom: gcc-msm8939: Add missing CAMSS CPP clock frequencies
clk: qcom: gcc-msm8939: Fix venus0_vcodec0_clk frequency definitions
clk: qcom: gcc-msm8939: Add missing CAMSS CCI bus clock
clk: qcom: gcc-msm8939: Fix weird field spacing in ftbl_gcc_camss_cci_clk
clk: qcom: gdsc: Bump parent usage count when GDSC is found enabled
clk: qcom: Drop mmcx gdsc supply for dispcc and videocc
clk: qcom: fix build error initializer element is not constant
clk: sprd: Add dt-bindings include file for UMS512
dt-bindings: clk: sprd: Add bindings for ums512 clock controller
clk: sunxi-ng: sun50i: h6: Modify GPU clock configuration to support DFS
dt-bindings: clock: qcom,gcc-msm8996: add more GCC clock sources
clk: qcom: add support for SM8350 DISPCC
...
+6705
-1499
+3
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml
+3
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml
-8
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml
-8
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-clock.yaml
···
24
24
- mediatek,mt8192-imp_iic_wrap_w
25
25
- mediatek,mt8192-imp_iic_wrap_n
26
26
- mediatek,mt8192-msdc_top
27
-
- mediatek,mt8192-msdc
28
27
- mediatek,mt8192-mfgcfg
29
28
- mediatek,mt8192-imgsys
30
29
- mediatek,mt8192-imgsys2
···
103
104
msdc_top: clock-controller@11f10000 {
104
105
compatible = "mediatek,mt8192-msdc_top";
105
106
reg = <0x11f10000 0x1000>;
106
-
#clock-cells = <1>;
107
-
};
108
-
109
-
- |
110
-
msdc: clock-controller@11f60000 {
111
-
compatible = "mediatek,mt8192-msdc";
112
-
reg = <0x11f60000 0x1000>;
113
107
#clock-cells = <1>;
114
108
};
115
109
+3
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml
+3
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml
+3
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml
+3
Documentation/devicetree/bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml
-1
Documentation/devicetree/bindings/clock/fixed-factor-clock.yaml
-1
Documentation/devicetree/bindings/clock/fixed-factor-clock.yaml
+31
-9
Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml
+31
-9
Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml
···
4
4
$id: http://devicetree.org/schemas/clock/qcom,gcc-apq8064.yaml#
5
5
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
-
title: Qualcomm Global Clock & Reset Controller Binding for APQ8064
7
+
title: Qualcomm Global Clock & Reset Controller Binding for APQ8064/MSM8960
8
8
9
9
allOf:
10
10
- $ref: qcom,gcc.yaml#
···
23
23
24
24
properties:
25
25
compatible:
26
-
const: qcom,gcc-apq8064
26
+
oneOf:
27
+
- items:
28
+
- enum:
29
+
- qcom,gcc-apq8064
30
+
- qcom,gcc-msm8960
31
+
- const: syscon
32
+
- enum:
33
+
- qcom,gcc-apq8064
34
+
- qcom,gcc-msm8960
35
+
deprecated: true
36
+
37
+
thermal-sensor:
38
+
description: child tsens device
39
+
$ref: /schemas/thermal/qcom-tsens.yaml#
27
40
28
41
nvmem-cells:
29
42
minItems: 1
30
43
maxItems: 2
44
+
deprecated: true
31
45
description:
32
46
Qualcomm TSENS (thermal sensor device) on some devices can
33
47
be part of GCC and hence the TSENS properties can also be part
···
51
37
52
38
nvmem-cell-names:
53
39
minItems: 1
40
+
deprecated: true
54
41
items:
55
42
- const: calib
56
43
- const: calib_backup
57
44
58
45
'#thermal-sensor-cells':
59
46
const: 1
47
+
deprecated: true
60
48
61
49
required:
62
50
- compatible
63
-
- nvmem-cells
64
-
- nvmem-cell-names
65
-
- '#thermal-sensor-cells'
66
51
67
52
unevaluatedProperties: false
68
53
69
54
examples:
70
55
- |
71
56
clock-controller@900000 {
72
-
compatible = "qcom,gcc-apq8064";
57
+
compatible = "qcom,gcc-apq8064", "syscon";
73
58
reg = <0x00900000 0x4000>;
74
-
nvmem-cells = <&tsens_calib>, <&tsens_backup>;
75
-
nvmem-cell-names = "calib", "calib_backup";
76
59
#clock-cells = <1>;
77
60
#reset-cells = <1>;
78
61
#power-domain-cells = <1>;
79
-
#thermal-sensor-cells = <1>;
62
+
63
+
thermal-sensor {
64
+
compatible = "qcom,msm8960-tsens";
65
+
66
+
nvmem-cells = <&tsens_calib>, <&tsens_backup>;
67
+
nvmem-cell-names = "calib", "calib_backup";
68
+
interrupts = <0 178 4>;
69
+
interrupt-names = "uplow";
70
+
71
+
#qcom,sensors = <11>;
72
+
#thermal-sensor-cells = <1>;
73
+
};
80
74
};
81
75
...
+5
Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml
+5
Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml
···
24
24
'#clock-cells':
25
25
const: 1
26
26
27
+
'#power-domain-cells':
28
+
const: 1
29
+
27
30
'#reset-cells':
28
31
const: 1
29
32
···
41
38
- compatible
42
39
- reg
43
40
- '#clock-cells'
41
+
- '#power-domain-cells'
44
42
- '#reset-cells'
45
43
46
44
additionalProperties: false
···
52
48
compatible = "qcom,gcc-ipq8074";
53
49
reg = <0x01800000 0x80000>;
54
50
#clock-cells = <1>;
51
+
#power-domain-cells = <1>;
55
52
#reset-cells = <1>;
56
53
};
57
54
...
+16
Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml
+16
Documentation/devicetree/bindings/clock/qcom,gcc-msm8996.yaml
···
22
22
const: qcom,gcc-msm8996
23
23
24
24
clocks:
25
+
minItems: 3
25
26
items:
26
27
- description: XO source
27
28
- description: Second XO source
28
29
- description: Sleep clock source
30
+
- description: PCIe 0 PIPE clock (optional)
31
+
- description: PCIe 1 PIPE clock (optional)
32
+
- description: PCIe 2 PIPE clock (optional)
33
+
- description: USB3 PIPE clock (optional)
34
+
- description: UFS RX symbol 0 clock (optional)
35
+
- description: UFS RX symbol 1 clock (optional)
36
+
- description: UFS TX symbol 0 clock (optional)
29
37
30
38
clock-names:
39
+
minItems: 3
31
40
items:
32
41
- const: cxo
33
42
- const: cxo2
34
43
- const: sleep_clk
44
+
- const: pcie_0_pipe_clk_src
45
+
- const: pcie_1_pipe_clk_src
46
+
- const: pcie_2_pipe_clk_src
47
+
- const: usb3_phy_pipe_clk_src
48
+
- const: ufs_rx_symbol_0_clk_src
49
+
- const: ufs_rx_symbol_1_clk_src
50
+
- const: ufs_tx_symbol_0_clk_src
35
51
36
52
'#clock-cells':
37
53
const: 1
+2
-3
Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
+2
-3
Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
···
44
44
- qcom,gcc-msm8916
45
45
- qcom,gcc-msm8939
46
46
- qcom,gcc-msm8953
47
-
- qcom,gcc-msm8960
48
47
- qcom,gcc-msm8974
49
48
- qcom,gcc-msm8974pro
50
49
- qcom,gcc-msm8974pro-ac
···
57
58
unevaluatedProperties: false
58
59
59
60
examples:
60
-
# Example for GCC for MSM8960:
61
+
# Example for GCC for MSM8974:
61
62
- |
62
63
clock-controller@900000 {
63
-
compatible = "qcom,gcc-msm8960";
64
+
compatible = "qcom,gcc-msm8974";
64
65
reg = <0x900000 0x4000>;
65
66
#clock-cells = <1>;
66
67
#reset-cells = <1>;
+3
Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml
+3
Documentation/devicetree/bindings/clock/qcom,gcc-sdm845.yaml
+83
-2
Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml
+83
-2
Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml
···
49
49
const: 1
50
50
51
51
clocks:
52
-
maxItems: 1
52
+
minItems: 1
53
+
maxItems: 2
53
54
54
55
clock-names:
55
-
const: xo
56
+
minItems: 1
57
+
maxItems: 2
56
58
57
59
required:
58
60
- compatible
59
61
- '#clock-cells'
62
+
63
+
allOf:
64
+
- if:
65
+
properties:
66
+
compatible:
67
+
contains:
68
+
enum:
69
+
- qcom,rpmcc-apq8060
70
+
- qcom,rpmcc-ipq806x
71
+
- qcom,rpmcc-msm8660
72
+
73
+
then:
74
+
properties:
75
+
clocks:
76
+
items:
77
+
- description: pxo clock
78
+
79
+
clock-names:
80
+
items:
81
+
- const: pxo
82
+
83
+
- if:
84
+
properties:
85
+
compatible:
86
+
contains:
87
+
const: qcom,rpmcc-apq8064
88
+
then:
89
+
properties:
90
+
clocks:
91
+
items:
92
+
- description: pxo clock
93
+
- description: cxo clock
94
+
95
+
clock-names:
96
+
items:
97
+
- const: pxo
98
+
- const: cxo
99
+
100
+
- if:
101
+
properties:
102
+
compatible:
103
+
contains:
104
+
enum:
105
+
- qcom,rpmcc-mdm9607
106
+
- qcom,rpmcc-msm8226
107
+
- qcom,rpmcc-msm8916
108
+
- qcom,rpmcc-msm8936
109
+
- qcom,rpmcc-msm8953
110
+
- qcom,rpmcc-msm8974
111
+
- qcom,rpmcc-msm8976
112
+
- qcom,rpmcc-msm8992
113
+
- qcom,rpmcc-msm8994
114
+
- qcom,rpmcc-msm8996
115
+
- qcom,rpmcc-msm8998
116
+
- qcom,rpmcc-qcm2290
117
+
- qcom,rpmcc-qcs404
118
+
- qcom,rpmcc-sdm660
119
+
- qcom,rpmcc-sm6115
120
+
- qcom,rpmcc-sm6125
121
+
122
+
then:
123
+
properties:
124
+
clocks:
125
+
items:
126
+
- description: xo clock
127
+
128
+
clock-names:
129
+
items:
130
+
- const: xo
60
131
61
132
additionalProperties: false
62
133
···
142
71
compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
143
72
#clock-cells = <1>;
144
73
};
74
+
};
75
+
};
76
+
77
+
- |
78
+
rpm {
79
+
clock-controller {
80
+
compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
81
+
#clock-cells = <1>;
82
+
clocks = <&pxo_board>;
83
+
clock-names = "pxo";
145
84
};
146
85
};
+3
-4
Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
+3
-4
Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml
···
45
45
description: |
46
46
- For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
47
47
and a core clock reference, as defined in
48
-
<dt-bindings/clock/r9a0*-cpg.h>
48
+
<dt-bindings/clock/r9a0*-cpg.h>,
49
49
- For module clocks, the two clock specifier cells must be "CPG_MOD" and
50
-
a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h> or
51
-
<dt-bindings/clock/r9a09g011-cpg.h>.
50
+
a module number, as defined in <dt-bindings/clock/r9a0*-cpg.h>.
52
51
const: 2
53
52
54
53
'#power-domain-cells':
···
61
62
'#reset-cells':
62
63
description:
63
64
The single reset specifier cell must be the module number, as defined in
64
-
the <dt-bindings/clock/r9a07g0*-cpg.h> or <dt-bindings/clock/r9a09g011-cpg.h>.
65
+
<dt-bindings/clock/r9a0*-cpg.h>.
65
66
const: 1
66
67
67
68
required:
+71
Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml
+71
Documentation/devicetree/bindings/clock/sprd,ums512-clk.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
# Copyright 2022 Unisoc Inc.
3
+
%YAML 1.2
4
+
---
5
+
$id: "http://devicetree.org/schemas/clock/sprd,ums512-clk.yaml#"
6
+
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
+
8
+
title: UMS512 Soc clock controller
9
+
10
+
maintainers:
11
+
- Orson Zhai <orsonzhai@gmail.com>
12
+
- Baolin Wang <baolin.wang7@gmail.com>
13
+
- Chunyan Zhang <zhang.lyra@gmail.com>
14
+
15
+
properties:
16
+
compatible:
17
+
enum:
18
+
- sprd,ums512-apahb-gate
19
+
- sprd,ums512-ap-clk
20
+
- sprd,ums512-aonapb-clk
21
+
- sprd,ums512-pmu-gate
22
+
- sprd,ums512-g0-pll
23
+
- sprd,ums512-g2-pll
24
+
- sprd,ums512-g3-pll
25
+
- sprd,ums512-gc-pll
26
+
- sprd,ums512-aon-gate
27
+
- sprd,ums512-audcpapb-gate
28
+
- sprd,ums512-audcpahb-gate
29
+
- sprd,ums512-gpu-clk
30
+
- sprd,ums512-mm-clk
31
+
- sprd,ums512-mm-gate-clk
32
+
- sprd,ums512-apapb-gate
33
+
34
+
"#clock-cells":
35
+
const: 1
36
+
37
+
clocks:
38
+
minItems: 1
39
+
maxItems: 4
40
+
description: |
41
+
The input parent clock(s) phandle for the clock, only list
42
+
fixed clocks which are declared in devicetree.
43
+
44
+
clock-names:
45
+
minItems: 1
46
+
items:
47
+
- const: ext-26m
48
+
- const: ext-32k
49
+
- const: ext-4m
50
+
- const: rco-100m
51
+
52
+
reg:
53
+
maxItems: 1
54
+
55
+
required:
56
+
- compatible
57
+
- '#clock-cells'
58
+
- reg
59
+
60
+
additionalProperties: false
61
+
62
+
examples:
63
+
- |
64
+
ap_clk: clock-controller@20200000 {
65
+
compatible = "sprd,ums512-ap-clk";
66
+
reg = <0x20200000 0x1000>;
67
+
clocks = <&ext_26m>;
68
+
clock-names = "ext-26m";
69
+
#clock-cells = <1>;
70
+
};
71
+
...
+81
-22
drivers/clk/clk-devres.c
+81
-22
drivers/clk/clk-devres.c
···
4
4
#include <linux/export.h>
5
5
#include <linux/gfp.h>
6
6
7
+
struct devm_clk_state {
8
+
struct clk *clk;
9
+
void (*exit)(struct clk *clk);
10
+
};
11
+
7
12
static void devm_clk_release(struct device *dev, void *res)
8
13
{
9
-
clk_put(*(struct clk **)res);
14
+
struct devm_clk_state *state = res;
15
+
16
+
if (state->exit)
17
+
state->exit(state->clk);
18
+
19
+
clk_put(state->clk);
20
+
}
21
+
22
+
static struct clk *__devm_clk_get(struct device *dev, const char *id,
23
+
struct clk *(*get)(struct device *dev, const char *id),
24
+
int (*init)(struct clk *clk),
25
+
void (*exit)(struct clk *clk))
26
+
{
27
+
struct devm_clk_state *state;
28
+
struct clk *clk;
29
+
int ret;
30
+
31
+
state = devres_alloc(devm_clk_release, sizeof(*state), GFP_KERNEL);
32
+
if (!state)
33
+
return ERR_PTR(-ENOMEM);
34
+
35
+
clk = get(dev, id);
36
+
if (IS_ERR(clk)) {
37
+
ret = PTR_ERR(clk);
38
+
goto err_clk_get;
39
+
}
40
+
41
+
if (init) {
42
+
ret = init(clk);
43
+
if (ret)
44
+
goto err_clk_init;
45
+
}
46
+
47
+
state->clk = clk;
48
+
state->exit = exit;
49
+
50
+
devres_add(dev, state);
51
+
52
+
return clk;
53
+
54
+
err_clk_init:
55
+
56
+
clk_put(clk);
57
+
err_clk_get:
58
+
59
+
devres_free(state);
60
+
return ERR_PTR(ret);
10
61
}
11
62
12
63
struct clk *devm_clk_get(struct device *dev, const char *id)
13
64
{
14
-
struct clk **ptr, *clk;
15
-
16
-
ptr = devres_alloc(devm_clk_release, sizeof(*ptr), GFP_KERNEL);
17
-
if (!ptr)
18
-
return ERR_PTR(-ENOMEM);
19
-
20
-
clk = clk_get(dev, id);
21
-
if (!IS_ERR(clk)) {
22
-
*ptr = clk;
23
-
devres_add(dev, ptr);
24
-
} else {
25
-
devres_free(ptr);
26
-
}
27
-
28
-
return clk;
65
+
return __devm_clk_get(dev, id, clk_get, NULL, NULL);
29
66
}
30
67
EXPORT_SYMBOL(devm_clk_get);
31
68
69
+
struct clk *devm_clk_get_prepared(struct device *dev, const char *id)
70
+
{
71
+
return __devm_clk_get(dev, id, clk_get, clk_prepare, clk_unprepare);
72
+
}
73
+
EXPORT_SYMBOL_GPL(devm_clk_get_prepared);
74
+
75
+
struct clk *devm_clk_get_enabled(struct device *dev, const char *id)
76
+
{
77
+
return __devm_clk_get(dev, id, clk_get,
78
+
clk_prepare_enable, clk_disable_unprepare);
79
+
}
80
+
EXPORT_SYMBOL_GPL(devm_clk_get_enabled);
81
+
32
82
struct clk *devm_clk_get_optional(struct device *dev, const char *id)
33
83
{
34
-
struct clk *clk = devm_clk_get(dev, id);
35
-
36
-
if (clk == ERR_PTR(-ENOENT))
37
-
return NULL;
38
-
39
-
return clk;
84
+
return __devm_clk_get(dev, id, clk_get_optional, NULL, NULL);
40
85
}
41
86
EXPORT_SYMBOL(devm_clk_get_optional);
87
+
88
+
struct clk *devm_clk_get_optional_prepared(struct device *dev, const char *id)
89
+
{
90
+
return __devm_clk_get(dev, id, clk_get_optional,
91
+
clk_prepare, clk_unprepare);
92
+
}
93
+
EXPORT_SYMBOL_GPL(devm_clk_get_optional_prepared);
94
+
95
+
struct clk *devm_clk_get_optional_enabled(struct device *dev, const char *id)
96
+
{
97
+
return __devm_clk_get(dev, id, clk_get_optional,
98
+
clk_prepare_enable, clk_disable_unprepare);
99
+
}
100
+
EXPORT_SYMBOL_GPL(devm_clk_get_optional_enabled);
42
101
43
102
struct clk_bulk_devres {
44
103
struct clk_bulk_data *clks;
+41
-15
drivers/clk/clk-fixed-factor.c
+41
-15
drivers/clk/clk-fixed-factor.c
···
78
78
79
79
static struct clk_hw *
80
80
__clk_hw_register_fixed_factor(struct device *dev, struct device_node *np,
81
-
const char *name, const char *parent_name, int index,
81
+
const char *name, const char *parent_name,
82
+
const struct clk_hw *parent_hw, int index,
82
83
unsigned long flags, unsigned int mult, unsigned int div,
83
84
bool devm)
84
85
{
···
111
110
init.flags = flags;
112
111
if (parent_name)
113
112
init.parent_names = &parent_name;
113
+
else if (parent_hw)
114
+
init.parent_hws = &parent_hw;
114
115
else
115
116
init.parent_data = &pdata;
116
117
init.num_parents = 1;
···
151
148
const char *name, unsigned int index, unsigned long flags,
152
149
unsigned int mult, unsigned int div)
153
150
{
154
-
return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, index,
151
+
return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, NULL, index,
155
152
flags, mult, div, true);
156
153
}
157
154
EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_index);
155
+
156
+
/**
157
+
* devm_clk_hw_register_fixed_factor_parent_hw - Register a fixed factor clock with
158
+
* pointer to parent clock
159
+
* @dev: device that is registering this clock
160
+
* @name: name of this clock
161
+
* @parent_hw: pointer to parent clk
162
+
* @flags: fixed factor flags
163
+
* @mult: multiplier
164
+
* @div: divider
165
+
*
166
+
* Return: Pointer to fixed factor clk_hw structure that was registered or
167
+
* an error pointer.
168
+
*/
169
+
struct clk_hw *devm_clk_hw_register_fixed_factor_parent_hw(struct device *dev,
170
+
const char *name, const struct clk_hw *parent_hw,
171
+
unsigned long flags, unsigned int mult, unsigned int div)
172
+
{
173
+
return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, parent_hw,
174
+
-1, flags, mult, div, true);
175
+
}
176
+
EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_parent_hw);
177
+
178
+
struct clk_hw *clk_hw_register_fixed_factor_parent_hw(struct device *dev,
179
+
const char *name, const struct clk_hw *parent_hw,
180
+
unsigned long flags, unsigned int mult, unsigned int div)
181
+
{
182
+
return __clk_hw_register_fixed_factor(dev, NULL, name, NULL,
183
+
parent_hw, -1, flags, mult, div,
184
+
false);
185
+
}
186
+
EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor_parent_hw);
158
187
159
188
struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
160
189
const char *name, const char *parent_name, unsigned long flags,
161
190
unsigned int mult, unsigned int div)
162
191
{
163
-
return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, -1,
192
+
return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL, -1,
164
193
flags, mult, div, false);
165
194
}
166
195
EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor);
···
239
204
const char *name, const char *parent_name, unsigned long flags,
240
205
unsigned int mult, unsigned int div)
241
206
{
242
-
return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, -1,
207
+
return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL, -1,
243
208
flags, mult, div, true);
244
209
}
245
210
EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor);
246
211
247
212
#ifdef CONFIG_OF
248
-
static const struct of_device_id set_rate_parent_matches[] = {
249
-
{ .compatible = "allwinner,sun4i-a10-pll3-2x-clk" },
250
-
{ /* Sentinel */ },
251
-
};
252
-
253
213
static struct clk_hw *_of_fixed_factor_clk_setup(struct device_node *node)
254
214
{
255
215
struct clk_hw *hw;
256
216
const char *clk_name = node->name;
257
-
unsigned long flags = 0;
258
217
u32 div, mult;
259
218
int ret;
260
219
···
266
237
267
238
of_property_read_string(node, "clock-output-names", &clk_name);
268
239
269
-
if (of_match_node(set_rate_parent_matches, node))
270
-
flags |= CLK_SET_RATE_PARENT;
271
-
272
-
hw = __clk_hw_register_fixed_factor(NULL, node, clk_name, NULL, 0,
273
-
flags, mult, div, false);
240
+
hw = __clk_hw_register_fixed_factor(NULL, node, clk_name, NULL, NULL, 0,
241
+
0, mult, div, false);
274
242
if (IS_ERR(hw)) {
275
243
/*
276
244
* Clear OF_POPULATED flag so that clock registration can be
-48
drivers/clk/clk.c
-48
drivers/clk/clk.c
···
4279
4279
}
4280
4280
EXPORT_SYMBOL_GPL(devm_clk_hw_register);
4281
4281
4282
-
static int devm_clk_match(struct device *dev, void *res, void *data)
4283
-
{
4284
-
struct clk *c = res;
4285
-
if (WARN_ON(!c))
4286
-
return 0;
4287
-
return c == data;
4288
-
}
4289
-
4290
-
static int devm_clk_hw_match(struct device *dev, void *res, void *data)
4291
-
{
4292
-
struct clk_hw *hw = res;
4293
-
4294
-
if (WARN_ON(!hw))
4295
-
return 0;
4296
-
return hw == data;
4297
-
}
4298
-
4299
-
/**
4300
-
* devm_clk_unregister - resource managed clk_unregister()
4301
-
* @dev: device that is unregistering the clock data
4302
-
* @clk: clock to unregister
4303
-
*
4304
-
* Deallocate a clock allocated with devm_clk_register(). Normally
4305
-
* this function will not need to be called and the resource management
4306
-
* code will ensure that the resource is freed.
4307
-
*/
4308
-
void devm_clk_unregister(struct device *dev, struct clk *clk)
4309
-
{
4310
-
WARN_ON(devres_release(dev, devm_clk_unregister_cb, devm_clk_match, clk));
4311
-
}
4312
-
EXPORT_SYMBOL_GPL(devm_clk_unregister);
4313
-
4314
-
/**
4315
-
* devm_clk_hw_unregister - resource managed clk_hw_unregister()
4316
-
* @dev: device that is unregistering the hardware-specific clock data
4317
-
* @hw: link to hardware-specific clock data
4318
-
*
4319
-
* Unregister a clk_hw registered with devm_clk_hw_register(). Normally
4320
-
* this function will not need to be called and the resource management
4321
-
* code will ensure that the resource is freed.
4322
-
*/
4323
-
void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw)
4324
-
{
4325
-
WARN_ON(devres_release(dev, devm_clk_hw_unregister_cb, devm_clk_hw_match,
4326
-
hw));
4327
-
}
4328
-
EXPORT_SYMBOL_GPL(devm_clk_hw_unregister);
4329
-
4330
4282
static void devm_clk_release(struct device *dev, void *res)
4331
4283
{
4332
4284
clk_put(*(struct clk **)res);
+21
-15
drivers/clk/imx/clk-fracn-gppll.c
+21
-15
drivers/clk/imx/clk-fracn-gppll.c
···
64
64
* Fout = Fvco / (rdiv * odiv)
65
65
*/
66
66
static const struct imx_fracn_gppll_rate_table fracn_tbl[] = {
67
-
PLL_FRACN_GP(650000000U, 81, 0, 0, 0, 3),
68
-
PLL_FRACN_GP(594000000U, 198, 0, 0, 0, 8),
69
-
PLL_FRACN_GP(560000000U, 70, 0, 0, 0, 3),
70
-
PLL_FRACN_GP(400000000U, 50, 0, 0, 0, 3),
67
+
PLL_FRACN_GP(650000000U, 81, 0, 1, 0, 3),
68
+
PLL_FRACN_GP(594000000U, 198, 0, 1, 0, 8),
69
+
PLL_FRACN_GP(560000000U, 70, 0, 1, 0, 3),
70
+
PLL_FRACN_GP(498000000U, 83, 0, 1, 0, 4),
71
+
PLL_FRACN_GP(484000000U, 121, 0, 1, 0, 6),
72
+
PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9),
73
+
PLL_FRACN_GP(400000000U, 50, 0, 1, 0, 3),
71
74
PLL_FRACN_GP(393216000U, 81, 92, 100, 0, 5)
72
75
};
73
76
···
134
131
mfi = FIELD_GET(PLL_MFI_MASK, pll_div);
135
132
136
133
rdiv = FIELD_GET(PLL_RDIV_MASK, pll_div);
137
-
rdiv = rdiv + 1;
138
134
odiv = FIELD_GET(PLL_ODIV_MASK, pll_div);
139
-
switch (odiv) {
140
-
case 0:
141
-
odiv = 2;
142
-
break;
143
-
case 1:
144
-
odiv = 3;
145
-
break;
146
-
default:
147
-
break;
148
-
}
149
135
150
136
/*
151
137
* Sometimes, the recalculated rate has deviation due to
···
151
159
152
160
if (rate)
153
161
return (unsigned long)rate;
162
+
163
+
if (!rdiv)
164
+
rdiv = rdiv + 1;
165
+
166
+
switch (odiv) {
167
+
case 0:
168
+
odiv = 2;
169
+
break;
170
+
case 1:
171
+
odiv = 3;
172
+
break;
173
+
default:
174
+
break;
175
+
}
154
176
155
177
/* Fvco = Fref * (MFI + MFN / MFD) */
156
178
fvco = fvco * mfi * mfd + fvco * mfn;
+3
-3
drivers/clk/imx/clk-imx93.c
+3
-3
drivers/clk/imx/clk-imx93.c
···
150
150
{ IMX93_CLK_A55_GATE, "a55", "a55_root", 0x8000, },
151
151
/* M33 critical clk for system run */
152
152
{ IMX93_CLK_CM33_GATE, "cm33", "m33_root", 0x8040, CLK_IS_CRITICAL },
153
-
{ IMX93_CLK_ADC1_GATE, "adc1", "osc_24m", 0x82c0, },
153
+
{ IMX93_CLK_ADC1_GATE, "adc1", "adc_root", 0x82c0, },
154
154
{ IMX93_CLK_WDOG1_GATE, "wdog1", "osc_24m", 0x8300, },
155
155
{ IMX93_CLK_WDOG2_GATE, "wdog2", "osc_24m", 0x8340, },
156
156
{ IMX93_CLK_WDOG3_GATE, "wdog3", "osc_24m", 0x8380, },
···
160
160
{ IMX93_CLK_SEMA2_GATE, "sema2", "bus_wakeup_root", 0x8480, },
161
161
{ IMX93_CLK_MU_A_GATE, "mu_a", "bus_aon_root", 0x84c0, },
162
162
{ IMX93_CLK_MU_B_GATE, "mu_b", "bus_aon_root", 0x8500, },
163
-
{ IMX93_CLK_EDMA1_GATE, "edma1", "wakeup_axi_root", 0x8540, },
163
+
{ IMX93_CLK_EDMA1_GATE, "edma1", "m33_root", 0x8540, },
164
164
{ IMX93_CLK_EDMA2_GATE, "edma2", "wakeup_axi_root", 0x8580, },
165
165
{ IMX93_CLK_FLEXSPI1_GATE, "flexspi", "flexspi_root", 0x8640, },
166
166
{ IMX93_CLK_GPIO1_GATE, "gpio1", "m33_root", 0x8880, },
···
219
219
{ IMX93_CLK_LCDIF_GATE, "lcdif", "media_apb_root", 0x9640, },
220
220
{ IMX93_CLK_PXP_GATE, "pxp", "media_apb_root", 0x9680, },
221
221
{ IMX93_CLK_ISI_GATE, "isi", "media_apb_root", 0x96c0, },
222
-
{ IMX93_CLK_NIC_MEDIA_GATE, "nic_media", "media_apb_root", 0x9700, },
222
+
{ IMX93_CLK_NIC_MEDIA_GATE, "nic_media", "media_axi_root", 0x9700, },
223
223
{ IMX93_CLK_USB_CONTROLLER_GATE, "usb_controller", "hsio_root", 0x9a00, },
224
224
{ IMX93_CLK_USB_TEST_60M_GATE, "usb_test_60m", "hsio_usb_test_60m_root", 0x9a40, },
225
225
{ IMX93_CLK_HSIO_TROUT_24M_GATE, "hsio_trout_24m", "osc_24m", 0x9a80, },
+9
-1
drivers/clk/mediatek/clk-mt2701-eth.c
+9
-1
drivers/clk/mediatek/clk-mt2701-eth.c
···
36
36
GATE_ETH(CLK_ETHSYS_CRYPTO, "crypto_clk", "ethif_sel", 29),
37
37
};
38
38
39
+
static u16 rst_ofs[] = { 0x34, };
40
+
41
+
static const struct mtk_clk_rst_desc clk_rst_desc = {
42
+
.version = MTK_RST_SIMPLE,
43
+
.rst_bank_ofs = rst_ofs,
44
+
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
45
+
};
46
+
39
47
static const struct of_device_id of_match_clk_mt2701_eth[] = {
40
48
{ .compatible = "mediatek,mt2701-ethsys", },
41
49
{}
···
66
58
"could not register clock provider: %s: %d\n",
67
59
pdev->name, r);
68
60
69
-
mtk_register_reset_controller(node, 1, 0x34);
61
+
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
70
62
71
63
return r;
72
64
}
+9
-1
drivers/clk/mediatek/clk-mt2701-g3d.c
+9
-1
drivers/clk/mediatek/clk-mt2701-g3d.c
···
35
35
GATE_G3D(CLK_G3DSYS_CORE, "g3d_core", "mfg_sel", 0),
36
36
};
37
37
38
+
static u16 rst_ofs[] = { 0xc, };
39
+
40
+
static const struct mtk_clk_rst_desc clk_rst_desc = {
41
+
.version = MTK_RST_SIMPLE,
42
+
.rst_bank_ofs = rst_ofs,
43
+
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
44
+
};
45
+
38
46
static int clk_mt2701_g3dsys_init(struct platform_device *pdev)
39
47
{
40
48
struct clk_hw_onecell_data *clk_data;
···
60
52
"could not register clock provider: %s: %d\n",
61
53
pdev->name, r);
62
54
63
-
mtk_register_reset_controller(node, 1, 0xc);
55
+
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
64
56
65
57
return r;
66
58
}
+9
-1
drivers/clk/mediatek/clk-mt2701-hif.c
+9
-1
drivers/clk/mediatek/clk-mt2701-hif.c
···
33
33
GATE_HIF(CLK_HIFSYS_PCIE2, "pcie2_clk", "ethpll_500m_ck", 26),
34
34
};
35
35
36
+
static u16 rst_ofs[] = { 0x34, };
37
+
38
+
static const struct mtk_clk_rst_desc clk_rst_desc = {
39
+
.version = MTK_RST_SIMPLE,
40
+
.rst_bank_ofs = rst_ofs,
41
+
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
42
+
};
43
+
36
44
static const struct of_device_id of_match_clk_mt2701_hif[] = {
37
45
{ .compatible = "mediatek,mt2701-hifsys", },
38
46
{}
···
65
57
return r;
66
58
}
67
59
68
-
mtk_register_reset_controller(node, 1, 0x34);
60
+
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
69
61
70
62
return 0;
71
63
}
+20
-2
drivers/clk/mediatek/clk-mt2701.c
+20
-2
drivers/clk/mediatek/clk-mt2701.c
···
735
735
FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2),
736
736
};
737
737
738
+
static u16 infrasys_rst_ofs[] = { 0x30, 0x34, };
739
+
static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };
740
+
741
+
static const struct mtk_clk_rst_desc clk_rst_desc[] = {
742
+
/* infrasys */
743
+
{
744
+
.version = MTK_RST_SIMPLE,
745
+
.rst_bank_ofs = infrasys_rst_ofs,
746
+
.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
747
+
},
748
+
/* pericfg */
749
+
{
750
+
.version = MTK_RST_SIMPLE,
751
+
.rst_bank_ofs = pericfg_rst_ofs,
752
+
.rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),
753
+
},
754
+
};
755
+
738
756
static struct clk_hw_onecell_data *infra_clk_data;
739
757
740
758
static void __init mtk_infrasys_init_early(struct device_node *node)
···
805
787
if (r)
806
788
return r;
807
789
808
-
mtk_register_reset_controller(node, 2, 0x30);
790
+
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]);
809
791
810
792
return 0;
811
793
}
···
928
910
if (r)
929
911
return r;
930
912
931
-
mtk_register_reset_controller(node, 2, 0x0);
913
+
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);
932
914
933
915
return 0;
934
916
}
+20
-2
drivers/clk/mediatek/clk-mt2712.c
+20
-2
drivers/clk/mediatek/clk-mt2712.c
···
1258
1258
0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0),
1259
1259
};
1260
1260
1261
+
static u16 infrasys_rst_ofs[] = { 0x30, 0x34, };
1262
+
static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };
1263
+
1264
+
static const struct mtk_clk_rst_desc clk_rst_desc[] = {
1265
+
/* infra */
1266
+
{
1267
+
.version = MTK_RST_SIMPLE,
1268
+
.rst_bank_ofs = infrasys_rst_ofs,
1269
+
.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
1270
+
},
1271
+
/* peri */
1272
+
{
1273
+
.version = MTK_RST_SIMPLE,
1274
+
.rst_bank_ofs = pericfg_rst_ofs,
1275
+
.rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),
1276
+
},
1277
+
};
1278
+
1261
1279
static int clk_mt2712_apmixed_probe(struct platform_device *pdev)
1262
1280
{
1263
1281
struct clk_hw_onecell_data *clk_data;
···
1379
1361
pr_err("%s(): could not register clock provider: %d\n",
1380
1362
__func__, r);
1381
1363
1382
-
mtk_register_reset_controller(node, 2, 0x30);
1364
+
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]);
1383
1365
1384
1366
return r;
1385
1367
}
···
1401
1383
pr_err("%s(): could not register clock provider: %d\n",
1402
1384
__func__, r);
1403
1385
1404
-
mtk_register_reset_controller(node, 2, 0);
1386
+
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);
1405
1387
1406
1388
return r;
1407
1389
}
+9
-1
drivers/clk/mediatek/clk-mt7622-eth.c
+9
-1
drivers/clk/mediatek/clk-mt7622-eth.c
···
65
65
"ssusb_cdr_fb", 5),
66
66
};
67
67
68
+
static u16 rst_ofs[] = { 0x34, };
69
+
70
+
static const struct mtk_clk_rst_desc clk_rst_desc = {
71
+
.version = MTK_RST_SIMPLE,
72
+
.rst_bank_ofs = rst_ofs,
73
+
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
74
+
};
75
+
68
76
static int clk_mt7622_ethsys_init(struct platform_device *pdev)
69
77
{
70
78
struct clk_hw_onecell_data *clk_data;
···
90
82
"could not register clock provider: %s: %d\n",
91
83
pdev->name, r);
92
84
93
-
mtk_register_reset_controller(node, 1, 0x34);
85
+
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
94
86
95
87
return r;
96
88
}
+10
-2
drivers/clk/mediatek/clk-mt7622-hif.c
+10
-2
drivers/clk/mediatek/clk-mt7622-hif.c
···
76
76
GATE_PCIE(CLK_SATA_PM_EN, "sata_pm_en", "univpll2_d4", 30),
77
77
};
78
78
79
+
static u16 rst_ofs[] = { 0x34, };
80
+
81
+
static const struct mtk_clk_rst_desc clk_rst_desc = {
82
+
.version = MTK_RST_SIMPLE,
83
+
.rst_bank_ofs = rst_ofs,
84
+
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
85
+
};
86
+
79
87
static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)
80
88
{
81
89
struct clk_hw_onecell_data *clk_data;
···
101
93
"could not register clock provider: %s: %d\n",
102
94
pdev->name, r);
103
95
104
-
mtk_register_reset_controller(node, 1, 0x34);
96
+
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
105
97
106
98
return r;
107
99
}
···
123
115
"could not register clock provider: %s: %d\n",
124
116
pdev->name, r);
125
117
126
-
mtk_register_reset_controller(node, 1, 0x34);
118
+
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
127
119
128
120
return r;
129
121
}
+20
-2
drivers/clk/mediatek/clk-mt7622.c
+20
-2
drivers/clk/mediatek/clk-mt7622.c
···
610
610
MUX(CLK_PERIBUS_SEL, "peribus_ck_sel", peribus_ck_parents, 0x05C, 0, 1),
611
611
};
612
612
613
+
static u16 infrasys_rst_ofs[] = { 0x30, };
614
+
static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };
615
+
616
+
static const struct mtk_clk_rst_desc clk_rst_desc[] = {
617
+
/* infrasys */
618
+
{
619
+
.version = MTK_RST_SIMPLE,
620
+
.rst_bank_ofs = infrasys_rst_ofs,
621
+
.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
622
+
},
623
+
/* pericfg */
624
+
{
625
+
.version = MTK_RST_SIMPLE,
626
+
.rst_bank_ofs = pericfg_rst_ofs,
627
+
.rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),
628
+
},
629
+
};
630
+
613
631
static int mtk_topckgen_init(struct platform_device *pdev)
614
632
{
615
633
struct clk_hw_onecell_data *clk_data;
···
681
663
if (r)
682
664
return r;
683
665
684
-
mtk_register_reset_controller(node, 1, 0x30);
666
+
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]);
685
667
686
668
return 0;
687
669
}
···
732
714
733
715
clk_prepare_enable(clk_data->hws[CLK_PERI_UART0_PD]->clk);
734
716
735
-
mtk_register_reset_controller(node, 2, 0x0);
717
+
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);
736
718
737
719
return 0;
738
720
}
+9
-1
drivers/clk/mediatek/clk-mt7629-eth.c
+9
-1
drivers/clk/mediatek/clk-mt7629-eth.c
···
76
76
}
77
77
};
78
78
79
+
static u16 rst_ofs[] = { 0x34, };
80
+
81
+
static const struct mtk_clk_rst_desc clk_rst_desc = {
82
+
.version = MTK_RST_SIMPLE,
83
+
.rst_bank_ofs = rst_ofs,
84
+
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
85
+
};
86
+
79
87
static int clk_mt7629_ethsys_init(struct platform_device *pdev)
80
88
{
81
89
struct clk_hw_onecell_data *clk_data;
···
100
92
"could not register clock provider: %s: %d\n",
101
93
pdev->name, r);
102
94
103
-
mtk_register_reset_controller(node, 1, 0x34);
95
+
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
104
96
105
97
return r;
106
98
}
+10
-2
drivers/clk/mediatek/clk-mt7629-hif.c
+10
-2
drivers/clk/mediatek/clk-mt7629-hif.c
···
71
71
GATE_PCIE(CLK_PCIE_P0_PIPE_EN, "pcie_p0_pipe_en", "pcie0_pipe_en", 23),
72
72
};
73
73
74
+
static u16 rst_ofs[] = { 0x34, };
75
+
76
+
static const struct mtk_clk_rst_desc clk_rst_desc = {
77
+
.version = MTK_RST_SIMPLE,
78
+
.rst_bank_ofs = rst_ofs,
79
+
.rst_bank_nr = ARRAY_SIZE(rst_ofs),
80
+
};
81
+
74
82
static int clk_mt7629_ssusbsys_init(struct platform_device *pdev)
75
83
{
76
84
struct clk_hw_onecell_data *clk_data;
···
96
88
"could not register clock provider: %s: %d\n",
97
89
pdev->name, r);
98
90
99
-
mtk_register_reset_controller(node, 1, 0x34);
91
+
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
100
92
101
93
return r;
102
94
}
···
118
110
"could not register clock provider: %s: %d\n",
119
111
pdev->name, r);
120
112
121
-
mtk_register_reset_controller(node, 1, 0x34);
113
+
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
122
114
123
115
return r;
124
116
}
+20
-2
drivers/clk/mediatek/clk-mt8135.c
+20
-2
drivers/clk/mediatek/clk-mt8135.c
···
514
514
MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1),
515
515
};
516
516
517
+
static u16 infrasys_rst_ofs[] = { 0x30, 0x34, };
518
+
static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };
519
+
520
+
static const struct mtk_clk_rst_desc clk_rst_desc[] = {
521
+
/* infrasys */
522
+
{
523
+
.version = MTK_RST_SIMPLE,
524
+
.rst_bank_ofs = infrasys_rst_ofs,
525
+
.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
526
+
},
527
+
/* pericfg */
528
+
{
529
+
.version = MTK_RST_SIMPLE,
530
+
.rst_bank_ofs = pericfg_rst_ofs,
531
+
.rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),
532
+
}
533
+
};
534
+
517
535
static void __init mtk_topckgen_init(struct device_node *node)
518
536
{
519
537
struct clk_hw_onecell_data *clk_data;
···
577
559
pr_err("%s(): could not register clock provider: %d\n",
578
560
__func__, r);
579
561
580
-
mtk_register_reset_controller(node, 2, 0x30);
562
+
mtk_register_reset_controller(node, &clk_rst_desc[0]);
581
563
}
582
564
CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8135-infracfg", mtk_infrasys_init);
583
565
···
605
587
pr_err("%s(): could not register clock provider: %d\n",
606
588
__func__, r);
607
589
608
-
mtk_register_reset_controller(node, 2, 0);
590
+
mtk_register_reset_controller(node, &clk_rst_desc[1]);
609
591
}
610
592
CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8135-pericfg", mtk_pericfg_init);
611
593
+20
-2
drivers/clk/mediatek/clk-mt8173.c
+20
-2
drivers/clk/mediatek/clk-mt8173.c
···
819
819
GATE_VENCLT(CLK_VENCLT_CKE1, "venclt_cke1", "venclt_sel", 4),
820
820
};
821
821
822
+
static u16 infrasys_rst_ofs[] = { 0x30, 0x34, };
823
+
static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };
824
+
825
+
static const struct mtk_clk_rst_desc clk_rst_desc[] = {
826
+
/* infrasys */
827
+
{
828
+
.version = MTK_RST_SIMPLE,
829
+
.rst_bank_ofs = infrasys_rst_ofs,
830
+
.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
831
+
},
832
+
/* pericfg */
833
+
{
834
+
.version = MTK_RST_SIMPLE,
835
+
.rst_bank_ofs = pericfg_rst_ofs,
836
+
.rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),
837
+
}
838
+
};
839
+
822
840
static struct clk_hw_onecell_data *mt8173_top_clk_data __initdata;
823
841
static struct clk_hw_onecell_data *mt8173_pll_clk_data __initdata;
824
842
···
900
882
pr_err("%s(): could not register clock provider: %d\n",
901
883
__func__, r);
902
884
903
-
mtk_register_reset_controller(node, 2, 0x30);
885
+
mtk_register_reset_controller(node, &clk_rst_desc[0]);
904
886
}
905
887
CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8173-infracfg", mtk_infrasys_init);
906
888
···
928
910
pr_err("%s(): could not register clock provider: %d\n",
929
911
__func__, r);
930
912
931
-
mtk_register_reset_controller(node, 2, 0);
913
+
mtk_register_reset_controller(node, &clk_rst_desc[1]);
932
914
}
933
915
CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8173-pericfg", mtk_pericfg_init);
934
916
+14
-4
drivers/clk/mediatek/clk-mt8183.c
+14
-4
drivers/clk/mediatek/clk-mt8183.c
···
18
18
19
19
#include <dt-bindings/clock/mt8183-clk.h>
20
20
21
-
/* Infra global controller reset set register */
22
-
#define INFRA_RST0_SET_OFFSET 0x120
23
-
24
21
static DEFINE_SPINLOCK(mt8183_clk_lock);
25
22
26
23
static const struct mtk_fixed_clk top_fixed_clks[] = {
···
1150
1153
0, 0, 32, 8, 0x02B4, 1, 0x02BC, 0x0014, 1, 0x02B8, 0, 0x02B4),
1151
1154
};
1152
1155
1156
+
static u16 infra_rst_ofs[] = {
1157
+
INFRA_RST0_SET_OFFSET,
1158
+
INFRA_RST1_SET_OFFSET,
1159
+
INFRA_RST2_SET_OFFSET,
1160
+
INFRA_RST3_SET_OFFSET,
1161
+
};
1162
+
1163
+
static const struct mtk_clk_rst_desc clk_rst_desc = {
1164
+
.version = MTK_RST_SET_CLR,
1165
+
.rst_bank_ofs = infra_rst_ofs,
1166
+
.rst_bank_nr = ARRAY_SIZE(infra_rst_ofs),
1167
+
};
1168
+
1153
1169
static int clk_mt8183_apmixed_probe(struct platform_device *pdev)
1154
1170
{
1155
1171
struct clk_hw_onecell_data *clk_data;
···
1250
1240
return r;
1251
1241
}
1252
1242
1253
-
mtk_register_reset_controller_set_clr(node, 4, INFRA_RST0_SET_OFFSET);
1243
+
mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
1254
1244
1255
1245
return r;
1256
1246
}
+23
drivers/clk/mediatek/clk-mt8186-infra_ao.c
+23
drivers/clk/mediatek/clk-mt8186-infra_ao.c
···
6
6
#include <linux/clk-provider.h>
7
7
#include <linux/platform_device.h>
8
8
#include <dt-bindings/clock/mt8186-clk.h>
9
+
#include <dt-bindings/reset/mt8186-resets.h>
9
10
10
11
#include "clk-gate.h"
11
12
#include "clk-mtk.h"
···
192
191
GATE_INFRA_AO3(CLK_INFRA_AO_FLASHIF_66M, "infra_ao_flashif_66m", "top_axi", 29),
193
192
};
194
193
194
+
static u16 infra_ao_rst_ofs[] = {
195
+
INFRA_RST0_SET_OFFSET,
196
+
INFRA_RST1_SET_OFFSET,
197
+
INFRA_RST2_SET_OFFSET,
198
+
INFRA_RST3_SET_OFFSET,
199
+
INFRA_RST4_SET_OFFSET,
200
+
};
201
+
202
+
static u16 infra_ao_idx_map[] = {
203
+
[MT8186_INFRA_THERMAL_CTRL_RST] = 0 * RST_NR_PER_BANK + 0,
204
+
[MT8186_INFRA_PTP_CTRL_RST] = 1 * RST_NR_PER_BANK + 0,
205
+
};
206
+
207
+
static struct mtk_clk_rst_desc infra_ao_rst_desc = {
208
+
.version = MTK_RST_SET_CLR,
209
+
.rst_bank_ofs = infra_ao_rst_ofs,
210
+
.rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs),
211
+
.rst_idx_map = infra_ao_idx_map,
212
+
.rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map),
213
+
};
214
+
195
215
static const struct mtk_clk_desc infra_ao_desc = {
196
216
.clks = infra_ao_clks,
197
217
.num_clks = ARRAY_SIZE(infra_ao_clks),
218
+
.rst_desc = &infra_ao_rst_desc,
198
219
};
199
220
200
221
static const struct of_device_id of_match_clk_mt8186_infra_ao[] = {
-21
drivers/clk/mediatek/clk-mt8192-msdc.c
-21
drivers/clk/mediatek/clk-mt8192-msdc.c
···
12
12
13
13
#include <dt-bindings/clock/mt8192-clk.h>
14
14
15
-
static const struct mtk_gate_regs msdc_cg_regs = {
16
-
.set_ofs = 0xb4,
17
-
.clr_ofs = 0xb4,
18
-
.sta_ofs = 0xb4,
19
-
};
20
-
21
15
static const struct mtk_gate_regs msdc_top_cg_regs = {
22
16
.set_ofs = 0x0,
23
17
.clr_ofs = 0x0,
24
18
.sta_ofs = 0x0,
25
19
};
26
20
27
-
#define GATE_MSDC(_id, _name, _parent, _shift) \
28
-
GATE_MTK(_id, _name, _parent, &msdc_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
29
-
30
21
#define GATE_MSDC_TOP(_id, _name, _parent, _shift) \
31
22
GATE_MTK(_id, _name, _parent, &msdc_top_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
32
-
33
-
static const struct mtk_gate msdc_clks[] = {
34
-
GATE_MSDC(CLK_MSDC_AXI_WRAP, "msdc_axi_wrap", "axi_sel", 22),
35
-
};
36
23
37
24
static const struct mtk_gate msdc_top_clks[] = {
38
25
GATE_MSDC_TOP(CLK_MSDC_TOP_AES_0P, "msdc_top_aes_0p", "aes_msdcfde_sel", 0),
···
39
52
GATE_MSDC_TOP(CLK_MSDC_TOP_AHB2AXI_BRG_AXI, "msdc_top_ahb2axi_brg_axi", "axi_sel", 14),
40
53
};
41
54
42
-
static const struct mtk_clk_desc msdc_desc = {
43
-
.clks = msdc_clks,
44
-
.num_clks = ARRAY_SIZE(msdc_clks),
45
-
};
46
-
47
55
static const struct mtk_clk_desc msdc_top_desc = {
48
56
.clks = msdc_top_clks,
49
57
.num_clks = ARRAY_SIZE(msdc_top_clks),
···
46
64
47
65
static const struct of_device_id of_match_clk_mt8192_msdc[] = {
48
66
{
49
-
.compatible = "mediatek,mt8192-msdc",
50
-
.data = &msdc_desc,
51
-
}, {
52
67
.compatible = "mediatek,mt8192-msdc_top",
53
68
.data = &msdc_top_desc,
54
69
}, {
+29
drivers/clk/mediatek/clk-mt8192.c
+29
drivers/clk/mediatek/clk-mt8192.c
···
18
18
#include "clk-pll.h"
19
19
20
20
#include <dt-bindings/clock/mt8192-clk.h>
21
+
#include <dt-bindings/reset/mt8192-resets.h>
21
22
22
23
static DEFINE_SPINLOCK(mt8192_clk_lock);
23
24
···
1115
1114
GATE_TOP(CLK_TOP_SSUSB_PHY_REF, "ssusb_phy_ref", "clk26m", 25),
1116
1115
};
1117
1116
1117
+
static u16 infra_ao_rst_ofs[] = {
1118
+
INFRA_RST0_SET_OFFSET,
1119
+
INFRA_RST1_SET_OFFSET,
1120
+
INFRA_RST2_SET_OFFSET,
1121
+
INFRA_RST3_SET_OFFSET,
1122
+
INFRA_RST4_SET_OFFSET,
1123
+
};
1124
+
1125
+
static u16 infra_ao_idx_map[] = {
1126
+
[MT8192_INFRA_RST0_THERM_CTRL_SWRST] = 0 * RST_NR_PER_BANK + 0,
1127
+
[MT8192_INFRA_RST2_PEXTP_PHY_SWRST] = 2 * RST_NR_PER_BANK + 15,
1128
+
[MT8192_INFRA_RST3_THERM_CTRL_PTP_SWRST] = 3 * RST_NR_PER_BANK + 5,
1129
+
[MT8192_INFRA_RST4_PCIE_TOP_SWRST] = 4 * RST_NR_PER_BANK + 1,
1130
+
[MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST] = 4 * RST_NR_PER_BANK + 12,
1131
+
};
1132
+
1133
+
static const struct mtk_clk_rst_desc clk_rst_desc = {
1134
+
.version = MTK_RST_SET_CLR,
1135
+
.rst_bank_ofs = infra_ao_rst_ofs,
1136
+
.rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs),
1137
+
.rst_idx_map = infra_ao_idx_map,
1138
+
.rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map),
1139
+
};
1140
+
1118
1141
#define MT8192_PLL_FMAX (3800UL * MHZ)
1119
1142
#define MT8192_PLL_FMIN (1500UL * MHZ)
1120
1143
#define MT8192_INTEGER_BITS 8
···
1262
1237
return -ENOMEM;
1263
1238
1264
1239
r = mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks), clk_data);
1240
+
if (r)
1241
+
goto free_clk_data;
1242
+
1243
+
r = mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
1265
1244
if (r)
1266
1245
goto free_clk_data;
1267
1246
+24
drivers/clk/mediatek/clk-mt8195-infra_ao.c
+24
drivers/clk/mediatek/clk-mt8195-infra_ao.c
···
7
7
#include "clk-mtk.h"
8
8
9
9
#include <dt-bindings/clock/mt8195-clk.h>
10
+
#include <dt-bindings/reset/mt8195-resets.h>
10
11
#include <linux/clk-provider.h>
11
12
#include <linux/platform_device.h>
12
13
···
183
182
GATE_INFRA_AO4(CLK_INFRA_AO_PERI_UFS_MEM_SUB, "infra_ao_peri_ufs_mem_sub", "mem_466m", 31),
184
183
};
185
184
185
+
static u16 infra_ao_rst_ofs[] = {
186
+
INFRA_RST0_SET_OFFSET,
187
+
INFRA_RST1_SET_OFFSET,
188
+
INFRA_RST2_SET_OFFSET,
189
+
INFRA_RST3_SET_OFFSET,
190
+
INFRA_RST4_SET_OFFSET,
191
+
};
192
+
193
+
static u16 infra_ao_idx_map[] = {
194
+
[MT8195_INFRA_RST0_THERM_CTRL_SWRST] = 0 * RST_NR_PER_BANK + 0,
195
+
[MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST] = 3 * RST_NR_PER_BANK + 5,
196
+
[MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST] = 4 * RST_NR_PER_BANK + 10,
197
+
};
198
+
199
+
static struct mtk_clk_rst_desc infra_ao_rst_desc = {
200
+
.version = MTK_RST_SET_CLR,
201
+
.rst_bank_ofs = infra_ao_rst_ofs,
202
+
.rst_bank_nr = ARRAY_SIZE(infra_ao_rst_ofs),
203
+
.rst_idx_map = infra_ao_idx_map,
204
+
.rst_idx_map_nr = ARRAY_SIZE(infra_ao_idx_map),
205
+
};
206
+
186
207
static const struct mtk_clk_desc infra_ao_desc = {
187
208
.clks = infra_ao_clks,
188
209
.num_clks = ARRAY_SIZE(infra_ao_clks),
210
+
.rst_desc = &infra_ao_rst_desc,
189
211
};
190
212
191
213
static const struct of_device_id of_match_clk_mt8195_infra_ao[] = {
+7
drivers/clk/mediatek/clk-mtk.c
+7
drivers/clk/mediatek/clk-mtk.c
+3
-6
drivers/clk/mediatek/clk-mtk.h
+3
-6
drivers/clk/mediatek/clk-mtk.h
···
13
13
#include <linux/spinlock.h>
14
14
#include <linux/types.h>
15
15
16
+
#include "reset.h"
17
+
16
18
#define MAX_MUX_GATE_BIT 31
17
19
#define INVALID_MUX_GATE_BIT (MAX_MUX_GATE_BIT + 1)
18
20
···
189
187
struct clk_hw *mtk_clk_register_ref2usb_tx(const char *name,
190
188
const char *parent_name, void __iomem *reg);
191
189
192
-
void mtk_register_reset_controller(struct device_node *np,
193
-
unsigned int num_regs, int regofs);
194
-
195
-
void mtk_register_reset_controller_set_clr(struct device_node *np,
196
-
unsigned int num_regs, int regofs);
197
-
198
190
struct mtk_clk_desc {
199
191
const struct mtk_gate *clks;
200
192
size_t num_clks;
193
+
const struct mtk_clk_rst_desc *rst_desc;
201
194
};
202
195
203
196
int mtk_clk_simple_probe(struct platform_device *pdev);
+145
-53
drivers/clk/mediatek/reset.c
+145
-53
drivers/clk/mediatek/reset.c
···
8
8
#include <linux/of.h>
9
9
#include <linux/platform_device.h>
10
10
#include <linux/regmap.h>
11
-
#include <linux/reset-controller.h>
12
11
#include <linux/slab.h>
13
12
14
-
#include "clk-mtk.h"
13
+
#include "reset.h"
15
14
16
-
struct mtk_reset {
17
-
struct regmap *regmap;
18
-
int regofs;
19
-
struct reset_controller_dev rcdev;
20
-
};
21
-
22
-
static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev,
23
-
unsigned long id)
15
+
static inline struct mtk_clk_rst_data *to_mtk_clk_rst_data(struct reset_controller_dev *rcdev)
24
16
{
25
-
struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
26
-
unsigned int reg = data->regofs + ((id / 32) << 4);
27
-
28
-
return regmap_write(data->regmap, reg, 1);
17
+
return container_of(rcdev, struct mtk_clk_rst_data, rcdev);
29
18
}
30
19
31
-
static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev,
32
-
unsigned long id)
20
+
static int mtk_reset_update(struct reset_controller_dev *rcdev,
21
+
unsigned long id, bool deassert)
33
22
{
34
-
struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
35
-
unsigned int reg = data->regofs + ((id / 32) << 4) + 0x4;
23
+
struct mtk_clk_rst_data *data = to_mtk_clk_rst_data(rcdev);
24
+
unsigned int val = deassert ? 0 : ~0;
36
25
37
-
return regmap_write(data->regmap, reg, 1);
26
+
return regmap_update_bits(data->regmap,
27
+
data->desc->rst_bank_ofs[id / RST_NR_PER_BANK],
28
+
BIT(id % RST_NR_PER_BANK), val);
38
29
}
39
30
40
31
static int mtk_reset_assert(struct reset_controller_dev *rcdev,
41
-
unsigned long id)
32
+
unsigned long id)
42
33
{
43
-
struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
44
-
45
-
return regmap_update_bits(data->regmap, data->regofs + ((id / 32) << 2),
46
-
BIT(id % 32), ~0);
34
+
return mtk_reset_update(rcdev, id, false);
47
35
}
48
36
49
37
static int mtk_reset_deassert(struct reset_controller_dev *rcdev,
50
-
unsigned long id)
38
+
unsigned long id)
51
39
{
52
-
struct mtk_reset *data = container_of(rcdev, struct mtk_reset, rcdev);
53
-
54
-
return regmap_update_bits(data->regmap, data->regofs + ((id / 32) << 2),
55
-
BIT(id % 32), 0);
40
+
return mtk_reset_update(rcdev, id, true);
56
41
}
57
42
58
-
static int mtk_reset(struct reset_controller_dev *rcdev,
59
-
unsigned long id)
43
+
static int mtk_reset(struct reset_controller_dev *rcdev, unsigned long id)
60
44
{
61
45
int ret;
62
46
···
51
67
return mtk_reset_deassert(rcdev, id);
52
68
}
53
69
70
+
static int mtk_reset_update_set_clr(struct reset_controller_dev *rcdev,
71
+
unsigned long id, bool deassert)
72
+
{
73
+
struct mtk_clk_rst_data *data = to_mtk_clk_rst_data(rcdev);
74
+
unsigned int deassert_ofs = deassert ? 0x4 : 0;
75
+
76
+
return regmap_write(data->regmap,
77
+
data->desc->rst_bank_ofs[id / RST_NR_PER_BANK] +
78
+
deassert_ofs,
79
+
BIT(id % RST_NR_PER_BANK));
80
+
}
81
+
82
+
static int mtk_reset_assert_set_clr(struct reset_controller_dev *rcdev,
83
+
unsigned long id)
84
+
{
85
+
return mtk_reset_update_set_clr(rcdev, id, false);
86
+
}
87
+
88
+
static int mtk_reset_deassert_set_clr(struct reset_controller_dev *rcdev,
89
+
unsigned long id)
90
+
{
91
+
return mtk_reset_update_set_clr(rcdev, id, true);
92
+
}
93
+
54
94
static int mtk_reset_set_clr(struct reset_controller_dev *rcdev,
55
-
unsigned long id)
95
+
unsigned long id)
56
96
{
57
97
int ret;
58
98
···
98
90
.reset = mtk_reset_set_clr,
99
91
};
100
92
101
-
static void mtk_register_reset_controller_common(struct device_node *np,
102
-
unsigned int num_regs, int regofs,
103
-
const struct reset_control_ops *reset_ops)
93
+
static int reset_xlate(struct reset_controller_dev *rcdev,
94
+
const struct of_phandle_args *reset_spec)
104
95
{
105
-
struct mtk_reset *data;
106
-
int ret;
96
+
struct mtk_clk_rst_data *data = to_mtk_clk_rst_data(rcdev);
97
+
98
+
if (reset_spec->args[0] >= rcdev->nr_resets ||
99
+
reset_spec->args[0] >= data->desc->rst_idx_map_nr)
100
+
return -EINVAL;
101
+
102
+
return data->desc->rst_idx_map[reset_spec->args[0]];
103
+
}
104
+
105
+
int mtk_register_reset_controller(struct device_node *np,
106
+
const struct mtk_clk_rst_desc *desc)
107
+
{
107
108
struct regmap *regmap;
109
+
const struct reset_control_ops *rcops = NULL;
110
+
struct mtk_clk_rst_data *data;
111
+
int ret;
112
+
113
+
if (!desc) {
114
+
pr_err("mtk clock reset desc is NULL\n");
115
+
return -EINVAL;
116
+
}
117
+
118
+
switch (desc->version) {
119
+
case MTK_RST_SIMPLE:
120
+
rcops = &mtk_reset_ops;
121
+
break;
122
+
case MTK_RST_SET_CLR:
123
+
rcops = &mtk_reset_ops_set_clr;
124
+
break;
125
+
default:
126
+
pr_err("Unknown reset version %d\n", desc->version);
127
+
return -EINVAL;
128
+
}
108
129
109
130
regmap = device_node_to_regmap(np);
110
131
if (IS_ERR(regmap)) {
111
132
pr_err("Cannot find regmap for %pOF: %pe\n", np, regmap);
112
-
return;
133
+
return -EINVAL;
113
134
}
114
135
115
136
data = kzalloc(sizeof(*data), GFP_KERNEL);
116
137
if (!data)
117
-
return;
138
+
return -ENOMEM;
118
139
140
+
data->desc = desc;
119
141
data->regmap = regmap;
120
-
data->regofs = regofs;
121
142
data->rcdev.owner = THIS_MODULE;
122
-
data->rcdev.nr_resets = num_regs * 32;
123
-
data->rcdev.ops = reset_ops;
143
+
data->rcdev.ops = rcops;
124
144
data->rcdev.of_node = np;
145
+
146
+
if (data->desc->rst_idx_map_nr > 0) {
147
+
data->rcdev.of_reset_n_cells = 1;
148
+
data->rcdev.nr_resets = desc->rst_idx_map_nr;
149
+
data->rcdev.of_xlate = reset_xlate;
150
+
} else {
151
+
data->rcdev.nr_resets = desc->rst_bank_nr * RST_NR_PER_BANK;
152
+
}
125
153
126
154
ret = reset_controller_register(&data->rcdev);
127
155
if (ret) {
128
156
pr_err("could not register reset controller: %d\n", ret);
129
157
kfree(data);
130
-
return;
158
+
return ret;
131
159
}
160
+
161
+
return 0;
132
162
}
133
163
134
-
void mtk_register_reset_controller(struct device_node *np,
135
-
unsigned int num_regs, int regofs)
164
+
int mtk_register_reset_controller_with_dev(struct device *dev,
165
+
const struct mtk_clk_rst_desc *desc)
136
166
{
137
-
mtk_register_reset_controller_common(np, num_regs, regofs,
138
-
&mtk_reset_ops);
139
-
}
167
+
struct device_node *np = dev->of_node;
168
+
struct regmap *regmap;
169
+
const struct reset_control_ops *rcops = NULL;
170
+
struct mtk_clk_rst_data *data;
171
+
int ret;
140
172
141
-
void mtk_register_reset_controller_set_clr(struct device_node *np,
142
-
unsigned int num_regs, int regofs)
143
-
{
144
-
mtk_register_reset_controller_common(np, num_regs, regofs,
145
-
&mtk_reset_ops_set_clr);
173
+
if (!desc) {
174
+
dev_err(dev, "mtk clock reset desc is NULL\n");
175
+
return -EINVAL;
176
+
}
177
+
178
+
switch (desc->version) {
179
+
case MTK_RST_SIMPLE:
180
+
rcops = &mtk_reset_ops;
181
+
break;
182
+
case MTK_RST_SET_CLR:
183
+
rcops = &mtk_reset_ops_set_clr;
184
+
break;
185
+
default:
186
+
dev_err(dev, "Unknown reset version %d\n", desc->version);
187
+
return -EINVAL;
188
+
}
189
+
190
+
regmap = device_node_to_regmap(np);
191
+
if (IS_ERR(regmap)) {
192
+
dev_err(dev, "Cannot find regmap %pe\n", regmap);
193
+
return -EINVAL;
194
+
}
195
+
196
+
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
197
+
if (!data)
198
+
return -ENOMEM;
199
+
200
+
data->desc = desc;
201
+
data->regmap = regmap;
202
+
data->rcdev.owner = THIS_MODULE;
203
+
data->rcdev.ops = rcops;
204
+
data->rcdev.of_node = np;
205
+
data->rcdev.dev = dev;
206
+
207
+
if (data->desc->rst_idx_map_nr > 0) {
208
+
data->rcdev.of_reset_n_cells = 1;
209
+
data->rcdev.nr_resets = desc->rst_idx_map_nr;
210
+
data->rcdev.of_xlate = reset_xlate;
211
+
} else {
212
+
data->rcdev.nr_resets = desc->rst_bank_nr * RST_NR_PER_BANK;
213
+
}
214
+
215
+
ret = devm_reset_controller_register(dev, &data->rcdev);
216
+
if (ret) {
217
+
dev_err(dev, "could not register reset controller: %d\n", ret);
218
+
return ret;
219
+
}
220
+
221
+
return 0;
146
222
}
147
223
148
224
MODULE_LICENSE("GPL");
+82
drivers/clk/mediatek/reset.h
+82
drivers/clk/mediatek/reset.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/*
3
+
* Copyright (c) 2022 MediaTek Inc.
4
+
*/
5
+
6
+
#ifndef __DRV_CLK_MTK_RESET_H
7
+
#define __DRV_CLK_MTK_RESET_H
8
+
9
+
#include <linux/reset-controller.h>
10
+
#include <linux/types.h>
11
+
12
+
#define RST_NR_PER_BANK 32
13
+
14
+
/* Infra global controller reset set register */
15
+
#define INFRA_RST0_SET_OFFSET 0x120
16
+
#define INFRA_RST1_SET_OFFSET 0x130
17
+
#define INFRA_RST2_SET_OFFSET 0x140
18
+
#define INFRA_RST3_SET_OFFSET 0x150
19
+
#define INFRA_RST4_SET_OFFSET 0x730
20
+
21
+
/**
22
+
* enum mtk_reset_version - Version of MediaTek clock reset controller.
23
+
* @MTK_RST_SIMPLE: Use the same registers for bit set and clear.
24
+
* @MTK_RST_SET_CLR: Use separate registers for bit set and clear.
25
+
* @MTK_RST_MAX: Total quantity of version for MediaTek clock reset controller.
26
+
*/
27
+
enum mtk_reset_version {
28
+
MTK_RST_SIMPLE = 0,
29
+
MTK_RST_SET_CLR,
30
+
MTK_RST_MAX,
31
+
};
32
+
33
+
/**
34
+
* struct mtk_clk_rst_desc - Description of MediaTek clock reset.
35
+
* @version: Reset version which is defined in enum mtk_reset_version.
36
+
* @rst_bank_ofs: Pointer to an array containing base offsets of the reset register.
37
+
* @rst_bank_nr: Quantity of reset bank.
38
+
* @rst_idx_map:Pointer to an array containing ids if input argument is index.
39
+
* This array is not necessary if our input argument does not mean index.
40
+
* @rst_idx_map_nr: Quantity of reset index map.
41
+
*/
42
+
struct mtk_clk_rst_desc {
43
+
enum mtk_reset_version version;
44
+
u16 *rst_bank_ofs;
45
+
u32 rst_bank_nr;
46
+
u16 *rst_idx_map;
47
+
u32 rst_idx_map_nr;
48
+
};
49
+
50
+
/**
51
+
* struct mtk_clk_rst_data - Data of MediaTek clock reset controller.
52
+
* @regmap: Pointer to base address of reset register address.
53
+
* @rcdev: Reset controller device.
54
+
* @desc: Pointer to description of the reset controller.
55
+
*/
56
+
struct mtk_clk_rst_data {
57
+
struct regmap *regmap;
58
+
struct reset_controller_dev rcdev;
59
+
const struct mtk_clk_rst_desc *desc;
60
+
};
61
+
62
+
/**
63
+
* mtk_register_reset_controller - Register MediaTek clock reset controller
64
+
* @np: Pointer to device node.
65
+
* @desc: Constant pointer to description of clock reset.
66
+
*
67
+
* Return: 0 on success and errorno otherwise.
68
+
*/
69
+
int mtk_register_reset_controller(struct device_node *np,
70
+
const struct mtk_clk_rst_desc *desc);
71
+
72
+
/**
73
+
* mtk_register_reset_controller - Register mediatek clock reset controller with device
74
+
* @np: Pointer to device.
75
+
* @desc: Constant pointer to description of clock reset.
76
+
*
77
+
* Return: 0 on success and errorno otherwise.
78
+
*/
79
+
int mtk_register_reset_controller_with_dev(struct device *dev,
80
+
const struct mtk_clk_rst_desc *desc);
81
+
82
+
#endif /* __DRV_CLK_MTK_RESET_H */
+4
-32
drivers/clk/meson/axg-audio.c
+4
-32
drivers/clk/meson/axg-audio.c
···
1657
1657
&sm1_sysclk_b_en,
1658
1658
};
1659
1659
1660
-
static int devm_clk_get_enable(struct device *dev, char *id)
1661
-
{
1662
-
struct clk *clk;
1663
-
int ret;
1664
-
1665
-
clk = devm_clk_get(dev, id);
1666
-
if (IS_ERR(clk)) {
1667
-
ret = PTR_ERR(clk);
1668
-
dev_err_probe(dev, ret, "failed to get %s", id);
1669
-
return ret;
1670
-
}
1671
-
1672
-
ret = clk_prepare_enable(clk);
1673
-
if (ret) {
1674
-
dev_err(dev, "failed to enable %s", id);
1675
-
return ret;
1676
-
}
1677
-
1678
-
ret = devm_add_action_or_reset(dev,
1679
-
(void(*)(void *))clk_disable_unprepare,
1680
-
clk);
1681
-
if (ret) {
1682
-
dev_err(dev, "failed to add reset action on %s", id);
1683
-
return ret;
1684
-
}
1685
-
1686
-
return 0;
1687
-
}
1688
-
1689
1660
struct axg_audio_reset_data {
1690
1661
struct reset_controller_dev rstc;
1691
1662
struct regmap *map;
···
1758
1787
struct regmap *map;
1759
1788
void __iomem *regs;
1760
1789
struct clk_hw *hw;
1790
+
struct clk *clk;
1761
1791
int ret, i;
1762
1792
1763
1793
data = of_device_get_match_data(dev);
···
1776
1804
}
1777
1805
1778
1806
/* Get the mandatory peripheral clock */
1779
-
ret = devm_clk_get_enable(dev, "pclk");
1780
-
if (ret)
1781
-
return ret;
1807
+
clk = devm_clk_get_enabled(dev, "pclk");
1808
+
if (IS_ERR(clk))
1809
+
return PTR_ERR(clk);
1782
1810
1783
1811
ret = device_reset(dev);
1784
1812
if (ret) {
+19
-3
drivers/clk/qcom/Kconfig
+19
-3
drivers/clk/qcom/Kconfig
···
166
166
167
167
config IPQ_GCC_8074
168
168
tristate "IPQ8074 Global Clock Controller"
169
+
select QCOM_GDSC
169
170
help
170
171
Support for global clock controller on ipq8074 devices.
171
172
Say Y if you want to use peripheral devices such as UART, SPI,
···
609
608
Support for the camera clock controller on SM8250 devices.
610
609
Say Y if you want to support camera devices and camera functionality.
611
610
611
+
config SM_CAMCC_8450
612
+
tristate "SM8450 Camera Clock Controller"
613
+
select SM_GCC_8450
614
+
help
615
+
Support for the camera clock controller on SM8450 devices.
616
+
Say Y if you want to support camera devices and camera functionality.
617
+
612
618
config SM_DISPCC_6125
613
619
tristate "SM6125 Display Clock Controller"
614
620
depends on SM_GCC_6125
···
626
618
splash screen
627
619
628
620
config SM_DISPCC_8250
629
-
tristate "SM8150 and SM8250 Display Clock Controller"
630
-
depends on SM_GCC_8150 || SM_GCC_8250
621
+
tristate "SM8150/SM8250/SM8350 Display Clock Controller"
622
+
depends on SM_GCC_8150 || SM_GCC_8250 || SM_GCC_8350
631
623
help
632
624
Support for the display clock controller on Qualcomm Technologies, Inc
633
-
SM8150 and SM8250 devices.
625
+
SM8150/SM8250/SM8350 devices.
634
626
Say Y if you want to support display devices and functionality such as
635
627
splash screen.
636
628
···
717
709
select SM_GCC_8250
718
710
help
719
711
Support for the graphics clock controller on SM8250 devices.
712
+
Say Y if you want to support graphics controller devices and
713
+
functionality such as 3D graphics.
714
+
715
+
config SM_GPUCC_8350
716
+
tristate "SM8350 Graphics Clock Controller"
717
+
select SM_GCC_8350
718
+
help
719
+
Support for the graphics clock controller on SM8350 devices.
720
720
Say Y if you want to support graphics controller devices and
721
721
functionality such as 3D graphics.
722
722
+3
drivers/clk/qcom/Makefile
+3
drivers/clk/qcom/Makefile
···
11
11
clk-qcom-y += clk-regmap-divider.o
12
12
clk-qcom-y += clk-regmap-mux.o
13
13
clk-qcom-y += clk-regmap-mux-div.o
14
+
clk-qcom-y += clk-regmap-phy-mux.o
14
15
clk-qcom-$(CONFIG_KRAIT_CLOCKS) += clk-krait.o
15
16
clk-qcom-y += clk-hfpll.o
16
17
clk-qcom-y += reset.o
···
89
88
obj-$(CONFIG_SDX_GCC_55) += gcc-sdx55.o
90
89
obj-$(CONFIG_SDX_GCC_65) += gcc-sdx65.o
91
90
obj-$(CONFIG_SM_CAMCC_8250) += camcc-sm8250.o
91
+
obj-$(CONFIG_SM_CAMCC_8450) += camcc-sm8450.o
92
92
obj-$(CONFIG_SM_DISPCC_6125) += dispcc-sm6125.o
93
93
obj-$(CONFIG_SM_DISPCC_6350) += dispcc-sm6350.o
94
94
obj-$(CONFIG_SM_DISPCC_8250) += dispcc-sm8250.o
···
103
101
obj-$(CONFIG_SM_GPUCC_6350) += gpucc-sm6350.o
104
102
obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o
105
103
obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o
104
+
obj-$(CONFIG_SM_GPUCC_8350) += gpucc-sm8350.o
106
105
obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o
107
106
obj-$(CONFIG_SM_VIDEOCC_8250) += videocc-sm8250.o
108
107
obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
+4
drivers/clk/qcom/camcc-sdm845.c
+4
drivers/clk/qcom/camcc-sdm845.c
···
1534
1534
},
1535
1535
};
1536
1536
1537
+
static struct gdsc titan_top_gdsc;
1538
+
1537
1539
static struct gdsc bps_gdsc = {
1538
1540
.gdscr = 0x6004,
1539
1541
.pd = {
···
1569
1567
.name = "ife_0_gdsc",
1570
1568
},
1571
1569
.flags = POLL_CFG_GDSCR,
1570
+
.parent = &titan_top_gdsc.pd,
1572
1571
.pwrsts = PWRSTS_OFF_ON,
1573
1572
};
1574
1573
···
1579
1576
.name = "ife_1_gdsc",
1580
1577
},
1581
1578
.flags = POLL_CFG_GDSCR,
1579
+
.parent = &titan_top_gdsc.pd,
1582
1580
.pwrsts = PWRSTS_OFF_ON,
1583
1581
};
1584
1582
+5
-11
drivers/clk/qcom/camcc-sm8250.c
+5
-11
drivers/clk/qcom/camcc-sm8250.c
···
2205
2205
},
2206
2206
};
2207
2207
2208
+
static struct gdsc titan_top_gdsc;
2209
+
2208
2210
static struct gdsc bps_gdsc = {
2209
2211
.gdscr = 0x7004,
2210
2212
.pd = {
···
2240
2238
.name = "ife_0_gdsc",
2241
2239
},
2242
2240
.flags = POLL_CFG_GDSCR,
2241
+
.parent = &titan_top_gdsc.pd,
2243
2242
.pwrsts = PWRSTS_OFF_ON,
2244
2243
};
2245
2244
···
2250
2247
.name = "ife_1_gdsc",
2251
2248
},
2252
2249
.flags = POLL_CFG_GDSCR,
2250
+
.parent = &titan_top_gdsc.pd,
2253
2251
.pwrsts = PWRSTS_OFF_ON,
2254
2252
};
2255
2253
···
2444
2440
},
2445
2441
};
2446
2442
2447
-
static int __init cam_cc_sm8250_init(void)
2448
-
{
2449
-
return platform_driver_register(&cam_cc_sm8250_driver);
2450
-
}
2451
-
subsys_initcall(cam_cc_sm8250_init);
2452
-
2453
-
static void __exit cam_cc_sm8250_exit(void)
2454
-
{
2455
-
platform_driver_unregister(&cam_cc_sm8250_driver);
2456
-
}
2457
-
module_exit(cam_cc_sm8250_exit);
2443
+
module_platform_driver(cam_cc_sm8250_driver);
2458
2444
2459
2445
MODULE_DESCRIPTION("QTI CAMCC SM8250 Driver");
2460
2446
MODULE_LICENSE("GPL v2");
+2856
drivers/clk/qcom/camcc-sm8450.c
+2856
drivers/clk/qcom/camcc-sm8450.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
4
+
*/
5
+
6
+
#include <linux/clk-provider.h>
7
+
#include <linux/mod_devicetable.h>
8
+
#include <linux/module.h>
9
+
#include <linux/platform_device.h>
10
+
#include <linux/regmap.h>
11
+
12
+
#include <dt-bindings/clock/qcom,sm8450-camcc.h>
13
+
14
+
#include "clk-alpha-pll.h"
15
+
#include "clk-branch.h"
16
+
#include "clk-pll.h"
17
+
#include "clk-rcg.h"
18
+
#include "clk-regmap-divider.h"
19
+
#include "clk-regmap-mux.h"
20
+
#include "clk-regmap.h"
21
+
#include "common.h"
22
+
#include "gdsc.h"
23
+
#include "reset.h"
24
+
25
+
enum {
26
+
DT_IFACE,
27
+
DT_BI_TCXO,
28
+
DT_BI_TCXO_AO,
29
+
DT_SLEEP_CLK
30
+
};
31
+
32
+
enum {
33
+
P_BI_TCXO,
34
+
P_CAM_CC_PLL0_OUT_EVEN,
35
+
P_CAM_CC_PLL0_OUT_MAIN,
36
+
P_CAM_CC_PLL0_OUT_ODD,
37
+
P_CAM_CC_PLL1_OUT_EVEN,
38
+
P_CAM_CC_PLL2_OUT_EVEN,
39
+
P_CAM_CC_PLL2_OUT_MAIN,
40
+
P_CAM_CC_PLL3_OUT_EVEN,
41
+
P_CAM_CC_PLL4_OUT_EVEN,
42
+
P_CAM_CC_PLL5_OUT_EVEN,
43
+
P_CAM_CC_PLL6_OUT_EVEN,
44
+
P_CAM_CC_PLL7_OUT_EVEN,
45
+
P_CAM_CC_PLL8_OUT_EVEN,
46
+
P_SLEEP_CLK,
47
+
};
48
+
49
+
static const struct pll_vco lucid_evo_vco[] = {
50
+
{ 249600000, 2000000000, 0 },
51
+
};
52
+
53
+
static const struct pll_vco rivian_evo_vco[] = {
54
+
{ 864000000, 1056000000, 0 },
55
+
};
56
+
57
+
static const struct clk_parent_data pll_parent_data_tcxo = { .index = DT_BI_TCXO };
58
+
59
+
static const struct alpha_pll_config cam_cc_pll0_config = {
60
+
.l = 0x3e,
61
+
.alpha = 0x8000,
62
+
.config_ctl_val = 0x20485699,
63
+
.config_ctl_hi_val = 0x00182261,
64
+
.config_ctl_hi1_val = 0x32aa299c,
65
+
.user_ctl_val = 0x00008400,
66
+
.user_ctl_hi_val = 0x00000805,
67
+
};
68
+
69
+
static struct clk_alpha_pll cam_cc_pll0 = {
70
+
.offset = 0x0,
71
+
.vco_table = lucid_evo_vco,
72
+
.num_vco = ARRAY_SIZE(lucid_evo_vco),
73
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
74
+
.clkr = {
75
+
.hw.init = &(const struct clk_init_data) {
76
+
.name = "cam_cc_pll0",
77
+
.parent_data = &pll_parent_data_tcxo,
78
+
.num_parents = 1,
79
+
.ops = &clk_alpha_pll_lucid_evo_ops,
80
+
},
81
+
},
82
+
};
83
+
84
+
static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = {
85
+
{ 0x1, 2 },
86
+
{ }
87
+
};
88
+
89
+
static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = {
90
+
.offset = 0x0,
91
+
.post_div_shift = 10,
92
+
.post_div_table = post_div_table_cam_cc_pll0_out_even,
93
+
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even),
94
+
.width = 4,
95
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
96
+
.clkr.hw.init = &(const struct clk_init_data) {
97
+
.name = "cam_cc_pll0_out_even",
98
+
.parent_data = &(const struct clk_parent_data) {
99
+
.hw = &cam_cc_pll0.clkr.hw,
100
+
},
101
+
.num_parents = 1,
102
+
.flags = CLK_SET_RATE_PARENT,
103
+
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
104
+
},
105
+
};
106
+
107
+
static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = {
108
+
{ 0x2, 3 },
109
+
{ }
110
+
};
111
+
112
+
static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = {
113
+
.offset = 0x0,
114
+
.post_div_shift = 14,
115
+
.post_div_table = post_div_table_cam_cc_pll0_out_odd,
116
+
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd),
117
+
.width = 4,
118
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
119
+
.clkr.hw.init = &(const struct clk_init_data) {
120
+
.name = "cam_cc_pll0_out_odd",
121
+
.parent_data = &(const struct clk_parent_data) {
122
+
.hw = &cam_cc_pll0.clkr.hw,
123
+
},
124
+
.num_parents = 1,
125
+
.flags = CLK_SET_RATE_PARENT,
126
+
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
127
+
},
128
+
};
129
+
130
+
static const struct alpha_pll_config cam_cc_pll1_config = {
131
+
.l = 0x25,
132
+
.alpha = 0xeaaa,
133
+
.config_ctl_val = 0x20485699,
134
+
.config_ctl_hi_val = 0x00182261,
135
+
.config_ctl_hi1_val = 0x32aa299c,
136
+
.user_ctl_val = 0x00000400,
137
+
.user_ctl_hi_val = 0x00000805,
138
+
};
139
+
140
+
static struct clk_alpha_pll cam_cc_pll1 = {
141
+
.offset = 0x1000,
142
+
.vco_table = lucid_evo_vco,
143
+
.num_vco = ARRAY_SIZE(lucid_evo_vco),
144
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
145
+
.clkr = {
146
+
.hw.init = &(const struct clk_init_data) {
147
+
.name = "cam_cc_pll1",
148
+
.parent_data = &pll_parent_data_tcxo,
149
+
.num_parents = 1,
150
+
.ops = &clk_alpha_pll_lucid_evo_ops,
151
+
},
152
+
},
153
+
};
154
+
155
+
static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = {
156
+
{ 0x1, 2 },
157
+
{ }
158
+
};
159
+
160
+
static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = {
161
+
.offset = 0x1000,
162
+
.post_div_shift = 10,
163
+
.post_div_table = post_div_table_cam_cc_pll1_out_even,
164
+
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll1_out_even),
165
+
.width = 4,
166
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
167
+
.clkr.hw.init = &(const struct clk_init_data) {
168
+
.name = "cam_cc_pll1_out_even",
169
+
.parent_data = &(const struct clk_parent_data) {
170
+
.hw = &cam_cc_pll1.clkr.hw,
171
+
},
172
+
.num_parents = 1,
173
+
.flags = CLK_SET_RATE_PARENT,
174
+
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
175
+
},
176
+
};
177
+
178
+
static const struct alpha_pll_config cam_cc_pll2_config = {
179
+
.l = 0x32,
180
+
.alpha = 0x0,
181
+
.config_ctl_val = 0x90008820,
182
+
.config_ctl_hi_val = 0x00890263,
183
+
.config_ctl_hi1_val = 0x00000217,
184
+
};
185
+
186
+
static struct clk_alpha_pll cam_cc_pll2 = {
187
+
.offset = 0x2000,
188
+
.vco_table = rivian_evo_vco,
189
+
.num_vco = ARRAY_SIZE(rivian_evo_vco),
190
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO],
191
+
.clkr = {
192
+
.hw.init = &(const struct clk_init_data) {
193
+
.name = "cam_cc_pll2",
194
+
.parent_data = &pll_parent_data_tcxo,
195
+
.num_parents = 1,
196
+
.ops = &clk_alpha_pll_rivian_evo_ops,
197
+
},
198
+
},
199
+
};
200
+
201
+
static const struct alpha_pll_config cam_cc_pll3_config = {
202
+
.l = 0x2d,
203
+
.alpha = 0x0,
204
+
.config_ctl_val = 0x20485699,
205
+
.config_ctl_hi_val = 0x00182261,
206
+
.config_ctl_hi1_val = 0x32aa299c,
207
+
.user_ctl_val = 0x00000400,
208
+
.user_ctl_hi_val = 0x00000805,
209
+
};
210
+
211
+
static struct clk_alpha_pll cam_cc_pll3 = {
212
+
.offset = 0x3000,
213
+
.vco_table = lucid_evo_vco,
214
+
.num_vco = ARRAY_SIZE(lucid_evo_vco),
215
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
216
+
.clkr = {
217
+
.hw.init = &(const struct clk_init_data) {
218
+
.name = "cam_cc_pll3",
219
+
.parent_data = &pll_parent_data_tcxo,
220
+
.num_parents = 1,
221
+
.ops = &clk_alpha_pll_lucid_evo_ops,
222
+
},
223
+
},
224
+
};
225
+
226
+
static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = {
227
+
{ 0x1, 2 },
228
+
{ }
229
+
};
230
+
231
+
static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = {
232
+
.offset = 0x3000,
233
+
.post_div_shift = 10,
234
+
.post_div_table = post_div_table_cam_cc_pll3_out_even,
235
+
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even),
236
+
.width = 4,
237
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
238
+
.clkr.hw.init = &(const struct clk_init_data) {
239
+
.name = "cam_cc_pll3_out_even",
240
+
.parent_data = &(const struct clk_parent_data) {
241
+
.hw = &cam_cc_pll3.clkr.hw,
242
+
},
243
+
.num_parents = 1,
244
+
.flags = CLK_SET_RATE_PARENT,
245
+
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
246
+
},
247
+
};
248
+
249
+
static const struct alpha_pll_config cam_cc_pll4_config = {
250
+
.l = 0x2d,
251
+
.alpha = 0x0,
252
+
.config_ctl_val = 0x20485699,
253
+
.config_ctl_hi_val = 0x00182261,
254
+
.config_ctl_hi1_val = 0x32aa299c,
255
+
.user_ctl_val = 0x00000400,
256
+
.user_ctl_hi_val = 0x00000805,
257
+
};
258
+
259
+
static struct clk_alpha_pll cam_cc_pll4 = {
260
+
.offset = 0x4000,
261
+
.vco_table = lucid_evo_vco,
262
+
.num_vco = ARRAY_SIZE(lucid_evo_vco),
263
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
264
+
.clkr = {
265
+
.hw.init = &(const struct clk_init_data) {
266
+
.name = "cam_cc_pll4",
267
+
.parent_data = &pll_parent_data_tcxo,
268
+
.num_parents = 1,
269
+
.ops = &clk_alpha_pll_lucid_evo_ops,
270
+
},
271
+
},
272
+
};
273
+
274
+
static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = {
275
+
{ 0x1, 2 },
276
+
{ }
277
+
};
278
+
279
+
static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = {
280
+
.offset = 0x4000,
281
+
.post_div_shift = 10,
282
+
.post_div_table = post_div_table_cam_cc_pll4_out_even,
283
+
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even),
284
+
.width = 4,
285
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
286
+
.clkr.hw.init = &(const struct clk_init_data) {
287
+
.name = "cam_cc_pll4_out_even",
288
+
.parent_data = &(const struct clk_parent_data) {
289
+
.hw = &cam_cc_pll4.clkr.hw,
290
+
},
291
+
.num_parents = 1,
292
+
.flags = CLK_SET_RATE_PARENT,
293
+
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
294
+
},
295
+
};
296
+
297
+
static const struct alpha_pll_config cam_cc_pll5_config = {
298
+
.l = 0x2d,
299
+
.alpha = 0x0,
300
+
.config_ctl_val = 0x20485699,
301
+
.config_ctl_hi_val = 0x00182261,
302
+
.config_ctl_hi1_val = 0x32aa299c,
303
+
.user_ctl_val = 0x00000400,
304
+
.user_ctl_hi_val = 0x00000805,
305
+
};
306
+
307
+
static struct clk_alpha_pll cam_cc_pll5 = {
308
+
.offset = 0x5000,
309
+
.vco_table = lucid_evo_vco,
310
+
.num_vco = ARRAY_SIZE(lucid_evo_vco),
311
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
312
+
.clkr = {
313
+
.hw.init = &(const struct clk_init_data) {
314
+
.name = "cam_cc_pll5",
315
+
.parent_data = &pll_parent_data_tcxo,
316
+
.num_parents = 1,
317
+
.ops = &clk_alpha_pll_lucid_evo_ops,
318
+
},
319
+
},
320
+
};
321
+
322
+
static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = {
323
+
{ 0x1, 2 },
324
+
{ }
325
+
};
326
+
327
+
static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = {
328
+
.offset = 0x5000,
329
+
.post_div_shift = 10,
330
+
.post_div_table = post_div_table_cam_cc_pll5_out_even,
331
+
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll5_out_even),
332
+
.width = 4,
333
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
334
+
.clkr.hw.init = &(const struct clk_init_data) {
335
+
.name = "cam_cc_pll5_out_even",
336
+
.parent_data = &(const struct clk_parent_data) {
337
+
.hw = &cam_cc_pll5.clkr.hw,
338
+
},
339
+
.num_parents = 1,
340
+
.flags = CLK_SET_RATE_PARENT,
341
+
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
342
+
},
343
+
};
344
+
345
+
static const struct alpha_pll_config cam_cc_pll6_config = {
346
+
.l = 0x2d,
347
+
.alpha = 0x0,
348
+
.config_ctl_val = 0x20485699,
349
+
.config_ctl_hi_val = 0x00182261,
350
+
.config_ctl_hi1_val = 0x32aa299c,
351
+
.user_ctl_val = 0x00000400,
352
+
.user_ctl_hi_val = 0x00000805,
353
+
};
354
+
355
+
static struct clk_alpha_pll cam_cc_pll6 = {
356
+
.offset = 0x6000,
357
+
.vco_table = lucid_evo_vco,
358
+
.num_vco = ARRAY_SIZE(lucid_evo_vco),
359
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
360
+
.clkr = {
361
+
.hw.init = &(const struct clk_init_data) {
362
+
.name = "cam_cc_pll6",
363
+
.parent_data = &pll_parent_data_tcxo,
364
+
.num_parents = 1,
365
+
.ops = &clk_alpha_pll_lucid_evo_ops,
366
+
},
367
+
},
368
+
};
369
+
370
+
static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = {
371
+
{ 0x1, 2 },
372
+
{ }
373
+
};
374
+
375
+
static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = {
376
+
.offset = 0x6000,
377
+
.post_div_shift = 10,
378
+
.post_div_table = post_div_table_cam_cc_pll6_out_even,
379
+
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll6_out_even),
380
+
.width = 4,
381
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
382
+
.clkr.hw.init = &(const struct clk_init_data) {
383
+
.name = "cam_cc_pll6_out_even",
384
+
.parent_data = &(const struct clk_parent_data) {
385
+
.hw = &cam_cc_pll6.clkr.hw,
386
+
},
387
+
.num_parents = 1,
388
+
.flags = CLK_SET_RATE_PARENT,
389
+
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
390
+
},
391
+
};
392
+
393
+
static const struct alpha_pll_config cam_cc_pll7_config = {
394
+
.l = 0x2d,
395
+
.alpha = 0x0,
396
+
.config_ctl_val = 0x20485699,
397
+
.config_ctl_hi_val = 0x00182261,
398
+
.config_ctl_hi1_val = 0x32aa299c,
399
+
.user_ctl_val = 0x00000400,
400
+
.user_ctl_hi_val = 0x00000805,
401
+
};
402
+
403
+
static struct clk_alpha_pll cam_cc_pll7 = {
404
+
.offset = 0x7000,
405
+
.vco_table = lucid_evo_vco,
406
+
.num_vco = ARRAY_SIZE(lucid_evo_vco),
407
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
408
+
.clkr = {
409
+
.hw.init = &(const struct clk_init_data) {
410
+
.name = "cam_cc_pll7",
411
+
.parent_data = &pll_parent_data_tcxo,
412
+
.num_parents = 1,
413
+
.ops = &clk_alpha_pll_lucid_evo_ops,
414
+
},
415
+
},
416
+
};
417
+
418
+
static const struct clk_div_table post_div_table_cam_cc_pll7_out_even[] = {
419
+
{ 0x1, 2 },
420
+
{ }
421
+
};
422
+
423
+
static struct clk_alpha_pll_postdiv cam_cc_pll7_out_even = {
424
+
.offset = 0x7000,
425
+
.post_div_shift = 10,
426
+
.post_div_table = post_div_table_cam_cc_pll7_out_even,
427
+
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll7_out_even),
428
+
.width = 4,
429
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
430
+
.clkr.hw.init = &(const struct clk_init_data) {
431
+
.name = "cam_cc_pll7_out_even",
432
+
.parent_data = &(const struct clk_parent_data) {
433
+
.hw = &cam_cc_pll7.clkr.hw,
434
+
},
435
+
.num_parents = 1,
436
+
.flags = CLK_SET_RATE_PARENT,
437
+
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
438
+
},
439
+
};
440
+
441
+
static const struct alpha_pll_config cam_cc_pll8_config = {
442
+
.l = 0x32,
443
+
.alpha = 0x0,
444
+
.config_ctl_val = 0x20485699,
445
+
.config_ctl_hi_val = 0x00182261,
446
+
.config_ctl_hi1_val = 0x32aa299c,
447
+
.user_ctl_val = 0x00000400,
448
+
.user_ctl_hi_val = 0x00000805,
449
+
};
450
+
451
+
static struct clk_alpha_pll cam_cc_pll8 = {
452
+
.offset = 0x8000,
453
+
.vco_table = lucid_evo_vco,
454
+
.num_vco = ARRAY_SIZE(lucid_evo_vco),
455
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
456
+
.clkr = {
457
+
.hw.init = &(const struct clk_init_data) {
458
+
.name = "cam_cc_pll8",
459
+
.parent_data = &pll_parent_data_tcxo,
460
+
.num_parents = 1,
461
+
.ops = &clk_alpha_pll_lucid_evo_ops,
462
+
},
463
+
},
464
+
};
465
+
466
+
static const struct clk_div_table post_div_table_cam_cc_pll8_out_even[] = {
467
+
{ 0x1, 2 },
468
+
{ }
469
+
};
470
+
471
+
static struct clk_alpha_pll_postdiv cam_cc_pll8_out_even = {
472
+
.offset = 0x8000,
473
+
.post_div_shift = 10,
474
+
.post_div_table = post_div_table_cam_cc_pll8_out_even,
475
+
.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll8_out_even),
476
+
.width = 4,
477
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
478
+
.clkr.hw.init = &(const struct clk_init_data) {
479
+
.name = "cam_cc_pll8_out_even",
480
+
.parent_data = &(const struct clk_parent_data) {
481
+
.hw = &cam_cc_pll8.clkr.hw,
482
+
},
483
+
.num_parents = 1,
484
+
.flags = CLK_SET_RATE_PARENT,
485
+
.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
486
+
},
487
+
};
488
+
489
+
static const struct parent_map cam_cc_parent_map_0[] = {
490
+
{ P_BI_TCXO, 0 },
491
+
{ P_CAM_CC_PLL0_OUT_MAIN, 1 },
492
+
{ P_CAM_CC_PLL0_OUT_EVEN, 2 },
493
+
{ P_CAM_CC_PLL0_OUT_ODD, 3 },
494
+
{ P_CAM_CC_PLL8_OUT_EVEN, 5 },
495
+
};
496
+
497
+
static const struct clk_parent_data cam_cc_parent_data_0[] = {
498
+
{ .index = DT_BI_TCXO },
499
+
{ .hw = &cam_cc_pll0.clkr.hw },
500
+
{ .hw = &cam_cc_pll0_out_even.clkr.hw },
501
+
{ .hw = &cam_cc_pll0_out_odd.clkr.hw },
502
+
{ .hw = &cam_cc_pll8_out_even.clkr.hw },
503
+
};
504
+
505
+
static const struct parent_map cam_cc_parent_map_1[] = {
506
+
{ P_BI_TCXO, 0 },
507
+
{ P_CAM_CC_PLL2_OUT_EVEN, 3 },
508
+
{ P_CAM_CC_PLL2_OUT_MAIN, 5 },
509
+
};
510
+
511
+
static const struct clk_parent_data cam_cc_parent_data_1[] = {
512
+
{ .index = DT_BI_TCXO },
513
+
{ .hw = &cam_cc_pll2.clkr.hw },
514
+
{ .hw = &cam_cc_pll2.clkr.hw },
515
+
};
516
+
517
+
static const struct parent_map cam_cc_parent_map_2[] = {
518
+
{ P_BI_TCXO, 0 },
519
+
{ P_CAM_CC_PLL3_OUT_EVEN, 6 },
520
+
};
521
+
522
+
static const struct clk_parent_data cam_cc_parent_data_2[] = {
523
+
{ .index = DT_BI_TCXO },
524
+
{ .hw = &cam_cc_pll3_out_even.clkr.hw },
525
+
};
526
+
527
+
static const struct parent_map cam_cc_parent_map_3[] = {
528
+
{ P_BI_TCXO, 0 },
529
+
{ P_CAM_CC_PLL4_OUT_EVEN, 6 },
530
+
};
531
+
532
+
static const struct clk_parent_data cam_cc_parent_data_3[] = {
533
+
{ .index = DT_BI_TCXO },
534
+
{ .hw = &cam_cc_pll4_out_even.clkr.hw },
535
+
};
536
+
537
+
static const struct parent_map cam_cc_parent_map_4[] = {
538
+
{ P_BI_TCXO, 0 },
539
+
{ P_CAM_CC_PLL5_OUT_EVEN, 6 },
540
+
};
541
+
542
+
static const struct clk_parent_data cam_cc_parent_data_4[] = {
543
+
{ .index = DT_BI_TCXO },
544
+
{ .hw = &cam_cc_pll5_out_even.clkr.hw },
545
+
};
546
+
547
+
static const struct parent_map cam_cc_parent_map_5[] = {
548
+
{ P_BI_TCXO, 0 },
549
+
{ P_CAM_CC_PLL1_OUT_EVEN, 4 },
550
+
};
551
+
552
+
static const struct clk_parent_data cam_cc_parent_data_5[] = {
553
+
{ .index = DT_BI_TCXO },
554
+
{ .hw = &cam_cc_pll1_out_even.clkr.hw },
555
+
};
556
+
557
+
static const struct parent_map cam_cc_parent_map_6[] = {
558
+
{ P_BI_TCXO, 0 },
559
+
{ P_CAM_CC_PLL6_OUT_EVEN, 6 },
560
+
};
561
+
562
+
static const struct clk_parent_data cam_cc_parent_data_6[] = {
563
+
{ .index = DT_BI_TCXO },
564
+
{ .hw = &cam_cc_pll6_out_even.clkr.hw },
565
+
};
566
+
567
+
static const struct parent_map cam_cc_parent_map_7[] = {
568
+
{ P_BI_TCXO, 0 },
569
+
{ P_CAM_CC_PLL7_OUT_EVEN, 6 },
570
+
};
571
+
572
+
static const struct clk_parent_data cam_cc_parent_data_7[] = {
573
+
{ .index = DT_BI_TCXO },
574
+
{ .hw = &cam_cc_pll7_out_even.clkr.hw },
575
+
};
576
+
577
+
static const struct parent_map cam_cc_parent_map_8[] = {
578
+
{ P_SLEEP_CLK, 0 },
579
+
};
580
+
581
+
static const struct clk_parent_data cam_cc_parent_data_8[] = {
582
+
{ .index = DT_SLEEP_CLK },
583
+
};
584
+
585
+
static const struct parent_map cam_cc_parent_map_9[] = {
586
+
{ P_BI_TCXO, 0 },
587
+
};
588
+
589
+
static const struct clk_parent_data cam_cc_parent_data_9_ao[] = {
590
+
{ .index = DT_BI_TCXO_AO, .name = "bi_tcxo_ao" },
591
+
};
592
+
593
+
static const struct freq_tbl ftbl_cam_cc_bps_clk_src[] = {
594
+
F(19200000, P_BI_TCXO, 1, 0, 0),
595
+
F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0),
596
+
F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
597
+
F(480000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
598
+
F(600000000, P_CAM_CC_PLL0_OUT_EVEN, 1, 0, 0),
599
+
{ }
600
+
};
601
+
602
+
static struct clk_rcg2 cam_cc_bps_clk_src = {
603
+
.cmd_rcgr = 0x10050,
604
+
.mnd_width = 0,
605
+
.hid_width = 5,
606
+
.parent_map = cam_cc_parent_map_0,
607
+
.freq_tbl = ftbl_cam_cc_bps_clk_src,
608
+
.clkr.hw.init = &(const struct clk_init_data) {
609
+
.name = "cam_cc_bps_clk_src",
610
+
.parent_data = cam_cc_parent_data_0,
611
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
612
+
.flags = CLK_SET_RATE_PARENT,
613
+
.ops = &clk_rcg2_ops,
614
+
},
615
+
};
616
+
617
+
static const struct freq_tbl ftbl_cam_cc_camnoc_axi_clk_src[] = {
618
+
F(19200000, P_BI_TCXO, 1, 0, 0),
619
+
F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0),
620
+
F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
621
+
{ }
622
+
};
623
+
624
+
static struct clk_rcg2 cam_cc_camnoc_axi_clk_src = {
625
+
.cmd_rcgr = 0x13194,
626
+
.mnd_width = 0,
627
+
.hid_width = 5,
628
+
.parent_map = cam_cc_parent_map_0,
629
+
.freq_tbl = ftbl_cam_cc_camnoc_axi_clk_src,
630
+
.clkr.hw.init = &(const struct clk_init_data) {
631
+
.name = "cam_cc_camnoc_axi_clk_src",
632
+
.parent_data = cam_cc_parent_data_0,
633
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
634
+
.flags = CLK_SET_RATE_PARENT,
635
+
.ops = &clk_rcg2_ops,
636
+
},
637
+
};
638
+
639
+
static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = {
640
+
F(19200000, P_BI_TCXO, 1, 0, 0),
641
+
F(37500000, P_CAM_CC_PLL0_OUT_EVEN, 16, 0, 0),
642
+
{ }
643
+
};
644
+
645
+
static struct clk_rcg2 cam_cc_cci_0_clk_src = {
646
+
.cmd_rcgr = 0x1312c,
647
+
.mnd_width = 8,
648
+
.hid_width = 5,
649
+
.parent_map = cam_cc_parent_map_0,
650
+
.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
651
+
.clkr.hw.init = &(const struct clk_init_data) {
652
+
.name = "cam_cc_cci_0_clk_src",
653
+
.parent_data = cam_cc_parent_data_0,
654
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
655
+
.flags = CLK_SET_RATE_PARENT,
656
+
.ops = &clk_rcg2_ops,
657
+
},
658
+
};
659
+
660
+
static struct clk_rcg2 cam_cc_cci_1_clk_src = {
661
+
.cmd_rcgr = 0x13148,
662
+
.mnd_width = 8,
663
+
.hid_width = 5,
664
+
.parent_map = cam_cc_parent_map_0,
665
+
.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
666
+
.clkr.hw.init = &(const struct clk_init_data) {
667
+
.name = "cam_cc_cci_1_clk_src",
668
+
.parent_data = cam_cc_parent_data_0,
669
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
670
+
.flags = CLK_SET_RATE_PARENT,
671
+
.ops = &clk_rcg2_ops,
672
+
},
673
+
};
674
+
675
+
static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = {
676
+
F(19200000, P_BI_TCXO, 1, 0, 0),
677
+
F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
678
+
F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
679
+
{ }
680
+
};
681
+
682
+
static struct clk_rcg2 cam_cc_cphy_rx_clk_src = {
683
+
.cmd_rcgr = 0x1104c,
684
+
.mnd_width = 0,
685
+
.hid_width = 5,
686
+
.parent_map = cam_cc_parent_map_0,
687
+
.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
688
+
.clkr.hw.init = &(const struct clk_init_data) {
689
+
.name = "cam_cc_cphy_rx_clk_src",
690
+
.parent_data = cam_cc_parent_data_0,
691
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
692
+
.flags = CLK_SET_RATE_PARENT,
693
+
.ops = &clk_rcg2_ops,
694
+
},
695
+
};
696
+
697
+
static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = {
698
+
F(19200000, P_BI_TCXO, 1, 0, 0),
699
+
F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
700
+
{ }
701
+
};
702
+
703
+
static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = {
704
+
.cmd_rcgr = 0x150e0,
705
+
.mnd_width = 0,
706
+
.hid_width = 5,
707
+
.parent_map = cam_cc_parent_map_0,
708
+
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
709
+
.clkr.hw.init = &(const struct clk_init_data) {
710
+
.name = "cam_cc_csi0phytimer_clk_src",
711
+
.parent_data = cam_cc_parent_data_0,
712
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
713
+
.flags = CLK_SET_RATE_PARENT,
714
+
.ops = &clk_rcg2_ops,
715
+
},
716
+
};
717
+
718
+
static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = {
719
+
.cmd_rcgr = 0x15104,
720
+
.mnd_width = 0,
721
+
.hid_width = 5,
722
+
.parent_map = cam_cc_parent_map_0,
723
+
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
724
+
.clkr.hw.init = &(const struct clk_init_data) {
725
+
.name = "cam_cc_csi1phytimer_clk_src",
726
+
.parent_data = cam_cc_parent_data_0,
727
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
728
+
.flags = CLK_SET_RATE_PARENT,
729
+
.ops = &clk_rcg2_ops,
730
+
},
731
+
};
732
+
733
+
static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = {
734
+
.cmd_rcgr = 0x15124,
735
+
.mnd_width = 0,
736
+
.hid_width = 5,
737
+
.parent_map = cam_cc_parent_map_0,
738
+
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
739
+
.clkr.hw.init = &(const struct clk_init_data) {
740
+
.name = "cam_cc_csi2phytimer_clk_src",
741
+
.parent_data = cam_cc_parent_data_0,
742
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
743
+
.flags = CLK_SET_RATE_PARENT,
744
+
.ops = &clk_rcg2_ops,
745
+
},
746
+
};
747
+
748
+
static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = {
749
+
.cmd_rcgr = 0x1514c,
750
+
.mnd_width = 0,
751
+
.hid_width = 5,
752
+
.parent_map = cam_cc_parent_map_0,
753
+
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
754
+
.clkr.hw.init = &(const struct clk_init_data) {
755
+
.name = "cam_cc_csi3phytimer_clk_src",
756
+
.parent_data = cam_cc_parent_data_0,
757
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
758
+
.flags = CLK_SET_RATE_PARENT,
759
+
.ops = &clk_rcg2_ops,
760
+
},
761
+
};
762
+
763
+
static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = {
764
+
.cmd_rcgr = 0x1516c,
765
+
.mnd_width = 0,
766
+
.hid_width = 5,
767
+
.parent_map = cam_cc_parent_map_0,
768
+
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
769
+
.clkr.hw.init = &(const struct clk_init_data) {
770
+
.name = "cam_cc_csi4phytimer_clk_src",
771
+
.parent_data = cam_cc_parent_data_0,
772
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
773
+
.flags = CLK_SET_RATE_PARENT,
774
+
.ops = &clk_rcg2_ops,
775
+
},
776
+
};
777
+
778
+
static struct clk_rcg2 cam_cc_csi5phytimer_clk_src = {
779
+
.cmd_rcgr = 0x1518c,
780
+
.mnd_width = 0,
781
+
.hid_width = 5,
782
+
.parent_map = cam_cc_parent_map_0,
783
+
.freq_tbl = ftbl_cam_cc_csi0phytimer_clk_src,
784
+
.clkr.hw.init = &(const struct clk_init_data) {
785
+
.name = "cam_cc_csi5phytimer_clk_src",
786
+
.parent_data = cam_cc_parent_data_0,
787
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
788
+
.flags = CLK_SET_RATE_PARENT,
789
+
.ops = &clk_rcg2_ops,
790
+
},
791
+
};
792
+
793
+
static const struct freq_tbl ftbl_cam_cc_csid_clk_src[] = {
794
+
F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
795
+
F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
796
+
{ }
797
+
};
798
+
799
+
static struct clk_rcg2 cam_cc_csid_clk_src = {
800
+
.cmd_rcgr = 0x13174,
801
+
.mnd_width = 0,
802
+
.hid_width = 5,
803
+
.parent_map = cam_cc_parent_map_0,
804
+
.freq_tbl = ftbl_cam_cc_csid_clk_src,
805
+
.clkr.hw.init = &(const struct clk_init_data) {
806
+
.name = "cam_cc_csid_clk_src",
807
+
.parent_data = cam_cc_parent_data_0,
808
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
809
+
.flags = CLK_SET_RATE_PARENT,
810
+
.ops = &clk_rcg2_ops,
811
+
},
812
+
};
813
+
814
+
static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = {
815
+
F(19200000, P_BI_TCXO, 1, 0, 0),
816
+
F(100000000, P_CAM_CC_PLL0_OUT_EVEN, 6, 0, 0),
817
+
F(200000000, P_CAM_CC_PLL0_OUT_EVEN, 3, 0, 0),
818
+
F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0),
819
+
F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
820
+
{ }
821
+
};
822
+
823
+
static struct clk_rcg2 cam_cc_fast_ahb_clk_src = {
824
+
.cmd_rcgr = 0x10018,
825
+
.mnd_width = 0,
826
+
.hid_width = 5,
827
+
.parent_map = cam_cc_parent_map_0,
828
+
.freq_tbl = ftbl_cam_cc_fast_ahb_clk_src,
829
+
.clkr.hw.init = &(const struct clk_init_data) {
830
+
.name = "cam_cc_fast_ahb_clk_src",
831
+
.parent_data = cam_cc_parent_data_0,
832
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
833
+
.flags = CLK_SET_RATE_PARENT,
834
+
.ops = &clk_rcg2_ops,
835
+
},
836
+
};
837
+
838
+
static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = {
839
+
F(19200000, P_BI_TCXO, 1, 0, 0),
840
+
F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
841
+
F(480000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
842
+
F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
843
+
{ }
844
+
};
845
+
846
+
static struct clk_rcg2 cam_cc_icp_clk_src = {
847
+
.cmd_rcgr = 0x13108,
848
+
.mnd_width = 0,
849
+
.hid_width = 5,
850
+
.parent_map = cam_cc_parent_map_0,
851
+
.freq_tbl = ftbl_cam_cc_icp_clk_src,
852
+
.clkr.hw.init = &(const struct clk_init_data) {
853
+
.name = "cam_cc_icp_clk_src",
854
+
.parent_data = cam_cc_parent_data_0,
855
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
856
+
.flags = CLK_SET_RATE_PARENT,
857
+
.ops = &clk_rcg2_ops,
858
+
},
859
+
};
860
+
861
+
static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = {
862
+
F(19200000, P_BI_TCXO, 1, 0, 0),
863
+
F(432000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
864
+
F(594000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
865
+
F(675000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
866
+
F(727000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
867
+
{ }
868
+
};
869
+
870
+
static struct clk_rcg2 cam_cc_ife_0_clk_src = {
871
+
.cmd_rcgr = 0x11018,
872
+
.mnd_width = 0,
873
+
.hid_width = 5,
874
+
.parent_map = cam_cc_parent_map_2,
875
+
.freq_tbl = ftbl_cam_cc_ife_0_clk_src,
876
+
.clkr.hw.init = &(const struct clk_init_data) {
877
+
.name = "cam_cc_ife_0_clk_src",
878
+
.parent_data = cam_cc_parent_data_2,
879
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
880
+
.flags = CLK_SET_RATE_PARENT,
881
+
.ops = &clk_rcg2_ops,
882
+
},
883
+
};
884
+
885
+
static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] = {
886
+
F(19200000, P_BI_TCXO, 1, 0, 0),
887
+
F(432000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
888
+
F(594000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
889
+
F(675000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
890
+
F(727000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
891
+
{ }
892
+
};
893
+
894
+
static struct clk_rcg2 cam_cc_ife_1_clk_src = {
895
+
.cmd_rcgr = 0x12018,
896
+
.mnd_width = 0,
897
+
.hid_width = 5,
898
+
.parent_map = cam_cc_parent_map_3,
899
+
.freq_tbl = ftbl_cam_cc_ife_1_clk_src,
900
+
.clkr.hw.init = &(const struct clk_init_data) {
901
+
.name = "cam_cc_ife_1_clk_src",
902
+
.parent_data = cam_cc_parent_data_3,
903
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
904
+
.flags = CLK_SET_RATE_PARENT,
905
+
.ops = &clk_rcg2_ops,
906
+
},
907
+
};
908
+
909
+
static const struct freq_tbl ftbl_cam_cc_ife_2_clk_src[] = {
910
+
F(432000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
911
+
F(594000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
912
+
F(675000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
913
+
F(727000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
914
+
{ }
915
+
};
916
+
917
+
static struct clk_rcg2 cam_cc_ife_2_clk_src = {
918
+
.cmd_rcgr = 0x12064,
919
+
.mnd_width = 0,
920
+
.hid_width = 5,
921
+
.parent_map = cam_cc_parent_map_4,
922
+
.freq_tbl = ftbl_cam_cc_ife_2_clk_src,
923
+
.clkr.hw.init = &(const struct clk_init_data) {
924
+
.name = "cam_cc_ife_2_clk_src",
925
+
.parent_data = cam_cc_parent_data_4,
926
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_4),
927
+
.flags = CLK_SET_RATE_PARENT,
928
+
.ops = &clk_rcg2_ops,
929
+
},
930
+
};
931
+
932
+
static const struct freq_tbl ftbl_cam_cc_ife_lite_clk_src[] = {
933
+
F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
934
+
F(480000000, P_CAM_CC_PLL8_OUT_EVEN, 1, 0, 0),
935
+
{ }
936
+
};
937
+
938
+
static struct clk_rcg2 cam_cc_ife_lite_clk_src = {
939
+
.cmd_rcgr = 0x13000,
940
+
.mnd_width = 0,
941
+
.hid_width = 5,
942
+
.parent_map = cam_cc_parent_map_0,
943
+
.freq_tbl = ftbl_cam_cc_ife_lite_clk_src,
944
+
.clkr.hw.init = &(const struct clk_init_data) {
945
+
.name = "cam_cc_ife_lite_clk_src",
946
+
.parent_data = cam_cc_parent_data_0,
947
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
948
+
.flags = CLK_SET_RATE_PARENT,
949
+
.ops = &clk_rcg2_ops,
950
+
},
951
+
};
952
+
953
+
static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = {
954
+
.cmd_rcgr = 0x13024,
955
+
.mnd_width = 0,
956
+
.hid_width = 5,
957
+
.parent_map = cam_cc_parent_map_0,
958
+
.freq_tbl = ftbl_cam_cc_ife_lite_clk_src,
959
+
.clkr.hw.init = &(const struct clk_init_data) {
960
+
.name = "cam_cc_ife_lite_csid_clk_src",
961
+
.parent_data = cam_cc_parent_data_0,
962
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
963
+
.flags = CLK_SET_RATE_PARENT,
964
+
.ops = &clk_rcg2_ops,
965
+
},
966
+
};
967
+
968
+
static const struct freq_tbl ftbl_cam_cc_ipe_nps_clk_src[] = {
969
+
F(364000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
970
+
F(500000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
971
+
F(600000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
972
+
F(700000000, P_CAM_CC_PLL1_OUT_EVEN, 1, 0, 0),
973
+
{ }
974
+
};
975
+
976
+
static struct clk_rcg2 cam_cc_ipe_nps_clk_src = {
977
+
.cmd_rcgr = 0x1008c,
978
+
.mnd_width = 0,
979
+
.hid_width = 5,
980
+
.parent_map = cam_cc_parent_map_5,
981
+
.freq_tbl = ftbl_cam_cc_ipe_nps_clk_src,
982
+
.clkr.hw.init = &(const struct clk_init_data) {
983
+
.name = "cam_cc_ipe_nps_clk_src",
984
+
.parent_data = cam_cc_parent_data_5,
985
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_5),
986
+
.flags = CLK_SET_RATE_PARENT,
987
+
.ops = &clk_rcg2_ops,
988
+
},
989
+
};
990
+
991
+
static struct clk_rcg2 cam_cc_jpeg_clk_src = {
992
+
.cmd_rcgr = 0x130dc,
993
+
.mnd_width = 0,
994
+
.hid_width = 5,
995
+
.parent_map = cam_cc_parent_map_0,
996
+
.freq_tbl = ftbl_cam_cc_bps_clk_src,
997
+
.clkr.hw.init = &(const struct clk_init_data) {
998
+
.name = "cam_cc_jpeg_clk_src",
999
+
.parent_data = cam_cc_parent_data_0,
1000
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1001
+
.flags = CLK_SET_RATE_PARENT,
1002
+
.ops = &clk_rcg2_ops,
1003
+
},
1004
+
};
1005
+
1006
+
static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = {
1007
+
F(19200000, P_BI_TCXO, 1, 0, 0),
1008
+
F(24000000, P_CAM_CC_PLL2_OUT_MAIN, 10, 1, 4),
1009
+
F(68571429, P_CAM_CC_PLL2_OUT_MAIN, 14, 0, 0),
1010
+
{ }
1011
+
};
1012
+
1013
+
static struct clk_rcg2 cam_cc_mclk0_clk_src = {
1014
+
.cmd_rcgr = 0x15000,
1015
+
.mnd_width = 8,
1016
+
.hid_width = 5,
1017
+
.parent_map = cam_cc_parent_map_1,
1018
+
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1019
+
.clkr.hw.init = &(const struct clk_init_data) {
1020
+
.name = "cam_cc_mclk0_clk_src",
1021
+
.parent_data = cam_cc_parent_data_1,
1022
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1023
+
.flags = CLK_SET_RATE_PARENT,
1024
+
.ops = &clk_rcg2_ops,
1025
+
},
1026
+
};
1027
+
1028
+
static struct clk_rcg2 cam_cc_mclk1_clk_src = {
1029
+
.cmd_rcgr = 0x1501c,
1030
+
.mnd_width = 8,
1031
+
.hid_width = 5,
1032
+
.parent_map = cam_cc_parent_map_1,
1033
+
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1034
+
.clkr.hw.init = &(const struct clk_init_data) {
1035
+
.name = "cam_cc_mclk1_clk_src",
1036
+
.parent_data = cam_cc_parent_data_1,
1037
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1038
+
.flags = CLK_SET_RATE_PARENT,
1039
+
.ops = &clk_rcg2_ops,
1040
+
},
1041
+
};
1042
+
1043
+
static struct clk_rcg2 cam_cc_mclk2_clk_src = {
1044
+
.cmd_rcgr = 0x15038,
1045
+
.mnd_width = 8,
1046
+
.hid_width = 5,
1047
+
.parent_map = cam_cc_parent_map_1,
1048
+
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1049
+
.clkr.hw.init = &(const struct clk_init_data) {
1050
+
.name = "cam_cc_mclk2_clk_src",
1051
+
.parent_data = cam_cc_parent_data_1,
1052
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1053
+
.flags = CLK_SET_RATE_PARENT,
1054
+
.ops = &clk_rcg2_ops,
1055
+
},
1056
+
};
1057
+
1058
+
static struct clk_rcg2 cam_cc_mclk3_clk_src = {
1059
+
.cmd_rcgr = 0x15054,
1060
+
.mnd_width = 8,
1061
+
.hid_width = 5,
1062
+
.parent_map = cam_cc_parent_map_1,
1063
+
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1064
+
.clkr.hw.init = &(const struct clk_init_data) {
1065
+
.name = "cam_cc_mclk3_clk_src",
1066
+
.parent_data = cam_cc_parent_data_1,
1067
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1068
+
.flags = CLK_SET_RATE_PARENT,
1069
+
.ops = &clk_rcg2_ops,
1070
+
},
1071
+
};
1072
+
1073
+
static struct clk_rcg2 cam_cc_mclk4_clk_src = {
1074
+
.cmd_rcgr = 0x15070,
1075
+
.mnd_width = 8,
1076
+
.hid_width = 5,
1077
+
.parent_map = cam_cc_parent_map_1,
1078
+
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1079
+
.clkr.hw.init = &(const struct clk_init_data) {
1080
+
.name = "cam_cc_mclk4_clk_src",
1081
+
.parent_data = cam_cc_parent_data_1,
1082
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1083
+
.flags = CLK_SET_RATE_PARENT,
1084
+
.ops = &clk_rcg2_ops,
1085
+
},
1086
+
};
1087
+
1088
+
static struct clk_rcg2 cam_cc_mclk5_clk_src = {
1089
+
.cmd_rcgr = 0x1508c,
1090
+
.mnd_width = 8,
1091
+
.hid_width = 5,
1092
+
.parent_map = cam_cc_parent_map_1,
1093
+
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1094
+
.clkr.hw.init = &(const struct clk_init_data) {
1095
+
.name = "cam_cc_mclk5_clk_src",
1096
+
.parent_data = cam_cc_parent_data_1,
1097
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1098
+
.flags = CLK_SET_RATE_PARENT,
1099
+
.ops = &clk_rcg2_ops,
1100
+
},
1101
+
};
1102
+
1103
+
static struct clk_rcg2 cam_cc_mclk6_clk_src = {
1104
+
.cmd_rcgr = 0x150a8,
1105
+
.mnd_width = 8,
1106
+
.hid_width = 5,
1107
+
.parent_map = cam_cc_parent_map_1,
1108
+
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1109
+
.clkr.hw.init = &(const struct clk_init_data) {
1110
+
.name = "cam_cc_mclk6_clk_src",
1111
+
.parent_data = cam_cc_parent_data_1,
1112
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1113
+
.flags = CLK_SET_RATE_PARENT,
1114
+
.ops = &clk_rcg2_ops,
1115
+
},
1116
+
};
1117
+
1118
+
static struct clk_rcg2 cam_cc_mclk7_clk_src = {
1119
+
.cmd_rcgr = 0x150c4,
1120
+
.mnd_width = 8,
1121
+
.hid_width = 5,
1122
+
.parent_map = cam_cc_parent_map_1,
1123
+
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
1124
+
.clkr.hw.init = &(const struct clk_init_data) {
1125
+
.name = "cam_cc_mclk7_clk_src",
1126
+
.parent_data = cam_cc_parent_data_1,
1127
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
1128
+
.flags = CLK_SET_RATE_PARENT,
1129
+
.ops = &clk_rcg2_ops,
1130
+
},
1131
+
};
1132
+
1133
+
static const struct freq_tbl ftbl_cam_cc_qdss_debug_clk_src[] = {
1134
+
F(19200000, P_BI_TCXO, 1, 0, 0),
1135
+
F(75000000, P_CAM_CC_PLL0_OUT_EVEN, 8, 0, 0),
1136
+
F(150000000, P_CAM_CC_PLL0_OUT_EVEN, 4, 0, 0),
1137
+
F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0),
1138
+
{ }
1139
+
};
1140
+
1141
+
static struct clk_rcg2 cam_cc_qdss_debug_clk_src = {
1142
+
.cmd_rcgr = 0x131bc,
1143
+
.mnd_width = 0,
1144
+
.hid_width = 5,
1145
+
.parent_map = cam_cc_parent_map_0,
1146
+
.freq_tbl = ftbl_cam_cc_qdss_debug_clk_src,
1147
+
.clkr.hw.init = &(const struct clk_init_data) {
1148
+
.name = "cam_cc_qdss_debug_clk_src",
1149
+
.parent_data = cam_cc_parent_data_0,
1150
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1151
+
.flags = CLK_SET_RATE_PARENT,
1152
+
.ops = &clk_rcg2_ops,
1153
+
},
1154
+
};
1155
+
1156
+
static const struct freq_tbl ftbl_cam_cc_sfe_0_clk_src[] = {
1157
+
F(432000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
1158
+
F(594000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
1159
+
F(675000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
1160
+
F(727000000, P_CAM_CC_PLL6_OUT_EVEN, 1, 0, 0),
1161
+
{ }
1162
+
};
1163
+
1164
+
static struct clk_rcg2 cam_cc_sfe_0_clk_src = {
1165
+
.cmd_rcgr = 0x13064,
1166
+
.mnd_width = 0,
1167
+
.hid_width = 5,
1168
+
.parent_map = cam_cc_parent_map_6,
1169
+
.freq_tbl = ftbl_cam_cc_sfe_0_clk_src,
1170
+
.clkr.hw.init = &(const struct clk_init_data) {
1171
+
.name = "cam_cc_sfe_0_clk_src",
1172
+
.parent_data = cam_cc_parent_data_6,
1173
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_6),
1174
+
.flags = CLK_SET_RATE_PARENT,
1175
+
.ops = &clk_rcg2_ops,
1176
+
},
1177
+
};
1178
+
1179
+
static const struct freq_tbl ftbl_cam_cc_sfe_1_clk_src[] = {
1180
+
F(432000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
1181
+
F(594000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
1182
+
F(675000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
1183
+
F(727000000, P_CAM_CC_PLL7_OUT_EVEN, 1, 0, 0),
1184
+
{ }
1185
+
};
1186
+
1187
+
static struct clk_rcg2 cam_cc_sfe_1_clk_src = {
1188
+
.cmd_rcgr = 0x130ac,
1189
+
.mnd_width = 0,
1190
+
.hid_width = 5,
1191
+
.parent_map = cam_cc_parent_map_7,
1192
+
.freq_tbl = ftbl_cam_cc_sfe_1_clk_src,
1193
+
.clkr.hw.init = &(const struct clk_init_data) {
1194
+
.name = "cam_cc_sfe_1_clk_src",
1195
+
.parent_data = cam_cc_parent_data_7,
1196
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_7),
1197
+
.flags = CLK_SET_RATE_PARENT,
1198
+
.ops = &clk_rcg2_ops,
1199
+
},
1200
+
};
1201
+
1202
+
static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = {
1203
+
F(32000, P_SLEEP_CLK, 1, 0, 0),
1204
+
{ }
1205
+
};
1206
+
1207
+
static struct clk_rcg2 cam_cc_sleep_clk_src = {
1208
+
.cmd_rcgr = 0x13210,
1209
+
.mnd_width = 0,
1210
+
.hid_width = 5,
1211
+
.parent_map = cam_cc_parent_map_8,
1212
+
.freq_tbl = ftbl_cam_cc_sleep_clk_src,
1213
+
.clkr.hw.init = &(const struct clk_init_data) {
1214
+
.name = "cam_cc_sleep_clk_src",
1215
+
.parent_data = cam_cc_parent_data_8,
1216
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_8),
1217
+
.flags = CLK_SET_RATE_PARENT,
1218
+
.ops = &clk_rcg2_ops,
1219
+
},
1220
+
};
1221
+
1222
+
static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = {
1223
+
F(19200000, P_BI_TCXO, 1, 0, 0),
1224
+
F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0),
1225
+
{ }
1226
+
};
1227
+
1228
+
static struct clk_rcg2 cam_cc_slow_ahb_clk_src = {
1229
+
.cmd_rcgr = 0x10034,
1230
+
.mnd_width = 8,
1231
+
.hid_width = 5,
1232
+
.parent_map = cam_cc_parent_map_0,
1233
+
.freq_tbl = ftbl_cam_cc_slow_ahb_clk_src,
1234
+
.clkr.hw.init = &(const struct clk_init_data) {
1235
+
.name = "cam_cc_slow_ahb_clk_src",
1236
+
.parent_data = cam_cc_parent_data_0,
1237
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
1238
+
.flags = CLK_SET_RATE_PARENT,
1239
+
.ops = &clk_rcg2_ops,
1240
+
},
1241
+
};
1242
+
1243
+
static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = {
1244
+
F(19200000, P_BI_TCXO, 1, 0, 0),
1245
+
{ }
1246
+
};
1247
+
1248
+
static struct clk_rcg2 cam_cc_xo_clk_src = {
1249
+
.cmd_rcgr = 0x131f4,
1250
+
.mnd_width = 0,
1251
+
.hid_width = 5,
1252
+
.parent_map = cam_cc_parent_map_9,
1253
+
.freq_tbl = ftbl_cam_cc_xo_clk_src,
1254
+
.clkr.hw.init = &(const struct clk_init_data) {
1255
+
.name = "cam_cc_xo_clk_src",
1256
+
.parent_data = cam_cc_parent_data_9_ao,
1257
+
.num_parents = ARRAY_SIZE(cam_cc_parent_data_9_ao),
1258
+
.flags = CLK_SET_RATE_PARENT,
1259
+
.ops = &clk_rcg2_ops,
1260
+
},
1261
+
};
1262
+
1263
+
static struct clk_branch cam_cc_gdsc_clk = {
1264
+
.halt_reg = 0x1320c,
1265
+
.halt_check = BRANCH_HALT,
1266
+
.clkr = {
1267
+
.enable_reg = 0x1320c,
1268
+
.enable_mask = BIT(0),
1269
+
.hw.init = &(const struct clk_init_data) {
1270
+
.name = "cam_cc_gdsc_clk",
1271
+
.parent_data = &(const struct clk_parent_data) {
1272
+
.hw = &cam_cc_xo_clk_src.clkr.hw,
1273
+
},
1274
+
.num_parents = 1,
1275
+
.flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1276
+
.ops = &clk_branch2_ops,
1277
+
},
1278
+
},
1279
+
};
1280
+
1281
+
static struct clk_branch cam_cc_bps_ahb_clk = {
1282
+
.halt_reg = 0x1004c,
1283
+
.halt_check = BRANCH_HALT,
1284
+
.clkr = {
1285
+
.enable_reg = 0x1004c,
1286
+
.enable_mask = BIT(0),
1287
+
.hw.init = &(const struct clk_init_data) {
1288
+
.name = "cam_cc_bps_ahb_clk",
1289
+
.parent_data = &(const struct clk_parent_data) {
1290
+
.hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
1291
+
},
1292
+
.num_parents = 1,
1293
+
.flags = CLK_SET_RATE_PARENT,
1294
+
.ops = &clk_branch2_ops,
1295
+
},
1296
+
},
1297
+
};
1298
+
1299
+
static struct clk_branch cam_cc_bps_clk = {
1300
+
.halt_reg = 0x10068,
1301
+
.halt_check = BRANCH_HALT,
1302
+
.clkr = {
1303
+
.enable_reg = 0x10068,
1304
+
.enable_mask = BIT(0),
1305
+
.hw.init = &(const struct clk_init_data) {
1306
+
.name = "cam_cc_bps_clk",
1307
+
.parent_data = &(const struct clk_parent_data) {
1308
+
.hw = &cam_cc_bps_clk_src.clkr.hw,
1309
+
},
1310
+
.num_parents = 1,
1311
+
.flags = CLK_SET_RATE_PARENT,
1312
+
.ops = &clk_branch2_ops,
1313
+
},
1314
+
},
1315
+
};
1316
+
1317
+
static struct clk_branch cam_cc_bps_fast_ahb_clk = {
1318
+
.halt_reg = 0x10030,
1319
+
.halt_check = BRANCH_HALT,
1320
+
.clkr = {
1321
+
.enable_reg = 0x10030,
1322
+
.enable_mask = BIT(0),
1323
+
.hw.init = &(const struct clk_init_data) {
1324
+
.name = "cam_cc_bps_fast_ahb_clk",
1325
+
.parent_data = &(const struct clk_parent_data) {
1326
+
.hw = &cam_cc_fast_ahb_clk_src.clkr.hw,
1327
+
},
1328
+
.num_parents = 1,
1329
+
.flags = CLK_SET_RATE_PARENT,
1330
+
.ops = &clk_branch2_ops,
1331
+
},
1332
+
},
1333
+
};
1334
+
1335
+
static struct clk_branch cam_cc_camnoc_axi_clk = {
1336
+
.halt_reg = 0x131ac,
1337
+
.halt_check = BRANCH_HALT,
1338
+
.clkr = {
1339
+
.enable_reg = 0x131ac,
1340
+
.enable_mask = BIT(0),
1341
+
.hw.init = &(const struct clk_init_data) {
1342
+
.name = "cam_cc_camnoc_axi_clk",
1343
+
.parent_data = &(const struct clk_parent_data) {
1344
+
.hw = &cam_cc_camnoc_axi_clk_src.clkr.hw,
1345
+
},
1346
+
.num_parents = 1,
1347
+
.flags = CLK_SET_RATE_PARENT,
1348
+
.ops = &clk_branch2_ops,
1349
+
},
1350
+
},
1351
+
};
1352
+
1353
+
static struct clk_branch cam_cc_camnoc_dcd_xo_clk = {
1354
+
.halt_reg = 0x131b4,
1355
+
.halt_check = BRANCH_HALT,
1356
+
.clkr = {
1357
+
.enable_reg = 0x131b4,
1358
+
.enable_mask = BIT(0),
1359
+
.hw.init = &(const struct clk_init_data) {
1360
+
.name = "cam_cc_camnoc_dcd_xo_clk",
1361
+
.parent_data = &(const struct clk_parent_data) {
1362
+
.hw = &cam_cc_xo_clk_src.clkr.hw,
1363
+
},
1364
+
.num_parents = 1,
1365
+
.flags = CLK_SET_RATE_PARENT,
1366
+
.ops = &clk_branch2_ops,
1367
+
},
1368
+
},
1369
+
};
1370
+
1371
+
static struct clk_branch cam_cc_cci_0_clk = {
1372
+
.halt_reg = 0x13144,
1373
+
.halt_check = BRANCH_HALT,
1374
+
.clkr = {
1375
+
.enable_reg = 0x13144,
1376
+
.enable_mask = BIT(0),
1377
+
.hw.init = &(const struct clk_init_data) {
1378
+
.name = "cam_cc_cci_0_clk",
1379
+
.parent_data = &(const struct clk_parent_data) {
1380
+
.hw = &cam_cc_cci_0_clk_src.clkr.hw,
1381
+
},
1382
+
.num_parents = 1,
1383
+
.flags = CLK_SET_RATE_PARENT,
1384
+
.ops = &clk_branch2_ops,
1385
+
},
1386
+
},
1387
+
};
1388
+
1389
+
static struct clk_branch cam_cc_cci_1_clk = {
1390
+
.halt_reg = 0x13160,
1391
+
.halt_check = BRANCH_HALT,
1392
+
.clkr = {
1393
+
.enable_reg = 0x13160,
1394
+
.enable_mask = BIT(0),
1395
+
.hw.init = &(const struct clk_init_data) {
1396
+
.name = "cam_cc_cci_1_clk",
1397
+
.parent_data = &(const struct clk_parent_data) {
1398
+
.hw = &cam_cc_cci_1_clk_src.clkr.hw,
1399
+
},
1400
+
.num_parents = 1,
1401
+
.flags = CLK_SET_RATE_PARENT,
1402
+
.ops = &clk_branch2_ops,
1403
+
},
1404
+
},
1405
+
};
1406
+
1407
+
static struct clk_branch cam_cc_core_ahb_clk = {
1408
+
.halt_reg = 0x131f0,
1409
+
.halt_check = BRANCH_HALT_DELAY,
1410
+
.clkr = {
1411
+
.enable_reg = 0x131f0,
1412
+
.enable_mask = BIT(0),
1413
+
.hw.init = &(const struct clk_init_data) {
1414
+
.name = "cam_cc_core_ahb_clk",
1415
+
.parent_data = &(const struct clk_parent_data) {
1416
+
.hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
1417
+
},
1418
+
.num_parents = 1,
1419
+
.flags = CLK_SET_RATE_PARENT,
1420
+
.ops = &clk_branch2_ops,
1421
+
},
1422
+
},
1423
+
};
1424
+
1425
+
static struct clk_branch cam_cc_cpas_ahb_clk = {
1426
+
.halt_reg = 0x13164,
1427
+
.halt_check = BRANCH_HALT,
1428
+
.clkr = {
1429
+
.enable_reg = 0x13164,
1430
+
.enable_mask = BIT(0),
1431
+
.hw.init = &(const struct clk_init_data) {
1432
+
.name = "cam_cc_cpas_ahb_clk",
1433
+
.parent_data = &(const struct clk_parent_data) {
1434
+
.hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
1435
+
},
1436
+
.num_parents = 1,
1437
+
.flags = CLK_SET_RATE_PARENT,
1438
+
.ops = &clk_branch2_ops,
1439
+
},
1440
+
},
1441
+
};
1442
+
1443
+
static struct clk_branch cam_cc_cpas_bps_clk = {
1444
+
.halt_reg = 0x10070,
1445
+
.halt_check = BRANCH_HALT,
1446
+
.clkr = {
1447
+
.enable_reg = 0x10070,
1448
+
.enable_mask = BIT(0),
1449
+
.hw.init = &(const struct clk_init_data) {
1450
+
.name = "cam_cc_cpas_bps_clk",
1451
+
.parent_data = &(const struct clk_parent_data) {
1452
+
.hw = &cam_cc_bps_clk_src.clkr.hw,
1453
+
},
1454
+
.num_parents = 1,
1455
+
.flags = CLK_SET_RATE_PARENT,
1456
+
.ops = &clk_branch2_ops,
1457
+
},
1458
+
},
1459
+
};
1460
+
1461
+
static struct clk_branch cam_cc_cpas_fast_ahb_clk = {
1462
+
.halt_reg = 0x1316c,
1463
+
.halt_check = BRANCH_HALT,
1464
+
.clkr = {
1465
+
.enable_reg = 0x1316c,
1466
+
.enable_mask = BIT(0),
1467
+
.hw.init = &(const struct clk_init_data) {
1468
+
.name = "cam_cc_cpas_fast_ahb_clk",
1469
+
.parent_data = &(const struct clk_parent_data) {
1470
+
.hw = &cam_cc_fast_ahb_clk_src.clkr.hw,
1471
+
},
1472
+
.num_parents = 1,
1473
+
.flags = CLK_SET_RATE_PARENT,
1474
+
.ops = &clk_branch2_ops,
1475
+
},
1476
+
},
1477
+
};
1478
+
1479
+
static struct clk_branch cam_cc_cpas_ife_0_clk = {
1480
+
.halt_reg = 0x11038,
1481
+
.halt_check = BRANCH_HALT,
1482
+
.clkr = {
1483
+
.enable_reg = 0x11038,
1484
+
.enable_mask = BIT(0),
1485
+
.hw.init = &(const struct clk_init_data) {
1486
+
.name = "cam_cc_cpas_ife_0_clk",
1487
+
.parent_data = &(const struct clk_parent_data) {
1488
+
.hw = &cam_cc_ife_0_clk_src.clkr.hw,
1489
+
},
1490
+
.num_parents = 1,
1491
+
.flags = CLK_SET_RATE_PARENT,
1492
+
.ops = &clk_branch2_ops,
1493
+
},
1494
+
},
1495
+
};
1496
+
1497
+
static struct clk_branch cam_cc_cpas_ife_1_clk = {
1498
+
.halt_reg = 0x12038,
1499
+
.halt_check = BRANCH_HALT,
1500
+
.clkr = {
1501
+
.enable_reg = 0x12038,
1502
+
.enable_mask = BIT(0),
1503
+
.hw.init = &(const struct clk_init_data) {
1504
+
.name = "cam_cc_cpas_ife_1_clk",
1505
+
.parent_data = &(const struct clk_parent_data) {
1506
+
.hw = &cam_cc_ife_1_clk_src.clkr.hw,
1507
+
},
1508
+
.num_parents = 1,
1509
+
.flags = CLK_SET_RATE_PARENT,
1510
+
.ops = &clk_branch2_ops,
1511
+
},
1512
+
},
1513
+
};
1514
+
1515
+
static struct clk_branch cam_cc_cpas_ife_2_clk = {
1516
+
.halt_reg = 0x12084,
1517
+
.halt_check = BRANCH_HALT,
1518
+
.clkr = {
1519
+
.enable_reg = 0x12084,
1520
+
.enable_mask = BIT(0),
1521
+
.hw.init = &(const struct clk_init_data) {
1522
+
.name = "cam_cc_cpas_ife_2_clk",
1523
+
.parent_data = &(const struct clk_parent_data) {
1524
+
.hw = &cam_cc_ife_2_clk_src.clkr.hw,
1525
+
},
1526
+
.num_parents = 1,
1527
+
.flags = CLK_SET_RATE_PARENT,
1528
+
.ops = &clk_branch2_ops,
1529
+
},
1530
+
},
1531
+
};
1532
+
1533
+
static struct clk_branch cam_cc_cpas_ife_lite_clk = {
1534
+
.halt_reg = 0x13020,
1535
+
.halt_check = BRANCH_HALT,
1536
+
.clkr = {
1537
+
.enable_reg = 0x13020,
1538
+
.enable_mask = BIT(0),
1539
+
.hw.init = &(const struct clk_init_data) {
1540
+
.name = "cam_cc_cpas_ife_lite_clk",
1541
+
.parent_data = &(const struct clk_parent_data) {
1542
+
.hw = &cam_cc_ife_lite_clk_src.clkr.hw,
1543
+
},
1544
+
.num_parents = 1,
1545
+
.flags = CLK_SET_RATE_PARENT,
1546
+
.ops = &clk_branch2_ops,
1547
+
},
1548
+
},
1549
+
};
1550
+
1551
+
static struct clk_branch cam_cc_cpas_ipe_nps_clk = {
1552
+
.halt_reg = 0x100ac,
1553
+
.halt_check = BRANCH_HALT,
1554
+
.clkr = {
1555
+
.enable_reg = 0x100ac,
1556
+
.enable_mask = BIT(0),
1557
+
.hw.init = &(const struct clk_init_data) {
1558
+
.name = "cam_cc_cpas_ipe_nps_clk",
1559
+
.parent_data = &(const struct clk_parent_data) {
1560
+
.hw = &cam_cc_ipe_nps_clk_src.clkr.hw,
1561
+
},
1562
+
.num_parents = 1,
1563
+
.flags = CLK_SET_RATE_PARENT,
1564
+
.ops = &clk_branch2_ops,
1565
+
},
1566
+
},
1567
+
};
1568
+
1569
+
static struct clk_branch cam_cc_cpas_sbi_clk = {
1570
+
.halt_reg = 0x100ec,
1571
+
.halt_check = BRANCH_HALT,
1572
+
.clkr = {
1573
+
.enable_reg = 0x100ec,
1574
+
.enable_mask = BIT(0),
1575
+
.hw.init = &(const struct clk_init_data) {
1576
+
.name = "cam_cc_cpas_sbi_clk",
1577
+
.parent_data = &(const struct clk_parent_data) {
1578
+
.hw = &cam_cc_ife_0_clk_src.clkr.hw,
1579
+
},
1580
+
.num_parents = 1,
1581
+
.flags = CLK_SET_RATE_PARENT,
1582
+
.ops = &clk_branch2_ops,
1583
+
},
1584
+
},
1585
+
};
1586
+
1587
+
static struct clk_branch cam_cc_cpas_sfe_0_clk = {
1588
+
.halt_reg = 0x13084,
1589
+
.halt_check = BRANCH_HALT,
1590
+
.clkr = {
1591
+
.enable_reg = 0x13084,
1592
+
.enable_mask = BIT(0),
1593
+
.hw.init = &(const struct clk_init_data) {
1594
+
.name = "cam_cc_cpas_sfe_0_clk",
1595
+
.parent_data = &(const struct clk_parent_data) {
1596
+
.hw = &cam_cc_sfe_0_clk_src.clkr.hw,
1597
+
},
1598
+
.num_parents = 1,
1599
+
.flags = CLK_SET_RATE_PARENT,
1600
+
.ops = &clk_branch2_ops,
1601
+
},
1602
+
},
1603
+
};
1604
+
1605
+
static struct clk_branch cam_cc_cpas_sfe_1_clk = {
1606
+
.halt_reg = 0x130cc,
1607
+
.halt_check = BRANCH_HALT,
1608
+
.clkr = {
1609
+
.enable_reg = 0x130cc,
1610
+
.enable_mask = BIT(0),
1611
+
.hw.init = &(const struct clk_init_data) {
1612
+
.name = "cam_cc_cpas_sfe_1_clk",
1613
+
.parent_data = &(const struct clk_parent_data) {
1614
+
.hw = &cam_cc_sfe_1_clk_src.clkr.hw,
1615
+
},
1616
+
.num_parents = 1,
1617
+
.flags = CLK_SET_RATE_PARENT,
1618
+
.ops = &clk_branch2_ops,
1619
+
},
1620
+
},
1621
+
};
1622
+
1623
+
static struct clk_branch cam_cc_csi0phytimer_clk = {
1624
+
.halt_reg = 0x150f8,
1625
+
.halt_check = BRANCH_HALT,
1626
+
.clkr = {
1627
+
.enable_reg = 0x150f8,
1628
+
.enable_mask = BIT(0),
1629
+
.hw.init = &(const struct clk_init_data) {
1630
+
.name = "cam_cc_csi0phytimer_clk",
1631
+
.parent_data = &(const struct clk_parent_data) {
1632
+
.hw = &cam_cc_csi0phytimer_clk_src.clkr.hw,
1633
+
},
1634
+
.num_parents = 1,
1635
+
.flags = CLK_SET_RATE_PARENT,
1636
+
.ops = &clk_branch2_ops,
1637
+
},
1638
+
},
1639
+
};
1640
+
1641
+
static struct clk_branch cam_cc_csi1phytimer_clk = {
1642
+
.halt_reg = 0x1511c,
1643
+
.halt_check = BRANCH_HALT,
1644
+
.clkr = {
1645
+
.enable_reg = 0x1511c,
1646
+
.enable_mask = BIT(0),
1647
+
.hw.init = &(const struct clk_init_data) {
1648
+
.name = "cam_cc_csi1phytimer_clk",
1649
+
.parent_data = &(const struct clk_parent_data) {
1650
+
.hw = &cam_cc_csi1phytimer_clk_src.clkr.hw,
1651
+
},
1652
+
.num_parents = 1,
1653
+
.flags = CLK_SET_RATE_PARENT,
1654
+
.ops = &clk_branch2_ops,
1655
+
},
1656
+
},
1657
+
};
1658
+
1659
+
static struct clk_branch cam_cc_csi2phytimer_clk = {
1660
+
.halt_reg = 0x1513c,
1661
+
.halt_check = BRANCH_HALT,
1662
+
.clkr = {
1663
+
.enable_reg = 0x1513c,
1664
+
.enable_mask = BIT(0),
1665
+
.hw.init = &(const struct clk_init_data) {
1666
+
.name = "cam_cc_csi2phytimer_clk",
1667
+
.parent_data = &(const struct clk_parent_data) {
1668
+
.hw = &cam_cc_csi2phytimer_clk_src.clkr.hw,
1669
+
},
1670
+
.num_parents = 1,
1671
+
.flags = CLK_SET_RATE_PARENT,
1672
+
.ops = &clk_branch2_ops,
1673
+
},
1674
+
},
1675
+
};
1676
+
1677
+
static struct clk_branch cam_cc_csi3phytimer_clk = {
1678
+
.halt_reg = 0x15164,
1679
+
.halt_check = BRANCH_HALT,
1680
+
.clkr = {
1681
+
.enable_reg = 0x15164,
1682
+
.enable_mask = BIT(0),
1683
+
.hw.init = &(const struct clk_init_data) {
1684
+
.name = "cam_cc_csi3phytimer_clk",
1685
+
.parent_data = &(const struct clk_parent_data) {
1686
+
.hw = &cam_cc_csi3phytimer_clk_src.clkr.hw,
1687
+
},
1688
+
.num_parents = 1,
1689
+
.flags = CLK_SET_RATE_PARENT,
1690
+
.ops = &clk_branch2_ops,
1691
+
},
1692
+
},
1693
+
};
1694
+
1695
+
static struct clk_branch cam_cc_csi4phytimer_clk = {
1696
+
.halt_reg = 0x15184,
1697
+
.halt_check = BRANCH_HALT,
1698
+
.clkr = {
1699
+
.enable_reg = 0x15184,
1700
+
.enable_mask = BIT(0),
1701
+
.hw.init = &(const struct clk_init_data) {
1702
+
.name = "cam_cc_csi4phytimer_clk",
1703
+
.parent_data = &(const struct clk_parent_data) {
1704
+
.hw = &cam_cc_csi4phytimer_clk_src.clkr.hw,
1705
+
},
1706
+
.num_parents = 1,
1707
+
.flags = CLK_SET_RATE_PARENT,
1708
+
.ops = &clk_branch2_ops,
1709
+
},
1710
+
},
1711
+
};
1712
+
1713
+
static struct clk_branch cam_cc_csi5phytimer_clk = {
1714
+
.halt_reg = 0x151a4,
1715
+
.halt_check = BRANCH_HALT,
1716
+
.clkr = {
1717
+
.enable_reg = 0x151a4,
1718
+
.enable_mask = BIT(0),
1719
+
.hw.init = &(const struct clk_init_data) {
1720
+
.name = "cam_cc_csi5phytimer_clk",
1721
+
.parent_data = &(const struct clk_parent_data) {
1722
+
.hw = &cam_cc_csi5phytimer_clk_src.clkr.hw,
1723
+
},
1724
+
.num_parents = 1,
1725
+
.flags = CLK_SET_RATE_PARENT,
1726
+
.ops = &clk_branch2_ops,
1727
+
},
1728
+
},
1729
+
};
1730
+
1731
+
static struct clk_branch cam_cc_csid_clk = {
1732
+
.halt_reg = 0x1318c,
1733
+
.halt_check = BRANCH_HALT,
1734
+
.clkr = {
1735
+
.enable_reg = 0x1318c,
1736
+
.enable_mask = BIT(0),
1737
+
.hw.init = &(const struct clk_init_data) {
1738
+
.name = "cam_cc_csid_clk",
1739
+
.parent_data = &(const struct clk_parent_data) {
1740
+
.hw = &cam_cc_csid_clk_src.clkr.hw,
1741
+
},
1742
+
.num_parents = 1,
1743
+
.flags = CLK_SET_RATE_PARENT,
1744
+
.ops = &clk_branch2_ops,
1745
+
},
1746
+
},
1747
+
};
1748
+
1749
+
static struct clk_branch cam_cc_csid_csiphy_rx_clk = {
1750
+
.halt_reg = 0x15100,
1751
+
.halt_check = BRANCH_HALT,
1752
+
.clkr = {
1753
+
.enable_reg = 0x15100,
1754
+
.enable_mask = BIT(0),
1755
+
.hw.init = &(const struct clk_init_data) {
1756
+
.name = "cam_cc_csid_csiphy_rx_clk",
1757
+
.parent_data = &(const struct clk_parent_data) {
1758
+
.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
1759
+
},
1760
+
.num_parents = 1,
1761
+
.flags = CLK_SET_RATE_PARENT,
1762
+
.ops = &clk_branch2_ops,
1763
+
},
1764
+
},
1765
+
};
1766
+
1767
+
static struct clk_branch cam_cc_csiphy0_clk = {
1768
+
.halt_reg = 0x150fc,
1769
+
.halt_check = BRANCH_HALT,
1770
+
.clkr = {
1771
+
.enable_reg = 0x150fc,
1772
+
.enable_mask = BIT(0),
1773
+
.hw.init = &(const struct clk_init_data) {
1774
+
.name = "cam_cc_csiphy0_clk",
1775
+
.parent_data = &(const struct clk_parent_data) {
1776
+
.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
1777
+
},
1778
+
.num_parents = 1,
1779
+
.flags = CLK_SET_RATE_PARENT,
1780
+
.ops = &clk_branch2_ops,
1781
+
},
1782
+
},
1783
+
};
1784
+
1785
+
static struct clk_branch cam_cc_csiphy1_clk = {
1786
+
.halt_reg = 0x15120,
1787
+
.halt_check = BRANCH_HALT,
1788
+
.clkr = {
1789
+
.enable_reg = 0x15120,
1790
+
.enable_mask = BIT(0),
1791
+
.hw.init = &(const struct clk_init_data) {
1792
+
.name = "cam_cc_csiphy1_clk",
1793
+
.parent_data = &(const struct clk_parent_data) {
1794
+
.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
1795
+
},
1796
+
.num_parents = 1,
1797
+
.flags = CLK_SET_RATE_PARENT,
1798
+
.ops = &clk_branch2_ops,
1799
+
},
1800
+
},
1801
+
};
1802
+
1803
+
static struct clk_branch cam_cc_csiphy2_clk = {
1804
+
.halt_reg = 0x15140,
1805
+
.halt_check = BRANCH_HALT,
1806
+
.clkr = {
1807
+
.enable_reg = 0x15140,
1808
+
.enable_mask = BIT(0),
1809
+
.hw.init = &(const struct clk_init_data) {
1810
+
.name = "cam_cc_csiphy2_clk",
1811
+
.parent_data = &(const struct clk_parent_data) {
1812
+
.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
1813
+
},
1814
+
.num_parents = 1,
1815
+
.flags = CLK_SET_RATE_PARENT,
1816
+
.ops = &clk_branch2_ops,
1817
+
},
1818
+
},
1819
+
};
1820
+
1821
+
static struct clk_branch cam_cc_csiphy3_clk = {
1822
+
.halt_reg = 0x15168,
1823
+
.halt_check = BRANCH_HALT,
1824
+
.clkr = {
1825
+
.enable_reg = 0x15168,
1826
+
.enable_mask = BIT(0),
1827
+
.hw.init = &(const struct clk_init_data) {
1828
+
.name = "cam_cc_csiphy3_clk",
1829
+
.parent_data = &(const struct clk_parent_data) {
1830
+
.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
1831
+
},
1832
+
.num_parents = 1,
1833
+
.flags = CLK_SET_RATE_PARENT,
1834
+
.ops = &clk_branch2_ops,
1835
+
},
1836
+
},
1837
+
};
1838
+
1839
+
static struct clk_branch cam_cc_csiphy4_clk = {
1840
+
.halt_reg = 0x15188,
1841
+
.halt_check = BRANCH_HALT,
1842
+
.clkr = {
1843
+
.enable_reg = 0x15188,
1844
+
.enable_mask = BIT(0),
1845
+
.hw.init = &(const struct clk_init_data) {
1846
+
.name = "cam_cc_csiphy4_clk",
1847
+
.parent_data = &(const struct clk_parent_data) {
1848
+
.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
1849
+
},
1850
+
.num_parents = 1,
1851
+
.flags = CLK_SET_RATE_PARENT,
1852
+
.ops = &clk_branch2_ops,
1853
+
},
1854
+
},
1855
+
};
1856
+
1857
+
static struct clk_branch cam_cc_csiphy5_clk = {
1858
+
.halt_reg = 0x151a8,
1859
+
.halt_check = BRANCH_HALT,
1860
+
.clkr = {
1861
+
.enable_reg = 0x151a8,
1862
+
.enable_mask = BIT(0),
1863
+
.hw.init = &(const struct clk_init_data) {
1864
+
.name = "cam_cc_csiphy5_clk",
1865
+
.parent_data = &(const struct clk_parent_data) {
1866
+
.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
1867
+
},
1868
+
.num_parents = 1,
1869
+
.flags = CLK_SET_RATE_PARENT,
1870
+
.ops = &clk_branch2_ops,
1871
+
},
1872
+
},
1873
+
};
1874
+
1875
+
static struct clk_branch cam_cc_icp_ahb_clk = {
1876
+
.halt_reg = 0x13128,
1877
+
.halt_check = BRANCH_HALT,
1878
+
.clkr = {
1879
+
.enable_reg = 0x13128,
1880
+
.enable_mask = BIT(0),
1881
+
.hw.init = &(const struct clk_init_data) {
1882
+
.name = "cam_cc_icp_ahb_clk",
1883
+
.parent_data = &(const struct clk_parent_data) {
1884
+
.hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
1885
+
},
1886
+
.num_parents = 1,
1887
+
.flags = CLK_SET_RATE_PARENT,
1888
+
.ops = &clk_branch2_ops,
1889
+
},
1890
+
},
1891
+
};
1892
+
1893
+
static struct clk_branch cam_cc_icp_clk = {
1894
+
.halt_reg = 0x13120,
1895
+
.halt_check = BRANCH_HALT,
1896
+
.clkr = {
1897
+
.enable_reg = 0x13120,
1898
+
.enable_mask = BIT(0),
1899
+
.hw.init = &(const struct clk_init_data) {
1900
+
.name = "cam_cc_icp_clk",
1901
+
.parent_data = &(const struct clk_parent_data) {
1902
+
.hw = &cam_cc_icp_clk_src.clkr.hw,
1903
+
},
1904
+
.num_parents = 1,
1905
+
.flags = CLK_SET_RATE_PARENT,
1906
+
.ops = &clk_branch2_ops,
1907
+
},
1908
+
},
1909
+
};
1910
+
1911
+
static struct clk_branch cam_cc_ife_0_clk = {
1912
+
.halt_reg = 0x11030,
1913
+
.halt_check = BRANCH_HALT,
1914
+
.clkr = {
1915
+
.enable_reg = 0x11030,
1916
+
.enable_mask = BIT(0),
1917
+
.hw.init = &(const struct clk_init_data) {
1918
+
.name = "cam_cc_ife_0_clk",
1919
+
.parent_data = &(const struct clk_parent_data) {
1920
+
.hw = &cam_cc_ife_0_clk_src.clkr.hw,
1921
+
},
1922
+
.num_parents = 1,
1923
+
.flags = CLK_SET_RATE_PARENT,
1924
+
.ops = &clk_branch2_ops,
1925
+
},
1926
+
},
1927
+
};
1928
+
1929
+
static struct clk_branch cam_cc_ife_0_dsp_clk = {
1930
+
.halt_reg = 0x1103c,
1931
+
.halt_check = BRANCH_HALT,
1932
+
.clkr = {
1933
+
.enable_reg = 0x1103c,
1934
+
.enable_mask = BIT(0),
1935
+
.hw.init = &(const struct clk_init_data) {
1936
+
.name = "cam_cc_ife_0_dsp_clk",
1937
+
.parent_data = &(const struct clk_parent_data) {
1938
+
.hw = &cam_cc_ife_0_clk_src.clkr.hw,
1939
+
},
1940
+
.num_parents = 1,
1941
+
.flags = CLK_SET_RATE_PARENT,
1942
+
.ops = &clk_branch2_ops,
1943
+
},
1944
+
},
1945
+
};
1946
+
1947
+
static struct clk_branch cam_cc_ife_0_fast_ahb_clk = {
1948
+
.halt_reg = 0x11048,
1949
+
.halt_check = BRANCH_HALT,
1950
+
.clkr = {
1951
+
.enable_reg = 0x11048,
1952
+
.enable_mask = BIT(0),
1953
+
.hw.init = &(const struct clk_init_data) {
1954
+
.name = "cam_cc_ife_0_fast_ahb_clk",
1955
+
.parent_data = &(const struct clk_parent_data) {
1956
+
.hw = &cam_cc_fast_ahb_clk_src.clkr.hw,
1957
+
},
1958
+
.num_parents = 1,
1959
+
.flags = CLK_SET_RATE_PARENT,
1960
+
.ops = &clk_branch2_ops,
1961
+
},
1962
+
},
1963
+
};
1964
+
1965
+
static struct clk_branch cam_cc_ife_1_clk = {
1966
+
.halt_reg = 0x12030,
1967
+
.halt_check = BRANCH_HALT,
1968
+
.clkr = {
1969
+
.enable_reg = 0x12030,
1970
+
.enable_mask = BIT(0),
1971
+
.hw.init = &(const struct clk_init_data) {
1972
+
.name = "cam_cc_ife_1_clk",
1973
+
.parent_data = &(const struct clk_parent_data) {
1974
+
.hw = &cam_cc_ife_1_clk_src.clkr.hw,
1975
+
},
1976
+
.num_parents = 1,
1977
+
.flags = CLK_SET_RATE_PARENT,
1978
+
.ops = &clk_branch2_ops,
1979
+
},
1980
+
},
1981
+
};
1982
+
1983
+
static struct clk_branch cam_cc_ife_1_dsp_clk = {
1984
+
.halt_reg = 0x1203c,
1985
+
.halt_check = BRANCH_HALT,
1986
+
.clkr = {
1987
+
.enable_reg = 0x1203c,
1988
+
.enable_mask = BIT(0),
1989
+
.hw.init = &(const struct clk_init_data) {
1990
+
.name = "cam_cc_ife_1_dsp_clk",
1991
+
.parent_data = &(const struct clk_parent_data) {
1992
+
.hw = &cam_cc_ife_1_clk_src.clkr.hw,
1993
+
},
1994
+
.num_parents = 1,
1995
+
.flags = CLK_SET_RATE_PARENT,
1996
+
.ops = &clk_branch2_ops,
1997
+
},
1998
+
},
1999
+
};
2000
+
2001
+
static struct clk_branch cam_cc_ife_1_fast_ahb_clk = {
2002
+
.halt_reg = 0x12048,
2003
+
.halt_check = BRANCH_HALT,
2004
+
.clkr = {
2005
+
.enable_reg = 0x12048,
2006
+
.enable_mask = BIT(0),
2007
+
.hw.init = &(const struct clk_init_data) {
2008
+
.name = "cam_cc_ife_1_fast_ahb_clk",
2009
+
.parent_data = &(const struct clk_parent_data) {
2010
+
.hw = &cam_cc_fast_ahb_clk_src.clkr.hw,
2011
+
},
2012
+
.num_parents = 1,
2013
+
.flags = CLK_SET_RATE_PARENT,
2014
+
.ops = &clk_branch2_ops,
2015
+
},
2016
+
},
2017
+
};
2018
+
2019
+
static struct clk_branch cam_cc_ife_2_clk = {
2020
+
.halt_reg = 0x1207c,
2021
+
.halt_check = BRANCH_HALT,
2022
+
.clkr = {
2023
+
.enable_reg = 0x1207c,
2024
+
.enable_mask = BIT(0),
2025
+
.hw.init = &(const struct clk_init_data) {
2026
+
.name = "cam_cc_ife_2_clk",
2027
+
.parent_data = &(const struct clk_parent_data) {
2028
+
.hw = &cam_cc_ife_2_clk_src.clkr.hw,
2029
+
},
2030
+
.num_parents = 1,
2031
+
.flags = CLK_SET_RATE_PARENT,
2032
+
.ops = &clk_branch2_ops,
2033
+
},
2034
+
},
2035
+
};
2036
+
2037
+
static struct clk_branch cam_cc_ife_2_dsp_clk = {
2038
+
.halt_reg = 0x12088,
2039
+
.halt_check = BRANCH_HALT,
2040
+
.clkr = {
2041
+
.enable_reg = 0x12088,
2042
+
.enable_mask = BIT(0),
2043
+
.hw.init = &(const struct clk_init_data) {
2044
+
.name = "cam_cc_ife_2_dsp_clk",
2045
+
.parent_data = &(const struct clk_parent_data) {
2046
+
.hw = &cam_cc_ife_2_clk_src.clkr.hw,
2047
+
},
2048
+
.num_parents = 1,
2049
+
.flags = CLK_SET_RATE_PARENT,
2050
+
.ops = &clk_branch2_ops,
2051
+
},
2052
+
},
2053
+
};
2054
+
2055
+
static struct clk_branch cam_cc_ife_2_fast_ahb_clk = {
2056
+
.halt_reg = 0x12094,
2057
+
.halt_check = BRANCH_HALT,
2058
+
.clkr = {
2059
+
.enable_reg = 0x12094,
2060
+
.enable_mask = BIT(0),
2061
+
.hw.init = &(const struct clk_init_data) {
2062
+
.name = "cam_cc_ife_2_fast_ahb_clk",
2063
+
.parent_data = &(const struct clk_parent_data) {
2064
+
.hw = &cam_cc_fast_ahb_clk_src.clkr.hw,
2065
+
},
2066
+
.num_parents = 1,
2067
+
.flags = CLK_SET_RATE_PARENT,
2068
+
.ops = &clk_branch2_ops,
2069
+
},
2070
+
},
2071
+
};
2072
+
2073
+
static struct clk_branch cam_cc_ife_lite_ahb_clk = {
2074
+
.halt_reg = 0x13048,
2075
+
.halt_check = BRANCH_HALT,
2076
+
.clkr = {
2077
+
.enable_reg = 0x13048,
2078
+
.enable_mask = BIT(0),
2079
+
.hw.init = &(const struct clk_init_data) {
2080
+
.name = "cam_cc_ife_lite_ahb_clk",
2081
+
.parent_data = &(const struct clk_parent_data) {
2082
+
.hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
2083
+
},
2084
+
.num_parents = 1,
2085
+
.flags = CLK_SET_RATE_PARENT,
2086
+
.ops = &clk_branch2_ops,
2087
+
},
2088
+
},
2089
+
};
2090
+
2091
+
static struct clk_branch cam_cc_ife_lite_clk = {
2092
+
.halt_reg = 0x13018,
2093
+
.halt_check = BRANCH_HALT,
2094
+
.clkr = {
2095
+
.enable_reg = 0x13018,
2096
+
.enable_mask = BIT(0),
2097
+
.hw.init = &(const struct clk_init_data) {
2098
+
.name = "cam_cc_ife_lite_clk",
2099
+
.parent_data = &(const struct clk_parent_data) {
2100
+
.hw = &cam_cc_ife_lite_clk_src.clkr.hw,
2101
+
},
2102
+
.num_parents = 1,
2103
+
.flags = CLK_SET_RATE_PARENT,
2104
+
.ops = &clk_branch2_ops,
2105
+
},
2106
+
},
2107
+
};
2108
+
2109
+
static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = {
2110
+
.halt_reg = 0x13044,
2111
+
.halt_check = BRANCH_HALT,
2112
+
.clkr = {
2113
+
.enable_reg = 0x13044,
2114
+
.enable_mask = BIT(0),
2115
+
.hw.init = &(const struct clk_init_data) {
2116
+
.name = "cam_cc_ife_lite_cphy_rx_clk",
2117
+
.parent_data = &(const struct clk_parent_data) {
2118
+
.hw = &cam_cc_cphy_rx_clk_src.clkr.hw,
2119
+
},
2120
+
.num_parents = 1,
2121
+
.flags = CLK_SET_RATE_PARENT,
2122
+
.ops = &clk_branch2_ops,
2123
+
},
2124
+
},
2125
+
};
2126
+
2127
+
static struct clk_branch cam_cc_ife_lite_csid_clk = {
2128
+
.halt_reg = 0x1303c,
2129
+
.halt_check = BRANCH_HALT,
2130
+
.clkr = {
2131
+
.enable_reg = 0x1303c,
2132
+
.enable_mask = BIT(0),
2133
+
.hw.init = &(const struct clk_init_data) {
2134
+
.name = "cam_cc_ife_lite_csid_clk",
2135
+
.parent_data = &(const struct clk_parent_data) {
2136
+
.hw = &cam_cc_ife_lite_csid_clk_src.clkr.hw,
2137
+
},
2138
+
.num_parents = 1,
2139
+
.flags = CLK_SET_RATE_PARENT,
2140
+
.ops = &clk_branch2_ops,
2141
+
},
2142
+
},
2143
+
};
2144
+
2145
+
static struct clk_branch cam_cc_ipe_nps_ahb_clk = {
2146
+
.halt_reg = 0x100c0,
2147
+
.halt_check = BRANCH_HALT,
2148
+
.clkr = {
2149
+
.enable_reg = 0x100c0,
2150
+
.enable_mask = BIT(0),
2151
+
.hw.init = &(const struct clk_init_data) {
2152
+
.name = "cam_cc_ipe_nps_ahb_clk",
2153
+
.parent_data = &(const struct clk_parent_data) {
2154
+
.hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
2155
+
},
2156
+
.num_parents = 1,
2157
+
.flags = CLK_SET_RATE_PARENT,
2158
+
.ops = &clk_branch2_ops,
2159
+
},
2160
+
},
2161
+
};
2162
+
2163
+
static struct clk_branch cam_cc_ipe_nps_clk = {
2164
+
.halt_reg = 0x100a4,
2165
+
.halt_check = BRANCH_HALT,
2166
+
.clkr = {
2167
+
.enable_reg = 0x100a4,
2168
+
.enable_mask = BIT(0),
2169
+
.hw.init = &(const struct clk_init_data) {
2170
+
.name = "cam_cc_ipe_nps_clk",
2171
+
.parent_data = &(const struct clk_parent_data) {
2172
+
.hw = &cam_cc_ipe_nps_clk_src.clkr.hw,
2173
+
},
2174
+
.num_parents = 1,
2175
+
.flags = CLK_SET_RATE_PARENT,
2176
+
.ops = &clk_branch2_ops,
2177
+
},
2178
+
},
2179
+
};
2180
+
2181
+
static struct clk_branch cam_cc_ipe_nps_fast_ahb_clk = {
2182
+
.halt_reg = 0x100c4,
2183
+
.halt_check = BRANCH_HALT,
2184
+
.clkr = {
2185
+
.enable_reg = 0x100c4,
2186
+
.enable_mask = BIT(0),
2187
+
.hw.init = &(const struct clk_init_data) {
2188
+
.name = "cam_cc_ipe_nps_fast_ahb_clk",
2189
+
.parent_data = &(const struct clk_parent_data) {
2190
+
.hw = &cam_cc_fast_ahb_clk_src.clkr.hw,
2191
+
},
2192
+
.num_parents = 1,
2193
+
.flags = CLK_SET_RATE_PARENT,
2194
+
.ops = &clk_branch2_ops,
2195
+
},
2196
+
},
2197
+
};
2198
+
2199
+
static struct clk_branch cam_cc_ipe_pps_clk = {
2200
+
.halt_reg = 0x100b0,
2201
+
.halt_check = BRANCH_HALT,
2202
+
.clkr = {
2203
+
.enable_reg = 0x100b0,
2204
+
.enable_mask = BIT(0),
2205
+
.hw.init = &(const struct clk_init_data) {
2206
+
.name = "cam_cc_ipe_pps_clk",
2207
+
.parent_data = &(const struct clk_parent_data) {
2208
+
.hw = &cam_cc_ipe_nps_clk_src.clkr.hw,
2209
+
},
2210
+
.num_parents = 1,
2211
+
.flags = CLK_SET_RATE_PARENT,
2212
+
.ops = &clk_branch2_ops,
2213
+
},
2214
+
},
2215
+
};
2216
+
2217
+
static struct clk_branch cam_cc_ipe_pps_fast_ahb_clk = {
2218
+
.halt_reg = 0x100c8,
2219
+
.halt_check = BRANCH_HALT,
2220
+
.clkr = {
2221
+
.enable_reg = 0x100c8,
2222
+
.enable_mask = BIT(0),
2223
+
.hw.init = &(const struct clk_init_data) {
2224
+
.name = "cam_cc_ipe_pps_fast_ahb_clk",
2225
+
.parent_data = &(const struct clk_parent_data) {
2226
+
.hw = &cam_cc_fast_ahb_clk_src.clkr.hw,
2227
+
},
2228
+
.num_parents = 1,
2229
+
.flags = CLK_SET_RATE_PARENT,
2230
+
.ops = &clk_branch2_ops,
2231
+
},
2232
+
},
2233
+
};
2234
+
2235
+
static struct clk_branch cam_cc_jpeg_clk = {
2236
+
.halt_reg = 0x130f4,
2237
+
.halt_check = BRANCH_HALT,
2238
+
.clkr = {
2239
+
.enable_reg = 0x130f4,
2240
+
.enable_mask = BIT(0),
2241
+
.hw.init = &(const struct clk_init_data) {
2242
+
.name = "cam_cc_jpeg_clk",
2243
+
.parent_data = &(const struct clk_parent_data) {
2244
+
.hw = &cam_cc_jpeg_clk_src.clkr.hw,
2245
+
},
2246
+
.num_parents = 1,
2247
+
.flags = CLK_SET_RATE_PARENT,
2248
+
.ops = &clk_branch2_ops,
2249
+
},
2250
+
},
2251
+
};
2252
+
2253
+
static struct clk_branch cam_cc_mclk0_clk = {
2254
+
.halt_reg = 0x15018,
2255
+
.halt_check = BRANCH_HALT,
2256
+
.clkr = {
2257
+
.enable_reg = 0x15018,
2258
+
.enable_mask = BIT(0),
2259
+
.hw.init = &(const struct clk_init_data) {
2260
+
.name = "cam_cc_mclk0_clk",
2261
+
.parent_data = &(const struct clk_parent_data) {
2262
+
.hw = &cam_cc_mclk0_clk_src.clkr.hw,
2263
+
},
2264
+
.num_parents = 1,
2265
+
.flags = CLK_SET_RATE_PARENT,
2266
+
.ops = &clk_branch2_ops,
2267
+
},
2268
+
},
2269
+
};
2270
+
2271
+
static struct clk_branch cam_cc_mclk1_clk = {
2272
+
.halt_reg = 0x15034,
2273
+
.halt_check = BRANCH_HALT,
2274
+
.clkr = {
2275
+
.enable_reg = 0x15034,
2276
+
.enable_mask = BIT(0),
2277
+
.hw.init = &(const struct clk_init_data) {
2278
+
.name = "cam_cc_mclk1_clk",
2279
+
.parent_data = &(const struct clk_parent_data) {
2280
+
.hw = &cam_cc_mclk1_clk_src.clkr.hw,
2281
+
},
2282
+
.num_parents = 1,
2283
+
.flags = CLK_SET_RATE_PARENT,
2284
+
.ops = &clk_branch2_ops,
2285
+
},
2286
+
},
2287
+
};
2288
+
2289
+
static struct clk_branch cam_cc_mclk2_clk = {
2290
+
.halt_reg = 0x15050,
2291
+
.halt_check = BRANCH_HALT,
2292
+
.clkr = {
2293
+
.enable_reg = 0x15050,
2294
+
.enable_mask = BIT(0),
2295
+
.hw.init = &(const struct clk_init_data) {
2296
+
.name = "cam_cc_mclk2_clk",
2297
+
.parent_data = &(const struct clk_parent_data) {
2298
+
.hw = &cam_cc_mclk2_clk_src.clkr.hw,
2299
+
},
2300
+
.num_parents = 1,
2301
+
.flags = CLK_SET_RATE_PARENT,
2302
+
.ops = &clk_branch2_ops,
2303
+
},
2304
+
},
2305
+
};
2306
+
2307
+
static struct clk_branch cam_cc_mclk3_clk = {
2308
+
.halt_reg = 0x1506c,
2309
+
.halt_check = BRANCH_HALT,
2310
+
.clkr = {
2311
+
.enable_reg = 0x1506c,
2312
+
.enable_mask = BIT(0),
2313
+
.hw.init = &(const struct clk_init_data) {
2314
+
.name = "cam_cc_mclk3_clk",
2315
+
.parent_data = &(const struct clk_parent_data) {
2316
+
.hw = &cam_cc_mclk3_clk_src.clkr.hw,
2317
+
},
2318
+
.num_parents = 1,
2319
+
.flags = CLK_SET_RATE_PARENT,
2320
+
.ops = &clk_branch2_ops,
2321
+
},
2322
+
},
2323
+
};
2324
+
2325
+
static struct clk_branch cam_cc_mclk4_clk = {
2326
+
.halt_reg = 0x15088,
2327
+
.halt_check = BRANCH_HALT,
2328
+
.clkr = {
2329
+
.enable_reg = 0x15088,
2330
+
.enable_mask = BIT(0),
2331
+
.hw.init = &(const struct clk_init_data) {
2332
+
.name = "cam_cc_mclk4_clk",
2333
+
.parent_data = &(const struct clk_parent_data) {
2334
+
.hw = &cam_cc_mclk4_clk_src.clkr.hw,
2335
+
},
2336
+
.num_parents = 1,
2337
+
.flags = CLK_SET_RATE_PARENT,
2338
+
.ops = &clk_branch2_ops,
2339
+
},
2340
+
},
2341
+
};
2342
+
2343
+
static struct clk_branch cam_cc_mclk5_clk = {
2344
+
.halt_reg = 0x150a4,
2345
+
.halt_check = BRANCH_HALT,
2346
+
.clkr = {
2347
+
.enable_reg = 0x150a4,
2348
+
.enable_mask = BIT(0),
2349
+
.hw.init = &(const struct clk_init_data) {
2350
+
.name = "cam_cc_mclk5_clk",
2351
+
.parent_data = &(const struct clk_parent_data) {
2352
+
.hw = &cam_cc_mclk5_clk_src.clkr.hw,
2353
+
},
2354
+
.num_parents = 1,
2355
+
.flags = CLK_SET_RATE_PARENT,
2356
+
.ops = &clk_branch2_ops,
2357
+
},
2358
+
},
2359
+
};
2360
+
2361
+
static struct clk_branch cam_cc_mclk6_clk = {
2362
+
.halt_reg = 0x150c0,
2363
+
.halt_check = BRANCH_HALT,
2364
+
.clkr = {
2365
+
.enable_reg = 0x150c0,
2366
+
.enable_mask = BIT(0),
2367
+
.hw.init = &(const struct clk_init_data) {
2368
+
.name = "cam_cc_mclk6_clk",
2369
+
.parent_data = &(const struct clk_parent_data) {
2370
+
.hw = &cam_cc_mclk6_clk_src.clkr.hw,
2371
+
},
2372
+
.num_parents = 1,
2373
+
.flags = CLK_SET_RATE_PARENT,
2374
+
.ops = &clk_branch2_ops,
2375
+
},
2376
+
},
2377
+
};
2378
+
2379
+
static struct clk_branch cam_cc_mclk7_clk = {
2380
+
.halt_reg = 0x150dc,
2381
+
.halt_check = BRANCH_HALT,
2382
+
.clkr = {
2383
+
.enable_reg = 0x150dc,
2384
+
.enable_mask = BIT(0),
2385
+
.hw.init = &(const struct clk_init_data) {
2386
+
.name = "cam_cc_mclk7_clk",
2387
+
.parent_data = &(const struct clk_parent_data) {
2388
+
.hw = &cam_cc_mclk7_clk_src.clkr.hw,
2389
+
},
2390
+
.num_parents = 1,
2391
+
.flags = CLK_SET_RATE_PARENT,
2392
+
.ops = &clk_branch2_ops,
2393
+
},
2394
+
},
2395
+
};
2396
+
2397
+
static struct clk_branch cam_cc_qdss_debug_clk = {
2398
+
.halt_reg = 0x131d4,
2399
+
.halt_check = BRANCH_HALT,
2400
+
.clkr = {
2401
+
.enable_reg = 0x131d4,
2402
+
.enable_mask = BIT(0),
2403
+
.hw.init = &(const struct clk_init_data) {
2404
+
.name = "cam_cc_qdss_debug_clk",
2405
+
.parent_data = &(const struct clk_parent_data) {
2406
+
.hw = &cam_cc_qdss_debug_clk_src.clkr.hw,
2407
+
},
2408
+
.num_parents = 1,
2409
+
.flags = CLK_SET_RATE_PARENT,
2410
+
.ops = &clk_branch2_ops,
2411
+
},
2412
+
},
2413
+
};
2414
+
2415
+
static struct clk_branch cam_cc_qdss_debug_xo_clk = {
2416
+
.halt_reg = 0x131d8,
2417
+
.halt_check = BRANCH_HALT,
2418
+
.clkr = {
2419
+
.enable_reg = 0x131d8,
2420
+
.enable_mask = BIT(0),
2421
+
.hw.init = &(const struct clk_init_data) {
2422
+
.name = "cam_cc_qdss_debug_xo_clk",
2423
+
.parent_data = &(const struct clk_parent_data) {
2424
+
.hw = &cam_cc_xo_clk_src.clkr.hw,
2425
+
},
2426
+
.num_parents = 1,
2427
+
.flags = CLK_SET_RATE_PARENT,
2428
+
.ops = &clk_branch2_ops,
2429
+
},
2430
+
},
2431
+
};
2432
+
2433
+
static struct clk_branch cam_cc_sbi_ahb_clk = {
2434
+
.halt_reg = 0x100f0,
2435
+
.halt_check = BRANCH_HALT,
2436
+
.clkr = {
2437
+
.enable_reg = 0x100f0,
2438
+
.enable_mask = BIT(0),
2439
+
.hw.init = &(const struct clk_init_data) {
2440
+
.name = "cam_cc_sbi_ahb_clk",
2441
+
.parent_data = &(const struct clk_parent_data) {
2442
+
.hw = &cam_cc_slow_ahb_clk_src.clkr.hw,
2443
+
},
2444
+
.num_parents = 1,
2445
+
.flags = CLK_SET_RATE_PARENT,
2446
+
.ops = &clk_branch2_ops,
2447
+
},
2448
+
},
2449
+
};
2450
+
2451
+
static struct clk_branch cam_cc_sbi_clk = {
2452
+
.halt_reg = 0x100e4,
2453
+
.halt_check = BRANCH_HALT,
2454
+
.clkr = {
2455
+
.enable_reg = 0x100e4,
2456
+
.enable_mask = BIT(0),
2457
+
.hw.init = &(const struct clk_init_data) {
2458
+
.name = "cam_cc_sbi_clk",
2459
+
.parent_data = &(const struct clk_parent_data) {
2460
+
.hw = &cam_cc_ife_0_clk_src.clkr.hw,
2461
+
},
2462
+
.num_parents = 1,
2463
+
.flags = CLK_SET_RATE_PARENT,
2464
+
.ops = &clk_branch2_ops,
2465
+
},
2466
+
},
2467
+
};
2468
+
2469
+
static struct clk_branch cam_cc_sfe_0_clk = {
2470
+
.halt_reg = 0x1307c,
2471
+
.halt_check = BRANCH_HALT,
2472
+
.clkr = {
2473
+
.enable_reg = 0x1307c,
2474
+
.enable_mask = BIT(0),
2475
+
.hw.init = &(const struct clk_init_data) {
2476
+
.name = "cam_cc_sfe_0_clk",
2477
+
.parent_data = &(const struct clk_parent_data) {
2478
+
.hw = &cam_cc_sfe_0_clk_src.clkr.hw,
2479
+
},
2480
+
.num_parents = 1,
2481
+
.flags = CLK_SET_RATE_PARENT,
2482
+
.ops = &clk_branch2_ops,
2483
+
},
2484
+
},
2485
+
};
2486
+
2487
+
static struct clk_branch cam_cc_sfe_0_fast_ahb_clk = {
2488
+
.halt_reg = 0x13090,
2489
+
.halt_check = BRANCH_HALT,
2490
+
.clkr = {
2491
+
.enable_reg = 0x13090,
2492
+
.enable_mask = BIT(0),
2493
+
.hw.init = &(const struct clk_init_data) {
2494
+
.name = "cam_cc_sfe_0_fast_ahb_clk",
2495
+
.parent_data = &(const struct clk_parent_data) {
2496
+
.hw = &cam_cc_fast_ahb_clk_src.clkr.hw,
2497
+
},
2498
+
.num_parents = 1,
2499
+
.flags = CLK_SET_RATE_PARENT,
2500
+
.ops = &clk_branch2_ops,
2501
+
},
2502
+
},
2503
+
};
2504
+
2505
+
static struct clk_branch cam_cc_sfe_1_clk = {
2506
+
.halt_reg = 0x130c4,
2507
+
.halt_check = BRANCH_HALT,
2508
+
.clkr = {
2509
+
.enable_reg = 0x130c4,
2510
+
.enable_mask = BIT(0),
2511
+
.hw.init = &(const struct clk_init_data) {
2512
+
.name = "cam_cc_sfe_1_clk",
2513
+
.parent_data = &(const struct clk_parent_data) {
2514
+
.hw = &cam_cc_sfe_1_clk_src.clkr.hw,
2515
+
},
2516
+
.num_parents = 1,
2517
+
.flags = CLK_SET_RATE_PARENT,
2518
+
.ops = &clk_branch2_ops,
2519
+
},
2520
+
},
2521
+
};
2522
+
2523
+
static struct clk_branch cam_cc_sfe_1_fast_ahb_clk = {
2524
+
.halt_reg = 0x130d8,
2525
+
.halt_check = BRANCH_HALT,
2526
+
.clkr = {
2527
+
.enable_reg = 0x130d8,
2528
+
.enable_mask = BIT(0),
2529
+
.hw.init = &(const struct clk_init_data) {
2530
+
.name = "cam_cc_sfe_1_fast_ahb_clk",
2531
+
.parent_data = &(const struct clk_parent_data) {
2532
+
.hw = &cam_cc_fast_ahb_clk_src.clkr.hw,
2533
+
},
2534
+
.num_parents = 1,
2535
+
.flags = CLK_SET_RATE_PARENT,
2536
+
.ops = &clk_branch2_ops,
2537
+
},
2538
+
},
2539
+
};
2540
+
2541
+
static struct clk_branch cam_cc_sleep_clk = {
2542
+
.halt_reg = 0x13228,
2543
+
.halt_check = BRANCH_HALT,
2544
+
.clkr = {
2545
+
.enable_reg = 0x13228,
2546
+
.enable_mask = BIT(0),
2547
+
.hw.init = &(const struct clk_init_data) {
2548
+
.name = "cam_cc_sleep_clk",
2549
+
.parent_data = &(const struct clk_parent_data) {
2550
+
.hw = &cam_cc_sleep_clk_src.clkr.hw,
2551
+
},
2552
+
.num_parents = 1,
2553
+
.flags = CLK_SET_RATE_PARENT,
2554
+
.ops = &clk_branch2_ops,
2555
+
},
2556
+
},
2557
+
};
2558
+
2559
+
static struct clk_regmap *cam_cc_sm8450_clocks[] = {
2560
+
[CAM_CC_BPS_AHB_CLK] = &cam_cc_bps_ahb_clk.clkr,
2561
+
[CAM_CC_BPS_CLK] = &cam_cc_bps_clk.clkr,
2562
+
[CAM_CC_BPS_CLK_SRC] = &cam_cc_bps_clk_src.clkr,
2563
+
[CAM_CC_BPS_FAST_AHB_CLK] = &cam_cc_bps_fast_ahb_clk.clkr,
2564
+
[CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr,
2565
+
[CAM_CC_CAMNOC_AXI_CLK_SRC] = &cam_cc_camnoc_axi_clk_src.clkr,
2566
+
[CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr,
2567
+
[CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr,
2568
+
[CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr,
2569
+
[CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr,
2570
+
[CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr,
2571
+
[CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr,
2572
+
[CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr,
2573
+
[CAM_CC_CPAS_BPS_CLK] = &cam_cc_cpas_bps_clk.clkr,
2574
+
[CAM_CC_CPAS_FAST_AHB_CLK] = &cam_cc_cpas_fast_ahb_clk.clkr,
2575
+
[CAM_CC_CPAS_IFE_0_CLK] = &cam_cc_cpas_ife_0_clk.clkr,
2576
+
[CAM_CC_CPAS_IFE_1_CLK] = &cam_cc_cpas_ife_1_clk.clkr,
2577
+
[CAM_CC_CPAS_IFE_2_CLK] = &cam_cc_cpas_ife_2_clk.clkr,
2578
+
[CAM_CC_CPAS_IFE_LITE_CLK] = &cam_cc_cpas_ife_lite_clk.clkr,
2579
+
[CAM_CC_CPAS_IPE_NPS_CLK] = &cam_cc_cpas_ipe_nps_clk.clkr,
2580
+
[CAM_CC_CPAS_SBI_CLK] = &cam_cc_cpas_sbi_clk.clkr,
2581
+
[CAM_CC_CPAS_SFE_0_CLK] = &cam_cc_cpas_sfe_0_clk.clkr,
2582
+
[CAM_CC_CPAS_SFE_1_CLK] = &cam_cc_cpas_sfe_1_clk.clkr,
2583
+
[CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr,
2584
+
[CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr,
2585
+
[CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr,
2586
+
[CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr,
2587
+
[CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr,
2588
+
[CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr,
2589
+
[CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr,
2590
+
[CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr,
2591
+
[CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr,
2592
+
[CAM_CC_CSI4PHYTIMER_CLK] = &cam_cc_csi4phytimer_clk.clkr,
2593
+
[CAM_CC_CSI4PHYTIMER_CLK_SRC] = &cam_cc_csi4phytimer_clk_src.clkr,
2594
+
[CAM_CC_CSI5PHYTIMER_CLK] = &cam_cc_csi5phytimer_clk.clkr,
2595
+
[CAM_CC_CSI5PHYTIMER_CLK_SRC] = &cam_cc_csi5phytimer_clk_src.clkr,
2596
+
[CAM_CC_CSID_CLK] = &cam_cc_csid_clk.clkr,
2597
+
[CAM_CC_CSID_CLK_SRC] = &cam_cc_csid_clk_src.clkr,
2598
+
[CAM_CC_CSID_CSIPHY_RX_CLK] = &cam_cc_csid_csiphy_rx_clk.clkr,
2599
+
[CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr,
2600
+
[CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr,
2601
+
[CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr,
2602
+
[CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr,
2603
+
[CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr,
2604
+
[CAM_CC_CSIPHY5_CLK] = &cam_cc_csiphy5_clk.clkr,
2605
+
[CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr,
2606
+
[CAM_CC_GDSC_CLK] = &cam_cc_gdsc_clk.clkr,
2607
+
[CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr,
2608
+
[CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr,
2609
+
[CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr,
2610
+
[CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr,
2611
+
[CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr,
2612
+
[CAM_CC_IFE_0_DSP_CLK] = &cam_cc_ife_0_dsp_clk.clkr,
2613
+
[CAM_CC_IFE_0_FAST_AHB_CLK] = &cam_cc_ife_0_fast_ahb_clk.clkr,
2614
+
[CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr,
2615
+
[CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr,
2616
+
[CAM_CC_IFE_1_DSP_CLK] = &cam_cc_ife_1_dsp_clk.clkr,
2617
+
[CAM_CC_IFE_1_FAST_AHB_CLK] = &cam_cc_ife_1_fast_ahb_clk.clkr,
2618
+
[CAM_CC_IFE_2_CLK] = &cam_cc_ife_2_clk.clkr,
2619
+
[CAM_CC_IFE_2_CLK_SRC] = &cam_cc_ife_2_clk_src.clkr,
2620
+
[CAM_CC_IFE_2_DSP_CLK] = &cam_cc_ife_2_dsp_clk.clkr,
2621
+
[CAM_CC_IFE_2_FAST_AHB_CLK] = &cam_cc_ife_2_fast_ahb_clk.clkr,
2622
+
[CAM_CC_IFE_LITE_AHB_CLK] = &cam_cc_ife_lite_ahb_clk.clkr,
2623
+
[CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr,
2624
+
[CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr,
2625
+
[CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr,
2626
+
[CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr,
2627
+
[CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr,
2628
+
[CAM_CC_IPE_NPS_AHB_CLK] = &cam_cc_ipe_nps_ahb_clk.clkr,
2629
+
[CAM_CC_IPE_NPS_CLK] = &cam_cc_ipe_nps_clk.clkr,
2630
+
[CAM_CC_IPE_NPS_CLK_SRC] = &cam_cc_ipe_nps_clk_src.clkr,
2631
+
[CAM_CC_IPE_NPS_FAST_AHB_CLK] = &cam_cc_ipe_nps_fast_ahb_clk.clkr,
2632
+
[CAM_CC_IPE_PPS_CLK] = &cam_cc_ipe_pps_clk.clkr,
2633
+
[CAM_CC_IPE_PPS_FAST_AHB_CLK] = &cam_cc_ipe_pps_fast_ahb_clk.clkr,
2634
+
[CAM_CC_JPEG_CLK] = &cam_cc_jpeg_clk.clkr,
2635
+
[CAM_CC_JPEG_CLK_SRC] = &cam_cc_jpeg_clk_src.clkr,
2636
+
[CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr,
2637
+
[CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr,
2638
+
[CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr,
2639
+
[CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr,
2640
+
[CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr,
2641
+
[CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr,
2642
+
[CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr,
2643
+
[CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr,
2644
+
[CAM_CC_MCLK4_CLK] = &cam_cc_mclk4_clk.clkr,
2645
+
[CAM_CC_MCLK4_CLK_SRC] = &cam_cc_mclk4_clk_src.clkr,
2646
+
[CAM_CC_MCLK5_CLK] = &cam_cc_mclk5_clk.clkr,
2647
+
[CAM_CC_MCLK5_CLK_SRC] = &cam_cc_mclk5_clk_src.clkr,
2648
+
[CAM_CC_MCLK6_CLK] = &cam_cc_mclk6_clk.clkr,
2649
+
[CAM_CC_MCLK6_CLK_SRC] = &cam_cc_mclk6_clk_src.clkr,
2650
+
[CAM_CC_MCLK7_CLK] = &cam_cc_mclk7_clk.clkr,
2651
+
[CAM_CC_MCLK7_CLK_SRC] = &cam_cc_mclk7_clk_src.clkr,
2652
+
[CAM_CC_PLL0] = &cam_cc_pll0.clkr,
2653
+
[CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr,
2654
+
[CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr,
2655
+
[CAM_CC_PLL1] = &cam_cc_pll1.clkr,
2656
+
[CAM_CC_PLL1_OUT_EVEN] = &cam_cc_pll1_out_even.clkr,
2657
+
[CAM_CC_PLL2] = &cam_cc_pll2.clkr,
2658
+
[CAM_CC_PLL3] = &cam_cc_pll3.clkr,
2659
+
[CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr,
2660
+
[CAM_CC_PLL4] = &cam_cc_pll4.clkr,
2661
+
[CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr,
2662
+
[CAM_CC_PLL5] = &cam_cc_pll5.clkr,
2663
+
[CAM_CC_PLL5_OUT_EVEN] = &cam_cc_pll5_out_even.clkr,
2664
+
[CAM_CC_PLL6] = &cam_cc_pll6.clkr,
2665
+
[CAM_CC_PLL6_OUT_EVEN] = &cam_cc_pll6_out_even.clkr,
2666
+
[CAM_CC_PLL7] = &cam_cc_pll7.clkr,
2667
+
[CAM_CC_PLL7_OUT_EVEN] = &cam_cc_pll7_out_even.clkr,
2668
+
[CAM_CC_PLL8] = &cam_cc_pll8.clkr,
2669
+
[CAM_CC_PLL8_OUT_EVEN] = &cam_cc_pll8_out_even.clkr,
2670
+
[CAM_CC_QDSS_DEBUG_CLK] = &cam_cc_qdss_debug_clk.clkr,
2671
+
[CAM_CC_QDSS_DEBUG_CLK_SRC] = &cam_cc_qdss_debug_clk_src.clkr,
2672
+
[CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr,
2673
+
[CAM_CC_SBI_AHB_CLK] = &cam_cc_sbi_ahb_clk.clkr,
2674
+
[CAM_CC_SBI_CLK] = &cam_cc_sbi_clk.clkr,
2675
+
[CAM_CC_SFE_0_CLK] = &cam_cc_sfe_0_clk.clkr,
2676
+
[CAM_CC_SFE_0_CLK_SRC] = &cam_cc_sfe_0_clk_src.clkr,
2677
+
[CAM_CC_SFE_0_FAST_AHB_CLK] = &cam_cc_sfe_0_fast_ahb_clk.clkr,
2678
+
[CAM_CC_SFE_1_CLK] = &cam_cc_sfe_1_clk.clkr,
2679
+
[CAM_CC_SFE_1_CLK_SRC] = &cam_cc_sfe_1_clk_src.clkr,
2680
+
[CAM_CC_SFE_1_FAST_AHB_CLK] = &cam_cc_sfe_1_fast_ahb_clk.clkr,
2681
+
[CAM_CC_SLEEP_CLK] = &cam_cc_sleep_clk.clkr,
2682
+
[CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr,
2683
+
[CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr,
2684
+
[CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr,
2685
+
};
2686
+
2687
+
static const struct qcom_reset_map cam_cc_sm8450_resets[] = {
2688
+
[CAM_CC_BPS_BCR] = { 0x10000 },
2689
+
[CAM_CC_ICP_BCR] = { 0x13104 },
2690
+
[CAM_CC_IFE_0_BCR] = { 0x11000 },
2691
+
[CAM_CC_IFE_1_BCR] = { 0x12000 },
2692
+
[CAM_CC_IFE_2_BCR] = { 0x1204c },
2693
+
[CAM_CC_IPE_0_BCR] = { 0x10074 },
2694
+
[CAM_CC_QDSS_DEBUG_BCR] = { 0x131b8 },
2695
+
[CAM_CC_SBI_BCR] = { 0x100cc },
2696
+
[CAM_CC_SFE_0_BCR] = { 0x1304c },
2697
+
[CAM_CC_SFE_1_BCR] = { 0x13094 },
2698
+
};
2699
+
2700
+
static const struct regmap_config cam_cc_sm8450_regmap_config = {
2701
+
.reg_bits = 32,
2702
+
.reg_stride = 4,
2703
+
.val_bits = 32,
2704
+
.max_register = 0x1601c,
2705
+
.fast_io = true,
2706
+
};
2707
+
2708
+
static struct gdsc titan_top_gdsc;
2709
+
2710
+
static struct gdsc bps_gdsc = {
2711
+
.gdscr = 0x10004,
2712
+
.pd = {
2713
+
.name = "bps_gdsc",
2714
+
},
2715
+
.flags = HW_CTRL | POLL_CFG_GDSCR,
2716
+
.pwrsts = PWRSTS_OFF_ON,
2717
+
};
2718
+
2719
+
static struct gdsc ipe_0_gdsc = {
2720
+
.gdscr = 0x10078,
2721
+
.pd = {
2722
+
.name = "ipe_0_gdsc",
2723
+
},
2724
+
.flags = HW_CTRL | POLL_CFG_GDSCR,
2725
+
.pwrsts = PWRSTS_OFF_ON,
2726
+
};
2727
+
2728
+
static struct gdsc sbi_gdsc = {
2729
+
.gdscr = 0x100d0,
2730
+
.pd = {
2731
+
.name = "sbi_gdsc",
2732
+
},
2733
+
.flags = POLL_CFG_GDSCR,
2734
+
.pwrsts = PWRSTS_OFF_ON,
2735
+
};
2736
+
2737
+
static struct gdsc ife_0_gdsc = {
2738
+
.gdscr = 0x11004,
2739
+
.pd = {
2740
+
.name = "ife_0_gdsc",
2741
+
},
2742
+
.flags = POLL_CFG_GDSCR,
2743
+
.parent = &titan_top_gdsc.pd,
2744
+
.pwrsts = PWRSTS_OFF_ON,
2745
+
};
2746
+
2747
+
static struct gdsc ife_1_gdsc = {
2748
+
.gdscr = 0x12004,
2749
+
.pd = {
2750
+
.name = "ife_1_gdsc",
2751
+
},
2752
+
.flags = POLL_CFG_GDSCR,
2753
+
.parent = &titan_top_gdsc.pd,
2754
+
.pwrsts = PWRSTS_OFF_ON,
2755
+
};
2756
+
2757
+
static struct gdsc ife_2_gdsc = {
2758
+
.gdscr = 0x12050,
2759
+
.pd = {
2760
+
.name = "ife_2_gdsc",
2761
+
},
2762
+
.flags = POLL_CFG_GDSCR,
2763
+
.parent = &titan_top_gdsc.pd,
2764
+
.pwrsts = PWRSTS_OFF_ON,
2765
+
};
2766
+
2767
+
static struct gdsc sfe_0_gdsc = {
2768
+
.gdscr = 0x13050,
2769
+
.pd = {
2770
+
.name = "sfe_0_gdsc",
2771
+
},
2772
+
.flags = POLL_CFG_GDSCR,
2773
+
.parent = &titan_top_gdsc.pd,
2774
+
.pwrsts = PWRSTS_OFF_ON,
2775
+
};
2776
+
2777
+
static struct gdsc sfe_1_gdsc = {
2778
+
.gdscr = 0x13098,
2779
+
.pd = {
2780
+
.name = "sfe_1_gdsc",
2781
+
},
2782
+
.flags = POLL_CFG_GDSCR,
2783
+
.parent = &titan_top_gdsc.pd,
2784
+
.pwrsts = PWRSTS_OFF_ON,
2785
+
};
2786
+
2787
+
static struct gdsc titan_top_gdsc = {
2788
+
.gdscr = 0x131dc,
2789
+
.pd = {
2790
+
.name = "titan_top_gdsc",
2791
+
},
2792
+
.flags = POLL_CFG_GDSCR,
2793
+
.pwrsts = PWRSTS_OFF_ON,
2794
+
};
2795
+
2796
+
static struct gdsc *cam_cc_sm8450_gdscs[] = {
2797
+
[BPS_GDSC] = &bps_gdsc,
2798
+
[IPE_0_GDSC] = &ipe_0_gdsc,
2799
+
[SBI_GDSC] = &sbi_gdsc,
2800
+
[IFE_0_GDSC] = &ife_0_gdsc,
2801
+
[IFE_1_GDSC] = &ife_1_gdsc,
2802
+
[IFE_2_GDSC] = &ife_2_gdsc,
2803
+
[SFE_0_GDSC] = &sfe_0_gdsc,
2804
+
[SFE_1_GDSC] = &sfe_1_gdsc,
2805
+
[TITAN_TOP_GDSC] = &titan_top_gdsc,
2806
+
};
2807
+
2808
+
static const struct qcom_cc_desc cam_cc_sm8450_desc = {
2809
+
.config = &cam_cc_sm8450_regmap_config,
2810
+
.clks = cam_cc_sm8450_clocks,
2811
+
.num_clks = ARRAY_SIZE(cam_cc_sm8450_clocks),
2812
+
.resets = cam_cc_sm8450_resets,
2813
+
.num_resets = ARRAY_SIZE(cam_cc_sm8450_resets),
2814
+
.gdscs = cam_cc_sm8450_gdscs,
2815
+
.num_gdscs = ARRAY_SIZE(cam_cc_sm8450_gdscs),
2816
+
};
2817
+
2818
+
static const struct of_device_id cam_cc_sm8450_match_table[] = {
2819
+
{ .compatible = "qcom,sm8450-camcc" },
2820
+
{ }
2821
+
};
2822
+
MODULE_DEVICE_TABLE(of, cam_cc_sm8450_match_table);
2823
+
2824
+
static int cam_cc_sm8450_probe(struct platform_device *pdev)
2825
+
{
2826
+
struct regmap *regmap;
2827
+
2828
+
regmap = qcom_cc_map(pdev, &cam_cc_sm8450_desc);
2829
+
if (IS_ERR(regmap))
2830
+
return PTR_ERR(regmap);
2831
+
2832
+
clk_lucid_evo_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config);
2833
+
clk_lucid_evo_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config);
2834
+
clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config);
2835
+
clk_lucid_evo_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);
2836
+
clk_lucid_evo_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);
2837
+
clk_lucid_evo_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config);
2838
+
clk_lucid_evo_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config);
2839
+
clk_lucid_evo_pll_configure(&cam_cc_pll7, regmap, &cam_cc_pll7_config);
2840
+
clk_lucid_evo_pll_configure(&cam_cc_pll8, regmap, &cam_cc_pll8_config);
2841
+
2842
+
return qcom_cc_really_probe(pdev, &cam_cc_sm8450_desc, regmap);
2843
+
}
2844
+
2845
+
static struct platform_driver cam_cc_sm8450_driver = {
2846
+
.probe = cam_cc_sm8450_probe,
2847
+
.driver = {
2848
+
.name = "camcc-sm8450",
2849
+
.of_match_table = cam_cc_sm8450_match_table,
2850
+
},
2851
+
};
2852
+
2853
+
module_platform_driver(cam_cc_sm8450_driver);
2854
+
2855
+
MODULE_DESCRIPTION("QCOM CAMCC SM8450 Driver");
2856
+
MODULE_LICENSE("GPL");
+139
-5
drivers/clk/qcom/clk-alpha-pll.c
+139
-5
drivers/clk/qcom/clk-alpha-pll.c
···
154
154
[PLL_OFF_TEST_CTL_U] = 0x30,
155
155
[PLL_OFF_TEST_CTL_U1] = 0x34,
156
156
},
157
+
[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO] = {
158
+
[PLL_OFF_OPMODE] = 0x04,
159
+
[PLL_OFF_STATUS] = 0x0c,
160
+
[PLL_OFF_L_VAL] = 0x10,
161
+
[PLL_OFF_USER_CTL] = 0x14,
162
+
[PLL_OFF_USER_CTL_U] = 0x18,
163
+
[PLL_OFF_CONFIG_CTL] = 0x1c,
164
+
[PLL_OFF_CONFIG_CTL_U] = 0x20,
165
+
[PLL_OFF_CONFIG_CTL_U1] = 0x24,
166
+
[PLL_OFF_TEST_CTL] = 0x28,
167
+
[PLL_OFF_TEST_CTL_U] = 0x2c,
168
+
},
157
169
};
158
170
EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
159
171
···
203
191
#define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21)
204
192
205
193
/* LUCID EVO PLL specific settings and offsets */
194
+
#define LUCID_EVO_PCAL_NOT_DONE BIT(8)
206
195
#define LUCID_EVO_ENABLE_VOTE_RUN BIT(25)
207
196
#define LUCID_EVO_PLL_L_VAL_MASK GENMASK(15, 0)
197
+
#define LUCID_EVO_PLL_CAL_L_VAL_SHIFT 16
208
198
209
199
/* ZONDA PLL specific */
210
200
#define ZONDA_PLL_OUT_MASK 0xf
···
1453
1439
EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops);
1454
1440
1455
1441
/**
1456
-
* clk_lucid_pll_configure - configure the lucid pll
1442
+
* clk_trion_pll_configure - configure the trion pll
1457
1443
*
1458
1444
* @pll: clk alpha pll
1459
1445
* @regmap: register map
···
1837
1823
.round_rate = clk_alpha_pll_round_rate,
1838
1824
.set_rate = alpha_pll_lucid_5lpe_set_rate,
1839
1825
};
1840
-
EXPORT_SYMBOL(clk_alpha_pll_lucid_5lpe_ops);
1826
+
EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_5lpe_ops);
1841
1827
1842
1828
const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops = {
1843
1829
.enable = alpha_pll_lucid_5lpe_enable,
···
1846
1832
.recalc_rate = clk_trion_pll_recalc_rate,
1847
1833
.round_rate = clk_alpha_pll_round_rate,
1848
1834
};
1849
-
EXPORT_SYMBOL(clk_alpha_pll_fixed_lucid_5lpe_ops);
1835
+
EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_5lpe_ops);
1850
1836
1851
1837
const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = {
1852
1838
.recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
1853
1839
.round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
1854
1840
.set_rate = clk_lucid_5lpe_pll_postdiv_set_rate,
1855
1841
};
1856
-
EXPORT_SYMBOL(clk_alpha_pll_postdiv_lucid_5lpe_ops);
1842
+
EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_5lpe_ops);
1857
1843
1858
1844
void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1859
1845
const struct alpha_pll_config *config)
···
2006
1992
.round_rate = clk_alpha_pll_round_rate,
2007
1993
.set_rate = clk_zonda_pll_set_rate,
2008
1994
};
2009
-
EXPORT_SYMBOL(clk_alpha_pll_zonda_ops);
1995
+
EXPORT_SYMBOL_GPL(clk_alpha_pll_zonda_ops);
1996
+
1997
+
void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
1998
+
const struct alpha_pll_config *config)
1999
+
{
2000
+
u32 lval = config->l;
2001
+
2002
+
lval |= TRION_PLL_CAL_VAL << LUCID_EVO_PLL_CAL_L_VAL_SHIFT;
2003
+
clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), lval);
2004
+
clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
2005
+
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
2006
+
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
2007
+
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
2008
+
clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
2009
+
clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
2010
+
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
2011
+
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
2012
+
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);
2013
+
2014
+
/* Disable PLL output */
2015
+
regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
2016
+
2017
+
/* Set operation mode to STANDBY and de-assert the reset */
2018
+
regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2019
+
regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
2020
+
}
2021
+
EXPORT_SYMBOL_GPL(clk_lucid_evo_pll_configure);
2010
2022
2011
2023
static int alpha_pll_lucid_evo_enable(struct clk_hw *hw)
2012
2024
{
···
2119
2079
regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2120
2080
}
2121
2081
2082
+
static int alpha_pll_lucid_evo_prepare(struct clk_hw *hw)
2083
+
{
2084
+
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2085
+
struct clk_hw *p;
2086
+
u32 val = 0;
2087
+
int ret;
2088
+
2089
+
/* Return early if calibration is not needed. */
2090
+
regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);
2091
+
if (!(val & LUCID_EVO_PCAL_NOT_DONE))
2092
+
return 0;
2093
+
2094
+
p = clk_hw_get_parent(hw);
2095
+
if (!p)
2096
+
return -EINVAL;
2097
+
2098
+
ret = alpha_pll_lucid_evo_enable(hw);
2099
+
if (ret)
2100
+
return ret;
2101
+
2102
+
alpha_pll_lucid_evo_disable(hw);
2103
+
2104
+
return 0;
2105
+
}
2106
+
2122
2107
static unsigned long alpha_pll_lucid_evo_recalc_rate(struct clk_hw *hw,
2123
2108
unsigned long parent_rate)
2124
2109
{
···
2179
2114
.set_rate = clk_lucid_evo_pll_postdiv_set_rate,
2180
2115
};
2181
2116
EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_evo_ops);
2117
+
2118
+
const struct clk_ops clk_alpha_pll_lucid_evo_ops = {
2119
+
.prepare = alpha_pll_lucid_evo_prepare,
2120
+
.enable = alpha_pll_lucid_evo_enable,
2121
+
.disable = alpha_pll_lucid_evo_disable,
2122
+
.is_enabled = clk_trion_pll_is_enabled,
2123
+
.recalc_rate = alpha_pll_lucid_evo_recalc_rate,
2124
+
.round_rate = clk_alpha_pll_round_rate,
2125
+
.set_rate = alpha_pll_lucid_5lpe_set_rate,
2126
+
};
2127
+
EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_evo_ops);
2128
+
2129
+
void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
2130
+
const struct alpha_pll_config *config)
2131
+
{
2132
+
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
2133
+
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
2134
+
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
2135
+
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
2136
+
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
2137
+
clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
2138
+
clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
2139
+
clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
2140
+
2141
+
regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
2142
+
2143
+
regmap_update_bits(regmap, PLL_MODE(pll),
2144
+
PLL_RESET_N | PLL_BYPASSNL | PLL_OUTCTRL,
2145
+
PLL_RESET_N | PLL_BYPASSNL);
2146
+
}
2147
+
EXPORT_SYMBOL_GPL(clk_rivian_evo_pll_configure);
2148
+
2149
+
static unsigned long clk_rivian_evo_pll_recalc_rate(struct clk_hw *hw,
2150
+
unsigned long parent_rate)
2151
+
{
2152
+
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2153
+
u32 l;
2154
+
2155
+
regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
2156
+
2157
+
return parent_rate * l;
2158
+
}
2159
+
2160
+
static long clk_rivian_evo_pll_round_rate(struct clk_hw *hw, unsigned long rate,
2161
+
unsigned long *prate)
2162
+
{
2163
+
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
2164
+
unsigned long min_freq, max_freq;
2165
+
u32 l;
2166
+
u64 a;
2167
+
2168
+
rate = alpha_pll_round_rate(rate, *prate, &l, &a, 0);
2169
+
if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
2170
+
return rate;
2171
+
2172
+
min_freq = pll->vco_table[0].min_freq;
2173
+
max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
2174
+
2175
+
return clamp(rate, min_freq, max_freq);
2176
+
}
2177
+
2178
+
const struct clk_ops clk_alpha_pll_rivian_evo_ops = {
2179
+
.enable = alpha_pll_lucid_5lpe_enable,
2180
+
.disable = alpha_pll_lucid_5lpe_disable,
2181
+
.is_enabled = clk_trion_pll_is_enabled,
2182
+
.recalc_rate = clk_rivian_evo_pll_recalc_rate,
2183
+
.round_rate = clk_rivian_evo_pll_round_rate,
2184
+
};
2185
+
EXPORT_SYMBOL_GPL(clk_alpha_pll_rivian_evo_ops);
+10
-1
drivers/clk/qcom/clk-alpha-pll.h
+10
-1
drivers/clk/qcom/clk-alpha-pll.h
···
18
18
CLK_ALPHA_PLL_TYPE_AGERA,
19
19
CLK_ALPHA_PLL_TYPE_ZONDA,
20
20
CLK_ALPHA_PLL_TYPE_LUCID_EVO,
21
+
CLK_ALPHA_PLL_TYPE_RIVIAN_EVO,
21
22
CLK_ALPHA_PLL_TYPE_MAX,
22
23
};
23
24
···
153
152
154
153
extern const struct clk_ops clk_alpha_pll_zonda_ops;
155
154
#define clk_alpha_pll_postdiv_zonda_ops clk_alpha_pll_postdiv_fabia_ops
155
+
156
+
extern const struct clk_ops clk_alpha_pll_lucid_evo_ops;
156
157
extern const struct clk_ops clk_alpha_pll_fixed_lucid_evo_ops;
157
158
extern const struct clk_ops clk_alpha_pll_postdiv_lucid_evo_ops;
159
+
160
+
extern const struct clk_ops clk_alpha_pll_rivian_evo_ops;
161
+
#define clk_alpha_pll_postdiv_rivian_evo_ops clk_alpha_pll_postdiv_fabia_ops
158
162
159
163
void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
160
164
const struct alpha_pll_config *config);
···
174
168
175
169
void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
176
170
const struct alpha_pll_config *config);
177
-
171
+
void clk_lucid_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
172
+
const struct alpha_pll_config *config);
173
+
void clk_rivian_evo_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
174
+
const struct alpha_pll_config *config);
178
175
179
176
#endif
+9
-6
drivers/clk/qcom/clk-hfpll.c
+9
-6
drivers/clk/qcom/clk-hfpll.c
···
72
72
regmap_update_bits(regmap, hd->mode_reg, PLL_RESET_N, PLL_RESET_N);
73
73
74
74
/* Wait for PLL to lock. */
75
-
if (hd->status_reg) {
76
-
do {
77
-
regmap_read(regmap, hd->status_reg, &val);
78
-
} while (!(val & BIT(hd->lock_bit)));
79
-
} else {
75
+
if (hd->status_reg)
76
+
/*
77
+
* Busy wait. Should never timeout, we add a timeout to
78
+
* prevent any sort of stall.
79
+
*/
80
+
regmap_read_poll_timeout(regmap, hd->status_reg, val,
81
+
!(val & BIT(hd->lock_bit)), 0,
82
+
100 * USEC_PER_MSEC);
83
+
else
80
84
udelay(60);
81
-
}
82
85
83
86
/* Enable PLL output. */
84
87
regmap_update_bits(regmap, hd->mode_reg, PLL_OUTCTRL, PLL_OUTCTRL);
+22
-1
drivers/clk/qcom/clk-krait.c
+22
-1
drivers/clk/qcom/clk-krait.c
···
18
18
static DEFINE_SPINLOCK(krait_clock_reg_lock);
19
19
20
20
#define LPL_SHIFT 8
21
+
#define SECCLKAGD BIT(4)
22
+
21
23
static void __krait_mux_set_sel(struct krait_mux_clk *mux, int sel)
22
24
{
23
25
unsigned long flags;
24
26
u32 regval;
25
27
26
28
spin_lock_irqsave(&krait_clock_reg_lock, flags);
29
+
27
30
regval = krait_get_l2_indirect_reg(mux->offset);
31
+
32
+
/* apq/ipq8064 Errata: disable sec_src clock gating during switch. */
33
+
if (mux->disable_sec_src_gating) {
34
+
regval |= SECCLKAGD;
35
+
krait_set_l2_indirect_reg(mux->offset, regval);
36
+
}
37
+
28
38
regval &= ~(mux->mask << mux->shift);
29
39
regval |= (sel & mux->mask) << mux->shift;
30
40
if (mux->lpl) {
···
42
32
regval |= (sel & mux->mask) << (mux->shift + LPL_SHIFT);
43
33
}
44
34
krait_set_l2_indirect_reg(mux->offset, regval);
45
-
spin_unlock_irqrestore(&krait_clock_reg_lock, flags);
35
+
36
+
/* apq/ipq8064 Errata: re-enabled sec_src clock gating. */
37
+
if (mux->disable_sec_src_gating) {
38
+
regval &= ~SECCLKAGD;
39
+
krait_set_l2_indirect_reg(mux->offset, regval);
40
+
}
46
41
47
42
/* Wait for switch to complete. */
48
43
mb();
49
44
udelay(1);
45
+
46
+
/*
47
+
* Unlock now to make sure the mux register is not
48
+
* modified while switching to the new parent.
49
+
*/
50
+
spin_unlock_irqrestore(&krait_clock_reg_lock, flags);
50
51
}
51
52
52
53
static int krait_mux_set_parent(struct clk_hw *hw, u8 index)
+1
drivers/clk/qcom/clk-krait.h
+1
drivers/clk/qcom/clk-krait.h
+12
-4
drivers/clk/qcom/clk-rcg2.c
+12
-4
drivers/clk/qcom/clk-rcg2.c
···
13
13
#include <linux/rational.h>
14
14
#include <linux/regmap.h>
15
15
#include <linux/math64.h>
16
+
#include <linux/minmax.h>
16
17
#include <linux/slab.h>
17
18
18
19
#include <asm/div64.h>
···
438
437
static int clk_rcg2_set_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)
439
438
{
440
439
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
441
-
u32 notn_m, n, m, d, not2d, mask, duty_per;
440
+
u32 notn_m, n, m, d, not2d, mask, duty_per, cfg;
442
441
int ret;
443
442
444
443
/* Duty-cycle cannot be modified for non-MND RCGs */
···
449
448
450
449
regmap_read(rcg->clkr.regmap, RCG_N_OFFSET(rcg), ¬n_m);
451
450
regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m);
451
+
regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg);
452
+
453
+
/* Duty-cycle cannot be modified if MND divider is in bypass mode. */
454
+
if (!(cfg & CFG_MODE_MASK))
455
+
return -EINVAL;
452
456
453
457
n = (~(notn_m) + m) & mask;
454
458
···
462
456
/* Calculate 2d value */
463
457
d = DIV_ROUND_CLOSEST(n * duty_per * 2, 100);
464
458
465
-
/* Check bit widths of 2d. If D is too big reduce duty cycle. */
466
-
if (d > mask)
467
-
d = mask;
459
+
/*
460
+
* Check bit widths of 2d. If D is too big reduce duty cycle.
461
+
* Also make sure it is never zero.
462
+
*/
463
+
d = clamp_val(d, 1, mask);
468
464
469
465
if ((d / 2) > (n - m))
470
466
d = (n - m) * 2;
+62
drivers/clk/qcom/clk-regmap-phy-mux.c
+62
drivers/clk/qcom/clk-regmap-phy-mux.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) 2022, Linaro Ltd.
4
+
*/
5
+
6
+
#include <linux/clk-provider.h>
7
+
#include <linux/bitfield.h>
8
+
#include <linux/regmap.h>
9
+
#include <linux/export.h>
10
+
11
+
#include "clk-regmap.h"
12
+
#include "clk-regmap-phy-mux.h"
13
+
14
+
#define PHY_MUX_MASK GENMASK(1, 0)
15
+
#define PHY_MUX_PHY_SRC 0
16
+
#define PHY_MUX_REF_SRC 2
17
+
18
+
static inline struct clk_regmap_phy_mux *to_clk_regmap_phy_mux(struct clk_regmap *clkr)
19
+
{
20
+
return container_of(clkr, struct clk_regmap_phy_mux, clkr);
21
+
}
22
+
23
+
static int phy_mux_is_enabled(struct clk_hw *hw)
24
+
{
25
+
struct clk_regmap *clkr = to_clk_regmap(hw);
26
+
struct clk_regmap_phy_mux *phy_mux = to_clk_regmap_phy_mux(clkr);
27
+
unsigned int val;
28
+
29
+
regmap_read(clkr->regmap, phy_mux->reg, &val);
30
+
val = FIELD_GET(PHY_MUX_MASK, val);
31
+
32
+
WARN_ON(val != PHY_MUX_PHY_SRC && val != PHY_MUX_REF_SRC);
33
+
34
+
return val == PHY_MUX_PHY_SRC;
35
+
}
36
+
37
+
static int phy_mux_enable(struct clk_hw *hw)
38
+
{
39
+
struct clk_regmap *clkr = to_clk_regmap(hw);
40
+
struct clk_regmap_phy_mux *phy_mux = to_clk_regmap_phy_mux(clkr);
41
+
42
+
return regmap_update_bits(clkr->regmap, phy_mux->reg,
43
+
PHY_MUX_MASK,
44
+
FIELD_PREP(PHY_MUX_MASK, PHY_MUX_PHY_SRC));
45
+
}
46
+
47
+
static void phy_mux_disable(struct clk_hw *hw)
48
+
{
49
+
struct clk_regmap *clkr = to_clk_regmap(hw);
50
+
struct clk_regmap_phy_mux *phy_mux = to_clk_regmap_phy_mux(clkr);
51
+
52
+
regmap_update_bits(clkr->regmap, phy_mux->reg,
53
+
PHY_MUX_MASK,
54
+
FIELD_PREP(PHY_MUX_MASK, PHY_MUX_REF_SRC));
55
+
}
56
+
57
+
const struct clk_ops clk_regmap_phy_mux_ops = {
58
+
.enable = phy_mux_enable,
59
+
.disable = phy_mux_disable,
60
+
.is_enabled = phy_mux_is_enabled,
61
+
};
62
+
EXPORT_SYMBOL_GPL(clk_regmap_phy_mux_ops);
+33
drivers/clk/qcom/clk-regmap-phy-mux.h
+33
drivers/clk/qcom/clk-regmap-phy-mux.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/*
3
+
* Copyright (c) 2022, Linaro Ltd.
4
+
*/
5
+
6
+
#ifndef __QCOM_CLK_REGMAP_PHY_MUX_H__
7
+
#define __QCOM_CLK_REGMAP_PHY_MUX_H__
8
+
9
+
#include "clk-regmap.h"
10
+
11
+
/*
12
+
* A clock implementation for PHY pipe and symbols clock muxes.
13
+
*
14
+
* If the clock is running off the from-PHY source, report it as enabled.
15
+
* Report it as disabled otherwise (if it uses reference source).
16
+
*
17
+
* This way the PHY will disable the pipe clock before turning off the GDSC,
18
+
* which in turn would lead to disabling corresponding pipe_clk_src (and thus
19
+
* it being parked to a safe, reference clock source). And vice versa, after
20
+
* enabling the GDSC the PHY will enable the pipe clock, which would cause
21
+
* pipe_clk_src to be switched from a safe source to the working one.
22
+
*
23
+
* For some platforms this should be used for the UFS symbol_clk_src clocks
24
+
* too.
25
+
*/
26
+
struct clk_regmap_phy_mux {
27
+
u32 reg;
28
+
struct clk_regmap clkr;
29
+
};
30
+
31
+
extern const struct clk_ops clk_regmap_phy_mux_ops;
32
+
33
+
#endif
+16
-8
drivers/clk/qcom/clk-rpm.c
+16
-8
drivers/clk/qcom/clk-rpm.c
···
23
23
#define QCOM_RPM_SCALING_ENABLE_ID 0x2
24
24
#define QCOM_RPM_XO_MODE_ON 0x2
25
25
26
+
static const struct clk_parent_data gcc_pxo[] = {
27
+
{ .fw_name = "pxo", .name = "pxo_board" },
28
+
};
29
+
30
+
static const struct clk_parent_data gcc_cxo[] = {
31
+
{ .fw_name = "cxo", .name = "cxo_board" },
32
+
};
33
+
26
34
#define DEFINE_CLK_RPM(_platform, _name, _active, r_id) \
27
35
static struct clk_rpm _platform##_##_active; \
28
36
static struct clk_rpm _platform##_##_name = { \
···
40
32
.hw.init = &(struct clk_init_data){ \
41
33
.ops = &clk_rpm_ops, \
42
34
.name = #_name, \
43
-
.parent_names = (const char *[]){ "pxo_board" }, \
44
-
.num_parents = 1, \
35
+
.parent_data = gcc_pxo, \
36
+
.num_parents = ARRAY_SIZE(gcc_pxo), \
45
37
}, \
46
38
}; \
47
39
static struct clk_rpm _platform##_##_active = { \
···
52
44
.hw.init = &(struct clk_init_data){ \
53
45
.ops = &clk_rpm_ops, \
54
46
.name = #_active, \
55
-
.parent_names = (const char *[]){ "pxo_board" }, \
56
-
.num_parents = 1, \
47
+
.parent_data = gcc_pxo, \
48
+
.num_parents = ARRAY_SIZE(gcc_pxo), \
57
49
}, \
58
50
}
59
51
···
64
56
.hw.init = &(struct clk_init_data){ \
65
57
.ops = &clk_rpm_xo_ops, \
66
58
.name = #_name, \
67
-
.parent_names = (const char *[]){ "cxo_board" }, \
68
-
.num_parents = 1, \
59
+
.parent_data = gcc_cxo, \
60
+
.num_parents = ARRAY_SIZE(gcc_cxo), \
69
61
}, \
70
62
}
71
63
···
76
68
.hw.init = &(struct clk_init_data){ \
77
69
.ops = &clk_rpm_fixed_ops, \
78
70
.name = #_name, \
79
-
.parent_names = (const char *[]){ "pxo" }, \
80
-
.num_parents = 1, \
71
+
.parent_data = gcc_pxo, \
72
+
.num_parents = ARRAY_SIZE(gcc_pxo), \
81
73
}, \
82
74
}
83
75
+5
drivers/clk/qcom/clk-rpmh.c
+5
drivers/clk/qcom/clk-rpmh.c
···
274
274
cmd.addr = c->res_addr;
275
275
cmd.data = BCM_TCS_CMD(1, enable, 0, cmd_state);
276
276
277
+
/*
278
+
* Send only an active only state request. RPMh continues to
279
+
* use the active state when we're in sleep/wake state as long
280
+
* as the sleep/wake state has never been set.
281
+
*/
277
282
ret = clk_rpmh_send(c, RPMH_ACTIVE_ONLY_STATE, &cmd, enable);
278
283
if (ret) {
279
284
dev_err(c->dev, "set active state of %s failed: (%d)\n",
+62
-2
drivers/clk/qcom/dispcc-sm8250.c
+62
-2
drivers/clk/qcom/dispcc-sm8250.c
···
43
43
{ 249600000, 2000000000, 0 },
44
44
};
45
45
46
+
static struct pll_vco lucid_5lpe_vco[] = {
47
+
{ 249600000, 1750000000, 0 },
48
+
};
49
+
46
50
static struct alpha_pll_config disp_cc_pll0_config = {
47
51
.l = 0x47,
48
52
.alpha = 0xE000,
···
1138
1134
},
1139
1135
.pwrsts = PWRSTS_OFF_ON,
1140
1136
.flags = HW_CTRL,
1141
-
.supply = "mmcx",
1142
1137
};
1143
1138
1144
1139
static struct clk_regmap *disp_cc_sm8250_clocks[] = {
···
1231
1228
{ .compatible = "qcom,sc8180x-dispcc" },
1232
1229
{ .compatible = "qcom,sm8150-dispcc" },
1233
1230
{ .compatible = "qcom,sm8250-dispcc" },
1231
+
{ .compatible = "qcom,sm8350-dispcc" },
1234
1232
{ }
1235
1233
};
1236
1234
MODULE_DEVICE_TABLE(of, disp_cc_sm8250_match_table);
···
1262
1258
return PTR_ERR(regmap);
1263
1259
}
1264
1260
1265
-
/* note: trion == lucid, except for the prepare() op */
1261
+
/* Apply differences for SM8150 and SM8350 */
1266
1262
BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION != CLK_ALPHA_PLL_TYPE_LUCID);
1267
1263
if (of_device_is_compatible(pdev->dev.of_node, "qcom,sc8180x-dispcc") ||
1268
1264
of_device_is_compatible(pdev->dev.of_node, "qcom,sm8150-dispcc")) {
···
1274
1270
disp_cc_pll1_config.config_ctl_hi1_val = 0x00000024;
1275
1271
disp_cc_pll1_config.user_ctl_hi1_val = 0x000000D0;
1276
1272
disp_cc_pll1_init.ops = &clk_alpha_pll_trion_ops;
1273
+
} else if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8350-dispcc")) {
1274
+
static struct clk_rcg2 * const rcgs[] = {
1275
+
&disp_cc_mdss_byte0_clk_src,
1276
+
&disp_cc_mdss_byte1_clk_src,
1277
+
&disp_cc_mdss_dp_aux1_clk_src,
1278
+
&disp_cc_mdss_dp_aux_clk_src,
1279
+
&disp_cc_mdss_dp_link1_clk_src,
1280
+
&disp_cc_mdss_dp_link_clk_src,
1281
+
&disp_cc_mdss_dp_pixel1_clk_src,
1282
+
&disp_cc_mdss_dp_pixel2_clk_src,
1283
+
&disp_cc_mdss_dp_pixel_clk_src,
1284
+
&disp_cc_mdss_esc0_clk_src,
1285
+
&disp_cc_mdss_mdp_clk_src,
1286
+
&disp_cc_mdss_pclk0_clk_src,
1287
+
&disp_cc_mdss_pclk1_clk_src,
1288
+
&disp_cc_mdss_rot_clk_src,
1289
+
&disp_cc_mdss_vsync_clk_src,
1290
+
};
1291
+
static struct clk_regmap_div * const divs[] = {
1292
+
&disp_cc_mdss_byte0_div_clk_src,
1293
+
&disp_cc_mdss_byte1_div_clk_src,
1294
+
&disp_cc_mdss_dp_link1_div_clk_src,
1295
+
&disp_cc_mdss_dp_link_div_clk_src,
1296
+
};
1297
+
unsigned int i;
1298
+
static bool offset_applied;
1299
+
1300
+
/*
1301
+
* note: trion == lucid, except for the prepare() op
1302
+
* only apply the offsets once (in case of deferred probe)
1303
+
*/
1304
+
if (!offset_applied) {
1305
+
for (i = 0; i < ARRAY_SIZE(rcgs); i++)
1306
+
rcgs[i]->cmd_rcgr -= 4;
1307
+
1308
+
for (i = 0; i < ARRAY_SIZE(divs); i++) {
1309
+
divs[i]->reg -= 4;
1310
+
divs[i]->width = 4;
1311
+
}
1312
+
1313
+
disp_cc_mdss_ahb_clk.halt_reg -= 4;
1314
+
disp_cc_mdss_ahb_clk.clkr.enable_reg -= 4;
1315
+
1316
+
offset_applied = true;
1317
+
}
1318
+
1319
+
disp_cc_mdss_ahb_clk_src.cmd_rcgr = 0x22a0;
1320
+
1321
+
disp_cc_pll0_config.config_ctl_hi1_val = 0x2a9a699c;
1322
+
disp_cc_pll0_config.test_ctl_hi1_val = 0x01800000;
1323
+
disp_cc_pll0_init.ops = &clk_alpha_pll_lucid_5lpe_ops;
1324
+
disp_cc_pll0.vco_table = lucid_5lpe_vco;
1325
+
disp_cc_pll1_config.config_ctl_hi1_val = 0x2a9a699c;
1326
+
disp_cc_pll1_config.test_ctl_hi1_val = 0x01800000;
1327
+
disp_cc_pll1_init.ops = &clk_alpha_pll_lucid_5lpe_ops;
1328
+
disp_cc_pll1.vco_table = lucid_5lpe_vco;
1277
1329
}
1278
1330
1279
1331
clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
+103
-1
drivers/clk/qcom/gcc-ipq8074.c
+103
-1
drivers/clk/qcom/gcc-ipq8074.c
···
22
22
#include "clk-alpha-pll.h"
23
23
#include "clk-regmap-divider.h"
24
24
#include "clk-regmap-mux.h"
25
+
#include "gdsc.h"
25
26
#include "reset.h"
26
27
27
28
enum {
···
663
662
},
664
663
.num_parents = 1,
665
664
.ops = &clk_branch2_ops,
665
+
.flags = CLK_IS_CRITICAL,
666
666
},
667
667
},
668
668
};
···
1790
1788
static const struct freq_tbl ftbl_nss_port5_rx_clk_src[] = {
1791
1789
F(19200000, P_XO, 1, 0, 0),
1792
1790
F(25000000, P_UNIPHY1_RX, 12.5, 0, 0),
1791
+
F(25000000, P_UNIPHY0_RX, 5, 0, 0),
1793
1792
F(78125000, P_UNIPHY1_RX, 4, 0, 0),
1794
1793
F(125000000, P_UNIPHY1_RX, 2.5, 0, 0),
1794
+
F(125000000, P_UNIPHY0_RX, 1, 0, 0),
1795
1795
F(156250000, P_UNIPHY1_RX, 2, 0, 0),
1796
1796
F(312500000, P_UNIPHY1_RX, 1, 0, 0),
1797
1797
{ }
···
1832
1828
static const struct freq_tbl ftbl_nss_port5_tx_clk_src[] = {
1833
1829
F(19200000, P_XO, 1, 0, 0),
1834
1830
F(25000000, P_UNIPHY1_TX, 12.5, 0, 0),
1831
+
F(25000000, P_UNIPHY0_TX, 5, 0, 0),
1835
1832
F(78125000, P_UNIPHY1_TX, 4, 0, 0),
1836
1833
F(125000000, P_UNIPHY1_TX, 2.5, 0, 0),
1834
+
F(125000000, P_UNIPHY0_TX, 1, 0, 0),
1837
1835
F(156250000, P_UNIPHY1_TX, 2, 0, 0),
1838
1836
F(312500000, P_UNIPHY1_TX, 1, 0, 0),
1839
1837
{ }
···
1873
1867
1874
1868
static const struct freq_tbl ftbl_nss_port6_rx_clk_src[] = {
1875
1869
F(19200000, P_XO, 1, 0, 0),
1870
+
F(25000000, P_UNIPHY2_RX, 5, 0, 0),
1876
1871
F(25000000, P_UNIPHY2_RX, 12.5, 0, 0),
1877
1872
F(78125000, P_UNIPHY2_RX, 4, 0, 0),
1873
+
F(125000000, P_UNIPHY2_RX, 1, 0, 0),
1878
1874
F(125000000, P_UNIPHY2_RX, 2.5, 0, 0),
1879
1875
F(156250000, P_UNIPHY2_RX, 2, 0, 0),
1880
1876
F(312500000, P_UNIPHY2_RX, 1, 0, 0),
···
1915
1907
1916
1908
static const struct freq_tbl ftbl_nss_port6_tx_clk_src[] = {
1917
1909
F(19200000, P_XO, 1, 0, 0),
1910
+
F(25000000, P_UNIPHY2_TX, 5, 0, 0),
1918
1911
F(25000000, P_UNIPHY2_TX, 12.5, 0, 0),
1919
1912
F(78125000, P_UNIPHY2_TX, 4, 0, 0),
1913
+
F(125000000, P_UNIPHY2_TX, 1, 0, 0),
1920
1914
F(125000000, P_UNIPHY2_TX, 2.5, 0, 0),
1921
1915
F(156250000, P_UNIPHY2_TX, 2, 0, 0),
1922
1916
F(312500000, P_UNIPHY2_TX, 1, 0, 0),
···
3184
3174
},
3185
3175
};
3186
3176
3177
+
static struct clk_branch gcc_crypto_ppe_clk = {
3178
+
.halt_reg = 0x68310,
3179
+
.halt_bit = 31,
3180
+
.clkr = {
3181
+
.enable_reg = 0x68310,
3182
+
.enable_mask = BIT(0),
3183
+
.hw.init = &(struct clk_init_data){
3184
+
.name = "gcc_crypto_ppe_clk",
3185
+
.parent_names = (const char *[]){
3186
+
"nss_ppe_clk_src"
3187
+
},
3188
+
.num_parents = 1,
3189
+
.flags = CLK_SET_RATE_PARENT,
3190
+
.ops = &clk_branch2_ops,
3191
+
},
3192
+
},
3193
+
};
3194
+
3187
3195
static struct clk_branch gcc_nssnoc_ce_apb_clk = {
3188
3196
.halt_reg = 0x6830c,
3189
3197
.clkr = {
···
3374
3346
3375
3347
static struct clk_branch gcc_ubi0_ahb_clk = {
3376
3348
.halt_reg = 0x6820c,
3349
+
.halt_check = BRANCH_HALT_DELAY,
3377
3350
.clkr = {
3378
3351
.enable_reg = 0x6820c,
3379
3352
.enable_mask = BIT(0),
···
3392
3363
3393
3364
static struct clk_branch gcc_ubi0_axi_clk = {
3394
3365
.halt_reg = 0x68200,
3366
+
.halt_check = BRANCH_HALT_DELAY,
3395
3367
.clkr = {
3396
3368
.enable_reg = 0x68200,
3397
3369
.enable_mask = BIT(0),
···
3410
3380
3411
3381
static struct clk_branch gcc_ubi0_nc_axi_clk = {
3412
3382
.halt_reg = 0x68204,
3383
+
.halt_check = BRANCH_HALT_DELAY,
3413
3384
.clkr = {
3414
3385
.enable_reg = 0x68204,
3415
3386
.enable_mask = BIT(0),
···
3428
3397
3429
3398
static struct clk_branch gcc_ubi0_core_clk = {
3430
3399
.halt_reg = 0x68210,
3400
+
.halt_check = BRANCH_HALT_DELAY,
3431
3401
.clkr = {
3432
3402
.enable_reg = 0x68210,
3433
3403
.enable_mask = BIT(0),
···
3446
3414
3447
3415
static struct clk_branch gcc_ubi0_mpt_clk = {
3448
3416
.halt_reg = 0x68208,
3417
+
.halt_check = BRANCH_HALT_DELAY,
3449
3418
.clkr = {
3450
3419
.enable_reg = 0x68208,
3451
3420
.enable_mask = BIT(0),
···
3464
3431
3465
3432
static struct clk_branch gcc_ubi1_ahb_clk = {
3466
3433
.halt_reg = 0x6822c,
3434
+
.halt_check = BRANCH_HALT_DELAY,
3467
3435
.clkr = {
3468
3436
.enable_reg = 0x6822c,
3469
3437
.enable_mask = BIT(0),
···
3482
3448
3483
3449
static struct clk_branch gcc_ubi1_axi_clk = {
3484
3450
.halt_reg = 0x68220,
3451
+
.halt_check = BRANCH_HALT_DELAY,
3485
3452
.clkr = {
3486
3453
.enable_reg = 0x68220,
3487
3454
.enable_mask = BIT(0),
···
3500
3465
3501
3466
static struct clk_branch gcc_ubi1_nc_axi_clk = {
3502
3467
.halt_reg = 0x68224,
3468
+
.halt_check = BRANCH_HALT_DELAY,
3503
3469
.clkr = {
3504
3470
.enable_reg = 0x68224,
3505
3471
.enable_mask = BIT(0),
···
3518
3482
3519
3483
static struct clk_branch gcc_ubi1_core_clk = {
3520
3484
.halt_reg = 0x68230,
3485
+
.halt_check = BRANCH_HALT_DELAY,
3521
3486
.clkr = {
3522
3487
.enable_reg = 0x68230,
3523
3488
.enable_mask = BIT(0),
···
3536
3499
3537
3500
static struct clk_branch gcc_ubi1_mpt_clk = {
3538
3501
.halt_reg = 0x68228,
3502
+
.halt_check = BRANCH_HALT_DELAY,
3539
3503
.clkr = {
3540
3504
.enable_reg = 0x68228,
3541
3505
.enable_mask = BIT(0),
···
4409
4371
},
4410
4372
};
4411
4373
4374
+
static struct gdsc usb0_gdsc = {
4375
+
.gdscr = 0x3e078,
4376
+
.pd = {
4377
+
.name = "usb0_gdsc",
4378
+
},
4379
+
.pwrsts = PWRSTS_OFF_ON,
4380
+
};
4381
+
4382
+
static struct gdsc usb1_gdsc = {
4383
+
.gdscr = 0x3f078,
4384
+
.pd = {
4385
+
.name = "usb1_gdsc",
4386
+
},
4387
+
.pwrsts = PWRSTS_OFF_ON,
4388
+
};
4389
+
4390
+
static const struct alpha_pll_config ubi32_pll_config = {
4391
+
.l = 0x4e,
4392
+
.config_ctl_val = 0x200d4aa8,
4393
+
.config_ctl_hi_val = 0x3c2,
4394
+
.main_output_mask = BIT(0),
4395
+
.aux_output_mask = BIT(1),
4396
+
.pre_div_val = 0x0,
4397
+
.pre_div_mask = BIT(12),
4398
+
.post_div_val = 0x0,
4399
+
.post_div_mask = GENMASK(9, 8),
4400
+
};
4401
+
4402
+
static const struct alpha_pll_config nss_crypto_pll_config = {
4403
+
.l = 0x3e,
4404
+
.alpha = 0x0,
4405
+
.alpha_hi = 0x80,
4406
+
.config_ctl_val = 0x4001055b,
4407
+
.main_output_mask = BIT(0),
4408
+
.pre_div_val = 0x0,
4409
+
.pre_div_mask = GENMASK(14, 12),
4410
+
.post_div_val = 0x1 << 8,
4411
+
.post_div_mask = GENMASK(11, 8),
4412
+
.vco_mask = GENMASK(21, 20),
4413
+
.vco_val = 0x0,
4414
+
.alpha_en_mask = BIT(24),
4415
+
};
4416
+
4412
4417
static struct clk_hw *gcc_ipq8074_hws[] = {
4413
4418
&gpll0_out_main_div2.hw,
4414
4419
&gpll6_out_main_div2.hw,
···
4690
4609
[GCC_PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr,
4691
4610
[GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
4692
4611
[GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
4612
+
[GCC_CRYPTO_PPE_CLK] = &gcc_crypto_ppe_clk.clkr,
4693
4613
};
4694
4614
4695
4615
static const struct qcom_reset_map gcc_ipq8074_resets[] = {
···
4828
4746
[GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
4829
4747
};
4830
4748
4749
+
static struct gdsc *gcc_ipq8074_gdscs[] = {
4750
+
[USB0_GDSC] = &usb0_gdsc,
4751
+
[USB1_GDSC] = &usb1_gdsc,
4752
+
};
4753
+
4831
4754
static const struct of_device_id gcc_ipq8074_match_table[] = {
4832
4755
{ .compatible = "qcom,gcc-ipq8074" },
4833
4756
{ }
···
4855
4768
.num_resets = ARRAY_SIZE(gcc_ipq8074_resets),
4856
4769
.clk_hws = gcc_ipq8074_hws,
4857
4770
.num_clk_hws = ARRAY_SIZE(gcc_ipq8074_hws),
4771
+
.gdscs = gcc_ipq8074_gdscs,
4772
+
.num_gdscs = ARRAY_SIZE(gcc_ipq8074_gdscs),
4858
4773
};
4859
4774
4860
4775
static int gcc_ipq8074_probe(struct platform_device *pdev)
4861
4776
{
4862
-
return qcom_cc_probe(pdev, &gcc_ipq8074_desc);
4777
+
struct regmap *regmap;
4778
+
4779
+
regmap = qcom_cc_map(pdev, &gcc_ipq8074_desc);
4780
+
if (IS_ERR(regmap))
4781
+
return PTR_ERR(regmap);
4782
+
4783
+
/* SW Workaround for UBI32 Huayra PLL */
4784
+
regmap_update_bits(regmap, 0x2501c, BIT(26), BIT(26));
4785
+
4786
+
clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);
4787
+
clk_alpha_pll_configure(&nss_crypto_pll_main, regmap,
4788
+
&nss_crypto_pll_config);
4789
+
4790
+
return qcom_cc_really_probe(pdev, &gcc_ipq8074_desc, regmap);
4863
4791
}
4864
4792
4865
4793
static struct platform_driver gcc_ipq8074_driver = {
+35
drivers/clk/qcom/gcc-msm8916.c
+35
drivers/clk/qcom/gcc-msm8916.c
···
765
765
},
766
766
};
767
767
768
+
/*
769
+
* This is a frequency table for "General Purpose" clocks.
770
+
* These clocks can be muxed to the SoC pins and may be used by
771
+
* external devices. They're often used as PWM source.
772
+
*
773
+
* See comment at ftbl_gcc_gp1_3_clk.
774
+
*/
768
775
static const struct freq_tbl ftbl_gcc_camss_gp0_1_clk[] = {
776
+
F(10000, P_XO, 16, 1, 120),
777
+
F(100000, P_XO, 16, 1, 12),
778
+
F(500000, P_GPLL0, 16, 1, 100),
779
+
F(1000000, P_GPLL0, 16, 1, 50),
780
+
F(2500000, P_GPLL0, 16, 1, 20),
781
+
F(5000000, P_GPLL0, 16, 1, 10),
769
782
F(100000000, P_GPLL0, 8, 0, 0),
770
783
F(200000000, P_GPLL0, 4, 0, 0),
771
784
{ }
···
940
927
},
941
928
};
942
929
930
+
/*
931
+
* This is a frequency table for "General Purpose" clocks.
932
+
* These clocks can be muxed to the SoC pins and may be used by
933
+
* external devices. They're often used as PWM source.
934
+
*
935
+
* Please note that MND divider must be enabled for duty-cycle
936
+
* control to be possible. (M != N) Also since D register is configured
937
+
* with a value multiplied by 2, and duty cycle is calculated as
938
+
* (2 * D) % 2^W
939
+
* DutyCycle = ----------------
940
+
* 2 * (N % 2^W)
941
+
* (where W = .mnd_width)
942
+
* N must be half or less than maximum value for the register.
943
+
* Otherwise duty-cycle control would be limited.
944
+
* (e.g. for 8-bit NMD N should be less than 128)
945
+
*/
943
946
static const struct freq_tbl ftbl_gcc_gp1_3_clk[] = {
947
+
F(10000, P_XO, 16, 1, 120),
948
+
F(100000, P_XO, 16, 1, 12),
949
+
F(500000, P_GPLL0, 16, 1, 100),
950
+
F(1000000, P_GPLL0, 16, 1, 50),
951
+
F(2500000, P_GPLL0, 16, 1, 20),
952
+
F(5000000, P_GPLL0, 16, 1, 10),
944
953
F(19200000, P_XO, 1, 0, 0),
945
954
{ }
946
955
};
+34
-13
drivers/clk/qcom/gcc-msm8939.c
+34
-13
drivers/clk/qcom/gcc-msm8939.c
···
632
632
};
633
633
634
634
static struct clk_rcg2 bimc_ddr_clk_src = {
635
-
.cmd_rcgr = 0x32004,
635
+
.cmd_rcgr = 0x32024,
636
636
.hid_width = 5,
637
637
.parent_map = gcc_xo_gpll0_bimc_map,
638
638
.clkr.hw.init = &(struct clk_init_data){
···
641
641
.num_parents = 3,
642
642
.ops = &clk_rcg2_ops,
643
643
.flags = CLK_GET_RATE_NOCACHE,
644
+
},
645
+
};
646
+
647
+
static struct clk_rcg2 system_mm_noc_bfdcd_clk_src = {
648
+
.cmd_rcgr = 0x2600c,
649
+
.hid_width = 5,
650
+
.parent_map = gcc_xo_gpll0_gpll6a_map,
651
+
.clkr.hw.init = &(struct clk_init_data){
652
+
.name = "system_mm_noc_bfdcd_clk_src",
653
+
.parent_data = gcc_xo_gpll0_gpll6a_parent_data,
654
+
.num_parents = 3,
655
+
.ops = &clk_rcg2_ops,
644
656
},
645
657
};
646
658
···
1014
1002
};
1015
1003
1016
1004
static const struct freq_tbl ftbl_gcc_camss_cci_clk[] = {
1017
-
F(19200000, P_XO, 1, 0, 0),
1005
+
F(19200000, P_XO, 1, 0, 0),
1006
+
F(37500000, P_GPLL0, 1, 3, 64),
1018
1007
{ }
1019
1008
};
1020
1009
···
1155
1142
1156
1143
static const struct freq_tbl ftbl_gcc_camss_cpp_clk[] = {
1157
1144
F(160000000, P_GPLL0, 5, 0, 0),
1145
+
F(200000000, P_GPLL0, 4, 0, 0),
1146
+
F(228570000, P_GPLL0, 3.5, 0, 0),
1147
+
F(266670000, P_GPLL0, 3, 0, 0),
1158
1148
F(320000000, P_GPLL0, 2.5, 0, 0),
1159
1149
F(465000000, P_GPLL2, 2, 0, 0),
1160
1150
{ }
···
1306
1290
F(50000000, P_GPLL0_AUX, 16, 0, 0),
1307
1291
F(80000000, P_GPLL0_AUX, 10, 0, 0),
1308
1292
F(100000000, P_GPLL0_AUX, 8, 0, 0),
1293
+
F(145500000, P_GPLL0_AUX, 5.5, 0, 0),
1294
+
F(153600000, P_GPLL0, 4, 0, 0),
1309
1295
F(160000000, P_GPLL0_AUX, 5, 0, 0),
1310
1296
F(177780000, P_GPLL0_AUX, 4.5, 0, 0),
1311
1297
F(200000000, P_GPLL0_AUX, 4, 0, 0),
···
1480
1462
};
1481
1463
1482
1464
static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
1465
+
F(57140000, P_GPLL0, 14, 0, 0),
1483
1466
F(80000000, P_GPLL0, 10, 0, 0),
1467
+
F(100000000, P_GPLL0, 8, 0, 0),
1484
1468
{ }
1485
1469
};
1486
1470
···
1843
1823
};
1844
1824
1845
1825
static const struct freq_tbl ftbl_gcc_venus0_vcodec0_clk[] = {
1846
-
F(100000000, P_GPLL0, 8, 0, 0),
1847
-
F(160000000, P_GPLL0, 5, 0, 0),
1848
-
F(228570000, P_GPLL0, 3.5, 0, 0),
1826
+
F(133330000, P_GPLL0, 6, 0, 0),
1827
+
F(200000000, P_GPLL0, 4, 0, 0),
1828
+
F(266670000, P_GPLL0, 3, 0, 0),
1849
1829
{ }
1850
1830
};
1851
1831
···
2461
2441
.hw.init = &(struct clk_init_data){
2462
2442
.name = "gcc_camss_jpeg_axi_clk",
2463
2443
.parent_data = &(const struct clk_parent_data){
2464
-
.hw = &system_noc_bfdcd_clk_src.clkr.hw,
2444
+
.hw = &system_mm_noc_bfdcd_clk_src.clkr.hw,
2465
2445
},
2466
2446
.num_parents = 1,
2467
2447
.flags = CLK_SET_RATE_PARENT,
···
2665
2645
.hw.init = &(struct clk_init_data){
2666
2646
.name = "gcc_camss_vfe_axi_clk",
2667
2647
.parent_data = &(const struct clk_parent_data){
2668
-
.hw = &system_noc_bfdcd_clk_src.clkr.hw,
2648
+
.hw = &system_mm_noc_bfdcd_clk_src.clkr.hw,
2669
2649
},
2670
2650
.num_parents = 1,
2671
2651
.flags = CLK_SET_RATE_PARENT,
···
2821
2801
.hw.init = &(struct clk_init_data){
2822
2802
.name = "gcc_mdss_axi_clk",
2823
2803
.parent_data = &(const struct clk_parent_data){
2824
-
.hw = &system_noc_bfdcd_clk_src.clkr.hw,
2804
+
.hw = &system_mm_noc_bfdcd_clk_src.clkr.hw,
2825
2805
},
2826
2806
.num_parents = 1,
2827
2807
.flags = CLK_SET_RATE_PARENT,
···
3213
3193
.hw.init = &(struct clk_init_data){
3214
3194
.name = "gcc_mdp_tbu_clk",
3215
3195
.parent_data = &(const struct clk_parent_data){
3216
-
.hw = &system_noc_bfdcd_clk_src.clkr.hw,
3196
+
.hw = &system_mm_noc_bfdcd_clk_src.clkr.hw,
3217
3197
},
3218
3198
.num_parents = 1,
3219
3199
.flags = CLK_SET_RATE_PARENT,
···
3231
3211
.hw.init = &(struct clk_init_data){
3232
3212
.name = "gcc_venus_tbu_clk",
3233
3213
.parent_data = &(const struct clk_parent_data){
3234
-
.hw = &system_noc_bfdcd_clk_src.clkr.hw,
3214
+
.hw = &system_mm_noc_bfdcd_clk_src.clkr.hw,
3235
3215
},
3236
3216
.num_parents = 1,
3237
3217
.flags = CLK_SET_RATE_PARENT,
···
3249
3229
.hw.init = &(struct clk_init_data){
3250
3230
.name = "gcc_vfe_tbu_clk",
3251
3231
.parent_data = &(const struct clk_parent_data){
3252
-
.hw = &system_noc_bfdcd_clk_src.clkr.hw,
3232
+
.hw = &system_mm_noc_bfdcd_clk_src.clkr.hw,
3253
3233
},
3254
3234
.num_parents = 1,
3255
3235
.flags = CLK_SET_RATE_PARENT,
···
3267
3247
.hw.init = &(struct clk_init_data){
3268
3248
.name = "gcc_jpeg_tbu_clk",
3269
3249
.parent_data = &(const struct clk_parent_data){
3270
-
.hw = &system_noc_bfdcd_clk_src.clkr.hw,
3250
+
.hw = &system_mm_noc_bfdcd_clk_src.clkr.hw,
3271
3251
},
3272
3252
.num_parents = 1,
3273
3253
.flags = CLK_SET_RATE_PARENT,
···
3504
3484
.hw.init = &(struct clk_init_data){
3505
3485
.name = "gcc_venus0_axi_clk",
3506
3486
.parent_data = &(const struct clk_parent_data){
3507
-
.hw = &system_noc_bfdcd_clk_src.clkr.hw,
3487
+
.hw = &system_mm_noc_bfdcd_clk_src.clkr.hw,
3508
3488
},
3509
3489
.num_parents = 1,
3510
3490
.flags = CLK_SET_RATE_PARENT,
···
3643
3623
[GPLL2_VOTE] = &gpll2_vote,
3644
3624
[PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
3645
3625
[SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
3626
+
[SYSTEM_MM_NOC_BFDCD_CLK_SRC] = &system_mm_noc_bfdcd_clk_src.clkr,
3646
3627
[CAMSS_AHB_CLK_SRC] = &camss_ahb_clk_src.clkr,
3647
3628
[APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
3648
3629
[CSI0_CLK_SRC] = &csi0_clk_src.clkr,
+5
-1
drivers/clk/qcom/gcc-msm8960.c
+5
-1
drivers/clk/qcom/gcc-msm8960.c
···
3641
3641
hfpll_l2.d = &hfpll_l2_8064_data;
3642
3642
}
3643
3643
3644
+
if (of_get_available_child_count(pdev->dev.of_node) != 0)
3645
+
return devm_of_platform_populate(&pdev->dev);
3646
+
3644
3647
tsens = platform_device_register_data(&pdev->dev, "qcom-tsens", -1,
3645
3648
NULL, 0);
3646
3649
if (IS_ERR(tsens))
···
3658
3655
{
3659
3656
struct platform_device *tsens = platform_get_drvdata(pdev);
3660
3657
3661
-
platform_device_unregister(tsens);
3658
+
if (tsens)
3659
+
platform_device_unregister(tsens);
3662
3660
3663
3661
return 0;
3664
3662
}
+6
-2
drivers/clk/qcom/gcc-msm8994.c
+6
-2
drivers/clk/qcom/gcc-msm8994.c
···
52
52
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
53
53
.clkr.hw.init = &(struct clk_init_data){
54
54
.name = "gpll0",
55
-
.parent_names = (const char *[]) { "gpll0_early" },
55
+
.parent_hws = (const struct clk_hw*[]){
56
+
&gpll0_early.clkr.hw
57
+
},
56
58
.num_parents = 1,
57
59
.ops = &clk_alpha_pll_postdiv_ops,
58
60
},
···
83
81
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
84
82
.clkr.hw.init = &(struct clk_init_data){
85
83
.name = "gpll4",
86
-
.parent_names = (const char *[]) { "gpll4_early" },
84
+
.parent_hws = (const struct clk_hw*[]){
85
+
&gpll4_early.clkr.hw
86
+
},
87
87
.num_parents = 1,
88
88
.ops = &clk_alpha_pll_postdiv_ops,
89
89
},
+15
-34
drivers/clk/qcom/gcc-sc7280.c
+15
-34
drivers/clk/qcom/gcc-sc7280.c
···
17
17
#include "clk-rcg.h"
18
18
#include "clk-regmap-divider.h"
19
19
#include "clk-regmap-mux.h"
20
+
#include "clk-regmap-phy-mux.h"
20
21
#include "common.h"
21
22
#include "gdsc.h"
22
23
#include "reset.h"
···
256
255
{ .hw = &gcc_gpll0_out_even.clkr.hw },
257
256
};
258
257
259
-
static const struct parent_map gcc_parent_map_6[] = {
260
-
{ P_PCIE_0_PIPE_CLK, 0 },
261
-
{ P_BI_TCXO, 2 },
262
-
};
263
-
264
-
static const struct clk_parent_data gcc_parent_data_6[] = {
265
-
{ .fw_name = "pcie_0_pipe_clk", .name = "pcie_0_pipe_clk" },
266
-
{ .fw_name = "bi_tcxo" },
267
-
};
268
-
269
-
static const struct parent_map gcc_parent_map_7[] = {
270
-
{ P_PCIE_1_PIPE_CLK, 0 },
271
-
{ P_BI_TCXO, 2 },
272
-
};
273
-
274
-
static const struct clk_parent_data gcc_parent_data_7[] = {
275
-
{ .fw_name = "pcie_1_pipe_clk", .name = "pcie_1_pipe_clk" },
276
-
{ .fw_name = "bi_tcxo" },
277
-
};
278
-
279
258
static const struct parent_map gcc_parent_map_8[] = {
280
259
{ P_BI_TCXO, 0 },
281
260
{ P_GCC_GPLL0_OUT_MAIN, 1 },
···
350
369
{ .hw = &gcc_mss_gpll0_main_div_clk_src.clkr.hw },
351
370
};
352
371
353
-
static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = {
372
+
static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = {
354
373
.reg = 0x6b054,
355
-
.shift = 0,
356
-
.width = 2,
357
-
.parent_map = gcc_parent_map_6,
358
374
.clkr = {
359
375
.hw.init = &(struct clk_init_data){
360
376
.name = "gcc_pcie_0_pipe_clk_src",
361
-
.parent_data = gcc_parent_data_6,
362
-
.num_parents = ARRAY_SIZE(gcc_parent_data_6),
363
-
.ops = &clk_regmap_mux_closest_ops,
377
+
.parent_data = &(const struct clk_parent_data){
378
+
.fw_name = "pcie_0_pipe_clk",
379
+
.name = "pcie_0_pipe_clk",
380
+
},
381
+
.num_parents = 1,
382
+
.ops = &clk_regmap_phy_mux_ops,
364
383
},
365
384
},
366
385
};
367
386
368
-
static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = {
387
+
static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = {
369
388
.reg = 0x8d054,
370
-
.shift = 0,
371
-
.width = 2,
372
-
.parent_map = gcc_parent_map_7,
373
389
.clkr = {
374
390
.hw.init = &(struct clk_init_data){
375
391
.name = "gcc_pcie_1_pipe_clk_src",
376
-
.parent_data = gcc_parent_data_7,
377
-
.num_parents = ARRAY_SIZE(gcc_parent_data_7),
378
-
.ops = &clk_regmap_mux_closest_ops,
392
+
.parent_data = &(const struct clk_parent_data){
393
+
.fw_name = "pcie_1_pipe_clk",
394
+
.name = "pcie_1_pipe_clk",
395
+
},
396
+
.num_parents = 1,
397
+
.ops = &clk_regmap_phy_mux_ops,
379
398
},
380
399
},
381
400
};
+52
-90
drivers/clk/qcom/gcc-sc8280xp.c
+52
-90
drivers/clk/qcom/gcc-sc8280xp.c
···
20
20
#include "clk-regmap.h"
21
21
#include "clk-regmap-divider.h"
22
22
#include "clk-regmap-mux.h"
23
+
#include "clk-regmap-phy-mux.h"
23
24
#include "common.h"
24
25
#include "gdsc.h"
25
26
#include "reset.h"
···
83
82
P_GCC_USB4_PHY_PCIE_PIPEGMUX_CLK_SRC,
84
83
P_GCC_USB4_PHY_PIPEGMUX_CLK_SRC,
85
84
P_GCC_USB4_PHY_SYS_PIPEGMUX_CLK_SRC,
86
-
P_PCIE_2A_PIPE_CLK,
87
-
P_PCIE_2B_PIPE_CLK,
88
-
P_PCIE_3A_PIPE_CLK,
89
-
P_PCIE_3B_PIPE_CLK,
90
-
P_PCIE_4_PIPE_CLK,
91
85
P_QUSB4PHY_1_GCC_USB4_RX0_CLK,
92
86
P_QUSB4PHY_1_GCC_USB4_RX1_CLK,
93
87
P_QUSB4PHY_GCC_USB4_RX0_CLK,
···
345
349
{ .hw = &gcc_gpll7.clkr.hw },
346
350
{ .index = DT_RXC1_REF_CLK },
347
351
{ .hw = &gcc_gpll0_out_even.clkr.hw },
348
-
};
349
-
350
-
static const struct parent_map gcc_parent_map_10[] = {
351
-
{ P_PCIE_2A_PIPE_CLK, 0 },
352
-
{ P_BI_TCXO, 2 },
353
-
};
354
-
355
-
static const struct clk_parent_data gcc_parent_data_10[] = {
356
-
{ .index = DT_PCIE_2A_PIPE_CLK },
357
-
{ .index = DT_BI_TCXO },
358
-
};
359
-
360
-
static const struct parent_map gcc_parent_map_11[] = {
361
-
{ P_PCIE_2B_PIPE_CLK, 0 },
362
-
{ P_BI_TCXO, 2 },
363
-
};
364
-
365
-
static const struct clk_parent_data gcc_parent_data_11[] = {
366
-
{ .index = DT_PCIE_2B_PIPE_CLK },
367
-
{ .index = DT_BI_TCXO },
368
-
};
369
-
370
-
static const struct parent_map gcc_parent_map_12[] = {
371
-
{ P_PCIE_3A_PIPE_CLK, 0 },
372
-
{ P_BI_TCXO, 2 },
373
-
};
374
-
375
-
static const struct clk_parent_data gcc_parent_data_12[] = {
376
-
{ .index = DT_PCIE_3A_PIPE_CLK },
377
-
{ .index = DT_BI_TCXO },
378
-
};
379
-
380
-
static const struct parent_map gcc_parent_map_13[] = {
381
-
{ P_PCIE_3B_PIPE_CLK, 0 },
382
-
{ P_BI_TCXO, 2 },
383
-
};
384
-
385
-
static const struct clk_parent_data gcc_parent_data_13[] = {
386
-
{ .index = DT_PCIE_3B_PIPE_CLK },
387
-
{ .index = DT_BI_TCXO },
388
-
};
389
-
390
-
static const struct parent_map gcc_parent_map_14[] = {
391
-
{ P_PCIE_4_PIPE_CLK, 0 },
392
-
{ P_BI_TCXO, 2 },
393
-
};
394
-
395
-
static const struct clk_parent_data gcc_parent_data_14[] = {
396
-
{ .index = DT_PCIE_4_PIPE_CLK },
397
-
{ .index = DT_BI_TCXO },
398
352
};
399
353
400
354
static const struct parent_map gcc_parent_map_15[] = {
···
687
741
{ .index = DT_USB4_PHY_GCC_USB4_PCIE_PIPE_CLK },
688
742
};
689
743
690
-
static struct clk_regmap_mux gcc_pcie_2a_pipe_clk_src = {
744
+
static struct clk_regmap_phy_mux gcc_pcie_2a_pipe_clk_src = {
691
745
.reg = 0x9d05c,
692
-
.shift = 0,
693
-
.width = 2,
694
-
.parent_map = gcc_parent_map_10,
695
746
.clkr = {
696
747
.hw.init = &(const struct clk_init_data) {
697
748
.name = "gcc_pcie_2a_pipe_clk_src",
698
-
.parent_data = gcc_parent_data_10,
699
-
.num_parents = ARRAY_SIZE(gcc_parent_data_10),
700
-
.ops = &clk_regmap_mux_closest_ops,
749
+
.parent_data = &(const struct clk_parent_data){
750
+
.index = DT_PCIE_2A_PIPE_CLK,
751
+
},
752
+
.num_parents = 1,
753
+
.ops = &clk_regmap_phy_mux_ops,
701
754
},
702
755
},
703
756
};
704
757
705
-
static struct clk_regmap_mux gcc_pcie_2b_pipe_clk_src = {
758
+
static struct clk_regmap_phy_mux gcc_pcie_2b_pipe_clk_src = {
706
759
.reg = 0x9e05c,
707
-
.shift = 0,
708
-
.width = 2,
709
-
.parent_map = gcc_parent_map_11,
710
760
.clkr = {
711
761
.hw.init = &(const struct clk_init_data) {
712
762
.name = "gcc_pcie_2b_pipe_clk_src",
713
-
.parent_data = gcc_parent_data_11,
714
-
.num_parents = ARRAY_SIZE(gcc_parent_data_11),
715
-
.ops = &clk_regmap_mux_closest_ops,
763
+
.parent_data = &(const struct clk_parent_data){
764
+
.index = DT_PCIE_2B_PIPE_CLK,
765
+
},
766
+
.num_parents = 1,
767
+
.ops = &clk_regmap_phy_mux_ops,
716
768
},
717
769
},
718
770
};
719
771
720
-
static struct clk_regmap_mux gcc_pcie_3a_pipe_clk_src = {
772
+
static struct clk_regmap_phy_mux gcc_pcie_3a_pipe_clk_src = {
721
773
.reg = 0xa005c,
722
-
.shift = 0,
723
-
.width = 2,
724
-
.parent_map = gcc_parent_map_12,
725
774
.clkr = {
726
775
.hw.init = &(const struct clk_init_data) {
727
776
.name = "gcc_pcie_3a_pipe_clk_src",
728
-
.parent_data = gcc_parent_data_12,
729
-
.num_parents = ARRAY_SIZE(gcc_parent_data_12),
730
-
.ops = &clk_regmap_mux_closest_ops,
777
+
.parent_data = &(const struct clk_parent_data){
778
+
.index = DT_PCIE_3A_PIPE_CLK,
779
+
},
780
+
.num_parents = 1,
781
+
.ops = &clk_regmap_phy_mux_ops,
731
782
},
732
783
},
733
784
};
734
785
735
-
static struct clk_regmap_mux gcc_pcie_3b_pipe_clk_src = {
786
+
static struct clk_regmap_phy_mux gcc_pcie_3b_pipe_clk_src = {
736
787
.reg = 0xa205c,
737
-
.shift = 0,
738
-
.width = 2,
739
-
.parent_map = gcc_parent_map_13,
740
788
.clkr = {
741
789
.hw.init = &(const struct clk_init_data) {
742
790
.name = "gcc_pcie_3b_pipe_clk_src",
743
-
.parent_data = gcc_parent_data_13,
744
-
.num_parents = ARRAY_SIZE(gcc_parent_data_13),
745
-
.ops = &clk_regmap_mux_closest_ops,
791
+
.parent_data = &(const struct clk_parent_data){
792
+
.index = DT_PCIE_3B_PIPE_CLK,
793
+
},
794
+
.num_parents = 1,
795
+
.ops = &clk_regmap_phy_mux_ops,
746
796
},
747
797
},
748
798
};
749
799
750
-
static struct clk_regmap_mux gcc_pcie_4_pipe_clk_src = {
800
+
static struct clk_regmap_phy_mux gcc_pcie_4_pipe_clk_src = {
751
801
.reg = 0x6b05c,
752
-
.shift = 0,
753
-
.width = 2,
754
-
.parent_map = gcc_parent_map_14,
755
802
.clkr = {
756
803
.hw.init = &(const struct clk_init_data) {
757
804
.name = "gcc_pcie_4_pipe_clk_src",
758
-
.parent_data = gcc_parent_data_14,
759
-
.num_parents = ARRAY_SIZE(gcc_parent_data_14),
760
-
.ops = &clk_regmap_mux_closest_ops,
805
+
.parent_data = &(const struct clk_parent_data){
806
+
.index = DT_PCIE_4_PIPE_CLK,
807
+
},
808
+
.num_parents = 1,
809
+
.ops = &clk_regmap_phy_mux_ops,
761
810
},
762
811
},
763
812
};
···
6748
6807
6749
6808
static struct gdsc pcie_0_tunnel_gdsc = {
6750
6809
.gdscr = 0xa4004,
6810
+
.collapse_ctrl = 0x52128,
6811
+
.collapse_mask = BIT(0),
6751
6812
.pd = {
6752
6813
.name = "pcie_0_tunnel_gdsc",
6753
6814
},
6754
6815
.pwrsts = PWRSTS_OFF_ON,
6816
+
.flags = VOTABLE,
6755
6817
};
6756
6818
6757
6819
static struct gdsc pcie_1_tunnel_gdsc = {
6758
6820
.gdscr = 0x8d004,
6821
+
.collapse_ctrl = 0x52128,
6822
+
.collapse_mask = BIT(1),
6759
6823
.pd = {
6760
6824
.name = "pcie_1_tunnel_gdsc",
6761
6825
},
6762
6826
.pwrsts = PWRSTS_OFF_ON,
6827
+
.flags = VOTABLE,
6763
6828
};
6764
6829
6765
6830
static struct gdsc pcie_2a_gdsc = {
6766
6831
.gdscr = 0x9d004,
6832
+
.collapse_ctrl = 0x52128,
6833
+
.collapse_mask = BIT(2),
6767
6834
.pd = {
6768
6835
.name = "pcie_2a_gdsc",
6769
6836
},
6770
6837
.pwrsts = PWRSTS_OFF_ON,
6838
+
.flags = VOTABLE,
6771
6839
};
6772
6840
6773
6841
static struct gdsc pcie_2b_gdsc = {
6774
6842
.gdscr = 0x9e004,
6843
+
.collapse_ctrl = 0x52128,
6844
+
.collapse_mask = BIT(3),
6775
6845
.pd = {
6776
6846
.name = "pcie_2b_gdsc",
6777
6847
},
6778
6848
.pwrsts = PWRSTS_OFF_ON,
6849
+
.flags = VOTABLE,
6779
6850
};
6780
6851
6781
6852
static struct gdsc pcie_3a_gdsc = {
6782
6853
.gdscr = 0xa0004,
6854
+
.collapse_ctrl = 0x52128,
6855
+
.collapse_mask = BIT(4),
6783
6856
.pd = {
6784
6857
.name = "pcie_3a_gdsc",
6785
6858
},
6786
6859
.pwrsts = PWRSTS_OFF_ON,
6860
+
.flags = VOTABLE,
6787
6861
};
6788
6862
6789
6863
static struct gdsc pcie_3b_gdsc = {
6790
6864
.gdscr = 0xa2004,
6865
+
.collapse_ctrl = 0x52128,
6866
+
.collapse_mask = BIT(5),
6791
6867
.pd = {
6792
6868
.name = "pcie_3b_gdsc",
6793
6869
},
6794
6870
.pwrsts = PWRSTS_OFF_ON,
6871
+
.flags = VOTABLE,
6795
6872
};
6796
6873
6797
6874
static struct gdsc pcie_4_gdsc = {
6798
6875
.gdscr = 0x6b004,
6876
+
.collapse_ctrl = 0x52128,
6877
+
.collapse_mask = BIT(6),
6799
6878
.pd = {
6800
6879
.name = "pcie_4_gdsc",
6801
6880
},
6802
6881
.pwrsts = PWRSTS_OFF_ON,
6882
+
.flags = VOTABLE,
6803
6883
};
6804
6884
6805
6885
static struct gdsc ufs_card_gdsc = {
+1
-1
drivers/clk/qcom/gcc-sm6350.c
+1
-1
drivers/clk/qcom/gcc-sm6350.c
+13
-36
drivers/clk/qcom/gcc-sm8450.c
+13
-36
drivers/clk/qcom/gcc-sm8450.c
···
17
17
#include "clk-regmap.h"
18
18
#include "clk-regmap-divider.h"
19
19
#include "clk-regmap-mux.h"
20
+
#include "clk-regmap-phy-mux.h"
20
21
#include "gdsc.h"
21
22
#include "reset.h"
22
23
···
27
26
P_GCC_GPLL0_OUT_MAIN,
28
27
P_GCC_GPLL4_OUT_MAIN,
29
28
P_GCC_GPLL9_OUT_MAIN,
30
-
P_PCIE_0_PIPE_CLK,
31
29
P_PCIE_1_PHY_AUX_CLK,
32
-
P_PCIE_1_PIPE_CLK,
33
30
P_SLEEP_CLK,
34
31
P_UFS_PHY_RX_SYMBOL_0_CLK,
35
32
P_UFS_PHY_RX_SYMBOL_1_CLK,
···
152
153
{ .fw_name = "bi_tcxo" },
153
154
};
154
155
155
-
static const struct parent_map gcc_parent_map_4[] = {
156
-
{ P_PCIE_0_PIPE_CLK, 0 },
157
-
{ P_BI_TCXO, 2 },
158
-
};
159
-
160
-
static const struct clk_parent_data gcc_parent_data_4[] = {
161
-
{ .fw_name = "pcie_0_pipe_clk", },
162
-
{ .fw_name = "bi_tcxo", },
163
-
};
164
-
165
156
static const struct parent_map gcc_parent_map_5[] = {
166
157
{ P_PCIE_1_PHY_AUX_CLK, 0 },
167
158
{ P_BI_TCXO, 2 },
···
159
170
160
171
static const struct clk_parent_data gcc_parent_data_5[] = {
161
172
{ .fw_name = "pcie_1_phy_aux_clk" },
162
-
{ .fw_name = "bi_tcxo" },
163
-
};
164
-
165
-
static const struct parent_map gcc_parent_map_6[] = {
166
-
{ P_PCIE_1_PIPE_CLK, 0 },
167
-
{ P_BI_TCXO, 2 },
168
-
};
169
-
170
-
static const struct clk_parent_data gcc_parent_data_6[] = {
171
-
{ .fw_name = "pcie_1_pipe_clk" },
172
173
{ .fw_name = "bi_tcxo" },
173
174
};
174
175
···
218
239
{ .fw_name = "bi_tcxo" },
219
240
};
220
241
221
-
static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = {
242
+
static struct clk_regmap_phy_mux gcc_pcie_0_pipe_clk_src = {
222
243
.reg = 0x7b060,
223
-
.shift = 0,
224
-
.width = 2,
225
-
.parent_map = gcc_parent_map_4,
226
244
.clkr = {
227
245
.hw.init = &(struct clk_init_data){
228
246
.name = "gcc_pcie_0_pipe_clk_src",
229
-
.parent_data = gcc_parent_data_4,
230
-
.num_parents = ARRAY_SIZE(gcc_parent_data_4),
231
-
.ops = &clk_regmap_mux_closest_ops,
247
+
.parent_data = &(const struct clk_parent_data){
248
+
.fw_name = "pcie_0_pipe_clk",
249
+
},
250
+
.num_parents = 1,
251
+
.ops = &clk_regmap_phy_mux_ops,
232
252
},
233
253
},
234
254
};
···
247
269
},
248
270
};
249
271
250
-
static struct clk_regmap_mux gcc_pcie_1_pipe_clk_src = {
272
+
static struct clk_regmap_phy_mux gcc_pcie_1_pipe_clk_src = {
251
273
.reg = 0x9d064,
252
-
.shift = 0,
253
-
.width = 2,
254
-
.parent_map = gcc_parent_map_6,
255
274
.clkr = {
256
275
.hw.init = &(struct clk_init_data){
257
276
.name = "gcc_pcie_1_pipe_clk_src",
258
-
.parent_data = gcc_parent_data_6,
259
-
.num_parents = ARRAY_SIZE(gcc_parent_data_6),
260
-
.ops = &clk_regmap_mux_closest_ops,
277
+
.parent_data = &(const struct clk_parent_data){
278
+
.fw_name = "pcie_1_pipe_clk",
279
+
},
280
+
.num_parents = 1,
281
+
.ops = &clk_regmap_phy_mux_ops,
261
282
},
262
283
},
263
284
};
+30
-6
drivers/clk/qcom/gdsc.c
+30
-6
drivers/clk/qcom/gdsc.c
···
132
132
return -ETIMEDOUT;
133
133
}
134
134
135
+
static int gdsc_update_collapse_bit(struct gdsc *sc, bool val)
136
+
{
137
+
u32 reg, mask;
138
+
int ret;
139
+
140
+
if (sc->collapse_mask) {
141
+
reg = sc->collapse_ctrl;
142
+
mask = sc->collapse_mask;
143
+
} else {
144
+
reg = sc->gdscr;
145
+
mask = SW_COLLAPSE_MASK;
146
+
}
147
+
148
+
ret = regmap_update_bits(sc->regmap, reg, mask, val ? mask : 0);
149
+
if (ret)
150
+
return ret;
151
+
152
+
return 0;
153
+
}
154
+
135
155
static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status)
136
156
{
137
157
int ret;
138
-
u32 val = (status == GDSC_ON) ? 0 : SW_COLLAPSE_MASK;
139
158
140
159
if (status == GDSC_ON && sc->rsupply) {
141
160
ret = regulator_enable(sc->rsupply);
···
162
143
return ret;
163
144
}
164
145
165
-
ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);
166
-
if (ret)
167
-
return ret;
146
+
ret = gdsc_update_collapse_bit(sc, status == GDSC_OFF);
168
147
169
148
/* If disabling votable gdscs, don't poll on status */
170
149
if ((sc->flags & VOTABLE) && status == GDSC_OFF) {
···
437
420
return ret;
438
421
}
439
422
423
+
/* ...and the power-domain */
424
+
ret = gdsc_pm_runtime_get(sc);
425
+
if (ret) {
426
+
if (sc->rsupply)
427
+
regulator_disable(sc->rsupply);
428
+
return ret;
429
+
}
430
+
440
431
/*
441
432
* Votable GDSCs can be ON due to Vote from other masters.
442
433
* If a Votable GDSC is ON, make sure we have a Vote.
443
434
*/
444
435
if (sc->flags & VOTABLE) {
445
-
ret = regmap_update_bits(sc->regmap, sc->gdscr,
446
-
SW_COLLAPSE_MASK, val);
436
+
ret = gdsc_update_collapse_bit(sc, false);
447
437
if (ret)
448
438
return ret;
449
439
}
+4
drivers/clk/qcom/gdsc.h
+4
drivers/clk/qcom/gdsc.h
···
18
18
* @pd: generic power domain
19
19
* @regmap: regmap for MMIO accesses
20
20
* @gdscr: gsdc control register
21
+
* @collapse_ctrl: APCS collapse-vote register
22
+
* @collapse_mask: APCS collapse-vote mask
21
23
* @gds_hw_ctrl: gds_hw_ctrl register
22
24
* @cxcs: offsets of branch registers to toggle mem/periph bits in
23
25
* @cxc_count: number of @cxcs
···
37
35
struct generic_pm_domain *parent;
38
36
struct regmap *regmap;
39
37
unsigned int gdscr;
38
+
unsigned int collapse_ctrl;
39
+
unsigned int collapse_mask;
40
40
unsigned int gds_hw_ctrl;
41
41
unsigned int clamp_io_ctrl;
42
42
unsigned int *cxcs;
+637
drivers/clk/qcom/gpucc-sm8350.c
+637
drivers/clk/qcom/gpucc-sm8350.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
4
+
* Copyright (c) 2022, Linaro Limited
5
+
*/
6
+
7
+
#include <linux/clk.h>
8
+
#include <linux/err.h>
9
+
#include <linux/kernel.h>
10
+
#include <linux/module.h>
11
+
#include <linux/of_device.h>
12
+
#include <linux/of.h>
13
+
#include <linux/regmap.h>
14
+
15
+
#include <dt-bindings/clock/qcom,gpucc-sm8350.h>
16
+
17
+
#include "clk-alpha-pll.h"
18
+
#include "clk-branch.h"
19
+
#include "clk-pll.h"
20
+
#include "clk-rcg.h"
21
+
#include "clk-regmap.h"
22
+
#include "common.h"
23
+
#include "clk-regmap-mux.h"
24
+
#include "clk-regmap-divider.h"
25
+
#include "gdsc.h"
26
+
#include "reset.h"
27
+
28
+
enum {
29
+
P_BI_TCXO,
30
+
P_GPLL0_OUT_MAIN,
31
+
P_GPLL0_OUT_MAIN_DIV,
32
+
P_GPU_CC_PLL0_OUT_MAIN,
33
+
P_GPU_CC_PLL1_OUT_MAIN,
34
+
};
35
+
36
+
static struct pll_vco lucid_5lpe_vco[] = {
37
+
{ 249600000, 1750000000, 0 },
38
+
};
39
+
40
+
static const struct alpha_pll_config gpu_cc_pll0_config = {
41
+
.l = 0x18,
42
+
.alpha = 0x6000,
43
+
.config_ctl_val = 0x20485699,
44
+
.config_ctl_hi_val = 0x00002261,
45
+
.config_ctl_hi1_val = 0x2a9a699c,
46
+
.test_ctl_val = 0x00000000,
47
+
.test_ctl_hi_val = 0x00000000,
48
+
.test_ctl_hi1_val = 0x01800000,
49
+
.user_ctl_val = 0x00000000,
50
+
.user_ctl_hi_val = 0x00000805,
51
+
.user_ctl_hi1_val = 0x00000000,
52
+
};
53
+
54
+
static const struct clk_parent_data gpu_cc_parent = {
55
+
.fw_name = "bi_tcxo",
56
+
};
57
+
58
+
static struct clk_alpha_pll gpu_cc_pll0 = {
59
+
.offset = 0x0,
60
+
.vco_table = lucid_5lpe_vco,
61
+
.num_vco = ARRAY_SIZE(lucid_5lpe_vco),
62
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
63
+
.clkr = {
64
+
.hw.init = &(const struct clk_init_data){
65
+
.name = "gpu_cc_pll0",
66
+
.parent_data = &gpu_cc_parent,
67
+
.num_parents = 1,
68
+
.ops = &clk_alpha_pll_lucid_5lpe_ops,
69
+
},
70
+
},
71
+
};
72
+
73
+
static const struct alpha_pll_config gpu_cc_pll1_config = {
74
+
.l = 0x1a,
75
+
.alpha = 0xaaa,
76
+
.config_ctl_val = 0x20485699,
77
+
.config_ctl_hi_val = 0x00002261,
78
+
.config_ctl_hi1_val = 0x2a9a699c,
79
+
.test_ctl_val = 0x00000000,
80
+
.test_ctl_hi_val = 0x00000000,
81
+
.test_ctl_hi1_val = 0x01800000,
82
+
.user_ctl_val = 0x00000000,
83
+
.user_ctl_hi_val = 0x00000805,
84
+
.user_ctl_hi1_val = 0x00000000,
85
+
};
86
+
87
+
static struct clk_alpha_pll gpu_cc_pll1 = {
88
+
.offset = 0x100,
89
+
.vco_table = lucid_5lpe_vco,
90
+
.num_vco = ARRAY_SIZE(lucid_5lpe_vco),
91
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
92
+
.clkr = {
93
+
.hw.init = &(struct clk_init_data){
94
+
.name = "gpu_cc_pll1",
95
+
.parent_data = &gpu_cc_parent,
96
+
.num_parents = 1,
97
+
.ops = &clk_alpha_pll_lucid_5lpe_ops,
98
+
},
99
+
},
100
+
};
101
+
102
+
static const struct parent_map gpu_cc_parent_map_0[] = {
103
+
{ P_BI_TCXO, 0 },
104
+
{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
105
+
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
106
+
{ P_GPLL0_OUT_MAIN, 5 },
107
+
{ P_GPLL0_OUT_MAIN_DIV, 6 },
108
+
};
109
+
110
+
static const struct clk_parent_data gpu_cc_parent_data_0[] = {
111
+
{ .fw_name = "bi_tcxo" },
112
+
{ .hw = &gpu_cc_pll0.clkr.hw },
113
+
{ .hw = &gpu_cc_pll1.clkr.hw },
114
+
{ .fw_name = "gcc_gpu_gpll0_clk_src" },
115
+
{ .fw_name = "gcc_gpu_gpll0_div_clk_src" },
116
+
};
117
+
118
+
static const struct parent_map gpu_cc_parent_map_1[] = {
119
+
{ P_BI_TCXO, 0 },
120
+
{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
121
+
{ P_GPLL0_OUT_MAIN, 5 },
122
+
{ P_GPLL0_OUT_MAIN_DIV, 6 },
123
+
};
124
+
125
+
static const struct clk_parent_data gpu_cc_parent_data_1[] = {
126
+
{ .fw_name = "bi_tcxo" },
127
+
{ .hw = &gpu_cc_pll1.clkr.hw },
128
+
{ .fw_name = "gcc_gpu_gpll0_clk_src" },
129
+
{ .fw_name = "gcc_gpu_gpll0_div_clk_src" },
130
+
};
131
+
132
+
static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
133
+
F(19200000, P_BI_TCXO, 1, 0, 0),
134
+
F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
135
+
F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),
136
+
{ }
137
+
};
138
+
139
+
static struct clk_rcg2 gpu_cc_gmu_clk_src = {
140
+
.cmd_rcgr = 0x1120,
141
+
.mnd_width = 0,
142
+
.hid_width = 5,
143
+
.parent_map = gpu_cc_parent_map_0,
144
+
.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
145
+
.clkr.hw.init = &(struct clk_init_data){
146
+
.name = "gpu_cc_gmu_clk_src",
147
+
.parent_data = gpu_cc_parent_data_0,
148
+
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
149
+
.flags = CLK_SET_RATE_PARENT,
150
+
.ops = &clk_rcg2_ops,
151
+
},
152
+
};
153
+
154
+
static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = {
155
+
F(150000000, P_GPLL0_OUT_MAIN_DIV, 2, 0, 0),
156
+
F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
157
+
F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
158
+
{ }
159
+
};
160
+
161
+
static struct clk_rcg2 gpu_cc_hub_clk_src = {
162
+
.cmd_rcgr = 0x117c,
163
+
.mnd_width = 0,
164
+
.hid_width = 5,
165
+
.parent_map = gpu_cc_parent_map_1,
166
+
.freq_tbl = ftbl_gpu_cc_hub_clk_src,
167
+
.clkr.hw.init = &(struct clk_init_data){
168
+
.name = "gpu_cc_hub_clk_src",
169
+
.parent_data = gpu_cc_parent_data_1,
170
+
.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
171
+
.flags = CLK_SET_RATE_PARENT,
172
+
.ops = &clk_rcg2_ops,
173
+
},
174
+
};
175
+
176
+
static struct clk_regmap_div gpu_cc_hub_ahb_div_clk_src = {
177
+
.reg = 0x11c0,
178
+
.shift = 0,
179
+
.width = 4,
180
+
.clkr.hw.init = &(struct clk_init_data) {
181
+
.name = "gpu_cc_hub_ahb_div_clk_src",
182
+
.parent_hws = (const struct clk_hw*[]){
183
+
&gpu_cc_hub_clk_src.clkr.hw,
184
+
},
185
+
.num_parents = 1,
186
+
.flags = CLK_SET_RATE_PARENT,
187
+
.ops = &clk_regmap_div_ro_ops,
188
+
},
189
+
};
190
+
191
+
static struct clk_regmap_div gpu_cc_hub_cx_int_div_clk_src = {
192
+
.reg = 0x11bc,
193
+
.shift = 0,
194
+
.width = 4,
195
+
.clkr.hw.init = &(struct clk_init_data) {
196
+
.name = "gpu_cc_hub_cx_int_div_clk_src",
197
+
.parent_hws = (const struct clk_hw*[]){
198
+
&gpu_cc_hub_clk_src.clkr.hw,
199
+
},
200
+
.num_parents = 1,
201
+
.flags = CLK_SET_RATE_PARENT,
202
+
.ops = &clk_regmap_div_ro_ops,
203
+
},
204
+
};
205
+
206
+
static struct clk_branch gpu_cc_ahb_clk = {
207
+
.halt_reg = 0x1078,
208
+
.halt_check = BRANCH_HALT_DELAY,
209
+
.clkr = {
210
+
.enable_reg = 0x1078,
211
+
.enable_mask = BIT(0),
212
+
.hw.init = &(struct clk_init_data){
213
+
.name = "gpu_cc_ahb_clk",
214
+
.parent_hws = (const struct clk_hw*[]){
215
+
&gpu_cc_hub_ahb_div_clk_src.clkr.hw,
216
+
},
217
+
.num_parents = 1,
218
+
.flags = CLK_SET_RATE_PARENT,
219
+
.ops = &clk_branch2_ops,
220
+
},
221
+
},
222
+
};
223
+
224
+
static struct clk_branch gpu_cc_cb_clk = {
225
+
.halt_reg = 0x1170,
226
+
.halt_check = BRANCH_HALT,
227
+
.clkr = {
228
+
.enable_reg = 0x1170,
229
+
.enable_mask = BIT(0),
230
+
.hw.init = &(struct clk_init_data){
231
+
.name = "gpu_cc_cb_clk",
232
+
.ops = &clk_branch2_ops,
233
+
},
234
+
},
235
+
};
236
+
237
+
static struct clk_branch gpu_cc_crc_ahb_clk = {
238
+
.halt_reg = 0x107c,
239
+
.halt_check = BRANCH_HALT_VOTED,
240
+
.clkr = {
241
+
.enable_reg = 0x107c,
242
+
.enable_mask = BIT(0),
243
+
.hw.init = &(struct clk_init_data){
244
+
.name = "gpu_cc_crc_ahb_clk",
245
+
.parent_hws = (const struct clk_hw*[]){
246
+
&gpu_cc_hub_ahb_div_clk_src.clkr.hw,
247
+
},
248
+
.num_parents = 1,
249
+
.flags = CLK_SET_RATE_PARENT,
250
+
.ops = &clk_branch2_ops,
251
+
},
252
+
},
253
+
};
254
+
255
+
static struct clk_branch gpu_cc_cx_apb_clk = {
256
+
.halt_reg = 0x1088,
257
+
.halt_check = BRANCH_HALT_VOTED,
258
+
.clkr = {
259
+
.enable_reg = 0x1088,
260
+
.enable_mask = BIT(0),
261
+
.hw.init = &(struct clk_init_data){
262
+
.name = "gpu_cc_cx_apb_clk",
263
+
.ops = &clk_branch2_ops,
264
+
},
265
+
},
266
+
};
267
+
268
+
static struct clk_branch gpu_cc_cx_gmu_clk = {
269
+
.halt_reg = 0x1098,
270
+
.halt_check = BRANCH_HALT,
271
+
.clkr = {
272
+
.enable_reg = 0x1098,
273
+
.enable_mask = BIT(0),
274
+
.hw.init = &(struct clk_init_data){
275
+
.name = "gpu_cc_cx_gmu_clk",
276
+
.parent_hws = (const struct clk_hw*[]){
277
+
&gpu_cc_gmu_clk_src.clkr.hw,
278
+
},
279
+
.num_parents = 1,
280
+
.flags = CLK_SET_RATE_PARENT,
281
+
.ops = &clk_branch2_aon_ops,
282
+
},
283
+
},
284
+
};
285
+
286
+
static struct clk_branch gpu_cc_cx_qdss_at_clk = {
287
+
.halt_reg = 0x1080,
288
+
.halt_check = BRANCH_HALT_VOTED,
289
+
.clkr = {
290
+
.enable_reg = 0x1080,
291
+
.enable_mask = BIT(0),
292
+
.hw.init = &(struct clk_init_data){
293
+
.name = "gpu_cc_cx_qdss_at_clk",
294
+
.ops = &clk_branch2_ops,
295
+
},
296
+
},
297
+
};
298
+
299
+
static struct clk_branch gpu_cc_cx_qdss_trig_clk = {
300
+
.halt_reg = 0x1094,
301
+
.halt_check = BRANCH_HALT_VOTED,
302
+
.clkr = {
303
+
.enable_reg = 0x1094,
304
+
.enable_mask = BIT(0),
305
+
.hw.init = &(struct clk_init_data){
306
+
.name = "gpu_cc_cx_qdss_trig_clk",
307
+
.ops = &clk_branch2_ops,
308
+
},
309
+
},
310
+
};
311
+
312
+
static struct clk_branch gpu_cc_cx_qdss_tsctr_clk = {
313
+
.halt_reg = 0x1084,
314
+
.halt_check = BRANCH_HALT_VOTED,
315
+
.clkr = {
316
+
.enable_reg = 0x1084,
317
+
.enable_mask = BIT(0),
318
+
.hw.init = &(struct clk_init_data){
319
+
.name = "gpu_cc_cx_qdss_tsctr_clk",
320
+
.ops = &clk_branch2_ops,
321
+
},
322
+
},
323
+
};
324
+
325
+
static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
326
+
.halt_reg = 0x108c,
327
+
.halt_check = BRANCH_HALT_VOTED,
328
+
.clkr = {
329
+
.enable_reg = 0x108c,
330
+
.enable_mask = BIT(0),
331
+
.hw.init = &(struct clk_init_data){
332
+
.name = "gpu_cc_cx_snoc_dvm_clk",
333
+
.ops = &clk_branch2_ops,
334
+
},
335
+
},
336
+
};
337
+
338
+
static struct clk_branch gpu_cc_cxo_aon_clk = {
339
+
.halt_reg = 0x1004,
340
+
.halt_check = BRANCH_HALT_VOTED,
341
+
.clkr = {
342
+
.enable_reg = 0x1004,
343
+
.enable_mask = BIT(0),
344
+
.hw.init = &(struct clk_init_data){
345
+
.name = "gpu_cc_cxo_aon_clk",
346
+
.ops = &clk_branch2_ops,
347
+
},
348
+
},
349
+
};
350
+
351
+
static struct clk_branch gpu_cc_cxo_clk = {
352
+
.halt_reg = 0x109c,
353
+
.halt_check = BRANCH_HALT,
354
+
.clkr = {
355
+
.enable_reg = 0x109c,
356
+
.enable_mask = BIT(0),
357
+
.hw.init = &(struct clk_init_data){
358
+
.name = "gpu_cc_cxo_clk",
359
+
.ops = &clk_branch2_ops,
360
+
},
361
+
},
362
+
};
363
+
364
+
static struct clk_branch gpu_cc_freq_measure_clk = {
365
+
.halt_reg = 0x120c,
366
+
.halt_check = BRANCH_HALT,
367
+
.clkr = {
368
+
.enable_reg = 0x120c,
369
+
.enable_mask = BIT(0),
370
+
.hw.init = &(struct clk_init_data){
371
+
.name = "gpu_cc_freq_measure_clk",
372
+
.ops = &clk_branch2_ops,
373
+
},
374
+
},
375
+
};
376
+
377
+
static struct clk_branch gpu_cc_gx_gmu_clk = {
378
+
.halt_reg = 0x1064,
379
+
.halt_check = BRANCH_HALT,
380
+
.clkr = {
381
+
.enable_reg = 0x1064,
382
+
.enable_mask = BIT(0),
383
+
.hw.init = &(struct clk_init_data){
384
+
.name = "gpu_cc_gx_gmu_clk",
385
+
.parent_hws = (const struct clk_hw*[]){
386
+
&gpu_cc_gmu_clk_src.clkr.hw,
387
+
},
388
+
.num_parents = 1,
389
+
.flags = CLK_SET_RATE_PARENT,
390
+
.ops = &clk_branch2_ops,
391
+
},
392
+
},
393
+
};
394
+
395
+
static struct clk_branch gpu_cc_gx_qdss_tsctr_clk = {
396
+
.halt_reg = 0x105c,
397
+
.halt_check = BRANCH_HALT_VOTED,
398
+
.clkr = {
399
+
.enable_reg = 0x105c,
400
+
.enable_mask = BIT(0),
401
+
.hw.init = &(struct clk_init_data){
402
+
.name = "gpu_cc_gx_qdss_tsctr_clk",
403
+
.ops = &clk_branch2_ops,
404
+
},
405
+
},
406
+
};
407
+
408
+
static struct clk_branch gpu_cc_gx_vsense_clk = {
409
+
.halt_reg = 0x1058,
410
+
.halt_check = BRANCH_HALT_VOTED,
411
+
.clkr = {
412
+
.enable_reg = 0x1058,
413
+
.enable_mask = BIT(0),
414
+
.hw.init = &(struct clk_init_data){
415
+
.name = "gpu_cc_gx_vsense_clk",
416
+
.ops = &clk_branch2_ops,
417
+
},
418
+
},
419
+
};
420
+
421
+
static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
422
+
.halt_reg = 0x5000,
423
+
.halt_check = BRANCH_HALT_VOTED,
424
+
.clkr = {
425
+
.enable_reg = 0x5000,
426
+
.enable_mask = BIT(0),
427
+
.hw.init = &(struct clk_init_data){
428
+
.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
429
+
.ops = &clk_branch2_ops,
430
+
},
431
+
},
432
+
};
433
+
434
+
static struct clk_branch gpu_cc_hub_aon_clk = {
435
+
.halt_reg = 0x1178,
436
+
.halt_check = BRANCH_HALT,
437
+
.clkr = {
438
+
.enable_reg = 0x1178,
439
+
.enable_mask = BIT(0),
440
+
.hw.init = &(struct clk_init_data){
441
+
.name = "gpu_cc_hub_aon_clk",
442
+
.parent_hws = (const struct clk_hw*[]){
443
+
&gpu_cc_hub_clk_src.clkr.hw,
444
+
},
445
+
.num_parents = 1,
446
+
.flags = CLK_SET_RATE_PARENT,
447
+
.ops = &clk_branch2_aon_ops,
448
+
},
449
+
},
450
+
};
451
+
452
+
static struct clk_branch gpu_cc_hub_cx_int_clk = {
453
+
.halt_reg = 0x1204,
454
+
.halt_check = BRANCH_HALT,
455
+
.clkr = {
456
+
.enable_reg = 0x1204,
457
+
.enable_mask = BIT(0),
458
+
.hw.init = &(struct clk_init_data){
459
+
.name = "gpu_cc_hub_cx_int_clk",
460
+
.parent_hws = (const struct clk_hw*[]){
461
+
&gpu_cc_hub_cx_int_div_clk_src.clkr.hw,
462
+
},
463
+
.num_parents = 1,
464
+
.flags = CLK_SET_RATE_PARENT,
465
+
.ops = &clk_branch2_aon_ops,
466
+
},
467
+
},
468
+
};
469
+
470
+
static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk = {
471
+
.halt_reg = 0x802c,
472
+
.halt_check = BRANCH_HALT,
473
+
.clkr = {
474
+
.enable_reg = 0x802c,
475
+
.enable_mask = BIT(0),
476
+
.hw.init = &(struct clk_init_data){
477
+
.name = "gpu_cc_mnd1x_0_gfx3d_clk",
478
+
.ops = &clk_branch2_ops,
479
+
},
480
+
},
481
+
};
482
+
483
+
static struct clk_branch gpu_cc_mnd1x_1_gfx3d_clk = {
484
+
.halt_reg = 0x8030,
485
+
.halt_check = BRANCH_HALT,
486
+
.clkr = {
487
+
.enable_reg = 0x8030,
488
+
.enable_mask = BIT(0),
489
+
.hw.init = &(struct clk_init_data){
490
+
.name = "gpu_cc_mnd1x_1_gfx3d_clk",
491
+
.ops = &clk_branch2_ops,
492
+
},
493
+
},
494
+
};
495
+
496
+
static struct clk_branch gpu_cc_sleep_clk = {
497
+
.halt_reg = 0x1090,
498
+
.halt_check = BRANCH_HALT_VOTED,
499
+
.clkr = {
500
+
.enable_reg = 0x1090,
501
+
.enable_mask = BIT(0),
502
+
.hw.init = &(struct clk_init_data){
503
+
.name = "gpu_cc_sleep_clk",
504
+
.ops = &clk_branch2_ops,
505
+
},
506
+
},
507
+
};
508
+
509
+
static struct gdsc gpu_cx_gdsc = {
510
+
.gdscr = 0x106c,
511
+
.gds_hw_ctrl = 0x1540,
512
+
.pd = {
513
+
.name = "gpu_cx_gdsc",
514
+
},
515
+
.pwrsts = PWRSTS_OFF_ON,
516
+
.flags = VOTABLE,
517
+
};
518
+
519
+
static struct gdsc gpu_gx_gdsc = {
520
+
.gdscr = 0x100c,
521
+
.clamp_io_ctrl = 0x1508,
522
+
.pd = {
523
+
.name = "gpu_gx_gdsc",
524
+
.power_on = gdsc_gx_do_nothing_enable,
525
+
},
526
+
.pwrsts = PWRSTS_OFF_ON,
527
+
.flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR,
528
+
};
529
+
530
+
static struct clk_regmap *gpu_cc_sm8350_clocks[] = {
531
+
[GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
532
+
[GPU_CC_CB_CLK] = &gpu_cc_cb_clk.clkr,
533
+
[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
534
+
[GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr,
535
+
[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
536
+
[GPU_CC_CX_QDSS_AT_CLK] = &gpu_cc_cx_qdss_at_clk.clkr,
537
+
[GPU_CC_CX_QDSS_TRIG_CLK] = &gpu_cc_cx_qdss_trig_clk.clkr,
538
+
[GPU_CC_CX_QDSS_TSCTR_CLK] = &gpu_cc_cx_qdss_tsctr_clk.clkr,
539
+
[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
540
+
[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
541
+
[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
542
+
[GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr,
543
+
[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
544
+
[GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr,
545
+
[GPU_CC_GX_QDSS_TSCTR_CLK] = &gpu_cc_gx_qdss_tsctr_clk.clkr,
546
+
[GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr,
547
+
[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
548
+
[GPU_CC_HUB_AHB_DIV_CLK_SRC] = &gpu_cc_hub_ahb_div_clk_src.clkr,
549
+
[GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
550
+
[GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr,
551
+
[GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr,
552
+
[GPU_CC_HUB_CX_INT_DIV_CLK_SRC] = &gpu_cc_hub_cx_int_div_clk_src.clkr,
553
+
[GPU_CC_MND1X_0_GFX3D_CLK] = &gpu_cc_mnd1x_0_gfx3d_clk.clkr,
554
+
[GPU_CC_MND1X_1_GFX3D_CLK] = &gpu_cc_mnd1x_1_gfx3d_clk.clkr,
555
+
[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
556
+
[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
557
+
[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
558
+
};
559
+
560
+
static const struct qcom_reset_map gpu_cc_sm8350_resets[] = {
561
+
[GPUCC_GPU_CC_ACD_BCR] = { 0x1160 },
562
+
[GPUCC_GPU_CC_CB_BCR] = { 0x116c },
563
+
[GPUCC_GPU_CC_CX_BCR] = { 0x1068 },
564
+
[GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x1174 },
565
+
[GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x10a0 },
566
+
[GPUCC_GPU_CC_GMU_BCR] = { 0x111c },
567
+
[GPUCC_GPU_CC_GX_BCR] = { 0x1008 },
568
+
[GPUCC_GPU_CC_XO_BCR] = { 0x1000 },
569
+
};
570
+
571
+
static struct gdsc *gpu_cc_sm8350_gdscs[] = {
572
+
[GPU_CX_GDSC] = &gpu_cx_gdsc,
573
+
[GPU_GX_GDSC] = &gpu_gx_gdsc,
574
+
};
575
+
576
+
static const struct regmap_config gpu_cc_sm8350_regmap_config = {
577
+
.reg_bits = 32,
578
+
.reg_stride = 4,
579
+
.val_bits = 32,
580
+
.max_register = 0x8030,
581
+
.fast_io = true,
582
+
};
583
+
584
+
static const struct qcom_cc_desc gpu_cc_sm8350_desc = {
585
+
.config = &gpu_cc_sm8350_regmap_config,
586
+
.clks = gpu_cc_sm8350_clocks,
587
+
.num_clks = ARRAY_SIZE(gpu_cc_sm8350_clocks),
588
+
.resets = gpu_cc_sm8350_resets,
589
+
.num_resets = ARRAY_SIZE(gpu_cc_sm8350_resets),
590
+
.gdscs = gpu_cc_sm8350_gdscs,
591
+
.num_gdscs = ARRAY_SIZE(gpu_cc_sm8350_gdscs),
592
+
};
593
+
594
+
static int gpu_cc_sm8350_probe(struct platform_device *pdev)
595
+
{
596
+
struct regmap *regmap;
597
+
598
+
regmap = qcom_cc_map(pdev, &gpu_cc_sm8350_desc);
599
+
if (IS_ERR(regmap)) {
600
+
dev_err(&pdev->dev, "Failed to map gpu cc registers\n");
601
+
return PTR_ERR(regmap);
602
+
}
603
+
604
+
clk_lucid_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
605
+
clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
606
+
607
+
return qcom_cc_really_probe(pdev, &gpu_cc_sm8350_desc, regmap);
608
+
}
609
+
610
+
static const struct of_device_id gpu_cc_sm8350_match_table[] = {
611
+
{ .compatible = "qcom,sm8350-gpucc" },
612
+
{ }
613
+
};
614
+
MODULE_DEVICE_TABLE(of, gpu_cc_sm8350_match_table);
615
+
616
+
static struct platform_driver gpu_cc_sm8350_driver = {
617
+
.probe = gpu_cc_sm8350_probe,
618
+
.driver = {
619
+
.name = "sm8350-gpucc",
620
+
.of_match_table = gpu_cc_sm8350_match_table,
621
+
},
622
+
};
623
+
624
+
static int __init gpu_cc_sm8350_init(void)
625
+
{
626
+
return platform_driver_register(&gpu_cc_sm8350_driver);
627
+
}
628
+
subsys_initcall(gpu_cc_sm8350_init);
629
+
630
+
static void __exit gpu_cc_sm8350_exit(void)
631
+
{
632
+
platform_driver_unregister(&gpu_cc_sm8350_driver);
633
+
}
634
+
module_exit(gpu_cc_sm8350_exit);
635
+
636
+
MODULE_DESCRIPTION("QTI GPU_CC SM8350 Driver");
637
+
MODULE_LICENSE("GPL v2");
+8
drivers/clk/qcom/krait-cc.c
+8
drivers/clk/qcom/krait-cc.c
···
139
139
mux->hw.init = &init;
140
140
mux->safe_sel = 0;
141
141
142
+
/* Checking for qcom,krait-cc-v1 or qcom,krait-cc-v2 is not
143
+
* enough to limit this to apq/ipq8064. Directly check machine
144
+
* compatible to correctly handle this errata.
145
+
*/
146
+
if (of_machine_is_compatible("qcom,ipq8064") ||
147
+
of_machine_is_compatible("qcom,apq8064"))
148
+
mux->disable_sec_src_gating = true;
149
+
142
150
init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
143
151
if (!init.name)
144
152
return -ENOMEM;
+654
-398
drivers/clk/qcom/mmcc-msm8996.c
+654
-398
drivers/clk/qcom/mmcc-msm8996.c
···
45
45
P_MMPLL4,
46
46
};
47
47
48
-
static const struct parent_map mmss_xo_hdmi_map[] = {
49
-
{ P_XO, 0 },
50
-
{ P_HDMIPLL, 1 }
51
-
};
52
-
53
-
static const char * const mmss_xo_hdmi[] = {
54
-
"xo",
55
-
"hdmipll"
56
-
};
57
-
58
-
static const struct parent_map mmss_xo_dsi0pll_dsi1pll_map[] = {
59
-
{ P_XO, 0 },
60
-
{ P_DSI0PLL, 1 },
61
-
{ P_DSI1PLL, 2 }
62
-
};
63
-
64
-
static const char * const mmss_xo_dsi0pll_dsi1pll[] = {
65
-
"xo",
66
-
"dsi0pll",
67
-
"dsi1pll"
68
-
};
69
-
70
-
static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = {
71
-
{ P_XO, 0 },
72
-
{ P_GPLL0, 5 },
73
-
{ P_GPLL0_DIV, 6 }
74
-
};
75
-
76
-
static const char * const mmss_xo_gpll0_gpll0_div[] = {
77
-
"xo",
78
-
"gpll0",
79
-
"gpll0_div"
80
-
};
81
-
82
-
static const struct parent_map mmss_xo_dsibyte_map[] = {
83
-
{ P_XO, 0 },
84
-
{ P_DSI0PLL_BYTE, 1 },
85
-
{ P_DSI1PLL_BYTE, 2 }
86
-
};
87
-
88
-
static const char * const mmss_xo_dsibyte[] = {
89
-
"xo",
90
-
"dsi0pllbyte",
91
-
"dsi1pllbyte"
92
-
};
93
-
94
-
static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = {
95
-
{ P_XO, 0 },
96
-
{ P_MMPLL0, 1 },
97
-
{ P_GPLL0, 5 },
98
-
{ P_GPLL0_DIV, 6 }
99
-
};
100
-
101
-
static const char * const mmss_xo_mmpll0_gpll0_gpll0_div[] = {
102
-
"xo",
103
-
"mmpll0",
104
-
"gpll0",
105
-
"gpll0_div"
106
-
};
107
-
108
-
static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = {
109
-
{ P_XO, 0 },
110
-
{ P_MMPLL0, 1 },
111
-
{ P_MMPLL1, 2 },
112
-
{ P_GPLL0, 5 },
113
-
{ P_GPLL0_DIV, 6 }
114
-
};
115
-
116
-
static const char * const mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = {
117
-
"xo",
118
-
"mmpll0",
119
-
"mmpll1",
120
-
"gpll0",
121
-
"gpll0_div"
122
-
};
123
-
124
-
static const struct parent_map mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map[] = {
125
-
{ P_XO, 0 },
126
-
{ P_MMPLL0, 1 },
127
-
{ P_MMPLL3, 3 },
128
-
{ P_GPLL0, 5 },
129
-
{ P_GPLL0_DIV, 6 }
130
-
};
131
-
132
-
static const char * const mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div[] = {
133
-
"xo",
134
-
"mmpll0",
135
-
"mmpll3",
136
-
"gpll0",
137
-
"gpll0_div"
138
-
};
139
-
140
-
static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = {
141
-
{ P_XO, 0 },
142
-
{ P_MMPLL0, 1 },
143
-
{ P_MMPLL5, 2 },
144
-
{ P_GPLL0, 5 },
145
-
{ P_GPLL0_DIV, 6 }
146
-
};
147
-
148
-
static const char * const mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = {
149
-
"xo",
150
-
"mmpll0",
151
-
"mmpll5",
152
-
"gpll0",
153
-
"gpll0_div"
154
-
};
155
-
156
-
static const struct parent_map mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map[] = {
157
-
{ P_XO, 0 },
158
-
{ P_MMPLL0, 1 },
159
-
{ P_MMPLL4, 3 },
160
-
{ P_GPLL0, 5 },
161
-
{ P_GPLL0_DIV, 6 }
162
-
};
163
-
164
-
static const char * const mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div[] = {
165
-
"xo",
166
-
"mmpll0",
167
-
"mmpll4",
168
-
"gpll0",
169
-
"gpll0_div"
170
-
};
171
-
172
-
static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map[] = {
173
-
{ P_XO, 0 },
174
-
{ P_MMPLL0, 1 },
175
-
{ P_MMPLL9, 2 },
176
-
{ P_MMPLL2, 3 },
177
-
{ P_MMPLL8, 4 },
178
-
{ P_GPLL0, 5 }
179
-
};
180
-
181
-
static const char * const mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0[] = {
182
-
"xo",
183
-
"mmpll0",
184
-
"mmpll9",
185
-
"mmpll2",
186
-
"mmpll8",
187
-
"gpll0"
188
-
};
189
-
190
-
static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map[] = {
191
-
{ P_XO, 0 },
192
-
{ P_MMPLL0, 1 },
193
-
{ P_MMPLL9, 2 },
194
-
{ P_MMPLL2, 3 },
195
-
{ P_MMPLL8, 4 },
196
-
{ P_GPLL0, 5 },
197
-
{ P_GPLL0_DIV, 6 }
198
-
};
199
-
200
-
static const char * const mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div[] = {
201
-
"xo",
202
-
"mmpll0",
203
-
"mmpll9",
204
-
"mmpll2",
205
-
"mmpll8",
206
-
"gpll0",
207
-
"gpll0_div"
208
-
};
209
-
210
-
static const struct parent_map mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map[] = {
211
-
{ P_XO, 0 },
212
-
{ P_MMPLL0, 1 },
213
-
{ P_MMPLL1, 2 },
214
-
{ P_MMPLL4, 3 },
215
-
{ P_MMPLL3, 4 },
216
-
{ P_GPLL0, 5 },
217
-
{ P_GPLL0_DIV, 6 }
218
-
};
219
-
220
-
static const char * const mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div[] = {
221
-
"xo",
222
-
"mmpll0",
223
-
"mmpll1",
224
-
"mmpll4",
225
-
"mmpll3",
226
-
"gpll0",
227
-
"gpll0_div"
228
-
};
229
-
230
48
static struct clk_fixed_factor gpll0_div = {
231
49
.mult = 1,
232
50
.div = 2,
233
51
.hw.init = &(struct clk_init_data){
234
52
.name = "gpll0_div",
235
-
.parent_names = (const char *[]){ "gpll0" },
53
+
.parent_data = (const struct clk_parent_data[]){
54
+
{ .fw_name = "gpll0", .name = "gpll0" },
55
+
},
236
56
.num_parents = 1,
237
57
.ops = &clk_fixed_factor_ops,
238
58
},
···
85
265
.enable_mask = BIT(0),
86
266
.hw.init = &(struct clk_init_data){
87
267
.name = "mmpll0_early",
88
-
.parent_names = (const char *[]){ "xo" },
268
+
.parent_data = (const struct clk_parent_data[]){
269
+
{ .fw_name = "xo", .name = "xo_board" },
270
+
},
89
271
.num_parents = 1,
90
272
.ops = &clk_alpha_pll_ops,
91
273
},
···
100
278
.width = 4,
101
279
.clkr.hw.init = &(struct clk_init_data){
102
280
.name = "mmpll0",
103
-
.parent_names = (const char *[]){ "mmpll0_early" },
281
+
.parent_hws = (const struct clk_hw*[]){
282
+
&mmpll0_early.clkr.hw
283
+
},
104
284
.num_parents = 1,
105
285
.ops = &clk_alpha_pll_postdiv_ops,
106
286
.flags = CLK_SET_RATE_PARENT,
···
119
295
.enable_mask = BIT(1),
120
296
.hw.init = &(struct clk_init_data){
121
297
.name = "mmpll1_early",
122
-
.parent_names = (const char *[]){ "xo" },
298
+
.parent_data = (const struct clk_parent_data[]){
299
+
{ .fw_name = "xo", .name = "xo_board" },
300
+
},
123
301
.num_parents = 1,
124
302
.ops = &clk_alpha_pll_ops,
125
303
}
···
134
308
.width = 4,
135
309
.clkr.hw.init = &(struct clk_init_data){
136
310
.name = "mmpll1",
137
-
.parent_names = (const char *[]){ "mmpll1_early" },
311
+
.parent_hws = (const struct clk_hw*[]){
312
+
&mmpll1_early.clkr.hw
313
+
},
138
314
.num_parents = 1,
139
315
.ops = &clk_alpha_pll_postdiv_ops,
140
316
.flags = CLK_SET_RATE_PARENT,
···
150
322
.num_vco = ARRAY_SIZE(mmpll_gfx_vco),
151
323
.clkr.hw.init = &(struct clk_init_data){
152
324
.name = "mmpll2_early",
153
-
.parent_names = (const char *[]){ "xo" },
325
+
.parent_data = (const struct clk_parent_data[]){
326
+
{ .fw_name = "xo", .name = "xo_board" },
327
+
},
154
328
.num_parents = 1,
155
329
.ops = &clk_alpha_pll_ops,
156
330
},
···
164
334
.width = 4,
165
335
.clkr.hw.init = &(struct clk_init_data){
166
336
.name = "mmpll2",
167
-
.parent_names = (const char *[]){ "mmpll2_early" },
337
+
.parent_hws = (const struct clk_hw*[]){
338
+
&mmpll2_early.clkr.hw
339
+
},
168
340
.num_parents = 1,
169
341
.ops = &clk_alpha_pll_postdiv_ops,
170
342
.flags = CLK_SET_RATE_PARENT,
···
180
348
.num_vco = ARRAY_SIZE(mmpll_p_vco),
181
349
.clkr.hw.init = &(struct clk_init_data){
182
350
.name = "mmpll3_early",
183
-
.parent_names = (const char *[]){ "xo" },
351
+
.parent_data = (const struct clk_parent_data[]){
352
+
{ .fw_name = "xo", .name = "xo_board" },
353
+
},
184
354
.num_parents = 1,
185
355
.ops = &clk_alpha_pll_ops,
186
356
},
···
194
360
.width = 4,
195
361
.clkr.hw.init = &(struct clk_init_data){
196
362
.name = "mmpll3",
197
-
.parent_names = (const char *[]){ "mmpll3_early" },
363
+
.parent_hws = (const struct clk_hw*[]){
364
+
&mmpll3_early.clkr.hw
365
+
},
198
366
.num_parents = 1,
199
367
.ops = &clk_alpha_pll_postdiv_ops,
200
368
.flags = CLK_SET_RATE_PARENT,
···
210
374
.num_vco = ARRAY_SIZE(mmpll_t_vco),
211
375
.clkr.hw.init = &(struct clk_init_data){
212
376
.name = "mmpll4_early",
213
-
.parent_names = (const char *[]){ "xo" },
377
+
.parent_data = (const struct clk_parent_data[]){
378
+
{ .fw_name = "xo", .name = "xo_board" },
379
+
},
214
380
.num_parents = 1,
215
381
.ops = &clk_alpha_pll_ops,
216
382
},
···
224
386
.width = 2,
225
387
.clkr.hw.init = &(struct clk_init_data){
226
388
.name = "mmpll4",
227
-
.parent_names = (const char *[]){ "mmpll4_early" },
389
+
.parent_hws = (const struct clk_hw*[]){
390
+
&mmpll4_early.clkr.hw
391
+
},
228
392
.num_parents = 1,
229
393
.ops = &clk_alpha_pll_postdiv_ops,
230
394
.flags = CLK_SET_RATE_PARENT,
···
240
400
.num_vco = ARRAY_SIZE(mmpll_p_vco),
241
401
.clkr.hw.init = &(struct clk_init_data){
242
402
.name = "mmpll5_early",
243
-
.parent_names = (const char *[]){ "xo" },
403
+
.parent_data = (const struct clk_parent_data[]){
404
+
{ .fw_name = "xo", .name = "xo_board" },
405
+
},
244
406
.num_parents = 1,
245
407
.ops = &clk_alpha_pll_ops,
246
408
},
···
254
412
.width = 4,
255
413
.clkr.hw.init = &(struct clk_init_data){
256
414
.name = "mmpll5",
257
-
.parent_names = (const char *[]){ "mmpll5_early" },
415
+
.parent_hws = (const struct clk_hw*[]){
416
+
&mmpll5_early.clkr.hw
417
+
},
258
418
.num_parents = 1,
259
419
.ops = &clk_alpha_pll_postdiv_ops,
260
420
.flags = CLK_SET_RATE_PARENT,
···
270
426
.num_vco = ARRAY_SIZE(mmpll_gfx_vco),
271
427
.clkr.hw.init = &(struct clk_init_data){
272
428
.name = "mmpll8_early",
273
-
.parent_names = (const char *[]){ "xo" },
429
+
.parent_data = (const struct clk_parent_data[]){
430
+
{ .fw_name = "xo", .name = "xo_board" },
431
+
},
274
432
.num_parents = 1,
275
433
.ops = &clk_alpha_pll_ops,
276
434
},
···
284
438
.width = 4,
285
439
.clkr.hw.init = &(struct clk_init_data){
286
440
.name = "mmpll8",
287
-
.parent_names = (const char *[]){ "mmpll8_early" },
441
+
.parent_hws = (const struct clk_hw*[]){
442
+
&mmpll8_early.clkr.hw
443
+
},
288
444
.num_parents = 1,
289
445
.ops = &clk_alpha_pll_postdiv_ops,
290
446
.flags = CLK_SET_RATE_PARENT,
···
300
452
.num_vco = ARRAY_SIZE(mmpll_t_vco),
301
453
.clkr.hw.init = &(struct clk_init_data){
302
454
.name = "mmpll9_early",
303
-
.parent_names = (const char *[]){ "xo" },
455
+
.parent_data = (const struct clk_parent_data[]){
456
+
{ .fw_name = "xo", .name = "xo_board" },
457
+
},
304
458
.num_parents = 1,
305
459
.ops = &clk_alpha_pll_ops,
306
460
},
···
314
464
.width = 2,
315
465
.clkr.hw.init = &(struct clk_init_data){
316
466
.name = "mmpll9",
317
-
.parent_names = (const char *[]){ "mmpll9_early" },
467
+
.parent_hws = (const struct clk_hw*[]){
468
+
&mmpll9_early.clkr.hw
469
+
},
318
470
.num_parents = 1,
319
471
.ops = &clk_alpha_pll_postdiv_ops,
320
472
.flags = CLK_SET_RATE_PARENT,
321
473
},
474
+
};
475
+
476
+
static const struct parent_map mmss_xo_hdmi_map[] = {
477
+
{ P_XO, 0 },
478
+
{ P_HDMIPLL, 1 }
479
+
};
480
+
481
+
static const struct clk_parent_data mmss_xo_hdmi[] = {
482
+
{ .fw_name = "xo", .name = "xo_board" },
483
+
{ .fw_name = "hdmipll", .name = "hdmipll" }
484
+
};
485
+
486
+
static const struct parent_map mmss_xo_dsi0pll_dsi1pll_map[] = {
487
+
{ P_XO, 0 },
488
+
{ P_DSI0PLL, 1 },
489
+
{ P_DSI1PLL, 2 }
490
+
};
491
+
492
+
static const struct clk_parent_data mmss_xo_dsi0pll_dsi1pll[] = {
493
+
{ .fw_name = "xo", .name = "xo_board" },
494
+
{ .fw_name = "dsi0pll", .name = "dsi0pll" },
495
+
{ .fw_name = "dsi1pll", .name = "dsi1pll" }
496
+
};
497
+
498
+
static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = {
499
+
{ P_XO, 0 },
500
+
{ P_GPLL0, 5 },
501
+
{ P_GPLL0_DIV, 6 }
502
+
};
503
+
504
+
static const struct clk_parent_data mmss_xo_gpll0_gpll0_div[] = {
505
+
{ .fw_name = "xo", .name = "xo_board" },
506
+
{ .fw_name = "gpll0", .name = "gpll0" },
507
+
{ .hw = &gpll0_div.hw }
508
+
};
509
+
510
+
static const struct parent_map mmss_xo_dsibyte_map[] = {
511
+
{ P_XO, 0 },
512
+
{ P_DSI0PLL_BYTE, 1 },
513
+
{ P_DSI1PLL_BYTE, 2 }
514
+
};
515
+
516
+
static const struct clk_parent_data mmss_xo_dsibyte[] = {
517
+
{ .fw_name = "xo", .name = "xo_board" },
518
+
{ .fw_name = "dsi0pllbyte", .name = "dsi0pllbyte" },
519
+
{ .fw_name = "dsi1pllbyte", .name = "dsi1pllbyte" }
520
+
};
521
+
522
+
static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = {
523
+
{ P_XO, 0 },
524
+
{ P_MMPLL0, 1 },
525
+
{ P_GPLL0, 5 },
526
+
{ P_GPLL0_DIV, 6 }
527
+
};
528
+
529
+
static const struct clk_parent_data mmss_xo_mmpll0_gpll0_gpll0_div[] = {
530
+
{ .fw_name = "xo", .name = "xo_board" },
531
+
{ .hw = &mmpll0.clkr.hw },
532
+
{ .fw_name = "gpll0", .name = "gpll0" },
533
+
{ .hw = &gpll0_div.hw }
534
+
};
535
+
536
+
static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = {
537
+
{ P_XO, 0 },
538
+
{ P_MMPLL0, 1 },
539
+
{ P_MMPLL1, 2 },
540
+
{ P_GPLL0, 5 },
541
+
{ P_GPLL0_DIV, 6 }
542
+
};
543
+
544
+
static const struct clk_parent_data mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = {
545
+
{ .fw_name = "xo", .name = "xo_board" },
546
+
{ .hw = &mmpll0.clkr.hw },
547
+
{ .hw = &mmpll1.clkr.hw },
548
+
{ .fw_name = "gpll0", .name = "gpll0" },
549
+
{ .hw = &gpll0_div.hw }
550
+
};
551
+
552
+
static const struct parent_map mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div_map[] = {
553
+
{ P_XO, 0 },
554
+
{ P_MMPLL0, 1 },
555
+
{ P_MMPLL3, 3 },
556
+
{ P_GPLL0, 5 },
557
+
{ P_GPLL0_DIV, 6 }
558
+
};
559
+
560
+
static const struct clk_parent_data mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div[] = {
561
+
{ .fw_name = "xo", .name = "xo_board" },
562
+
{ .hw = &mmpll0.clkr.hw },
563
+
{ .hw = &mmpll3.clkr.hw },
564
+
{ .fw_name = "gpll0", .name = "gpll0" },
565
+
{ .hw = &gpll0_div.hw }
566
+
};
567
+
568
+
static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = {
569
+
{ P_XO, 0 },
570
+
{ P_MMPLL0, 1 },
571
+
{ P_MMPLL5, 2 },
572
+
{ P_GPLL0, 5 },
573
+
{ P_GPLL0_DIV, 6 }
574
+
};
575
+
576
+
static const struct clk_parent_data mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = {
577
+
{ .fw_name = "xo", .name = "xo_board" },
578
+
{ .hw = &mmpll0.clkr.hw },
579
+
{ .hw = &mmpll5.clkr.hw },
580
+
{ .fw_name = "gpll0", .name = "gpll0" },
581
+
{ .hw = &gpll0_div.hw }
582
+
};
583
+
584
+
static const struct parent_map mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div_map[] = {
585
+
{ P_XO, 0 },
586
+
{ P_MMPLL0, 1 },
587
+
{ P_MMPLL4, 3 },
588
+
{ P_GPLL0, 5 },
589
+
{ P_GPLL0_DIV, 6 }
590
+
};
591
+
592
+
static const struct clk_parent_data mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div[] = {
593
+
{ .fw_name = "xo", .name = "xo_board" },
594
+
{ .hw = &mmpll0.clkr.hw },
595
+
{ .hw = &mmpll4.clkr.hw },
596
+
{ .fw_name = "gpll0", .name = "gpll0" },
597
+
{ .hw = &gpll0_div.hw }
598
+
};
599
+
600
+
static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map[] = {
601
+
{ P_XO, 0 },
602
+
{ P_MMPLL0, 1 },
603
+
{ P_MMPLL9, 2 },
604
+
{ P_MMPLL2, 3 },
605
+
{ P_MMPLL8, 4 },
606
+
{ P_GPLL0, 5 }
607
+
};
608
+
609
+
static const struct clk_parent_data mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0[] = {
610
+
{ .fw_name = "xo", .name = "xo_board" },
611
+
{ .hw = &mmpll0.clkr.hw },
612
+
{ .hw = &mmpll9.clkr.hw },
613
+
{ .hw = &mmpll2.clkr.hw },
614
+
{ .hw = &mmpll8.clkr.hw },
615
+
{ .fw_name = "gpll0", .name = "gpll0" },
616
+
};
617
+
618
+
static const struct parent_map mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map[] = {
619
+
{ P_XO, 0 },
620
+
{ P_MMPLL0, 1 },
621
+
{ P_MMPLL9, 2 },
622
+
{ P_MMPLL2, 3 },
623
+
{ P_MMPLL8, 4 },
624
+
{ P_GPLL0, 5 },
625
+
{ P_GPLL0_DIV, 6 }
626
+
};
627
+
628
+
static const struct clk_parent_data mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div[] = {
629
+
{ .fw_name = "xo", .name = "xo_board" },
630
+
{ .hw = &mmpll0.clkr.hw },
631
+
{ .hw = &mmpll9.clkr.hw },
632
+
{ .hw = &mmpll2.clkr.hw },
633
+
{ .hw = &mmpll8.clkr.hw },
634
+
{ .fw_name = "gpll0", .name = "gpll0" },
635
+
{ .hw = &gpll0_div.hw }
636
+
};
637
+
638
+
static const struct parent_map mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div_map[] = {
639
+
{ P_XO, 0 },
640
+
{ P_MMPLL0, 1 },
641
+
{ P_MMPLL1, 2 },
642
+
{ P_MMPLL4, 3 },
643
+
{ P_MMPLL3, 4 },
644
+
{ P_GPLL0, 5 },
645
+
{ P_GPLL0_DIV, 6 }
646
+
};
647
+
648
+
static const struct clk_parent_data mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div[] = {
649
+
{ .fw_name = "xo", .name = "xo_board" },
650
+
{ .hw = &mmpll0.clkr.hw },
651
+
{ .hw = &mmpll1.clkr.hw },
652
+
{ .hw = &mmpll4.clkr.hw },
653
+
{ .hw = &mmpll3.clkr.hw },
654
+
{ .fw_name = "gpll0", .name = "gpll0" },
655
+
{ .hw = &gpll0_div.hw }
322
656
};
323
657
324
658
static const struct freq_tbl ftbl_ahb_clk_src[] = {
···
519
485
.freq_tbl = ftbl_ahb_clk_src,
520
486
.clkr.hw.init = &(struct clk_init_data){
521
487
.name = "ahb_clk_src",
522
-
.parent_names = mmss_xo_mmpll0_gpll0_gpll0_div,
523
-
.num_parents = 4,
488
+
.parent_data = mmss_xo_mmpll0_gpll0_gpll0_div,
489
+
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_gpll0_gpll0_div),
524
490
.ops = &clk_rcg2_ops,
525
491
},
526
492
};
···
543
509
.freq_tbl = ftbl_axi_clk_src,
544
510
.clkr.hw.init = &(struct clk_init_data){
545
511
.name = "axi_clk_src",
546
-
.parent_names = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
547
-
.num_parents = 5,
512
+
.parent_data = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
513
+
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div),
548
514
.ops = &clk_rcg2_ops,
549
515
},
550
516
};
···
556
522
.freq_tbl = ftbl_axi_clk_src,
557
523
.clkr.hw.init = &(struct clk_init_data){
558
524
.name = "maxi_clk_src",
559
-
.parent_names = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
560
-
.num_parents = 5,
525
+
.parent_data = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
526
+
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div),
561
527
.ops = &clk_rcg2_ops,
562
528
},
563
529
};
···
569
535
.parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_map,
570
536
.clkr.hw.init = &(struct clk_init_data){
571
537
.name = "gfx3d_clk_src",
572
-
.parent_names = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0,
573
-
.num_parents = 6,
538
+
.parent_data = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0,
539
+
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0),
574
540
.ops = &clk_gfx3d_ops,
575
541
.flags = CLK_SET_RATE_PARENT,
576
542
},
···
594
560
.freq_tbl = ftbl_rbbmtimer_clk_src,
595
561
.clkr.hw.init = &(struct clk_init_data){
596
562
.name = "rbbmtimer_clk_src",
597
-
.parent_names = mmss_xo_mmpll0_gpll0_gpll0_div,
598
-
.num_parents = 4,
563
+
.parent_data = mmss_xo_mmpll0_gpll0_gpll0_div,
564
+
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_gpll0_gpll0_div),
599
565
.ops = &clk_rcg2_ops,
600
566
},
601
567
};
···
606
572
.parent_map = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div_map,
607
573
.clkr.hw.init = &(struct clk_init_data){
608
574
.name = "isense_clk_src",
609
-
.parent_names = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div,
610
-
.num_parents = 7,
575
+
.parent_data = mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div,
576
+
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll9_mmpll2_mmpll8_gpll0_gpll0_div),
611
577
.ops = &clk_rcg2_ops,
612
578
},
613
579
};
···
625
591
.freq_tbl = ftbl_rbcpr_clk_src,
626
592
.clkr.hw.init = &(struct clk_init_data){
627
593
.name = "rbcpr_clk_src",
628
-
.parent_names = mmss_xo_mmpll0_gpll0_gpll0_div,
629
-
.num_parents = 4,
594
+
.parent_data = mmss_xo_mmpll0_gpll0_gpll0_div,
595
+
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_gpll0_gpll0_div),
630
596
.ops = &clk_rcg2_ops,
631
597
},
632
598
};
···
647
613
.freq_tbl = ftbl_video_core_clk_src,
648
614
.clkr.hw.init = &(struct clk_init_data){
649
615
.name = "video_core_clk_src",
650
-
.parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div,
651
-
.num_parents = 5,
616
+
.parent_data = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div,
617
+
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div),
652
618
.ops = &clk_rcg2_ops,
653
619
},
654
620
};
···
661
627
.freq_tbl = ftbl_video_core_clk_src,
662
628
.clkr.hw.init = &(struct clk_init_data){
663
629
.name = "video_subcore0_clk_src",
664
-
.parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div,
665
-
.num_parents = 5,
630
+
.parent_data = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div,
631
+
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div),
666
632
.ops = &clk_rcg2_ops,
667
633
},
668
634
};
···
675
641
.freq_tbl = ftbl_video_core_clk_src,
676
642
.clkr.hw.init = &(struct clk_init_data){
677
643
.name = "video_subcore1_clk_src",
678
-
.parent_names = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div,
679
-
.num_parents = 5,
644
+
.parent_data = mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div,
645
+
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_gpll0_gpll0_div),
680
646
.ops = &clk_rcg2_ops,
681
647
},
682
648
};
···
688
654
.parent_map = mmss_xo_dsi0pll_dsi1pll_map,
689
655
.clkr.hw.init = &(struct clk_init_data){
690
656
.name = "pclk0_clk_src",
691
-
.parent_names = mmss_xo_dsi0pll_dsi1pll,
692
-
.num_parents = 3,
657
+
.parent_data = mmss_xo_dsi0pll_dsi1pll,
658
+
.num_parents = ARRAY_SIZE(mmss_xo_dsi0pll_dsi1pll),
693
659
.ops = &clk_pixel_ops,
694
660
.flags = CLK_SET_RATE_PARENT,
695
661
},
···
702
668
.parent_map = mmss_xo_dsi0pll_dsi1pll_map,
703
669
.clkr.hw.init = &(struct clk_init_data){
704
670
.name = "pclk1_clk_src",
705
-
.parent_names = mmss_xo_dsi0pll_dsi1pll,
706
-
.num_parents = 3,
671
+
.parent_data = mmss_xo_dsi0pll_dsi1pll,
672
+
.num_parents = ARRAY_SIZE(mmss_xo_dsi0pll_dsi1pll),
707
673
.ops = &clk_pixel_ops,
708
674
.flags = CLK_SET_RATE_PARENT,
709
675
},
···
729
695
.freq_tbl = ftbl_mdp_clk_src,
730
696
.clkr.hw.init = &(struct clk_init_data){
731
697
.name = "mdp_clk_src",
732
-
.parent_names = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div,
733
-
.num_parents = 5,
698
+
.parent_data = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div,
699
+
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div),
734
700
.ops = &clk_rcg2_ops,
735
701
},
736
702
};
···
747
713
.freq_tbl = extpclk_freq_tbl,
748
714
.clkr.hw.init = &(struct clk_init_data){
749
715
.name = "extpclk_clk_src",
750
-
.parent_names = mmss_xo_hdmi,
751
-
.num_parents = 2,
716
+
.parent_data = mmss_xo_hdmi,
717
+
.num_parents = ARRAY_SIZE(mmss_xo_hdmi),
752
718
.ops = &clk_byte_ops,
753
719
.flags = CLK_SET_RATE_PARENT,
754
720
},
···
766
732
.freq_tbl = ftbl_mdss_vsync_clk,
767
733
.clkr.hw.init = &(struct clk_init_data){
768
734
.name = "vsync_clk_src",
769
-
.parent_names = mmss_xo_gpll0_gpll0_div,
770
-
.num_parents = 3,
735
+
.parent_data = mmss_xo_gpll0_gpll0_div,
736
+
.num_parents = ARRAY_SIZE(mmss_xo_gpll0_gpll0_div),
771
737
.ops = &clk_rcg2_ops,
772
738
},
773
739
};
···
784
750
.freq_tbl = ftbl_mdss_hdmi_clk,
785
751
.clkr.hw.init = &(struct clk_init_data){
786
752
.name = "hdmi_clk_src",
787
-
.parent_names = mmss_xo_gpll0_gpll0_div,
788
-
.num_parents = 3,
753
+
.parent_data = mmss_xo_gpll0_gpll0_div,
754
+
.num_parents = ARRAY_SIZE(mmss_xo_gpll0_gpll0_div),
789
755
.ops = &clk_rcg2_ops,
790
756
},
791
757
};
···
796
762
.parent_map = mmss_xo_dsibyte_map,
797
763
.clkr.hw.init = &(struct clk_init_data){
798
764
.name = "byte0_clk_src",
799
-
.parent_names = mmss_xo_dsibyte,
800
-
.num_parents = 3,
765
+
.parent_data = mmss_xo_dsibyte,
766
+
.num_parents = ARRAY_SIZE(mmss_xo_dsibyte),
801
767
.ops = &clk_byte2_ops,
802
768
.flags = CLK_SET_RATE_PARENT,
803
769
},
···
809
775
.parent_map = mmss_xo_dsibyte_map,
810
776
.clkr.hw.init = &(struct clk_init_data){
811
777
.name = "byte1_clk_src",
812
-
.parent_names = mmss_xo_dsibyte,
813
-
.num_parents = 3,
778
+
.parent_data = mmss_xo_dsibyte,
779
+
.num_parents = ARRAY_SIZE(mmss_xo_dsibyte),
814
780
.ops = &clk_byte2_ops,
815
781
.flags = CLK_SET_RATE_PARENT,
816
782
},
···
828
794
.freq_tbl = ftbl_mdss_esc0_1_clk,
829
795
.clkr.hw.init = &(struct clk_init_data){
830
796
.name = "esc0_clk_src",
831
-
.parent_names = mmss_xo_dsibyte,
832
-
.num_parents = 3,
797
+
.parent_data = mmss_xo_dsibyte,
798
+
.num_parents = ARRAY_SIZE(mmss_xo_dsibyte),
833
799
.ops = &clk_rcg2_ops,
834
800
},
835
801
};
···
841
807
.freq_tbl = ftbl_mdss_esc0_1_clk,
842
808
.clkr.hw.init = &(struct clk_init_data){
843
809
.name = "esc1_clk_src",
844
-
.parent_names = mmss_xo_dsibyte,
845
-
.num_parents = 3,
810
+
.parent_data = mmss_xo_dsibyte,
811
+
.num_parents = ARRAY_SIZE(mmss_xo_dsibyte),
846
812
.ops = &clk_rcg2_ops,
847
813
},
848
814
};
···
865
831
.freq_tbl = ftbl_camss_gp0_clk_src,
866
832
.clkr.hw.init = &(struct clk_init_data){
867
833
.name = "camss_gp0_clk_src",
868
-
.parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
869
-
.num_parents = 5,
834
+
.parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
835
+
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div),
870
836
.ops = &clk_rcg2_ops,
871
837
},
872
838
};
···
879
845
.freq_tbl = ftbl_camss_gp0_clk_src,
880
846
.clkr.hw.init = &(struct clk_init_data){
881
847
.name = "camss_gp1_clk_src",
882
-
.parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
883
-
.num_parents = 5,
848
+
.parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
849
+
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div),
884
850
.ops = &clk_rcg2_ops,
885
851
},
886
852
};
···
907
873
.freq_tbl = ftbl_mclk0_clk_src,
908
874
.clkr.hw.init = &(struct clk_init_data){
909
875
.name = "mclk0_clk_src",
910
-
.parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
911
-
.num_parents = 5,
876
+
.parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
877
+
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div),
912
878
.ops = &clk_rcg2_ops,
913
879
},
914
880
};
···
921
887
.freq_tbl = ftbl_mclk0_clk_src,
922
888
.clkr.hw.init = &(struct clk_init_data){
923
889
.name = "mclk1_clk_src",
924
-
.parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
925
-
.num_parents = 5,
890
+
.parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
891
+
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div),
926
892
.ops = &clk_rcg2_ops,
927
893
},
928
894
};
···
935
901
.freq_tbl = ftbl_mclk0_clk_src,
936
902
.clkr.hw.init = &(struct clk_init_data){
937
903
.name = "mclk2_clk_src",
938
-
.parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
939
-
.num_parents = 5,
904
+
.parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
905
+
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div),
940
906
.ops = &clk_rcg2_ops,
941
907
},
942
908
};
···
949
915
.freq_tbl = ftbl_mclk0_clk_src,
950
916
.clkr.hw.init = &(struct clk_init_data){
951
917
.name = "mclk3_clk_src",
952
-
.parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
953
-
.num_parents = 5,
918
+
.parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
919
+
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div),
954
920
.ops = &clk_rcg2_ops,
955
921
},
956
922
};
···
971
937
.freq_tbl = ftbl_cci_clk_src,
972
938
.clkr.hw.init = &(struct clk_init_data){
973
939
.name = "cci_clk_src",
974
-
.parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
975
-
.num_parents = 5,
940
+
.parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
941
+
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div),
976
942
.ops = &clk_rcg2_ops,
977
943
},
978
944
};
···
991
957
.freq_tbl = ftbl_csi0phytimer_clk_src,
992
958
.clkr.hw.init = &(struct clk_init_data){
993
959
.name = "csi0phytimer_clk_src",
994
-
.parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
995
-
.num_parents = 7,
960
+
.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
961
+
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
996
962
.ops = &clk_rcg2_ops,
997
963
},
998
964
};
···
1004
970
.freq_tbl = ftbl_csi0phytimer_clk_src,
1005
971
.clkr.hw.init = &(struct clk_init_data){
1006
972
.name = "csi1phytimer_clk_src",
1007
-
.parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1008
-
.num_parents = 7,
973
+
.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
974
+
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1009
975
.ops = &clk_rcg2_ops,
1010
976
},
1011
977
};
···
1017
983
.freq_tbl = ftbl_csi0phytimer_clk_src,
1018
984
.clkr.hw.init = &(struct clk_init_data){
1019
985
.name = "csi2phytimer_clk_src",
1020
-
.parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1021
-
.num_parents = 7,
986
+
.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
987
+
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1022
988
.ops = &clk_rcg2_ops,
1023
989
},
1024
990
};
···
1038
1004
.freq_tbl = ftbl_csiphy0_3p_clk_src,
1039
1005
.clkr.hw.init = &(struct clk_init_data){
1040
1006
.name = "csiphy0_3p_clk_src",
1041
-
.parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1042
-
.num_parents = 7,
1007
+
.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1008
+
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1043
1009
.ops = &clk_rcg2_ops,
1044
1010
},
1045
1011
};
···
1051
1017
.freq_tbl = ftbl_csiphy0_3p_clk_src,
1052
1018
.clkr.hw.init = &(struct clk_init_data){
1053
1019
.name = "csiphy1_3p_clk_src",
1054
-
.parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1055
-
.num_parents = 7,
1020
+
.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1021
+
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1056
1022
.ops = &clk_rcg2_ops,
1057
1023
},
1058
1024
};
···
1064
1030
.freq_tbl = ftbl_csiphy0_3p_clk_src,
1065
1031
.clkr.hw.init = &(struct clk_init_data){
1066
1032
.name = "csiphy2_3p_clk_src",
1067
-
.parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1068
-
.num_parents = 7,
1033
+
.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1034
+
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1069
1035
.ops = &clk_rcg2_ops,
1070
1036
},
1071
1037
};
···
1087
1053
.freq_tbl = ftbl_jpeg0_clk_src,
1088
1054
.clkr.hw.init = &(struct clk_init_data){
1089
1055
.name = "jpeg0_clk_src",
1090
-
.parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1091
-
.num_parents = 7,
1056
+
.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1057
+
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1092
1058
.ops = &clk_rcg2_ops,
1093
1059
},
1094
1060
};
···
1109
1075
.freq_tbl = ftbl_jpeg2_clk_src,
1110
1076
.clkr.hw.init = &(struct clk_init_data){
1111
1077
.name = "jpeg2_clk_src",
1112
-
.parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1113
-
.num_parents = 7,
1078
+
.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1079
+
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1114
1080
.ops = &clk_rcg2_ops,
1115
1081
},
1116
1082
};
···
1122
1088
.freq_tbl = ftbl_jpeg0_clk_src,
1123
1089
.clkr.hw.init = &(struct clk_init_data){
1124
1090
.name = "jpeg_dma_clk_src",
1125
-
.parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1126
-
.num_parents = 7,
1091
+
.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1092
+
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1127
1093
.ops = &clk_rcg2_ops,
1128
1094
},
1129
1095
};
···
1145
1111
.freq_tbl = ftbl_vfe0_clk_src,
1146
1112
.clkr.hw.init = &(struct clk_init_data){
1147
1113
.name = "vfe0_clk_src",
1148
-
.parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1149
-
.num_parents = 7,
1114
+
.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1115
+
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1150
1116
.ops = &clk_rcg2_ops,
1151
1117
},
1152
1118
};
···
1158
1124
.freq_tbl = ftbl_vfe0_clk_src,
1159
1125
.clkr.hw.init = &(struct clk_init_data){
1160
1126
.name = "vfe1_clk_src",
1161
-
.parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1162
-
.num_parents = 7,
1127
+
.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1128
+
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1163
1129
.ops = &clk_rcg2_ops,
1164
1130
},
1165
1131
};
···
1180
1146
.freq_tbl = ftbl_cpp_clk_src,
1181
1147
.clkr.hw.init = &(struct clk_init_data){
1182
1148
.name = "cpp_clk_src",
1183
-
.parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1184
-
.num_parents = 7,
1149
+
.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1150
+
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1185
1151
.ops = &clk_rcg2_ops,
1186
1152
},
1187
1153
};
···
1202
1168
.freq_tbl = ftbl_csi0_clk_src,
1203
1169
.clkr.hw.init = &(struct clk_init_data){
1204
1170
.name = "csi0_clk_src",
1205
-
.parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1206
-
.num_parents = 7,
1171
+
.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1172
+
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1207
1173
.ops = &clk_rcg2_ops,
1208
1174
},
1209
1175
};
···
1215
1181
.freq_tbl = ftbl_csi0_clk_src,
1216
1182
.clkr.hw.init = &(struct clk_init_data){
1217
1183
.name = "csi1_clk_src",
1218
-
.parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1219
-
.num_parents = 7,
1184
+
.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1185
+
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1220
1186
.ops = &clk_rcg2_ops,
1221
1187
},
1222
1188
};
···
1228
1194
.freq_tbl = ftbl_csi0_clk_src,
1229
1195
.clkr.hw.init = &(struct clk_init_data){
1230
1196
.name = "csi2_clk_src",
1231
-
.parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1232
-
.num_parents = 7,
1197
+
.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1198
+
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1233
1199
.ops = &clk_rcg2_ops,
1234
1200
},
1235
1201
};
···
1241
1207
.freq_tbl = ftbl_csi0_clk_src,
1242
1208
.clkr.hw.init = &(struct clk_init_data){
1243
1209
.name = "csi3_clk_src",
1244
-
.parent_names = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1245
-
.num_parents = 7,
1210
+
.parent_data = mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div,
1211
+
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_mmpll4_mmpll3_gpll0_gpll0_div),
1246
1212
.ops = &clk_rcg2_ops,
1247
1213
},
1248
1214
};
···
1261
1227
.freq_tbl = ftbl_fd_core_clk_src,
1262
1228
.clkr.hw.init = &(struct clk_init_data){
1263
1229
.name = "fd_core_clk_src",
1264
-
.parent_names = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
1265
-
.num_parents = 5,
1230
+
.parent_data = mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div,
1231
+
.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_gpll0_gpll0_div),
1266
1232
.ops = &clk_rcg2_ops,
1267
1233
},
1268
1234
};
···
1274
1240
.enable_mask = BIT(0),
1275
1241
.hw.init = &(struct clk_init_data){
1276
1242
.name = "mmss_mmagic_ahb_clk",
1277
-
.parent_names = (const char *[]){ "ahb_clk_src" },
1243
+
.parent_hws = (const struct clk_hw*[]){
1244
+
&ahb_clk_src.clkr.hw
1245
+
},
1278
1246
.num_parents = 1,
1279
1247
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1280
1248
.ops = &clk_branch2_ops,
···
1291
1255
.enable_mask = BIT(0),
1292
1256
.hw.init = &(struct clk_init_data){
1293
1257
.name = "mmss_mmagic_cfg_ahb_clk",
1294
-
.parent_names = (const char *[]){ "ahb_clk_src" },
1258
+
.parent_hws = (const struct clk_hw*[]){
1259
+
&ahb_clk_src.clkr.hw
1260
+
},
1295
1261
.num_parents = 1,
1296
1262
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1297
1263
.ops = &clk_branch2_ops,
···
1308
1270
.enable_mask = BIT(0),
1309
1271
.hw.init = &(struct clk_init_data){
1310
1272
.name = "mmss_misc_ahb_clk",
1311
-
.parent_names = (const char *[]){ "ahb_clk_src" },
1273
+
.parent_hws = (const struct clk_hw*[]){
1274
+
&ahb_clk_src.clkr.hw
1275
+
},
1312
1276
.num_parents = 1,
1313
1277
.flags = CLK_SET_RATE_PARENT,
1314
1278
.ops = &clk_branch2_ops,
···
1325
1285
.enable_mask = BIT(0),
1326
1286
.hw.init = &(struct clk_init_data){
1327
1287
.name = "mmss_misc_cxo_clk",
1328
-
.parent_names = (const char *[]){ "xo" },
1288
+
.parent_data = (const struct clk_parent_data[]){
1289
+
{ .fw_name = "xo", .name = "xo_board" },
1290
+
},
1329
1291
.num_parents = 1,
1330
1292
.ops = &clk_branch2_ops,
1331
1293
},
···
1341
1299
.enable_mask = BIT(0),
1342
1300
.hw.init = &(struct clk_init_data){
1343
1301
.name = "mmss_mmagic_maxi_clk",
1344
-
.parent_names = (const char *[]){ "maxi_clk_src" },
1302
+
.parent_hws = (const struct clk_hw*[]){
1303
+
&maxi_clk_src.clkr.hw
1304
+
},
1345
1305
.num_parents = 1,
1346
1306
.flags = CLK_SET_RATE_PARENT,
1347
1307
.ops = &clk_branch2_ops,
···
1358
1314
.enable_mask = BIT(0),
1359
1315
.hw.init = &(struct clk_init_data){
1360
1316
.name = "mmagic_camss_axi_clk",
1361
-
.parent_names = (const char *[]){ "axi_clk_src" },
1317
+
.parent_hws = (const struct clk_hw*[]){
1318
+
&axi_clk_src.clkr.hw
1319
+
},
1362
1320
.num_parents = 1,
1363
1321
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1364
1322
.ops = &clk_branch2_ops,
···
1375
1329
.enable_mask = BIT(0),
1376
1330
.hw.init = &(struct clk_init_data){
1377
1331
.name = "mmagic_camss_noc_cfg_ahb_clk",
1378
-
.parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" },
1332
+
.parent_data = (const struct clk_parent_data[]){
1333
+
{ .fw_name = "gcc_mmss_noc_cfg_ahb_clk", .name = "gcc_mmss_noc_cfg_ahb_clk" },
1334
+
},
1379
1335
.num_parents = 1,
1380
1336
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1381
1337
.ops = &clk_branch2_ops,
···
1392
1344
.enable_mask = BIT(0),
1393
1345
.hw.init = &(struct clk_init_data){
1394
1346
.name = "smmu_vfe_ahb_clk",
1395
-
.parent_names = (const char *[]){ "ahb_clk_src" },
1347
+
.parent_hws = (const struct clk_hw*[]){
1348
+
&ahb_clk_src.clkr.hw
1349
+
},
1396
1350
.num_parents = 1,
1397
1351
.flags = CLK_SET_RATE_PARENT,
1398
1352
.ops = &clk_branch2_ops,
···
1409
1359
.enable_mask = BIT(0),
1410
1360
.hw.init = &(struct clk_init_data){
1411
1361
.name = "smmu_vfe_axi_clk",
1412
-
.parent_names = (const char *[]){ "axi_clk_src" },
1362
+
.parent_hws = (const struct clk_hw*[]){
1363
+
&axi_clk_src.clkr.hw
1364
+
},
1413
1365
.num_parents = 1,
1414
1366
.flags = CLK_SET_RATE_PARENT,
1415
1367
.ops = &clk_branch2_ops,
···
1426
1374
.enable_mask = BIT(0),
1427
1375
.hw.init = &(struct clk_init_data){
1428
1376
.name = "smmu_cpp_ahb_clk",
1429
-
.parent_names = (const char *[]){ "ahb_clk_src" },
1377
+
.parent_hws = (const struct clk_hw*[]){
1378
+
&ahb_clk_src.clkr.hw
1379
+
},
1430
1380
.num_parents = 1,
1431
1381
.flags = CLK_SET_RATE_PARENT,
1432
1382
.ops = &clk_branch2_ops,
···
1443
1389
.enable_mask = BIT(0),
1444
1390
.hw.init = &(struct clk_init_data){
1445
1391
.name = "smmu_cpp_axi_clk",
1446
-
.parent_names = (const char *[]){ "axi_clk_src" },
1392
+
.parent_hws = (const struct clk_hw*[]){
1393
+
&axi_clk_src.clkr.hw
1394
+
},
1447
1395
.num_parents = 1,
1448
1396
.flags = CLK_SET_RATE_PARENT,
1449
1397
.ops = &clk_branch2_ops,
···
1460
1404
.enable_mask = BIT(0),
1461
1405
.hw.init = &(struct clk_init_data){
1462
1406
.name = "smmu_jpeg_ahb_clk",
1463
-
.parent_names = (const char *[]){ "ahb_clk_src" },
1407
+
.parent_hws = (const struct clk_hw*[]){
1408
+
&ahb_clk_src.clkr.hw
1409
+
},
1464
1410
.num_parents = 1,
1465
1411
.flags = CLK_SET_RATE_PARENT,
1466
1412
.ops = &clk_branch2_ops,
···
1477
1419
.enable_mask = BIT(0),
1478
1420
.hw.init = &(struct clk_init_data){
1479
1421
.name = "smmu_jpeg_axi_clk",
1480
-
.parent_names = (const char *[]){ "axi_clk_src" },
1422
+
.parent_hws = (const struct clk_hw*[]){
1423
+
&axi_clk_src.clkr.hw
1424
+
},
1481
1425
.num_parents = 1,
1482
1426
.flags = CLK_SET_RATE_PARENT,
1483
1427
.ops = &clk_branch2_ops,
···
1494
1434
.enable_mask = BIT(0),
1495
1435
.hw.init = &(struct clk_init_data){
1496
1436
.name = "mmagic_mdss_axi_clk",
1497
-
.parent_names = (const char *[]){ "axi_clk_src" },
1437
+
.parent_hws = (const struct clk_hw*[]){
1438
+
&axi_clk_src.clkr.hw
1439
+
},
1498
1440
.num_parents = 1,
1499
1441
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1500
1442
.ops = &clk_branch2_ops,
···
1511
1449
.enable_mask = BIT(0),
1512
1450
.hw.init = &(struct clk_init_data){
1513
1451
.name = "mmagic_mdss_noc_cfg_ahb_clk",
1514
-
.parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" },
1452
+
.parent_data = (const struct clk_parent_data[]){
1453
+
{ .fw_name = "gcc_mmss_noc_cfg_ahb_clk", .name = "gcc_mmss_noc_cfg_ahb_clk" },
1454
+
},
1515
1455
.num_parents = 1,
1516
1456
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1517
1457
.ops = &clk_branch2_ops,
···
1528
1464
.enable_mask = BIT(0),
1529
1465
.hw.init = &(struct clk_init_data){
1530
1466
.name = "smmu_rot_ahb_clk",
1531
-
.parent_names = (const char *[]){ "ahb_clk_src" },
1467
+
.parent_hws = (const struct clk_hw*[]){
1468
+
&ahb_clk_src.clkr.hw
1469
+
},
1532
1470
.num_parents = 1,
1533
1471
.flags = CLK_SET_RATE_PARENT,
1534
1472
.ops = &clk_branch2_ops,
···
1545
1479
.enable_mask = BIT(0),
1546
1480
.hw.init = &(struct clk_init_data){
1547
1481
.name = "smmu_rot_axi_clk",
1548
-
.parent_names = (const char *[]){ "axi_clk_src" },
1482
+
.parent_hws = (const struct clk_hw*[]){
1483
+
&axi_clk_src.clkr.hw
1484
+
},
1549
1485
.num_parents = 1,
1550
1486
.flags = CLK_SET_RATE_PARENT,
1551
1487
.ops = &clk_branch2_ops,
···
1562
1494
.enable_mask = BIT(0),
1563
1495
.hw.init = &(struct clk_init_data){
1564
1496
.name = "smmu_mdp_ahb_clk",
1565
-
.parent_names = (const char *[]){ "ahb_clk_src" },
1497
+
.parent_hws = (const struct clk_hw*[]){
1498
+
&ahb_clk_src.clkr.hw
1499
+
},
1566
1500
.num_parents = 1,
1567
1501
.flags = CLK_SET_RATE_PARENT,
1568
1502
.ops = &clk_branch2_ops,
···
1579
1509
.enable_mask = BIT(0),
1580
1510
.hw.init = &(struct clk_init_data){
1581
1511
.name = "smmu_mdp_axi_clk",
1582
-
.parent_names = (const char *[]){ "axi_clk_src" },
1512
+
.parent_hws = (const struct clk_hw*[]){
1513
+
&axi_clk_src.clkr.hw
1514
+
},
1583
1515
.num_parents = 1,
1584
1516
.flags = CLK_SET_RATE_PARENT,
1585
1517
.ops = &clk_branch2_ops,
···
1596
1524
.enable_mask = BIT(0),
1597
1525
.hw.init = &(struct clk_init_data){
1598
1526
.name = "mmagic_video_axi_clk",
1599
-
.parent_names = (const char *[]){ "axi_clk_src" },
1527
+
.parent_hws = (const struct clk_hw*[]){
1528
+
&axi_clk_src.clkr.hw
1529
+
},
1600
1530
.num_parents = 1,
1601
1531
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1602
1532
.ops = &clk_branch2_ops,
···
1613
1539
.enable_mask = BIT(0),
1614
1540
.hw.init = &(struct clk_init_data){
1615
1541
.name = "mmagic_video_noc_cfg_ahb_clk",
1616
-
.parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" },
1542
+
.parent_data = (const struct clk_parent_data[]){
1543
+
{ .fw_name = "gcc_mmss_noc_cfg_ahb_clk", .name = "gcc_mmss_noc_cfg_ahb_clk" },
1544
+
},
1617
1545
.num_parents = 1,
1618
1546
.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
1619
1547
.ops = &clk_branch2_ops,
···
1630
1554
.enable_mask = BIT(0),
1631
1555
.hw.init = &(struct clk_init_data){
1632
1556
.name = "smmu_video_ahb_clk",
1633
-
.parent_names = (const char *[]){ "ahb_clk_src" },
1557
+
.parent_hws = (const struct clk_hw*[]){
1558
+
&ahb_clk_src.clkr.hw
1559
+
},
1634
1560
.num_parents = 1,
1635
1561
.flags = CLK_SET_RATE_PARENT,
1636
1562
.ops = &clk_branch2_ops,
···
1647
1569
.enable_mask = BIT(0),
1648
1570
.hw.init = &(struct clk_init_data){
1649
1571
.name = "smmu_video_axi_clk",
1650
-
.parent_names = (const char *[]){ "axi_clk_src" },
1572
+
.parent_hws = (const struct clk_hw*[]){
1573
+
&axi_clk_src.clkr.hw
1574
+
},
1651
1575
.num_parents = 1,
1652
1576
.flags = CLK_SET_RATE_PARENT,
1653
1577
.ops = &clk_branch2_ops,
···
1664
1584
.enable_mask = BIT(0),
1665
1585
.hw.init = &(struct clk_init_data){
1666
1586
.name = "mmagic_bimc_noc_cfg_ahb_clk",
1667
-
.parent_names = (const char *[]){ "gcc_mmss_noc_cfg_ahb_clk" },
1587
+
.parent_data = (const struct clk_parent_data[]){
1588
+
{ .fw_name = "gcc_mmss_noc_cfg_ahb_clk", .name = "gcc_mmss_noc_cfg_ahb_clk" },
1589
+
},
1668
1590
.num_parents = 1,
1669
1591
.flags = CLK_SET_RATE_PARENT,
1670
1592
.ops = &clk_branch2_ops,
···
1681
1599
.enable_mask = BIT(0),
1682
1600
.hw.init = &(struct clk_init_data){
1683
1601
.name = "gpu_gx_gfx3d_clk",
1684
-
.parent_names = (const char *[]){ "gfx3d_clk_src" },
1602
+
.parent_hws = (const struct clk_hw*[]){
1603
+
&gfx3d_clk_src.rcg.clkr.hw
1604
+
},
1685
1605
.num_parents = 1,
1686
1606
.flags = CLK_SET_RATE_PARENT,
1687
1607
.ops = &clk_branch2_ops,
···
1698
1614
.enable_mask = BIT(0),
1699
1615
.hw.init = &(struct clk_init_data){
1700
1616
.name = "gpu_gx_rbbmtimer_clk",
1701
-
.parent_names = (const char *[]){ "rbbmtimer_clk_src" },
1617
+
.parent_hws = (const struct clk_hw*[]){
1618
+
&rbbmtimer_clk_src.clkr.hw
1619
+
},
1702
1620
.num_parents = 1,
1703
1621
.flags = CLK_SET_RATE_PARENT,
1704
1622
.ops = &clk_branch2_ops,
···
1715
1629
.enable_mask = BIT(0),
1716
1630
.hw.init = &(struct clk_init_data){
1717
1631
.name = "gpu_ahb_clk",
1718
-
.parent_names = (const char *[]){ "ahb_clk_src" },
1632
+
.parent_hws = (const struct clk_hw*[]){
1633
+
&ahb_clk_src.clkr.hw
1634
+
},
1719
1635
.num_parents = 1,
1720
1636
.flags = CLK_SET_RATE_PARENT,
1721
1637
.ops = &clk_branch2_ops,
···
1732
1644
.enable_mask = BIT(0),
1733
1645
.hw.init = &(struct clk_init_data){
1734
1646
.name = "gpu_aon_isense_clk",
1735
-
.parent_names = (const char *[]){ "isense_clk_src" },
1647
+
.parent_hws = (const struct clk_hw*[]){
1648
+
&isense_clk_src.clkr.hw
1649
+
},
1736
1650
.num_parents = 1,
1737
1651
.flags = CLK_SET_RATE_PARENT,
1738
1652
.ops = &clk_branch2_ops,
···
1749
1659
.enable_mask = BIT(0),
1750
1660
.hw.init = &(struct clk_init_data){
1751
1661
.name = "vmem_maxi_clk",
1752
-
.parent_names = (const char *[]){ "maxi_clk_src" },
1662
+
.parent_hws = (const struct clk_hw*[]){
1663
+
&maxi_clk_src.clkr.hw
1664
+
},
1753
1665
.num_parents = 1,
1754
1666
.flags = CLK_SET_RATE_PARENT,
1755
1667
.ops = &clk_branch2_ops,
···
1766
1674
.enable_mask = BIT(0),
1767
1675
.hw.init = &(struct clk_init_data){
1768
1676
.name = "vmem_ahb_clk",
1769
-
.parent_names = (const char *[]){ "ahb_clk_src" },
1677
+
.parent_hws = (const struct clk_hw*[]){
1678
+
&ahb_clk_src.clkr.hw
1679
+
},
1770
1680
.num_parents = 1,
1771
1681
.flags = CLK_SET_RATE_PARENT,
1772
1682
.ops = &clk_branch2_ops,
···
1783
1689
.enable_mask = BIT(0),
1784
1690
.hw.init = &(struct clk_init_data){
1785
1691
.name = "mmss_rbcpr_clk",
1786
-
.parent_names = (const char *[]){ "rbcpr_clk_src" },
1692
+
.parent_hws = (const struct clk_hw*[]){
1693
+
&rbcpr_clk_src.clkr.hw
1694
+
},
1787
1695
.num_parents = 1,
1788
1696
.flags = CLK_SET_RATE_PARENT,
1789
1697
.ops = &clk_branch2_ops,
···
1800
1704
.enable_mask = BIT(0),
1801
1705
.hw.init = &(struct clk_init_data){
1802
1706
.name = "mmss_rbcpr_ahb_clk",
1803
-
.parent_names = (const char *[]){ "ahb_clk_src" },
1707
+
.parent_hws = (const struct clk_hw*[]){
1708
+
&ahb_clk_src.clkr.hw
1709
+
},
1804
1710
.num_parents = 1,
1805
1711
.flags = CLK_SET_RATE_PARENT,
1806
1712
.ops = &clk_branch2_ops,
···
1817
1719
.enable_mask = BIT(0),
1818
1720
.hw.init = &(struct clk_init_data){
1819
1721
.name = "video_core_clk",
1820
-
.parent_names = (const char *[]){ "video_core_clk_src" },
1722
+
.parent_hws = (const struct clk_hw*[]){
1723
+
&video_core_clk_src.clkr.hw
1724
+
},
1821
1725
.num_parents = 1,
1822
1726
.flags = CLK_SET_RATE_PARENT,
1823
1727
.ops = &clk_branch2_ops,
···
1834
1734
.enable_mask = BIT(0),
1835
1735
.hw.init = &(struct clk_init_data){
1836
1736
.name = "video_axi_clk",
1837
-
.parent_names = (const char *[]){ "axi_clk_src" },
1737
+
.parent_hws = (const struct clk_hw*[]){
1738
+
&axi_clk_src.clkr.hw
1739
+
},
1838
1740
.num_parents = 1,
1839
1741
.flags = CLK_SET_RATE_PARENT,
1840
1742
.ops = &clk_branch2_ops,
···
1851
1749
.enable_mask = BIT(0),
1852
1750
.hw.init = &(struct clk_init_data){
1853
1751
.name = "video_maxi_clk",
1854
-
.parent_names = (const char *[]){ "maxi_clk_src" },
1752
+
.parent_hws = (const struct clk_hw*[]){
1753
+
&maxi_clk_src.clkr.hw
1754
+
},
1855
1755
.num_parents = 1,
1856
1756
.flags = CLK_SET_RATE_PARENT,
1857
1757
.ops = &clk_branch2_ops,
···
1868
1764
.enable_mask = BIT(0),
1869
1765
.hw.init = &(struct clk_init_data){
1870
1766
.name = "video_ahb_clk",
1871
-
.parent_names = (const char *[]){ "ahb_clk_src" },
1767
+
.parent_hws = (const struct clk_hw*[]){
1768
+
&ahb_clk_src.clkr.hw
1769
+
},
1872
1770
.num_parents = 1,
1873
1771
.flags = CLK_SET_RATE_PARENT,
1874
1772
.ops = &clk_branch2_ops,
···
1885
1779
.enable_mask = BIT(0),
1886
1780
.hw.init = &(struct clk_init_data){
1887
1781
.name = "video_subcore0_clk",
1888
-
.parent_names = (const char *[]){ "video_subcore0_clk_src" },
1782
+
.parent_hws = (const struct clk_hw*[]){
1783
+
&video_subcore0_clk_src.clkr.hw
1784
+
},
1889
1785
.num_parents = 1,
1890
1786
.flags = CLK_SET_RATE_PARENT,
1891
1787
.ops = &clk_branch2_ops,
···
1902
1794
.enable_mask = BIT(0),
1903
1795
.hw.init = &(struct clk_init_data){
1904
1796
.name = "video_subcore1_clk",
1905
-
.parent_names = (const char *[]){ "video_subcore1_clk_src" },
1797
+
.parent_hws = (const struct clk_hw*[]){
1798
+
&video_subcore1_clk_src.clkr.hw
1799
+
},
1906
1800
.num_parents = 1,
1907
1801
.flags = CLK_SET_RATE_PARENT,
1908
1802
.ops = &clk_branch2_ops,
···
1919
1809
.enable_mask = BIT(0),
1920
1810
.hw.init = &(struct clk_init_data){
1921
1811
.name = "mdss_ahb_clk",
1922
-
.parent_names = (const char *[]){ "ahb_clk_src" },
1812
+
.parent_hws = (const struct clk_hw*[]){
1813
+
&ahb_clk_src.clkr.hw
1814
+
},
1923
1815
.num_parents = 1,
1924
1816
.flags = CLK_SET_RATE_PARENT,
1925
1817
.ops = &clk_branch2_ops,
···
1936
1824
.enable_mask = BIT(0),
1937
1825
.hw.init = &(struct clk_init_data){
1938
1826
.name = "mdss_hdmi_ahb_clk",
1939
-
.parent_names = (const char *[]){ "ahb_clk_src" },
1827
+
.parent_hws = (const struct clk_hw*[]){
1828
+
&ahb_clk_src.clkr.hw
1829
+
},
1940
1830
.num_parents = 1,
1941
1831
.flags = CLK_SET_RATE_PARENT,
1942
1832
.ops = &clk_branch2_ops,
···
1953
1839
.enable_mask = BIT(0),
1954
1840
.hw.init = &(struct clk_init_data){
1955
1841
.name = "mdss_axi_clk",
1956
-
.parent_names = (const char *[]){ "axi_clk_src" },
1842
+
.parent_hws = (const struct clk_hw*[]){
1843
+
&axi_clk_src.clkr.hw
1844
+
},
1957
1845
.num_parents = 1,
1958
1846
.flags = CLK_SET_RATE_PARENT,
1959
1847
.ops = &clk_branch2_ops,
···
1970
1854
.enable_mask = BIT(0),
1971
1855
.hw.init = &(struct clk_init_data){
1972
1856
.name = "mdss_pclk0_clk",
1973
-
.parent_names = (const char *[]){ "pclk0_clk_src" },
1857
+
.parent_hws = (const struct clk_hw*[]){
1858
+
&pclk0_clk_src.clkr.hw
1859
+
},
1974
1860
.num_parents = 1,
1975
1861
.flags = CLK_SET_RATE_PARENT,
1976
1862
.ops = &clk_branch2_ops,
···
1987
1869
.enable_mask = BIT(0),
1988
1870
.hw.init = &(struct clk_init_data){
1989
1871
.name = "mdss_pclk1_clk",
1990
-
.parent_names = (const char *[]){ "pclk1_clk_src" },
1872
+
.parent_hws = (const struct clk_hw*[]){
1873
+
&pclk1_clk_src.clkr.hw
1874
+
},
1991
1875
.num_parents = 1,
1992
1876
.flags = CLK_SET_RATE_PARENT,
1993
1877
.ops = &clk_branch2_ops,
···
2004
1884
.enable_mask = BIT(0),
2005
1885
.hw.init = &(struct clk_init_data){
2006
1886
.name = "mdss_mdp_clk",
2007
-
.parent_names = (const char *[]){ "mdp_clk_src" },
1887
+
.parent_hws = (const struct clk_hw*[]){
1888
+
&mdp_clk_src.clkr.hw
1889
+
},
2008
1890
.num_parents = 1,
2009
1891
.flags = CLK_SET_RATE_PARENT,
2010
1892
.ops = &clk_branch2_ops,
···
2021
1899
.enable_mask = BIT(0),
2022
1900
.hw.init = &(struct clk_init_data){
2023
1901
.name = "mdss_extpclk_clk",
2024
-
.parent_names = (const char *[]){ "extpclk_clk_src" },
1902
+
.parent_hws = (const struct clk_hw*[]){
1903
+
&extpclk_clk_src.clkr.hw
1904
+
},
2025
1905
.num_parents = 1,
2026
1906
.flags = CLK_SET_RATE_PARENT,
2027
1907
.ops = &clk_branch2_ops,
···
2038
1914
.enable_mask = BIT(0),
2039
1915
.hw.init = &(struct clk_init_data){
2040
1916
.name = "mdss_vsync_clk",
2041
-
.parent_names = (const char *[]){ "vsync_clk_src" },
1917
+
.parent_hws = (const struct clk_hw*[]){
1918
+
&vsync_clk_src.clkr.hw
1919
+
},
2042
1920
.num_parents = 1,
2043
1921
.flags = CLK_SET_RATE_PARENT,
2044
1922
.ops = &clk_branch2_ops,
···
2055
1929
.enable_mask = BIT(0),
2056
1930
.hw.init = &(struct clk_init_data){
2057
1931
.name = "mdss_hdmi_clk",
2058
-
.parent_names = (const char *[]){ "hdmi_clk_src" },
1932
+
.parent_hws = (const struct clk_hw*[]){
1933
+
&hdmi_clk_src.clkr.hw
1934
+
},
2059
1935
.num_parents = 1,
2060
1936
.flags = CLK_SET_RATE_PARENT,
2061
1937
.ops = &clk_branch2_ops,
···
2072
1944
.enable_mask = BIT(0),
2073
1945
.hw.init = &(struct clk_init_data){
2074
1946
.name = "mdss_byte0_clk",
2075
-
.parent_names = (const char *[]){ "byte0_clk_src" },
1947
+
.parent_hws = (const struct clk_hw*[]){
1948
+
&byte0_clk_src.clkr.hw
1949
+
},
2076
1950
.num_parents = 1,
2077
1951
.flags = CLK_SET_RATE_PARENT,
2078
1952
.ops = &clk_branch2_ops,
···
2089
1959
.enable_mask = BIT(0),
2090
1960
.hw.init = &(struct clk_init_data){
2091
1961
.name = "mdss_byte1_clk",
2092
-
.parent_names = (const char *[]){ "byte1_clk_src" },
1962
+
.parent_hws = (const struct clk_hw*[]){
1963
+
&byte1_clk_src.clkr.hw
1964
+
},
2093
1965
.num_parents = 1,
2094
1966
.flags = CLK_SET_RATE_PARENT,
2095
1967
.ops = &clk_branch2_ops,
···
2106
1974
.enable_mask = BIT(0),
2107
1975
.hw.init = &(struct clk_init_data){
2108
1976
.name = "mdss_esc0_clk",
2109
-
.parent_names = (const char *[]){ "esc0_clk_src" },
1977
+
.parent_hws = (const struct clk_hw*[]){
1978
+
&esc0_clk_src.clkr.hw
1979
+
},
2110
1980
.num_parents = 1,
2111
1981
.flags = CLK_SET_RATE_PARENT,
2112
1982
.ops = &clk_branch2_ops,
···
2123
1989
.enable_mask = BIT(0),
2124
1990
.hw.init = &(struct clk_init_data){
2125
1991
.name = "mdss_esc1_clk",
2126
-
.parent_names = (const char *[]){ "esc1_clk_src" },
1992
+
.parent_hws = (const struct clk_hw*[]){
1993
+
&esc1_clk_src.clkr.hw
1994
+
},
2127
1995
.num_parents = 1,
2128
1996
.flags = CLK_SET_RATE_PARENT,
2129
1997
.ops = &clk_branch2_ops,
···
2140
2004
.enable_mask = BIT(0),
2141
2005
.hw.init = &(struct clk_init_data){
2142
2006
.name = "camss_top_ahb_clk",
2143
-
.parent_names = (const char *[]){ "ahb_clk_src" },
2007
+
.parent_hws = (const struct clk_hw*[]){
2008
+
&ahb_clk_src.clkr.hw
2009
+
},
2144
2010
.num_parents = 1,
2145
2011
.flags = CLK_SET_RATE_PARENT,
2146
2012
.ops = &clk_branch2_ops,
···
2157
2019
.enable_mask = BIT(0),
2158
2020
.hw.init = &(struct clk_init_data){
2159
2021
.name = "camss_ahb_clk",
2160
-
.parent_names = (const char *[]){ "ahb_clk_src" },
2022
+
.parent_hws = (const struct clk_hw*[]){
2023
+
&ahb_clk_src.clkr.hw
2024
+
},
2161
2025
.num_parents = 1,
2162
2026
.flags = CLK_SET_RATE_PARENT,
2163
2027
.ops = &clk_branch2_ops,
···
2174
2034
.enable_mask = BIT(0),
2175
2035
.hw.init = &(struct clk_init_data){
2176
2036
.name = "camss_micro_ahb_clk",
2177
-
.parent_names = (const char *[]){ "ahb_clk_src" },
2037
+
.parent_hws = (const struct clk_hw*[]){
2038
+
&ahb_clk_src.clkr.hw
2039
+
},
2178
2040
.num_parents = 1,
2179
2041
.flags = CLK_SET_RATE_PARENT,
2180
2042
.ops = &clk_branch2_ops,
···
2191
2049
.enable_mask = BIT(0),
2192
2050
.hw.init = &(struct clk_init_data){
2193
2051
.name = "camss_gp0_clk",
2194
-
.parent_names = (const char *[]){ "camss_gp0_clk_src" },
2052
+
.parent_hws = (const struct clk_hw*[]){
2053
+
&camss_gp0_clk_src.clkr.hw
2054
+
},
2195
2055
.num_parents = 1,
2196
2056
.flags = CLK_SET_RATE_PARENT,
2197
2057
.ops = &clk_branch2_ops,
···
2208
2064
.enable_mask = BIT(0),
2209
2065
.hw.init = &(struct clk_init_data){
2210
2066
.name = "camss_gp1_clk",
2211
-
.parent_names = (const char *[]){ "camss_gp1_clk_src" },
2067
+
.parent_hws = (const struct clk_hw*[]){
2068
+
&camss_gp1_clk_src.clkr.hw
2069
+
},
2212
2070
.num_parents = 1,
2213
2071
.flags = CLK_SET_RATE_PARENT,
2214
2072
.ops = &clk_branch2_ops,
···
2225
2079
.enable_mask = BIT(0),
2226
2080
.hw.init = &(struct clk_init_data){
2227
2081
.name = "camss_mclk0_clk",
2228
-
.parent_names = (const char *[]){ "mclk0_clk_src" },
2082
+
.parent_hws = (const struct clk_hw*[]){
2083
+
&mclk0_clk_src.clkr.hw
2084
+
},
2229
2085
.num_parents = 1,
2230
2086
.flags = CLK_SET_RATE_PARENT,
2231
2087
.ops = &clk_branch2_ops,
···
2242
2094
.enable_mask = BIT(0),
2243
2095
.hw.init = &(struct clk_init_data){
2244
2096
.name = "camss_mclk1_clk",
2245
-
.parent_names = (const char *[]){ "mclk1_clk_src" },
2097
+
.parent_hws = (const struct clk_hw*[]){
2098
+
&mclk1_clk_src.clkr.hw
2099
+
},
2246
2100
.num_parents = 1,
2247
2101
.flags = CLK_SET_RATE_PARENT,
2248
2102
.ops = &clk_branch2_ops,
···
2259
2109
.enable_mask = BIT(0),
2260
2110
.hw.init = &(struct clk_init_data){
2261
2111
.name = "camss_mclk2_clk",
2262
-
.parent_names = (const char *[]){ "mclk2_clk_src" },
2112
+
.parent_hws = (const struct clk_hw*[]){
2113
+
&mclk2_clk_src.clkr.hw
2114
+
},
2263
2115
.num_parents = 1,
2264
2116
.flags = CLK_SET_RATE_PARENT,
2265
2117
.ops = &clk_branch2_ops,
···
2276
2124
.enable_mask = BIT(0),
2277
2125
.hw.init = &(struct clk_init_data){
2278
2126
.name = "camss_mclk3_clk",
2279
-
.parent_names = (const char *[]){ "mclk3_clk_src" },
2127
+
.parent_hws = (const struct clk_hw*[]){
2128
+
&mclk3_clk_src.clkr.hw
2129
+
},
2280
2130
.num_parents = 1,
2281
2131
.flags = CLK_SET_RATE_PARENT,
2282
2132
.ops = &clk_branch2_ops,
···
2293
2139
.enable_mask = BIT(0),
2294
2140
.hw.init = &(struct clk_init_data){
2295
2141
.name = "camss_cci_clk",
2296
-
.parent_names = (const char *[]){ "cci_clk_src" },
2142
+
.parent_hws = (const struct clk_hw*[]){
2143
+
&cci_clk_src.clkr.hw
2144
+
},
2297
2145
.num_parents = 1,
2298
2146
.flags = CLK_SET_RATE_PARENT,
2299
2147
.ops = &clk_branch2_ops,
···
2310
2154
.enable_mask = BIT(0),
2311
2155
.hw.init = &(struct clk_init_data){
2312
2156
.name = "camss_cci_ahb_clk",
2313
-
.parent_names = (const char *[]){ "ahb_clk_src" },
2157
+
.parent_hws = (const struct clk_hw*[]){
2158
+
&ahb_clk_src.clkr.hw
2159
+
},
2314
2160
.num_parents = 1,
2315
2161
.flags = CLK_SET_RATE_PARENT,
2316
2162
.ops = &clk_branch2_ops,
···
2327
2169
.enable_mask = BIT(0),
2328
2170
.hw.init = &(struct clk_init_data){
2329
2171
.name = "camss_csi0phytimer_clk",
2330
-
.parent_names = (const char *[]){ "csi0phytimer_clk_src" },
2172
+
.parent_hws = (const struct clk_hw*[]){
2173
+
&csi0phytimer_clk_src.clkr.hw
2174
+
},
2331
2175
.num_parents = 1,
2332
2176
.flags = CLK_SET_RATE_PARENT,
2333
2177
.ops = &clk_branch2_ops,
···
2344
2184
.enable_mask = BIT(0),
2345
2185
.hw.init = &(struct clk_init_data){
2346
2186
.name = "camss_csi1phytimer_clk",
2347
-
.parent_names = (const char *[]){ "csi1phytimer_clk_src" },
2187
+
.parent_hws = (const struct clk_hw*[]){
2188
+
&csi1phytimer_clk_src.clkr.hw
2189
+
},
2348
2190
.num_parents = 1,
2349
2191
.flags = CLK_SET_RATE_PARENT,
2350
2192
.ops = &clk_branch2_ops,
···
2361
2199
.enable_mask = BIT(0),
2362
2200
.hw.init = &(struct clk_init_data){
2363
2201
.name = "camss_csi2phytimer_clk",
2364
-
.parent_names = (const char *[]){ "csi2phytimer_clk_src" },
2202
+
.parent_hws = (const struct clk_hw*[]){
2203
+
&csi2phytimer_clk_src.clkr.hw
2204
+
},
2365
2205
.num_parents = 1,
2366
2206
.flags = CLK_SET_RATE_PARENT,
2367
2207
.ops = &clk_branch2_ops,
···
2378
2214
.enable_mask = BIT(0),
2379
2215
.hw.init = &(struct clk_init_data){
2380
2216
.name = "camss_csiphy0_3p_clk",
2381
-
.parent_names = (const char *[]){ "csiphy0_3p_clk_src" },
2217
+
.parent_hws = (const struct clk_hw*[]){
2218
+
&csiphy0_3p_clk_src.clkr.hw
2219
+
},
2382
2220
.num_parents = 1,
2383
2221
.flags = CLK_SET_RATE_PARENT,
2384
2222
.ops = &clk_branch2_ops,
···
2395
2229
.enable_mask = BIT(0),
2396
2230
.hw.init = &(struct clk_init_data){
2397
2231
.name = "camss_csiphy1_3p_clk",
2398
-
.parent_names = (const char *[]){ "csiphy1_3p_clk_src" },
2232
+
.parent_hws = (const struct clk_hw*[]){
2233
+
&csiphy1_3p_clk_src.clkr.hw
2234
+
},
2399
2235
.num_parents = 1,
2400
2236
.flags = CLK_SET_RATE_PARENT,
2401
2237
.ops = &clk_branch2_ops,
···
2412
2244
.enable_mask = BIT(0),
2413
2245
.hw.init = &(struct clk_init_data){
2414
2246
.name = "camss_csiphy2_3p_clk",
2415
-
.parent_names = (const char *[]){ "csiphy2_3p_clk_src" },
2247
+
.parent_hws = (const struct clk_hw*[]){
2248
+
&csiphy2_3p_clk_src.clkr.hw
2249
+
},
2416
2250
.num_parents = 1,
2417
2251
.flags = CLK_SET_RATE_PARENT,
2418
2252
.ops = &clk_branch2_ops,
···
2429
2259
.enable_mask = BIT(0),
2430
2260
.hw.init = &(struct clk_init_data){
2431
2261
.name = "camss_jpeg0_clk",
2432
-
.parent_names = (const char *[]){ "jpeg0_clk_src" },
2262
+
.parent_hws = (const struct clk_hw*[]){
2263
+
&jpeg0_clk_src.clkr.hw
2264
+
},
2433
2265
.num_parents = 1,
2434
2266
.flags = CLK_SET_RATE_PARENT,
2435
2267
.ops = &clk_branch2_ops,
···
2446
2274
.enable_mask = BIT(0),
2447
2275
.hw.init = &(struct clk_init_data){
2448
2276
.name = "camss_jpeg2_clk",
2449
-
.parent_names = (const char *[]){ "jpeg2_clk_src" },
2277
+
.parent_hws = (const struct clk_hw*[]){
2278
+
&jpeg2_clk_src.clkr.hw
2279
+
},
2450
2280
.num_parents = 1,
2451
2281
.flags = CLK_SET_RATE_PARENT,
2452
2282
.ops = &clk_branch2_ops,
···
2463
2289
.enable_mask = BIT(0),
2464
2290
.hw.init = &(struct clk_init_data){
2465
2291
.name = "camss_jpeg_dma_clk",
2466
-
.parent_names = (const char *[]){ "jpeg_dma_clk_src" },
2292
+
.parent_hws = (const struct clk_hw*[]){
2293
+
&jpeg_dma_clk_src.clkr.hw
2294
+
},
2467
2295
.num_parents = 1,
2468
2296
.flags = CLK_SET_RATE_PARENT,
2469
2297
.ops = &clk_branch2_ops,
···
2480
2304
.enable_mask = BIT(0),
2481
2305
.hw.init = &(struct clk_init_data){
2482
2306
.name = "camss_jpeg_ahb_clk",
2483
-
.parent_names = (const char *[]){ "ahb_clk_src" },
2307
+
.parent_hws = (const struct clk_hw*[]){
2308
+
&ahb_clk_src.clkr.hw
2309
+
},
2484
2310
.num_parents = 1,
2485
2311
.flags = CLK_SET_RATE_PARENT,
2486
2312
.ops = &clk_branch2_ops,
···
2497
2319
.enable_mask = BIT(0),
2498
2320
.hw.init = &(struct clk_init_data){
2499
2321
.name = "camss_jpeg_axi_clk",
2500
-
.parent_names = (const char *[]){ "axi_clk_src" },
2322
+
.parent_hws = (const struct clk_hw*[]){
2323
+
&axi_clk_src.clkr.hw
2324
+
},
2501
2325
.num_parents = 1,
2502
2326
.flags = CLK_SET_RATE_PARENT,
2503
2327
.ops = &clk_branch2_ops,
···
2514
2334
.enable_mask = BIT(0),
2515
2335
.hw.init = &(struct clk_init_data){
2516
2336
.name = "camss_vfe_ahb_clk",
2517
-
.parent_names = (const char *[]){ "ahb_clk_src" },
2337
+
.parent_hws = (const struct clk_hw*[]){
2338
+
&ahb_clk_src.clkr.hw
2339
+
},
2518
2340
.num_parents = 1,
2519
2341
.flags = CLK_SET_RATE_PARENT,
2520
2342
.ops = &clk_branch2_ops,
···
2531
2349
.enable_mask = BIT(0),
2532
2350
.hw.init = &(struct clk_init_data){
2533
2351
.name = "camss_vfe_axi_clk",
2534
-
.parent_names = (const char *[]){ "axi_clk_src" },
2352
+
.parent_hws = (const struct clk_hw*[]){
2353
+
&axi_clk_src.clkr.hw
2354
+
},
2535
2355
.num_parents = 1,
2536
2356
.flags = CLK_SET_RATE_PARENT,
2537
2357
.ops = &clk_branch2_ops,
···
2548
2364
.enable_mask = BIT(0),
2549
2365
.hw.init = &(struct clk_init_data){
2550
2366
.name = "camss_vfe0_clk",
2551
-
.parent_names = (const char *[]){ "vfe0_clk_src" },
2367
+
.parent_hws = (const struct clk_hw*[]){
2368
+
&vfe0_clk_src.clkr.hw
2369
+
},
2552
2370
.num_parents = 1,
2553
2371
.flags = CLK_SET_RATE_PARENT,
2554
2372
.ops = &clk_branch2_ops,
···
2565
2379
.enable_mask = BIT(0),
2566
2380
.hw.init = &(struct clk_init_data){
2567
2381
.name = "camss_vfe0_stream_clk",
2568
-
.parent_names = (const char *[]){ "vfe0_clk_src" },
2382
+
.parent_hws = (const struct clk_hw*[]){
2383
+
&vfe0_clk_src.clkr.hw
2384
+
},
2569
2385
.num_parents = 1,
2570
2386
.flags = CLK_SET_RATE_PARENT,
2571
2387
.ops = &clk_branch2_ops,
···
2582
2394
.enable_mask = BIT(0),
2583
2395
.hw.init = &(struct clk_init_data){
2584
2396
.name = "camss_vfe0_ahb_clk",
2585
-
.parent_names = (const char *[]){ "ahb_clk_src" },
2397
+
.parent_hws = (const struct clk_hw*[]){
2398
+
&ahb_clk_src.clkr.hw
2399
+
},
2586
2400
.num_parents = 1,
2587
2401
.flags = CLK_SET_RATE_PARENT,
2588
2402
.ops = &clk_branch2_ops,
···
2599
2409
.enable_mask = BIT(0),
2600
2410
.hw.init = &(struct clk_init_data){
2601
2411
.name = "camss_vfe1_clk",
2602
-
.parent_names = (const char *[]){ "vfe1_clk_src" },
2412
+
.parent_hws = (const struct clk_hw*[]){
2413
+
&vfe1_clk_src.clkr.hw
2414
+
},
2603
2415
.num_parents = 1,
2604
2416
.flags = CLK_SET_RATE_PARENT,
2605
2417
.ops = &clk_branch2_ops,
···
2616
2424
.enable_mask = BIT(0),
2617
2425
.hw.init = &(struct clk_init_data){
2618
2426
.name = "camss_vfe1_stream_clk",
2619
-
.parent_names = (const char *[]){ "vfe1_clk_src" },
2427
+
.parent_hws = (const struct clk_hw*[]){
2428
+
&vfe1_clk_src.clkr.hw
2429
+
},
2620
2430
.num_parents = 1,
2621
2431
.flags = CLK_SET_RATE_PARENT,
2622
2432
.ops = &clk_branch2_ops,
···
2633
2439
.enable_mask = BIT(0),
2634
2440
.hw.init = &(struct clk_init_data){
2635
2441
.name = "camss_vfe1_ahb_clk",
2636
-
.parent_names = (const char *[]){ "ahb_clk_src" },
2442
+
.parent_hws = (const struct clk_hw*[]){
2443
+
&ahb_clk_src.clkr.hw
2444
+
},
2637
2445
.num_parents = 1,
2638
2446
.flags = CLK_SET_RATE_PARENT,
2639
2447
.ops = &clk_branch2_ops,
···
2650
2454
.enable_mask = BIT(0),
2651
2455
.hw.init = &(struct clk_init_data){
2652
2456
.name = "camss_csi_vfe0_clk",
2653
-
.parent_names = (const char *[]){ "vfe0_clk_src" },
2457
+
.parent_hws = (const struct clk_hw*[]){
2458
+
&vfe0_clk_src.clkr.hw
2459
+
},
2654
2460
.num_parents = 1,
2655
2461
.flags = CLK_SET_RATE_PARENT,
2656
2462
.ops = &clk_branch2_ops,
···
2667
2469
.enable_mask = BIT(0),
2668
2470
.hw.init = &(struct clk_init_data){
2669
2471
.name = "camss_csi_vfe1_clk",
2670
-
.parent_names = (const char *[]){ "vfe1_clk_src" },
2472
+
.parent_hws = (const struct clk_hw*[]){
2473
+
&vfe1_clk_src.clkr.hw
2474
+
},
2671
2475
.num_parents = 1,
2672
2476
.flags = CLK_SET_RATE_PARENT,
2673
2477
.ops = &clk_branch2_ops,
···
2684
2484
.enable_mask = BIT(0),
2685
2485
.hw.init = &(struct clk_init_data){
2686
2486
.name = "camss_cpp_vbif_ahb_clk",
2687
-
.parent_names = (const char *[]){ "ahb_clk_src" },
2487
+
.parent_hws = (const struct clk_hw*[]){
2488
+
&ahb_clk_src.clkr.hw
2489
+
},
2688
2490
.num_parents = 1,
2689
2491
.flags = CLK_SET_RATE_PARENT,
2690
2492
.ops = &clk_branch2_ops,
···
2701
2499
.enable_mask = BIT(0),
2702
2500
.hw.init = &(struct clk_init_data){
2703
2501
.name = "camss_cpp_axi_clk",
2704
-
.parent_names = (const char *[]){ "axi_clk_src" },
2502
+
.parent_hws = (const struct clk_hw*[]){
2503
+
&axi_clk_src.clkr.hw
2504
+
},
2705
2505
.num_parents = 1,
2706
2506
.flags = CLK_SET_RATE_PARENT,
2707
2507
.ops = &clk_branch2_ops,
···
2718
2514
.enable_mask = BIT(0),
2719
2515
.hw.init = &(struct clk_init_data){
2720
2516
.name = "camss_cpp_clk",
2721
-
.parent_names = (const char *[]){ "cpp_clk_src" },
2517
+
.parent_hws = (const struct clk_hw*[]){
2518
+
&cpp_clk_src.clkr.hw
2519
+
},
2722
2520
.num_parents = 1,
2723
2521
.flags = CLK_SET_RATE_PARENT,
2724
2522
.ops = &clk_branch2_ops,
···
2735
2529
.enable_mask = BIT(0),
2736
2530
.hw.init = &(struct clk_init_data){
2737
2531
.name = "camss_cpp_ahb_clk",
2738
-
.parent_names = (const char *[]){ "ahb_clk_src" },
2532
+
.parent_hws = (const struct clk_hw*[]){
2533
+
&ahb_clk_src.clkr.hw
2534
+
},
2739
2535
.num_parents = 1,
2740
2536
.flags = CLK_SET_RATE_PARENT,
2741
2537
.ops = &clk_branch2_ops,
···
2752
2544
.enable_mask = BIT(0),
2753
2545
.hw.init = &(struct clk_init_data){
2754
2546
.name = "camss_csi0_clk",
2755
-
.parent_names = (const char *[]){ "csi0_clk_src" },
2547
+
.parent_hws = (const struct clk_hw*[]){
2548
+
&csi0_clk_src.clkr.hw
2549
+
},
2756
2550
.num_parents = 1,
2757
2551
.flags = CLK_SET_RATE_PARENT,
2758
2552
.ops = &clk_branch2_ops,
···
2769
2559
.enable_mask = BIT(0),
2770
2560
.hw.init = &(struct clk_init_data){
2771
2561
.name = "camss_csi0_ahb_clk",
2772
-
.parent_names = (const char *[]){ "ahb_clk_src" },
2562
+
.parent_hws = (const struct clk_hw*[]){
2563
+
&ahb_clk_src.clkr.hw
2564
+
},
2773
2565
.num_parents = 1,
2774
2566
.flags = CLK_SET_RATE_PARENT,
2775
2567
.ops = &clk_branch2_ops,
···
2786
2574
.enable_mask = BIT(0),
2787
2575
.hw.init = &(struct clk_init_data){
2788
2576
.name = "camss_csi0phy_clk",
2789
-
.parent_names = (const char *[]){ "csi0_clk_src" },
2577
+
.parent_hws = (const struct clk_hw*[]){
2578
+
&csi0_clk_src.clkr.hw
2579
+
},
2790
2580
.num_parents = 1,
2791
2581
.flags = CLK_SET_RATE_PARENT,
2792
2582
.ops = &clk_branch2_ops,
···
2803
2589
.enable_mask = BIT(0),
2804
2590
.hw.init = &(struct clk_init_data){
2805
2591
.name = "camss_csi0rdi_clk",
2806
-
.parent_names = (const char *[]){ "csi0_clk_src" },
2592
+
.parent_hws = (const struct clk_hw*[]){
2593
+
&csi0_clk_src.clkr.hw
2594
+
},
2807
2595
.num_parents = 1,
2808
2596
.flags = CLK_SET_RATE_PARENT,
2809
2597
.ops = &clk_branch2_ops,
···
2820
2604
.enable_mask = BIT(0),
2821
2605
.hw.init = &(struct clk_init_data){
2822
2606
.name = "camss_csi0pix_clk",
2823
-
.parent_names = (const char *[]){ "csi0_clk_src" },
2607
+
.parent_hws = (const struct clk_hw*[]){
2608
+
&csi0_clk_src.clkr.hw
2609
+
},
2824
2610
.num_parents = 1,
2825
2611
.flags = CLK_SET_RATE_PARENT,
2826
2612
.ops = &clk_branch2_ops,
···
2837
2619
.enable_mask = BIT(0),
2838
2620
.hw.init = &(struct clk_init_data){
2839
2621
.name = "camss_csi1_clk",
2840
-
.parent_names = (const char *[]){ "csi1_clk_src" },
2622
+
.parent_hws = (const struct clk_hw*[]){
2623
+
&csi1_clk_src.clkr.hw
2624
+
},
2841
2625
.num_parents = 1,
2842
2626
.flags = CLK_SET_RATE_PARENT,
2843
2627
.ops = &clk_branch2_ops,
···
2854
2634
.enable_mask = BIT(0),
2855
2635
.hw.init = &(struct clk_init_data){
2856
2636
.name = "camss_csi1_ahb_clk",
2857
-
.parent_names = (const char *[]){ "ahb_clk_src" },
2637
+
.parent_hws = (const struct clk_hw*[]){
2638
+
&ahb_clk_src.clkr.hw
2639
+
},
2858
2640
.num_parents = 1,
2859
2641
.flags = CLK_SET_RATE_PARENT,
2860
2642
.ops = &clk_branch2_ops,
···
2871
2649
.enable_mask = BIT(0),
2872
2650
.hw.init = &(struct clk_init_data){
2873
2651
.name = "camss_csi1phy_clk",
2874
-
.parent_names = (const char *[]){ "csi1_clk_src" },
2652
+
.parent_hws = (const struct clk_hw*[]){
2653
+
&csi1_clk_src.clkr.hw
2654
+
},
2875
2655
.num_parents = 1,
2876
2656
.flags = CLK_SET_RATE_PARENT,
2877
2657
.ops = &clk_branch2_ops,
···
2888
2664
.enable_mask = BIT(0),
2889
2665
.hw.init = &(struct clk_init_data){
2890
2666
.name = "camss_csi1rdi_clk",
2891
-
.parent_names = (const char *[]){ "csi1_clk_src" },
2667
+
.parent_hws = (const struct clk_hw*[]){
2668
+
&csi1_clk_src.clkr.hw
2669
+
},
2892
2670
.num_parents = 1,
2893
2671
.flags = CLK_SET_RATE_PARENT,
2894
2672
.ops = &clk_branch2_ops,
···
2905
2679
.enable_mask = BIT(0),
2906
2680
.hw.init = &(struct clk_init_data){
2907
2681
.name = "camss_csi1pix_clk",
2908
-
.parent_names = (const char *[]){ "csi1_clk_src" },
2682
+
.parent_hws = (const struct clk_hw*[]){
2683
+
&csi1_clk_src.clkr.hw
2684
+
},
2909
2685
.num_parents = 1,
2910
2686
.flags = CLK_SET_RATE_PARENT,
2911
2687
.ops = &clk_branch2_ops,
···
2922
2694
.enable_mask = BIT(0),
2923
2695
.hw.init = &(struct clk_init_data){
2924
2696
.name = "camss_csi2_clk",
2925
-
.parent_names = (const char *[]){ "csi2_clk_src" },
2697
+
.parent_hws = (const struct clk_hw*[]){
2698
+
&csi2_clk_src.clkr.hw
2699
+
},
2926
2700
.num_parents = 1,
2927
2701
.flags = CLK_SET_RATE_PARENT,
2928
2702
.ops = &clk_branch2_ops,
···
2939
2709
.enable_mask = BIT(0),
2940
2710
.hw.init = &(struct clk_init_data){
2941
2711
.name = "camss_csi2_ahb_clk",
2942
-
.parent_names = (const char *[]){ "ahb_clk_src" },
2712
+
.parent_hws = (const struct clk_hw*[]){
2713
+
&ahb_clk_src.clkr.hw
2714
+
},
2943
2715
.num_parents = 1,
2944
2716
.flags = CLK_SET_RATE_PARENT,
2945
2717
.ops = &clk_branch2_ops,
···
2956
2724
.enable_mask = BIT(0),
2957
2725
.hw.init = &(struct clk_init_data){
2958
2726
.name = "camss_csi2phy_clk",
2959
-
.parent_names = (const char *[]){ "csi2_clk_src" },
2727
+
.parent_hws = (const struct clk_hw*[]){
2728
+
&csi2_clk_src.clkr.hw
2729
+
},
2960
2730
.num_parents = 1,
2961
2731
.flags = CLK_SET_RATE_PARENT,
2962
2732
.ops = &clk_branch2_ops,
···
2973
2739
.enable_mask = BIT(0),
2974
2740
.hw.init = &(struct clk_init_data){
2975
2741
.name = "camss_csi2rdi_clk",
2976
-
.parent_names = (const char *[]){ "csi2_clk_src" },
2742
+
.parent_hws = (const struct clk_hw*[]){
2743
+
&csi2_clk_src.clkr.hw
2744
+
},
2977
2745
.num_parents = 1,
2978
2746
.flags = CLK_SET_RATE_PARENT,
2979
2747
.ops = &clk_branch2_ops,
···
2990
2754
.enable_mask = BIT(0),
2991
2755
.hw.init = &(struct clk_init_data){
2992
2756
.name = "camss_csi2pix_clk",
2993
-
.parent_names = (const char *[]){ "csi2_clk_src" },
2757
+
.parent_hws = (const struct clk_hw*[]){
2758
+
&csi2_clk_src.clkr.hw
2759
+
},
2994
2760
.num_parents = 1,
2995
2761
.flags = CLK_SET_RATE_PARENT,
2996
2762
.ops = &clk_branch2_ops,
···
3007
2769
.enable_mask = BIT(0),
3008
2770
.hw.init = &(struct clk_init_data){
3009
2771
.name = "camss_csi3_clk",
3010
-
.parent_names = (const char *[]){ "csi3_clk_src" },
2772
+
.parent_hws = (const struct clk_hw*[]){
2773
+
&csi3_clk_src.clkr.hw
2774
+
},
3011
2775
.num_parents = 1,
3012
2776
.flags = CLK_SET_RATE_PARENT,
3013
2777
.ops = &clk_branch2_ops,
···
3024
2784
.enable_mask = BIT(0),
3025
2785
.hw.init = &(struct clk_init_data){
3026
2786
.name = "camss_csi3_ahb_clk",
3027
-
.parent_names = (const char *[]){ "ahb_clk_src" },
2787
+
.parent_hws = (const struct clk_hw*[]){
2788
+
&ahb_clk_src.clkr.hw
2789
+
},
3028
2790
.num_parents = 1,
3029
2791
.flags = CLK_SET_RATE_PARENT,
3030
2792
.ops = &clk_branch2_ops,
···
3041
2799
.enable_mask = BIT(0),
3042
2800
.hw.init = &(struct clk_init_data){
3043
2801
.name = "camss_csi3phy_clk",
3044
-
.parent_names = (const char *[]){ "csi3_clk_src" },
2802
+
.parent_hws = (const struct clk_hw*[]){
2803
+
&csi3_clk_src.clkr.hw
2804
+
},
3045
2805
.num_parents = 1,
3046
2806
.flags = CLK_SET_RATE_PARENT,
3047
2807
.ops = &clk_branch2_ops,
···
3058
2814
.enable_mask = BIT(0),
3059
2815
.hw.init = &(struct clk_init_data){
3060
2816
.name = "camss_csi3rdi_clk",
3061
-
.parent_names = (const char *[]){ "csi3_clk_src" },
2817
+
.parent_hws = (const struct clk_hw*[]){
2818
+
&csi3_clk_src.clkr.hw
2819
+
},
3062
2820
.num_parents = 1,
3063
2821
.flags = CLK_SET_RATE_PARENT,
3064
2822
.ops = &clk_branch2_ops,
···
3075
2829
.enable_mask = BIT(0),
3076
2830
.hw.init = &(struct clk_init_data){
3077
2831
.name = "camss_csi3pix_clk",
3078
-
.parent_names = (const char *[]){ "csi3_clk_src" },
2832
+
.parent_hws = (const struct clk_hw*[]){
2833
+
&csi3_clk_src.clkr.hw
2834
+
},
3079
2835
.num_parents = 1,
3080
2836
.flags = CLK_SET_RATE_PARENT,
3081
2837
.ops = &clk_branch2_ops,
···
3092
2844
.enable_mask = BIT(0),
3093
2845
.hw.init = &(struct clk_init_data){
3094
2846
.name = "camss_ispif_ahb_clk",
3095
-
.parent_names = (const char *[]){ "ahb_clk_src" },
2847
+
.parent_hws = (const struct clk_hw*[]){
2848
+
&ahb_clk_src.clkr.hw
2849
+
},
3096
2850
.num_parents = 1,
3097
2851
.flags = CLK_SET_RATE_PARENT,
3098
2852
.ops = &clk_branch2_ops,
···
3109
2859
.enable_mask = BIT(0),
3110
2860
.hw.init = &(struct clk_init_data){
3111
2861
.name = "fd_core_clk",
3112
-
.parent_names = (const char *[]){ "fd_core_clk_src" },
2862
+
.parent_hws = (const struct clk_hw*[]){
2863
+
&fd_core_clk_src.clkr.hw
2864
+
},
3113
2865
.num_parents = 1,
3114
2866
.flags = CLK_SET_RATE_PARENT,
3115
2867
.ops = &clk_branch2_ops,
···
3126
2874
.enable_mask = BIT(0),
3127
2875
.hw.init = &(struct clk_init_data){
3128
2876
.name = "fd_core_uar_clk",
3129
-
.parent_names = (const char *[]){ "fd_core_clk_src" },
2877
+
.parent_hws = (const struct clk_hw*[]){
2878
+
&fd_core_clk_src.clkr.hw
2879
+
},
3130
2880
.num_parents = 1,
3131
2881
.flags = CLK_SET_RATE_PARENT,
3132
2882
.ops = &clk_branch2_ops,
···
3143
2889
.enable_mask = BIT(0),
3144
2890
.hw.init = &(struct clk_init_data){
3145
2891
.name = "fd_ahb_clk",
3146
-
.parent_names = (const char *[]){ "ahb_clk_src" },
2892
+
.parent_hws = (const struct clk_hw*[]){
2893
+
&ahb_clk_src.clkr.hw
2894
+
},
3147
2895
.num_parents = 1,
3148
2896
.flags = CLK_SET_RATE_PARENT,
3149
2897
.ops = &clk_branch2_ops,
-4
drivers/clk/qcom/videocc-sm8250.c
-4
drivers/clk/qcom/videocc-sm8250.c
···
277
277
},
278
278
.flags = 0,
279
279
.pwrsts = PWRSTS_OFF_ON,
280
-
.supply = "mmcx",
281
280
};
282
281
283
282
static struct gdsc mvs1c_gdsc = {
···
286
287
},
287
288
.flags = 0,
288
289
.pwrsts = PWRSTS_OFF_ON,
289
-
.supply = "mmcx",
290
290
};
291
291
292
292
static struct gdsc mvs0_gdsc = {
···
295
297
},
296
298
.flags = HW_CTRL,
297
299
.pwrsts = PWRSTS_OFF_ON,
298
-
.supply = "mmcx",
299
300
};
300
301
301
302
static struct gdsc mvs1_gdsc = {
···
304
307
},
305
308
.flags = HW_CTRL,
306
309
.pwrsts = PWRSTS_OFF_ON,
307
-
.supply = "mmcx",
308
310
};
309
311
310
312
static struct clk_regmap *video_cc_sm8250_clocks[] = {
+11
-11
drivers/clk/renesas/clk-r8a73a4.c
+11
-11
drivers/clk/renesas/clk-r8a73a4.c
···
18
18
struct r8a73a4_cpg {
19
19
struct clk_onecell_data data;
20
20
spinlock_t lock;
21
-
void __iomem *reg;
22
21
};
23
22
24
23
#define CPG_CKSCR 0xc0
···
58
59
59
60
static struct clk * __init
60
61
r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg,
61
-
const char *name)
62
+
void __iomem *base, const char *name)
62
63
{
63
64
const struct clk_div_table *table = NULL;
64
65
const char *parent_name;
···
68
69
69
70
70
71
if (!strcmp(name, "main")) {
71
-
u32 ckscr = readl(cpg->reg + CPG_CKSCR);
72
+
u32 ckscr = readl(base + CPG_CKSCR);
72
73
73
74
switch ((ckscr >> 28) & 3) {
74
75
case 0: /* extal1 */
···
92
93
* clock implementation and we currently have no need to change
93
94
* the multiplier value.
94
95
*/
95
-
u32 value = readl(cpg->reg + CPG_PLL0CR);
96
+
u32 value = readl(base + CPG_PLL0CR);
96
97
97
98
parent_name = "main";
98
99
mult = ((value >> 24) & 0x7f) + 1;
99
100
if (value & BIT(20))
100
101
div = 2;
101
102
} else if (!strcmp(name, "pll1")) {
102
-
u32 value = readl(cpg->reg + CPG_PLL1CR);
103
+
u32 value = readl(base + CPG_PLL1CR);
103
104
104
105
parent_name = "main";
105
106
/* XXX: enable bit? */
···
122
123
default:
123
124
return ERR_PTR(-EINVAL);
124
125
}
125
-
value = readl(cpg->reg + cr);
126
+
value = readl(base + cr);
126
127
switch ((value >> 5) & 7) {
127
128
case 0:
128
129
parent_name = "main";
···
158
159
shift = 0;
159
160
}
160
161
div *= 32;
161
-
mult = 0x20 - ((readl(cpg->reg + CPG_FRQCRC) >> shift) & 0x1f);
162
+
mult = 0x20 - ((readl(base + CPG_FRQCRC) >> shift) & 0x1f);
162
163
} else {
163
164
struct div4_clk *c;
164
165
···
180
181
mult, div);
181
182
} else {
182
183
return clk_register_divider_table(NULL, name, parent_name, 0,
183
-
cpg->reg + reg, shift, 4, 0,
184
+
base + reg, shift, 4, 0,
184
185
table, &cpg->lock);
185
186
}
186
187
}
···
188
189
static void __init r8a73a4_cpg_clocks_init(struct device_node *np)
189
190
{
190
191
struct r8a73a4_cpg *cpg;
192
+
void __iomem *base;
191
193
struct clk **clks;
192
194
unsigned int i;
193
195
int num_clks;
···
213
213
cpg->data.clks = clks;
214
214
cpg->data.clk_num = num_clks;
215
215
216
-
cpg->reg = of_iomap(np, 0);
217
-
if (WARN_ON(cpg->reg == NULL))
216
+
base = of_iomap(np, 0);
217
+
if (WARN_ON(base == NULL))
218
218
return;
219
219
220
220
for (i = 0; i < num_clks; ++i) {
···
224
224
of_property_read_string_index(np, "clock-output-names", i,
225
225
&name);
226
226
227
-
clk = r8a73a4_cpg_register_clock(np, cpg, name);
227
+
clk = r8a73a4_cpg_register_clock(np, cpg, base, name);
228
228
if (IS_ERR(clk))
229
229
pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
230
230
__func__, np, name, PTR_ERR(clk));
+10
-10
drivers/clk/renesas/clk-r8a7740.c
+10
-10
drivers/clk/renesas/clk-r8a7740.c
···
18
18
struct r8a7740_cpg {
19
19
struct clk_onecell_data data;
20
20
spinlock_t lock;
21
-
void __iomem *reg;
22
21
};
23
22
24
23
#define CPG_FRQCRA 0x00
···
60
61
61
62
static struct clk * __init
62
63
r8a7740_cpg_register_clock(struct device_node *np, struct r8a7740_cpg *cpg,
63
-
const char *name)
64
+
void __iomem *base, const char *name)
64
65
{
65
66
const struct clk_div_table *table = NULL;
66
67
const char *parent_name;
···
95
96
* clock implementation and we currently have no need to change
96
97
* the multiplier value.
97
98
*/
98
-
u32 value = readl(cpg->reg + CPG_FRQCRC);
99
+
u32 value = readl(base + CPG_FRQCRC);
99
100
parent_name = "system";
100
101
mult = ((value >> 24) & 0x7f) + 1;
101
102
} else if (!strcmp(name, "pllc1")) {
102
-
u32 value = readl(cpg->reg + CPG_FRQCRA);
103
+
u32 value = readl(base + CPG_FRQCRA);
103
104
parent_name = "system";
104
105
mult = ((value >> 24) & 0x7f) + 1;
105
106
div = 2;
106
107
} else if (!strcmp(name, "pllc2")) {
107
-
u32 value = readl(cpg->reg + CPG_PLLC2CR);
108
+
u32 value = readl(base + CPG_PLLC2CR);
108
109
parent_name = "system";
109
110
mult = ((value >> 24) & 0x3f) + 1;
110
111
} else if (!strcmp(name, "usb24s")) {
111
-
u32 value = readl(cpg->reg + CPG_USBCKCR);
112
+
u32 value = readl(base + CPG_USBCKCR);
112
113
if (value & BIT(7))
113
114
/* extal2 */
114
115
parent_name = of_clk_get_parent_name(np, 1);
···
136
137
mult, div);
137
138
} else {
138
139
return clk_register_divider_table(NULL, name, parent_name, 0,
139
-
cpg->reg + reg, shift, 4, 0,
140
+
base + reg, shift, 4, 0,
140
141
table, &cpg->lock);
141
142
}
142
143
}
···
144
145
static void __init r8a7740_cpg_clocks_init(struct device_node *np)
145
146
{
146
147
struct r8a7740_cpg *cpg;
148
+
void __iomem *base;
147
149
struct clk **clks;
148
150
unsigned int i;
149
151
int num_clks;
···
172
172
cpg->data.clks = clks;
173
173
cpg->data.clk_num = num_clks;
174
174
175
-
cpg->reg = of_iomap(np, 0);
176
-
if (WARN_ON(cpg->reg == NULL))
175
+
base = of_iomap(np, 0);
176
+
if (WARN_ON(base == NULL))
177
177
return;
178
178
179
179
for (i = 0; i < num_clks; ++i) {
···
183
183
of_property_read_string_index(np, "clock-output-names", i,
184
184
&name);
185
185
186
-
clk = r8a7740_cpg_register_clock(np, cpg, name);
186
+
clk = r8a7740_cpg_register_clock(np, cpg, base, name);
187
187
if (IS_ERR(clk))
188
188
pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
189
189
__func__, np, name, PTR_ERR(clk));
+9
-22
drivers/clk/renesas/clk-r8a7778.c
+9
-22
drivers/clk/renesas/clk-r8a7778.c
···
11
11
#include <linux/slab.h>
12
12
#include <linux/soc/renesas/rcar-rst.h>
13
13
14
-
struct r8a7778_cpg {
15
-
struct clk_onecell_data data;
16
-
spinlock_t lock;
17
-
void __iomem *reg;
18
-
};
19
-
20
14
/* PLL multipliers per bits 11, 12, and 18 of MODEMR */
21
15
static const struct {
22
16
unsigned long plla_mult;
···
41
47
static u32 cpg_mode_divs __initdata;
42
48
43
49
static struct clk * __init
44
-
r8a7778_cpg_register_clock(struct device_node *np, struct r8a7778_cpg *cpg,
45
-
const char *name)
50
+
r8a7778_cpg_register_clock(struct device_node *np, const char *name)
46
51
{
47
52
if (!strcmp(name, "plla")) {
48
53
return clk_register_fixed_factor(NULL, "plla",
···
70
77
71
78
static void __init r8a7778_cpg_clocks_init(struct device_node *np)
72
79
{
73
-
struct r8a7778_cpg *cpg;
80
+
struct clk_onecell_data *data;
74
81
struct clk **clks;
75
82
unsigned int i;
76
83
int num_clks;
···
93
100
return;
94
101
}
95
102
96
-
cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
103
+
data = kzalloc(sizeof(*data), GFP_KERNEL);
97
104
clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
98
-
if (cpg == NULL || clks == NULL) {
105
+
if (data == NULL || clks == NULL) {
99
106
/* We're leaking memory on purpose, there's no point in cleaning
100
107
* up as the system won't boot anyway.
101
108
*/
102
109
return;
103
110
}
104
111
105
-
spin_lock_init(&cpg->lock);
106
-
107
-
cpg->data.clks = clks;
108
-
cpg->data.clk_num = num_clks;
109
-
110
-
cpg->reg = of_iomap(np, 0);
111
-
if (WARN_ON(cpg->reg == NULL))
112
-
return;
112
+
data->clks = clks;
113
+
data->clk_num = num_clks;
113
114
114
115
for (i = 0; i < num_clks; ++i) {
115
116
const char *name;
···
112
125
of_property_read_string_index(np, "clock-output-names", i,
113
126
&name);
114
127
115
-
clk = r8a7778_cpg_register_clock(np, cpg, name);
128
+
clk = r8a7778_cpg_register_clock(np, name);
116
129
if (IS_ERR(clk))
117
130
pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
118
131
__func__, np, name, PTR_ERR(clk));
119
132
else
120
-
cpg->data.clks[i] = clk;
133
+
data->clks[i] = clk;
121
134
}
122
135
123
-
of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
136
+
of_clk_add_provider(np, of_clk_src_onecell_get, data);
124
137
125
138
cpg_mstp_add_clk_domain(np);
126
139
}
+9
-18
drivers/clk/renesas/clk-r8a7779.c
+9
-18
drivers/clk/renesas/clk-r8a7779.c
···
21
21
22
22
#define CPG_NUM_CLOCKS (R8A7779_CLK_OUT + 1)
23
23
24
-
struct r8a7779_cpg {
25
-
struct clk_onecell_data data;
26
-
spinlock_t lock;
27
-
void __iomem *reg;
28
-
};
29
-
30
24
/* -----------------------------------------------------------------------------
31
25
* CPG Clock Data
32
26
*/
···
81
87
*/
82
88
83
89
static struct clk * __init
84
-
r8a7779_cpg_register_clock(struct device_node *np, struct r8a7779_cpg *cpg,
90
+
r8a7779_cpg_register_clock(struct device_node *np,
85
91
const struct cpg_clk_config *config,
86
92
unsigned int plla_mult, const char *name)
87
93
{
···
113
119
static void __init r8a7779_cpg_clocks_init(struct device_node *np)
114
120
{
115
121
const struct cpg_clk_config *config;
116
-
struct r8a7779_cpg *cpg;
122
+
struct clk_onecell_data *data;
117
123
struct clk **clks;
118
124
unsigned int i, plla_mult;
119
125
int num_clks;
···
128
134
return;
129
135
}
130
136
131
-
cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
137
+
data = kzalloc(sizeof(*data), GFP_KERNEL);
132
138
clks = kcalloc(CPG_NUM_CLOCKS, sizeof(*clks), GFP_KERNEL);
133
-
if (cpg == NULL || clks == NULL) {
139
+
if (data == NULL || clks == NULL) {
134
140
/* We're leaking memory on purpose, there's no point in cleaning
135
141
* up as the system won't boot anyway.
136
142
*/
137
143
return;
138
144
}
139
145
140
-
spin_lock_init(&cpg->lock);
141
-
142
-
cpg->data.clks = clks;
143
-
cpg->data.clk_num = num_clks;
146
+
data->clks = clks;
147
+
data->clk_num = num_clks;
144
148
145
149
config = &cpg_clk_configs[CPG_CLK_CONFIG_INDEX(mode)];
146
150
plla_mult = cpg_plla_mult[CPG_PLLA_MULT_INDEX(mode)];
···
150
158
of_property_read_string_index(np, "clock-output-names", i,
151
159
&name);
152
160
153
-
clk = r8a7779_cpg_register_clock(np, cpg, config,
154
-
plla_mult, name);
161
+
clk = r8a7779_cpg_register_clock(np, config, plla_mult, name);
155
162
if (IS_ERR(clk))
156
163
pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
157
164
__func__, np, name, PTR_ERR(clk));
158
165
else
159
-
cpg->data.clks[i] = clk;
166
+
data->clks[i] = clk;
160
167
}
161
168
162
-
of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
169
+
of_clk_add_provider(np, of_clk_src_onecell_get, data);
163
170
164
171
cpg_mstp_add_clk_domain(np);
165
172
}
+15
-18
drivers/clk/renesas/clk-rz.c
+15
-18
drivers/clk/renesas/clk-rz.c
···
15
15
#include <linux/of_address.h>
16
16
#include <linux/slab.h>
17
17
18
-
struct rz_cpg {
19
-
struct clk_onecell_data data;
20
-
void __iomem *reg;
21
-
};
22
-
23
18
#define CPG_FRQCR 0x10
24
19
#define CPG_FRQCR2 0x14
25
20
···
44
49
}
45
50
46
51
static struct clk * __init
47
-
rz_cpg_register_clock(struct device_node *np, struct rz_cpg *cpg, const char *name)
52
+
rz_cpg_register_clock(struct device_node *np, void __iomem *base,
53
+
const char *name)
48
54
{
49
55
u32 val;
50
56
unsigned mult;
···
61
65
}
62
66
63
67
/* If mapping regs failed, skip non-pll clocks. System will boot anyhow */
64
-
if (!cpg->reg)
68
+
if (!base)
65
69
return ERR_PTR(-ENXIO);
66
70
67
71
/* FIXME:"i" and "g" are variable clocks with non-integer dividers (e.g. 2/3)
···
69
73
* let them run at fixed current speed and implement the details later.
70
74
*/
71
75
if (strcmp(name, "i") == 0)
72
-
val = (readl(cpg->reg + CPG_FRQCR) >> 8) & 3;
76
+
val = (readl(base + CPG_FRQCR) >> 8) & 3;
73
77
else if (strcmp(name, "g") == 0)
74
-
val = readl(cpg->reg + CPG_FRQCR2) & 3;
78
+
val = readl(base + CPG_FRQCR2) & 3;
75
79
else
76
80
return ERR_PTR(-EINVAL);
77
81
···
81
85
82
86
static void __init rz_cpg_clocks_init(struct device_node *np)
83
87
{
84
-
struct rz_cpg *cpg;
88
+
struct clk_onecell_data *data;
85
89
struct clk **clks;
90
+
void __iomem *base;
86
91
unsigned i;
87
92
int num_clks;
88
93
···
91
94
if (WARN(num_clks <= 0, "can't count CPG clocks\n"))
92
95
return;
93
96
94
-
cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
97
+
data = kzalloc(sizeof(*data), GFP_KERNEL);
95
98
clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
96
-
BUG_ON(!cpg || !clks);
99
+
BUG_ON(!data || !clks);
97
100
98
-
cpg->data.clks = clks;
99
-
cpg->data.clk_num = num_clks;
101
+
data->clks = clks;
102
+
data->clk_num = num_clks;
100
103
101
-
cpg->reg = of_iomap(np, 0);
104
+
base = of_iomap(np, 0);
102
105
103
106
for (i = 0; i < num_clks; ++i) {
104
107
const char *name;
···
106
109
107
110
of_property_read_string_index(np, "clock-output-names", i, &name);
108
111
109
-
clk = rz_cpg_register_clock(np, cpg, name);
112
+
clk = rz_cpg_register_clock(np, base, name);
110
113
if (IS_ERR(clk))
111
114
pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
112
115
__func__, np, name, PTR_ERR(clk));
113
116
else
114
-
cpg->data.clks[i] = clk;
117
+
data->clks[i] = clk;
115
118
}
116
119
117
-
of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
120
+
of_clk_add_provider(np, of_clk_src_onecell_get, data);
118
121
119
122
cpg_mstp_add_clk_domain(np);
120
123
}
+13
-13
drivers/clk/renesas/clk-sh73a0.c
+13
-13
drivers/clk/renesas/clk-sh73a0.c
···
18
18
struct sh73a0_cpg {
19
19
struct clk_onecell_data data;
20
20
spinlock_t lock;
21
-
void __iomem *reg;
22
21
};
23
22
24
23
#define CPG_FRQCRA 0x00
···
72
73
73
74
static struct clk * __init
74
75
sh73a0_cpg_register_clock(struct device_node *np, struct sh73a0_cpg *cpg,
75
-
const char *name)
76
+
void __iomem *base, const char *name)
76
77
{
77
78
const struct clk_div_table *table = NULL;
78
79
unsigned int shift, reg, width;
···
82
83
83
84
if (!strcmp(name, "main")) {
84
85
/* extal1, extal1_div2, extal2, extal2_div2 */
85
-
u32 parent_idx = (readl(cpg->reg + CPG_CKSCR) >> 28) & 3;
86
+
u32 parent_idx = (readl(base + CPG_CKSCR) >> 28) & 3;
86
87
87
88
parent_name = of_clk_get_parent_name(np, parent_idx >> 1);
88
89
div = (parent_idx & 1) + 1;
89
90
} else if (!strncmp(name, "pll", 3)) {
90
-
void __iomem *enable_reg = cpg->reg;
91
+
void __iomem *enable_reg = base;
91
92
u32 enable_bit = name[3] - '0';
92
93
93
94
parent_name = "main";
···
107
108
default:
108
109
return ERR_PTR(-EINVAL);
109
110
}
110
-
if (readl(cpg->reg + CPG_PLLECR) & BIT(enable_bit)) {
111
+
if (readl(base + CPG_PLLECR) & BIT(enable_bit)) {
111
112
mult = ((readl(enable_reg) >> 24) & 0x3f) + 1;
112
113
/* handle CFG bit for PLL1 and PLL2 */
113
114
if (enable_bit == 1 || enable_bit == 2)
···
116
117
}
117
118
} else if (!strcmp(name, "dsi0phy") || !strcmp(name, "dsi1phy")) {
118
119
u32 phy_no = name[3] - '0';
119
-
void __iomem *dsi_reg = cpg->reg +
120
+
void __iomem *dsi_reg = base +
120
121
(phy_no ? CPG_DSI1PHYCR : CPG_DSI0PHYCR);
121
122
122
123
parent_name = phy_no ? "dsi1pck" : "dsi0pck";
···
153
154
mult, div);
154
155
} else {
155
156
return clk_register_divider_table(NULL, name, parent_name, 0,
156
-
cpg->reg + reg, shift, width, 0,
157
+
base + reg, shift, width, 0,
157
158
table, &cpg->lock);
158
159
}
159
160
}
···
161
162
static void __init sh73a0_cpg_clocks_init(struct device_node *np)
162
163
{
163
164
struct sh73a0_cpg *cpg;
165
+
void __iomem *base;
164
166
struct clk **clks;
165
167
unsigned int i;
166
168
int num_clks;
···
186
186
cpg->data.clks = clks;
187
187
cpg->data.clk_num = num_clks;
188
188
189
-
cpg->reg = of_iomap(np, 0);
190
-
if (WARN_ON(cpg->reg == NULL))
189
+
base = of_iomap(np, 0);
190
+
if (WARN_ON(base == NULL))
191
191
return;
192
192
193
193
/* Set SDHI clocks to a known state */
194
-
writel(0x108, cpg->reg + CPG_SD0CKCR);
195
-
writel(0x108, cpg->reg + CPG_SD1CKCR);
196
-
writel(0x108, cpg->reg + CPG_SD2CKCR);
194
+
writel(0x108, base + CPG_SD0CKCR);
195
+
writel(0x108, base + CPG_SD1CKCR);
196
+
writel(0x108, base + CPG_SD2CKCR);
197
197
198
198
for (i = 0; i < num_clks; ++i) {
199
199
const char *name;
···
202
202
of_property_read_string_index(np, "clock-output-names", i,
203
203
&name);
204
204
205
-
clk = sh73a0_cpg_register_clock(np, cpg, name);
205
+
clk = sh73a0_cpg_register_clock(np, cpg, base, name);
206
206
if (IS_ERR(clk))
207
207
pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
208
208
__func__, np, name, PTR_ERR(clk));
+10
drivers/clk/renesas/r8a779f0-cpg-mssr.c
+10
drivers/clk/renesas/r8a779f0-cpg-mssr.c
···
77
77
DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN4_RPCSRC, CLK_PLL5),
78
78
79
79
/* Core Clock Outputs */
80
+
DEF_GEN4_Z("z0", R8A779F0_CLK_Z0, CLK_TYPE_GEN4_Z, CLK_PLL2, 2, 0),
81
+
DEF_GEN4_Z("z1", R8A779F0_CLK_Z1, CLK_TYPE_GEN4_Z, CLK_PLL2, 2, 8),
80
82
DEF_FIXED("s0d2", R8A779F0_CLK_S0D2, CLK_S0, 2, 1),
81
83
DEF_FIXED("s0d3", R8A779F0_CLK_S0D3, CLK_S0, 3, 1),
82
84
DEF_FIXED("s0d4", R8A779F0_CLK_S0D4, CLK_S0, 4, 1),
···
120
118
};
121
119
122
120
static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = {
121
+
DEF_MOD("hscif0", 514, R8A779F0_CLK_S0D3),
122
+
DEF_MOD("hscif1", 515, R8A779F0_CLK_S0D3),
123
+
DEF_MOD("hscif2", 516, R8A779F0_CLK_S0D3),
124
+
DEF_MOD("hscif3", 517, R8A779F0_CLK_S0D3),
123
125
DEF_MOD("i2c0", 518, R8A779F0_CLK_S0D6_PER),
124
126
DEF_MOD("i2c1", 519, R8A779F0_CLK_S0D6_PER),
125
127
DEF_MOD("i2c2", 520, R8A779F0_CLK_S0D6_PER),
126
128
DEF_MOD("i2c3", 521, R8A779F0_CLK_S0D6_PER),
127
129
DEF_MOD("i2c4", 522, R8A779F0_CLK_S0D6_PER),
128
130
DEF_MOD("i2c5", 523, R8A779F0_CLK_S0D6_PER),
131
+
DEF_MOD("pcie0", 624, R8A779F0_CLK_S0D2),
132
+
DEF_MOD("pcie1", 625, R8A779F0_CLK_S0D2),
129
133
DEF_MOD("scif0", 702, R8A779F0_CLK_S0D12_PER),
130
134
DEF_MOD("scif1", 703, R8A779F0_CLK_S0D12_PER),
131
135
DEF_MOD("scif3", 704, R8A779F0_CLK_S0D12_PER),
132
136
DEF_MOD("scif4", 705, R8A779F0_CLK_S0D12_PER),
137
+
DEF_MOD("sdhi0", 706, R8A779F0_CLK_SD0),
133
138
DEF_MOD("sys-dmac0", 709, R8A779F0_CLK_S0D3_PER),
134
139
DEF_MOD("sys-dmac1", 710, R8A779F0_CLK_S0D3_PER),
135
140
DEF_MOD("wdt", 907, R8A779F0_CLK_R),
136
141
DEF_MOD("pfc0", 915, R8A779F0_CLK_CL16M),
142
+
DEF_MOD("tsc", 919, R8A779F0_CLK_CL16M),
137
143
DEF_MOD("ufs", 1514, R8A779F0_CLK_S0D4_HSC),
138
144
};
139
145
+15
-17
drivers/clk/renesas/r9a06g032-clocks.c
+15
-17
drivers/clk/renesas/r9a06g032-clocks.c
···
51
51
struct {
52
52
u16 div, mul;
53
53
};
54
-
unsigned int factor;
55
-
unsigned int frequency;
56
54
/* for dual gate */
57
55
struct {
58
-
uint16_t group : 1, index: 3;
56
+
uint16_t group : 1;
59
57
u16 sel, g1, r1, g2, r2;
60
58
} dual;
61
59
};
···
83
85
.source = 1 + R9A06G032_##_src, .name = _n, \
84
86
.reg = _reg, .div_min = _min, .div_max = _max, \
85
87
.div_table = { __VA_ARGS__ } }
86
-
#define D_UGATE(_idx, _n, _src, _g, _gi, _g1, _r1, _g2, _r2) \
88
+
#define D_UGATE(_idx, _n, _src, _g, _g1, _r1, _g2, _r2) \
87
89
{ .type = K_DUALGATE, .index = R9A06G032_##_idx, \
88
90
.source = 1 + R9A06G032_##_src, .name = _n, \
89
-
.dual = { .group = _g, .index = _gi, \
91
+
.dual = { .group = _g, \
90
92
.g1 = _g1, .r1 = _r1, .g2 = _g2, .r2 = _r2 }, }
91
93
92
94
enum { K_GATE = 0, K_FFC, K_DIV, K_BITSEL, K_DUALGATE };
···
288
290
.name = "uart_group_012",
289
291
.type = K_BITSEL,
290
292
.source = 1 + R9A06G032_DIV_UART,
291
-
/* R9A06G032_SYSCTRL_REG_PWRCTRL_PG1_PR2 */
292
-
.dual.sel = ((0xec / 4) << 5) | 24,
293
+
/* R9A06G032_SYSCTRL_REG_PWRCTRL_PG0_0 */
294
+
.dual.sel = ((0x34 / 4) << 5) | 30,
293
295
.dual.group = 0,
294
296
},
295
297
{
···
297
299
.name = "uart_group_34567",
298
300
.type = K_BITSEL,
299
301
.source = 1 + R9A06G032_DIV_P2_PG,
300
-
/* R9A06G032_SYSCTRL_REG_PWRCTRL_PG0_0 */
301
-
.dual.sel = ((0x34 / 4) << 5) | 30,
302
+
/* R9A06G032_SYSCTRL_REG_PWRCTRL_PG1_PR2 */
303
+
.dual.sel = ((0xec / 4) << 5) | 24,
302
304
.dual.group = 1,
303
305
},
304
-
D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0, 0, 0x1b2, 0x1b3, 0x1b4, 0x1b5),
305
-
D_UGATE(CLK_UART1, "clk_uart1", UART_GROUP_012, 0, 1, 0x1b6, 0x1b7, 0x1b8, 0x1b9),
306
-
D_UGATE(CLK_UART2, "clk_uart2", UART_GROUP_012, 0, 2, 0x1ba, 0x1bb, 0x1bc, 0x1bd),
307
-
D_UGATE(CLK_UART3, "clk_uart3", UART_GROUP_34567, 1, 0, 0x760, 0x761, 0x762, 0x763),
308
-
D_UGATE(CLK_UART4, "clk_uart4", UART_GROUP_34567, 1, 1, 0x764, 0x765, 0x766, 0x767),
309
-
D_UGATE(CLK_UART5, "clk_uart5", UART_GROUP_34567, 1, 2, 0x768, 0x769, 0x76a, 0x76b),
310
-
D_UGATE(CLK_UART6, "clk_uart6", UART_GROUP_34567, 1, 3, 0x76c, 0x76d, 0x76e, 0x76f),
311
-
D_UGATE(CLK_UART7, "clk_uart7", UART_GROUP_34567, 1, 4, 0x770, 0x771, 0x772, 0x773),
306
+
D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0, 0x1b2, 0x1b3, 0x1b4, 0x1b5),
307
+
D_UGATE(CLK_UART1, "clk_uart1", UART_GROUP_012, 0, 0x1b6, 0x1b7, 0x1b8, 0x1b9),
308
+
D_UGATE(CLK_UART2, "clk_uart2", UART_GROUP_012, 0, 0x1ba, 0x1bb, 0x1bc, 0x1bd),
309
+
D_UGATE(CLK_UART3, "clk_uart3", UART_GROUP_34567, 1, 0x760, 0x761, 0x762, 0x763),
310
+
D_UGATE(CLK_UART4, "clk_uart4", UART_GROUP_34567, 1, 0x764, 0x765, 0x766, 0x767),
311
+
D_UGATE(CLK_UART5, "clk_uart5", UART_GROUP_34567, 1, 0x768, 0x769, 0x76a, 0x76b),
312
+
D_UGATE(CLK_UART6, "clk_uart6", UART_GROUP_34567, 1, 0x76c, 0x76d, 0x76e, 0x76f),
313
+
D_UGATE(CLK_UART7, "clk_uart7", UART_GROUP_34567, 1, 0x770, 0x771, 0x772, 0x773),
312
314
};
313
315
314
316
struct r9a06g032_priv {
+32
drivers/clk/renesas/r9a07g043-cpg.c
+32
drivers/clk/renesas/r9a07g043-cpg.c
···
36
36
CLK_PLL3_DIV2_4_2,
37
37
CLK_SEL_PLL3_3,
38
38
CLK_DIV_PLL3_C,
39
+
#ifdef CONFIG_ARM64
39
40
CLK_PLL5,
40
41
CLK_PLL5_500,
41
42
CLK_PLL5_250,
43
+
#endif
42
44
CLK_PLL6,
43
45
CLK_PLL6_250,
44
46
CLK_P1_DIV2,
···
102
100
DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3),
103
101
DEF_MUX_RO(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3, sel_pll3_3),
104
102
DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3, DIVPL3C, dtable_1_32),
103
+
#ifdef CONFIG_ARM64
105
104
DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1),
106
105
DEF_FIXED(".pll5_500", CLK_PLL5_500, CLK_PLL5, 1, 6),
107
106
DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_500, 1, 2),
107
+
#endif
108
108
DEF_FIXED(".pll6", CLK_PLL6, CLK_EXTAL, 125, 6),
109
109
DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2),
110
110
···
130
126
};
131
127
132
128
static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
129
+
#ifdef CONFIG_ARM64
133
130
DEF_MOD("gic", R9A07G043_GIC600_GICCLK, R9A07G043_CLK_P1,
134
131
0x514, 0),
135
132
DEF_MOD("ia55_pclk", R9A07G043_IA55_PCLK, R9A07G043_CLK_P2,
136
133
0x518, 0),
137
134
DEF_MOD("ia55_clk", R9A07G043_IA55_CLK, R9A07G043_CLK_P1,
138
135
0x518, 1),
136
+
#endif
137
+
#ifdef CONFIG_RISCV
138
+
DEF_MOD("iax45_pclk", R9A07G043_IAX45_PCLK, R9A07G043_CLK_P2,
139
+
0x518, 0),
140
+
DEF_MOD("iax45_clk", R9A07G043_IAX45_CLK, R9A07G043_CLK_P1,
141
+
0x518, 1),
142
+
#endif
139
143
DEF_MOD("dmac_aclk", R9A07G043_DMAC_ACLK, R9A07G043_CLK_P1,
140
144
0x52c, 0),
141
145
DEF_MOD("dmac_pclk", R9A07G043_DMAC_PCLK, CLK_P1_DIV2,
···
255
243
};
256
244
257
245
static struct rzg2l_reset r9a07g043_resets[] = {
246
+
#ifdef CONFIG_ARM64
258
247
DEF_RST(R9A07G043_GIC600_GICRESET_N, 0x814, 0),
259
248
DEF_RST(R9A07G043_GIC600_DBG_GICRESET_N, 0x814, 1),
260
249
DEF_RST(R9A07G043_IA55_RESETN, 0x818, 0),
250
+
#endif
251
+
#ifdef CONFIG_RISCV
252
+
DEF_RST(R9A07G043_IAX45_RESETN, 0x818, 0),
253
+
#endif
261
254
DEF_RST(R9A07G043_DMAC_ARESETN, 0x82c, 0),
262
255
DEF_RST(R9A07G043_DMAC_RST_ASYNC, 0x82c, 1),
263
256
DEF_RST(R9A07G043_OSTM0_PRESETZ, 0x834, 0),
···
308
291
};
309
292
310
293
static const unsigned int r9a07g043_crit_mod_clks[] __initconst = {
294
+
#ifdef CONFIG_ARM64
311
295
MOD_CLK_BASE + R9A07G043_GIC600_GICCLK,
312
296
MOD_CLK_BASE + R9A07G043_IA55_CLK,
297
+
#endif
298
+
#ifdef CONFIG_RISCV
299
+
MOD_CLK_BASE + R9A07G043_IAX45_CLK,
300
+
#endif
313
301
MOD_CLK_BASE + R9A07G043_DMAC_ACLK,
314
302
};
315
303
···
332
310
/* Module Clocks */
333
311
.mod_clks = r9a07g043_mod_clks,
334
312
.num_mod_clks = ARRAY_SIZE(r9a07g043_mod_clks),
313
+
#ifdef CONFIG_ARM64
335
314
.num_hw_mod_clks = R9A07G043_TSU_PCLK + 1,
315
+
#endif
316
+
#ifdef CONFIG_RISCV
317
+
.num_hw_mod_clks = R9A07G043_IAX45_PCLK + 1,
318
+
#endif
336
319
337
320
/* Resets */
338
321
.resets = r9a07g043_resets,
322
+
#ifdef CONFIG_ARM64
339
323
.num_resets = R9A07G043_TSU_PRESETN + 1, /* Last reset ID + 1 */
324
+
#endif
325
+
#ifdef CONFIG_RISCV
326
+
.num_resets = R9A07G043_IAX45_RESETN + 1, /* Last reset ID + 1 */
327
+
#endif
340
328
341
329
.has_clk_mon_regs = true,
342
330
};
+16
-1
drivers/clk/renesas/r9a07g044-cpg.c
+16
-1
drivers/clk/renesas/r9a07g044-cpg.c
···
182
182
};
183
183
184
184
static const struct {
185
-
struct rzg2l_mod_clk common[71];
185
+
struct rzg2l_mod_clk common[76];
186
186
#ifdef CONFIG_CLK_R9A07G054
187
187
struct rzg2l_mod_clk drp[0];
188
188
#endif
···
204
204
0x534, 1),
205
205
DEF_MOD("ostm2_pclk", R9A07G044_OSTM2_PCLK, R9A07G044_CLK_P0,
206
206
0x534, 2),
207
+
DEF_MOD("gpt_pclk", R9A07G044_GPT_PCLK, R9A07G044_CLK_P0,
208
+
0x540, 0),
209
+
DEF_MOD("poeg_a_clkp", R9A07G044_POEG_A_CLKP, R9A07G044_CLK_P0,
210
+
0x544, 0),
211
+
DEF_MOD("poeg_b_clkp", R9A07G044_POEG_B_CLKP, R9A07G044_CLK_P0,
212
+
0x544, 1),
213
+
DEF_MOD("poeg_c_clkp", R9A07G044_POEG_C_CLKP, R9A07G044_CLK_P0,
214
+
0x544, 2),
215
+
DEF_MOD("poeg_d_clkp", R9A07G044_POEG_D_CLKP, R9A07G044_CLK_P0,
216
+
0x544, 3),
207
217
DEF_MOD("wdt0_pclk", R9A07G044_WDT0_PCLK, R9A07G044_CLK_P0,
208
218
0x548, 0),
209
219
DEF_MOD("wdt0_clk", R9A07G044_WDT0_CLK, R9A07G044_OSCCLK,
···
356
346
DEF_RST(R9A07G044_OSTM0_PRESETZ, 0x834, 0),
357
347
DEF_RST(R9A07G044_OSTM1_PRESETZ, 0x834, 1),
358
348
DEF_RST(R9A07G044_OSTM2_PRESETZ, 0x834, 2),
349
+
DEF_RST(R9A07G044_GPT_RST_C, 0x840, 0),
350
+
DEF_RST(R9A07G044_POEG_A_RST, 0x844, 0),
351
+
DEF_RST(R9A07G044_POEG_B_RST, 0x844, 1),
352
+
DEF_RST(R9A07G044_POEG_C_RST, 0x844, 2),
353
+
DEF_RST(R9A07G044_POEG_D_RST, 0x844, 3),
359
354
DEF_RST(R9A07G044_WDT0_PRESETN, 0x848, 0),
360
355
DEF_RST(R9A07G044_WDT1_PRESETN, 0x848, 1),
361
356
DEF_RST(R9A07G044_WDT2_PRESETN, 0x848, 2),
+5
drivers/clk/renesas/r9a09g011-cpg.c
+5
drivers/clk/renesas/r9a09g011-cpg.c
···
126
126
};
127
127
128
128
static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = {
129
+
DEF_MOD("pfc", R9A09G011_PFC_PCLK, CLK_MAIN, 0x400, 2),
129
130
DEF_MOD("gic", R9A09G011_GIC_CLK, CLK_SEL_B_D2, 0x400, 5),
130
131
DEF_COUPLED("eth_axi", R9A09G011_ETH0_CLK_AXI, CLK_PLL2_200, 0x40c, 8),
131
132
DEF_COUPLED("eth_chi", R9A09G011_ETH0_CLK_CHI, CLK_PLL2_100, 0x40c, 8),
132
133
DEF_MOD("eth_clk_gptp", R9A09G011_ETH0_GPTP_EXT, CLK_PLL2_100, 0x40c, 9),
133
134
DEF_MOD("syc_cnt_clk", R9A09G011_SYC_CNT_CLK, CLK_MAIN_24, 0x41c, 12),
135
+
DEF_MOD("wdt0_pclk", R9A09G011_WDT0_PCLK, CLK_SEL_E, 0x428, 12),
136
+
DEF_MOD("wdt0_clk", R9A09G011_WDT0_CLK, CLK_MAIN, 0x428, 13),
134
137
DEF_MOD("urt_pclk", R9A09G011_URT_PCLK, CLK_SEL_E, 0x438, 4),
135
138
DEF_MOD("urt0_clk", R9A09G011_URT0_CLK, CLK_SEL_W0, 0x438, 5),
136
139
DEF_MOD("ca53", R9A09G011_CA53_CLK, CLK_DIV_A, 0x448, 0),
137
140
};
138
141
139
142
static const struct rzg2l_reset r9a09g011_resets[] = {
143
+
DEF_RST(R9A09G011_PFC_PRESETN, 0x600, 2),
140
144
DEF_RST_MON(R9A09G011_ETH0_RST_HW_N, 0x608, 11, 11),
141
145
DEF_RST_MON(R9A09G011_SYC_RST_N, 0x610, 9, 13),
146
+
DEF_RST_MON(R9A09G011_WDT0_PRESETN, 0x614, 12, 19),
142
147
};
143
148
144
149
static const unsigned int r9a09g011_crit_mod_clks[] __initconst = {
+1
-1
drivers/clk/renesas/rcar-gen4-cpg.c
+1
-1
drivers/clk/renesas/rcar-gen4-cpg.c
···
23
23
#include "rcar-gen4-cpg.h"
24
24
#include "rcar-cpg-lib.h"
25
25
26
-
static const struct rcar_gen4_cpg_pll_config *cpg_pll_config __initconst;
26
+
static const struct rcar_gen4_cpg_pll_config *cpg_pll_config __initdata;
27
27
static unsigned int cpg_clk_extalr __initdata;
28
28
static u32 cpg_mode __initdata;
29
29
+1
-1
drivers/clk/renesas/rzg2l-cpg.c
+1
-1
drivers/clk/renesas/rzg2l-cpg.c
···
1180
1180
s8 monbit = info->resets[id].monbit;
1181
1181
1182
1182
if (info->has_clk_mon_regs) {
1183
-
return !(readl(priv->base + CLK_MRST_R(reg)) & bitmask);
1183
+
return !!(readl(priv->base + CLK_MRST_R(reg)) & bitmask);
1184
1184
} else if (monbit >= 0) {
1185
1185
u32 monbitmask = BIT(monbit);
1186
1186
+2
-13
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
+2
-13
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
···
143
143
&w1_clk.common,
144
144
};
145
145
146
-
static struct ccu_common *sun50i_h616_r_ccu_clks[] = {
147
-
&r_apb1_clk.common,
148
-
&r_apb2_clk.common,
149
-
&r_apb1_twd_clk.common,
150
-
&r_apb2_i2c_clk.common,
151
-
&r_apb2_rsb_clk.common,
152
-
&r_apb1_ir_clk.common,
153
-
&r_apb1_rtc_clk.common,
154
-
&ir_clk.common,
155
-
};
156
-
157
146
static struct clk_hw_onecell_data sun50i_h6_r_hw_clks = {
158
147
.hws = {
159
148
[CLK_AR100] = &ar100_clk.common.hw,
···
208
219
};
209
220
210
221
static const struct sunxi_ccu_desc sun50i_h616_r_ccu_desc = {
211
-
.ccu_clks = sun50i_h616_r_ccu_clks,
212
-
.num_ccu_clks = ARRAY_SIZE(sun50i_h616_r_ccu_clks),
222
+
.ccu_clks = sun50i_h6_r_ccu_clks,
223
+
.num_ccu_clks = ARRAY_SIZE(sun50i_h6_r_ccu_clks),
213
224
214
225
.hw_clks = &sun50i_h616_r_hw_clks,
215
226
+13
-3
drivers/clk/sunxi-ng/ccu-sun50i-h6.c
+13
-3
drivers/clk/sunxi-ng/ccu-sun50i-h6.c
···
95
95
},
96
96
};
97
97
98
+
/* For GPU PLL, using an output divider for DFS causes system to fail */
98
99
#define SUN50I_H6_PLL_GPU_REG 0x030
99
100
static struct ccu_nkmp pll_gpu_clk = {
100
101
.enable = BIT(31),
101
102
.lock = BIT(28),
102
103
.n = _SUNXI_CCU_MULT_MIN(8, 8, 12),
103
104
.m = _SUNXI_CCU_DIV(1, 1), /* input divider */
104
-
.p = _SUNXI_CCU_DIV(0, 1), /* output divider */
105
105
.common = {
106
106
.reg = 0x030,
107
107
.hw.init = CLK_HW_INIT("pll-gpu", "osc24M",
···
294
294
static SUNXI_CCU_GATE(bus_deinterlace_clk, "bus-deinterlace", "psi-ahb1-ahb2",
295
295
0x62c, BIT(0), 0);
296
296
297
+
/* Keep GPU_CLK divider const to avoid DFS instability. */
297
298
static const char * const gpu_parents[] = { "pll-gpu" };
298
-
static SUNXI_CCU_M_WITH_MUX_GATE(gpu_clk, "gpu", gpu_parents, 0x670,
299
-
0, 3, /* M */
299
+
static SUNXI_CCU_MUX_WITH_GATE(gpu_clk, "gpu", gpu_parents, 0x670,
300
300
24, 1, /* mux */
301
301
BIT(31), /* gate */
302
302
CLK_SET_RATE_PARENT);
···
1190
1190
reg = devm_platform_ioremap_resource(pdev, 0);
1191
1191
if (IS_ERR(reg))
1192
1192
return PTR_ERR(reg);
1193
+
1194
+
/* Force PLL_GPU output divider bits to 0 */
1195
+
val = readl(reg + SUN50I_H6_PLL_GPU_REG);
1196
+
val &= ~BIT(0);
1197
+
writel(val, reg + SUN50I_H6_PLL_GPU_REG);
1198
+
1199
+
/* Force GPU_CLK divider bits to 0 */
1200
+
val = readl(reg + gpu_clk.common.reg);
1201
+
val &= ~GENMASK(3, 0);
1202
+
writel(val, reg + gpu_clk.common.reg);
1193
1203
1194
1204
/* Enable the lock bits on all PLLs */
1195
1205
for (i = 0; i < ARRAY_SIZE(pll_regs); i++) {
+20
-59
drivers/clk/sunxi-ng/ccu-sun8i-de2.c
+20
-59
drivers/clk/sunxi-ng/ccu-sun8i-de2.c
···
53
53
static SUNXI_CCU_M(rot_div_a83_clk, "rot-div", "pll-de", 0x0c, 0x0c, 4,
54
54
CLK_SET_RATE_PARENT);
55
55
56
-
static struct ccu_common *sun8i_a83t_de2_clks[] = {
56
+
static struct ccu_common *sun8i_de2_ccu_clks[] = {
57
57
&mixer0_clk.common,
58
58
&mixer1_clk.common,
59
59
&wb_clk.common,
60
+
&rot_clk.common,
60
61
61
62
&bus_mixer0_clk.common,
62
63
&bus_mixer1_clk.common,
63
64
&bus_wb_clk.common,
65
+
&bus_rot_clk.common,
66
+
67
+
&mixer0_div_clk.common,
68
+
&mixer1_div_clk.common,
69
+
&wb_div_clk.common,
70
+
&rot_div_clk.common,
64
71
65
72
&mixer0_div_a83_clk.common,
66
73
&mixer1_div_a83_clk.common,
67
74
&wb_div_a83_clk.common,
68
-
69
-
&bus_rot_clk.common,
70
-
&rot_clk.common,
71
75
&rot_div_a83_clk.common,
72
-
};
73
-
74
-
static struct ccu_common *sun8i_h3_de2_clks[] = {
75
-
&mixer0_clk.common,
76
-
&mixer1_clk.common,
77
-
&wb_clk.common,
78
-
79
-
&bus_mixer0_clk.common,
80
-
&bus_mixer1_clk.common,
81
-
&bus_wb_clk.common,
82
-
83
-
&mixer0_div_clk.common,
84
-
&mixer1_div_clk.common,
85
-
&wb_div_clk.common,
86
-
};
87
-
88
-
static struct ccu_common *sun8i_v3s_de2_clks[] = {
89
-
&mixer0_clk.common,
90
-
&wb_clk.common,
91
-
92
-
&bus_mixer0_clk.common,
93
-
&bus_wb_clk.common,
94
-
95
-
&mixer0_div_clk.common,
96
-
&wb_div_clk.common,
97
-
};
98
-
99
-
static struct ccu_common *sun50i_a64_de2_clks[] = {
100
-
&mixer0_clk.common,
101
-
&mixer1_clk.common,
102
-
&wb_clk.common,
103
-
104
-
&bus_mixer0_clk.common,
105
-
&bus_mixer1_clk.common,
106
-
&bus_wb_clk.common,
107
-
108
-
&mixer0_div_clk.common,
109
-
&mixer1_div_clk.common,
110
-
&wb_div_clk.common,
111
-
112
-
&bus_rot_clk.common,
113
-
&rot_clk.common,
114
-
&rot_div_clk.common,
115
76
};
116
77
117
78
static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks = {
···
180
219
};
181
220
182
221
static const struct sunxi_ccu_desc sun8i_a83t_de2_clk_desc = {
183
-
.ccu_clks = sun8i_a83t_de2_clks,
184
-
.num_ccu_clks = ARRAY_SIZE(sun8i_a83t_de2_clks),
222
+
.ccu_clks = sun8i_de2_ccu_clks,
223
+
.num_ccu_clks = ARRAY_SIZE(sun8i_de2_ccu_clks),
185
224
186
225
.hw_clks = &sun8i_a83t_de2_hw_clks,
187
226
···
190
229
};
191
230
192
231
static const struct sunxi_ccu_desc sun8i_h3_de2_clk_desc = {
193
-
.ccu_clks = sun8i_h3_de2_clks,
194
-
.num_ccu_clks = ARRAY_SIZE(sun8i_h3_de2_clks),
232
+
.ccu_clks = sun8i_de2_ccu_clks,
233
+
.num_ccu_clks = ARRAY_SIZE(sun8i_de2_ccu_clks),
195
234
196
235
.hw_clks = &sun8i_h3_de2_hw_clks,
197
236
···
200
239
};
201
240
202
241
static const struct sunxi_ccu_desc sun8i_r40_de2_clk_desc = {
203
-
.ccu_clks = sun50i_a64_de2_clks,
204
-
.num_ccu_clks = ARRAY_SIZE(sun50i_a64_de2_clks),
242
+
.ccu_clks = sun8i_de2_ccu_clks,
243
+
.num_ccu_clks = ARRAY_SIZE(sun8i_de2_ccu_clks),
205
244
206
245
.hw_clks = &sun50i_a64_de2_hw_clks,
207
246
···
210
249
};
211
250
212
251
static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = {
213
-
.ccu_clks = sun8i_v3s_de2_clks,
214
-
.num_ccu_clks = ARRAY_SIZE(sun8i_v3s_de2_clks),
252
+
.ccu_clks = sun8i_de2_ccu_clks,
253
+
.num_ccu_clks = ARRAY_SIZE(sun8i_de2_ccu_clks),
215
254
216
255
.hw_clks = &sun8i_v3s_de2_hw_clks,
217
256
···
220
259
};
221
260
222
261
static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = {
223
-
.ccu_clks = sun50i_a64_de2_clks,
224
-
.num_ccu_clks = ARRAY_SIZE(sun50i_a64_de2_clks),
262
+
.ccu_clks = sun8i_de2_ccu_clks,
263
+
.num_ccu_clks = ARRAY_SIZE(sun8i_de2_ccu_clks),
225
264
226
265
.hw_clks = &sun50i_a64_de2_hw_clks,
227
266
···
230
269
};
231
270
232
271
static const struct sunxi_ccu_desc sun50i_h5_de2_clk_desc = {
233
-
.ccu_clks = sun8i_h3_de2_clks,
234
-
.num_ccu_clks = ARRAY_SIZE(sun8i_h3_de2_clks),
272
+
.ccu_clks = sun8i_de2_ccu_clks,
273
+
.num_ccu_clks = ARRAY_SIZE(sun8i_de2_ccu_clks),
235
274
236
275
.hw_clks = &sun8i_h3_de2_hw_clks,
237
276
+3
-110
drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+3
-110
drivers/clk/sunxi-ng/ccu-sun8i-h3.c
···
562
562
&bus_uart2_clk.common,
563
563
&bus_uart3_clk.common,
564
564
&bus_scr0_clk.common,
565
+
&bus_scr1_clk.common,
565
566
&bus_ephy_clk.common,
566
567
&bus_dbg_clk.common,
567
568
&ths_clk.common,
···
576
575
&mmc2_clk.common,
577
576
&mmc2_sample_clk.common,
578
577
&mmc2_output_clk.common,
579
-
&ts_clk.common,
580
-
&ce_clk.common,
581
-
&spi0_clk.common,
582
-
&spi1_clk.common,
583
-
&i2s0_clk.common,
584
-
&i2s1_clk.common,
585
-
&i2s2_clk.common,
586
-
&spdif_clk.common,
587
-
&usb_phy0_clk.common,
588
-
&usb_phy1_clk.common,
589
-
&usb_phy2_clk.common,
590
-
&usb_phy3_clk.common,
591
-
&usb_ohci0_clk.common,
592
-
&usb_ohci1_clk.common,
593
-
&usb_ohci2_clk.common,
594
-
&usb_ohci3_clk.common,
595
-
&dram_clk.common,
596
-
&dram_ve_clk.common,
597
-
&dram_csi_clk.common,
598
-
&dram_deinterlace_clk.common,
599
-
&dram_ts_clk.common,
600
-
&de_clk.common,
601
-
&tcon_clk.common,
602
-
&tve_clk.common,
603
-
&deinterlace_clk.common,
604
-
&csi_misc_clk.common,
605
-
&csi_sclk_clk.common,
606
-
&csi_mclk_clk.common,
607
-
&ve_clk.common,
608
-
&ac_dig_clk.common,
609
-
&avs_clk.common,
610
-
&hdmi_clk.common,
611
-
&hdmi_ddc_clk.common,
612
-
&mbus_clk.common,
613
-
&gpu_clk.common,
614
-
};
615
-
616
-
static struct ccu_common *sun50i_h5_ccu_clks[] = {
617
-
&pll_cpux_clk.common,
618
-
&pll_audio_base_clk.common,
619
-
&pll_video_clk.common,
620
-
&pll_ve_clk.common,
621
-
&pll_ddr_clk.common,
622
-
&pll_periph0_clk.common,
623
-
&pll_gpu_clk.common,
624
-
&pll_periph1_clk.common,
625
-
&pll_de_clk.common,
626
-
&cpux_clk.common,
627
-
&axi_clk.common,
628
-
&ahb1_clk.common,
629
-
&apb1_clk.common,
630
-
&apb2_clk.common,
631
-
&ahb2_clk.common,
632
-
&bus_ce_clk.common,
633
-
&bus_dma_clk.common,
634
-
&bus_mmc0_clk.common,
635
-
&bus_mmc1_clk.common,
636
-
&bus_mmc2_clk.common,
637
-
&bus_nand_clk.common,
638
-
&bus_dram_clk.common,
639
-
&bus_emac_clk.common,
640
-
&bus_ts_clk.common,
641
-
&bus_hstimer_clk.common,
642
-
&bus_spi0_clk.common,
643
-
&bus_spi1_clk.common,
644
-
&bus_otg_clk.common,
645
-
&bus_ehci0_clk.common,
646
-
&bus_ehci1_clk.common,
647
-
&bus_ehci2_clk.common,
648
-
&bus_ehci3_clk.common,
649
-
&bus_ohci0_clk.common,
650
-
&bus_ohci1_clk.common,
651
-
&bus_ohci2_clk.common,
652
-
&bus_ohci3_clk.common,
653
-
&bus_ve_clk.common,
654
-
&bus_tcon0_clk.common,
655
-
&bus_tcon1_clk.common,
656
-
&bus_deinterlace_clk.common,
657
-
&bus_csi_clk.common,
658
-
&bus_tve_clk.common,
659
-
&bus_hdmi_clk.common,
660
-
&bus_de_clk.common,
661
-
&bus_gpu_clk.common,
662
-
&bus_msgbox_clk.common,
663
-
&bus_spinlock_clk.common,
664
-
&bus_codec_clk.common,
665
-
&bus_spdif_clk.common,
666
-
&bus_pio_clk.common,
667
-
&bus_ths_clk.common,
668
-
&bus_i2s0_clk.common,
669
-
&bus_i2s1_clk.common,
670
-
&bus_i2s2_clk.common,
671
-
&bus_i2c0_clk.common,
672
-
&bus_i2c1_clk.common,
673
-
&bus_i2c2_clk.common,
674
-
&bus_uart0_clk.common,
675
-
&bus_uart1_clk.common,
676
-
&bus_uart2_clk.common,
677
-
&bus_uart3_clk.common,
678
-
&bus_scr0_clk.common,
679
-
&bus_scr1_clk.common,
680
-
&bus_ephy_clk.common,
681
-
&bus_dbg_clk.common,
682
-
&ths_clk.common,
683
-
&nand_clk.common,
684
-
&mmc0_clk.common,
685
-
&mmc1_clk.common,
686
-
&mmc2_clk.common,
687
578
&ts_clk.common,
688
579
&ce_clk.common,
689
580
&spi0_clk.common,
···
1009
1116
};
1010
1117
1011
1118
static const struct sunxi_ccu_desc sun50i_h5_ccu_desc = {
1012
-
.ccu_clks = sun50i_h5_ccu_clks,
1013
-
.num_ccu_clks = ARRAY_SIZE(sun50i_h5_ccu_clks),
1119
+
.ccu_clks = sun8i_h3_ccu_clks,
1120
+
.num_ccu_clks = ARRAY_SIZE(sun8i_h3_ccu_clks),
1014
1121
1015
1122
.hw_clks = &sun50i_h5_hw_clks,
1016
1123
+8
-32
drivers/clk/sunxi-ng/ccu-sun8i-r.c
+8
-32
drivers/clk/sunxi-ng/ccu-sun8i-r.c
···
114
114
},
115
115
};
116
116
117
-
static struct ccu_common *sun8i_a83t_r_ccu_clks[] = {
117
+
static struct ccu_common *sun8i_r_ccu_clks[] = {
118
118
&ar100_clk.common,
119
119
&apb0_clk.common,
120
120
&apb0_pio_clk.common,
···
124
124
&apb0_uart_clk.common,
125
125
&apb0_i2c_clk.common,
126
126
&apb0_twd_clk.common,
127
+
&ir_clk.common,
127
128
&a83t_ir_clk.common,
128
-
};
129
-
130
-
static struct ccu_common *sun8i_h3_r_ccu_clks[] = {
131
-
&ar100_clk.common,
132
-
&apb0_clk.common,
133
-
&apb0_pio_clk.common,
134
-
&apb0_ir_clk.common,
135
-
&apb0_timer_clk.common,
136
-
&apb0_uart_clk.common,
137
-
&apb0_i2c_clk.common,
138
-
&apb0_twd_clk.common,
139
-
&ir_clk.common,
140
-
};
141
-
142
-
static struct ccu_common *sun50i_a64_r_ccu_clks[] = {
143
-
&ar100_clk.common,
144
-
&apb0_clk.common,
145
-
&apb0_pio_clk.common,
146
-
&apb0_ir_clk.common,
147
-
&apb0_timer_clk.common,
148
-
&apb0_rsb_clk.common,
149
-
&apb0_uart_clk.common,
150
-
&apb0_i2c_clk.common,
151
-
&apb0_twd_clk.common,
152
-
&ir_clk.common,
153
129
};
154
130
155
131
static struct clk_hw_onecell_data sun8i_a83t_r_hw_clks = {
···
202
226
};
203
227
204
228
static const struct sunxi_ccu_desc sun8i_a83t_r_ccu_desc = {
205
-
.ccu_clks = sun8i_a83t_r_ccu_clks,
206
-
.num_ccu_clks = ARRAY_SIZE(sun8i_a83t_r_ccu_clks),
229
+
.ccu_clks = sun8i_r_ccu_clks,
230
+
.num_ccu_clks = ARRAY_SIZE(sun8i_r_ccu_clks),
207
231
208
232
.hw_clks = &sun8i_a83t_r_hw_clks,
209
233
···
212
236
};
213
237
214
238
static const struct sunxi_ccu_desc sun8i_h3_r_ccu_desc = {
215
-
.ccu_clks = sun8i_h3_r_ccu_clks,
216
-
.num_ccu_clks = ARRAY_SIZE(sun8i_h3_r_ccu_clks),
239
+
.ccu_clks = sun8i_r_ccu_clks,
240
+
.num_ccu_clks = ARRAY_SIZE(sun8i_r_ccu_clks),
217
241
218
242
.hw_clks = &sun8i_h3_r_hw_clks,
219
243
···
222
246
};
223
247
224
248
static const struct sunxi_ccu_desc sun50i_a64_r_ccu_desc = {
225
-
.ccu_clks = sun50i_a64_r_ccu_clks,
226
-
.num_ccu_clks = ARRAY_SIZE(sun50i_a64_r_ccu_clks),
249
+
.ccu_clks = sun8i_r_ccu_clks,
250
+
.num_ccu_clks = ARRAY_SIZE(sun8i_r_ccu_clks),
227
251
228
252
.hw_clks = &sun50i_a64_r_hw_clks,
229
253
+6
-78
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
+6
-78
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
···
421
421
&bus_de_clk.common,
422
422
&bus_codec_clk.common,
423
423
&bus_pio_clk.common,
424
-
&bus_i2c0_clk.common,
425
-
&bus_i2c1_clk.common,
426
-
&bus_uart0_clk.common,
427
-
&bus_uart1_clk.common,
428
-
&bus_uart2_clk.common,
429
-
&bus_ephy_clk.common,
430
-
&bus_dbg_clk.common,
431
-
&mmc0_clk.common,
432
-
&mmc0_sample_clk.common,
433
-
&mmc0_output_clk.common,
434
-
&mmc1_clk.common,
435
-
&mmc1_sample_clk.common,
436
-
&mmc1_output_clk.common,
437
-
&mmc2_clk.common,
438
-
&mmc2_sample_clk.common,
439
-
&mmc2_output_clk.common,
440
-
&ce_clk.common,
441
-
&spi0_clk.common,
442
-
&usb_phy0_clk.common,
443
-
&usb_ohci0_clk.common,
444
-
&dram_clk.common,
445
-
&dram_ve_clk.common,
446
-
&dram_csi_clk.common,
447
-
&dram_ohci_clk.common,
448
-
&dram_ehci_clk.common,
449
-
&de_clk.common,
450
-
&tcon_clk.common,
451
-
&csi_misc_clk.common,
452
-
&csi0_mclk_clk.common,
453
-
&csi1_sclk_clk.common,
454
-
&csi1_mclk_clk.common,
455
-
&ve_clk.common,
456
-
&ac_dig_clk.common,
457
-
&avs_clk.common,
458
-
&mbus_clk.common,
459
-
&mipi_csi_clk.common,
460
-
};
461
-
462
-
static const struct clk_hw *clk_parent_pll_audio[] = {
463
-
&pll_audio_base_clk.common.hw
464
-
};
465
-
466
-
static struct ccu_common *sun8i_v3_ccu_clks[] = {
467
-
&pll_cpu_clk.common,
468
-
&pll_audio_base_clk.common,
469
-
&pll_video_clk.common,
470
-
&pll_ve_clk.common,
471
-
&pll_ddr0_clk.common,
472
-
&pll_periph0_clk.common,
473
-
&pll_isp_clk.common,
474
-
&pll_periph1_clk.common,
475
-
&pll_ddr1_clk.common,
476
-
&cpu_clk.common,
477
-
&axi_clk.common,
478
-
&ahb1_clk.common,
479
-
&apb1_clk.common,
480
-
&apb2_clk.common,
481
-
&ahb2_clk.common,
482
-
&bus_ce_clk.common,
483
-
&bus_dma_clk.common,
484
-
&bus_mmc0_clk.common,
485
-
&bus_mmc1_clk.common,
486
-
&bus_mmc2_clk.common,
487
-
&bus_dram_clk.common,
488
-
&bus_emac_clk.common,
489
-
&bus_hstimer_clk.common,
490
-
&bus_spi0_clk.common,
491
-
&bus_otg_clk.common,
492
-
&bus_ehci0_clk.common,
493
-
&bus_ohci0_clk.common,
494
-
&bus_ve_clk.common,
495
-
&bus_tcon0_clk.common,
496
-
&bus_csi_clk.common,
497
-
&bus_de_clk.common,
498
-
&bus_codec_clk.common,
499
-
&bus_pio_clk.common,
500
424
&bus_i2s0_clk.common,
501
425
&bus_i2c0_clk.common,
502
426
&bus_i2c1_clk.common,
···
459
535
&avs_clk.common,
460
536
&mbus_clk.common,
461
537
&mipi_csi_clk.common,
538
+
};
539
+
540
+
static const struct clk_hw *clk_parent_pll_audio[] = {
541
+
&pll_audio_base_clk.common.hw
462
542
};
463
543
464
544
/* We hardcode the divider to 1 for SDM support */
···
726
798
};
727
799
728
800
static const struct sunxi_ccu_desc sun8i_v3_ccu_desc = {
729
-
.ccu_clks = sun8i_v3_ccu_clks,
730
-
.num_ccu_clks = ARRAY_SIZE(sun8i_v3_ccu_clks),
801
+
.ccu_clks = sun8i_v3s_ccu_clks,
802
+
.num_ccu_clks = ARRAY_SIZE(sun8i_v3s_ccu_clks),
731
803
732
804
.hw_clks = &sun8i_v3_hw_clks,
733
805
+1
-3
drivers/clk/sunxi/Kconfig
+1
-3
drivers/clk/sunxi/Kconfig
···
1
1
# SPDX-License-Identifier: GPL-2.0-only
2
2
menuconfig CLK_SUNXI
3
3
bool "Legacy clock support for Allwinner SoCs"
4
-
depends on ARCH_SUNXI || COMPILE_TEST
4
+
depends on (ARM && ARCH_SUNXI) || COMPILE_TEST
5
5
default y
6
6
7
7
if CLK_SUNXI
···
19
19
20
20
config CLK_SUNXI_PRCM_SUN6I
21
21
bool "Legacy A31 PRCM driver"
22
-
select MFD_SUN6I_PRCM
23
22
default y
24
23
help
25
24
Legacy clock driver for the A31 PRCM clocks. Those are
···
26
27
27
28
config CLK_SUNXI_PRCM_SUN8I
28
29
bool "Legacy sun8i PRCM driver"
29
-
select MFD_SUN6I_PRCM
30
30
default y
31
31
help
32
32
Legacy clock driver for the sun8i family PRCM clocks.
+105
-105
drivers/clk/ti/clk-44xx.c
+105
-105
drivers/clk/ti/clk-44xx.c
···
56
56
};
57
57
58
58
static const char * const omap4_func_dmic_abe_gfclk_parents[] __initconst = {
59
-
"abe_cm:clk:0018:26",
59
+
"abe-clkctrl:0018:26",
60
60
"pad_clks_ck",
61
61
"slimbus_clk",
62
62
NULL,
···
76
76
};
77
77
78
78
static const char * const omap4_func_mcasp_abe_gfclk_parents[] __initconst = {
79
-
"abe_cm:clk:0020:26",
79
+
"abe-clkctrl:0020:26",
80
80
"pad_clks_ck",
81
81
"slimbus_clk",
82
82
NULL,
···
89
89
};
90
90
91
91
static const char * const omap4_func_mcbsp1_gfclk_parents[] __initconst = {
92
-
"abe_cm:clk:0028:26",
92
+
"abe-clkctrl:0028:26",
93
93
"pad_clks_ck",
94
94
"slimbus_clk",
95
95
NULL,
···
102
102
};
103
103
104
104
static const char * const omap4_func_mcbsp2_gfclk_parents[] __initconst = {
105
-
"abe_cm:clk:0030:26",
105
+
"abe-clkctrl:0030:26",
106
106
"pad_clks_ck",
107
107
"slimbus_clk",
108
108
NULL,
···
115
115
};
116
116
117
117
static const char * const omap4_func_mcbsp3_gfclk_parents[] __initconst = {
118
-
"abe_cm:clk:0038:26",
118
+
"abe-clkctrl:0038:26",
119
119
"pad_clks_ck",
120
120
"slimbus_clk",
121
121
NULL,
···
183
183
184
184
static const struct omap_clkctrl_reg_data omap4_abe_clkctrl_regs[] __initconst = {
185
185
{ OMAP4_L4_ABE_CLKCTRL, NULL, 0, "ocp_abe_iclk" },
186
-
{ OMAP4_AESS_CLKCTRL, omap4_aess_bit_data, CLKF_SW_SUP, "abe_cm:clk:0008:24" },
186
+
{ OMAP4_AESS_CLKCTRL, omap4_aess_bit_data, CLKF_SW_SUP, "abe-clkctrl:0008:24" },
187
187
{ OMAP4_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" },
188
-
{ OMAP4_DMIC_CLKCTRL, omap4_dmic_bit_data, CLKF_SW_SUP, "abe_cm:clk:0018:24" },
189
-
{ OMAP4_MCASP_CLKCTRL, omap4_mcasp_bit_data, CLKF_SW_SUP, "abe_cm:clk:0020:24" },
190
-
{ OMAP4_MCBSP1_CLKCTRL, omap4_mcbsp1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0028:24" },
191
-
{ OMAP4_MCBSP2_CLKCTRL, omap4_mcbsp2_bit_data, CLKF_SW_SUP, "abe_cm:clk:0030:24" },
192
-
{ OMAP4_MCBSP3_CLKCTRL, omap4_mcbsp3_bit_data, CLKF_SW_SUP, "abe_cm:clk:0038:24" },
193
-
{ OMAP4_SLIMBUS1_CLKCTRL, omap4_slimbus1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0040:8" },
194
-
{ OMAP4_TIMER5_CLKCTRL, omap4_timer5_bit_data, CLKF_SW_SUP, "abe_cm:clk:0048:24" },
195
-
{ OMAP4_TIMER6_CLKCTRL, omap4_timer6_bit_data, CLKF_SW_SUP, "abe_cm:clk:0050:24" },
196
-
{ OMAP4_TIMER7_CLKCTRL, omap4_timer7_bit_data, CLKF_SW_SUP, "abe_cm:clk:0058:24" },
197
-
{ OMAP4_TIMER8_CLKCTRL, omap4_timer8_bit_data, CLKF_SW_SUP, "abe_cm:clk:0060:24" },
188
+
{ OMAP4_DMIC_CLKCTRL, omap4_dmic_bit_data, CLKF_SW_SUP, "abe-clkctrl:0018:24" },
189
+
{ OMAP4_MCASP_CLKCTRL, omap4_mcasp_bit_data, CLKF_SW_SUP, "abe-clkctrl:0020:24" },
190
+
{ OMAP4_MCBSP1_CLKCTRL, omap4_mcbsp1_bit_data, CLKF_SW_SUP, "abe-clkctrl:0028:24" },
191
+
{ OMAP4_MCBSP2_CLKCTRL, omap4_mcbsp2_bit_data, CLKF_SW_SUP, "abe-clkctrl:0030:24" },
192
+
{ OMAP4_MCBSP3_CLKCTRL, omap4_mcbsp3_bit_data, CLKF_SW_SUP, "abe-clkctrl:0038:24" },
193
+
{ OMAP4_SLIMBUS1_CLKCTRL, omap4_slimbus1_bit_data, CLKF_SW_SUP, "abe-clkctrl:0040:8" },
194
+
{ OMAP4_TIMER5_CLKCTRL, omap4_timer5_bit_data, CLKF_SW_SUP, "abe-clkctrl:0048:24" },
195
+
{ OMAP4_TIMER6_CLKCTRL, omap4_timer6_bit_data, CLKF_SW_SUP, "abe-clkctrl:0050:24" },
196
+
{ OMAP4_TIMER7_CLKCTRL, omap4_timer7_bit_data, CLKF_SW_SUP, "abe-clkctrl:0058:24" },
197
+
{ OMAP4_TIMER8_CLKCTRL, omap4_timer8_bit_data, CLKF_SW_SUP, "abe-clkctrl:0060:24" },
198
198
{ OMAP4_WD_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
199
199
{ 0 },
200
200
};
···
287
287
288
288
static const struct omap_clkctrl_reg_data omap4_iss_clkctrl_regs[] __initconst = {
289
289
{ OMAP4_ISS_CLKCTRL, omap4_iss_bit_data, CLKF_SW_SUP, "ducati_clk_mux_ck" },
290
-
{ OMAP4_FDIF_CLKCTRL, omap4_fdif_bit_data, CLKF_SW_SUP, "iss_cm:clk:0008:24" },
290
+
{ OMAP4_FDIF_CLKCTRL, omap4_fdif_bit_data, CLKF_SW_SUP, "iss-clkctrl:0008:24" },
291
291
{ 0 },
292
292
};
293
293
···
320
320
};
321
321
322
322
static const struct omap_clkctrl_reg_data omap4_l3_dss_clkctrl_regs[] __initconst = {
323
-
{ OMAP4_DSS_CORE_CLKCTRL, omap4_dss_core_bit_data, CLKF_SW_SUP, "l3_dss_cm:clk:0000:8" },
323
+
{ OMAP4_DSS_CORE_CLKCTRL, omap4_dss_core_bit_data, CLKF_SW_SUP, "l3-dss-clkctrl:0000:8" },
324
324
{ 0 },
325
325
};
326
326
···
336
336
};
337
337
338
338
static const struct omap_clkctrl_reg_data omap4_l3_gfx_clkctrl_regs[] __initconst = {
339
-
{ OMAP4_GPU_CLKCTRL, omap4_gpu_bit_data, CLKF_SW_SUP, "l3_gfx_cm:clk:0000:24" },
339
+
{ OMAP4_GPU_CLKCTRL, omap4_gpu_bit_data, CLKF_SW_SUP, "l3-gfx-clkctrl:0000:24" },
340
340
{ 0 },
341
341
};
342
342
···
372
372
};
373
373
374
374
static const char * const omap4_usb_host_hs_utmi_p1_clk_parents[] __initconst = {
375
-
"l3_init_cm:clk:0038:24",
375
+
"l3-init-clkctrl:0038:24",
376
376
NULL,
377
377
};
378
378
379
379
static const char * const omap4_usb_host_hs_utmi_p2_clk_parents[] __initconst = {
380
-
"l3_init_cm:clk:0038:25",
380
+
"l3-init-clkctrl:0038:25",
381
381
NULL,
382
382
};
383
383
···
418
418
};
419
419
420
420
static const char * const omap4_usb_otg_hs_xclk_parents[] __initconst = {
421
-
"l3_init_cm:clk:0040:24",
421
+
"l3-init-clkctrl:0040:24",
422
422
NULL,
423
423
};
424
424
···
452
452
};
453
453
454
454
static const struct omap_clkctrl_reg_data omap4_l3_init_clkctrl_regs[] __initconst = {
455
-
{ OMAP4_MMC1_CLKCTRL, omap4_mmc1_bit_data, CLKF_SW_SUP, "l3_init_cm:clk:0008:24" },
456
-
{ OMAP4_MMC2_CLKCTRL, omap4_mmc2_bit_data, CLKF_SW_SUP, "l3_init_cm:clk:0010:24" },
457
-
{ OMAP4_HSI_CLKCTRL, omap4_hsi_bit_data, CLKF_HW_SUP, "l3_init_cm:clk:0018:24" },
455
+
{ OMAP4_MMC1_CLKCTRL, omap4_mmc1_bit_data, CLKF_SW_SUP, "l3-init-clkctrl:0008:24" },
456
+
{ OMAP4_MMC2_CLKCTRL, omap4_mmc2_bit_data, CLKF_SW_SUP, "l3-init-clkctrl:0010:24" },
457
+
{ OMAP4_HSI_CLKCTRL, omap4_hsi_bit_data, CLKF_HW_SUP, "l3-init-clkctrl:0018:24" },
458
458
{ OMAP4_USB_HOST_HS_CLKCTRL, omap4_usb_host_hs_bit_data, CLKF_SW_SUP, "init_60m_fclk" },
459
459
{ OMAP4_USB_OTG_HS_CLKCTRL, omap4_usb_otg_hs_bit_data, CLKF_HW_SUP, "l3_div_ck" },
460
460
{ OMAP4_USB_TLL_HS_CLKCTRL, omap4_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_div_ck" },
461
461
{ OMAP4_USB_HOST_FS_CLKCTRL, NULL, CLKF_SW_SUP, "func_48mc_fclk" },
462
-
{ OMAP4_OCP2SCP_USB_PHY_CLKCTRL, omap4_ocp2scp_usb_phy_bit_data, CLKF_HW_SUP, "l3_init_cm:clk:00c0:8" },
462
+
{ OMAP4_OCP2SCP_USB_PHY_CLKCTRL, omap4_ocp2scp_usb_phy_bit_data, CLKF_HW_SUP, "l3-init-clkctrl:00c0:8" },
463
463
{ 0 },
464
464
};
465
465
···
530
530
};
531
531
532
532
static const char * const omap4_per_mcbsp4_gfclk_parents[] __initconst = {
533
-
"l4_per_cm:clk:00c0:26",
533
+
"l4-per-clkctrl:00c0:26",
534
534
"pad_clks_ck",
535
535
NULL,
536
536
};
···
570
570
};
571
571
572
572
static const struct omap_clkctrl_reg_data omap4_l4_per_clkctrl_regs[] __initconst = {
573
-
{ OMAP4_TIMER10_CLKCTRL, omap4_timer10_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0008:24" },
574
-
{ OMAP4_TIMER11_CLKCTRL, omap4_timer11_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0010:24" },
575
-
{ OMAP4_TIMER2_CLKCTRL, omap4_timer2_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0018:24" },
576
-
{ OMAP4_TIMER3_CLKCTRL, omap4_timer3_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0020:24" },
577
-
{ OMAP4_TIMER4_CLKCTRL, omap4_timer4_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0028:24" },
578
-
{ OMAP4_TIMER9_CLKCTRL, omap4_timer9_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0030:24" },
573
+
{ OMAP4_TIMER10_CLKCTRL, omap4_timer10_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0008:24" },
574
+
{ OMAP4_TIMER11_CLKCTRL, omap4_timer11_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0010:24" },
575
+
{ OMAP4_TIMER2_CLKCTRL, omap4_timer2_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0018:24" },
576
+
{ OMAP4_TIMER3_CLKCTRL, omap4_timer3_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0020:24" },
577
+
{ OMAP4_TIMER4_CLKCTRL, omap4_timer4_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0028:24" },
578
+
{ OMAP4_TIMER9_CLKCTRL, omap4_timer9_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0030:24" },
579
579
{ OMAP4_ELM_CLKCTRL, NULL, 0, "l4_div_ck" },
580
580
{ OMAP4_GPIO2_CLKCTRL, omap4_gpio2_bit_data, CLKF_HW_SUP, "l4_div_ck" },
581
581
{ OMAP4_GPIO3_CLKCTRL, omap4_gpio3_bit_data, CLKF_HW_SUP, "l4_div_ck" },
···
588
588
{ OMAP4_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
589
589
{ OMAP4_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
590
590
{ OMAP4_L4_PER_CLKCTRL, NULL, 0, "l4_div_ck" },
591
-
{ OMAP4_MCBSP4_CLKCTRL, omap4_mcbsp4_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:00c0:24" },
591
+
{ OMAP4_MCBSP4_CLKCTRL, omap4_mcbsp4_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:00c0:24" },
592
592
{ OMAP4_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
593
593
{ OMAP4_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
594
594
{ OMAP4_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
595
595
{ OMAP4_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
596
596
{ OMAP4_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
597
597
{ OMAP4_MMC4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
598
-
{ OMAP4_SLIMBUS2_CLKCTRL, omap4_slimbus2_bit_data, CLKF_SW_SUP, "l4_per_cm:clk:0118:8" },
598
+
{ OMAP4_SLIMBUS2_CLKCTRL, omap4_slimbus2_bit_data, CLKF_SW_SUP, "l4-per-clkctrl:0118:8" },
599
599
{ OMAP4_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
600
600
{ OMAP4_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
601
601
{ OMAP4_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
···
630
630
{ OMAP4_L4_WKUP_CLKCTRL, NULL, 0, "l4_wkup_clk_mux_ck" },
631
631
{ OMAP4_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
632
632
{ OMAP4_GPIO1_CLKCTRL, omap4_gpio1_bit_data, CLKF_HW_SUP, "l4_wkup_clk_mux_ck" },
633
-
{ OMAP4_TIMER1_CLKCTRL, omap4_timer1_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0020:24" },
633
+
{ OMAP4_TIMER1_CLKCTRL, omap4_timer1_bit_data, CLKF_SW_SUP, "l4-wkup-clkctrl:0020:24" },
634
634
{ OMAP4_COUNTER_32K_CLKCTRL, NULL, 0, "sys_32k_ck" },
635
635
{ OMAP4_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
636
636
{ 0 },
···
644
644
};
645
645
646
646
static const char * const omap4_trace_clk_div_div_ck_parents[] __initconst = {
647
-
"emu_sys_cm:clk:0000:22",
647
+
"emu-sys-clkctrl:0000:22",
648
648
NULL,
649
649
};
650
650
···
662
662
};
663
663
664
664
static const char * const omap4_stm_clk_div_ck_parents[] __initconst = {
665
-
"emu_sys_cm:clk:0000:20",
665
+
"emu-sys-clkctrl:0000:20",
666
666
NULL,
667
667
};
668
668
···
716
716
* hwmod support. Once hwmod is removed, these can be removed
717
717
* also.
718
718
*/
719
-
DT_CLK(NULL, "aess_fclk", "abe_cm:0008:24"),
720
-
DT_CLK(NULL, "cm2_dm10_mux", "l4_per_cm:0008:24"),
721
-
DT_CLK(NULL, "cm2_dm11_mux", "l4_per_cm:0010:24"),
722
-
DT_CLK(NULL, "cm2_dm2_mux", "l4_per_cm:0018:24"),
723
-
DT_CLK(NULL, "cm2_dm3_mux", "l4_per_cm:0020:24"),
724
-
DT_CLK(NULL, "cm2_dm4_mux", "l4_per_cm:0028:24"),
725
-
DT_CLK(NULL, "cm2_dm9_mux", "l4_per_cm:0030:24"),
726
-
DT_CLK(NULL, "dmic_sync_mux_ck", "abe_cm:0018:26"),
727
-
DT_CLK(NULL, "dmt1_clk_mux", "l4_wkup_cm:0020:24"),
728
-
DT_CLK(NULL, "dss_48mhz_clk", "l3_dss_cm:0000:9"),
729
-
DT_CLK(NULL, "dss_dss_clk", "l3_dss_cm:0000:8"),
730
-
DT_CLK(NULL, "dss_sys_clk", "l3_dss_cm:0000:10"),
731
-
DT_CLK(NULL, "dss_tv_clk", "l3_dss_cm:0000:11"),
732
-
DT_CLK(NULL, "fdif_fck", "iss_cm:0008:24"),
733
-
DT_CLK(NULL, "func_dmic_abe_gfclk", "abe_cm:0018:24"),
734
-
DT_CLK(NULL, "func_mcasp_abe_gfclk", "abe_cm:0020:24"),
735
-
DT_CLK(NULL, "func_mcbsp1_gfclk", "abe_cm:0028:24"),
736
-
DT_CLK(NULL, "func_mcbsp2_gfclk", "abe_cm:0030:24"),
737
-
DT_CLK(NULL, "func_mcbsp3_gfclk", "abe_cm:0038:24"),
738
-
DT_CLK(NULL, "gpio1_dbclk", "l4_wkup_cm:0018:8"),
739
-
DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:0040:8"),
740
-
DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:0048:8"),
741
-
DT_CLK(NULL, "gpio4_dbclk", "l4_per_cm:0050:8"),
742
-
DT_CLK(NULL, "gpio5_dbclk", "l4_per_cm:0058:8"),
743
-
DT_CLK(NULL, "gpio6_dbclk", "l4_per_cm:0060:8"),
744
-
DT_CLK(NULL, "hsi_fck", "l3_init_cm:0018:24"),
745
-
DT_CLK(NULL, "hsmmc1_fclk", "l3_init_cm:0008:24"),
746
-
DT_CLK(NULL, "hsmmc2_fclk", "l3_init_cm:0010:24"),
747
-
DT_CLK(NULL, "iss_ctrlclk", "iss_cm:0000:8"),
748
-
DT_CLK(NULL, "mcasp_sync_mux_ck", "abe_cm:0020:26"),
749
-
DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe_cm:0028:26"),
750
-
DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe_cm:0030:26"),
751
-
DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe_cm:0038:26"),
752
-
DT_CLK(NULL, "mcbsp4_sync_mux_ck", "l4_per_cm:00c0:26"),
753
-
DT_CLK(NULL, "ocp2scp_usb_phy_phy_48m", "l3_init_cm:00c0:8"),
754
-
DT_CLK(NULL, "otg_60m_gfclk", "l3_init_cm:0040:24"),
755
-
DT_CLK(NULL, "per_mcbsp4_gfclk", "l4_per_cm:00c0:24"),
756
-
DT_CLK(NULL, "pmd_stm_clock_mux_ck", "emu_sys_cm:0000:20"),
757
-
DT_CLK(NULL, "pmd_trace_clk_mux_ck", "emu_sys_cm:0000:22"),
758
-
DT_CLK(NULL, "sgx_clk_mux", "l3_gfx_cm:0000:24"),
759
-
DT_CLK(NULL, "slimbus1_fclk_0", "abe_cm:0040:8"),
760
-
DT_CLK(NULL, "slimbus1_fclk_1", "abe_cm:0040:9"),
761
-
DT_CLK(NULL, "slimbus1_fclk_2", "abe_cm:0040:10"),
762
-
DT_CLK(NULL, "slimbus1_slimbus_clk", "abe_cm:0040:11"),
763
-
DT_CLK(NULL, "slimbus2_fclk_0", "l4_per_cm:0118:8"),
764
-
DT_CLK(NULL, "slimbus2_fclk_1", "l4_per_cm:0118:9"),
765
-
DT_CLK(NULL, "slimbus2_slimbus_clk", "l4_per_cm:0118:10"),
766
-
DT_CLK(NULL, "stm_clk_div_ck", "emu_sys_cm:0000:27"),
767
-
DT_CLK(NULL, "timer5_sync_mux", "abe_cm:0048:24"),
768
-
DT_CLK(NULL, "timer6_sync_mux", "abe_cm:0050:24"),
769
-
DT_CLK(NULL, "timer7_sync_mux", "abe_cm:0058:24"),
770
-
DT_CLK(NULL, "timer8_sync_mux", "abe_cm:0060:24"),
771
-
DT_CLK(NULL, "trace_clk_div_div_ck", "emu_sys_cm:0000:24"),
772
-
DT_CLK(NULL, "usb_host_hs_func48mclk", "l3_init_cm:0038:15"),
773
-
DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3_init_cm:0038:13"),
774
-
DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3_init_cm:0038:14"),
775
-
DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3_init_cm:0038:11"),
776
-
DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3_init_cm:0038:12"),
777
-
DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3_init_cm:0038:8"),
778
-
DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3_init_cm:0038:9"),
779
-
DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3_init_cm:0038:10"),
780
-
DT_CLK(NULL, "usb_otg_hs_xclk", "l3_init_cm:0040:8"),
781
-
DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3_init_cm:0048:8"),
782
-
DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3_init_cm:0048:9"),
783
-
DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3_init_cm:0048:10"),
784
-
DT_CLK(NULL, "utmi_p1_gfclk", "l3_init_cm:0038:24"),
785
-
DT_CLK(NULL, "utmi_p2_gfclk", "l3_init_cm:0038:25"),
719
+
DT_CLK(NULL, "aess_fclk", "abe-clkctrl:0008:24"),
720
+
DT_CLK(NULL, "cm2_dm10_mux", "l4-per-clkctrl:0008:24"),
721
+
DT_CLK(NULL, "cm2_dm11_mux", "l4-per-clkctrl:0010:24"),
722
+
DT_CLK(NULL, "cm2_dm2_mux", "l4-per-clkctrl:0018:24"),
723
+
DT_CLK(NULL, "cm2_dm3_mux", "l4-per-clkctrl:0020:24"),
724
+
DT_CLK(NULL, "cm2_dm4_mux", "l4-per-clkctrl:0028:24"),
725
+
DT_CLK(NULL, "cm2_dm9_mux", "l4-per-clkctrl:0030:24"),
726
+
DT_CLK(NULL, "dmic_sync_mux_ck", "abe-clkctrl:0018:26"),
727
+
DT_CLK(NULL, "dmt1_clk_mux", "l4-wkup-clkctrl:0020:24"),
728
+
DT_CLK(NULL, "dss_48mhz_clk", "l3-dss-clkctrl:0000:9"),
729
+
DT_CLK(NULL, "dss_dss_clk", "l3-dss-clkctrl:0000:8"),
730
+
DT_CLK(NULL, "dss_sys_clk", "l3-dss-clkctrl:0000:10"),
731
+
DT_CLK(NULL, "dss_tv_clk", "l3-dss-clkctrl:0000:11"),
732
+
DT_CLK(NULL, "fdif_fck", "iss-clkctrl:0008:24"),
733
+
DT_CLK(NULL, "func_dmic_abe_gfclk", "abe-clkctrl:0018:24"),
734
+
DT_CLK(NULL, "func_mcasp_abe_gfclk", "abe-clkctrl:0020:24"),
735
+
DT_CLK(NULL, "func_mcbsp1_gfclk", "abe-clkctrl:0028:24"),
736
+
DT_CLK(NULL, "func_mcbsp2_gfclk", "abe-clkctrl:0030:24"),
737
+
DT_CLK(NULL, "func_mcbsp3_gfclk", "abe-clkctrl:0038:24"),
738
+
DT_CLK(NULL, "gpio1_dbclk", "l4-wkup-clkctrl:0018:8"),
739
+
DT_CLK(NULL, "gpio2_dbclk", "l4-per-clkctrl:0040:8"),
740
+
DT_CLK(NULL, "gpio3_dbclk", "l4-per-clkctrl:0048:8"),
741
+
DT_CLK(NULL, "gpio4_dbclk", "l4-per-clkctrl:0050:8"),
742
+
DT_CLK(NULL, "gpio5_dbclk", "l4-per-clkctrl:0058:8"),
743
+
DT_CLK(NULL, "gpio6_dbclk", "l4-per-clkctrl:0060:8"),
744
+
DT_CLK(NULL, "hsi_fck", "l3-init-clkctrl:0018:24"),
745
+
DT_CLK(NULL, "hsmmc1_fclk", "l3-init-clkctrl:0008:24"),
746
+
DT_CLK(NULL, "hsmmc2_fclk", "l3-init-clkctrl:0010:24"),
747
+
DT_CLK(NULL, "iss_ctrlclk", "iss-clkctrl:0000:8"),
748
+
DT_CLK(NULL, "mcasp_sync_mux_ck", "abe-clkctrl:0020:26"),
749
+
DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe-clkctrl:0028:26"),
750
+
DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe-clkctrl:0030:26"),
751
+
DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe-clkctrl:0038:26"),
752
+
DT_CLK(NULL, "mcbsp4_sync_mux_ck", "l4-per-clkctrl:00c0:26"),
753
+
DT_CLK(NULL, "ocp2scp_usb_phy_phy_48m", "l3-init-clkctrl:00c0:8"),
754
+
DT_CLK(NULL, "otg_60m_gfclk", "l3-init-clkctrl:0040:24"),
755
+
DT_CLK(NULL, "per_mcbsp4_gfclk", "l4-per-clkctrl:00c0:24"),
756
+
DT_CLK(NULL, "pmd_stm_clock_mux_ck", "emu-sys-clkctrl:0000:20"),
757
+
DT_CLK(NULL, "pmd_trace_clk_mux_ck", "emu-sys-clkctrl:0000:22"),
758
+
DT_CLK(NULL, "sgx_clk_mux", "l3-gfx-clkctrl:0000:24"),
759
+
DT_CLK(NULL, "slimbus1_fclk_0", "abe-clkctrl:0040:8"),
760
+
DT_CLK(NULL, "slimbus1_fclk_1", "abe-clkctrl:0040:9"),
761
+
DT_CLK(NULL, "slimbus1_fclk_2", "abe-clkctrl:0040:10"),
762
+
DT_CLK(NULL, "slimbus1_slimbus_clk", "abe-clkctrl:0040:11"),
763
+
DT_CLK(NULL, "slimbus2_fclk_0", "l4-per-clkctrl:0118:8"),
764
+
DT_CLK(NULL, "slimbus2_fclk_1", "l4-per-clkctrl:0118:9"),
765
+
DT_CLK(NULL, "slimbus2_slimbus_clk", "l4-per-clkctrl:0118:10"),
766
+
DT_CLK(NULL, "stm_clk_div_ck", "emu-sys-clkctrl:0000:27"),
767
+
DT_CLK(NULL, "timer5_sync_mux", "abe-clkctrl:0048:24"),
768
+
DT_CLK(NULL, "timer6_sync_mux", "abe-clkctrl:0050:24"),
769
+
DT_CLK(NULL, "timer7_sync_mux", "abe-clkctrl:0058:24"),
770
+
DT_CLK(NULL, "timer8_sync_mux", "abe-clkctrl:0060:24"),
771
+
DT_CLK(NULL, "trace_clk_div_div_ck", "emu-sys-clkctrl:0000:24"),
772
+
DT_CLK(NULL, "usb_host_hs_func48mclk", "l3-init-clkctrl:0038:15"),
773
+
DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3-init-clkctrl:0038:13"),
774
+
DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3-init-clkctrl:0038:14"),
775
+
DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3-init-clkctrl:0038:11"),
776
+
DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3-init-clkctrl:0038:12"),
777
+
DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3-init-clkctrl:0038:8"),
778
+
DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3-init-clkctrl:0038:9"),
779
+
DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3_init-clkctrl:0038:10"),
780
+
DT_CLK(NULL, "usb_otg_hs_xclk", "l3-init-clkctrl:0040:8"),
781
+
DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3-init-clkctrl:0048:8"),
782
+
DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3-init-clkctrl:0048:9"),
783
+
DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3-init-clkctrl:0048:10"),
784
+
DT_CLK(NULL, "utmi_p1_gfclk", "l3-init-clkctrl:0038:24"),
785
+
DT_CLK(NULL, "utmi_p2_gfclk", "l3-init-clkctrl:0038:25"),
786
786
{ .node_name = NULL },
787
787
};
788
788
+80
-80
drivers/clk/ti/clk-54xx.c
+80
-80
drivers/clk/ti/clk-54xx.c
···
50
50
};
51
51
52
52
static const char * const omap5_dmic_gfclk_parents[] __initconst = {
53
-
"abe_cm:clk:0018:26",
53
+
"abe-clkctrl:0018:26",
54
54
"pad_clks_ck",
55
55
"slimbus_clk",
56
56
NULL,
···
70
70
};
71
71
72
72
static const char * const omap5_mcbsp1_gfclk_parents[] __initconst = {
73
-
"abe_cm:clk:0028:26",
73
+
"abe-clkctrl:0028:26",
74
74
"pad_clks_ck",
75
75
"slimbus_clk",
76
76
NULL,
···
83
83
};
84
84
85
85
static const char * const omap5_mcbsp2_gfclk_parents[] __initconst = {
86
-
"abe_cm:clk:0030:26",
86
+
"abe-clkctrl:0030:26",
87
87
"pad_clks_ck",
88
88
"slimbus_clk",
89
89
NULL,
···
96
96
};
97
97
98
98
static const char * const omap5_mcbsp3_gfclk_parents[] __initconst = {
99
-
"abe_cm:clk:0038:26",
99
+
"abe-clkctrl:0038:26",
100
100
"pad_clks_ck",
101
101
"slimbus_clk",
102
102
NULL,
···
136
136
137
137
static const struct omap_clkctrl_reg_data omap5_abe_clkctrl_regs[] __initconst = {
138
138
{ OMAP5_L4_ABE_CLKCTRL, NULL, 0, "abe_iclk" },
139
-
{ OMAP5_AESS_CLKCTRL, omap5_aess_bit_data, CLKF_SW_SUP, "abe_cm:clk:0008:24" },
139
+
{ OMAP5_AESS_CLKCTRL, omap5_aess_bit_data, CLKF_SW_SUP, "abe-clkctrl:0008:24" },
140
140
{ OMAP5_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" },
141
-
{ OMAP5_DMIC_CLKCTRL, omap5_dmic_bit_data, CLKF_SW_SUP, "abe_cm:clk:0018:24" },
142
-
{ OMAP5_MCBSP1_CLKCTRL, omap5_mcbsp1_bit_data, CLKF_SW_SUP, "abe_cm:clk:0028:24" },
143
-
{ OMAP5_MCBSP2_CLKCTRL, omap5_mcbsp2_bit_data, CLKF_SW_SUP, "abe_cm:clk:0030:24" },
144
-
{ OMAP5_MCBSP3_CLKCTRL, omap5_mcbsp3_bit_data, CLKF_SW_SUP, "abe_cm:clk:0038:24" },
145
-
{ OMAP5_TIMER5_CLKCTRL, omap5_timer5_bit_data, CLKF_SW_SUP, "abe_cm:clk:0048:24" },
146
-
{ OMAP5_TIMER6_CLKCTRL, omap5_timer6_bit_data, CLKF_SW_SUP, "abe_cm:clk:0050:24" },
147
-
{ OMAP5_TIMER7_CLKCTRL, omap5_timer7_bit_data, CLKF_SW_SUP, "abe_cm:clk:0058:24" },
148
-
{ OMAP5_TIMER8_CLKCTRL, omap5_timer8_bit_data, CLKF_SW_SUP, "abe_cm:clk:0060:24" },
141
+
{ OMAP5_DMIC_CLKCTRL, omap5_dmic_bit_data, CLKF_SW_SUP, "abe-clkctrl:0018:24" },
142
+
{ OMAP5_MCBSP1_CLKCTRL, omap5_mcbsp1_bit_data, CLKF_SW_SUP, "abe-clkctrl:0028:24" },
143
+
{ OMAP5_MCBSP2_CLKCTRL, omap5_mcbsp2_bit_data, CLKF_SW_SUP, "abe-clkctrl:0030:24" },
144
+
{ OMAP5_MCBSP3_CLKCTRL, omap5_mcbsp3_bit_data, CLKF_SW_SUP, "abe-clkctrl:0038:24" },
145
+
{ OMAP5_TIMER5_CLKCTRL, omap5_timer5_bit_data, CLKF_SW_SUP, "abe-clkctrl:0048:24" },
146
+
{ OMAP5_TIMER6_CLKCTRL, omap5_timer6_bit_data, CLKF_SW_SUP, "abe-clkctrl:0050:24" },
147
+
{ OMAP5_TIMER7_CLKCTRL, omap5_timer7_bit_data, CLKF_SW_SUP, "abe-clkctrl:0058:24" },
148
+
{ OMAP5_TIMER8_CLKCTRL, omap5_timer8_bit_data, CLKF_SW_SUP, "abe-clkctrl:0060:24" },
149
149
{ 0 },
150
150
};
151
151
···
268
268
};
269
269
270
270
static const struct omap_clkctrl_reg_data omap5_l4per_clkctrl_regs[] __initconst = {
271
-
{ OMAP5_TIMER10_CLKCTRL, omap5_timer10_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0008:24" },
272
-
{ OMAP5_TIMER11_CLKCTRL, omap5_timer11_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0010:24" },
273
-
{ OMAP5_TIMER2_CLKCTRL, omap5_timer2_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0018:24" },
274
-
{ OMAP5_TIMER3_CLKCTRL, omap5_timer3_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0020:24" },
275
-
{ OMAP5_TIMER4_CLKCTRL, omap5_timer4_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0028:24" },
276
-
{ OMAP5_TIMER9_CLKCTRL, omap5_timer9_bit_data, CLKF_SW_SUP, "l4per_cm:clk:0030:24" },
271
+
{ OMAP5_TIMER10_CLKCTRL, omap5_timer10_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0008:24" },
272
+
{ OMAP5_TIMER11_CLKCTRL, omap5_timer11_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0010:24" },
273
+
{ OMAP5_TIMER2_CLKCTRL, omap5_timer2_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0018:24" },
274
+
{ OMAP5_TIMER3_CLKCTRL, omap5_timer3_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0020:24" },
275
+
{ OMAP5_TIMER4_CLKCTRL, omap5_timer4_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0028:24" },
276
+
{ OMAP5_TIMER9_CLKCTRL, omap5_timer9_bit_data, CLKF_SW_SUP, "l4per-clkctrl:0030:24" },
277
277
{ OMAP5_GPIO2_CLKCTRL, omap5_gpio2_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
278
278
{ OMAP5_GPIO3_CLKCTRL, omap5_gpio3_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
279
279
{ OMAP5_GPIO4_CLKCTRL, omap5_gpio4_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
···
345
345
};
346
346
347
347
static const struct omap_clkctrl_reg_data omap5_dss_clkctrl_regs[] __initconst = {
348
-
{ OMAP5_DSS_CORE_CLKCTRL, omap5_dss_core_bit_data, CLKF_SW_SUP, "dss_cm:clk:0000:8" },
348
+
{ OMAP5_DSS_CORE_CLKCTRL, omap5_dss_core_bit_data, CLKF_SW_SUP, "dss-clkctrl:0000:8" },
349
349
{ 0 },
350
350
};
351
351
···
378
378
};
379
379
380
380
static const struct omap_clkctrl_reg_data omap5_gpu_clkctrl_regs[] __initconst = {
381
-
{ OMAP5_GPU_CLKCTRL, omap5_gpu_core_bit_data, CLKF_SW_SUP, "gpu_cm:clk:0000:24" },
381
+
{ OMAP5_GPU_CLKCTRL, omap5_gpu_core_bit_data, CLKF_SW_SUP, "gpu-clkctrl:0000:24" },
382
382
{ 0 },
383
383
};
384
384
···
389
389
};
390
390
391
391
static const char * const omap5_mmc1_fclk_parents[] __initconst = {
392
-
"l3init_cm:clk:0008:24",
392
+
"l3init-clkctrl:0008:24",
393
393
NULL,
394
394
};
395
395
···
405
405
};
406
406
407
407
static const char * const omap5_mmc2_fclk_parents[] __initconst = {
408
-
"l3init_cm:clk:0010:24",
408
+
"l3init-clkctrl:0010:24",
409
409
NULL,
410
410
};
411
411
···
430
430
};
431
431
432
432
static const char * const omap5_usb_host_hs_utmi_p1_clk_parents[] __initconst = {
433
-
"l3init_cm:clk:0038:24",
433
+
"l3init-clkctrl:0038:24",
434
434
NULL,
435
435
};
436
436
437
437
static const char * const omap5_usb_host_hs_utmi_p2_clk_parents[] __initconst = {
438
-
"l3init_cm:clk:0038:25",
438
+
"l3init-clkctrl:0038:25",
439
439
NULL,
440
440
};
441
441
···
494
494
};
495
495
496
496
static const struct omap_clkctrl_reg_data omap5_l3init_clkctrl_regs[] __initconst = {
497
-
{ OMAP5_MMC1_CLKCTRL, omap5_mmc1_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0008:25" },
498
-
{ OMAP5_MMC2_CLKCTRL, omap5_mmc2_bit_data, CLKF_SW_SUP, "l3init_cm:clk:0010:25" },
497
+
{ OMAP5_MMC1_CLKCTRL, omap5_mmc1_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0008:25" },
498
+
{ OMAP5_MMC2_CLKCTRL, omap5_mmc2_bit_data, CLKF_SW_SUP, "l3init-clkctrl:0010:25" },
499
499
{ OMAP5_USB_HOST_HS_CLKCTRL, omap5_usb_host_hs_bit_data, CLKF_SW_SUP, "l3init_60m_fclk" },
500
500
{ OMAP5_USB_TLL_HS_CLKCTRL, omap5_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_root_clk_div" },
501
501
{ OMAP5_SATA_CLKCTRL, omap5_sata_bit_data, CLKF_SW_SUP, "func_48m_fclk" },
···
519
519
{ OMAP5_L4_WKUP_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
520
520
{ OMAP5_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
521
521
{ OMAP5_GPIO1_CLKCTRL, omap5_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },
522
-
{ OMAP5_TIMER1_CLKCTRL, omap5_timer1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0020:24" },
522
+
{ OMAP5_TIMER1_CLKCTRL, omap5_timer1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0020:24" },
523
523
{ OMAP5_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
524
524
{ OMAP5_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
525
525
{ 0 },
···
549
549
static struct ti_dt_clk omap54xx_clks[] = {
550
550
DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
551
551
DT_CLK(NULL, "sys_clkin_ck", "sys_clkin"),
552
-
DT_CLK(NULL, "dmic_gfclk", "abe_cm:0018:24"),
553
-
DT_CLK(NULL, "dmic_sync_mux_ck", "abe_cm:0018:26"),
554
-
DT_CLK(NULL, "dss_32khz_clk", "dss_cm:0000:11"),
555
-
DT_CLK(NULL, "dss_48mhz_clk", "dss_cm:0000:9"),
556
-
DT_CLK(NULL, "dss_dss_clk", "dss_cm:0000:8"),
557
-
DT_CLK(NULL, "dss_sys_clk", "dss_cm:0000:10"),
558
-
DT_CLK(NULL, "gpio1_dbclk", "wkupaon_cm:0018:8"),
559
-
DT_CLK(NULL, "gpio2_dbclk", "l4per_cm:0040:8"),
560
-
DT_CLK(NULL, "gpio3_dbclk", "l4per_cm:0048:8"),
561
-
DT_CLK(NULL, "gpio4_dbclk", "l4per_cm:0050:8"),
562
-
DT_CLK(NULL, "gpio5_dbclk", "l4per_cm:0058:8"),
563
-
DT_CLK(NULL, "gpio6_dbclk", "l4per_cm:0060:8"),
564
-
DT_CLK(NULL, "gpio7_dbclk", "l4per_cm:00f0:8"),
565
-
DT_CLK(NULL, "gpio8_dbclk", "l4per_cm:00f8:8"),
566
-
DT_CLK(NULL, "mcbsp1_gfclk", "abe_cm:0028:24"),
567
-
DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe_cm:0028:26"),
568
-
DT_CLK(NULL, "mcbsp2_gfclk", "abe_cm:0030:24"),
569
-
DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe_cm:0030:26"),
570
-
DT_CLK(NULL, "mcbsp3_gfclk", "abe_cm:0038:24"),
571
-
DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe_cm:0038:26"),
572
-
DT_CLK(NULL, "mmc1_32khz_clk", "l3init_cm:0008:8"),
573
-
DT_CLK(NULL, "mmc1_fclk", "l3init_cm:0008:25"),
574
-
DT_CLK(NULL, "mmc1_fclk_mux", "l3init_cm:0008:24"),
575
-
DT_CLK(NULL, "mmc2_fclk", "l3init_cm:0010:25"),
576
-
DT_CLK(NULL, "mmc2_fclk_mux", "l3init_cm:0010:24"),
577
-
DT_CLK(NULL, "sata_ref_clk", "l3init_cm:0068:8"),
578
-
DT_CLK(NULL, "timer10_gfclk_mux", "l4per_cm:0008:24"),
579
-
DT_CLK(NULL, "timer11_gfclk_mux", "l4per_cm:0010:24"),
580
-
DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon_cm:0020:24"),
581
-
DT_CLK(NULL, "timer2_gfclk_mux", "l4per_cm:0018:24"),
582
-
DT_CLK(NULL, "timer3_gfclk_mux", "l4per_cm:0020:24"),
583
-
DT_CLK(NULL, "timer4_gfclk_mux", "l4per_cm:0028:24"),
584
-
DT_CLK(NULL, "timer5_gfclk_mux", "abe_cm:0048:24"),
585
-
DT_CLK(NULL, "timer6_gfclk_mux", "abe_cm:0050:24"),
586
-
DT_CLK(NULL, "timer7_gfclk_mux", "abe_cm:0058:24"),
587
-
DT_CLK(NULL, "timer8_gfclk_mux", "abe_cm:0060:24"),
588
-
DT_CLK(NULL, "timer9_gfclk_mux", "l4per_cm:0030:24"),
589
-
DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3init_cm:0038:13"),
590
-
DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3init_cm:0038:14"),
591
-
DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "l3init_cm:0038:7"),
592
-
DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3init_cm:0038:11"),
593
-
DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3init_cm:0038:12"),
594
-
DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "l3init_cm:0038:6"),
595
-
DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3init_cm:0038:8"),
596
-
DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3init_cm:0038:9"),
597
-
DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3init_cm:0038:10"),
598
-
DT_CLK(NULL, "usb_otg_ss_refclk960m", "l3init_cm:00d0:8"),
599
-
DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3init_cm:0048:8"),
600
-
DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3init_cm:0048:9"),
601
-
DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3init_cm:0048:10"),
602
-
DT_CLK(NULL, "utmi_p1_gfclk", "l3init_cm:0038:24"),
603
-
DT_CLK(NULL, "utmi_p2_gfclk", "l3init_cm:0038:25"),
552
+
DT_CLK(NULL, "dmic_gfclk", "abe-clkctrl:0018:24"),
553
+
DT_CLK(NULL, "dmic_sync_mux_ck", "abe-clkctrl:0018:26"),
554
+
DT_CLK(NULL, "dss_32khz_clk", "dss-clkctrl:0000:11"),
555
+
DT_CLK(NULL, "dss_48mhz_clk", "dss-clkctrl:0000:9"),
556
+
DT_CLK(NULL, "dss_dss_clk", "dss-clkctrl:0000:8"),
557
+
DT_CLK(NULL, "dss_sys_clk", "dss-clkctrl:0000:10"),
558
+
DT_CLK(NULL, "gpio1_dbclk", "wkupaon-clkctrl:0018:8"),
559
+
DT_CLK(NULL, "gpio2_dbclk", "l4per-clkctrl:0040:8"),
560
+
DT_CLK(NULL, "gpio3_dbclk", "l4per-clkctrl:0048:8"),
561
+
DT_CLK(NULL, "gpio4_dbclk", "l4per-clkctrl:0050:8"),
562
+
DT_CLK(NULL, "gpio5_dbclk", "l4per-clkctrl:0058:8"),
563
+
DT_CLK(NULL, "gpio6_dbclk", "l4per-clkctrl:0060:8"),
564
+
DT_CLK(NULL, "gpio7_dbclk", "l4per-clkctrl:00f0:8"),
565
+
DT_CLK(NULL, "gpio8_dbclk", "l4per-clkctrl:00f8:8"),
566
+
DT_CLK(NULL, "mcbsp1_gfclk", "abe-clkctrl:0028:24"),
567
+
DT_CLK(NULL, "mcbsp1_sync_mux_ck", "abe-clkctrl:0028:26"),
568
+
DT_CLK(NULL, "mcbsp2_gfclk", "abe-clkctrl:0030:24"),
569
+
DT_CLK(NULL, "mcbsp2_sync_mux_ck", "abe-clkctrl:0030:26"),
570
+
DT_CLK(NULL, "mcbsp3_gfclk", "abe-clkctrl:0038:24"),
571
+
DT_CLK(NULL, "mcbsp3_sync_mux_ck", "abe-clkctrl:0038:26"),
572
+
DT_CLK(NULL, "mmc1_32khz_clk", "l3init-clkctrl:0008:8"),
573
+
DT_CLK(NULL, "mmc1_fclk", "l3init-clkctrl:0008:25"),
574
+
DT_CLK(NULL, "mmc1_fclk_mux", "l3init-clkctrl:0008:24"),
575
+
DT_CLK(NULL, "mmc2_fclk", "l3init-clkctrl:0010:25"),
576
+
DT_CLK(NULL, "mmc2_fclk_mux", "l3init-clkctrl:0010:24"),
577
+
DT_CLK(NULL, "sata_ref_clk", "l3init-clkctrl:0068:8"),
578
+
DT_CLK(NULL, "timer10_gfclk_mux", "l4per-clkctrl:0008:24"),
579
+
DT_CLK(NULL, "timer11_gfclk_mux", "l4per-clkctrl:0010:24"),
580
+
DT_CLK(NULL, "timer1_gfclk_mux", "wkupaon-clkctrl:0020:24"),
581
+
DT_CLK(NULL, "timer2_gfclk_mux", "l4per-clkctrl:0018:24"),
582
+
DT_CLK(NULL, "timer3_gfclk_mux", "l4per-clkctrl:0020:24"),
583
+
DT_CLK(NULL, "timer4_gfclk_mux", "l4per-clkctrl:0028:24"),
584
+
DT_CLK(NULL, "timer5_gfclk_mux", "abe-clkctrl:0048:24"),
585
+
DT_CLK(NULL, "timer6_gfclk_mux", "abe-clkctrl:0050:24"),
586
+
DT_CLK(NULL, "timer7_gfclk_mux", "abe-clkctrl:0058:24"),
587
+
DT_CLK(NULL, "timer8_gfclk_mux", "abe-clkctrl:0060:24"),
588
+
DT_CLK(NULL, "timer9_gfclk_mux", "l4per-clkctrl:0030:24"),
589
+
DT_CLK(NULL, "usb_host_hs_hsic480m_p1_clk", "l3init-clkctrl:0038:13"),
590
+
DT_CLK(NULL, "usb_host_hs_hsic480m_p2_clk", "l3init-clkctrl:0038:14"),
591
+
DT_CLK(NULL, "usb_host_hs_hsic480m_p3_clk", "l3init-clkctrl:0038:7"),
592
+
DT_CLK(NULL, "usb_host_hs_hsic60m_p1_clk", "l3init-clkctrl:0038:11"),
593
+
DT_CLK(NULL, "usb_host_hs_hsic60m_p2_clk", "l3init-clkctrl:0038:12"),
594
+
DT_CLK(NULL, "usb_host_hs_hsic60m_p3_clk", "l3init-clkctrl:0038:6"),
595
+
DT_CLK(NULL, "usb_host_hs_utmi_p1_clk", "l3init-clkctrl:0038:8"),
596
+
DT_CLK(NULL, "usb_host_hs_utmi_p2_clk", "l3init-clkctrl:0038:9"),
597
+
DT_CLK(NULL, "usb_host_hs_utmi_p3_clk", "l3init-clkctrl:0038:10"),
598
+
DT_CLK(NULL, "usb_otg_ss_refclk960m", "l3init-clkctrl:00d0:8"),
599
+
DT_CLK(NULL, "usb_tll_hs_usb_ch0_clk", "l3init-clkctrl:0048:8"),
600
+
DT_CLK(NULL, "usb_tll_hs_usb_ch1_clk", "l3init-clkctrl:0048:9"),
601
+
DT_CLK(NULL, "usb_tll_hs_usb_ch2_clk", "l3init-clkctrl:0048:10"),
602
+
DT_CLK(NULL, "utmi_p1_gfclk", "l3init-clkctrl:0038:24"),
603
+
DT_CLK(NULL, "utmi_p2_gfclk", "l3init-clkctrl:0038:25"),
604
604
{ .node_name = NULL },
605
605
};
606
606
-4
drivers/clk/ti/clkctrl.c
-4
drivers/clk/ti/clkctrl.c
···
520
520
char *c;
521
521
u16 soc_mask = 0;
522
522
523
-
if (!(ti_clk_get_features()->flags & TI_CLK_CLKCTRL_COMPAT) &&
524
-
of_node_name_eq(node, "clk"))
525
-
ti_clk_features.flags |= TI_CLK_CLKCTRL_COMPAT;
526
-
527
523
addrp = of_get_address(node, 0, NULL, NULL);
528
524
addr = (u32)of_translate_address(node, addrp);
529
525
+1
include/dt-bindings/clock/qcom,gcc-ipq8074.h
+1
include/dt-bindings/clock/qcom,gcc-ipq8074.h
+1
include/dt-bindings/clock/qcom,gcc-msm8939.h
+1
include/dt-bindings/clock/qcom,gcc-msm8939.h
+20
include/dt-bindings/clock/r9a07g043-cpg.h
+20
include/dt-bindings/clock/r9a07g043-cpg.h
···
108
108
#define R9A07G043_ADC_ADCLK 76
109
109
#define R9A07G043_ADC_PCLK 77
110
110
#define R9A07G043_TSU_PCLK 78
111
+
#define R9A07G043_NCEPLDM_DM_CLK 79 /* RZ/Five Only */
112
+
#define R9A07G043_NCEPLDM_ACLK 80 /* RZ/Five Only */
113
+
#define R9A07G043_NCEPLDM_TCK 81 /* RZ/Five Only */
114
+
#define R9A07G043_NCEPLMT_ACLK 82 /* RZ/Five Only */
115
+
#define R9A07G043_NCEPLIC_ACLK 83 /* RZ/Five Only */
116
+
#define R9A07G043_AX45MP_CORE0_CLK 84 /* RZ/Five Only */
117
+
#define R9A07G043_AX45MP_ACLK 85 /* RZ/Five Only */
118
+
#define R9A07G043_IAX45_CLK 86 /* RZ/Five Only */
119
+
#define R9A07G043_IAX45_PCLK 87 /* RZ/Five Only */
111
120
112
121
/* R9A07G043 Resets */
113
122
#define R9A07G043_CA55_RST_1_0 0 /* RZ/G2UL Only */
···
189
180
#define R9A07G043_ADC_PRESETN 67
190
181
#define R9A07G043_ADC_ADRST_N 68
191
182
#define R9A07G043_TSU_PRESETN 69
183
+
#define R9A07G043_NCEPLDM_DTM_PWR_RST_N 70 /* RZ/Five Only */
184
+
#define R9A07G043_NCEPLDM_ARESETN 71 /* RZ/Five Only */
185
+
#define R9A07G043_NCEPLMT_POR_RSTN 72 /* RZ/Five Only */
186
+
#define R9A07G043_NCEPLMT_ARESETN 73 /* RZ/Five Only */
187
+
#define R9A07G043_NCEPLIC_ARESETN 74 /* RZ/Five Only */
188
+
#define R9A07G043_AX45MP_ARESETNM 75 /* RZ/Five Only */
189
+
#define R9A07G043_AX45MP_ARESETNS 76 /* RZ/Five Only */
190
+
#define R9A07G043_AX45MP_L2_RESETN 77 /* RZ/Five Only */
191
+
#define R9A07G043_AX45MP_CORE0_RESETN 78 /* RZ/Five Only */
192
+
#define R9A07G043_IAX45_RESETN 79 /* RZ/Five Only */
193
+
192
194
193
195
#endif /* __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ */
+397
include/dt-bindings/clock/sprd,ums512-clk.h
+397
include/dt-bindings/clock/sprd,ums512-clk.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Unisoc UMS512 SoC DTS file
4
+
*
5
+
* Copyright (C) 2022, Unisoc Inc.
6
+
*/
7
+
8
+
#ifndef _DT_BINDINGS_CLK_UMS512_H_
9
+
#define _DT_BINDINGS_CLK_UMS512_H_
10
+
11
+
#define CLK_26M_AUD 0
12
+
#define CLK_13M 1
13
+
#define CLK_6M5 2
14
+
#define CLK_4M3 3
15
+
#define CLK_2M 4
16
+
#define CLK_1M 5
17
+
#define CLK_250K 6
18
+
#define CLK_RCO_25M 7
19
+
#define CLK_RCO_4M 8
20
+
#define CLK_RCO_2M 9
21
+
#define CLK_ISPPLL_GATE 10
22
+
#define CLK_DPLL0_GATE 11
23
+
#define CLK_DPLL1_GATE 12
24
+
#define CLK_LPLL_GATE 13
25
+
#define CLK_TWPLL_GATE 14
26
+
#define CLK_GPLL_GATE 15
27
+
#define CLK_RPLL_GATE 16
28
+
#define CLK_CPPLL_GATE 17
29
+
#define CLK_MPLL0_GATE 18
30
+
#define CLK_MPLL1_GATE 19
31
+
#define CLK_MPLL2_GATE 20
32
+
#define CLK_PMU_GATE_NUM (CLK_MPLL2_GATE + 1)
33
+
34
+
#define CLK_DPLL0 0
35
+
#define CLK_DPLL0_58M31 1
36
+
#define CLK_ANLG_PHY_G0_NUM (CLK_DPLL0_58M31 + 1)
37
+
38
+
#define CLK_MPLL1 0
39
+
#define CLK_MPLL1_63M38 1
40
+
#define CLK_ANLG_PHY_G2_NUM (CLK_MPLL1_63M38 + 1)
41
+
42
+
#define CLK_RPLL 0
43
+
#define CLK_AUDIO_GATE 1
44
+
#define CLK_MPLL0 2
45
+
#define CLK_MPLL0_56M88 3
46
+
#define CLK_MPLL2 4
47
+
#define CLK_MPLL2_47M13 5
48
+
#define CLK_ANLG_PHY_G3_NUM (CLK_MPLL2_47M13 + 1)
49
+
50
+
#define CLK_TWPLL 0
51
+
#define CLK_TWPLL_768M 1
52
+
#define CLK_TWPLL_384M 2
53
+
#define CLK_TWPLL_192M 3
54
+
#define CLK_TWPLL_96M 4
55
+
#define CLK_TWPLL_48M 5
56
+
#define CLK_TWPLL_24M 6
57
+
#define CLK_TWPLL_12M 7
58
+
#define CLK_TWPLL_512M 8
59
+
#define CLK_TWPLL_256M 9
60
+
#define CLK_TWPLL_128M 10
61
+
#define CLK_TWPLL_64M 11
62
+
#define CLK_TWPLL_307M2 12
63
+
#define CLK_TWPLL_219M4 13
64
+
#define CLK_TWPLL_170M6 14
65
+
#define CLK_TWPLL_153M6 15
66
+
#define CLK_TWPLL_76M8 16
67
+
#define CLK_TWPLL_51M2 17
68
+
#define CLK_TWPLL_38M4 18
69
+
#define CLK_TWPLL_19M2 19
70
+
#define CLK_TWPLL_12M29 20
71
+
#define CLK_LPLL 21
72
+
#define CLK_LPLL_614M4 22
73
+
#define CLK_LPLL_409M6 23
74
+
#define CLK_LPLL_245M76 24
75
+
#define CLK_LPLL_30M72 25
76
+
#define CLK_ISPPLL 26
77
+
#define CLK_ISPPLL_468M 27
78
+
#define CLK_ISPPLL_78M 28
79
+
#define CLK_GPLL 29
80
+
#define CLK_GPLL_40M 30
81
+
#define CLK_CPPLL 31
82
+
#define CLK_CPPLL_39M32 32
83
+
#define CLK_ANLG_PHY_GC_NUM (CLK_CPPLL_39M32 + 1)
84
+
85
+
#define CLK_AP_APB 0
86
+
#define CLK_IPI 1
87
+
#define CLK_AP_UART0 2
88
+
#define CLK_AP_UART1 3
89
+
#define CLK_AP_UART2 4
90
+
#define CLK_AP_I2C0 5
91
+
#define CLK_AP_I2C1 6
92
+
#define CLK_AP_I2C2 7
93
+
#define CLK_AP_I2C3 8
94
+
#define CLK_AP_I2C4 9
95
+
#define CLK_AP_SPI0 10
96
+
#define CLK_AP_SPI1 11
97
+
#define CLK_AP_SPI2 12
98
+
#define CLK_AP_SPI3 13
99
+
#define CLK_AP_IIS0 14
100
+
#define CLK_AP_IIS1 15
101
+
#define CLK_AP_IIS2 16
102
+
#define CLK_AP_SIM 17
103
+
#define CLK_AP_CE 18
104
+
#define CLK_SDIO0_2X 19
105
+
#define CLK_SDIO1_2X 20
106
+
#define CLK_EMMC_2X 21
107
+
#define CLK_VSP 22
108
+
#define CLK_DISPC0 23
109
+
#define CLK_DISPC0_DPI 24
110
+
#define CLK_DSI_APB 25
111
+
#define CLK_DSI_RXESC 26
112
+
#define CLK_DSI_LANEBYTE 27
113
+
#define CLK_VDSP 28
114
+
#define CLK_VDSP_M 29
115
+
#define CLK_AP_CLK_NUM (CLK_VDSP_M + 1)
116
+
117
+
#define CLK_DSI_EB 0
118
+
#define CLK_DISPC_EB 1
119
+
#define CLK_VSP_EB 2
120
+
#define CLK_VDMA_EB 3
121
+
#define CLK_DMA_PUB_EB 4
122
+
#define CLK_DMA_SEC_EB 5
123
+
#define CLK_IPI_EB 6
124
+
#define CLK_AHB_CKG_EB 7
125
+
#define CLK_BM_CLK_EB 8
126
+
#define CLK_AP_AHB_GATE_NUM (CLK_BM_CLK_EB + 1)
127
+
128
+
#define CLK_AON_APB 0
129
+
#define CLK_ADI 1
130
+
#define CLK_AUX0 2
131
+
#define CLK_AUX1 3
132
+
#define CLK_AUX2 4
133
+
#define CLK_PROBE 5
134
+
#define CLK_PWM0 6
135
+
#define CLK_PWM1 7
136
+
#define CLK_PWM2 8
137
+
#define CLK_PWM3 9
138
+
#define CLK_EFUSE 10
139
+
#define CLK_UART0 11
140
+
#define CLK_UART1 12
141
+
#define CLK_THM0 13
142
+
#define CLK_THM1 14
143
+
#define CLK_THM2 15
144
+
#define CLK_THM3 16
145
+
#define CLK_AON_I2C 17
146
+
#define CLK_AON_IIS 18
147
+
#define CLK_SCC 19
148
+
#define CLK_APCPU_DAP 20
149
+
#define CLK_APCPU_DAP_MTCK 21
150
+
#define CLK_APCPU_TS 22
151
+
#define CLK_DEBUG_TS 23
152
+
#define CLK_DSI_TEST_S 24
153
+
#define CLK_DJTAG_TCK 25
154
+
#define CLK_DJTAG_TCK_HW 26
155
+
#define CLK_AON_TMR 27
156
+
#define CLK_AON_PMU 28
157
+
#define CLK_DEBOUNCE 29
158
+
#define CLK_APCPU_PMU 30
159
+
#define CLK_TOP_DVFS 31
160
+
#define CLK_OTG_UTMI 32
161
+
#define CLK_OTG_REF 33
162
+
#define CLK_CSSYS 34
163
+
#define CLK_CSSYS_PUB 35
164
+
#define CLK_CSSYS_APB 36
165
+
#define CLK_AP_AXI 37
166
+
#define CLK_AP_MM 38
167
+
#define CLK_SDIO2_2X 39
168
+
#define CLK_ANALOG_IO_APB 40
169
+
#define CLK_DMC_REF_CLK 41
170
+
#define CLK_EMC 42
171
+
#define CLK_USB 43
172
+
#define CLK_26M_PMU 44
173
+
#define CLK_AON_APB_NUM (CLK_26M_PMU + 1)
174
+
175
+
#define CLK_MM_AHB 0
176
+
#define CLK_MM_MTX 1
177
+
#define CLK_SENSOR0 2
178
+
#define CLK_SENSOR1 3
179
+
#define CLK_SENSOR2 4
180
+
#define CLK_CPP 5
181
+
#define CLK_JPG 6
182
+
#define CLK_FD 7
183
+
#define CLK_DCAM_IF 8
184
+
#define CLK_DCAM_AXI 9
185
+
#define CLK_ISP 10
186
+
#define CLK_MIPI_CSI0 11
187
+
#define CLK_MIPI_CSI1 12
188
+
#define CLK_MIPI_CSI2 13
189
+
#define CLK_MM_CLK_NUM (CLK_MIPI_CSI2 + 1)
190
+
191
+
#define CLK_RC100M_CAL_EB 0
192
+
#define CLK_DJTAG_TCK_EB 1
193
+
#define CLK_DJTAG_EB 2
194
+
#define CLK_AUX0_EB 3
195
+
#define CLK_AUX1_EB 4
196
+
#define CLK_AUX2_EB 5
197
+
#define CLK_PROBE_EB 6
198
+
#define CLK_MM_EB 7
199
+
#define CLK_GPU_EB 8
200
+
#define CLK_MSPI_EB 9
201
+
#define CLK_APCPU_DAP_EB 10
202
+
#define CLK_AON_CSSYS_EB 11
203
+
#define CLK_CSSYS_APB_EB 12
204
+
#define CLK_CSSYS_PUB_EB 13
205
+
#define CLK_SDPHY_CFG_EB 14
206
+
#define CLK_SDPHY_REF_EB 15
207
+
#define CLK_EFUSE_EB 16
208
+
#define CLK_GPIO_EB 17
209
+
#define CLK_MBOX_EB 18
210
+
#define CLK_KPD_EB 19
211
+
#define CLK_AON_SYST_EB 20
212
+
#define CLK_AP_SYST_EB 21
213
+
#define CLK_AON_TMR_EB 22
214
+
#define CLK_OTG_UTMI_EB 23
215
+
#define CLK_OTG_PHY_EB 24
216
+
#define CLK_SPLK_EB 25
217
+
#define CLK_PIN_EB 26
218
+
#define CLK_ANA_EB 27
219
+
#define CLK_APCPU_TS0_EB 28
220
+
#define CLK_APB_BUSMON_EB 29
221
+
#define CLK_AON_IIS_EB 30
222
+
#define CLK_SCC_EB 31
223
+
#define CLK_THM0_EB 32
224
+
#define CLK_THM1_EB 33
225
+
#define CLK_THM2_EB 34
226
+
#define CLK_ASIM_TOP_EB 35
227
+
#define CLK_I2C_EB 36
228
+
#define CLK_PMU_EB 37
229
+
#define CLK_ADI_EB 38
230
+
#define CLK_EIC_EB 39
231
+
#define CLK_AP_INTC0_EB 40
232
+
#define CLK_AP_INTC1_EB 41
233
+
#define CLK_AP_INTC2_EB 42
234
+
#define CLK_AP_INTC3_EB 43
235
+
#define CLK_AP_INTC4_EB 44
236
+
#define CLK_AP_INTC5_EB 45
237
+
#define CLK_AUDCP_INTC_EB 46
238
+
#define CLK_AP_TMR0_EB 47
239
+
#define CLK_AP_TMR1_EB 48
240
+
#define CLK_AP_TMR2_EB 49
241
+
#define CLK_PWM0_EB 50
242
+
#define CLK_PWM1_EB 51
243
+
#define CLK_PWM2_EB 52
244
+
#define CLK_PWM3_EB 53
245
+
#define CLK_AP_WDG_EB 54
246
+
#define CLK_APCPU_WDG_EB 55
247
+
#define CLK_SERDES_EB 56
248
+
#define CLK_ARCH_RTC_EB 57
249
+
#define CLK_KPD_RTC_EB 58
250
+
#define CLK_AON_SYST_RTC_EB 59
251
+
#define CLK_AP_SYST_RTC_EB 60
252
+
#define CLK_AON_TMR_RTC_EB 61
253
+
#define CLK_EIC_RTC_EB 62
254
+
#define CLK_EIC_RTCDV5_EB 63
255
+
#define CLK_AP_WDG_RTC_EB 64
256
+
#define CLK_AC_WDG_RTC_EB 65
257
+
#define CLK_AP_TMR0_RTC_EB 66
258
+
#define CLK_AP_TMR1_RTC_EB 67
259
+
#define CLK_AP_TMR2_RTC_EB 68
260
+
#define CLK_DCXO_LC_RTC_EB 69
261
+
#define CLK_BB_CAL_RTC_EB 70
262
+
#define CLK_AP_EMMC_RTC_EB 71
263
+
#define CLK_AP_SDIO0_RTC_EB 72
264
+
#define CLK_AP_SDIO1_RTC_EB 73
265
+
#define CLK_AP_SDIO2_RTC_EB 74
266
+
#define CLK_DSI_CSI_TEST_EB 75
267
+
#define CLK_DJTAG_TCK_EN 76
268
+
#define CLK_DPHY_REF_EB 77
269
+
#define CLK_DMC_REF_EB 78
270
+
#define CLK_OTG_REF_EB 79
271
+
#define CLK_TSEN_EB 80
272
+
#define CLK_TMR_EB 81
273
+
#define CLK_RC100M_REF_EB 82
274
+
#define CLK_RC100M_FDK_EB 83
275
+
#define CLK_DEBOUNCE_EB 84
276
+
#define CLK_DET_32K_EB 85
277
+
#define CLK_TOP_CSSYS_EB 86
278
+
#define CLK_AP_AXI_EN 87
279
+
#define CLK_SDIO0_2X_EN 88
280
+
#define CLK_SDIO0_1X_EN 89
281
+
#define CLK_SDIO1_2X_EN 90
282
+
#define CLK_SDIO1_1X_EN 91
283
+
#define CLK_SDIO2_2X_EN 92
284
+
#define CLK_SDIO2_1X_EN 93
285
+
#define CLK_EMMC_2X_EN 94
286
+
#define CLK_EMMC_1X_EN 95
287
+
#define CLK_PLL_TEST_EN 96
288
+
#define CLK_CPHY_CFG_EN 97
289
+
#define CLK_DEBUG_TS_EN 98
290
+
#define CLK_ACCESS_AUD_EN 99
291
+
#define CLK_AON_APB_GATE_NUM (CLK_ACCESS_AUD_EN + 1)
292
+
293
+
#define CLK_MM_CPP_EB 0
294
+
#define CLK_MM_JPG_EB 1
295
+
#define CLK_MM_DCAM_EB 2
296
+
#define CLK_MM_ISP_EB 3
297
+
#define CLK_MM_CSI2_EB 4
298
+
#define CLK_MM_CSI1_EB 5
299
+
#define CLK_MM_CSI0_EB 6
300
+
#define CLK_MM_CKG_EB 7
301
+
#define CLK_ISP_AHB_EB 8
302
+
#define CLK_MM_DVFS_EB 9
303
+
#define CLK_MM_FD_EB 10
304
+
#define CLK_MM_SENSOR2_EB 11
305
+
#define CLK_MM_SENSOR1_EB 12
306
+
#define CLK_MM_SENSOR0_EB 13
307
+
#define CLK_MM_MIPI_CSI2_EB 14
308
+
#define CLK_MM_MIPI_CSI1_EB 15
309
+
#define CLK_MM_MIPI_CSI0_EB 16
310
+
#define CLK_DCAM_AXI_EB 17
311
+
#define CLK_ISP_AXI_EB 18
312
+
#define CLK_MM_CPHY_EB 19
313
+
#define CLK_MM_GATE_CLK_NUM (CLK_MM_CPHY_EB + 1)
314
+
315
+
#define CLK_SIM0_EB 0
316
+
#define CLK_IIS0_EB 1
317
+
#define CLK_IIS1_EB 2
318
+
#define CLK_IIS2_EB 3
319
+
#define CLK_APB_REG_EB 4
320
+
#define CLK_SPI0_EB 5
321
+
#define CLK_SPI1_EB 6
322
+
#define CLK_SPI2_EB 7
323
+
#define CLK_SPI3_EB 8
324
+
#define CLK_I2C0_EB 9
325
+
#define CLK_I2C1_EB 10
326
+
#define CLK_I2C2_EB 11
327
+
#define CLK_I2C3_EB 12
328
+
#define CLK_I2C4_EB 13
329
+
#define CLK_UART0_EB 14
330
+
#define CLK_UART1_EB 15
331
+
#define CLK_UART2_EB 16
332
+
#define CLK_SIM0_32K_EB 17
333
+
#define CLK_SPI0_LFIN_EB 18
334
+
#define CLK_SPI1_LFIN_EB 19
335
+
#define CLK_SPI2_LFIN_EB 20
336
+
#define CLK_SPI3_LFIN_EB 21
337
+
#define CLK_SDIO0_EB 22
338
+
#define CLK_SDIO1_EB 23
339
+
#define CLK_SDIO2_EB 24
340
+
#define CLK_EMMC_EB 25
341
+
#define CLK_SDIO0_32K_EB 26
342
+
#define CLK_SDIO1_32K_EB 27
343
+
#define CLK_SDIO2_32K_EB 28
344
+
#define CLK_EMMC_32K_EB 29
345
+
#define CLK_AP_APB_GATE_NUM (CLK_EMMC_32K_EB + 1)
346
+
347
+
#define CLK_GPU_CORE_EB 0
348
+
#define CLK_GPU_CORE 1
349
+
#define CLK_GPU_MEM_EB 2
350
+
#define CLK_GPU_MEM 3
351
+
#define CLK_GPU_SYS_EB 4
352
+
#define CLK_GPU_SYS 5
353
+
#define CLK_GPU_CLK_NUM (CLK_GPU_SYS + 1)
354
+
355
+
#define CLK_AUDCP_IIS0_EB 0
356
+
#define CLK_AUDCP_IIS1_EB 1
357
+
#define CLK_AUDCP_IIS2_EB 2
358
+
#define CLK_AUDCP_UART_EB 3
359
+
#define CLK_AUDCP_DMA_CP_EB 4
360
+
#define CLK_AUDCP_DMA_AP_EB 5
361
+
#define CLK_AUDCP_SRC48K_EB 6
362
+
#define CLK_AUDCP_MCDT_EB 7
363
+
#define CLK_AUDCP_VBCIFD_EB 8
364
+
#define CLK_AUDCP_VBC_EB 9
365
+
#define CLK_AUDCP_SPLK_EB 10
366
+
#define CLK_AUDCP_ICU_EB 11
367
+
#define CLK_AUDCP_DMA_AP_ASHB_EB 12
368
+
#define CLK_AUDCP_DMA_CP_ASHB_EB 13
369
+
#define CLK_AUDCP_AUD_EB 14
370
+
#define CLK_AUDCP_VBC_24M_EB 15
371
+
#define CLK_AUDCP_TMR_26M_EB 16
372
+
#define CLK_AUDCP_DVFS_ASHB_EB 17
373
+
#define CLK_AUDCP_AHB_GATE_NUM (CLK_AUDCP_DVFS_ASHB_EB + 1)
374
+
375
+
#define CLK_AUDCP_WDG_EB 0
376
+
#define CLK_AUDCP_RTC_WDG_EB 1
377
+
#define CLK_AUDCP_TMR0_EB 2
378
+
#define CLK_AUDCP_TMR1_EB 3
379
+
#define CLK_AUDCP_APB_GATE_NUM (CLK_AUDCP_TMR1_EB + 1)
380
+
381
+
#define CLK_ACORE0 0
382
+
#define CLK_ACORE1 1
383
+
#define CLK_ACORE2 2
384
+
#define CLK_ACORE3 3
385
+
#define CLK_ACORE4 4
386
+
#define CLK_ACORE5 5
387
+
#define CLK_PCORE0 6
388
+
#define CLK_PCORE1 7
389
+
#define CLK_SCU 8
390
+
#define CLK_ACE 9
391
+
#define CLK_PERIPH 10
392
+
#define CLK_GIC 11
393
+
#define CLK_ATB 12
394
+
#define CLK_DEBUG_APB 13
395
+
#define CLK_APCPU_SEC_NUM (CLK_DEBUG_APB + 1)
396
+
397
+
#endif /* _DT_BINDINGS_CLK_UMS512_H_ */
+5
include/dt-bindings/reset/mt8186-resets.h
+5
include/dt-bindings/reset/mt8186-resets.h
···
7
7
#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8186
8
8
#define _DT_BINDINGS_RESET_CONTROLLER_MT8186
9
9
10
+
/* TOPRGU resets */
10
11
#define MT8186_TOPRGU_INFRA_SW_RST 0
11
12
#define MT8186_TOPRGU_MM_SW_RST 1
12
13
#define MT8186_TOPRGU_MFG_SW_RST 2
···
33
32
34
33
/* MMSYS resets */
35
34
#define MT8186_MMSYS_SW0_RST_B_DISP_DSI0 19
35
+
36
+
/* INFRA resets */
37
+
#define MT8186_INFRA_THERMAL_CTRL_RST 0
38
+
#define MT8186_INFRA_PTP_CTRL_RST 1
36
39
37
40
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8186 */
+8
include/dt-bindings/reset/mt8192-resets.h
+8
include/dt-bindings/reset/mt8192-resets.h
···
7
7
#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8192
8
8
#define _DT_BINDINGS_RESET_CONTROLLER_MT8192
9
9
10
+
/* TOPRGU resets */
10
11
#define MT8192_TOPRGU_MM_SW_RST 1
11
12
#define MT8192_TOPRGU_MFG_SW_RST 2
12
13
#define MT8192_TOPRGU_VENC_SW_RST 3
···
30
29
31
30
/* MMSYS resets */
32
31
#define MT8192_MMSYS_SW0_RST_B_DISP_DSI0 15
32
+
33
+
/* INFRA resets */
34
+
#define MT8192_INFRA_RST0_THERM_CTRL_SWRST 0
35
+
#define MT8192_INFRA_RST2_PEXTP_PHY_SWRST 1
36
+
#define MT8192_INFRA_RST3_THERM_CTRL_PTP_SWRST 2
37
+
#define MT8192_INFRA_RST4_PCIE_TOP_SWRST 3
38
+
#define MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST 4
33
39
34
40
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8192 */
+6
include/dt-bindings/reset/mt8195-resets.h
+6
include/dt-bindings/reset/mt8195-resets.h
···
7
7
#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8195
8
8
#define _DT_BINDINGS_RESET_CONTROLLER_MT8195
9
9
10
+
/* TOPRGU resets */
10
11
#define MT8195_TOPRGU_CONN_MCU_SW_RST 0
11
12
#define MT8195_TOPRGU_INFRA_GRST_SW_RST 1
12
13
#define MT8195_TOPRGU_APU_SW_RST 2
···
26
25
#define MT8195_TOPRGU_SPMI_MST_SW_RST 23
27
26
28
27
#define MT8195_TOPRGU_SW_RST_NUM 16
28
+
29
+
/* INFRA resets */
30
+
#define MT8195_INFRA_RST0_THERM_CTRL_SWRST 0
31
+
#define MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST 1
32
+
#define MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST 2
29
33
30
34
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */
+34
-2
include/linux/clk-provider.h
+34
-2
include/linux/clk-provider.h
···
832
832
NULL, (flags), (reg), (shift), (width), \
833
833
(clk_divider_flags), NULL, (lock))
834
834
/**
835
+
* devm_clk_hw_register_divider_parent_hw - register a divider clock with the clock framework
836
+
* @dev: device registering this clock
837
+
* @name: name of this clock
838
+
* @parent_hw: pointer to parent clk
839
+
* @flags: framework-specific flags
840
+
* @reg: register address to adjust divider
841
+
* @shift: number of bits to shift the bitfield
842
+
* @width: width of the bitfield
843
+
* @clk_divider_flags: divider-specific flags for this clock
844
+
* @lock: shared register lock for this clock
845
+
*/
846
+
#define devm_clk_hw_register_divider_parent_hw(dev, name, parent_hw, flags, \
847
+
reg, shift, width, \
848
+
clk_divider_flags, lock) \
849
+
__devm_clk_hw_register_divider((dev), NULL, (name), NULL, \
850
+
(parent_hw), NULL, (flags), (reg), \
851
+
(shift), (width), (clk_divider_flags), \
852
+
NULL, (lock))
853
+
/**
835
854
* devm_clk_hw_register_divider_table - register a table based divider clock
836
855
* with the clock framework (devres variant)
837
856
* @dev: device registering this clock
···
980
961
(parent_names), NULL, NULL, (flags), (reg), \
981
962
(shift), BIT((width)) - 1, (clk_mux_flags), \
982
963
NULL, (lock))
964
+
#define devm_clk_hw_register_mux_parent_hws(dev, name, parent_hws, \
965
+
num_parents, flags, reg, shift, \
966
+
width, clk_mux_flags, lock) \
967
+
__devm_clk_hw_register_mux((dev), NULL, (name), (num_parents), NULL, \
968
+
(parent_hws), NULL, (flags), (reg), \
969
+
(shift), BIT((width)) - 1, \
970
+
(clk_mux_flags), NULL, (lock))
983
971
984
972
int clk_mux_val_to_index(struct clk_hw *hw, const u32 *table, unsigned int flags,
985
973
unsigned int val);
···
1032
1006
struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev,
1033
1007
const char *name, unsigned int index, unsigned long flags,
1034
1008
unsigned int mult, unsigned int div);
1009
+
1010
+
struct clk_hw *devm_clk_hw_register_fixed_factor_parent_hw(struct device *dev,
1011
+
const char *name, const struct clk_hw *parent_hw,
1012
+
unsigned long flags, unsigned int mult, unsigned int div);
1013
+
1014
+
struct clk_hw *clk_hw_register_fixed_factor_parent_hw(struct device *dev,
1015
+
const char *name, const struct clk_hw *parent_hw,
1016
+
unsigned long flags, unsigned int mult, unsigned int div);
1035
1017
/**
1036
1018
* struct clk_fractional_divider - adjustable fractional divider clock
1037
1019
*
···
1210
1176
int __must_check of_clk_hw_register(struct device_node *node, struct clk_hw *hw);
1211
1177
1212
1178
void clk_unregister(struct clk *clk);
1213
-
void devm_clk_unregister(struct device *dev, struct clk *clk);
1214
1179
1215
1180
void clk_hw_unregister(struct clk_hw *hw);
1216
-
void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw);
1217
1181
1218
1182
/* helper functions */
1219
1183
const char *__clk_get_name(const struct clk *clk);
+128
-6
include/linux/clk.h
+128
-6
include/linux/clk.h
···
443
443
* @dev: device for clock "consumer"
444
444
* @id: clock consumer ID
445
445
*
446
-
* Returns a struct clk corresponding to the clock producer, or
446
+
* Context: May sleep.
447
+
*
448
+
* Return: a struct clk corresponding to the clock producer, or
447
449
* valid IS_ERR() condition containing errno. The implementation
448
450
* uses @dev and @id to determine the clock consumer, and thereby
449
451
* the clock producer. (IOW, @id may be identical strings, but
450
452
* clk_get may return different clock producers depending on @dev.)
451
453
*
452
-
* Drivers must assume that the clock source is not enabled.
453
-
*
454
-
* devm_clk_get should not be called from within interrupt context.
454
+
* Drivers must assume that the clock source is neither prepared nor
455
+
* enabled.
455
456
*
456
457
* The clock will automatically be freed when the device is unbound
457
458
* from the bus.
···
460
459
struct clk *devm_clk_get(struct device *dev, const char *id);
461
460
462
461
/**
462
+
* devm_clk_get_prepared - devm_clk_get() + clk_prepare()
463
+
* @dev: device for clock "consumer"
464
+
* @id: clock consumer ID
465
+
*
466
+
* Context: May sleep.
467
+
*
468
+
* Return: a struct clk corresponding to the clock producer, or
469
+
* valid IS_ERR() condition containing errno. The implementation
470
+
* uses @dev and @id to determine the clock consumer, and thereby
471
+
* the clock producer. (IOW, @id may be identical strings, but
472
+
* clk_get may return different clock producers depending on @dev.)
473
+
*
474
+
* The returned clk (if valid) is prepared. Drivers must however assume
475
+
* that the clock is not enabled.
476
+
*
477
+
* The clock will automatically be unprepared and freed when the device
478
+
* is unbound from the bus.
479
+
*/
480
+
struct clk *devm_clk_get_prepared(struct device *dev, const char *id);
481
+
482
+
/**
483
+
* devm_clk_get_enabled - devm_clk_get() + clk_prepare_enable()
484
+
* @dev: device for clock "consumer"
485
+
* @id: clock consumer ID
486
+
*
487
+
* Context: May sleep.
488
+
*
489
+
* Return: a struct clk corresponding to the clock producer, or
490
+
* valid IS_ERR() condition containing errno. The implementation
491
+
* uses @dev and @id to determine the clock consumer, and thereby
492
+
* the clock producer. (IOW, @id may be identical strings, but
493
+
* clk_get may return different clock producers depending on @dev.)
494
+
*
495
+
* The returned clk (if valid) is prepared and enabled.
496
+
*
497
+
* The clock will automatically be disabled, unprepared and freed
498
+
* when the device is unbound from the bus.
499
+
*/
500
+
struct clk *devm_clk_get_enabled(struct device *dev, const char *id);
501
+
502
+
/**
463
503
* devm_clk_get_optional - lookup and obtain a managed reference to an optional
464
504
* clock producer.
465
505
* @dev: device for clock "consumer"
466
506
* @id: clock consumer ID
467
507
*
468
-
* Behaves the same as devm_clk_get() except where there is no clock producer.
469
-
* In this case, instead of returning -ENOENT, the function returns NULL.
508
+
* Context: May sleep.
509
+
*
510
+
* Return: a struct clk corresponding to the clock producer, or
511
+
* valid IS_ERR() condition containing errno. The implementation
512
+
* uses @dev and @id to determine the clock consumer, and thereby
513
+
* the clock producer. If no such clk is found, it returns NULL
514
+
* which serves as a dummy clk. That's the only difference compared
515
+
* to devm_clk_get().
516
+
*
517
+
* Drivers must assume that the clock source is neither prepared nor
518
+
* enabled.
519
+
*
520
+
* The clock will automatically be freed when the device is unbound
521
+
* from the bus.
470
522
*/
471
523
struct clk *devm_clk_get_optional(struct device *dev, const char *id);
524
+
525
+
/**
526
+
* devm_clk_get_optional_prepared - devm_clk_get_optional() + clk_prepare()
527
+
* @dev: device for clock "consumer"
528
+
* @id: clock consumer ID
529
+
*
530
+
* Context: May sleep.
531
+
*
532
+
* Return: a struct clk corresponding to the clock producer, or
533
+
* valid IS_ERR() condition containing errno. The implementation
534
+
* uses @dev and @id to determine the clock consumer, and thereby
535
+
* the clock producer. If no such clk is found, it returns NULL
536
+
* which serves as a dummy clk. That's the only difference compared
537
+
* to devm_clk_get_prepared().
538
+
*
539
+
* The returned clk (if valid) is prepared. Drivers must however
540
+
* assume that the clock is not enabled.
541
+
*
542
+
* The clock will automatically be unprepared and freed when the
543
+
* device is unbound from the bus.
544
+
*/
545
+
struct clk *devm_clk_get_optional_prepared(struct device *dev, const char *id);
546
+
547
+
/**
548
+
* devm_clk_get_optional_enabled - devm_clk_get_optional() +
549
+
* clk_prepare_enable()
550
+
* @dev: device for clock "consumer"
551
+
* @id: clock consumer ID
552
+
*
553
+
* Context: May sleep.
554
+
*
555
+
* Return: a struct clk corresponding to the clock producer, or
556
+
* valid IS_ERR() condition containing errno. The implementation
557
+
* uses @dev and @id to determine the clock consumer, and thereby
558
+
* the clock producer. If no such clk is found, it returns NULL
559
+
* which serves as a dummy clk. That's the only difference compared
560
+
* to devm_clk_get_enabled().
561
+
*
562
+
* The returned clk (if valid) is prepared and enabled.
563
+
*
564
+
* The clock will automatically be disabled, unprepared and freed
565
+
* when the device is unbound from the bus.
566
+
*/
567
+
struct clk *devm_clk_get_optional_enabled(struct device *dev, const char *id);
472
568
473
569
/**
474
570
* devm_get_clk_from_child - lookup and obtain a managed reference to a
···
911
813
return NULL;
912
814
}
913
815
816
+
static inline struct clk *devm_clk_get_prepared(struct device *dev,
817
+
const char *id)
818
+
{
819
+
return NULL;
820
+
}
821
+
822
+
static inline struct clk *devm_clk_get_enabled(struct device *dev,
823
+
const char *id)
824
+
{
825
+
return NULL;
826
+
}
827
+
914
828
static inline struct clk *devm_clk_get_optional(struct device *dev,
915
829
const char *id)
830
+
{
831
+
return NULL;
832
+
}
833
+
834
+
static inline struct clk *devm_clk_get_optional_prepared(struct device *dev,
835
+
const char *id)
836
+
{
837
+
return NULL;
838
+
}
839
+
840
+
static inline struct clk *devm_clk_get_optional_enabled(struct device *dev,
841
+
const char *id)
916
842
{
917
843
return NULL;
918
844
}