Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'gpio-updates-for-v6.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux
Pull gpio updates from Bartosz Golaszewski:
"Here are the updates for this merge window from the GPIO subsystem.
We have more lines removed than added thanks to dropping of a driver
for a platform that's no longer supported. Otherwise the changes are
pretty straightforward: support for some new models, various
improvements to existing drivers, some tweaks to the core library code
and DT bindings updates.
Summary:
- remove gpio-vr41xx driver as the only platform using it got dropped
too
- add support for suspend/resume to gpio-davinci
- improvements to the GPIO character device code
- add support for disabling bias for in-kernel users (up until now
only user-space could set it)
- drop unused devm_gpio_free()
- fix a refcount issue in gpiolib OF
- use device match helpers where applicable
- add support for a new model to gpio-rockchip
- non-functional improvements in gpio-adp5588
- improve and simplify teardown in gpio-twl4030 and gpio-ucb1400
- modernize the gpio-74xx-mmio and gpio-adnp drivers
- coding style improvements in gpio-xilinx, gpio-104-idi-48
- support new model (pca9571) in gpio-pca9570
- convert the DT bindings to YAML for gpio-mvebu and update the
document
- don't return error codes from remove() in gpio-brcmstb
- add a library for the intel 8255 PPI interface and use it in
drivers
- reduce using magic numbers and improve code readability in several
drivers
- convert DT bindings to YAML for gpio-tpic2810
- add new models to DT bindings for gpio-frl-imx
- Kconfig improvements
- other minor tweaks and improvements"
* tag 'gpio-updates-for-v6.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux: (52 commits)
dt-bindings: gpio: fsl-imx-gpio: Add i.MXRT compatibles
gpio: 74xx-mmio: Use bits instead of plain numbers for flags
gpio: xilinx: add missing blank line after declarations
MAINTAINERS: Update Intel 8255 GPIO driver file list
gpio: gpio-mm: Implement and utilize register structures
gpio: 104-idi-48: Implement and utilize register structures
gpio: 104-dio-48e: Implement and utilize register structures
gpio: i8255: Introduce the Intel 8255 interface library module
gpio: 104-idio-16: Implement and utilize register structures
gpio: ws16c48: Implement and utilize register structures
gpio: remove VR41XX related gpio driver
dt-bindings: gpio: add pull-disable flag
gpiolib: acpi: support bias pull disable
gpiolib: of: support bias pull disable
gpiolib: add support for bias pull disable
gpio: 74xx-mmio: use bits.h macros for all masks
gpio: 74xx-mmio: Check MMIO_74XX_DIR_IN flag in mmio_74xx_dir_in()
gpio: 74xx-mmio: Make use of device properties
gpiolib: cdev: compile out HTE unless CONFIG_HTE selected
gpiolib: cdev: consolidate edge detector configuration flags
...
+1197
-1452
+1
-1
Documentation/devicetree/bindings/arm/marvell/ap80x-system-controller.txt
+1
-1
Documentation/devicetree/bindings/arm/marvell/ap80x-system-controller.txt
+1
-1
Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt
+1
-1
Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt
+2
Documentation/devicetree/bindings/gpio/fsl-imx-gpio.yaml
+2
Documentation/devicetree/bindings/gpio/fsl-imx-gpio.yaml
-93
Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
-93
Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
···
1
-
* Marvell EBU GPIO controller
2
-
3
-
Required properties:
4
-
5
-
- compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio",
6
-
"marvell,armadaxp-gpio" or "marvell,armada-8k-gpio".
7
-
8
-
"marvell,orion-gpio" should be used for Orion, Kirkwood, Dove,
9
-
Discovery (except MV78200) and Armada 370. "marvell,mv78200-gpio"
10
-
should be used for the Discovery MV78200.
11
-
12
-
"marvel,armadaxp-gpio" should be used for all Armada XP SoCs
13
-
(MV78230, MV78260, MV78460).
14
-
15
-
"marvell,armada-8k-gpio" should be used for the Armada 7K and 8K
16
-
SoCs (either from AP or CP), see
17
-
Documentation/devicetree/bindings/arm/marvell/ap80x-system-controller.txt
18
-
for specific details about the offset property.
19
-
20
-
- reg: Address and length of the register set for the device. Only one
21
-
entry is expected, except for the "marvell,armadaxp-gpio" variant
22
-
for which two entries are expected: one for the general registers,
23
-
one for the per-cpu registers. Not used for marvell,armada-8k-gpio.
24
-
25
-
- interrupts: The list of interrupts that are used for all the pins
26
-
managed by this GPIO bank. There can be more than one interrupt
27
-
(example: 1 interrupt per 8 pins on Armada XP, which means 4
28
-
interrupts per bank of 32 GPIOs).
29
-
30
-
- interrupt-controller: identifies the node as an interrupt controller
31
-
32
-
- #interrupt-cells: specifies the number of cells needed to encode an
33
-
interrupt source. Should be two.
34
-
The first cell is the GPIO number.
35
-
The second cell is used to specify flags:
36
-
bits[3:0] trigger type and level flags:
37
-
1 = low-to-high edge triggered.
38
-
2 = high-to-low edge triggered.
39
-
4 = active high level-sensitive.
40
-
8 = active low level-sensitive.
41
-
42
-
- gpio-controller: marks the device node as a gpio controller
43
-
44
-
- ngpios: number of GPIOs this controller has
45
-
46
-
- #gpio-cells: Should be two. The first cell is the pin number. The
47
-
second cell is reserved for flags, unused at the moment.
48
-
49
-
Optional properties:
50
-
51
-
In order to use the GPIO lines in PWM mode, some additional optional
52
-
properties are required.
53
-
54
-
- compatible: Must contain "marvell,armada-370-gpio"
55
-
56
-
- reg: an additional register set is needed, for the GPIO Blink
57
-
Counter on/off registers.
58
-
59
-
- reg-names: Must contain an entry "pwm" corresponding to the
60
-
additional register range needed for PWM operation.
61
-
62
-
- #pwm-cells: Should be two. The first cell is the GPIO line number. The
63
-
second cell is the period in nanoseconds.
64
-
65
-
- clocks: Must be a phandle to the clock for the GPIO controller.
66
-
67
-
Example:
68
-
69
-
gpio0: gpio@d0018100 {
70
-
compatible = "marvell,armadaxp-gpio";
71
-
reg = <0xd0018100 0x40>,
72
-
<0xd0018800 0x30>;
73
-
ngpios = <32>;
74
-
gpio-controller;
75
-
#gpio-cells = <2>;
76
-
interrupt-controller;
77
-
#interrupt-cells = <2>;
78
-
interrupts = <16>, <17>, <18>, <19>;
79
-
};
80
-
81
-
gpio1: gpio@18140 {
82
-
compatible = "marvell,armada-370-gpio";
83
-
reg = <0x18140 0x40>, <0x181c8 0x08>;
84
-
reg-names = "gpio", "pwm";
85
-
ngpios = <17>;
86
-
gpio-controller;
87
-
#gpio-cells = <2>;
88
-
#pwm-cells = <2>;
89
-
interrupt-controller;
90
-
#interrupt-cells = <2>;
91
-
interrupts = <87>, <88>, <89>;
92
-
clocks = <&coreclk 0>;
93
-
};
+146
Documentation/devicetree/bindings/gpio/gpio-mvebu.yaml
+146
Documentation/devicetree/bindings/gpio/gpio-mvebu.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/gpio/gpio-mvebu.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Marvell EBU GPIO controller
8
+
9
+
maintainers:
10
+
- Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11
+
- Andrew Lunn <andrew@lunn.ch>
12
+
13
+
properties:
14
+
compatible:
15
+
oneOf:
16
+
- enum:
17
+
- marvell,armada-8k-gpio
18
+
- marvell,orion-gpio
19
+
20
+
- items:
21
+
- enum:
22
+
- marvell,mv78200-gpio
23
+
- marvell,armada-370-gpio
24
+
- const: marvell,orion-gpio
25
+
26
+
- description: Deprecated binding
27
+
items:
28
+
- const: marvell,armadaxp-gpio
29
+
- const: marvell,orion-gpio
30
+
deprecated: true
31
+
32
+
reg:
33
+
description: |
34
+
Address and length of the register set for the device. Not used for
35
+
marvell,armada-8k-gpio.
36
+
37
+
A second entry can be provided, for the PWM function using the GPIO Blink
38
+
Counter on/off registers.
39
+
minItems: 1
40
+
maxItems: 2
41
+
42
+
reg-names:
43
+
items:
44
+
- const: gpio
45
+
- const: pwm
46
+
minItems: 1
47
+
48
+
offset:
49
+
$ref: /schemas/types.yaml#/definitions/uint32
50
+
description: Offset in the register map for the gpio registers (in bytes)
51
+
52
+
interrupts:
53
+
description: |
54
+
The list of interrupts that are used for all the pins managed by this
55
+
GPIO bank. There can be more than one interrupt (example: 1 interrupt
56
+
per 8 pins on Armada XP, which means 4 interrupts per bank of 32
57
+
GPIOs).
58
+
minItems: 1
59
+
maxItems: 4
60
+
61
+
interrupt-controller: true
62
+
63
+
"#interrupt-cells":
64
+
const: 2
65
+
66
+
gpio-controller: true
67
+
68
+
ngpios:
69
+
minimum: 1
70
+
maximum: 32
71
+
72
+
"#gpio-cells":
73
+
const: 2
74
+
75
+
marvell,pwm-offset:
76
+
$ref: /schemas/types.yaml#/definitions/uint32
77
+
description: Offset in the register map for the pwm registers (in bytes)
78
+
79
+
"#pwm-cells":
80
+
description:
81
+
The first cell is the GPIO line number. The second cell is the period
82
+
in nanoseconds.
83
+
const: 2
84
+
85
+
clocks:
86
+
description:
87
+
Clock(s) used for PWM function.
88
+
items:
89
+
- description: Core clock
90
+
- description: AXI bus clock
91
+
minItems: 1
92
+
93
+
clock-names:
94
+
items:
95
+
- const: core
96
+
- const: axi
97
+
minItems: 1
98
+
99
+
required:
100
+
- compatible
101
+
- gpio-controller
102
+
- ngpios
103
+
- "#gpio-cells"
104
+
105
+
allOf:
106
+
- if:
107
+
properties:
108
+
compatible:
109
+
contains:
110
+
const: marvell,armada-8k-gpio
111
+
then:
112
+
required:
113
+
- offset
114
+
else:
115
+
required:
116
+
- reg
117
+
118
+
unevaluatedProperties: true
119
+
120
+
examples:
121
+
- |
122
+
gpio@d0018100 {
123
+
compatible = "marvell,armadaxp-gpio", "marvell,orion-gpio";
124
+
reg = <0xd0018100 0x40>, <0xd0018800 0x30>;
125
+
ngpios = <32>;
126
+
gpio-controller;
127
+
#gpio-cells = <2>;
128
+
interrupt-controller;
129
+
#interrupt-cells = <2>;
130
+
interrupts = <16>, <17>, <18>, <19>;
131
+
};
132
+
133
+
- |
134
+
gpio@18140 {
135
+
compatible = "marvell,armada-370-gpio", "marvell,orion-gpio";
136
+
reg = <0x18140 0x40>, <0x181c8 0x08>;
137
+
reg-names = "gpio", "pwm";
138
+
ngpios = <17>;
139
+
gpio-controller;
140
+
#gpio-cells = <2>;
141
+
#pwm-cells = <2>;
142
+
interrupt-controller;
143
+
#interrupt-cells = <2>;
144
+
interrupts = <87>, <88>, <89>;
145
+
clocks = <&coreclk 0>;
146
+
};
+1
Documentation/devicetree/bindings/gpio/gpio-pca9570.yaml
+1
Documentation/devicetree/bindings/gpio/gpio-pca9570.yaml
-16
Documentation/devicetree/bindings/gpio/gpio-tpic2810.txt
-16
Documentation/devicetree/bindings/gpio/gpio-tpic2810.txt
···
1
-
TPIC2810 GPIO controller bindings
2
-
3
-
Required properties:
4
-
- compatible : Should be "ti,tpic2810".
5
-
- reg : The I2C address of the device
6
-
- gpio-controller : Marks the device node as a GPIO controller.
7
-
- #gpio-cells : Should be two. For consumer use see gpio.txt.
8
-
9
-
Example:
10
-
11
-
gpio@60 {
12
-
compatible = "ti,tpic2810";
13
-
reg = <0x60>;
14
-
gpio-controller;
15
-
#gpio-cells = <2>;
16
-
};
+51
Documentation/devicetree/bindings/gpio/gpio-tpic2810.yaml
+51
Documentation/devicetree/bindings/gpio/gpio-tpic2810.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/gpio/gpio-tpic2810.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: TPIC2810 GPIO controller bindings
8
+
9
+
maintainers:
10
+
- Aswath Govindraju <a-govindraju@ti.com>
11
+
12
+
properties:
13
+
compatible:
14
+
enum:
15
+
- ti,tpic2810
16
+
17
+
reg:
18
+
maxItems: 1
19
+
20
+
gpio-controller: true
21
+
22
+
"#gpio-cells":
23
+
const: 2
24
+
25
+
gpio-line-names:
26
+
minItems: 1
27
+
maxItems: 32
28
+
29
+
required:
30
+
- compatible
31
+
- reg
32
+
- gpio-controller
33
+
- "#gpio-cells"
34
+
35
+
additionalProperties: false
36
+
37
+
examples:
38
+
- |
39
+
#include <dt-bindings/gpio/gpio.h>
40
+
41
+
i2c {
42
+
#address-cells = <1>;
43
+
#size-cells = <0>;
44
+
gpio@60 {
45
+
compatible = "ti,tpic2810";
46
+
reg = <0x60>;
47
+
gpio-controller;
48
+
#gpio-cells = <2>;
49
+
gpio-line-names = "LED A", "LED B", "LED C";
50
+
};
51
+
};
+1
-3
Documentation/devicetree/bindings/gpio/renesas,rcar-gpio.yaml
+1
-3
Documentation/devicetree/bindings/gpio/renesas,rcar-gpio.yaml
···
49
49
- const: renesas,rcar-gen3-gpio # R-Car Gen3 or RZ/G2
50
50
51
51
- items:
52
-
- const: renesas,gpio-r8a779a0 # R-Car V3U
53
-
54
-
- items:
55
52
- enum:
53
+
- renesas,gpio-r8a779a0 # R-Car V3U
56
54
- renesas,gpio-r8a779f0 # R-Car S4-8
57
55
- const: renesas,rcar-gen4-gpio # R-Car Gen4
58
56
+2
Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml
+2
Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml
-1
Documentation/driver-api/driver-model/devres.rst
-1
Documentation/driver-api/driver-model/devres.rst
+8
-1
MAINTAINERS
+8
-1
MAINTAINERS
···
10045
10045
S: Maintained
10046
10046
F: drivers/video/fbdev/i810/
10047
10047
10048
+
INTEL 8255 GPIO DRIVER
10049
+
M: William Breathitt Gray <william.gray@linaro.org>
10050
+
L: linux-gpio@vger.kernel.org
10051
+
S: Maintained
10052
+
F: drivers/gpio/gpio-i8255.c
10053
+
F: drivers/gpio/gpio-i8255.h
10054
+
10048
10055
INTEL ASoC DRIVERS
10049
10056
M: Cezary Rojewski <cezary.rojewski@intel.com>
10050
10057
M: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
···
16510
16503
S: Maintained
16511
16504
Q: https://patchwork.ozlabs.org/project/linux-pwm/list/
16512
16505
T: git git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm.git
16513
-
F: Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
16506
+
F: Documentation/devicetree/bindings/gpio/gpio-mvebu.yaml
16514
16507
F: Documentation/devicetree/bindings/pwm/
16515
16508
F: Documentation/driver-api/pwm.rst
16516
16509
F: drivers/gpio/gpio-mvebu.c
+16
-6
drivers/gpio/Kconfig
+16
-6
drivers/gpio/Kconfig
···
544
544
tristate "SAMA5D2 PIOBU GPIO support"
545
545
depends on MFD_SYSCON
546
546
depends on OF_GPIO
547
+
depends on ARCH_AT91 || COMPILE_TEST
547
548
select GPIO_SYSCON
548
549
help
549
550
Say yes here to use the PIOBU pins as GPIOs.
···
691
690
help
692
691
Say yes here to support GPIO on Tohisba Visconti.
693
692
694
-
config GPIO_VR41XX
695
-
tristate "NEC VR4100 series General-purpose I/O Unit support"
696
-
depends on CPU_VR41XX
697
-
help
698
-
Say yes here to support the NEC VR4100 series General-purpose I/O Unit.
699
-
700
693
config GPIO_VX855
701
694
tristate "VIA VX855/VX875 GPIO"
702
695
depends on (X86 || COMPILE_TEST) && PCI
···
824
829
menu "Port-mapped I/O GPIO drivers"
825
830
depends on X86 # Unconditional I/O space access
826
831
832
+
config GPIO_I8255
833
+
tristate
834
+
help
835
+
Enables support for the i8255 interface library functions. The i8255
836
+
interface library provides functions to facilitate communication with
837
+
interfaces compatible with the venerable Intel 8255 Programmable
838
+
Peripheral Interface (PPI). The Intel 8255 PPI chip was first released
839
+
in the early 1970s but compatible interfaces are nowadays typically
840
+
found embedded in larger VLSI processing chips and FPGA components.
841
+
842
+
If built as a module its name will be gpio-i8255.
843
+
827
844
config GPIO_104_DIO_48E
828
845
tristate "ACCES 104-DIO-48E GPIO support"
829
846
depends on PC104
830
847
select ISA_BUS_API
831
848
select GPIOLIB_IRQCHIP
849
+
select GPIO_I8255
832
850
help
833
851
Enables GPIO support for the ACCES 104-DIO-48E series (104-DIO-48E,
834
852
104-DIO-24E). The base port addresses for the devices may be
···
865
857
depends on PC104
866
858
select ISA_BUS_API
867
859
select GPIOLIB_IRQCHIP
860
+
select GPIO_I8255
868
861
help
869
862
Enables GPIO support for the ACCES 104-IDI-48 family (104-IDI-48A,
870
863
104-IDI-48AC, 104-IDI-48B, 104-IDI-48BC). The base port addresses for
···
886
877
tristate "Diamond Systems GPIO-MM GPIO support"
887
878
depends on PC104
888
879
select ISA_BUS_API
880
+
select GPIO_I8255
889
881
help
890
882
Enables GPIO support for the Diamond Systems GPIO-MM and GPIO-MM-12.
891
883
+1
-1
drivers/gpio/Makefile
+1
-1
drivers/gpio/Makefile
···
67
67
obj-$(CONFIG_GPIO_HISI) += gpio-hisi.o
68
68
obj-$(CONFIG_GPIO_HLWD) += gpio-hlwd.o
69
69
obj-$(CONFIG_HTC_EGPIO) += gpio-htc-egpio.o
70
+
obj-$(CONFIG_GPIO_I8255) += gpio-i8255.o
70
71
obj-$(CONFIG_GPIO_ICH) += gpio-ich.o
71
72
obj-$(CONFIG_GPIO_IDT3243X) += gpio-idt3243x.o
72
73
obj-$(CONFIG_GPIO_IOP) += gpio-iop.o
···
170
169
obj-$(CONFIG_GPIO_VIPERBOARD) += gpio-viperboard.o
171
170
obj-$(CONFIG_GPIO_VIRTIO) += gpio-virtio.o
172
171
obj-$(CONFIG_GPIO_VISCONTI) += gpio-visconti.o
173
-
obj-$(CONFIG_GPIO_VR41XX) += gpio-vr41xx.o
174
172
obj-$(CONFIG_GPIO_VX855) += gpio-vx855.o
175
173
obj-$(CONFIG_GPIO_WCD934X) += gpio-wcd934x.o
176
174
obj-$(CONFIG_GPIO_WHISKEY_COVE) += gpio-wcove.o
+74
-175
drivers/gpio/gpio-104-dio-48e.c
+74
-175
drivers/gpio/gpio-104-dio-48e.c
···
6
6
* This driver supports the following ACCES devices: 104-DIO-48E and
7
7
* 104-DIO-24E.
8
8
*/
9
-
#include <linux/bitmap.h>
10
-
#include <linux/bitops.h>
9
+
#include <linux/bits.h>
11
10
#include <linux/device.h>
12
11
#include <linux/errno.h>
13
12
#include <linux/gpio/driver.h>
···
19
20
#include <linux/module.h>
20
21
#include <linux/moduleparam.h>
21
22
#include <linux/spinlock.h>
23
+
#include <linux/types.h>
24
+
25
+
#include "gpio-i8255.h"
26
+
27
+
MODULE_IMPORT_NS(I8255);
22
28
23
29
#define DIO48E_EXTENT 16
24
30
#define MAX_NUM_DIO48E max_num_isa_dev(DIO48E_EXTENT)
···
37
33
module_param_hw_array(irq, uint, irq, NULL, 0);
38
34
MODULE_PARM_DESC(irq, "ACCES 104-DIO-48E interrupt line numbers");
39
35
36
+
#define DIO48E_NUM_PPI 2
37
+
38
+
/**
39
+
* struct dio48e_reg - device register structure
40
+
* @ppi: Programmable Peripheral Interface groups
41
+
* @enable_buffer: Enable/Disable Buffer groups
42
+
* @unused1: Unused
43
+
* @enable_interrupt: Write: Enable Interrupt
44
+
* Read: Disable Interrupt
45
+
* @unused2: Unused
46
+
* @enable_counter: Write: Enable Counter/Timer Addressing
47
+
* Read: Disable Counter/Timer Addressing
48
+
* @unused3: Unused
49
+
* @clear_interrupt: Clear Interrupt
50
+
*/
51
+
struct dio48e_reg {
52
+
struct i8255 ppi[DIO48E_NUM_PPI];
53
+
u8 enable_buffer[DIO48E_NUM_PPI];
54
+
u8 unused1;
55
+
u8 enable_interrupt;
56
+
u8 unused2;
57
+
u8 enable_counter;
58
+
u8 unused3;
59
+
u8 clear_interrupt;
60
+
};
61
+
40
62
/**
41
63
* struct dio48e_gpio - GPIO device private data structure
42
-
* @chip: instance of the gpio_chip
43
-
* @io_state: bit I/O state (whether bit is set to input or output)
44
-
* @out_state: output bits state
45
-
* @control: Control registers state
46
-
* @lock: synchronization lock to prevent I/O race conditions
47
-
* @base: base port address of the GPIO device
48
-
* @irq_mask: I/O bits affected by interrupts
64
+
* @chip: instance of the gpio_chip
65
+
* @ppi_state: PPI device states
66
+
* @lock: synchronization lock to prevent I/O race conditions
67
+
* @reg: I/O address offset for the device registers
68
+
* @irq_mask: I/O bits affected by interrupts
49
69
*/
50
70
struct dio48e_gpio {
51
71
struct gpio_chip chip;
52
-
unsigned char io_state[6];
53
-
unsigned char out_state[6];
54
-
unsigned char control[2];
72
+
struct i8255_state ppi_state[DIO48E_NUM_PPI];
55
73
raw_spinlock_t lock;
56
-
void __iomem *base;
74
+
struct dio48e_reg __iomem *reg;
57
75
unsigned char irq_mask;
58
76
};
59
77
60
78
static int dio48e_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
61
79
{
62
80
struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
63
-
const unsigned int port = offset / 8;
64
-
const unsigned int mask = BIT(offset % 8);
65
81
66
-
if (dio48egpio->io_state[port] & mask)
67
-
return GPIO_LINE_DIRECTION_IN;
82
+
if (i8255_get_direction(dio48egpio->ppi_state, offset))
83
+
return GPIO_LINE_DIRECTION_IN;
68
84
69
85
return GPIO_LINE_DIRECTION_OUT;
70
86
}
···
92
68
static int dio48e_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
93
69
{
94
70
struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
95
-
const unsigned int io_port = offset / 8;
96
-
const unsigned int control_port = io_port / 3;
97
-
void __iomem *const control_addr = dio48egpio->base + 3 + control_port * 4;
98
-
unsigned long flags;
99
-
unsigned int control;
100
71
101
-
raw_spin_lock_irqsave(&dio48egpio->lock, flags);
102
-
103
-
/* Check if configuring Port C */
104
-
if (io_port == 2 || io_port == 5) {
105
-
/* Port C can be configured by nibble */
106
-
if (offset % 8 > 3) {
107
-
dio48egpio->io_state[io_port] |= 0xF0;
108
-
dio48egpio->control[control_port] |= BIT(3);
109
-
} else {
110
-
dio48egpio->io_state[io_port] |= 0x0F;
111
-
dio48egpio->control[control_port] |= BIT(0);
112
-
}
113
-
} else {
114
-
dio48egpio->io_state[io_port] |= 0xFF;
115
-
if (io_port == 0 || io_port == 3)
116
-
dio48egpio->control[control_port] |= BIT(4);
117
-
else
118
-
dio48egpio->control[control_port] |= BIT(1);
119
-
}
120
-
121
-
control = BIT(7) | dio48egpio->control[control_port];
122
-
iowrite8(control, control_addr);
123
-
control &= ~BIT(7);
124
-
iowrite8(control, control_addr);
125
-
126
-
raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
72
+
i8255_direction_input(dio48egpio->reg->ppi, dio48egpio->ppi_state,
73
+
offset);
127
74
128
75
return 0;
129
76
}
···
103
108
int value)
104
109
{
105
110
struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
106
-
const unsigned int io_port = offset / 8;
107
-
const unsigned int control_port = io_port / 3;
108
-
const unsigned int mask = BIT(offset % 8);
109
-
void __iomem *const control_addr = dio48egpio->base + 3 + control_port * 4;
110
-
const unsigned int out_port = (io_port > 2) ? io_port + 1 : io_port;
111
-
unsigned long flags;
112
-
unsigned int control;
113
111
114
-
raw_spin_lock_irqsave(&dio48egpio->lock, flags);
115
-
116
-
/* Check if configuring Port C */
117
-
if (io_port == 2 || io_port == 5) {
118
-
/* Port C can be configured by nibble */
119
-
if (offset % 8 > 3) {
120
-
dio48egpio->io_state[io_port] &= 0x0F;
121
-
dio48egpio->control[control_port] &= ~BIT(3);
122
-
} else {
123
-
dio48egpio->io_state[io_port] &= 0xF0;
124
-
dio48egpio->control[control_port] &= ~BIT(0);
125
-
}
126
-
} else {
127
-
dio48egpio->io_state[io_port] &= 0x00;
128
-
if (io_port == 0 || io_port == 3)
129
-
dio48egpio->control[control_port] &= ~BIT(4);
130
-
else
131
-
dio48egpio->control[control_port] &= ~BIT(1);
132
-
}
133
-
134
-
if (value)
135
-
dio48egpio->out_state[io_port] |= mask;
136
-
else
137
-
dio48egpio->out_state[io_port] &= ~mask;
138
-
139
-
control = BIT(7) | dio48egpio->control[control_port];
140
-
iowrite8(control, control_addr);
141
-
142
-
iowrite8(dio48egpio->out_state[io_port], dio48egpio->base + out_port);
143
-
144
-
control &= ~BIT(7);
145
-
iowrite8(control, control_addr);
146
-
147
-
raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
112
+
i8255_direction_output(dio48egpio->reg->ppi, dio48egpio->ppi_state,
113
+
offset, value);
148
114
149
115
return 0;
150
116
}
···
113
157
static int dio48e_gpio_get(struct gpio_chip *chip, unsigned int offset)
114
158
{
115
159
struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
116
-
const unsigned int port = offset / 8;
117
-
const unsigned int mask = BIT(offset % 8);
118
-
const unsigned int in_port = (port > 2) ? port + 1 : port;
119
-
unsigned long flags;
120
-
unsigned int port_state;
121
160
122
-
raw_spin_lock_irqsave(&dio48egpio->lock, flags);
123
-
124
-
/* ensure that GPIO is set for input */
125
-
if (!(dio48egpio->io_state[port] & mask)) {
126
-
raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
127
-
return -EINVAL;
128
-
}
129
-
130
-
port_state = ioread8(dio48egpio->base + in_port);
131
-
132
-
raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
133
-
134
-
return !!(port_state & mask);
161
+
return i8255_get(dio48egpio->reg->ppi, offset);
135
162
}
136
-
137
-
static const size_t ports[] = { 0, 1, 2, 4, 5, 6 };
138
163
139
164
static int dio48e_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
140
165
unsigned long *bits)
141
166
{
142
167
struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
143
-
unsigned long offset;
144
-
unsigned long gpio_mask;
145
-
void __iomem *port_addr;
146
-
unsigned long port_state;
147
168
148
-
/* clear bits array to a clean slate */
149
-
bitmap_zero(bits, chip->ngpio);
150
-
151
-
for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) {
152
-
port_addr = dio48egpio->base + ports[offset / 8];
153
-
port_state = ioread8(port_addr) & gpio_mask;
154
-
155
-
bitmap_set_value8(bits, port_state, offset);
156
-
}
169
+
i8255_get_multiple(dio48egpio->reg->ppi, mask, bits, chip->ngpio);
157
170
158
171
return 0;
159
172
}
···
130
205
static void dio48e_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
131
206
{
132
207
struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
133
-
const unsigned int port = offset / 8;
134
-
const unsigned int mask = BIT(offset % 8);
135
-
const unsigned int out_port = (port > 2) ? port + 1 : port;
136
-
unsigned long flags;
137
208
138
-
raw_spin_lock_irqsave(&dio48egpio->lock, flags);
139
-
140
-
if (value)
141
-
dio48egpio->out_state[port] |= mask;
142
-
else
143
-
dio48egpio->out_state[port] &= ~mask;
144
-
145
-
iowrite8(dio48egpio->out_state[port], dio48egpio->base + out_port);
146
-
147
-
raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
209
+
i8255_set(dio48egpio->reg->ppi, dio48egpio->ppi_state, offset, value);
148
210
}
149
211
150
212
static void dio48e_gpio_set_multiple(struct gpio_chip *chip,
151
213
unsigned long *mask, unsigned long *bits)
152
214
{
153
215
struct dio48e_gpio *const dio48egpio = gpiochip_get_data(chip);
154
-
unsigned long offset;
155
-
unsigned long gpio_mask;
156
-
size_t index;
157
-
void __iomem *port_addr;
158
-
unsigned long bitmask;
159
-
unsigned long flags;
160
216
161
-
for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) {
162
-
index = offset / 8;
163
-
port_addr = dio48egpio->base + ports[index];
164
-
165
-
bitmask = bitmap_get_value8(bits, offset) & gpio_mask;
166
-
167
-
raw_spin_lock_irqsave(&dio48egpio->lock, flags);
168
-
169
-
/* update output state data and set device gpio register */
170
-
dio48egpio->out_state[index] &= ~gpio_mask;
171
-
dio48egpio->out_state[index] |= bitmask;
172
-
iowrite8(dio48egpio->out_state[index], port_addr);
173
-
174
-
raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
175
-
}
217
+
i8255_set_multiple(dio48egpio->reg->ppi, dio48egpio->ppi_state, mask,
218
+
bits, chip->ngpio);
176
219
}
177
220
178
221
static void dio48e_irq_ack(struct irq_data *data)
···
167
274
168
275
if (!dio48egpio->irq_mask)
169
276
/* disable interrupts */
170
-
ioread8(dio48egpio->base + 0xB);
277
+
ioread8(&dio48egpio->reg->enable_interrupt);
171
278
172
279
raw_spin_unlock_irqrestore(&dio48egpio->lock, flags);
173
280
}
···
187
294
188
295
if (!dio48egpio->irq_mask) {
189
296
/* enable interrupts */
190
-
iowrite8(0x00, dio48egpio->base + 0xF);
191
-
iowrite8(0x00, dio48egpio->base + 0xB);
297
+
iowrite8(0x00, &dio48egpio->reg->clear_interrupt);
298
+
iowrite8(0x00, &dio48egpio->reg->enable_interrupt);
192
299
}
193
300
194
301
if (offset == 19)
···
234
341
235
342
raw_spin_lock(&dio48egpio->lock);
236
343
237
-
iowrite8(0x00, dio48egpio->base + 0xF);
344
+
iowrite8(0x00, &dio48egpio->reg->clear_interrupt);
238
345
239
346
raw_spin_unlock(&dio48egpio->lock);
240
347
···
266
373
struct dio48e_gpio *const dio48egpio = gpiochip_get_data(gc);
267
374
268
375
/* Disable IRQ by default */
269
-
ioread8(dio48egpio->base + 0xB);
376
+
ioread8(&dio48egpio->reg->enable_interrupt);
270
377
271
378
return 0;
379
+
}
380
+
381
+
static void dio48e_init_ppi(struct i8255 __iomem *const ppi,
382
+
struct i8255_state *const ppi_state)
383
+
{
384
+
const unsigned long ngpio = 24;
385
+
const unsigned long mask = GENMASK(ngpio - 1, 0);
386
+
const unsigned long bits = 0;
387
+
unsigned long i;
388
+
389
+
/* Initialize all GPIO to output 0 */
390
+
for (i = 0; i < DIO48E_NUM_PPI; i++) {
391
+
i8255_mode0_output(&ppi[i]);
392
+
i8255_set_multiple(&ppi[i], &ppi_state[i], &mask, &bits, ngpio);
393
+
}
272
394
}
273
395
274
396
static int dio48e_probe(struct device *dev, unsigned int id)
···
303
395
return -EBUSY;
304
396
}
305
397
306
-
dio48egpio->base = devm_ioport_map(dev, base[id], DIO48E_EXTENT);
307
-
if (!dio48egpio->base)
398
+
dio48egpio->reg = devm_ioport_map(dev, base[id], DIO48E_EXTENT);
399
+
if (!dio48egpio->reg)
308
400
return -ENOMEM;
309
401
310
402
dio48egpio->chip.label = name;
···
333
425
334
426
raw_spin_lock_init(&dio48egpio->lock);
335
427
336
-
/* initialize all GPIO as output */
337
-
iowrite8(0x80, dio48egpio->base + 3);
338
-
iowrite8(0x00, dio48egpio->base);
339
-
iowrite8(0x00, dio48egpio->base + 1);
340
-
iowrite8(0x00, dio48egpio->base + 2);
341
-
iowrite8(0x00, dio48egpio->base + 3);
342
-
iowrite8(0x80, dio48egpio->base + 7);
343
-
iowrite8(0x00, dio48egpio->base + 4);
344
-
iowrite8(0x00, dio48egpio->base + 5);
345
-
iowrite8(0x00, dio48egpio->base + 6);
346
-
iowrite8(0x00, dio48egpio->base + 7);
428
+
i8255_state_init(dio48egpio->ppi_state, DIO48E_NUM_PPI);
429
+
dio48e_init_ppi(dio48egpio->reg->ppi, dio48egpio->ppi_state);
347
430
348
431
err = devm_gpiochip_add_data(dev, &dio48egpio->chip, dio48egpio);
349
432
if (err) {
+67
-90
drivers/gpio/gpio-104-idi-48.c
+67
-90
drivers/gpio/gpio-104-idi-48.c
···
6
6
* This driver supports the following ACCES devices: 104-IDI-48A,
7
7
* 104-IDI-48AC, 104-IDI-48B, and 104-IDI-48BC.
8
8
*/
9
-
#include <linux/bitmap.h>
10
-
#include <linux/bitops.h>
9
+
#include <linux/bits.h>
11
10
#include <linux/device.h>
12
11
#include <linux/errno.h>
13
12
#include <linux/gpio/driver.h>
···
19
20
#include <linux/module.h>
20
21
#include <linux/moduleparam.h>
21
22
#include <linux/spinlock.h>
23
+
#include <linux/types.h>
24
+
25
+
#include "gpio-i8255.h"
26
+
27
+
MODULE_IMPORT_NS(I8255);
22
28
23
29
#define IDI_48_EXTENT 8
24
30
#define MAX_NUM_IDI_48 max_num_isa_dev(IDI_48_EXTENT)
···
38
34
MODULE_PARM_DESC(irq, "ACCES 104-IDI-48 interrupt line numbers");
39
35
40
36
/**
37
+
* struct idi_48_reg - device register structure
38
+
* @port0: Port 0 Inputs
39
+
* @unused: Unused
40
+
* @port1: Port 1 Inputs
41
+
* @irq: Read: IRQ Status Register/IRQ Clear
42
+
* Write: IRQ Enable/Disable
43
+
*/
44
+
struct idi_48_reg {
45
+
u8 port0[3];
46
+
u8 unused;
47
+
u8 port1[3];
48
+
u8 irq;
49
+
};
50
+
51
+
/**
41
52
* struct idi_48_gpio - GPIO device private data structure
42
53
* @chip: instance of the gpio_chip
43
54
* @lock: synchronization lock to prevent I/O race conditions
44
-
* @ack_lock: synchronization lock to prevent IRQ handler race conditions
45
55
* @irq_mask: input bits affected by interrupts
46
-
* @base: base port address of the GPIO device
56
+
* @reg: I/O address offset for the device registers
47
57
* @cos_enb: Change-Of-State IRQ enable boundaries mask
48
58
*/
49
59
struct idi_48_gpio {
50
60
struct gpio_chip chip;
51
-
raw_spinlock_t lock;
52
-
spinlock_t ack_lock;
61
+
spinlock_t lock;
53
62
unsigned char irq_mask[6];
54
-
void __iomem *base;
63
+
struct idi_48_reg __iomem *reg;
55
64
unsigned char cos_enb;
56
65
};
57
66
58
-
static int idi_48_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
67
+
static int idi_48_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
59
68
{
60
69
return GPIO_LINE_DIRECTION_IN;
61
70
}
62
71
63
-
static int idi_48_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
72
+
static int idi_48_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
64
73
{
65
74
return 0;
66
75
}
67
76
68
-
static int idi_48_gpio_get(struct gpio_chip *chip, unsigned offset)
77
+
static int idi_48_gpio_get(struct gpio_chip *chip, unsigned int offset)
69
78
{
70
79
struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);
71
-
unsigned i;
72
-
static const unsigned int register_offset[6] = { 0, 1, 2, 4, 5, 6 };
73
-
void __iomem *port_addr;
74
-
unsigned mask;
80
+
void __iomem *const ppi = idi48gpio->reg;
75
81
76
-
for (i = 0; i < 48; i += 8)
77
-
if (offset < i + 8) {
78
-
port_addr = idi48gpio->base + register_offset[i / 8];
79
-
mask = BIT(offset - i);
80
-
81
-
return !!(ioread8(port_addr) & mask);
82
-
}
83
-
84
-
/* The following line should never execute since offset < 48 */
85
-
return 0;
82
+
return i8255_get(ppi, offset);
86
83
}
87
84
88
85
static int idi_48_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
89
86
unsigned long *bits)
90
87
{
91
88
struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);
92
-
unsigned long offset;
93
-
unsigned long gpio_mask;
94
-
static const size_t ports[] = { 0, 1, 2, 4, 5, 6 };
95
-
void __iomem *port_addr;
96
-
unsigned long port_state;
89
+
void __iomem *const ppi = idi48gpio->reg;
97
90
98
-
/* clear bits array to a clean slate */
99
-
bitmap_zero(bits, chip->ngpio);
100
-
101
-
for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) {
102
-
port_addr = idi48gpio->base + ports[offset / 8];
103
-
port_state = ioread8(port_addr) & gpio_mask;
104
-
105
-
bitmap_set_value8(bits, port_state, offset);
106
-
}
91
+
i8255_get_multiple(ppi, mask, bits, chip->ngpio);
107
92
108
93
return 0;
109
94
}
···
105
112
{
106
113
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
107
114
struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);
108
-
const unsigned offset = irqd_to_hwirq(data);
109
-
unsigned i;
110
-
unsigned mask;
111
-
unsigned boundary;
115
+
const unsigned int offset = irqd_to_hwirq(data);
116
+
const unsigned long boundary = offset / 8;
117
+
const unsigned long mask = BIT(offset % 8);
112
118
unsigned long flags;
113
119
114
-
for (i = 0; i < 48; i += 8)
115
-
if (offset < i + 8) {
116
-
mask = BIT(offset - i);
117
-
boundary = i / 8;
120
+
spin_lock_irqsave(&idi48gpio->lock, flags);
118
121
119
-
idi48gpio->irq_mask[boundary] &= ~mask;
122
+
idi48gpio->irq_mask[boundary] &= ~mask;
120
123
121
-
if (!idi48gpio->irq_mask[boundary]) {
122
-
idi48gpio->cos_enb &= ~BIT(boundary);
124
+
/* Exit early if there are still input lines with IRQ unmasked */
125
+
if (idi48gpio->irq_mask[boundary])
126
+
goto exit;
123
127
124
-
raw_spin_lock_irqsave(&idi48gpio->lock, flags);
128
+
idi48gpio->cos_enb &= ~BIT(boundary);
125
129
126
-
iowrite8(idi48gpio->cos_enb, idi48gpio->base + 7);
130
+
iowrite8(idi48gpio->cos_enb, &idi48gpio->reg->irq);
127
131
128
-
raw_spin_unlock_irqrestore(&idi48gpio->lock, flags);
129
-
}
130
-
131
-
return;
132
-
}
132
+
exit:
133
+
spin_unlock_irqrestore(&idi48gpio->lock, flags);
133
134
}
134
135
135
136
static void idi_48_irq_unmask(struct irq_data *data)
136
137
{
137
138
struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
138
139
struct idi_48_gpio *const idi48gpio = gpiochip_get_data(chip);
139
-
const unsigned offset = irqd_to_hwirq(data);
140
-
unsigned i;
141
-
unsigned mask;
142
-
unsigned boundary;
143
-
unsigned prev_irq_mask;
140
+
const unsigned int offset = irqd_to_hwirq(data);
141
+
const unsigned long boundary = offset / 8;
142
+
const unsigned long mask = BIT(offset % 8);
143
+
unsigned int prev_irq_mask;
144
144
unsigned long flags;
145
145
146
-
for (i = 0; i < 48; i += 8)
147
-
if (offset < i + 8) {
148
-
mask = BIT(offset - i);
149
-
boundary = i / 8;
150
-
prev_irq_mask = idi48gpio->irq_mask[boundary];
146
+
spin_lock_irqsave(&idi48gpio->lock, flags);
151
147
152
-
idi48gpio->irq_mask[boundary] |= mask;
148
+
prev_irq_mask = idi48gpio->irq_mask[boundary];
153
149
154
-
if (!prev_irq_mask) {
155
-
idi48gpio->cos_enb |= BIT(boundary);
150
+
idi48gpio->irq_mask[boundary] |= mask;
156
151
157
-
raw_spin_lock_irqsave(&idi48gpio->lock, flags);
152
+
/* Exit early if IRQ was already unmasked for this boundary */
153
+
if (prev_irq_mask)
154
+
goto exit;
158
155
159
-
iowrite8(idi48gpio->cos_enb, idi48gpio->base + 7);
156
+
idi48gpio->cos_enb |= BIT(boundary);
160
157
161
-
raw_spin_unlock_irqrestore(&idi48gpio->lock, flags);
162
-
}
158
+
iowrite8(idi48gpio->cos_enb, &idi48gpio->reg->irq);
163
159
164
-
return;
165
-
}
160
+
exit:
161
+
spin_unlock_irqrestore(&idi48gpio->lock, flags);
166
162
}
167
163
168
-
static int idi_48_irq_set_type(struct irq_data *data, unsigned flow_type)
164
+
static int idi_48_irq_set_type(struct irq_data *data, unsigned int flow_type)
169
165
{
170
166
/* The only valid irq types are none and both-edges */
171
167
if (flow_type != IRQ_TYPE_NONE &&
···
182
200
unsigned long gpio;
183
201
struct gpio_chip *const chip = &idi48gpio->chip;
184
202
185
-
spin_lock(&idi48gpio->ack_lock);
203
+
spin_lock(&idi48gpio->lock);
186
204
187
-
raw_spin_lock(&idi48gpio->lock);
188
-
189
-
cos_status = ioread8(idi48gpio->base + 7);
190
-
191
-
raw_spin_unlock(&idi48gpio->lock);
205
+
cos_status = ioread8(&idi48gpio->reg->irq);
192
206
193
207
/* IRQ Status (bit 6) is active low (0 = IRQ generated by device) */
194
208
if (cos_status & BIT(6)) {
195
-
spin_unlock(&idi48gpio->ack_lock);
209
+
spin_unlock(&idi48gpio->lock);
196
210
return IRQ_NONE;
197
211
}
198
212
···
206
228
}
207
229
}
208
230
209
-
spin_unlock(&idi48gpio->ack_lock);
231
+
spin_unlock(&idi48gpio->lock);
210
232
211
233
return IRQ_HANDLED;
212
234
}
···
228
250
struct idi_48_gpio *const idi48gpio = gpiochip_get_data(gc);
229
251
230
252
/* Disable IRQ by default */
231
-
iowrite8(0, idi48gpio->base + 7);
232
-
ioread8(idi48gpio->base + 7);
253
+
iowrite8(0, &idi48gpio->reg->irq);
254
+
ioread8(&idi48gpio->reg->irq);
233
255
234
256
return 0;
235
257
}
···
251
273
return -EBUSY;
252
274
}
253
275
254
-
idi48gpio->base = devm_ioport_map(dev, base[id], IDI_48_EXTENT);
255
-
if (!idi48gpio->base)
276
+
idi48gpio->reg = devm_ioport_map(dev, base[id], IDI_48_EXTENT);
277
+
if (!idi48gpio->reg)
256
278
return -ENOMEM;
257
279
258
280
idi48gpio->chip.label = name;
···
276
298
girq->handler = handle_edge_irq;
277
299
girq->init_hw = idi_48_irq_init_hw;
278
300
279
-
raw_spin_lock_init(&idi48gpio->lock);
280
-
spin_lock_init(&idi48gpio->ack_lock);
301
+
spin_lock_init(&idi48gpio->lock);
281
302
282
303
err = devm_gpiochip_add_data(dev, &idi48gpio->chip, idi48gpio);
283
304
if (err) {
+42
-18
drivers/gpio/gpio-104-idio-16.c
+42
-18
drivers/gpio/gpio-104-idio-16.c
···
6
6
* This driver supports the following ACCES devices: 104-IDIO-16,
7
7
* 104-IDIO-16E, 104-IDO-16, 104-IDIO-8, 104-IDIO-8E, and 104-IDO-8.
8
8
*/
9
-
#include <linux/bitops.h>
9
+
#include <linux/bits.h>
10
10
#include <linux/device.h>
11
11
#include <linux/errno.h>
12
12
#include <linux/gpio/driver.h>
···
19
19
#include <linux/module.h>
20
20
#include <linux/moduleparam.h>
21
21
#include <linux/spinlock.h>
22
+
#include <linux/types.h>
22
23
23
24
#define IDIO_16_EXTENT 8
24
25
#define MAX_NUM_IDIO_16 max_num_isa_dev(IDIO_16_EXTENT)
···
34
33
MODULE_PARM_DESC(irq, "ACCES 104-IDIO-16 interrupt line numbers");
35
34
36
35
/**
36
+
* struct idio_16_reg - device registers structure
37
+
* @out0_7: Read: N/A
38
+
* Write: FET Drive Outputs 0-7
39
+
* @in0_7: Read: Isolated Inputs 0-7
40
+
* Write: Clear Interrupt
41
+
* @irq_ctl: Read: Enable IRQ
42
+
* Write: Disable IRQ
43
+
* @unused: N/A
44
+
* @out8_15: Read: N/A
45
+
* Write: FET Drive Outputs 8-15
46
+
* @in8_15: Read: Isolated Inputs 8-15
47
+
* Write: N/A
48
+
*/
49
+
struct idio_16_reg {
50
+
u8 out0_7;
51
+
u8 in0_7;
52
+
u8 irq_ctl;
53
+
u8 unused;
54
+
u8 out8_15;
55
+
u8 in8_15;
56
+
};
57
+
58
+
/**
37
59
* struct idio_16_gpio - GPIO device private data structure
38
60
* @chip: instance of the gpio_chip
39
61
* @lock: synchronization lock to prevent I/O race conditions
40
62
* @irq_mask: I/O bits affected by interrupts
41
-
* @base: base port address of the GPIO device
63
+
* @reg: I/O address offset for the device registers
42
64
* @out_state: output bits state
43
65
*/
44
66
struct idio_16_gpio {
45
67
struct gpio_chip chip;
46
68
raw_spinlock_t lock;
47
69
unsigned long irq_mask;
48
-
void __iomem *base;
70
+
struct idio_16_reg __iomem *reg;
49
71
unsigned int out_state;
50
72
};
51
73
···
103
79
return -EINVAL;
104
80
105
81
if (offset < 24)
106
-
return !!(ioread8(idio16gpio->base + 1) & mask);
82
+
return !!(ioread8(&idio16gpio->reg->in0_7) & mask);
107
83
108
-
return !!(ioread8(idio16gpio->base + 5) & (mask>>8));
84
+
return !!(ioread8(&idio16gpio->reg->in8_15) & (mask>>8));
109
85
}
110
86
111
87
static int idio_16_gpio_get_multiple(struct gpio_chip *chip,
···
115
91
116
92
*bits = 0;
117
93
if (*mask & GENMASK(23, 16))
118
-
*bits |= (unsigned long)ioread8(idio16gpio->base + 1) << 16;
94
+
*bits |= (unsigned long)ioread8(&idio16gpio->reg->in0_7) << 16;
119
95
if (*mask & GENMASK(31, 24))
120
-
*bits |= (unsigned long)ioread8(idio16gpio->base + 5) << 24;
96
+
*bits |= (unsigned long)ioread8(&idio16gpio->reg->in8_15) << 24;
121
97
122
98
return 0;
123
99
}
···
140
116
idio16gpio->out_state &= ~mask;
141
117
142
118
if (offset > 7)
143
-
iowrite8(idio16gpio->out_state >> 8, idio16gpio->base + 4);
119
+
iowrite8(idio16gpio->out_state >> 8, &idio16gpio->reg->out8_15);
144
120
else
145
-
iowrite8(idio16gpio->out_state, idio16gpio->base);
121
+
iowrite8(idio16gpio->out_state, &idio16gpio->reg->out0_7);
146
122
147
123
raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
148
124
}
···
159
135
idio16gpio->out_state |= *mask & *bits;
160
136
161
137
if (*mask & 0xFF)
162
-
iowrite8(idio16gpio->out_state, idio16gpio->base);
138
+
iowrite8(idio16gpio->out_state, &idio16gpio->reg->out0_7);
163
139
if ((*mask >> 8) & 0xFF)
164
-
iowrite8(idio16gpio->out_state >> 8, idio16gpio->base + 4);
140
+
iowrite8(idio16gpio->out_state >> 8, &idio16gpio->reg->out8_15);
165
141
166
142
raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
167
143
}
···
182
158
if (!idio16gpio->irq_mask) {
183
159
raw_spin_lock_irqsave(&idio16gpio->lock, flags);
184
160
185
-
iowrite8(0, idio16gpio->base + 2);
161
+
iowrite8(0, &idio16gpio->reg->irq_ctl);
186
162
187
163
raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
188
164
}
···
201
177
if (!prev_irq_mask) {
202
178
raw_spin_lock_irqsave(&idio16gpio->lock, flags);
203
179
204
-
ioread8(idio16gpio->base + 2);
180
+
ioread8(&idio16gpio->reg->irq_ctl);
205
181
206
182
raw_spin_unlock_irqrestore(&idio16gpio->lock, flags);
207
183
}
···
236
212
237
213
raw_spin_lock(&idio16gpio->lock);
238
214
239
-
iowrite8(0, idio16gpio->base + 1);
215
+
iowrite8(0, &idio16gpio->reg->in0_7);
240
216
241
217
raw_spin_unlock(&idio16gpio->lock);
242
218
···
256
232
struct idio_16_gpio *const idio16gpio = gpiochip_get_data(gc);
257
233
258
234
/* Disable IRQ by default */
259
-
iowrite8(0, idio16gpio->base + 2);
260
-
iowrite8(0, idio16gpio->base + 1);
235
+
iowrite8(0, &idio16gpio->reg->irq_ctl);
236
+
iowrite8(0, &idio16gpio->reg->in0_7);
261
237
262
238
return 0;
263
239
}
···
279
255
return -EBUSY;
280
256
}
281
257
282
-
idio16gpio->base = devm_ioport_map(dev, base[id], IDIO_16_EXTENT);
283
-
if (!idio16gpio->base)
258
+
idio16gpio->reg = devm_ioport_map(dev, base[id], IDIO_16_EXTENT);
259
+
if (!idio16gpio->reg)
284
260
return -ENOMEM;
285
261
286
262
idio16gpio->chip.label = name;
+12
-7
drivers/gpio/gpio-74xx-mmio.c
+12
-7
drivers/gpio/gpio-74xx-mmio.c
···
5
5
* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
6
6
*/
7
7
8
+
#include <linux/bits.h>
8
9
#include <linux/err.h>
9
-
#include <linux/module.h>
10
-
#include <linux/of_device.h>
11
10
#include <linux/gpio/driver.h>
11
+
#include <linux/mod_devicetable.h>
12
+
#include <linux/module.h>
12
13
#include <linux/platform_device.h>
14
+
#include <linux/property.h>
13
15
14
-
#define MMIO_74XX_DIR_IN (0 << 8)
15
-
#define MMIO_74XX_DIR_OUT (1 << 8)
16
-
#define MMIO_74XX_BIT_CNT(x) ((x) & 0xff)
16
+
#define MMIO_74XX_DIR_IN BIT(8)
17
+
#define MMIO_74XX_DIR_OUT BIT(9)
18
+
#define MMIO_74XX_BIT_CNT(x) ((x) & GENMASK(7, 0))
17
19
18
20
struct mmio_74xx_gpio_priv {
19
21
struct gpio_chip gc;
···
89
87
{
90
88
struct mmio_74xx_gpio_priv *priv = gpiochip_get_data(gc);
91
89
92
-
return (priv->flags & MMIO_74XX_DIR_OUT) ? -ENOTSUPP : 0;
90
+
if (priv->flags & MMIO_74XX_DIR_IN)
91
+
return 0;
92
+
93
+
return -ENOTSUPP;
93
94
}
94
95
95
96
static int mmio_74xx_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
···
117
112
if (!priv)
118
113
return -ENOMEM;
119
114
120
-
priv->flags = (uintptr_t)of_device_get_match_data(&pdev->dev);
115
+
priv->flags = (uintptr_t)device_get_match_data(&pdev->dev);
121
116
122
117
dat = devm_platform_ioremap_resource(pdev, 0);
123
118
if (IS_ERR(dat))
+7
-12
drivers/gpio/gpio-adnp.c
+7
-12
drivers/gpio/gpio-adnp.c
···
6
6
#include <linux/gpio/driver.h>
7
7
#include <linux/i2c.h>
8
8
#include <linux/interrupt.h>
9
+
#include <linux/mod_devicetable.h>
9
10
#include <linux/module.h>
10
-
#include <linux/of_irq.h>
11
+
#include <linux/property.h>
11
12
#include <linux/seq_file.h>
12
13
#include <linux/slab.h>
13
14
···
486
485
return 0;
487
486
}
488
487
489
-
static int adnp_i2c_probe(struct i2c_client *client,
490
-
const struct i2c_device_id *id)
488
+
static int adnp_i2c_probe(struct i2c_client *client)
491
489
{
492
-
struct device_node *np = client->dev.of_node;
490
+
struct device *dev = &client->dev;
493
491
struct adnp *adnp;
494
492
u32 num_gpios;
495
493
int err;
496
494
497
-
err = of_property_read_u32(np, "nr-gpios", &num_gpios);
495
+
err = device_property_read_u32(dev, "nr-gpios", &num_gpios);
498
496
if (err < 0)
499
497
return err;
500
-
501
-
client->irq = irq_of_parse_and_map(np, 0);
502
-
if (!client->irq)
503
-
return -EPROBE_DEFER;
504
498
505
499
adnp = devm_kzalloc(&client->dev, sizeof(*adnp), GFP_KERNEL);
506
500
if (!adnp)
···
504
508
mutex_init(&adnp->i2c_lock);
505
509
adnp->client = client;
506
510
507
-
err = adnp_gpio_setup(adnp, num_gpios,
508
-
of_property_read_bool(np, "interrupt-controller"));
511
+
err = adnp_gpio_setup(adnp, num_gpios, device_property_read_bool(dev, "interrupt-controller"));
509
512
if (err)
510
513
return err;
511
514
···
530
535
.name = "gpio-adnp",
531
536
.of_match_table = adnp_of_match,
532
537
},
533
-
.probe = adnp_i2c_probe,
538
+
.probe_new = adnp_i2c_probe,
534
539
.id_table = adnp_i2c_id,
535
540
};
536
541
module_i2c_driver(adnp_i2c_driver);
+11
-15
drivers/gpio/gpio-adp5588.c
+11
-15
drivers/gpio/gpio-adp5588.c
···
6
6
* Copyright 2009-2010 Analog Devices Inc.
7
7
*/
8
8
9
-
#include <linux/module.h>
10
-
#include <linux/kernel.h>
11
-
#include <linux/slab.h>
12
-
#include <linux/init.h>
13
-
#include <linux/i2c.h>
14
9
#include <linux/gpio/driver.h>
10
+
#include <linux/i2c.h>
11
+
#include <linux/init.h>
15
12
#include <linux/interrupt.h>
16
13
#include <linux/irq.h>
17
-
#include <linux/of_device.h>
14
+
#include <linux/kernel.h>
15
+
#include <linux/mod_devicetable.h>
16
+
#include <linux/module.h>
17
+
#include <linux/slab.h>
18
18
19
19
#include <linux/platform_data/adp5588.h>
20
-
21
-
#define DRV_NAME "adp5588-gpio"
22
20
23
21
/*
24
22
* Early pre 4.0 Silicon required to delay readout by at least 25ms,
···
420
422
}
421
423
422
424
static const struct i2c_device_id adp5588_gpio_id[] = {
423
-
{DRV_NAME, 0},
425
+
{ "adp5588-gpio" },
424
426
{}
425
427
};
426
428
MODULE_DEVICE_TABLE(i2c, adp5588_gpio_id);
427
429
428
-
#ifdef CONFIG_OF
429
430
static const struct of_device_id adp5588_gpio_of_id[] = {
430
-
{ .compatible = "adi," DRV_NAME, },
431
-
{},
431
+
{ .compatible = "adi,adp5588-gpio" },
432
+
{}
432
433
};
433
434
MODULE_DEVICE_TABLE(of, adp5588_gpio_of_id);
434
-
#endif
435
435
436
436
static struct i2c_driver adp5588_gpio_driver = {
437
437
.driver = {
438
-
.name = DRV_NAME,
439
-
.of_match_table = of_match_ptr(adp5588_gpio_of_id),
438
+
.name = "adp5588-gpio",
439
+
.of_match_table = adp5588_gpio_of_id,
440
440
},
441
441
.probe_new = adp5588_gpio_probe,
442
442
.remove = adp5588_gpio_remove,
+2
-7
drivers/gpio/gpio-brcmstb.c
+2
-7
drivers/gpio/gpio-brcmstb.c
···
375
375
{
376
376
struct brcmstb_gpio_priv *priv = platform_get_drvdata(pdev);
377
377
struct brcmstb_gpio_bank *bank;
378
-
int offset, ret = 0, virq;
379
-
380
-
if (!priv) {
381
-
dev_err(&pdev->dev, "called %s without drvdata!\n", __func__);
382
-
return -EFAULT;
383
-
}
378
+
int offset, virq;
384
379
385
380
if (priv->parent_irq > 0)
386
381
irq_set_chained_handler_and_data(priv->parent_irq, NULL, NULL);
···
396
401
list_for_each_entry(bank, &priv->bank_list, node)
397
402
gpiochip_remove(&bank->gc);
398
403
399
-
return ret;
404
+
return 0;
400
405
}
401
406
402
407
static int brcmstb_gpio_of_xlate(struct gpio_chip *gc,
+83
drivers/gpio/gpio-davinci.c
+83
drivers/gpio/gpio-davinci.c
···
22
22
#include <linux/platform_data/gpio-davinci.h>
23
23
#include <linux/irqchip/chained_irq.h>
24
24
#include <linux/spinlock.h>
25
+
#include <linux/pm_runtime.h>
25
26
26
27
#include <asm-generic/gpio.h>
27
28
···
63
62
void __iomem *regs[MAX_REGS_BANKS];
64
63
int gpio_unbanked;
65
64
int irqs[MAX_INT_PER_BANK];
65
+
struct davinci_gpio_regs context[MAX_REGS_BANKS];
66
+
u32 binten_context;
66
67
};
67
68
68
69
static inline u32 __gpio_mask(unsigned gpio)
···
625
622
return 0;
626
623
}
627
624
625
+
static void davinci_gpio_save_context(struct davinci_gpio_controller *chips,
626
+
u32 nbank)
627
+
{
628
+
struct davinci_gpio_regs __iomem *g;
629
+
struct davinci_gpio_regs *context;
630
+
u32 bank;
631
+
void __iomem *base;
632
+
633
+
base = chips->regs[0] - offset_array[0];
634
+
chips->binten_context = readl_relaxed(base + BINTEN);
635
+
636
+
for (bank = 0; bank < nbank; bank++) {
637
+
g = chips->regs[bank];
638
+
context = &chips->context[bank];
639
+
context->dir = readl_relaxed(&g->dir);
640
+
context->set_data = readl_relaxed(&g->set_data);
641
+
context->set_rising = readl_relaxed(&g->set_rising);
642
+
context->set_falling = readl_relaxed(&g->set_falling);
643
+
}
644
+
645
+
/* Clear Bank interrupt enable bit */
646
+
writel_relaxed(0, base + BINTEN);
647
+
648
+
/* Clear all interrupt status registers */
649
+
writel_relaxed(GENMASK(31, 0), &g->intstat);
650
+
}
651
+
652
+
static void davinci_gpio_restore_context(struct davinci_gpio_controller *chips,
653
+
u32 nbank)
654
+
{
655
+
struct davinci_gpio_regs __iomem *g;
656
+
struct davinci_gpio_regs *context;
657
+
u32 bank;
658
+
void __iomem *base;
659
+
660
+
base = chips->regs[0] - offset_array[0];
661
+
662
+
if (readl_relaxed(base + BINTEN) != chips->binten_context)
663
+
writel_relaxed(chips->binten_context, base + BINTEN);
664
+
665
+
for (bank = 0; bank < nbank; bank++) {
666
+
g = chips->regs[bank];
667
+
context = &chips->context[bank];
668
+
if (readl_relaxed(&g->dir) != context->dir)
669
+
writel_relaxed(context->dir, &g->dir);
670
+
if (readl_relaxed(&g->set_data) != context->set_data)
671
+
writel_relaxed(context->set_data, &g->set_data);
672
+
if (readl_relaxed(&g->set_rising) != context->set_rising)
673
+
writel_relaxed(context->set_rising, &g->set_rising);
674
+
if (readl_relaxed(&g->set_falling) != context->set_falling)
675
+
writel_relaxed(context->set_falling, &g->set_falling);
676
+
}
677
+
}
678
+
679
+
static int davinci_gpio_suspend(struct device *dev)
680
+
{
681
+
struct davinci_gpio_controller *chips = dev_get_drvdata(dev);
682
+
struct davinci_gpio_platform_data *pdata = dev_get_platdata(dev);
683
+
u32 nbank = DIV_ROUND_UP(pdata->ngpio, 32);
684
+
685
+
davinci_gpio_save_context(chips, nbank);
686
+
687
+
return 0;
688
+
}
689
+
690
+
static int davinci_gpio_resume(struct device *dev)
691
+
{
692
+
struct davinci_gpio_controller *chips = dev_get_drvdata(dev);
693
+
struct davinci_gpio_platform_data *pdata = dev_get_platdata(dev);
694
+
u32 nbank = DIV_ROUND_UP(pdata->ngpio, 32);
695
+
696
+
davinci_gpio_restore_context(chips, nbank);
697
+
698
+
return 0;
699
+
}
700
+
701
+
DEFINE_SIMPLE_DEV_PM_OPS(davinci_gpio_dev_pm_ops, davinci_gpio_suspend,
702
+
davinci_gpio_resume);
703
+
628
704
static const struct of_device_id davinci_gpio_ids[] = {
629
705
{ .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
630
706
{ .compatible = "ti,am654-gpio", keystone_gpio_get_irq_chip},
···
716
634
.probe = davinci_gpio_probe,
717
635
.driver = {
718
636
.name = "davinci_gpio",
637
+
.pm = pm_sleep_ptr(&davinci_gpio_dev_pm_ops),
719
638
.of_match_table = of_match_ptr(davinci_gpio_ids),
720
639
},
721
640
};
+39
-163
drivers/gpio/gpio-gpio-mm.c
+39
-163
drivers/gpio/gpio-gpio-mm.c
···
6
6
* This driver supports the following Diamond Systems devices: GPIO-MM and
7
7
* GPIO-MM-12.
8
8
*/
9
-
#include <linux/bitmap.h>
10
-
#include <linux/bitops.h>
11
9
#include <linux/device.h>
12
10
#include <linux/errno.h>
13
11
#include <linux/gpio/driver.h>
···
15
17
#include <linux/kernel.h>
16
18
#include <linux/module.h>
17
19
#include <linux/moduleparam.h>
18
-
#include <linux/spinlock.h>
20
+
21
+
#include "gpio-i8255.h"
22
+
23
+
MODULE_IMPORT_NS(I8255);
19
24
20
25
#define GPIOMM_EXTENT 8
21
26
#define MAX_NUM_GPIOMM max_num_isa_dev(GPIOMM_EXTENT)
···
28
27
module_param_hw_array(base, uint, ioport, &num_gpiomm, 0);
29
28
MODULE_PARM_DESC(base, "Diamond Systems GPIO-MM base addresses");
30
29
30
+
#define GPIOMM_NUM_PPI 2
31
+
31
32
/**
32
33
* struct gpiomm_gpio - GPIO device private data structure
33
-
* @chip: instance of the gpio_chip
34
-
* @io_state: bit I/O state (whether bit is set to input or output)
35
-
* @out_state: output bits state
36
-
* @control: Control registers state
37
-
* @lock: synchronization lock to prevent I/O race conditions
38
-
* @base: base port address of the GPIO device
34
+
* @chip: instance of the gpio_chip
35
+
* @ppi_state: Programmable Peripheral Interface group states
36
+
* @ppi: Programmable Peripheral Interface groups
39
37
*/
40
38
struct gpiomm_gpio {
41
39
struct gpio_chip chip;
42
-
unsigned char io_state[6];
43
-
unsigned char out_state[6];
44
-
unsigned char control[2];
45
-
spinlock_t lock;
46
-
void __iomem *base;
40
+
struct i8255_state ppi_state[GPIOMM_NUM_PPI];
41
+
struct i8255 __iomem *ppi;
47
42
};
48
43
49
44
static int gpiomm_gpio_get_direction(struct gpio_chip *chip,
50
45
unsigned int offset)
51
46
{
52
47
struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
53
-
const unsigned int port = offset / 8;
54
-
const unsigned int mask = BIT(offset % 8);
55
48
56
-
if (gpiommgpio->io_state[port] & mask)
49
+
if (i8255_get_direction(gpiommgpio->ppi_state, offset))
57
50
return GPIO_LINE_DIRECTION_IN;
58
51
59
52
return GPIO_LINE_DIRECTION_OUT;
···
57
62
unsigned int offset)
58
63
{
59
64
struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
60
-
const unsigned int io_port = offset / 8;
61
-
const unsigned int control_port = io_port / 3;
62
-
unsigned long flags;
63
-
unsigned int control;
64
65
65
-
spin_lock_irqsave(&gpiommgpio->lock, flags);
66
-
67
-
/* Check if configuring Port C */
68
-
if (io_port == 2 || io_port == 5) {
69
-
/* Port C can be configured by nibble */
70
-
if (offset % 8 > 3) {
71
-
gpiommgpio->io_state[io_port] |= 0xF0;
72
-
gpiommgpio->control[control_port] |= BIT(3);
73
-
} else {
74
-
gpiommgpio->io_state[io_port] |= 0x0F;
75
-
gpiommgpio->control[control_port] |= BIT(0);
76
-
}
77
-
} else {
78
-
gpiommgpio->io_state[io_port] |= 0xFF;
79
-
if (io_port == 0 || io_port == 3)
80
-
gpiommgpio->control[control_port] |= BIT(4);
81
-
else
82
-
gpiommgpio->control[control_port] |= BIT(1);
83
-
}
84
-
85
-
control = BIT(7) | gpiommgpio->control[control_port];
86
-
iowrite8(control, gpiommgpio->base + 3 + control_port*4);
87
-
88
-
spin_unlock_irqrestore(&gpiommgpio->lock, flags);
66
+
i8255_direction_input(gpiommgpio->ppi, gpiommgpio->ppi_state, offset);
89
67
90
68
return 0;
91
69
}
···
67
99
unsigned int offset, int value)
68
100
{
69
101
struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
70
-
const unsigned int io_port = offset / 8;
71
-
const unsigned int control_port = io_port / 3;
72
-
const unsigned int mask = BIT(offset % 8);
73
-
const unsigned int out_port = (io_port > 2) ? io_port + 1 : io_port;
74
-
unsigned long flags;
75
-
unsigned int control;
76
102
77
-
spin_lock_irqsave(&gpiommgpio->lock, flags);
78
-
79
-
/* Check if configuring Port C */
80
-
if (io_port == 2 || io_port == 5) {
81
-
/* Port C can be configured by nibble */
82
-
if (offset % 8 > 3) {
83
-
gpiommgpio->io_state[io_port] &= 0x0F;
84
-
gpiommgpio->control[control_port] &= ~BIT(3);
85
-
} else {
86
-
gpiommgpio->io_state[io_port] &= 0xF0;
87
-
gpiommgpio->control[control_port] &= ~BIT(0);
88
-
}
89
-
} else {
90
-
gpiommgpio->io_state[io_port] &= 0x00;
91
-
if (io_port == 0 || io_port == 3)
92
-
gpiommgpio->control[control_port] &= ~BIT(4);
93
-
else
94
-
gpiommgpio->control[control_port] &= ~BIT(1);
95
-
}
96
-
97
-
if (value)
98
-
gpiommgpio->out_state[io_port] |= mask;
99
-
else
100
-
gpiommgpio->out_state[io_port] &= ~mask;
101
-
102
-
control = BIT(7) | gpiommgpio->control[control_port];
103
-
iowrite8(control, gpiommgpio->base + 3 + control_port*4);
104
-
105
-
iowrite8(gpiommgpio->out_state[io_port], gpiommgpio->base + out_port);
106
-
107
-
spin_unlock_irqrestore(&gpiommgpio->lock, flags);
103
+
i8255_direction_output(gpiommgpio->ppi, gpiommgpio->ppi_state, offset,
104
+
value);
108
105
109
106
return 0;
110
107
}
···
77
144
static int gpiomm_gpio_get(struct gpio_chip *chip, unsigned int offset)
78
145
{
79
146
struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
80
-
const unsigned int port = offset / 8;
81
-
const unsigned int mask = BIT(offset % 8);
82
-
const unsigned int in_port = (port > 2) ? port + 1 : port;
83
-
unsigned long flags;
84
-
unsigned int port_state;
85
147
86
-
spin_lock_irqsave(&gpiommgpio->lock, flags);
87
-
88
-
/* ensure that GPIO is set for input */
89
-
if (!(gpiommgpio->io_state[port] & mask)) {
90
-
spin_unlock_irqrestore(&gpiommgpio->lock, flags);
91
-
return -EINVAL;
92
-
}
93
-
94
-
port_state = ioread8(gpiommgpio->base + in_port);
95
-
96
-
spin_unlock_irqrestore(&gpiommgpio->lock, flags);
97
-
98
-
return !!(port_state & mask);
148
+
return i8255_get(gpiommgpio->ppi, offset);
99
149
}
100
-
101
-
static const size_t ports[] = { 0, 1, 2, 4, 5, 6 };
102
150
103
151
static int gpiomm_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
104
152
unsigned long *bits)
105
153
{
106
154
struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
107
-
unsigned long offset;
108
-
unsigned long gpio_mask;
109
-
void __iomem *port_addr;
110
-
unsigned long port_state;
111
155
112
-
/* clear bits array to a clean slate */
113
-
bitmap_zero(bits, chip->ngpio);
114
-
115
-
for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) {
116
-
port_addr = gpiommgpio->base + ports[offset / 8];
117
-
port_state = ioread8(port_addr) & gpio_mask;
118
-
119
-
bitmap_set_value8(bits, port_state, offset);
120
-
}
156
+
i8255_get_multiple(gpiommgpio->ppi, mask, bits, chip->ngpio);
121
157
122
158
return 0;
123
159
}
···
95
193
int value)
96
194
{
97
195
struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
98
-
const unsigned int port = offset / 8;
99
-
const unsigned int mask = BIT(offset % 8);
100
-
const unsigned int out_port = (port > 2) ? port + 1 : port;
101
-
unsigned long flags;
102
196
103
-
spin_lock_irqsave(&gpiommgpio->lock, flags);
104
-
105
-
if (value)
106
-
gpiommgpio->out_state[port] |= mask;
107
-
else
108
-
gpiommgpio->out_state[port] &= ~mask;
109
-
110
-
iowrite8(gpiommgpio->out_state[port], gpiommgpio->base + out_port);
111
-
112
-
spin_unlock_irqrestore(&gpiommgpio->lock, flags);
197
+
i8255_set(gpiommgpio->ppi, gpiommgpio->ppi_state, offset, value);
113
198
}
114
199
115
200
static void gpiomm_gpio_set_multiple(struct gpio_chip *chip,
116
201
unsigned long *mask, unsigned long *bits)
117
202
{
118
203
struct gpiomm_gpio *const gpiommgpio = gpiochip_get_data(chip);
119
-
unsigned long offset;
120
-
unsigned long gpio_mask;
121
-
size_t index;
122
-
void __iomem *port_addr;
123
-
unsigned long bitmask;
124
-
unsigned long flags;
125
204
126
-
for_each_set_clump8(offset, gpio_mask, mask, ARRAY_SIZE(ports) * 8) {
127
-
index = offset / 8;
128
-
port_addr = gpiommgpio->base + ports[index];
129
-
130
-
bitmask = bitmap_get_value8(bits, offset) & gpio_mask;
131
-
132
-
spin_lock_irqsave(&gpiommgpio->lock, flags);
133
-
134
-
/* update output state data and set device gpio register */
135
-
gpiommgpio->out_state[index] &= ~gpio_mask;
136
-
gpiommgpio->out_state[index] |= bitmask;
137
-
iowrite8(gpiommgpio->out_state[index], port_addr);
138
-
139
-
spin_unlock_irqrestore(&gpiommgpio->lock, flags);
140
-
}
205
+
i8255_set_multiple(gpiommgpio->ppi, gpiommgpio->ppi_state, mask, bits,
206
+
chip->ngpio);
141
207
}
142
208
143
209
#define GPIOMM_NGPIO 48
···
119
249
"Port 2B4", "Port 2B5", "Port 2B6", "Port 2B7", "Port 2C0", "Port 2C1",
120
250
"Port 2C2", "Port 2C3", "Port 2C4", "Port 2C5", "Port 2C6", "Port 2C7",
121
251
};
252
+
253
+
static void gpiomm_init_dio(struct i8255 __iomem *const ppi,
254
+
struct i8255_state *const ppi_state)
255
+
{
256
+
const unsigned long ngpio = 24;
257
+
const unsigned long mask = GENMASK(ngpio - 1, 0);
258
+
const unsigned long bits = 0;
259
+
unsigned long i;
260
+
261
+
/* Initialize all GPIO to output 0 */
262
+
for (i = 0; i < GPIOMM_NUM_PPI; i++) {
263
+
i8255_mode0_output(&ppi[i]);
264
+
i8255_set_multiple(&ppi[i], &ppi_state[i], &mask, &bits, ngpio);
265
+
}
266
+
}
122
267
123
268
static int gpiomm_probe(struct device *dev, unsigned int id)
124
269
{
···
151
266
return -EBUSY;
152
267
}
153
268
154
-
gpiommgpio->base = devm_ioport_map(dev, base[id], GPIOMM_EXTENT);
155
-
if (!gpiommgpio->base)
269
+
gpiommgpio->ppi = devm_ioport_map(dev, base[id], GPIOMM_EXTENT);
270
+
if (!gpiommgpio->ppi)
156
271
return -ENOMEM;
157
272
158
273
gpiommgpio->chip.label = name;
···
169
284
gpiommgpio->chip.set = gpiomm_gpio_set;
170
285
gpiommgpio->chip.set_multiple = gpiomm_gpio_set_multiple;
171
286
172
-
spin_lock_init(&gpiommgpio->lock);
287
+
i8255_state_init(gpiommgpio->ppi_state, GPIOMM_NUM_PPI);
288
+
gpiomm_init_dio(gpiommgpio->ppi, gpiommgpio->ppi_state);
173
289
174
290
err = devm_gpiochip_add_data(dev, &gpiommgpio->chip, gpiommgpio);
175
291
if (err) {
176
292
dev_err(dev, "GPIO registering failed (%d)\n", err);
177
293
return err;
178
294
}
179
-
180
-
/* initialize all GPIO as output */
181
-
iowrite8(0x80, gpiommgpio->base + 3);
182
-
iowrite8(0x00, gpiommgpio->base);
183
-
iowrite8(0x00, gpiommgpio->base + 1);
184
-
iowrite8(0x00, gpiommgpio->base + 2);
185
-
iowrite8(0x80, gpiommgpio->base + 7);
186
-
iowrite8(0x00, gpiommgpio->base + 4);
187
-
iowrite8(0x00, gpiommgpio->base + 5);
188
-
iowrite8(0x00, gpiommgpio->base + 6);
189
295
190
296
return 0;
191
297
}
+287
drivers/gpio/gpio-i8255.c
+287
drivers/gpio/gpio-i8255.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Intel 8255 Programmable Peripheral Interface
4
+
* Copyright (C) 2022 William Breathitt Gray
5
+
*/
6
+
#include <linux/bitmap.h>
7
+
#include <linux/err.h>
8
+
#include <linux/export.h>
9
+
#include <linux/io.h>
10
+
#include <linux/module.h>
11
+
#include <linux/spinlock.h>
12
+
#include <linux/types.h>
13
+
14
+
#include "gpio-i8255.h"
15
+
16
+
#define I8255_CONTROL_PORTC_LOWER_DIRECTION BIT(0)
17
+
#define I8255_CONTROL_PORTB_DIRECTION BIT(1)
18
+
#define I8255_CONTROL_PORTC_UPPER_DIRECTION BIT(3)
19
+
#define I8255_CONTROL_PORTA_DIRECTION BIT(4)
20
+
#define I8255_CONTROL_MODE_SET BIT(7)
21
+
#define I8255_PORTA 0
22
+
#define I8255_PORTB 1
23
+
#define I8255_PORTC 2
24
+
25
+
static int i8255_get_port(struct i8255 __iomem *const ppi,
26
+
const unsigned long io_port, const unsigned long mask)
27
+
{
28
+
const unsigned long bank = io_port / 3;
29
+
const unsigned long ppi_port = io_port % 3;
30
+
31
+
return ioread8(&ppi[bank].port[ppi_port]) & mask;
32
+
}
33
+
34
+
static u8 i8255_direction_mask(const unsigned long offset)
35
+
{
36
+
const unsigned long port_offset = offset % 8;
37
+
const unsigned long io_port = offset / 8;
38
+
const unsigned long ppi_port = io_port % 3;
39
+
40
+
switch (ppi_port) {
41
+
case I8255_PORTA:
42
+
return I8255_CONTROL_PORTA_DIRECTION;
43
+
case I8255_PORTB:
44
+
return I8255_CONTROL_PORTB_DIRECTION;
45
+
case I8255_PORTC:
46
+
/* Port C can be configured by nibble */
47
+
if (port_offset >= 4)
48
+
return I8255_CONTROL_PORTC_UPPER_DIRECTION;
49
+
return I8255_CONTROL_PORTC_LOWER_DIRECTION;
50
+
default:
51
+
/* Should never reach this path */
52
+
return 0;
53
+
}
54
+
}
55
+
56
+
static void i8255_set_port(struct i8255 __iomem *const ppi,
57
+
struct i8255_state *const state,
58
+
const unsigned long io_port,
59
+
const unsigned long mask, const unsigned long bits)
60
+
{
61
+
const unsigned long bank = io_port / 3;
62
+
const unsigned long ppi_port = io_port % 3;
63
+
unsigned long flags;
64
+
unsigned long out_state;
65
+
66
+
spin_lock_irqsave(&state[bank].lock, flags);
67
+
68
+
out_state = ioread8(&ppi[bank].port[ppi_port]);
69
+
out_state = (out_state & ~mask) | (bits & mask);
70
+
iowrite8(out_state, &ppi[bank].port[ppi_port]);
71
+
72
+
spin_unlock_irqrestore(&state[bank].lock, flags);
73
+
}
74
+
75
+
/**
76
+
* i8255_direction_input - configure signal offset as input
77
+
* @ppi: Intel 8255 Programmable Peripheral Interface banks
78
+
* @state: devices states of the respective PPI banks
79
+
* @offset: signal offset to configure as input
80
+
*
81
+
* Configures a signal @offset as input for the respective Intel 8255
82
+
* Programmable Peripheral Interface (@ppi) banks. The @state control_state
83
+
* values are updated to reflect the new configuration.
84
+
*/
85
+
void i8255_direction_input(struct i8255 __iomem *const ppi,
86
+
struct i8255_state *const state,
87
+
const unsigned long offset)
88
+
{
89
+
const unsigned long io_port = offset / 8;
90
+
const unsigned long bank = io_port / 3;
91
+
unsigned long flags;
92
+
93
+
spin_lock_irqsave(&state[bank].lock, flags);
94
+
95
+
state[bank].control_state |= I8255_CONTROL_MODE_SET;
96
+
state[bank].control_state |= i8255_direction_mask(offset);
97
+
98
+
iowrite8(state[bank].control_state, &ppi[bank].control);
99
+
100
+
spin_unlock_irqrestore(&state[bank].lock, flags);
101
+
}
102
+
EXPORT_SYMBOL_NS_GPL(i8255_direction_input, I8255);
103
+
104
+
/**
105
+
* i8255_direction_output - configure signal offset as output
106
+
* @ppi: Intel 8255 Programmable Peripheral Interface banks
107
+
* @state: devices states of the respective PPI banks
108
+
* @offset: signal offset to configure as output
109
+
* @value: signal value to output
110
+
*
111
+
* Configures a signal @offset as output for the respective Intel 8255
112
+
* Programmable Peripheral Interface (@ppi) banks and sets the respective signal
113
+
* output to the desired @value. The @state control_state values are updated to
114
+
* reflect the new configuration.
115
+
*/
116
+
void i8255_direction_output(struct i8255 __iomem *const ppi,
117
+
struct i8255_state *const state,
118
+
const unsigned long offset,
119
+
const unsigned long value)
120
+
{
121
+
const unsigned long io_port = offset / 8;
122
+
const unsigned long bank = io_port / 3;
123
+
unsigned long flags;
124
+
125
+
spin_lock_irqsave(&state[bank].lock, flags);
126
+
127
+
state[bank].control_state |= I8255_CONTROL_MODE_SET;
128
+
state[bank].control_state &= ~i8255_direction_mask(offset);
129
+
130
+
iowrite8(state[bank].control_state, &ppi[bank].control);
131
+
132
+
spin_unlock_irqrestore(&state[bank].lock, flags);
133
+
134
+
i8255_set(ppi, state, offset, value);
135
+
}
136
+
EXPORT_SYMBOL_NS_GPL(i8255_direction_output, I8255);
137
+
138
+
/**
139
+
* i8255_get - get signal value at signal offset
140
+
* @ppi: Intel 8255 Programmable Peripheral Interface banks
141
+
* @offset: offset of signal to get
142
+
*
143
+
* Returns the signal value (0=low, 1=high) for the signal at @offset for the
144
+
* respective Intel 8255 Programmable Peripheral Interface (@ppi) banks.
145
+
*/
146
+
int i8255_get(struct i8255 __iomem *const ppi, const unsigned long offset)
147
+
{
148
+
const unsigned long io_port = offset / 8;
149
+
const unsigned long offset_mask = BIT(offset % 8);
150
+
151
+
return !!i8255_get_port(ppi, io_port, offset_mask);
152
+
}
153
+
EXPORT_SYMBOL_NS_GPL(i8255_get, I8255);
154
+
155
+
/**
156
+
* i8255_get_direction - get the I/O direction for a signal offset
157
+
* @state: devices states of the respective PPI banks
158
+
* @offset: offset of signal to get direction
159
+
*
160
+
* Returns the signal direction (0=output, 1=input) for the signal at @offset.
161
+
*/
162
+
int i8255_get_direction(const struct i8255_state *const state,
163
+
const unsigned long offset)
164
+
{
165
+
const unsigned long io_port = offset / 8;
166
+
const unsigned long bank = io_port / 3;
167
+
168
+
return !!(state[bank].control_state & i8255_direction_mask(offset));
169
+
}
170
+
EXPORT_SYMBOL_NS_GPL(i8255_get_direction, I8255);
171
+
172
+
/**
173
+
* i8255_get_multiple - get multiple signal values at multiple signal offsets
174
+
* @ppi: Intel 8255 Programmable Peripheral Interface banks
175
+
* @mask: mask of signals to get
176
+
* @bits: bitmap to store signal values
177
+
* @ngpio: number of GPIO signals of the respective PPI banks
178
+
*
179
+
* Stores in @bits the values (0=low, 1=high) for the signals defined by @mask
180
+
* for the respective Intel 8255 Programmable Peripheral Interface (@ppi) banks.
181
+
*/
182
+
void i8255_get_multiple(struct i8255 __iomem *const ppi,
183
+
const unsigned long *const mask,
184
+
unsigned long *const bits, const unsigned long ngpio)
185
+
{
186
+
unsigned long offset;
187
+
unsigned long port_mask;
188
+
unsigned long io_port;
189
+
unsigned long port_state;
190
+
191
+
bitmap_zero(bits, ngpio);
192
+
193
+
for_each_set_clump8(offset, port_mask, mask, ngpio) {
194
+
io_port = offset / 8;
195
+
port_state = i8255_get_port(ppi, io_port, port_mask);
196
+
197
+
bitmap_set_value8(bits, port_state, offset);
198
+
}
199
+
}
200
+
EXPORT_SYMBOL_NS_GPL(i8255_get_multiple, I8255);
201
+
202
+
/**
203
+
* i8255_mode0_output - configure all PPI ports to MODE 0 output mode
204
+
* @ppi: Intel 8255 Programmable Peripheral Interface bank
205
+
*
206
+
* Configures all Intel 8255 Programmable Peripheral Interface (@ppi) ports to
207
+
* MODE 0 (Basic Input/Output) output mode.
208
+
*/
209
+
void i8255_mode0_output(struct i8255 __iomem *const ppi)
210
+
{
211
+
iowrite8(I8255_CONTROL_MODE_SET, &ppi->control);
212
+
}
213
+
EXPORT_SYMBOL_NS_GPL(i8255_mode0_output, I8255);
214
+
215
+
/**
216
+
* i8255_set - set signal value at signal offset
217
+
* @ppi: Intel 8255 Programmable Peripheral Interface banks
218
+
* @state: devices states of the respective PPI banks
219
+
* @offset: offset of signal to set
220
+
* @value: value of signal to set
221
+
*
222
+
* Assigns output @value for the signal at @offset for the respective Intel 8255
223
+
* Programmable Peripheral Interface (@ppi) banks.
224
+
*/
225
+
void i8255_set(struct i8255 __iomem *const ppi, struct i8255_state *const state,
226
+
const unsigned long offset, const unsigned long value)
227
+
{
228
+
const unsigned long io_port = offset / 8;
229
+
const unsigned long port_offset = offset % 8;
230
+
const unsigned long mask = BIT(port_offset);
231
+
const unsigned long bits = value << port_offset;
232
+
233
+
i8255_set_port(ppi, state, io_port, mask, bits);
234
+
}
235
+
EXPORT_SYMBOL_NS_GPL(i8255_set, I8255);
236
+
237
+
/**
238
+
* i8255_set_multiple - set signal values at multiple signal offsets
239
+
* @ppi: Intel 8255 Programmable Peripheral Interface banks
240
+
* @state: devices states of the respective PPI banks
241
+
* @mask: mask of signals to set
242
+
* @bits: bitmap of signal output values
243
+
* @ngpio: number of GPIO signals of the respective PPI banks
244
+
*
245
+
* Assigns output values defined by @bits for the signals defined by @mask for
246
+
* the respective Intel 8255 Programmable Peripheral Interface (@ppi) banks.
247
+
*/
248
+
void i8255_set_multiple(struct i8255 __iomem *const ppi,
249
+
struct i8255_state *const state,
250
+
const unsigned long *const mask,
251
+
const unsigned long *const bits,
252
+
const unsigned long ngpio)
253
+
{
254
+
unsigned long offset;
255
+
unsigned long port_mask;
256
+
unsigned long io_port;
257
+
unsigned long value;
258
+
259
+
for_each_set_clump8(offset, port_mask, mask, ngpio) {
260
+
io_port = offset / 8;
261
+
value = bitmap_get_value8(bits, offset);
262
+
i8255_set_port(ppi, state, io_port, port_mask, value);
263
+
}
264
+
}
265
+
EXPORT_SYMBOL_NS_GPL(i8255_set_multiple, I8255);
266
+
267
+
/**
268
+
* i8255_state_init - initialize i8255_state structure
269
+
* @state: devices states of the respective PPI banks
270
+
* @nbanks: number of Intel 8255 Programmable Peripheral Interface banks
271
+
*
272
+
* Initializes the @state of each Intel 8255 Programmable Peripheral Interface
273
+
* bank for use in i8255 library functions.
274
+
*/
275
+
void i8255_state_init(struct i8255_state *const state,
276
+
const unsigned long nbanks)
277
+
{
278
+
unsigned long bank;
279
+
280
+
for (bank = 0; bank < nbanks; bank++)
281
+
spin_lock_init(&state[bank].lock);
282
+
}
283
+
EXPORT_SYMBOL_NS_GPL(i8255_state_init, I8255);
284
+
285
+
MODULE_AUTHOR("William Breathitt Gray");
286
+
MODULE_DESCRIPTION("Intel 8255 Programmable Peripheral Interface");
287
+
MODULE_LICENSE("GPL");
+46
drivers/gpio/gpio-i8255.h
+46
drivers/gpio/gpio-i8255.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0 */
2
+
/* Copyright 2022 William Breathitt Gray */
3
+
#ifndef _I8255_H_
4
+
#define _I8255_H_
5
+
6
+
#include <linux/spinlock.h>
7
+
#include <linux/types.h>
8
+
9
+
/**
10
+
* struct i8255 - Intel 8255 register structure
11
+
* @port: Port A, B, and C
12
+
* @control: Control register
13
+
*/
14
+
struct i8255 {
15
+
u8 port[3];
16
+
u8 control;
17
+
};
18
+
19
+
/**
20
+
* struct i8255_state - Intel 8255 state structure
21
+
* @lock: synchronization lock for accessing device state
22
+
* @control_state: Control register state
23
+
*/
24
+
struct i8255_state {
25
+
spinlock_t lock;
26
+
u8 control_state;
27
+
};
28
+
29
+
void i8255_direction_input(struct i8255 __iomem *ppi, struct i8255_state *state,
30
+
unsigned long offset);
31
+
void i8255_direction_output(struct i8255 __iomem *ppi,
32
+
struct i8255_state *state, unsigned long offset,
33
+
unsigned long value);
34
+
int i8255_get(struct i8255 __iomem *ppi, unsigned long offset);
35
+
int i8255_get_direction(const struct i8255_state *state, unsigned long offset);
36
+
void i8255_get_multiple(struct i8255 __iomem *ppi, const unsigned long *mask,
37
+
unsigned long *bits, unsigned long ngpio);
38
+
void i8255_mode0_output(struct i8255 __iomem *const ppi);
39
+
void i8255_set(struct i8255 __iomem *ppi, struct i8255_state *state,
40
+
unsigned long offset, unsigned long value);
41
+
void i8255_set_multiple(struct i8255 __iomem *ppi, struct i8255_state *state,
42
+
const unsigned long *mask, const unsigned long *bits,
43
+
unsigned long ngpio);
44
+
void i8255_state_init(struct i8255_state *const state, unsigned long nbanks);
45
+
46
+
#endif /* _I8255_H_ */
+8
-8
drivers/gpio/gpio-lp3943.c
+8
-8
drivers/gpio/gpio-lp3943.c
···
42
42
u16 input_mask; /* 1 = GPIO is input direction, 0 = output */
43
43
};
44
44
45
-
static int lp3943_gpio_request(struct gpio_chip *chip, unsigned offset)
45
+
static int lp3943_gpio_request(struct gpio_chip *chip, unsigned int offset)
46
46
{
47
47
struct lp3943_gpio *lp3943_gpio = gpiochip_get_data(chip);
48
48
struct lp3943 *lp3943 = lp3943_gpio->lp3943;
···
54
54
return 0;
55
55
}
56
56
57
-
static void lp3943_gpio_free(struct gpio_chip *chip, unsigned offset)
57
+
static void lp3943_gpio_free(struct gpio_chip *chip, unsigned int offset)
58
58
{
59
59
struct lp3943_gpio *lp3943_gpio = gpiochip_get_data(chip);
60
60
struct lp3943 *lp3943 = lp3943_gpio->lp3943;
···
72
72
val << mux[offset].shift);
73
73
}
74
74
75
-
static int lp3943_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
75
+
static int lp3943_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
76
76
{
77
77
struct lp3943_gpio *lp3943_gpio = gpiochip_get_data(chip);
78
78
···
82
82
}
83
83
84
84
static int lp3943_get_gpio_in_status(struct lp3943_gpio *lp3943_gpio,
85
-
struct gpio_chip *chip, unsigned offset)
85
+
struct gpio_chip *chip, unsigned int offset)
86
86
{
87
87
u8 addr, read;
88
88
int err;
···
107
107
}
108
108
109
109
static int lp3943_get_gpio_out_status(struct lp3943_gpio *lp3943_gpio,
110
-
struct gpio_chip *chip, unsigned offset)
110
+
struct gpio_chip *chip, unsigned int offset)
111
111
{
112
112
struct lp3943 *lp3943 = lp3943_gpio->lp3943;
113
113
const struct lp3943_reg_cfg *mux = lp3943->mux_cfg;
···
128
128
return -EINVAL;
129
129
}
130
130
131
-
static int lp3943_gpio_get(struct gpio_chip *chip, unsigned offset)
131
+
static int lp3943_gpio_get(struct gpio_chip *chip, unsigned int offset)
132
132
{
133
133
struct lp3943_gpio *lp3943_gpio = gpiochip_get_data(chip);
134
134
···
147
147
return lp3943_get_gpio_out_status(lp3943_gpio, chip, offset);
148
148
}
149
149
150
-
static void lp3943_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
150
+
static void lp3943_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
151
151
{
152
152
struct lp3943_gpio *lp3943_gpio = gpiochip_get_data(chip);
153
153
u8 data;
···
160
160
lp3943_gpio_set_mode(lp3943_gpio, offset, data);
161
161
}
162
162
163
-
static int lp3943_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
163
+
static int lp3943_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
164
164
int value)
165
165
{
166
166
struct lp3943_gpio *lp3943_gpio = gpiochip_get_data(chip);
+2
drivers/gpio/gpio-pca9570.c
+2
drivers/gpio/gpio-pca9570.c
···
121
121
122
122
static const struct i2c_device_id pca9570_id_table[] = {
123
123
{ "pca9570", 4 },
124
+
{ "pca9571", 8 },
124
125
{ /* sentinel */ }
125
126
};
126
127
MODULE_DEVICE_TABLE(i2c, pca9570_id_table);
127
128
128
129
static const struct of_device_id pca9570_of_match_table[] = {
129
130
{ .compatible = "nxp,pca9570", .data = (void *)4 },
131
+
{ .compatible = "nxp,pca9571", .data = (void *)8 },
130
132
{ /* sentinel */ }
131
133
};
132
134
MODULE_DEVICE_TABLE(of, pca9570_of_match_table);
+18
-25
drivers/gpio/gpio-pch.c
+18
-25
drivers/gpio/gpio-pch.c
···
37
37
u32 reset;
38
38
};
39
39
40
+
#define PCI_DEVICE_ID_INTEL_EG20T_PCH 0x8803
41
+
#define PCI_DEVICE_ID_ROHM_ML7223m_IOH 0x8014
42
+
#define PCI_DEVICE_ID_ROHM_ML7223n_IOH 0x8043
43
+
#define PCI_DEVICE_ID_ROHM_EG20T_PCH 0x8803
44
+
40
45
enum pch_type_t {
41
46
INTEL_EG20T_PCH,
42
47
OKISEMI_ML7223m_IOH, /* LAPIS Semiconductor ML7223 IOH PCIe Bus-m */
···
362
357
363
358
chip->dev = dev;
364
359
ret = pcim_enable_device(pdev);
365
-
if (ret) {
366
-
dev_err(dev, "pci_enable_device FAILED");
367
-
return ret;
368
-
}
360
+
if (ret)
361
+
return dev_err_probe(dev, ret, "Failed to enable PCI device\n");
369
362
370
363
ret = pcim_iomap_regions(pdev, BIT(1), KBUILD_MODNAME);
371
-
if (ret) {
372
-
dev_err(dev, "pci_request_regions FAILED-%d", ret);
373
-
return ret;
374
-
}
364
+
if (ret)
365
+
return dev_err_probe(dev, ret, "Failed to request and map PCI regions\n");
375
366
376
367
chip->base = pcim_iomap_table(pdev)[1];
377
368
chip->ioh = id->driver_data;
···
377
376
pch_gpio_setup(chip);
378
377
379
378
ret = devm_gpiochip_add_data(dev, &chip->gpio, chip);
380
-
if (ret) {
381
-
dev_err(dev, "PCH gpio: Failed to register GPIO\n");
382
-
return ret;
383
-
}
379
+
if (ret)
380
+
return dev_err_probe(dev, ret, "Failed to register GPIO\n");
384
381
385
382
irq_base = devm_irq_alloc_descs(dev, -1, 0,
386
383
gpio_pins[chip->ioh], NUMA_NO_NODE);
···
395
396
396
397
ret = devm_request_irq(dev, pdev->irq, pch_gpio_handler,
397
398
IRQF_SHARED, KBUILD_MODNAME, chip);
398
-
if (ret) {
399
-
dev_err(dev, "request_irq failed\n");
400
-
return ret;
401
-
}
399
+
if (ret)
400
+
return dev_err_probe(dev, ret, "Failed to request IRQ\n");
402
401
403
402
return pch_gpio_alloc_generic_chip(chip, irq_base, gpio_pins[chip->ioh]);
404
403
}
···
430
433
static SIMPLE_DEV_PM_OPS(pch_gpio_pm_ops, pch_gpio_suspend, pch_gpio_resume);
431
434
432
435
static const struct pci_device_id pch_gpio_pcidev_id[] = {
433
-
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8803),
434
-
.driver_data = INTEL_EG20T_PCH },
435
-
{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8014),
436
-
.driver_data = OKISEMI_ML7223m_IOH },
437
-
{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8043),
438
-
.driver_data = OKISEMI_ML7223n_IOH },
439
-
{ PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8803),
440
-
.driver_data = INTEL_EG20T_PCH },
441
-
{ 0, }
436
+
{ PCI_DEVICE_DATA(INTEL, EG20T_PCH, INTEL_EG20T_PCH) },
437
+
{ PCI_DEVICE_DATA(ROHM, ML7223m_IOH, OKISEMI_ML7223m_IOH) },
438
+
{ PCI_DEVICE_DATA(ROHM, ML7223n_IOH, OKISEMI_ML7223n_IOH) },
439
+
{ PCI_DEVICE_DATA(ROHM, EG20T_PCH, INTEL_EG20T_PCH) },
440
+
{ }
442
441
};
443
442
MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id);
444
443
+2
-1
drivers/gpio/gpio-rockchip.c
+2
-1
drivers/gpio/gpio-rockchip.c
···
27
27
28
28
#define GPIO_TYPE_V1 (0) /* GPIO Version ID reserved */
29
29
#define GPIO_TYPE_V2 (0x01000C2B) /* GPIO Version ID 0x01000C2B */
30
+
#define GPIO_TYPE_V2_1 (0x0101157C) /* GPIO Version ID 0x0101157C */
30
31
31
32
static const struct rockchip_gpio_regs gpio_regs_v1 = {
32
33
.port_dr = 0x00,
···
665
664
id = readl(bank->reg_base + gpio_regs_v2.version_id);
666
665
667
666
/* If not gpio v2, that is default to v1. */
668
-
if (id == GPIO_TYPE_V2) {
667
+
if (id == GPIO_TYPE_V2 || id == GPIO_TYPE_V2_1) {
669
668
bank->gpio_regs = &gpio_regs_v2;
670
669
bank->gpio_type = GPIO_TYPE_V2;
671
670
bank->db_clk = of_clk_get(bank->of_node, 1);
+2
-16
drivers/gpio/gpio-twl4030.c
+2
-16
drivers/gpio/gpio-twl4030.c
···
593
593
/* Cannot use as gpio_twl4030_probe() calls us */
594
594
static int gpio_twl4030_remove(struct platform_device *pdev)
595
595
{
596
-
struct twl4030_gpio_platform_data *pdata = dev_get_platdata(&pdev->dev);
597
596
struct gpio_twl4030_priv *priv = platform_get_drvdata(pdev);
598
-
int status;
599
-
600
-
if (pdata && pdata->teardown) {
601
-
status = pdata->teardown(&pdev->dev, priv->gpio_chip.base,
602
-
TWL4030_GPIO_MAX);
603
-
if (status) {
604
-
dev_dbg(&pdev->dev, "teardown --> %d\n", status);
605
-
return status;
606
-
}
607
-
}
608
597
609
598
gpiochip_remove(&priv->gpio_chip);
610
599
611
-
if (is_module())
612
-
return 0;
613
-
614
600
/* REVISIT no support yet for deregistering all the IRQs */
615
-
WARN_ON(1);
616
-
return -EIO;
601
+
WARN_ON(!is_module());
602
+
return 0;
617
603
}
618
604
619
605
static const struct of_device_id twl_gpio_match[] = {
-20
drivers/gpio/gpio-ucb1400.c
-20
drivers/gpio/gpio-ucb1400.c
···
64
64
ucb->gc.can_sleep = true;
65
65
66
66
err = devm_gpiochip_add_data(&dev->dev, &ucb->gc, ucb);
67
-
if (err)
68
-
goto err;
69
-
70
-
if (ucb->gpio_setup)
71
-
err = ucb->gpio_setup(&dev->dev, ucb->gc.ngpio);
72
67
73
68
err:
74
69
return err;
75
70
76
71
}
77
72
78
-
static int ucb1400_gpio_remove(struct platform_device *dev)
79
-
{
80
-
int err = 0;
81
-
struct ucb1400_gpio *ucb = platform_get_drvdata(dev);
82
-
83
-
if (ucb && ucb->gpio_teardown) {
84
-
err = ucb->gpio_teardown(&dev->dev, ucb->gc.ngpio);
85
-
if (err)
86
-
return err;
87
-
}
88
-
89
-
return err;
90
-
}
91
-
92
73
static struct platform_driver ucb1400_gpio_driver = {
93
74
.probe = ucb1400_gpio_probe,
94
-
.remove = ucb1400_gpio_remove,
95
75
.driver = {
96
76
.name = "ucb1400_gpio"
97
77
},
-541
drivers/gpio/gpio-vr41xx.c
-541
drivers/gpio/gpio-vr41xx.c
···
1
-
// SPDX-License-Identifier: GPL-2.0+
2
-
/*
3
-
* Driver for NEC VR4100 series General-purpose I/O Unit.
4
-
*
5
-
* Copyright (C) 2002 MontaVista Software Inc.
6
-
* Author: Yoichi Yuasa <source@mvista.com>
7
-
* Copyright (C) 2003-2009 Yoichi Yuasa <yuasa@linux-mips.org>
8
-
*/
9
-
#include <linux/errno.h>
10
-
#include <linux/fs.h>
11
-
#include <linux/gpio/driver.h>
12
-
#include <linux/init.h>
13
-
#include <linux/interrupt.h>
14
-
#include <linux/io.h>
15
-
#include <linux/irq.h>
16
-
#include <linux/kernel.h>
17
-
#include <linux/module.h>
18
-
#include <linux/platform_device.h>
19
-
#include <linux/spinlock.h>
20
-
#include <linux/types.h>
21
-
22
-
#include <asm/vr41xx/giu.h>
23
-
#include <asm/vr41xx/irq.h>
24
-
#include <asm/vr41xx/vr41xx.h>
25
-
26
-
MODULE_AUTHOR("Yoichi Yuasa <yuasa@linux-mips.org>");
27
-
MODULE_DESCRIPTION("NEC VR4100 series General-purpose I/O Unit driver");
28
-
MODULE_LICENSE("GPL");
29
-
30
-
#define GIUIOSELL 0x00
31
-
#define GIUIOSELH 0x02
32
-
#define GIUPIODL 0x04
33
-
#define GIUPIODH 0x06
34
-
#define GIUINTSTATL 0x08
35
-
#define GIUINTSTATH 0x0a
36
-
#define GIUINTENL 0x0c
37
-
#define GIUINTENH 0x0e
38
-
#define GIUINTTYPL 0x10
39
-
#define GIUINTTYPH 0x12
40
-
#define GIUINTALSELL 0x14
41
-
#define GIUINTALSELH 0x16
42
-
#define GIUINTHTSELL 0x18
43
-
#define GIUINTHTSELH 0x1a
44
-
#define GIUPODATL 0x1c
45
-
#define GIUPODATEN 0x1c
46
-
#define GIUPODATH 0x1e
47
-
#define PIOEN0 0x0100
48
-
#define PIOEN1 0x0200
49
-
#define GIUPODAT 0x1e
50
-
#define GIUFEDGEINHL 0x20
51
-
#define GIUFEDGEINHH 0x22
52
-
#define GIUREDGEINHL 0x24
53
-
#define GIUREDGEINHH 0x26
54
-
55
-
#define GIUUSEUPDN 0x1e0
56
-
#define GIUTERMUPDN 0x1e2
57
-
58
-
#define GPIO_HAS_PULLUPDOWN_IO 0x0001
59
-
#define GPIO_HAS_OUTPUT_ENABLE 0x0002
60
-
#define GPIO_HAS_INTERRUPT_EDGE_SELECT 0x0100
61
-
62
-
enum {
63
-
GPIO_INPUT,
64
-
GPIO_OUTPUT,
65
-
};
66
-
67
-
static DEFINE_SPINLOCK(giu_lock);
68
-
static unsigned long giu_flags;
69
-
70
-
static void __iomem *giu_base;
71
-
static struct gpio_chip vr41xx_gpio_chip;
72
-
73
-
#define giu_read(offset) readw(giu_base + (offset))
74
-
#define giu_write(offset, value) writew((value), giu_base + (offset))
75
-
76
-
#define GPIO_PIN_OF_IRQ(irq) ((irq) - GIU_IRQ_BASE)
77
-
#define GIUINT_HIGH_OFFSET 16
78
-
#define GIUINT_HIGH_MAX 32
79
-
80
-
static inline u16 giu_set(u16 offset, u16 set)
81
-
{
82
-
u16 data;
83
-
84
-
data = giu_read(offset);
85
-
data |= set;
86
-
giu_write(offset, data);
87
-
88
-
return data;
89
-
}
90
-
91
-
static inline u16 giu_clear(u16 offset, u16 clear)
92
-
{
93
-
u16 data;
94
-
95
-
data = giu_read(offset);
96
-
data &= ~clear;
97
-
giu_write(offset, data);
98
-
99
-
return data;
100
-
}
101
-
102
-
static void ack_giuint_low(struct irq_data *d)
103
-
{
104
-
giu_write(GIUINTSTATL, 1 << GPIO_PIN_OF_IRQ(d->irq));
105
-
}
106
-
107
-
static void mask_giuint_low(struct irq_data *d)
108
-
{
109
-
giu_clear(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(d->irq));
110
-
}
111
-
112
-
static void mask_ack_giuint_low(struct irq_data *d)
113
-
{
114
-
unsigned int pin;
115
-
116
-
pin = GPIO_PIN_OF_IRQ(d->irq);
117
-
giu_clear(GIUINTENL, 1 << pin);
118
-
giu_write(GIUINTSTATL, 1 << pin);
119
-
}
120
-
121
-
static void unmask_giuint_low(struct irq_data *d)
122
-
{
123
-
giu_set(GIUINTENL, 1 << GPIO_PIN_OF_IRQ(d->irq));
124
-
}
125
-
126
-
static unsigned int startup_giuint(struct irq_data *data)
127
-
{
128
-
int ret;
129
-
130
-
ret = gpiochip_lock_as_irq(&vr41xx_gpio_chip, irqd_to_hwirq(data));
131
-
if (ret) {
132
-
dev_err(vr41xx_gpio_chip.parent,
133
-
"unable to lock HW IRQ %lu for IRQ\n",
134
-
data->hwirq);
135
-
return ret;
136
-
}
137
-
138
-
/* Satisfy the .enable semantics by unmasking the line */
139
-
unmask_giuint_low(data);
140
-
return 0;
141
-
}
142
-
143
-
static void shutdown_giuint(struct irq_data *data)
144
-
{
145
-
mask_giuint_low(data);
146
-
gpiochip_unlock_as_irq(&vr41xx_gpio_chip, data->hwirq);
147
-
}
148
-
149
-
static struct irq_chip giuint_low_irq_chip = {
150
-
.name = "GIUINTL",
151
-
.irq_ack = ack_giuint_low,
152
-
.irq_mask = mask_giuint_low,
153
-
.irq_mask_ack = mask_ack_giuint_low,
154
-
.irq_unmask = unmask_giuint_low,
155
-
.irq_startup = startup_giuint,
156
-
.irq_shutdown = shutdown_giuint,
157
-
};
158
-
159
-
static void ack_giuint_high(struct irq_data *d)
160
-
{
161
-
giu_write(GIUINTSTATH,
162
-
1 << (GPIO_PIN_OF_IRQ(d->irq) - GIUINT_HIGH_OFFSET));
163
-
}
164
-
165
-
static void mask_giuint_high(struct irq_data *d)
166
-
{
167
-
giu_clear(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(d->irq) - GIUINT_HIGH_OFFSET));
168
-
}
169
-
170
-
static void mask_ack_giuint_high(struct irq_data *d)
171
-
{
172
-
unsigned int pin;
173
-
174
-
pin = GPIO_PIN_OF_IRQ(d->irq) - GIUINT_HIGH_OFFSET;
175
-
giu_clear(GIUINTENH, 1 << pin);
176
-
giu_write(GIUINTSTATH, 1 << pin);
177
-
}
178
-
179
-
static void unmask_giuint_high(struct irq_data *d)
180
-
{
181
-
giu_set(GIUINTENH, 1 << (GPIO_PIN_OF_IRQ(d->irq) - GIUINT_HIGH_OFFSET));
182
-
}
183
-
184
-
static struct irq_chip giuint_high_irq_chip = {
185
-
.name = "GIUINTH",
186
-
.irq_ack = ack_giuint_high,
187
-
.irq_mask = mask_giuint_high,
188
-
.irq_mask_ack = mask_ack_giuint_high,
189
-
.irq_unmask = unmask_giuint_high,
190
-
};
191
-
192
-
static int giu_get_irq(unsigned int irq)
193
-
{
194
-
u16 pendl, pendh, maskl, maskh;
195
-
int i;
196
-
197
-
pendl = giu_read(GIUINTSTATL);
198
-
pendh = giu_read(GIUINTSTATH);
199
-
maskl = giu_read(GIUINTENL);
200
-
maskh = giu_read(GIUINTENH);
201
-
202
-
maskl &= pendl;
203
-
maskh &= pendh;
204
-
205
-
if (maskl) {
206
-
for (i = 0; i < 16; i++) {
207
-
if (maskl & (1 << i))
208
-
return GIU_IRQ(i);
209
-
}
210
-
} else if (maskh) {
211
-
for (i = 0; i < 16; i++) {
212
-
if (maskh & (1 << i))
213
-
return GIU_IRQ(i + GIUINT_HIGH_OFFSET);
214
-
}
215
-
}
216
-
217
-
printk(KERN_ERR "spurious GIU interrupt: %04x(%04x),%04x(%04x)\n",
218
-
maskl, pendl, maskh, pendh);
219
-
220
-
return -EINVAL;
221
-
}
222
-
223
-
void vr41xx_set_irq_trigger(unsigned int pin, irq_trigger_t trigger,
224
-
irq_signal_t signal)
225
-
{
226
-
u16 mask;
227
-
228
-
if (pin < GIUINT_HIGH_OFFSET) {
229
-
mask = 1 << pin;
230
-
if (trigger != IRQ_TRIGGER_LEVEL) {
231
-
giu_set(GIUINTTYPL, mask);
232
-
if (signal == IRQ_SIGNAL_HOLD)
233
-
giu_set(GIUINTHTSELL, mask);
234
-
else
235
-
giu_clear(GIUINTHTSELL, mask);
236
-
if (giu_flags & GPIO_HAS_INTERRUPT_EDGE_SELECT) {
237
-
switch (trigger) {
238
-
case IRQ_TRIGGER_EDGE_FALLING:
239
-
giu_set(GIUFEDGEINHL, mask);
240
-
giu_clear(GIUREDGEINHL, mask);
241
-
break;
242
-
case IRQ_TRIGGER_EDGE_RISING:
243
-
giu_clear(GIUFEDGEINHL, mask);
244
-
giu_set(GIUREDGEINHL, mask);
245
-
break;
246
-
default:
247
-
giu_set(GIUFEDGEINHL, mask);
248
-
giu_set(GIUREDGEINHL, mask);
249
-
break;
250
-
}
251
-
}
252
-
irq_set_chip_and_handler(GIU_IRQ(pin),
253
-
&giuint_low_irq_chip,
254
-
handle_edge_irq);
255
-
} else {
256
-
giu_clear(GIUINTTYPL, mask);
257
-
giu_clear(GIUINTHTSELL, mask);
258
-
irq_set_chip_and_handler(GIU_IRQ(pin),
259
-
&giuint_low_irq_chip,
260
-
handle_level_irq);
261
-
}
262
-
giu_write(GIUINTSTATL, mask);
263
-
} else if (pin < GIUINT_HIGH_MAX) {
264
-
mask = 1 << (pin - GIUINT_HIGH_OFFSET);
265
-
if (trigger != IRQ_TRIGGER_LEVEL) {
266
-
giu_set(GIUINTTYPH, mask);
267
-
if (signal == IRQ_SIGNAL_HOLD)
268
-
giu_set(GIUINTHTSELH, mask);
269
-
else
270
-
giu_clear(GIUINTHTSELH, mask);
271
-
if (giu_flags & GPIO_HAS_INTERRUPT_EDGE_SELECT) {
272
-
switch (trigger) {
273
-
case IRQ_TRIGGER_EDGE_FALLING:
274
-
giu_set(GIUFEDGEINHH, mask);
275
-
giu_clear(GIUREDGEINHH, mask);
276
-
break;
277
-
case IRQ_TRIGGER_EDGE_RISING:
278
-
giu_clear(GIUFEDGEINHH, mask);
279
-
giu_set(GIUREDGEINHH, mask);
280
-
break;
281
-
default:
282
-
giu_set(GIUFEDGEINHH, mask);
283
-
giu_set(GIUREDGEINHH, mask);
284
-
break;
285
-
}
286
-
}
287
-
irq_set_chip_and_handler(GIU_IRQ(pin),
288
-
&giuint_high_irq_chip,
289
-
handle_edge_irq);
290
-
} else {
291
-
giu_clear(GIUINTTYPH, mask);
292
-
giu_clear(GIUINTHTSELH, mask);
293
-
irq_set_chip_and_handler(GIU_IRQ(pin),
294
-
&giuint_high_irq_chip,
295
-
handle_level_irq);
296
-
}
297
-
giu_write(GIUINTSTATH, mask);
298
-
}
299
-
}
300
-
EXPORT_SYMBOL_GPL(vr41xx_set_irq_trigger);
301
-
302
-
void vr41xx_set_irq_level(unsigned int pin, irq_level_t level)
303
-
{
304
-
u16 mask;
305
-
306
-
if (pin < GIUINT_HIGH_OFFSET) {
307
-
mask = 1 << pin;
308
-
if (level == IRQ_LEVEL_HIGH)
309
-
giu_set(GIUINTALSELL, mask);
310
-
else
311
-
giu_clear(GIUINTALSELL, mask);
312
-
giu_write(GIUINTSTATL, mask);
313
-
} else if (pin < GIUINT_HIGH_MAX) {
314
-
mask = 1 << (pin - GIUINT_HIGH_OFFSET);
315
-
if (level == IRQ_LEVEL_HIGH)
316
-
giu_set(GIUINTALSELH, mask);
317
-
else
318
-
giu_clear(GIUINTALSELH, mask);
319
-
giu_write(GIUINTSTATH, mask);
320
-
}
321
-
}
322
-
EXPORT_SYMBOL_GPL(vr41xx_set_irq_level);
323
-
324
-
static int giu_set_direction(struct gpio_chip *chip, unsigned pin, int dir)
325
-
{
326
-
u16 offset, mask, reg;
327
-
unsigned long flags;
328
-
329
-
if (pin >= chip->ngpio)
330
-
return -EINVAL;
331
-
332
-
if (pin < 16) {
333
-
offset = GIUIOSELL;
334
-
mask = 1 << pin;
335
-
} else if (pin < 32) {
336
-
offset = GIUIOSELH;
337
-
mask = 1 << (pin - 16);
338
-
} else {
339
-
if (giu_flags & GPIO_HAS_OUTPUT_ENABLE) {
340
-
offset = GIUPODATEN;
341
-
mask = 1 << (pin - 32);
342
-
} else {
343
-
switch (pin) {
344
-
case 48:
345
-
offset = GIUPODATH;
346
-
mask = PIOEN0;
347
-
break;
348
-
case 49:
349
-
offset = GIUPODATH;
350
-
mask = PIOEN1;
351
-
break;
352
-
default:
353
-
return -EINVAL;
354
-
}
355
-
}
356
-
}
357
-
358
-
spin_lock_irqsave(&giu_lock, flags);
359
-
360
-
reg = giu_read(offset);
361
-
if (dir == GPIO_OUTPUT)
362
-
reg |= mask;
363
-
else
364
-
reg &= ~mask;
365
-
giu_write(offset, reg);
366
-
367
-
spin_unlock_irqrestore(&giu_lock, flags);
368
-
369
-
return 0;
370
-
}
371
-
372
-
static int vr41xx_gpio_get(struct gpio_chip *chip, unsigned pin)
373
-
{
374
-
u16 reg, mask;
375
-
376
-
if (pin >= chip->ngpio)
377
-
return -EINVAL;
378
-
379
-
if (pin < 16) {
380
-
reg = giu_read(GIUPIODL);
381
-
mask = 1 << pin;
382
-
} else if (pin < 32) {
383
-
reg = giu_read(GIUPIODH);
384
-
mask = 1 << (pin - 16);
385
-
} else if (pin < 48) {
386
-
reg = giu_read(GIUPODATL);
387
-
mask = 1 << (pin - 32);
388
-
} else {
389
-
reg = giu_read(GIUPODATH);
390
-
mask = 1 << (pin - 48);
391
-
}
392
-
393
-
if (reg & mask)
394
-
return 1;
395
-
396
-
return 0;
397
-
}
398
-
399
-
static void vr41xx_gpio_set(struct gpio_chip *chip, unsigned pin,
400
-
int value)
401
-
{
402
-
u16 offset, mask, reg;
403
-
unsigned long flags;
404
-
405
-
if (pin >= chip->ngpio)
406
-
return;
407
-
408
-
if (pin < 16) {
409
-
offset = GIUPIODL;
410
-
mask = 1 << pin;
411
-
} else if (pin < 32) {
412
-
offset = GIUPIODH;
413
-
mask = 1 << (pin - 16);
414
-
} else if (pin < 48) {
415
-
offset = GIUPODATL;
416
-
mask = 1 << (pin - 32);
417
-
} else {
418
-
offset = GIUPODATH;
419
-
mask = 1 << (pin - 48);
420
-
}
421
-
422
-
spin_lock_irqsave(&giu_lock, flags);
423
-
424
-
reg = giu_read(offset);
425
-
if (value)
426
-
reg |= mask;
427
-
else
428
-
reg &= ~mask;
429
-
giu_write(offset, reg);
430
-
431
-
spin_unlock_irqrestore(&giu_lock, flags);
432
-
}
433
-
434
-
435
-
static int vr41xx_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
436
-
{
437
-
return giu_set_direction(chip, offset, GPIO_INPUT);
438
-
}
439
-
440
-
static int vr41xx_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
441
-
int value)
442
-
{
443
-
vr41xx_gpio_set(chip, offset, value);
444
-
445
-
return giu_set_direction(chip, offset, GPIO_OUTPUT);
446
-
}
447
-
448
-
static int vr41xx_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
449
-
{
450
-
if (offset >= chip->ngpio)
451
-
return -EINVAL;
452
-
453
-
return GIU_IRQ_BASE + offset;
454
-
}
455
-
456
-
static struct gpio_chip vr41xx_gpio_chip = {
457
-
.label = "vr41xx",
458
-
.owner = THIS_MODULE,
459
-
.direction_input = vr41xx_gpio_direction_input,
460
-
.get = vr41xx_gpio_get,
461
-
.direction_output = vr41xx_gpio_direction_output,
462
-
.set = vr41xx_gpio_set,
463
-
.to_irq = vr41xx_gpio_to_irq,
464
-
};
465
-
466
-
static int giu_probe(struct platform_device *pdev)
467
-
{
468
-
unsigned int trigger, i, pin;
469
-
struct irq_chip *chip;
470
-
int irq;
471
-
472
-
switch (pdev->id) {
473
-
case GPIO_50PINS_PULLUPDOWN:
474
-
giu_flags = GPIO_HAS_PULLUPDOWN_IO;
475
-
vr41xx_gpio_chip.ngpio = 50;
476
-
break;
477
-
case GPIO_36PINS:
478
-
vr41xx_gpio_chip.ngpio = 36;
479
-
break;
480
-
case GPIO_48PINS_EDGE_SELECT:
481
-
giu_flags = GPIO_HAS_INTERRUPT_EDGE_SELECT;
482
-
vr41xx_gpio_chip.ngpio = 48;
483
-
break;
484
-
default:
485
-
dev_err(&pdev->dev, "GIU: unknown ID %d\n", pdev->id);
486
-
return -ENODEV;
487
-
}
488
-
489
-
giu_base = devm_platform_ioremap_resource(pdev, 0);
490
-
if (IS_ERR(giu_base))
491
-
return PTR_ERR(giu_base);
492
-
493
-
vr41xx_gpio_chip.parent = &pdev->dev;
494
-
495
-
if (gpiochip_add_data(&vr41xx_gpio_chip, NULL))
496
-
return -ENODEV;
497
-
498
-
giu_write(GIUINTENL, 0);
499
-
giu_write(GIUINTENH, 0);
500
-
501
-
trigger = giu_read(GIUINTTYPH) << 16;
502
-
trigger |= giu_read(GIUINTTYPL);
503
-
for (i = GIU_IRQ_BASE; i <= GIU_IRQ_LAST; i++) {
504
-
pin = GPIO_PIN_OF_IRQ(i);
505
-
if (pin < GIUINT_HIGH_OFFSET)
506
-
chip = &giuint_low_irq_chip;
507
-
else
508
-
chip = &giuint_high_irq_chip;
509
-
510
-
if (trigger & (1 << pin))
511
-
irq_set_chip_and_handler(i, chip, handle_edge_irq);
512
-
else
513
-
irq_set_chip_and_handler(i, chip, handle_level_irq);
514
-
515
-
}
516
-
517
-
irq = platform_get_irq(pdev, 0);
518
-
if (irq < 0 || irq >= nr_irqs)
519
-
return -EBUSY;
520
-
521
-
return cascade_irq(irq, giu_get_irq);
522
-
}
523
-
524
-
static int giu_remove(struct platform_device *pdev)
525
-
{
526
-
if (giu_base) {
527
-
giu_base = NULL;
528
-
}
529
-
530
-
return 0;
531
-
}
532
-
533
-
static struct platform_driver giu_device_driver = {
534
-
.probe = giu_probe,
535
-
.remove = giu_remove,
536
-
.driver = {
537
-
.name = "GIU",
538
-
},
539
-
};
540
-
541
-
module_platform_driver(giu_device_driver);
+84
-36
drivers/gpio/gpio-ws16c48.c
+84
-36
drivers/gpio/gpio-ws16c48.c
···
4
4
* Copyright (C) 2016 William Breathitt Gray
5
5
*/
6
6
#include <linux/bitmap.h>
7
-
#include <linux/bitops.h>
8
7
#include <linux/device.h>
9
8
#include <linux/errno.h>
10
9
#include <linux/gpio/driver.h>
···
16
17
#include <linux/module.h>
17
18
#include <linux/moduleparam.h>
18
19
#include <linux/spinlock.h>
20
+
#include <linux/types.h>
19
21
20
-
#define WS16C48_EXTENT 16
22
+
#define WS16C48_EXTENT 10
21
23
#define MAX_NUM_WS16C48 max_num_isa_dev(WS16C48_EXTENT)
22
24
23
25
static unsigned int base[MAX_NUM_WS16C48];
···
31
31
MODULE_PARM_DESC(irq, "WinSystems WS16C48 interrupt line numbers");
32
32
33
33
/**
34
+
* struct ws16c48_reg - device register structure
35
+
* @port: Port 0 through 5 I/O
36
+
* @int_pending: Interrupt Pending
37
+
* @page_lock: Register page (Bits 7-6) and I/O port lock (Bits 5-0)
38
+
* @pol_enab_int_id: Interrupt polarity, enable, and ID
39
+
*/
40
+
struct ws16c48_reg {
41
+
u8 port[6];
42
+
u8 int_pending;
43
+
u8 page_lock;
44
+
u8 pol_enab_int_id[3];
45
+
};
46
+
47
+
/**
34
48
* struct ws16c48_gpio - GPIO device private data structure
35
49
* @chip: instance of the gpio_chip
36
50
* @io_state: bit I/O state (whether bit is set to input or output)
···
52
38
* @lock: synchronization lock to prevent I/O race conditions
53
39
* @irq_mask: I/O bits affected by interrupts
54
40
* @flow_mask: IRQ flow type mask for the respective I/O bits
55
-
* @base: base port address of the GPIO device
41
+
* @reg: I/O address offset for the device registers
56
42
*/
57
43
struct ws16c48_gpio {
58
44
struct gpio_chip chip;
···
61
47
raw_spinlock_t lock;
62
48
unsigned long irq_mask;
63
49
unsigned long flow_mask;
64
-
void __iomem *base;
50
+
struct ws16c48_reg __iomem *reg;
65
51
};
66
52
67
53
static int ws16c48_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
···
87
73
88
74
ws16c48gpio->io_state[port] |= mask;
89
75
ws16c48gpio->out_state[port] &= ~mask;
90
-
iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
76
+
iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->reg->port + port);
91
77
92
78
raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
93
79
···
109
95
ws16c48gpio->out_state[port] |= mask;
110
96
else
111
97
ws16c48gpio->out_state[port] &= ~mask;
112
-
iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
98
+
iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->reg->port + port);
113
99
114
100
raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
115
101
···
132
118
return -EINVAL;
133
119
}
134
120
135
-
port_state = ioread8(ws16c48gpio->base + port);
121
+
port_state = ioread8(ws16c48gpio->reg->port + port);
136
122
137
123
raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
138
124
···
145
131
struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
146
132
unsigned long offset;
147
133
unsigned long gpio_mask;
148
-
void __iomem *port_addr;
134
+
size_t index;
135
+
u8 __iomem *port_addr;
149
136
unsigned long port_state;
150
137
151
138
/* clear bits array to a clean slate */
152
139
bitmap_zero(bits, chip->ngpio);
153
140
154
141
for_each_set_clump8(offset, gpio_mask, mask, chip->ngpio) {
155
-
port_addr = ws16c48gpio->base + offset / 8;
142
+
index = offset / 8;
143
+
port_addr = ws16c48gpio->reg->port + index;
156
144
port_state = ioread8(port_addr) & gpio_mask;
157
145
158
146
bitmap_set_value8(bits, port_state, offset);
···
182
166
ws16c48gpio->out_state[port] |= mask;
183
167
else
184
168
ws16c48gpio->out_state[port] &= ~mask;
185
-
iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
169
+
iowrite8(ws16c48gpio->out_state[port], ws16c48gpio->reg->port + port);
186
170
187
171
raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
188
172
}
···
194
178
unsigned long offset;
195
179
unsigned long gpio_mask;
196
180
size_t index;
197
-
void __iomem *port_addr;
181
+
u8 __iomem *port_addr;
198
182
unsigned long bitmask;
199
183
unsigned long flags;
200
184
201
185
for_each_set_clump8(offset, gpio_mask, mask, chip->ngpio) {
202
186
index = offset / 8;
203
-
port_addr = ws16c48gpio->base + index;
187
+
port_addr = ws16c48gpio->reg->port + index;
204
188
205
189
/* mask out GPIO configured for input */
206
190
gpio_mask &= ~ws16c48gpio->io_state[index];
···
235
219
236
220
port_state = ws16c48gpio->irq_mask >> (8*port);
237
221
238
-
iowrite8(0x80, ws16c48gpio->base + 7);
239
-
iowrite8(port_state & ~mask, ws16c48gpio->base + 8 + port);
240
-
iowrite8(port_state | mask, ws16c48gpio->base + 8 + port);
241
-
iowrite8(0xC0, ws16c48gpio->base + 7);
222
+
/* Select Register Page 2; Unlock all I/O ports */
223
+
iowrite8(0x80, &ws16c48gpio->reg->page_lock);
224
+
225
+
/* Clear pending interrupt */
226
+
iowrite8(port_state & ~mask, ws16c48gpio->reg->pol_enab_int_id + port);
227
+
iowrite8(port_state | mask, ws16c48gpio->reg->pol_enab_int_id + port);
228
+
229
+
/* Select Register Page 3; Unlock all I/O ports */
230
+
iowrite8(0xC0, &ws16c48gpio->reg->page_lock);
242
231
243
232
raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
244
233
}
···
256
235
const unsigned long mask = BIT(offset);
257
236
const unsigned port = offset / 8;
258
237
unsigned long flags;
238
+
unsigned long port_state;
259
239
260
240
/* only the first 3 ports support interrupts */
261
241
if (port > 2)
···
265
243
raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
266
244
267
245
ws16c48gpio->irq_mask &= ~mask;
246
+
port_state = ws16c48gpio->irq_mask >> (8 * port);
268
247
269
-
iowrite8(0x80, ws16c48gpio->base + 7);
270
-
iowrite8(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port);
271
-
iowrite8(0xC0, ws16c48gpio->base + 7);
248
+
/* Select Register Page 2; Unlock all I/O ports */
249
+
iowrite8(0x80, &ws16c48gpio->reg->page_lock);
250
+
251
+
/* Disable interrupt */
252
+
iowrite8(port_state, ws16c48gpio->reg->pol_enab_int_id + port);
253
+
254
+
/* Select Register Page 3; Unlock all I/O ports */
255
+
iowrite8(0xC0, &ws16c48gpio->reg->page_lock);
272
256
273
257
raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
274
258
}
···
287
259
const unsigned long mask = BIT(offset);
288
260
const unsigned port = offset / 8;
289
261
unsigned long flags;
262
+
unsigned long port_state;
290
263
291
264
/* only the first 3 ports support interrupts */
292
265
if (port > 2)
···
296
267
raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
297
268
298
269
ws16c48gpio->irq_mask |= mask;
270
+
port_state = ws16c48gpio->irq_mask >> (8 * port);
299
271
300
-
iowrite8(0x80, ws16c48gpio->base + 7);
301
-
iowrite8(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port);
302
-
iowrite8(0xC0, ws16c48gpio->base + 7);
272
+
/* Select Register Page 2; Unlock all I/O ports */
273
+
iowrite8(0x80, &ws16c48gpio->reg->page_lock);
274
+
275
+
/* Enable interrupt */
276
+
iowrite8(port_state, ws16c48gpio->reg->pol_enab_int_id + port);
277
+
278
+
/* Select Register Page 3; Unlock all I/O ports */
279
+
iowrite8(0xC0, &ws16c48gpio->reg->page_lock);
303
280
304
281
raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
305
282
}
···
318
283
const unsigned long mask = BIT(offset);
319
284
const unsigned port = offset / 8;
320
285
unsigned long flags;
286
+
unsigned long port_state;
321
287
322
288
/* only the first 3 ports support interrupts */
323
289
if (port > 2)
···
340
304
return -EINVAL;
341
305
}
342
306
343
-
iowrite8(0x40, ws16c48gpio->base + 7);
344
-
iowrite8(ws16c48gpio->flow_mask >> (8*port), ws16c48gpio->base + 8 + port);
345
-
iowrite8(0xC0, ws16c48gpio->base + 7);
307
+
port_state = ws16c48gpio->flow_mask >> (8 * port);
308
+
309
+
/* Select Register Page 1; Unlock all I/O ports */
310
+
iowrite8(0x40, &ws16c48gpio->reg->page_lock);
311
+
312
+
/* Set interrupt polarity */
313
+
iowrite8(port_state, ws16c48gpio->reg->pol_enab_int_id + port);
314
+
315
+
/* Select Register Page 3; Unlock all I/O ports */
316
+
iowrite8(0xC0, &ws16c48gpio->reg->page_lock);
346
317
347
318
raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
348
319
···
368
325
{
369
326
struct ws16c48_gpio *const ws16c48gpio = dev_id;
370
327
struct gpio_chip *const chip = &ws16c48gpio->chip;
328
+
struct ws16c48_reg __iomem *const reg = ws16c48gpio->reg;
371
329
unsigned long int_pending;
372
330
unsigned long port;
373
331
unsigned long int_id;
374
332
unsigned long gpio;
375
333
376
-
int_pending = ioread8(ws16c48gpio->base + 6) & 0x7;
334
+
int_pending = ioread8(®->int_pending) & 0x7;
377
335
if (!int_pending)
378
336
return IRQ_NONE;
379
337
380
338
/* loop until all pending interrupts are handled */
381
339
do {
382
340
for_each_set_bit(port, &int_pending, 3) {
383
-
int_id = ioread8(ws16c48gpio->base + 8 + port);
341
+
int_id = ioread8(reg->pol_enab_int_id + port);
384
342
for_each_set_bit(gpio, &int_id, 8)
385
343
generic_handle_domain_irq(chip->irq.domain,
386
344
gpio + 8*port);
387
345
}
388
346
389
-
int_pending = ioread8(ws16c48gpio->base + 6) & 0x7;
347
+
int_pending = ioread8(®->int_pending) & 0x7;
390
348
} while (int_pending);
391
349
392
350
return IRQ_HANDLED;
···
413
369
{
414
370
struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(gc);
415
371
416
-
/* Disable IRQ by default */
417
-
iowrite8(0x80, ws16c48gpio->base + 7);
418
-
iowrite8(0, ws16c48gpio->base + 8);
419
-
iowrite8(0, ws16c48gpio->base + 9);
420
-
iowrite8(0, ws16c48gpio->base + 10);
421
-
iowrite8(0xC0, ws16c48gpio->base + 7);
372
+
/* Select Register Page 2; Unlock all I/O ports */
373
+
iowrite8(0x80, &ws16c48gpio->reg->page_lock);
374
+
375
+
/* Disable interrupts for all lines */
376
+
iowrite8(0, &ws16c48gpio->reg->pol_enab_int_id[0]);
377
+
iowrite8(0, &ws16c48gpio->reg->pol_enab_int_id[1]);
378
+
iowrite8(0, &ws16c48gpio->reg->pol_enab_int_id[2]);
379
+
380
+
/* Select Register Page 3; Unlock all I/O ports */
381
+
iowrite8(0xC0, &ws16c48gpio->reg->page_lock);
422
382
423
383
return 0;
424
384
}
···
444
396
return -EBUSY;
445
397
}
446
398
447
-
ws16c48gpio->base = devm_ioport_map(dev, base[id], WS16C48_EXTENT);
448
-
if (!ws16c48gpio->base)
399
+
ws16c48gpio->reg = devm_ioport_map(dev, base[id], WS16C48_EXTENT);
400
+
if (!ws16c48gpio->reg)
449
401
return -ENOMEM;
450
402
451
403
ws16c48gpio->chip.label = name;
+1
-5
drivers/gpio/gpio-xgs-iproc.c
+1
-5
drivers/gpio/gpio-xgs-iproc.c
···
281
281
282
282
static int iproc_gpio_remove(struct platform_device *pdev)
283
283
{
284
-
struct iproc_gpio_chip *chip;
285
-
286
-
chip = platform_get_drvdata(pdev);
287
-
if (!chip)
288
-
return -ENODEV;
284
+
struct iproc_gpio_chip *chip = platform_get_drvdata(pdev);
289
285
290
286
if (chip->intr) {
291
287
u32 val;
+2
drivers/gpio/gpio-xilinx.c
+2
drivers/gpio/gpio-xilinx.c
···
117
117
static void xgpio_read_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a)
118
118
{
119
119
void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32);
120
+
120
121
xgpio_set_value32(a, bit, xgpio_readreg(addr));
121
122
}
122
123
123
124
static void xgpio_write_ch(struct xgpio_instance *chip, int reg, int bit, unsigned long *a)
124
125
{
125
126
void __iomem *addr = chip->regs + reg + xgpio_regoffset(chip, bit / 32);
127
+
126
128
xgpio_writereg(addr, xgpio_get_value32(a, bit));
127
129
}
128
130
+3
drivers/gpio/gpiolib-acpi.c
+3
drivers/gpio/gpiolib-acpi.c
+151
-140
drivers/gpio/gpiolib-cdev.c
+151
-140
drivers/gpio/gpiolib-cdev.c
···
434
434
struct linereq *req;
435
435
unsigned int irq;
436
436
/*
437
-
* eflags is set by edge_detector_setup(), edge_detector_stop() and
438
-
* edge_detector_update(), which are themselves mutually exclusive,
439
-
* and is accessed by edge_irq_thread() and debounce_work_func(),
440
-
* which can both live with a slightly stale value.
437
+
* The flags for the active edge detector configuration.
438
+
*
439
+
* edflags is set by linereq_create(), linereq_free(), and
440
+
* linereq_set_config_unlocked(), which are themselves mutually
441
+
* exclusive, and is accessed by edge_irq_thread(),
442
+
* process_hw_ts_thread() and debounce_work_func(),
443
+
* which can all live with a slightly stale value.
441
444
*/
442
-
u64 eflags;
445
+
u64 edflags;
443
446
/*
444
447
* timestamp_ns and req_seqno are accessed only by
445
448
* edge_irq_handler() and edge_irq_thread(), which are themselves
···
472
469
* stale value.
473
470
*/
474
471
unsigned int level;
475
-
/*
476
-
* -- hte specific fields --
477
-
*/
472
+
#ifdef CONFIG_HTE
478
473
struct hte_ts_desc hdesc;
479
474
/*
480
475
* HTE provider sets line level at the time of event. The valid
···
489
488
* last sequence number before debounce period expires.
490
489
*/
491
490
u32 last_seqno;
491
+
#endif /* CONFIG_HTE */
492
492
};
493
493
494
494
/**
···
547
545
GPIO_V2_LINE_FLAG_EVENT_CLOCK_HTE | \
548
546
GPIO_V2_LINE_BIAS_FLAGS)
549
547
548
+
/* subset of flags relevant for edge detector configuration */
549
+
#define GPIO_V2_LINE_EDGE_DETECTOR_FLAGS \
550
+
(GPIO_V2_LINE_FLAG_ACTIVE_LOW | \
551
+
GPIO_V2_LINE_FLAG_EVENT_CLOCK_HTE | \
552
+
GPIO_V2_LINE_EDGE_FLAGS)
553
+
550
554
static void linereq_put_event(struct linereq *lr,
551
555
struct gpio_v2_line_event *le)
552
556
{
···
575
567
{
576
568
if (test_bit(FLAG_EVENT_CLOCK_REALTIME, &line->desc->flags))
577
569
return ktime_get_real_ns();
578
-
else if (test_bit(FLAG_EVENT_CLOCK_HTE, &line->desc->flags))
570
+
else if (IS_ENABLED(CONFIG_HTE) &&
571
+
test_bit(FLAG_EVENT_CLOCK_HTE, &line->desc->flags))
579
572
return line->timestamp_ns;
580
573
581
574
return ktime_get_ns();
582
575
}
576
+
577
+
static u32 line_event_id(int level)
578
+
{
579
+
return level ? GPIO_V2_LINE_EVENT_RISING_EDGE :
580
+
GPIO_V2_LINE_EVENT_FALLING_EDGE;
581
+
}
582
+
583
+
#ifdef CONFIG_HTE
583
584
584
585
static enum hte_return process_hw_ts_thread(void *p)
585
586
{
586
587
struct line *line;
587
588
struct linereq *lr;
588
589
struct gpio_v2_line_event le;
590
+
u64 edflags;
589
591
int level;
590
-
u64 eflags;
591
592
592
593
if (!p)
593
594
return HTE_CB_HANDLED;
···
607
590
memset(&le, 0, sizeof(le));
608
591
609
592
le.timestamp_ns = line->timestamp_ns;
610
-
eflags = READ_ONCE(line->eflags);
593
+
edflags = READ_ONCE(line->edflags);
611
594
612
-
if (eflags == GPIO_V2_LINE_FLAG_EDGE_BOTH) {
613
-
if (line->raw_level >= 0) {
614
-
if (test_bit(FLAG_ACTIVE_LOW, &line->desc->flags))
615
-
level = !line->raw_level;
616
-
else
617
-
level = line->raw_level;
618
-
} else {
619
-
level = gpiod_get_value_cansleep(line->desc);
620
-
}
595
+
switch (edflags & GPIO_V2_LINE_EDGE_FLAGS) {
596
+
case GPIO_V2_LINE_FLAG_EDGE_BOTH:
597
+
level = (line->raw_level >= 0) ?
598
+
line->raw_level :
599
+
gpiod_get_raw_value_cansleep(line->desc);
621
600
622
-
if (level)
623
-
le.id = GPIO_V2_LINE_EVENT_RISING_EDGE;
624
-
else
625
-
le.id = GPIO_V2_LINE_EVENT_FALLING_EDGE;
626
-
} else if (eflags == GPIO_V2_LINE_FLAG_EDGE_RISING) {
627
-
/* Emit low-to-high event */
601
+
if (edflags & GPIO_V2_LINE_FLAG_ACTIVE_LOW)
602
+
level = !level;
603
+
604
+
le.id = line_event_id(level);
605
+
break;
606
+
case GPIO_V2_LINE_FLAG_EDGE_RISING:
628
607
le.id = GPIO_V2_LINE_EVENT_RISING_EDGE;
629
-
} else if (eflags == GPIO_V2_LINE_FLAG_EDGE_FALLING) {
630
-
/* Emit high-to-low event */
608
+
break;
609
+
case GPIO_V2_LINE_FLAG_EDGE_FALLING:
631
610
le.id = GPIO_V2_LINE_EVENT_FALLING_EDGE;
632
-
} else {
611
+
break;
612
+
default:
633
613
return HTE_CB_HANDLED;
634
614
}
635
615
le.line_seqno = line->line_seqno;
···
673
659
return HTE_CB_HANDLED;
674
660
}
675
661
662
+
static int hte_edge_setup(struct line *line, u64 eflags)
663
+
{
664
+
int ret;
665
+
unsigned long flags = 0;
666
+
struct hte_ts_desc *hdesc = &line->hdesc;
667
+
668
+
if (eflags & GPIO_V2_LINE_FLAG_EDGE_RISING)
669
+
flags |= test_bit(FLAG_ACTIVE_LOW, &line->desc->flags) ?
670
+
HTE_FALLING_EDGE_TS :
671
+
HTE_RISING_EDGE_TS;
672
+
if (eflags & GPIO_V2_LINE_FLAG_EDGE_FALLING)
673
+
flags |= test_bit(FLAG_ACTIVE_LOW, &line->desc->flags) ?
674
+
HTE_RISING_EDGE_TS :
675
+
HTE_FALLING_EDGE_TS;
676
+
677
+
line->total_discard_seq = 0;
678
+
679
+
hte_init_line_attr(hdesc, desc_to_gpio(line->desc), flags, NULL,
680
+
line->desc);
681
+
682
+
ret = hte_ts_get(NULL, hdesc, 0);
683
+
if (ret)
684
+
return ret;
685
+
686
+
return hte_request_ts_ns(hdesc, process_hw_ts, process_hw_ts_thread,
687
+
line);
688
+
}
689
+
690
+
#else
691
+
692
+
static int hte_edge_setup(struct line *line, u64 eflags)
693
+
{
694
+
return 0;
695
+
}
696
+
#endif /* CONFIG_HTE */
697
+
676
698
static irqreturn_t edge_irq_thread(int irq, void *p)
677
699
{
678
700
struct line *line = p;
679
701
struct linereq *lr = line->req;
680
702
struct gpio_v2_line_event le;
681
-
u64 eflags;
682
703
683
704
/* Do not leak kernel stack to userspace */
684
705
memset(&le, 0, sizeof(le));
···
732
683
}
733
684
line->timestamp_ns = 0;
734
685
735
-
eflags = READ_ONCE(line->eflags);
736
-
if (eflags == GPIO_V2_LINE_FLAG_EDGE_BOTH) {
737
-
int level = gpiod_get_value_cansleep(line->desc);
738
-
739
-
if (level)
740
-
/* Emit low-to-high event */
741
-
le.id = GPIO_V2_LINE_EVENT_RISING_EDGE;
742
-
else
743
-
/* Emit high-to-low event */
744
-
le.id = GPIO_V2_LINE_EVENT_FALLING_EDGE;
745
-
} else if (eflags == GPIO_V2_LINE_FLAG_EDGE_RISING) {
746
-
/* Emit low-to-high event */
686
+
switch (READ_ONCE(line->edflags) & GPIO_V2_LINE_EDGE_FLAGS) {
687
+
case GPIO_V2_LINE_FLAG_EDGE_BOTH:
688
+
le.id = line_event_id(gpiod_get_value_cansleep(line->desc));
689
+
break;
690
+
case GPIO_V2_LINE_FLAG_EDGE_RISING:
747
691
le.id = GPIO_V2_LINE_EVENT_RISING_EDGE;
748
-
} else if (eflags == GPIO_V2_LINE_FLAG_EDGE_FALLING) {
749
-
/* Emit high-to-low event */
692
+
break;
693
+
case GPIO_V2_LINE_FLAG_EDGE_FALLING:
750
694
le.id = GPIO_V2_LINE_EVENT_FALLING_EDGE;
751
-
} else {
695
+
break;
696
+
default:
752
697
return IRQ_NONE;
753
698
}
754
699
line->line_seqno++;
···
807
764
struct gpio_v2_line_event le;
808
765
struct line *line = container_of(work, struct line, work.work);
809
766
struct linereq *lr;
810
-
int level, diff_seqno;
811
-
u64 eflags;
767
+
u64 eflags, edflags = READ_ONCE(line->edflags);
768
+
int level = -1;
769
+
#ifdef CONFIG_HTE
770
+
int diff_seqno;
812
771
813
-
if (test_bit(FLAG_EVENT_CLOCK_HTE, &line->desc->flags)) {
772
+
if (edflags & GPIO_V2_LINE_FLAG_EVENT_CLOCK_HTE)
814
773
level = line->raw_level;
815
-
if (level < 0)
816
-
level = gpiod_get_raw_value_cansleep(line->desc);
817
-
} else {
774
+
#endif
775
+
if (level < 0)
818
776
level = gpiod_get_raw_value_cansleep(line->desc);
819
-
}
820
777
if (level < 0) {
821
778
pr_debug_ratelimited("debouncer failed to read line value\n");
822
779
return;
···
828
785
WRITE_ONCE(line->level, level);
829
786
830
787
/* -- edge detection -- */
831
-
eflags = READ_ONCE(line->eflags);
788
+
eflags = edflags & GPIO_V2_LINE_EDGE_FLAGS;
832
789
if (!eflags)
833
790
return;
834
791
835
792
/* switch from physical level to logical - if they differ */
836
-
if (test_bit(FLAG_ACTIVE_LOW, &line->desc->flags))
793
+
if (edflags & GPIO_V2_LINE_FLAG_ACTIVE_LOW)
837
794
level = !level;
838
795
839
796
/* ignore edges that are not being monitored */
···
847
804
lr = line->req;
848
805
le.timestamp_ns = line_event_timestamp(line);
849
806
le.offset = gpio_chip_hwgpio(line->desc);
850
-
if (test_bit(FLAG_EVENT_CLOCK_HTE, &line->desc->flags)) {
807
+
#ifdef CONFIG_HTE
808
+
if (edflags & GPIO_V2_LINE_FLAG_EVENT_CLOCK_HTE) {
851
809
/* discard events except the last one */
852
810
line->total_discard_seq -= 1;
853
811
diff_seqno = line->last_seqno - line->total_discard_seq -
···
857
813
le.line_seqno = line->line_seqno;
858
814
le.seqno = (lr->num_lines == 1) ?
859
815
le.line_seqno : atomic_add_return(diff_seqno, &lr->seqno);
860
-
} else {
816
+
} else
817
+
#endif /* CONFIG_HTE */
818
+
{
861
819
line->line_seqno++;
862
820
le.line_seqno = line->line_seqno;
863
821
le.seqno = (lr->num_lines == 1) ?
864
822
le.line_seqno : atomic_inc_return(&lr->seqno);
865
823
}
866
824
867
-
if (level)
868
-
/* Emit low-to-high event */
869
-
le.id = GPIO_V2_LINE_EVENT_RISING_EDGE;
870
-
else
871
-
/* Emit high-to-low event */
872
-
le.id = GPIO_V2_LINE_EVENT_FALLING_EDGE;
825
+
le.id = line_event_id(level);
873
826
874
827
linereq_put_event(lr, &le);
875
828
}
876
829
877
-
static int hte_edge_setup(struct line *line, u64 eflags)
878
-
{
879
-
int ret;
880
-
unsigned long flags = 0;
881
-
struct hte_ts_desc *hdesc = &line->hdesc;
882
-
883
-
if (eflags & GPIO_V2_LINE_FLAG_EDGE_RISING)
884
-
flags |= test_bit(FLAG_ACTIVE_LOW, &line->desc->flags) ?
885
-
HTE_FALLING_EDGE_TS : HTE_RISING_EDGE_TS;
886
-
if (eflags & GPIO_V2_LINE_FLAG_EDGE_FALLING)
887
-
flags |= test_bit(FLAG_ACTIVE_LOW, &line->desc->flags) ?
888
-
HTE_RISING_EDGE_TS : HTE_FALLING_EDGE_TS;
889
-
890
-
line->total_discard_seq = 0;
891
-
892
-
hte_init_line_attr(hdesc, desc_to_gpio(line->desc), flags,
893
-
NULL, line->desc);
894
-
895
-
ret = hte_ts_get(NULL, hdesc, 0);
896
-
if (ret)
897
-
return ret;
898
-
899
-
return hte_request_ts_ns(hdesc, process_hw_ts,
900
-
process_hw_ts_thread, line);
901
-
}
902
-
903
-
static int debounce_setup(struct line *line,
904
-
unsigned int debounce_period_us, bool hte_req)
830
+
static int debounce_setup(struct line *line, unsigned int debounce_period_us)
905
831
{
906
832
unsigned long irqflags;
907
833
int ret, level, irq;
···
891
877
if (level < 0)
892
878
return level;
893
879
894
-
if (!hte_req) {
880
+
if (!(IS_ENABLED(CONFIG_HTE) &&
881
+
test_bit(FLAG_EVENT_CLOCK_HTE, &line->desc->flags))) {
895
882
irq = gpiod_to_irq(line->desc);
896
883
if (irq < 0)
897
884
return -ENXIO;
···
904
889
return ret;
905
890
line->irq = irq;
906
891
} else {
907
-
ret = hte_edge_setup(line,
908
-
GPIO_V2_LINE_FLAG_EDGE_RISING |
909
-
GPIO_V2_LINE_FLAG_EDGE_FALLING);
892
+
ret = hte_edge_setup(line, GPIO_V2_LINE_FLAG_EDGE_BOTH);
910
893
if (ret)
911
894
return ret;
912
895
}
···
943
930
return 0;
944
931
}
945
932
946
-
static void edge_detector_stop(struct line *line, bool hte_en)
933
+
static void edge_detector_stop(struct line *line)
947
934
{
948
-
if (line->irq && !hte_en) {
935
+
if (line->irq) {
949
936
free_irq(line->irq, line);
950
937
line->irq = 0;
951
938
}
952
939
953
-
if (hte_en)
940
+
#ifdef CONFIG_HTE
941
+
if (READ_ONCE(line->edflags) & GPIO_V2_LINE_FLAG_EVENT_CLOCK_HTE)
954
942
hte_ts_put(&line->hdesc);
943
+
#endif
955
944
956
945
cancel_delayed_work_sync(&line->work);
957
946
WRITE_ONCE(line->sw_debounced, 0);
958
-
WRITE_ONCE(line->eflags, 0);
947
+
WRITE_ONCE(line->edflags, 0);
959
948
if (line->desc)
960
949
WRITE_ONCE(line->desc->debounce_period_us, 0);
961
950
/* do not change line->level - see comment in debounced_value() */
···
965
950
966
951
static int edge_detector_setup(struct line *line,
967
952
struct gpio_v2_line_config *lc,
968
-
unsigned int line_idx,
969
-
u64 eflags, bool hte_req)
953
+
unsigned int line_idx, u64 edflags)
970
954
{
971
955
u32 debounce_period_us;
972
956
unsigned long irqflags = 0;
957
+
u64 eflags;
973
958
int irq, ret;
974
959
960
+
eflags = edflags & GPIO_V2_LINE_EDGE_FLAGS;
975
961
if (eflags && !kfifo_initialized(&line->req->events)) {
976
962
ret = kfifo_alloc(&line->req->events,
977
963
line->req->event_buffer_size, GFP_KERNEL);
978
964
if (ret)
979
965
return ret;
980
966
}
981
-
WRITE_ONCE(line->eflags, eflags);
982
967
if (gpio_v2_line_config_debounced(lc, line_idx)) {
983
968
debounce_period_us = gpio_v2_line_config_debounce_period(lc, line_idx);
984
-
ret = debounce_setup(line, debounce_period_us, hte_req);
969
+
ret = debounce_setup(line, debounce_period_us);
985
970
if (ret)
986
971
return ret;
987
972
WRITE_ONCE(line->desc->debounce_period_us, debounce_period_us);
···
991
976
if (!eflags || READ_ONCE(line->sw_debounced))
992
977
return 0;
993
978
994
-
if (hte_req)
995
-
return hte_edge_setup(line, eflags);
979
+
if (IS_ENABLED(CONFIG_HTE) &&
980
+
(edflags & GPIO_V2_LINE_FLAG_EVENT_CLOCK_HTE))
981
+
return hte_edge_setup(line, edflags);
996
982
997
983
irq = gpiod_to_irq(line->desc);
998
984
if (irq < 0)
···
1019
1003
1020
1004
static int edge_detector_update(struct line *line,
1021
1005
struct gpio_v2_line_config *lc,
1022
-
unsigned int line_idx,
1023
-
u64 flags, bool polarity_change,
1024
-
bool prev_hte_flag)
1006
+
unsigned int line_idx, u64 edflags)
1025
1007
{
1026
-
u64 eflags = flags & GPIO_V2_LINE_EDGE_FLAGS;
1008
+
u64 active_edflags = READ_ONCE(line->edflags);
1027
1009
unsigned int debounce_period_us =
1028
1010
gpio_v2_line_config_debounce_period(lc, line_idx);
1029
-
bool hte_change = (prev_hte_flag !=
1030
-
((flags & GPIO_V2_LINE_FLAG_EVENT_CLOCK_HTE) != 0));
1031
1011
1032
-
if ((READ_ONCE(line->eflags) == eflags) && !polarity_change &&
1033
-
(READ_ONCE(line->desc->debounce_period_us) == debounce_period_us)
1034
-
&& !hte_change)
1012
+
if ((active_edflags == edflags) &&
1013
+
(READ_ONCE(line->desc->debounce_period_us) == debounce_period_us))
1035
1014
return 0;
1036
1015
1037
1016
/* sw debounced and still will be...*/
1038
1017
if (debounce_period_us && READ_ONCE(line->sw_debounced)) {
1039
-
WRITE_ONCE(line->eflags, eflags);
1040
1018
WRITE_ONCE(line->desc->debounce_period_us, debounce_period_us);
1041
1019
return 0;
1042
1020
}
1043
1021
1044
1022
/* reconfiguring edge detection or sw debounce being disabled */
1045
-
if ((line->irq && !READ_ONCE(line->sw_debounced)) || prev_hte_flag ||
1023
+
if ((line->irq && !READ_ONCE(line->sw_debounced)) ||
1024
+
(active_edflags & GPIO_V2_LINE_FLAG_EVENT_CLOCK_HTE) ||
1046
1025
(!debounce_period_us && READ_ONCE(line->sw_debounced)))
1047
-
edge_detector_stop(line, prev_hte_flag);
1026
+
edge_detector_stop(line);
1048
1027
1049
-
return edge_detector_setup(line, lc, line_idx, eflags,
1050
-
flags & GPIO_V2_LINE_FLAG_EVENT_CLOCK_HTE);
1028
+
return edge_detector_setup(line, lc, line_idx, edflags);
1051
1029
}
1052
1030
1053
1031
static u64 gpio_v2_line_config_flags(struct gpio_v2_line_config *lc,
···
1077
1067
/* Return an error if an unknown flag is set */
1078
1068
if (flags & ~GPIO_V2_LINE_VALID_FLAGS)
1079
1069
return -EINVAL;
1070
+
1071
+
if (!IS_ENABLED(CONFIG_HTE) &&
1072
+
(flags & GPIO_V2_LINE_FLAG_EVENT_CLOCK_HTE))
1073
+
return -EOPNOTSUPP;
1074
+
1080
1075
/*
1081
1076
* Do not allow both INPUT and OUTPUT flags to be set as they are
1082
1077
* contradictory.
···
1091
1076
return -EINVAL;
1092
1077
1093
1078
/* Only allow one event clock source */
1094
-
if ((flags & GPIO_V2_LINE_FLAG_EVENT_CLOCK_REALTIME) &&
1079
+
if (IS_ENABLED(CONFIG_HTE) &&
1080
+
(flags & GPIO_V2_LINE_FLAG_EVENT_CLOCK_REALTIME) &&
1095
1081
(flags & GPIO_V2_LINE_FLAG_EVENT_CLOCK_HTE))
1096
1082
return -EINVAL;
1097
1083
···
1316
1300
struct gpio_v2_line_config *lc)
1317
1301
{
1318
1302
struct gpio_desc *desc;
1303
+
struct line *line;
1319
1304
unsigned int i;
1320
-
u64 flags;
1321
-
bool polarity_change;
1322
-
bool prev_hte_flag;
1305
+
u64 flags, edflags;
1323
1306
int ret;
1324
1307
1325
1308
for (i = 0; i < lr->num_lines; i++) {
1309
+
line = &lr->lines[i];
1326
1310
desc = lr->lines[i].desc;
1327
1311
flags = gpio_v2_line_config_flags(lc, i);
1328
-
polarity_change =
1329
-
(!!test_bit(FLAG_ACTIVE_LOW, &desc->flags) !=
1330
-
((flags & GPIO_V2_LINE_FLAG_ACTIVE_LOW) != 0));
1331
-
1332
-
prev_hte_flag = !!test_bit(FLAG_EVENT_CLOCK_HTE, &desc->flags);
1333
-
1334
1312
gpio_v2_line_config_flags_to_desc_flags(flags, &desc->flags);
1313
+
edflags = flags & GPIO_V2_LINE_EDGE_DETECTOR_FLAGS;
1335
1314
/*
1336
1315
* Lines have to be requested explicitly for input
1337
1316
* or output, else the line will be treated "as is".
···
1334
1323
if (flags & GPIO_V2_LINE_FLAG_OUTPUT) {
1335
1324
int val = gpio_v2_line_config_output_value(lc, i);
1336
1325
1337
-
edge_detector_stop(&lr->lines[i], prev_hte_flag);
1326
+
edge_detector_stop(line);
1338
1327
ret = gpiod_direction_output(desc, val);
1339
1328
if (ret)
1340
1329
return ret;
···
1343
1332
if (ret)
1344
1333
return ret;
1345
1334
1346
-
ret = edge_detector_update(&lr->lines[i], lc, i,
1347
-
flags, polarity_change, prev_hte_flag);
1335
+
ret = edge_detector_update(line, lc, i, edflags);
1348
1336
if (ret)
1349
1337
return ret;
1350
1338
}
1339
+
1340
+
WRITE_ONCE(line->edflags, edflags);
1351
1341
1352
1342
blocking_notifier_call_chain(&desc->gdev->notifier,
1353
1343
GPIO_V2_LINE_CHANGED_CONFIG,
···
1476
1464
static void linereq_free(struct linereq *lr)
1477
1465
{
1478
1466
unsigned int i;
1479
-
bool hte = false;
1480
1467
1481
1468
for (i = 0; i < lr->num_lines; i++) {
1482
-
if (lr->lines[i].desc)
1483
-
hte = !!test_bit(FLAG_EVENT_CLOCK_HTE,
1484
-
&lr->lines[i].desc->flags);
1485
-
edge_detector_stop(&lr->lines[i], hte);
1486
-
if (lr->lines[i].desc)
1469
+
if (lr->lines[i].desc) {
1470
+
edge_detector_stop(&lr->lines[i]);
1487
1471
gpiod_free(lr->lines[i].desc);
1472
+
}
1488
1473
}
1489
1474
kfifo_free(&lr->events);
1490
1475
kfree(lr->label);
···
1515
1506
struct gpio_v2_line_config *lc;
1516
1507
struct linereq *lr;
1517
1508
struct file *file;
1518
-
u64 flags;
1509
+
u64 flags, edflags;
1519
1510
unsigned int i;
1520
1511
int fd, ret;
1521
1512
···
1589
1580
if (ret < 0)
1590
1581
goto out_free_linereq;
1591
1582
1583
+
edflags = flags & GPIO_V2_LINE_EDGE_DETECTOR_FLAGS;
1592
1584
/*
1593
1585
* Lines have to be requested explicitly for input
1594
1586
* or output, else the line will be treated "as is".
···
1606
1596
goto out_free_linereq;
1607
1597
1608
1598
ret = edge_detector_setup(&lr->lines[i], lc, i,
1609
-
flags & GPIO_V2_LINE_EDGE_FLAGS,
1610
-
flags & GPIO_V2_LINE_FLAG_EVENT_CLOCK_HTE);
1599
+
edflags);
1611
1600
if (ret)
1612
1601
goto out_free_linereq;
1613
1602
}
1603
+
1604
+
lr->lines[i].edflags = edflags;
1614
1605
1615
1606
blocking_notifier_call_chain(&desc->gdev->notifier,
1616
1607
GPIO_V2_LINE_CHANGED_REQUESTED, desc);
-32
drivers/gpio/gpiolib-devres.c
-32
drivers/gpio/gpiolib-devres.c
···
375
375
}
376
376
EXPORT_SYMBOL_GPL(devm_gpiod_put_array);
377
377
378
-
379
-
380
-
381
378
static void devm_gpio_release(struct device *dev, void *res)
382
379
{
383
380
unsigned *gpio = res;
384
381
385
382
gpio_free(*gpio);
386
-
}
387
-
388
-
static int devm_gpio_match(struct device *dev, void *res, void *data)
389
-
{
390
-
unsigned *this = res, *gpio = data;
391
-
392
-
return *this == *gpio;
393
383
}
394
384
395
385
/**
···
392
402
* same arguments and performs the same function as
393
403
* gpio_request(). GPIOs requested with this function will be
394
404
* automatically freed on driver detach.
395
-
*
396
-
* If an GPIO allocated with this function needs to be freed
397
-
* separately, devm_gpio_free() must be used.
398
405
*/
399
-
400
406
int devm_gpio_request(struct device *dev, unsigned gpio, const char *label)
401
407
{
402
408
unsigned *dr;
···
444
458
return 0;
445
459
}
446
460
EXPORT_SYMBOL_GPL(devm_gpio_request_one);
447
-
448
-
/**
449
-
* devm_gpio_free - free a GPIO
450
-
* @dev: device to free GPIO for
451
-
* @gpio: GPIO to free
452
-
*
453
-
* Except for the extra @dev argument, this function takes the
454
-
* same arguments and performs the same function as gpio_free().
455
-
* This function instead of gpio_free() should be used to manually
456
-
* free GPIOs allocated with devm_gpio_request().
457
-
*/
458
-
void devm_gpio_free(struct device *dev, unsigned int gpio)
459
-
{
460
-
461
-
WARN_ON(devres_release(dev, devm_gpio_release, devm_gpio_match,
462
-
&gpio));
463
-
}
464
-
EXPORT_SYMBOL_GPL(devm_gpio_free);
465
461
466
462
static void devm_gpio_chip_release(void *data)
467
463
{
+11
-2
drivers/gpio/gpiolib-of.c
+11
-2
drivers/gpio/gpiolib-of.c
···
354
354
if (flags & OF_GPIO_PULL_DOWN)
355
355
lflags |= GPIO_PULL_DOWN;
356
356
357
+
if (flags & OF_GPIO_PULL_DISABLE)
358
+
lflags |= GPIO_PULL_DISABLE;
359
+
357
360
ret = gpiod_configure_flags(desc, propname, lflags, dflags);
358
361
if (ret < 0) {
359
362
gpiod_put(desc);
···
559
556
*flags |= GPIO_PULL_UP;
560
557
if (of_flags & OF_GPIO_PULL_DOWN)
561
558
*flags |= GPIO_PULL_DOWN;
559
+
if (of_flags & OF_GPIO_PULL_DISABLE)
560
+
*flags |= GPIO_PULL_DISABLE;
562
561
563
562
return desc;
564
563
}
···
626
621
*lflags |= GPIO_PULL_UP;
627
622
if (xlate_flags & OF_GPIO_PULL_DOWN)
628
623
*lflags |= GPIO_PULL_DOWN;
624
+
if (xlate_flags & OF_GPIO_PULL_DISABLE)
625
+
*lflags |= GPIO_PULL_DISABLE;
629
626
630
627
if (of_property_read_bool(np, "input"))
631
628
*dflags |= GPIOD_IN;
···
727
720
728
721
static int of_gpiochip_match_node(struct gpio_chip *chip, void *data)
729
722
{
730
-
return chip->gpiodev->dev.of_node == data;
723
+
return device_match_of_node(&chip->gpiodev->dev, data);
731
724
}
732
725
733
726
static struct gpio_chip *of_find_gpiochip_by_node(struct device_node *np)
···
867
860
if (mm_gc->save_regs)
868
861
mm_gc->save_regs(mm_gc);
869
862
870
-
mm_gc->gc.of_node = np;
863
+
of_node_put(mm_gc->gc.of_node);
864
+
mm_gc->gc.of_node = of_node_get(np);
871
865
872
866
ret = gpiochip_add_data(gc, data);
873
867
if (ret)
···
876
868
877
869
return 0;
878
870
err2:
871
+
of_node_put(np);
879
872
iounmap(mm_gc->regs);
880
873
err1:
881
874
kfree(gc->label);
+6
-2
drivers/gpio/gpiolib.c
+6
-2
drivers/gpio/gpiolib.c
···
3942
3942
if (lflags & GPIO_OPEN_SOURCE)
3943
3943
set_bit(FLAG_OPEN_SOURCE, &desc->flags);
3944
3944
3945
-
if ((lflags & GPIO_PULL_UP) && (lflags & GPIO_PULL_DOWN)) {
3945
+
if (((lflags & GPIO_PULL_UP) && (lflags & GPIO_PULL_DOWN)) ||
3946
+
((lflags & GPIO_PULL_UP) && (lflags & GPIO_PULL_DISABLE)) ||
3947
+
((lflags & GPIO_PULL_DOWN) && (lflags & GPIO_PULL_DISABLE))) {
3946
3948
gpiod_err(desc,
3947
-
"both pull-up and pull-down enabled, invalid configuration\n");
3949
+
"multiple pull-up, pull-down or pull-disable enabled, invalid configuration\n");
3948
3950
return -EINVAL;
3949
3951
}
3950
3952
···
3954
3952
set_bit(FLAG_PULL_UP, &desc->flags);
3955
3953
else if (lflags & GPIO_PULL_DOWN)
3956
3954
set_bit(FLAG_PULL_DOWN, &desc->flags);
3955
+
else if (lflags & GPIO_PULL_DISABLE)
3956
+
set_bit(FLAG_BIAS_DISABLE, &desc->flags);
3957
3957
3958
3958
ret = gpiod_set_transitory(desc, (lflags & GPIO_TRANSITORY));
3959
3959
if (ret < 0)
+2
-4
drivers/mfd/ucb1400_core.c
+2
-4
drivers/mfd/ucb1400_core.c
···
72
72
73
73
/* GPIO */
74
74
ucb_gpio.ac97 = ac97;
75
-
if (pdata) {
76
-
ucb_gpio.gpio_setup = pdata->gpio_setup;
77
-
ucb_gpio.gpio_teardown = pdata->gpio_teardown;
75
+
if (pdata)
78
76
ucb_gpio.gpio_offset = pdata->gpio_offset;
79
-
}
77
+
80
78
ucb->ucb1400_gpio = platform_device_alloc("ucb1400_gpio", -1);
81
79
if (!ucb->ucb1400_gpio) {
82
80
err = -ENOMEM;
+3
include/dt-bindings/gpio/gpio.h
+3
include/dt-bindings/gpio/gpio.h
-6
include/linux/gpio.h
-6
include/linux/gpio.h
···
95
95
int devm_gpio_request(struct device *dev, unsigned gpio, const char *label);
96
96
int devm_gpio_request_one(struct device *dev, unsigned gpio,
97
97
unsigned long flags, const char *label);
98
-
void devm_gpio_free(struct device *dev, unsigned int gpio);
99
98
100
99
#else /* ! CONFIG_GPIOLIB */
101
100
···
237
238
{
238
239
WARN_ON(1);
239
240
return -EINVAL;
240
-
}
241
-
242
-
static inline void devm_gpio_free(struct device *dev, unsigned int gpio)
243
-
{
244
-
WARN_ON(1);
245
241
}
246
242
247
243
#endif /* ! CONFIG_GPIOLIB */
+1
include/linux/gpio/machine.h
+1
include/linux/gpio/machine.h
-2
include/linux/mfd/twl.h
-2
include/linux/mfd/twl.h
+1
include/linux/of_gpio.h
+1
include/linux/of_gpio.h