Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'for-7.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/pateldipen1984/linux
Pull hte updates from Dipen Patel:
- Add tegra264 HTE driver and dt binding support
- Remove tegra194 SoC Kconfig dependency
- Replace use of system_unbound_wq with system_dfl_wq
* tag 'for-7.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/pateldipen1984/linux:
hte: tegra194: Add Tegra264 GTE support
dt-bindings: timestamp: Add Tegra264 support
hte: tegra194: remove Kconfig dependency on Tegra194 SoC
hte: replace use of system_unbound_wq with system_dfl_wq
+146
-9
+14
Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml
+14
Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml
···
25
25
- nvidia,tegra194-gte-lic
26
26
- nvidia,tegra234-gte-aon
27
27
- nvidia,tegra234-gte-lic
28
+
- nvidia,tegra264-gte-aon
29
+
- nvidia,tegra264-gte-lic
28
30
29
31
reg:
30
32
maxItems: 1
···
114
112
contains:
115
113
enum:
116
114
- nvidia,tegra234-gte-aon
115
+
- nvidia,tegra264-gte-aon
117
116
then:
118
117
required:
119
118
- nvidia,gpio-controller
119
+
120
+
- if:
121
+
properties:
122
+
compatible:
123
+
contains:
124
+
enum:
125
+
- nvidia,tegra264-gte-aon
126
+
- nvidia,tegra264-gte-lic
127
+
then:
128
+
properties:
129
+
nvidia,slices: false
120
130
121
131
additionalProperties: false
122
132
+3
-3
drivers/hte/Kconfig
+3
-3
drivers/hte/Kconfig
···
16
16
17
17
config HTE_TEGRA194
18
18
tristate "NVIDIA Tegra194 HTE Support"
19
-
depends on (ARCH_TEGRA_194_SOC || COMPILE_TEST)
19
+
depends on (ARCH_TEGRA || COMPILE_TEST)
20
20
depends on GPIOLIB
21
21
help
22
22
Enable this option for integrated hardware timestamping engine also
23
23
known as generic timestamping engine (GTE) support on NVIDIA Tegra194
24
-
systems-on-chip. The driver supports 352 LIC IRQs and 39 AON GPIOs
25
-
lines for timestamping in realtime.
24
+
and later systems-on-chip. The driver supports 352 LIC IRQs and 39
25
+
AON GPIOs lines for timestamping in realtime.
26
26
27
27
config HTE_TEGRA194_TEST
28
28
tristate "NVIDIA Tegra194 HTE Test"
+128
-5
drivers/hte/hte-tegra194.c
+128
-5
drivers/hte/hte-tegra194.c
···
20
20
21
21
#define HTE_SUSPEND 0
22
22
23
-
/* HTE source clock TSC is 31.25MHz */
23
+
/* HTE source clock TSC is 1GHz for T264 and 31.25MHz for others */
24
24
#define HTE_TS_CLK_RATE_HZ 31250000ULL
25
+
#define HTE_TS_CLK_RATE_1G 1000000000ULL
25
26
#define HTE_CLK_RATE_NS 32
26
-
#define HTE_TS_NS_SHIFT __builtin_ctz(HTE_CLK_RATE_NS)
27
+
#define HTE_CLK_RATE_NS_1G 1
27
28
28
29
#define NV_AON_SLICE_INVALID -1
29
30
#define NV_LINES_IN_SLICE 32
···
121
120
u32 slices;
122
121
u32 map_sz;
123
122
u32 sec_map_sz;
123
+
u64 tsc_clkrate_hz;
124
+
u32 tsc_clkrate_ns;
124
125
const struct tegra_hte_line_mapped *map;
125
126
const struct tegra_hte_line_mapped *sec_map;
126
127
};
···
320
317
[40] = {2, NV_AON_HTE_SLICE2_IRQ_GPIO_23},
321
318
};
322
319
320
+
static const struct tegra_hte_line_mapped tegra264_aon_gpio_map[] = {
321
+
/* gpio, slice, bit_index */
322
+
/* AA port */
323
+
[0] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_29},
324
+
[1] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_28},
325
+
[2] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_27},
326
+
[3] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_26},
327
+
[4] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_25},
328
+
[5] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_24},
329
+
[6] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_23},
330
+
[7] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_22},
331
+
/* BB port */
332
+
[8] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_21},
333
+
[9] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_20},
334
+
/* CC port */
335
+
[10] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_19},
336
+
[11] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_18},
337
+
[12] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_17},
338
+
[13] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_16},
339
+
[14] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_15},
340
+
[15] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_14},
341
+
[16] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_13},
342
+
[17] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_12},
343
+
/* DD port */
344
+
[18] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_11},
345
+
[19] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_10},
346
+
[20] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_9},
347
+
[21] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_8},
348
+
[22] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_7},
349
+
[23] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_6},
350
+
[24] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_5},
351
+
[25] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_4},
352
+
/* EE port */
353
+
[26] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_3},
354
+
[27] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_2},
355
+
[28] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_1},
356
+
[29] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_0},
357
+
};
358
+
359
+
static const struct tegra_hte_line_mapped tegra264_aon_gpio_sec_map[] = {
360
+
/* gpio, slice, bit_index */
361
+
/* AA port */
362
+
[0] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_29},
363
+
[1] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_28},
364
+
[2] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_27},
365
+
[3] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_26},
366
+
[4] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_25},
367
+
[5] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_24},
368
+
[6] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_23},
369
+
[7] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_22},
370
+
/* BB port */
371
+
[8] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_21},
372
+
[9] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_20},
373
+
[10] = {NV_AON_SLICE_INVALID, 0},
374
+
[11] = {NV_AON_SLICE_INVALID, 0},
375
+
[12] = {NV_AON_SLICE_INVALID, 0},
376
+
[13] = {NV_AON_SLICE_INVALID, 0},
377
+
[14] = {NV_AON_SLICE_INVALID, 0},
378
+
[15] = {NV_AON_SLICE_INVALID, 0},
379
+
/* CC port */
380
+
[16] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_19},
381
+
[17] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_18},
382
+
[18] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_17},
383
+
[19] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_16},
384
+
[20] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_15},
385
+
[21] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_14},
386
+
[22] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_13},
387
+
[23] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_12},
388
+
/* DD port */
389
+
[24] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_11},
390
+
[25] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_10},
391
+
[26] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_9},
392
+
[27] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_8},
393
+
[28] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_7},
394
+
[29] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_6},
395
+
[30] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_5},
396
+
[31] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_4},
397
+
/* EE port */
398
+
[32] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_3},
399
+
[33] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_2},
400
+
[34] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_1},
401
+
[35] = {3, NV_AON_HTE_SLICE2_IRQ_GPIO_0},
402
+
[36] = {NV_AON_SLICE_INVALID, 0},
403
+
[37] = {NV_AON_SLICE_INVALID, 0},
404
+
[38] = {NV_AON_SLICE_INVALID, 0},
405
+
[39] = {NV_AON_SLICE_INVALID, 0},
406
+
};
407
+
323
408
static const struct tegra_hte_data t194_aon_hte = {
324
409
.map_sz = ARRAY_SIZE(tegra194_aon_gpio_map),
325
410
.map = tegra194_aon_gpio_map,
···
415
324
.sec_map = tegra194_aon_gpio_sec_map,
416
325
.type = HTE_TEGRA_TYPE_GPIO,
417
326
.slices = 3,
327
+
.tsc_clkrate_hz = HTE_TS_CLK_RATE_HZ,
328
+
.tsc_clkrate_ns = HTE_CLK_RATE_NS,
418
329
};
419
330
420
331
static const struct tegra_hte_data t234_aon_hte = {
···
426
333
.sec_map = tegra234_aon_gpio_sec_map,
427
334
.type = HTE_TEGRA_TYPE_GPIO,
428
335
.slices = 3,
336
+
.tsc_clkrate_hz = HTE_TS_CLK_RATE_HZ,
337
+
.tsc_clkrate_ns = HTE_CLK_RATE_NS,
338
+
};
339
+
340
+
static const struct tegra_hte_data t264_aon_hte = {
341
+
.map_sz = ARRAY_SIZE(tegra264_aon_gpio_map),
342
+
.map = tegra264_aon_gpio_map,
343
+
.sec_map_sz = ARRAY_SIZE(tegra264_aon_gpio_sec_map),
344
+
.sec_map = tegra264_aon_gpio_sec_map,
345
+
.type = HTE_TEGRA_TYPE_GPIO,
346
+
.slices = 4,
347
+
.tsc_clkrate_hz = HTE_TS_CLK_RATE_1G,
348
+
.tsc_clkrate_ns = HTE_CLK_RATE_NS_1G,
429
349
};
430
350
431
351
static const struct tegra_hte_data t194_lic_hte = {
···
446
340
.map = NULL,
447
341
.type = HTE_TEGRA_TYPE_LIC,
448
342
.slices = 11,
343
+
.tsc_clkrate_hz = HTE_TS_CLK_RATE_HZ,
344
+
.tsc_clkrate_ns = HTE_CLK_RATE_NS,
449
345
};
450
346
451
347
static const struct tegra_hte_data t234_lic_hte = {
···
455
347
.map = NULL,
456
348
.type = HTE_TEGRA_TYPE_LIC,
457
349
.slices = 17,
350
+
.tsc_clkrate_hz = HTE_TS_CLK_RATE_HZ,
351
+
.tsc_clkrate_ns = HTE_CLK_RATE_NS,
352
+
};
353
+
354
+
static const struct tegra_hte_data t264_lic_hte = {
355
+
.map_sz = 0,
356
+
.map = NULL,
357
+
.type = HTE_TEGRA_TYPE_LIC,
358
+
.slices = 10,
359
+
.tsc_clkrate_hz = HTE_TS_CLK_RATE_1G,
360
+
.tsc_clkrate_ns = HTE_CLK_RATE_NS_1G,
458
361
};
459
362
460
363
static inline u32 tegra_hte_readl(struct tegra_hte_soc *hte, u32 reg)
···
693
574
static int tegra_hte_clk_src_info(struct hte_chip *chip,
694
575
struct hte_clk_info *ci)
695
576
{
696
-
(void)chip;
577
+
struct tegra_hte_soc *hte_dev = chip->data;
697
578
698
579
if (!ci)
699
580
return -EINVAL;
700
581
701
-
ci->hz = HTE_TS_CLK_RATE_HZ;
582
+
ci->hz = hte_dev->prov_data->tsc_clkrate_hz;
702
583
ci->type = CLOCK_MONOTONIC;
703
584
704
585
return 0;
···
721
602
{
722
603
u32 tsh, tsl, src, pv, cv, acv, slice, bit_index, line_id;
723
604
u64 tsc;
605
+
u8 tsc_ns_shift;
724
606
struct hte_ts_data el;
725
607
608
+
tsc_ns_shift = __builtin_ctz(gs->prov_data->tsc_clkrate_ns);
726
609
while ((tegra_hte_readl(gs, HTE_TESTATUS) >>
727
610
HTE_TESTATUS_OCCUPANCY_SHIFT) &
728
611
HTE_TESTATUS_OCCUPANCY_MASK) {
···
742
621
while (acv) {
743
622
bit_index = __builtin_ctz(acv);
744
623
line_id = bit_index + (slice << 5);
745
-
el.tsc = tsc << HTE_TS_NS_SHIFT;
624
+
el.tsc = tsc << tsc_ns_shift;
746
625
el.raw_level = tegra_hte_get_level(gs, line_id);
747
626
hte_push_ts_ns(gs->chip, line_id, &el);
748
627
acv &= ~BIT(bit_index);
···
777
656
{ .compatible = "nvidia,tegra194-gte-aon", .data = &t194_aon_hte},
778
657
{ .compatible = "nvidia,tegra234-gte-lic", .data = &t234_lic_hte},
779
658
{ .compatible = "nvidia,tegra234-gte-aon", .data = &t234_aon_hte},
659
+
{ .compatible = "nvidia,tegra264-gte-lic", .data = &t264_lic_hte},
660
+
{ .compatible = "nvidia,tegra264-gte-aon", .data = &t264_aon_hte},
780
661
{ }
781
662
};
782
663
MODULE_DEVICE_TABLE(of, tegra_hte_of_match);