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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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linux
Merge branch 'net-stmmac-pcs-preparation'
Russell King says:
====================
net: stmmac: pcs preparation
These three patches prepare for the PCS changes, which, subject
to Qualcomm testing, should be coming in the next cycle.
====================
Link: https://patch.msgid.link/aXyRlFw7ZuhRPiKo@shell.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+44
-31
-2
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
-2
drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c
+15
-3
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+15
-3
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
···
906
906
/* Refresh the MAC-specific capabilities */
907
907
stmmac_mac_update_caps(priv);
908
908
909
+
if (priv->hw_cap_support && !priv->dma_cap.half_duplex)
910
+
priv->hw->link.caps &= ~(MAC_1000HD | MAC_100HD | MAC_10HD);
911
+
909
912
config->mac_capabilities = priv->hw->link.caps;
910
913
911
914
if (priv->plat->max_speed)
···
3159
3156
phy_intf_sel = PHY_INTF_SEL_GMII_MII;
3160
3157
else if (phy_interface_mode_is_rgmii(interface))
3161
3158
phy_intf_sel = PHY_INTF_SEL_RGMII;
3162
-
else if (interface == PHY_INTERFACE_MODE_SGMII)
3163
-
phy_intf_sel = PHY_INTF_SEL_SGMII;
3164
3159
else if (interface == PHY_INTERFACE_MODE_RMII)
3165
3160
phy_intf_sel = PHY_INTF_SEL_RMII;
3166
3161
else if (interface == PHY_INTERFACE_MODE_REVMII)
···
3172
3171
{
3173
3172
struct plat_stmmacenet_data *plat_dat = priv->plat;
3174
3173
phy_interface_t interface;
3174
+
struct phylink_pcs *pcs;
3175
3175
int phy_intf_sel, ret;
3176
3176
3177
3177
if (!plat_dat->set_phy_intf_sel)
3178
3178
return 0;
3179
3179
3180
3180
interface = plat_dat->phy_interface;
3181
-
phy_intf_sel = stmmac_get_phy_intf_sel(interface);
3181
+
3182
+
/* Check whether this mode uses a PCS */
3183
+
pcs = stmmac_mac_select_pcs(&priv->phylink_config, interface);
3184
+
if (priv->integrated_pcs && pcs == &priv->integrated_pcs->pcs) {
3185
+
/* Request the phy_intf_sel from the integrated PCS */
3186
+
phy_intf_sel = stmmac_integrated_pcs_get_phy_intf_sel(pcs,
3187
+
interface);
3188
+
} else {
3189
+
phy_intf_sel = stmmac_get_phy_intf_sel(interface);
3190
+
}
3191
+
3182
3192
if (phy_intf_sel < 0) {
3183
3193
netdev_err(priv->dev,
3184
3194
"failed to get phy_intf_sel for %s: %pe\n",
+27
-4
drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
+27
-4
drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.c
···
2
2
#include "stmmac.h"
3
3
#include "stmmac_pcs.h"
4
4
5
+
/*
6
+
* GMAC_AN_STATUS is equivalent to MII_BMSR
7
+
* GMAC_ANE_ADV is equivalent to 802.3z MII_ADVERTISE
8
+
* GMAC_ANE_LPA is equivalent to 802.3z MII_LPA
9
+
* GMAC_ANE_EXP is equivalent to MII_EXPANSION
10
+
* GMAC_TBI is equivalent to MII_ESTATUS
11
+
*
12
+
* ADV, LPA and EXP are only available for the TBI and RTBI modes.
13
+
*/
14
+
#define GMAC_AN_STATUS 0x04 /* AN status */
15
+
#define GMAC_ANE_ADV 0x08 /* ANE Advertisement */
16
+
#define GMAC_ANE_LPA 0x0c /* ANE link partener ability */
17
+
#define GMAC_TBI 0x14 /* TBI extend status */
18
+
5
19
static int dwmac_integrated_pcs_enable(struct phylink_pcs *pcs)
6
20
{
7
21
struct stmmac_pcs *spcs = phylink_pcs_to_stmmac_pcs(pcs);
···
63
49
struct stmmac_extra_stats *x)
64
50
{
65
51
struct stmmac_pcs *spcs = priv->integrated_pcs;
66
-
u32 val = readl(spcs->base + GMAC_AN_STATUS(0));
52
+
u32 val = readl(spcs->base + GMAC_AN_STATUS);
67
53
68
54
if (status & PCS_ANE_IRQ) {
69
55
x->irq_pcs_ane_n++;
70
-
if (val & GMAC_AN_STATUS_ANC)
56
+
if (val & BMSR_ANEGCOMPLETE)
71
57
dev_info(priv->device,
72
58
"PCS ANE process completed\n");
73
59
}
···
75
61
if (status & PCS_LINK_IRQ) {
76
62
x->irq_pcs_link_n++;
77
63
dev_info(priv->device, "PCS Link %s\n",
78
-
val & GMAC_AN_STATUS_LS ? "Up" : "Down");
64
+
val & BMSR_LSTATUS ? "Up" : "Down");
79
65
80
-
phylink_pcs_change(&spcs->pcs, val & GMAC_AN_STATUS_LS);
66
+
phylink_pcs_change(&spcs->pcs, val & BMSR_LSTATUS);
81
67
}
68
+
}
69
+
70
+
int stmmac_integrated_pcs_get_phy_intf_sel(struct phylink_pcs *pcs,
71
+
phy_interface_t interface)
72
+
{
73
+
if (interface == PHY_INTERFACE_MODE_SGMII)
74
+
return PHY_INTF_SEL_SGMII;
75
+
76
+
return -EINVAL;
82
77
}
83
78
84
79
int stmmac_integrated_pcs_init(struct stmmac_priv *priv, unsigned int offset,
+2
-22
drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
+2
-22
drivers/net/ethernet/stmicro/stmmac/stmmac_pcs.h
···
16
16
17
17
/* PCS registers (AN/TBI/SGMII/RGMII) offsets */
18
18
#define GMAC_AN_CTRL(x) (x) /* AN control */
19
-
#define GMAC_AN_STATUS(x) (x + 0x4) /* AN status */
20
-
21
-
/* ADV, LPA and EXP are only available for the TBI and RTBI interfaces */
22
-
#define GMAC_ANE_ADV(x) (x + 0x8) /* ANE Advertisement */
23
-
#define GMAC_ANE_LPA(x) (x + 0xc) /* ANE link partener ability */
24
-
#define GMAC_ANE_EXP(x) (x + 0x10) /* ANE expansion */
25
-
#define GMAC_TBI(x) (x + 0x14) /* TBI extend status */
26
19
27
20
/* AN Configuration defines */
28
21
#define GMAC_AN_CTRL_RAN BIT_U32(9) /* Restart Auto-Negotiation */
···
24
31
#define GMAC_AN_CTRL_ECD BIT_U32(16) /* Enable Comma Detect */
25
32
#define GMAC_AN_CTRL_LR BIT_U32(17) /* Lock to Reference */
26
33
#define GMAC_AN_CTRL_SGMRAL BIT_U32(18) /* SGMII RAL Control */
27
-
28
-
/* AN Status defines */
29
-
#define GMAC_AN_STATUS_LS BIT_U32(2) /* Link Status 0:down 1:up */
30
-
#define GMAC_AN_STATUS_ANA BIT_U32(3) /* Auto-Negotiation Ability */
31
-
#define GMAC_AN_STATUS_ANC BIT_U32(5) /* Auto-Negotiation Complete */
32
-
#define GMAC_AN_STATUS_ES BIT_U32(8) /* Extended Status */
33
-
34
-
/* ADV and LPA defines */
35
-
#define GMAC_ANE_FD BIT_U32(5)
36
-
#define GMAC_ANE_HD BIT_U32(6)
37
-
#define GMAC_ANE_PSE GENMASK_U32(8, 7)
38
-
#define GMAC_ANE_PSE_SHIFT 7
39
-
#define GMAC_ANE_RFE GENMASK_U32(13, 12)
40
-
#define GMAC_ANE_RFE_SHIFT 12
41
-
#define GMAC_ANE_ACK BIT_U32(14)
42
34
43
35
struct stmmac_priv;
44
36
···
42
64
43
65
void stmmac_integrated_pcs_irq(struct stmmac_priv *priv, u32 status,
44
66
struct stmmac_extra_stats *x);
67
+
int stmmac_integrated_pcs_get_phy_intf_sel(struct phylink_pcs *pcs,
68
+
phy_interface_t interface);
45
69
int stmmac_integrated_pcs_init(struct stmmac_priv *priv, unsigned int offset,
46
70
u32 int_mask);
47
71