Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
LoongArch: Add detection for SC.Q support
Check the CPUCFG2_SCQ bit to determine if the current CPU supports the
SC.Q instruction.
Reviewed-by: Hengqi Chen <hengqi.chen@gmail.com>
Tested-by: Hengqi Chen <hengqi.chen@gmail.com>
Co-developed-by: Yangyang Lian <lianyangyang@kylinos.cn>
Signed-off-by: Yangyang Lian <lianyangyang@kylinos.cn>
Signed-off-by: George Guo <guodongtai@kylinos.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
authored by
George Guo
and committed by
Huacai Chen
48543c42
07d5798a
+39
-30
+1
arch/loongarch/include/asm/cpu-features.h
+1
arch/loongarch/include/asm/cpu-features.h
···
35
35
*/
36
36
#define cpu_has_cpucfg cpu_opt(LOONGARCH_CPU_CPUCFG)
37
37
#define cpu_has_lam cpu_opt(LOONGARCH_CPU_LAM)
38
+
#define cpu_has_scq cpu_opt(LOONGARCH_CPU_SCQ)
38
39
#define cpu_has_ual cpu_opt(LOONGARCH_CPU_UAL)
39
40
#define cpu_has_fpu cpu_opt(LOONGARCH_CPU_FPU)
40
41
#define cpu_has_lsx cpu_opt(LOONGARCH_CPU_LSX)
+32
-30
arch/loongarch/include/asm/cpu.h
+32
-30
arch/loongarch/include/asm/cpu.h
···
95
95
*/
96
96
#define CPU_FEATURE_CPUCFG 0 /* CPU has CPUCFG */
97
97
#define CPU_FEATURE_LAM 1 /* CPU has Atomic instructions */
98
-
#define CPU_FEATURE_UAL 2 /* CPU supports unaligned access */
99
-
#define CPU_FEATURE_FPU 3 /* CPU has FPU */
100
-
#define CPU_FEATURE_LSX 4 /* CPU has LSX (128-bit SIMD) */
101
-
#define CPU_FEATURE_LASX 5 /* CPU has LASX (256-bit SIMD) */
102
-
#define CPU_FEATURE_CRC32 6 /* CPU has CRC32 instructions */
103
-
#define CPU_FEATURE_COMPLEX 7 /* CPU has Complex instructions */
104
-
#define CPU_FEATURE_CRYPTO 8 /* CPU has Crypto instructions */
105
-
#define CPU_FEATURE_LVZ 9 /* CPU has Virtualization extension */
106
-
#define CPU_FEATURE_LBT_X86 10 /* CPU has X86 Binary Translation */
107
-
#define CPU_FEATURE_LBT_ARM 11 /* CPU has ARM Binary Translation */
108
-
#define CPU_FEATURE_LBT_MIPS 12 /* CPU has MIPS Binary Translation */
109
-
#define CPU_FEATURE_TLB 13 /* CPU has TLB */
110
-
#define CPU_FEATURE_CSR 14 /* CPU has CSR */
111
-
#define CPU_FEATURE_IOCSR 15 /* CPU has IOCSR */
112
-
#define CPU_FEATURE_WATCH 16 /* CPU has watchpoint registers */
113
-
#define CPU_FEATURE_VINT 17 /* CPU has vectored interrupts */
114
-
#define CPU_FEATURE_CSRIPI 18 /* CPU has CSR-IPI */
115
-
#define CPU_FEATURE_EXTIOI 19 /* CPU has EXT-IOI */
116
-
#define CPU_FEATURE_PREFETCH 20 /* CPU has prefetch instructions */
117
-
#define CPU_FEATURE_PMP 21 /* CPU has perfermance counter */
118
-
#define CPU_FEATURE_SCALEFREQ 22 /* CPU supports cpufreq scaling */
119
-
#define CPU_FEATURE_FLATMODE 23 /* CPU has flat mode */
120
-
#define CPU_FEATURE_EIODECODE 24 /* CPU has EXTIOI interrupt pin decode mode */
121
-
#define CPU_FEATURE_GUESTID 25 /* CPU has GuestID feature */
122
-
#define CPU_FEATURE_HYPERVISOR 26 /* CPU has hypervisor (running in VM) */
123
-
#define CPU_FEATURE_PTW 27 /* CPU has hardware page table walker */
124
-
#define CPU_FEATURE_LSPW 28 /* CPU has LSPW (lddir/ldpte instructions) */
125
-
#define CPU_FEATURE_MSGINT 29 /* CPU has MSG interrupt */
126
-
#define CPU_FEATURE_AVECINT 30 /* CPU has AVEC interrupt */
127
-
#define CPU_FEATURE_REDIRECTINT 31 /* CPU has interrupt remapping */
98
+
#define CPU_FEATURE_SCQ 2 /* CPU has SC.Q instruction */
99
+
#define CPU_FEATURE_UAL 3 /* CPU supports unaligned access */
100
+
#define CPU_FEATURE_FPU 4 /* CPU has FPU */
101
+
#define CPU_FEATURE_LSX 5 /* CPU has LSX (128-bit SIMD) */
102
+
#define CPU_FEATURE_LASX 6 /* CPU has LASX (256-bit SIMD) */
103
+
#define CPU_FEATURE_CRC32 7 /* CPU has CRC32 instructions */
104
+
#define CPU_FEATURE_COMPLEX 8 /* CPU has Complex instructions */
105
+
#define CPU_FEATURE_CRYPTO 9 /* CPU has Crypto instructions */
106
+
#define CPU_FEATURE_LVZ 10 /* CPU has Virtualization extension */
107
+
#define CPU_FEATURE_LBT_X86 11 /* CPU has X86 Binary Translation */
108
+
#define CPU_FEATURE_LBT_ARM 12 /* CPU has ARM Binary Translation */
109
+
#define CPU_FEATURE_LBT_MIPS 13 /* CPU has MIPS Binary Translation */
110
+
#define CPU_FEATURE_TLB 14 /* CPU has TLB */
111
+
#define CPU_FEATURE_CSR 15 /* CPU has CSR */
112
+
#define CPU_FEATURE_IOCSR 16 /* CPU has IOCSR */
113
+
#define CPU_FEATURE_WATCH 17 /* CPU has watchpoint registers */
114
+
#define CPU_FEATURE_VINT 18 /* CPU has vectored interrupts */
115
+
#define CPU_FEATURE_CSRIPI 19 /* CPU has CSR-IPI */
116
+
#define CPU_FEATURE_EXTIOI 20 /* CPU has EXT-IOI */
117
+
#define CPU_FEATURE_PREFETCH 21 /* CPU has prefetch instructions */
118
+
#define CPU_FEATURE_PMP 22 /* CPU has perfermance counter */
119
+
#define CPU_FEATURE_SCALEFREQ 23 /* CPU supports cpufreq scaling */
120
+
#define CPU_FEATURE_FLATMODE 24 /* CPU has flat mode */
121
+
#define CPU_FEATURE_EIODECODE 25 /* CPU has EXTIOI interrupt pin decode mode */
122
+
#define CPU_FEATURE_GUESTID 26 /* CPU has GuestID feature */
123
+
#define CPU_FEATURE_HYPERVISOR 27 /* CPU has hypervisor (running in VM) */
124
+
#define CPU_FEATURE_PTW 28 /* CPU has hardware page table walker */
125
+
#define CPU_FEATURE_LSPW 29 /* CPU has LSPW (lddir/ldpte instructions) */
126
+
#define CPU_FEATURE_MSGINT 30 /* CPU has MSG interrupt */
127
+
#define CPU_FEATURE_AVECINT 31 /* CPU has AVEC interrupt */
128
+
#define CPU_FEATURE_REDIRECTINT 32 /* CPU has interrupt remapping */
128
129
129
130
#define LOONGARCH_CPU_CPUCFG BIT_ULL(CPU_FEATURE_CPUCFG)
130
131
#define LOONGARCH_CPU_LAM BIT_ULL(CPU_FEATURE_LAM)
132
+
#define LOONGARCH_CPU_SCQ BIT_ULL(CPU_FEATURE_SCQ)
131
133
#define LOONGARCH_CPU_UAL BIT_ULL(CPU_FEATURE_UAL)
132
134
#define LOONGARCH_CPU_FPU BIT_ULL(CPU_FEATURE_FPU)
133
135
#define LOONGARCH_CPU_LSX BIT_ULL(CPU_FEATURE_LSX)
+1
arch/loongarch/include/uapi/asm/hwcap.h
+1
arch/loongarch/include/uapi/asm/hwcap.h
+4
arch/loongarch/kernel/cpu-probe.c
+4
arch/loongarch/kernel/cpu-probe.c
···
177
177
c->options |= LOONGARCH_CPU_LAM;
178
178
elf_hwcap |= HWCAP_LOONGARCH_LAM;
179
179
}
180
+
if (config & CPUCFG2_SCQ) {
181
+
c->options |= LOONGARCH_CPU_SCQ;
182
+
elf_hwcap |= HWCAP_LOONGARCH_SCQ;
183
+
}
180
184
if (config & CPUCFG2_FP) {
181
185
c->options |= LOONGARCH_CPU_FPU;
182
186
elf_hwcap |= HWCAP_LOONGARCH_FPU;
+1
arch/loongarch/kernel/proc.c
+1
arch/loongarch/kernel/proc.c
···
62
62
seq_printf(m, "Features\t\t:");
63
63
if (cpu_has_cpucfg) seq_printf(m, " cpucfg");
64
64
if (cpu_has_lam) seq_printf(m, " lam");
65
+
if (cpu_has_scq) seq_printf(m, " scq");
65
66
if (cpu_has_ual) seq_printf(m, " ual");
66
67
if (cpu_has_fpu) seq_printf(m, " fpu");
67
68
if (cpu_has_lsx) seq_printf(m, " lsx");