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drm/amdgpu: Add host driver reserved-region

Use reserve region helpers for initializing/reserving host driver
reserved region in virtualization environment.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Lijo Lazar and committed by
Alex Deucher
4c616e84 daaf24d1

+27 -67
+3 -3
drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
··· 161 161 ((drv_start_addr & (ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION << 162 162 ATOM_VRAM_OPERATION_FLAGS_SHIFT)) == 0)) { 163 163 /* driver request VRAM reservation for SR-IOV */ 164 - adev->mman.drv_vram_usage_start_offset = (drv_start_addr & 165 - (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10; 166 - adev->mman.drv_vram_usage_size = drv_size << 10; 164 + amdgpu_ttm_init_vram_resv(adev, AMDGPU_RESV_DRV_VRAM_USAGE, 165 + (drv_start_addr & (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10, 166 + drv_size << 10, true); 167 167 } 168 168 169 169 *usage_bytes = 0;
+9 -46
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
··· 1730 1730 } 1731 1731 1732 1732 /* 1733 - * Driver Reservation functions 1734 - */ 1735 - /** 1736 - * amdgpu_ttm_drv_reserve_vram_fini - free drv reserved vram 1737 - * 1738 - * @adev: amdgpu_device pointer 1739 - * 1740 - * free drv reserved vram if it has been reserved. 1741 - */ 1742 - static void amdgpu_ttm_drv_reserve_vram_fini(struct amdgpu_device *adev) 1743 - { 1744 - amdgpu_bo_free_kernel(&adev->mman.drv_vram_usage_reserved_bo, 1745 - NULL, 1746 - &adev->mman.drv_vram_usage_va); 1747 - } 1748 - 1749 - /** 1750 - * amdgpu_ttm_drv_reserve_vram_init - create bo vram reservation from driver 1751 - * 1752 - * @adev: amdgpu_device pointer 1753 - * 1754 - * create bo vram reservation from drv. 1755 - */ 1756 - static int amdgpu_ttm_drv_reserve_vram_init(struct amdgpu_device *adev) 1757 - { 1758 - u64 vram_size = adev->gmc.visible_vram_size; 1759 - 1760 - adev->mman.drv_vram_usage_va = NULL; 1761 - adev->mman.drv_vram_usage_reserved_bo = NULL; 1762 - 1763 - if (adev->mman.drv_vram_usage_size == 0 || 1764 - adev->mman.drv_vram_usage_size > vram_size) 1765 - return 0; 1766 - 1767 - return amdgpu_bo_create_kernel_at(adev, 1768 - adev->mman.drv_vram_usage_start_offset, 1769 - adev->mman.drv_vram_usage_size, 1770 - &adev->mman.drv_vram_usage_reserved_bo, 1771 - &adev->mman.drv_vram_usage_va); 1772 - } 1773 - 1774 - /* 1775 1733 * Memoy training reservation functions 1776 1734 */ 1777 1735 ··· 2106 2148 * The reserved VRAM for the driver must be pinned to a specific 2107 2149 * location in VRAM, so reserve it early. 2108 2150 */ 2109 - r = amdgpu_ttm_drv_reserve_vram_init(adev); 2110 - if (r) 2111 - return r; 2151 + if (adev->mman.resv_region[AMDGPU_RESV_DRV_VRAM_USAGE].size > 2152 + adev->gmc.visible_vram_size) { 2153 + adev->mman.resv_region[AMDGPU_RESV_DRV_VRAM_USAGE].size = 0; 2154 + } else { 2155 + r = amdgpu_ttm_mark_vram_reserved(adev, AMDGPU_RESV_DRV_VRAM_USAGE); 2156 + if (r) 2157 + return r; 2158 + } 2112 2159 2113 2160 /* 2114 2161 * only NAVI10 and later ASICs support IP discovery. ··· 2269 2306 2270 2307 amdgpu_ttm_free_mmio_remap_bo(adev); 2271 2308 amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_FW_VRAM_USAGE); 2272 - amdgpu_ttm_drv_reserve_vram_fini(adev); 2309 + amdgpu_ttm_unmark_vram_reserved(adev, AMDGPU_RESV_DRV_VRAM_USAGE); 2273 2310 2274 2311 if (drm_dev_enter(adev_to_drm(adev), &idx)) { 2275 2312
-6
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
··· 105 105 106 106 bool keep_stolen_vga_memory; 107 107 108 - /* driver VRAM reservation */ 109 - u64 drv_vram_usage_start_offset; 110 - u64 drv_vram_usage_size; 111 - struct amdgpu_bo *drv_vram_usage_reserved_bo; 112 - void *drv_vram_usage_va; 113 - 114 108 struct amdgpu_vram_resv resv_region[AMDGPU_RESV_MAX]; 115 109 116 110 /* PAGE_SIZE'd BO for process memory r/w over SDMA. */
+11 -8
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
··· 438 438 uint64_t retired_page; 439 439 uint32_t bp_idx, bp_cnt; 440 440 void *fw_va = adev->mman.resv_region[AMDGPU_RESV_FW_VRAM_USAGE].cpu_ptr; 441 - void *vram_usage_va = fw_va ? fw_va : adev->mman.drv_vram_usage_va; 441 + void *drv_va = adev->mman.resv_region[AMDGPU_RESV_DRV_VRAM_USAGE].cpu_ptr; 442 + void *vram_usage_va = fw_va ? fw_va : drv_va; 442 443 443 444 memset(&bp, 0, sizeof(bp)); 444 445 ··· 708 707 { 709 708 uint32_t *pfvf_data = NULL; 710 709 void *fw_va = adev->mman.resv_region[AMDGPU_RESV_FW_VRAM_USAGE].cpu_ptr; 710 + void *drv_va = adev->mman.resv_region[AMDGPU_RESV_DRV_VRAM_USAGE].cpu_ptr; 711 711 712 712 adev->virt.fw_reserve.p_pf2vf = NULL; 713 713 adev->virt.fw_reserve.p_vf2pf = NULL; 714 714 adev->virt.vf2pf_update_interval_ms = 0; 715 715 adev->virt.vf2pf_update_retry_cnt = 0; 716 716 717 - if (fw_va && adev->mman.drv_vram_usage_va) { 717 + if (fw_va && drv_va) { 718 718 dev_warn(adev->dev, "Currently fw_vram and drv_vram should not have values at the same time!"); 719 - } else if (fw_va || adev->mman.drv_vram_usage_va) { 719 + } else if (fw_va || drv_va) { 720 720 /* go through this logic in ip_init and reset to init workqueue*/ 721 721 amdgpu_virt_exchange_data(adev); 722 722 ··· 763 761 uint32_t bp_block_size = 0; 764 762 struct amd_sriov_msg_pf2vf_info *pf2vf_v2 = NULL; 765 763 void *fw_va = adev->mman.resv_region[AMDGPU_RESV_FW_VRAM_USAGE].cpu_ptr; 764 + void *drv_va = adev->mman.resv_region[AMDGPU_RESV_DRV_VRAM_USAGE].cpu_ptr; 766 765 767 - if (fw_va || adev->mman.drv_vram_usage_va) { 766 + if (fw_va || drv_va) { 768 767 if (fw_va) { 769 768 if (adev->virt.req_init_data_ver == GPU_CRIT_REGION_V2) { 770 769 adev->virt.fw_reserve.p_pf2vf = ··· 790 787 adev->virt.fw_reserve.ras_telemetry = 791 788 (fw_va + (AMD_SRIOV_MSG_RAS_TELEMETRY_OFFSET_KB_V1 << 10)); 792 789 } 793 - } else if (adev->mman.drv_vram_usage_va) { 790 + } else if (drv_va) { 794 791 adev->virt.fw_reserve.p_pf2vf = 795 792 (struct amd_sriov_msg_pf2vf_info_header *) 796 - (adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB_V1 << 10)); 793 + (drv_va + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB_V1 << 10)); 797 794 adev->virt.fw_reserve.p_vf2pf = 798 795 (struct amd_sriov_msg_vf2pf_info_header *) 799 - (adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB_V1 << 10)); 796 + (drv_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB_V1 << 10)); 800 797 adev->virt.fw_reserve.ras_telemetry = 801 - (adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_RAS_TELEMETRY_OFFSET_KB_V1 << 10)); 798 + (drv_va + (AMD_SRIOV_MSG_RAS_TELEMETRY_OFFSET_KB_V1 << 10)); 802 799 } 803 800 804 801 amdgpu_virt_read_pf2vf_data(adev);
+4 -4
drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_virt_ras_cmd.c
··· 37 37 struct amdsriov_ras_telemetry *ras_telemetry_cpu; 38 38 struct amdsriov_ras_telemetry *ras_telemetry_gpu; 39 39 void *fw_va = adev->mman.resv_region[AMDGPU_RESV_FW_VRAM_USAGE].cpu_ptr; 40 + void *drv_va = adev->mman.resv_region[AMDGPU_RESV_DRV_VRAM_USAGE].cpu_ptr; 40 41 uint64_t fw_vram_usage_start_offset = 0; 41 42 uint64_t ras_telemetry_offset = 0; 42 43 ··· 48 47 fw_vram_usage_start_offset = adev->mman.resv_region[AMDGPU_RESV_FW_VRAM_USAGE].offset; 49 48 ras_telemetry_offset = (uintptr_t)adev->virt.fw_reserve.ras_telemetry - 50 49 (uintptr_t)fw_va; 51 - } else if (adev->mman.drv_vram_usage_va && 52 - adev->mman.drv_vram_usage_va <= adev->virt.fw_reserve.ras_telemetry) { 53 - fw_vram_usage_start_offset = adev->mman.drv_vram_usage_start_offset; 50 + } else if (drv_va && drv_va <= adev->virt.fw_reserve.ras_telemetry) { 51 + fw_vram_usage_start_offset = adev->mman.resv_region[AMDGPU_RESV_DRV_VRAM_USAGE].offset; 54 52 ras_telemetry_offset = (uintptr_t)adev->virt.fw_reserve.ras_telemetry - 55 - (uintptr_t)adev->mman.drv_vram_usage_va; 53 + (uintptr_t)drv_va; 56 54 } else { 57 55 return -EINVAL; 58 56 }