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Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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drm/i915/vrr: Enable DC Balance

Enable DC Balance from vrr compute config and related hw flag.
Also to add pipe restrictions along with this.

--v2:
- Use dc balance check instead of source restriction.
--v3:
- Club pipe restriction check with dc balance enablement. (Ankit)
--v4:
- Separate out Pipe restrictions to patch#7

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20251223104542.2688548-19-mitulkumar.ajitkumar.golani@intel.com

authored by

Mitul Golani and committed by
Ankit Nautiyal 55581927 5786499a

+9
+9
drivers/gpu/drm/i915/display/intel_vrr.c
··· 399 399 crtc_state->vrr.dc_balance.vblank_target = 400 400 DIV_ROUND_UP((crtc_state->vrr.vmax - crtc_state->vrr.vmin) * 401 401 DCB_BLANK_TARGET, 100); 402 + crtc_state->vrr.dc_balance.enable = true; 402 403 } 403 404 404 405 void ··· 790 789 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 791 790 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 792 791 enum pipe pipe = crtc->pipe; 792 + u32 vrr_ctl = intel_de_read(display, TRANS_VRR_CTL(display, cpu_transcoder)); 793 793 794 794 if (!crtc_state->vrr.dc_balance.enable) 795 795 return; ··· 829 827 intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder), 830 828 ADAPTIVE_SYNC_COUNTER_EN); 831 829 intel_pipedmc_dcb_enable(NULL, crtc); 830 + 831 + vrr_ctl |= VRR_CTL_DCB_ADJ_ENABLE; 832 + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl); 832 833 } 833 834 834 835 static void ··· 841 836 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 842 837 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 843 838 enum pipe pipe = crtc->pipe; 839 + u32 vrr_ctl = intel_de_read(display, TRANS_VRR_CTL(display, cpu_transcoder)); 844 840 845 841 if (!old_crtc_state->vrr.dc_balance.enable) 846 842 return; ··· 864 858 intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder), 0); 865 859 intel_de_write(display, TRANS_VRR_DCB_VMAX(cpu_transcoder), 0); 866 860 intel_de_write(display, TRANS_VRR_DCB_FLIPLINE(cpu_transcoder), 0); 861 + 862 + vrr_ctl &= ~VRR_CTL_DCB_ADJ_ENABLE; 863 + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl); 867 864 } 868 865 869 866 static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,