Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
mmc: dw_mmc: add a quirk for accessing 64-bit FIFOs in two halves
In certain DW MMC implementations (such as in some Exynos7870
controllers), 64-bit read/write is not allowed from a 64-bit FIFO.
Add a quirk which facilitates accessing the 64-bit FIFO registers in two
32-bit halves.
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Link: https://lore.kernel.org/r/20250219-exynos7870-mmc-v2-2-b4255a3e39ed@disroot.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
authored by
Kaustabh Chakraborty
and committed by
Ulf Hansson
57c0902f
63dde9c3
+119
-2
+92
-2
drivers/mmc/host/dw_mmc.c
+92
-2
drivers/mmc/host/dw_mmc.c
···
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}
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}
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+
static void dw_mci_push_data64_32(struct dw_mci *host, void *buf, int cnt)
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{
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struct mmc_data *data = host->data;
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int init_cnt = cnt;
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+
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/* try and push anything in the part_buf */
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if (unlikely(host->part_buf_count)) {
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int len = dw_mci_push_part_bytes(host, buf, cnt);
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+
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buf += len;
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cnt -= len;
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+
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if (host->part_buf_count == 8) {
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mci_fifo_l_writeq(host->fifo_reg, host->part_buf);
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host->part_buf_count = 0;
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}
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}
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#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
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if (unlikely((unsigned long)buf & 0x7)) {
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while (cnt >= 8) {
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u64 aligned_buf[16];
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int len = min(cnt & -8, (int)sizeof(aligned_buf));
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int items = len >> 3;
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int i;
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/* memcpy from input buffer into aligned buffer */
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memcpy(aligned_buf, buf, len);
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buf += len;
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cnt -= len;
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/* push data from aligned buffer into fifo */
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for (i = 0; i < items; ++i)
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mci_fifo_l_writeq(host->fifo_reg, aligned_buf[i]);
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}
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} else
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#endif
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{
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u64 *pdata = buf;
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+
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for (; cnt >= 8; cnt -= 8)
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mci_fifo_l_writeq(host->fifo_reg, *pdata++);
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buf = pdata;
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}
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/* put anything remaining in the part_buf */
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if (cnt) {
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dw_mci_set_part_bytes(host, buf, cnt);
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/* Push data if we have reached the expected data length */
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if ((data->bytes_xfered + init_cnt) ==
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(data->blksz * data->blocks))
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mci_fifo_l_writeq(host->fifo_reg, host->part_buf);
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}
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}
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+
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static void dw_mci_pull_data64_32(struct dw_mci *host, void *buf, int cnt)
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{
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#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
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if (unlikely((unsigned long)buf & 0x7)) {
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while (cnt >= 8) {
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/* pull data from fifo into aligned buffer */
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u64 aligned_buf[16];
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int len = min(cnt & -8, (int)sizeof(aligned_buf));
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int items = len >> 3;
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int i;
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for (i = 0; i < items; ++i)
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aligned_buf[i] = mci_fifo_l_readq(host->fifo_reg);
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/* memcpy from aligned buffer into output buffer */
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memcpy(buf, aligned_buf, len);
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buf += len;
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cnt -= len;
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}
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} else
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#endif
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{
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u64 *pdata = buf;
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+
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for (; cnt >= 8; cnt -= 8)
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*pdata++ = mci_fifo_l_readq(host->fifo_reg);
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buf = pdata;
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}
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if (cnt) {
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host->part_buf = mci_fifo_l_readq(host->fifo_reg);
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dw_mci_pull_final_bytes(host, buf, cnt);
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}
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}
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+
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static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
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{
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int len;
···
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width = 16;
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host->data_shift = 1;
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} else if (i == 2) {
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-
host->push_data = dw_mci_push_data64;
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-
host->pull_data = dw_mci_pull_data64;
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+
if ((host->quirks & DW_MMC_QUIRK_FIFO64_32)) {
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host->push_data = dw_mci_push_data64_32;
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host->pull_data = dw_mci_pull_data64_32;
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} else {
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host->push_data = dw_mci_push_data64;
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host->pull_data = dw_mci_pull_data64;
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}
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width = 64;
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host->data_shift = 3;
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} else {
+27
drivers/mmc/host/dw_mmc.h
+27
drivers/mmc/host/dw_mmc.h
···
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/* Support for longer data read timeout */
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#define DW_MMC_QUIRK_EXTENDED_TMOUT BIT(0)
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/* Force 32-bit access to the FIFO */
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#define DW_MMC_QUIRK_FIFO64_32 BIT(1)
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#define DW_MMC_240A 0x240a
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#define DW_MMC_280A 0x280a
···
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#define mci_fifo_writew(__value, __reg) __raw_writew(__reg, __value)
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#define mci_fifo_writel(__value, __reg) __raw_writel(__reg, __value)
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#define mci_fifo_writeq(__value, __reg) __raw_writeq(__reg, __value)
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/*
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* Some dw_mmc devices have 64-bit FIFOs, but expect them to be
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* accessed using two 32-bit accesses. If such controller is used
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* with a 64-bit kernel, this has to be done explicitly.
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*/
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static inline u64 mci_fifo_l_readq(void __iomem *addr)
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{
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u64 ans;
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u32 proxy[2];
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+
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proxy[0] = mci_fifo_readl(addr);
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proxy[1] = mci_fifo_readl(addr + 4);
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memcpy(&ans, proxy, 8);
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return ans;
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}
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+
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static inline void mci_fifo_l_writeq(void __iomem *addr, u64 value)
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+
{
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u32 proxy[2];
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+
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memcpy(proxy, &value, 8);
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mci_fifo_writel(addr, proxy[0]);
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mci_fifo_writel(addr + 4, proxy[1]);
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}
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/* Register access macros */
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#define mci_readl(dev, reg) \