clk: renesas: rzg2l: Add support for MSTOP in clock enable/disable API

+66 -66

drivers/clk/renesas/r9a07g043-cpg.c

··· 164 164 static const struct rzg2l_mod_clk r9a07g043_mod_clks[] = { 165 165 #ifdef CONFIG_ARM64 166 166 DEF_MOD("gic", R9A07G043_GIC600_GICCLK, R9A07G043_CLK_P1, 167 - 0x514, 0), 167 + 0x514, 0, 0), 168 168 DEF_MOD("ia55_pclk", R9A07G043_IA55_PCLK, R9A07G043_CLK_P2, 169 - 0x518, 0), 169 + 0x518, 0, 0), 170 170 DEF_MOD("ia55_clk", R9A07G043_IA55_CLK, R9A07G043_CLK_P1, 171 - 0x518, 1), 171 + 0x518, 1, 0), 172 172 #endif 173 173 #ifdef CONFIG_RISCV 174 174 DEF_MOD("iax45_pclk", R9A07G043_IAX45_PCLK, R9A07G043_CLK_P2, 175 - 0x518, 0), 175 + 0x518, 0, 0), 176 176 DEF_MOD("iax45_clk", R9A07G043_IAX45_CLK, R9A07G043_CLK_P1, 177 - 0x518, 1), 177 + 0x518, 1, 0), 178 178 #endif 179 179 DEF_MOD("dmac_aclk", R9A07G043_DMAC_ACLK, R9A07G043_CLK_P1, 180 - 0x52c, 0), 180 + 0x52c, 0, 0), 181 181 DEF_MOD("dmac_pclk", R9A07G043_DMAC_PCLK, CLK_P1_DIV2, 182 - 0x52c, 1), 182 + 0x52c, 1, 0), 183 183 DEF_MOD("ostm0_pclk", R9A07G043_OSTM0_PCLK, R9A07G043_CLK_P0, 184 - 0x534, 0), 184 + 0x534, 0, 0), 185 185 DEF_MOD("ostm1_pclk", R9A07G043_OSTM1_PCLK, R9A07G043_CLK_P0, 186 - 0x534, 1), 186 + 0x534, 1, 0), 187 187 DEF_MOD("ostm2_pclk", R9A07G043_OSTM2_PCLK, R9A07G043_CLK_P0, 188 - 0x534, 2), 188 + 0x534, 2, 0), 189 189 DEF_MOD("mtu_x_mck", R9A07G043_MTU_X_MCK_MTU3, R9A07G043_CLK_P0, 190 - 0x538, 0), 190 + 0x538, 0, 0), 191 191 DEF_MOD("wdt0_pclk", R9A07G043_WDT0_PCLK, R9A07G043_CLK_P0, 192 - 0x548, 0), 192 + 0x548, 0, 0), 193 193 DEF_MOD("wdt0_clk", R9A07G043_WDT0_CLK, R9A07G043_OSCCLK, 194 - 0x548, 1), 194 + 0x548, 1, 0), 195 195 DEF_MOD("spi_clk2", R9A07G043_SPI_CLK2, R9A07G043_CLK_SPI1, 196 - 0x550, 0), 196 + 0x550, 0, 0), 197 197 DEF_MOD("spi_clk", R9A07G043_SPI_CLK, R9A07G043_CLK_SPI0, 198 - 0x550, 1), 198 + 0x550, 1, 0), 199 199 DEF_MOD("sdhi0_imclk", R9A07G043_SDHI0_IMCLK, CLK_SD0_DIV4, 200 - 0x554, 0), 200 + 0x554, 0, 0), 201 201 DEF_MOD("sdhi0_imclk2", R9A07G043_SDHI0_IMCLK2, CLK_SD0_DIV4, 202 - 0x554, 1), 202 + 0x554, 1, 0), 203 203 DEF_MOD("sdhi0_clk_hs", R9A07G043_SDHI0_CLK_HS, R9A07G043_CLK_SD0, 204 - 0x554, 2), 204 + 0x554, 2, 0), 205 205 DEF_MOD("sdhi0_aclk", R9A07G043_SDHI0_ACLK, R9A07G043_CLK_P1, 206 - 0x554, 3), 206 + 0x554, 3, 0), 207 207 DEF_MOD("sdhi1_imclk", R9A07G043_SDHI1_IMCLK, CLK_SD1_DIV4, 208 - 0x554, 4), 208 + 0x554, 4, 0), 209 209 DEF_MOD("sdhi1_imclk2", R9A07G043_SDHI1_IMCLK2, CLK_SD1_DIV4, 210 - 0x554, 5), 210 + 0x554, 5, 0), 211 211 DEF_MOD("sdhi1_clk_hs", R9A07G043_SDHI1_CLK_HS, R9A07G043_CLK_SD1, 212 - 0x554, 6), 212 + 0x554, 6, 0), 213 213 DEF_MOD("sdhi1_aclk", R9A07G043_SDHI1_ACLK, R9A07G043_CLK_P1, 214 - 0x554, 7), 214 + 0x554, 7, 0), 215 215 #ifdef CONFIG_ARM64 216 216 DEF_MOD("cru_sysclk", R9A07G043_CRU_SYSCLK, CLK_M2_DIV2, 217 - 0x564, 0), 217 + 0x564, 0, 0), 218 218 DEF_MOD("cru_vclk", R9A07G043_CRU_VCLK, R9A07G043_CLK_M2, 219 - 0x564, 1), 219 + 0x564, 1, 0), 220 220 DEF_MOD("cru_pclk", R9A07G043_CRU_PCLK, R9A07G043_CLK_ZT, 221 - 0x564, 2), 221 + 0x564, 2, 0), 222 222 DEF_MOD("cru_aclk", R9A07G043_CRU_ACLK, R9A07G043_CLK_M0, 223 - 0x564, 3), 223 + 0x564, 3, 0), 224 224 DEF_COUPLED("lcdc_clk_a", R9A07G043_LCDC_CLK_A, R9A07G043_CLK_M0, 225 - 0x56c, 0), 225 + 0x56c, 0, 0), 226 226 DEF_COUPLED("lcdc_clk_p", R9A07G043_LCDC_CLK_P, R9A07G043_CLK_ZT, 227 - 0x56c, 0), 227 + 0x56c, 0, 0), 228 228 DEF_MOD("lcdc_clk_d", R9A07G043_LCDC_CLK_D, R9A07G043_CLK_M3, 229 - 0x56c, 1), 229 + 0x56c, 1, 0), 230 230 #endif 231 231 DEF_MOD("ssi0_pclk", R9A07G043_SSI0_PCLK2, R9A07G043_CLK_P0, 232 - 0x570, 0), 232 + 0x570, 0, 0), 233 233 DEF_MOD("ssi0_sfr", R9A07G043_SSI0_PCLK_SFR, R9A07G043_CLK_P0, 234 - 0x570, 1), 234 + 0x570, 1, 0), 235 235 DEF_MOD("ssi1_pclk", R9A07G043_SSI1_PCLK2, R9A07G043_CLK_P0, 236 - 0x570, 2), 236 + 0x570, 2, 0), 237 237 DEF_MOD("ssi1_sfr", R9A07G043_SSI1_PCLK_SFR, R9A07G043_CLK_P0, 238 - 0x570, 3), 238 + 0x570, 3, 0), 239 239 DEF_MOD("ssi2_pclk", R9A07G043_SSI2_PCLK2, R9A07G043_CLK_P0, 240 - 0x570, 4), 240 + 0x570, 4, 0), 241 241 DEF_MOD("ssi2_sfr", R9A07G043_SSI2_PCLK_SFR, R9A07G043_CLK_P0, 242 - 0x570, 5), 242 + 0x570, 5, 0), 243 243 DEF_MOD("ssi3_pclk", R9A07G043_SSI3_PCLK2, R9A07G043_CLK_P0, 244 - 0x570, 6), 244 + 0x570, 6, 0), 245 245 DEF_MOD("ssi3_sfr", R9A07G043_SSI3_PCLK_SFR, R9A07G043_CLK_P0, 246 - 0x570, 7), 246 + 0x570, 7, 0), 247 247 DEF_MOD("usb0_host", R9A07G043_USB_U2H0_HCLK, R9A07G043_CLK_P1, 248 - 0x578, 0), 248 + 0x578, 0, 0), 249 249 DEF_MOD("usb1_host", R9A07G043_USB_U2H1_HCLK, R9A07G043_CLK_P1, 250 - 0x578, 1), 250 + 0x578, 1, 0), 251 251 DEF_MOD("usb0_func", R9A07G043_USB_U2P_EXR_CPUCLK, R9A07G043_CLK_P1, 252 - 0x578, 2), 252 + 0x578, 2, 0), 253 253 DEF_MOD("usb_pclk", R9A07G043_USB_PCLK, R9A07G043_CLK_P1, 254 - 0x578, 3), 254 + 0x578, 3, 0), 255 255 DEF_COUPLED("eth0_axi", R9A07G043_ETH0_CLK_AXI, R9A07G043_CLK_M0, 256 - 0x57c, 0), 256 + 0x57c, 0, 0), 257 257 DEF_COUPLED("eth0_chi", R9A07G043_ETH0_CLK_CHI, R9A07G043_CLK_ZT, 258 - 0x57c, 0), 258 + 0x57c, 0, 0), 259 259 DEF_COUPLED("eth1_axi", R9A07G043_ETH1_CLK_AXI, R9A07G043_CLK_M0, 260 - 0x57c, 1), 260 + 0x57c, 1, 0), 261 261 DEF_COUPLED("eth1_chi", R9A07G043_ETH1_CLK_CHI, R9A07G043_CLK_ZT, 262 - 0x57c, 1), 262 + 0x57c, 1, 0), 263 263 DEF_MOD("i2c0", R9A07G043_I2C0_PCLK, R9A07G043_CLK_P0, 264 - 0x580, 0), 264 + 0x580, 0, 0), 265 265 DEF_MOD("i2c1", R9A07G043_I2C1_PCLK, R9A07G043_CLK_P0, 266 - 0x580, 1), 266 + 0x580, 1, 0), 267 267 DEF_MOD("i2c2", R9A07G043_I2C2_PCLK, R9A07G043_CLK_P0, 268 - 0x580, 2), 268 + 0x580, 2, 0), 269 269 DEF_MOD("i2c3", R9A07G043_I2C3_PCLK, R9A07G043_CLK_P0, 270 - 0x580, 3), 270 + 0x580, 3, 0), 271 271 DEF_MOD("scif0", R9A07G043_SCIF0_CLK_PCK, R9A07G043_CLK_P0, 272 - 0x584, 0), 272 + 0x584, 0, 0), 273 273 DEF_MOD("scif1", R9A07G043_SCIF1_CLK_PCK, R9A07G043_CLK_P0, 274 - 0x584, 1), 274 + 0x584, 1, 0), 275 275 DEF_MOD("scif2", R9A07G043_SCIF2_CLK_PCK, R9A07G043_CLK_P0, 276 - 0x584, 2), 276 + 0x584, 2, 0), 277 277 DEF_MOD("scif3", R9A07G043_SCIF3_CLK_PCK, R9A07G043_CLK_P0, 278 - 0x584, 3), 278 + 0x584, 3, 0), 279 279 DEF_MOD("scif4", R9A07G043_SCIF4_CLK_PCK, R9A07G043_CLK_P0, 280 - 0x584, 4), 280 + 0x584, 4, 0), 281 281 DEF_MOD("sci0", R9A07G043_SCI0_CLKP, R9A07G043_CLK_P0, 282 - 0x588, 0), 282 + 0x588, 0, 0), 283 283 DEF_MOD("sci1", R9A07G043_SCI1_CLKP, R9A07G043_CLK_P0, 284 - 0x588, 1), 284 + 0x588, 1, 0), 285 285 DEF_MOD("rspi0", R9A07G043_RSPI0_CLKB, R9A07G043_CLK_P0, 286 - 0x590, 0), 286 + 0x590, 0, 0), 287 287 DEF_MOD("rspi1", R9A07G043_RSPI1_CLKB, R9A07G043_CLK_P0, 288 - 0x590, 1), 288 + 0x590, 1, 0), 289 289 DEF_MOD("rspi2", R9A07G043_RSPI2_CLKB, R9A07G043_CLK_P0, 290 - 0x590, 2), 290 + 0x590, 2, 0), 291 291 DEF_MOD("canfd", R9A07G043_CANFD_PCLK, R9A07G043_CLK_P0, 292 - 0x594, 0), 292 + 0x594, 0, 0), 293 293 DEF_MOD("gpio", R9A07G043_GPIO_HCLK, R9A07G043_OSCCLK, 294 - 0x598, 0), 294 + 0x598, 0, 0), 295 295 DEF_MOD("adc_adclk", R9A07G043_ADC_ADCLK, R9A07G043_CLK_TSU, 296 - 0x5a8, 0), 296 + 0x5a8, 0, 0), 297 297 DEF_MOD("adc_pclk", R9A07G043_ADC_PCLK, R9A07G043_CLK_P0, 298 - 0x5a8, 1), 298 + 0x5a8, 1, 0), 299 299 DEF_MOD("tsu_pclk", R9A07G043_TSU_PCLK, R9A07G043_CLK_TSU, 300 - 0x5ac, 0), 300 + 0x5ac, 0, 0), 301 301 #ifdef CONFIG_RISCV 302 302 DEF_MOD("nceplic_aclk", R9A07G043_NCEPLIC_ACLK, R9A07G043_CLK_P1, 303 - 0x608, 0), 303 + 0x608, 0, 0), 304 304 #endif 305 305 }; 306 306

+84 -84

drivers/clk/renesas/r9a07g044-cpg.c

··· 242 242 } mod_clks = { 243 243 .common = { 244 244 DEF_MOD("gic", R9A07G044_GIC600_GICCLK, R9A07G044_CLK_P1, 245 - 0x514, 0), 245 + 0x514, 0, 0), 246 246 DEF_MOD("ia55_pclk", R9A07G044_IA55_PCLK, R9A07G044_CLK_P2, 247 - 0x518, 0), 247 + 0x518, 0, 0), 248 248 DEF_MOD("ia55_clk", R9A07G044_IA55_CLK, R9A07G044_CLK_P1, 249 - 0x518, 1), 249 + 0x518, 1, 0), 250 250 DEF_MOD("dmac_aclk", R9A07G044_DMAC_ACLK, R9A07G044_CLK_P1, 251 - 0x52c, 0), 251 + 0x52c, 0, 0), 252 252 DEF_MOD("dmac_pclk", R9A07G044_DMAC_PCLK, CLK_P1_DIV2, 253 - 0x52c, 1), 253 + 0x52c, 1, 0), 254 254 DEF_MOD("ostm0_pclk", R9A07G044_OSTM0_PCLK, R9A07G044_CLK_P0, 255 - 0x534, 0), 255 + 0x534, 0, 0), 256 256 DEF_MOD("ostm1_pclk", R9A07G044_OSTM1_PCLK, R9A07G044_CLK_P0, 257 - 0x534, 1), 257 + 0x534, 1, 0), 258 258 DEF_MOD("ostm2_pclk", R9A07G044_OSTM2_PCLK, R9A07G044_CLK_P0, 259 - 0x534, 2), 259 + 0x534, 2, 0), 260 260 DEF_MOD("mtu_x_mck", R9A07G044_MTU_X_MCK_MTU3, R9A07G044_CLK_P0, 261 - 0x538, 0), 261 + 0x538, 0, 0), 262 262 DEF_MOD("gpt_pclk", R9A07G044_GPT_PCLK, R9A07G044_CLK_P0, 263 - 0x540, 0), 263 + 0x540, 0, 0), 264 264 DEF_MOD("poeg_a_clkp", R9A07G044_POEG_A_CLKP, R9A07G044_CLK_P0, 265 - 0x544, 0), 265 + 0x544, 0, 0), 266 266 DEF_MOD("poeg_b_clkp", R9A07G044_POEG_B_CLKP, R9A07G044_CLK_P0, 267 - 0x544, 1), 267 + 0x544, 1, 0), 268 268 DEF_MOD("poeg_c_clkp", R9A07G044_POEG_C_CLKP, R9A07G044_CLK_P0, 269 - 0x544, 2), 269 + 0x544, 2, 0), 270 270 DEF_MOD("poeg_d_clkp", R9A07G044_POEG_D_CLKP, R9A07G044_CLK_P0, 271 - 0x544, 3), 271 + 0x544, 3, 0), 272 272 DEF_MOD("wdt0_pclk", R9A07G044_WDT0_PCLK, R9A07G044_CLK_P0, 273 - 0x548, 0), 273 + 0x548, 0, 0), 274 274 DEF_MOD("wdt0_clk", R9A07G044_WDT0_CLK, R9A07G044_OSCCLK, 275 - 0x548, 1), 275 + 0x548, 1, 0), 276 276 DEF_MOD("wdt1_pclk", R9A07G044_WDT1_PCLK, R9A07G044_CLK_P0, 277 - 0x548, 2), 277 + 0x548, 2, 0), 278 278 DEF_MOD("wdt1_clk", R9A07G044_WDT1_CLK, R9A07G044_OSCCLK, 279 - 0x548, 3), 279 + 0x548, 3, 0), 280 280 DEF_MOD("spi_clk2", R9A07G044_SPI_CLK2, R9A07G044_CLK_SPI1, 281 - 0x550, 0), 281 + 0x550, 0, 0), 282 282 DEF_MOD("spi_clk", R9A07G044_SPI_CLK, R9A07G044_CLK_SPI0, 283 - 0x550, 1), 283 + 0x550, 1, 0), 284 284 DEF_MOD("sdhi0_imclk", R9A07G044_SDHI0_IMCLK, CLK_SD0_DIV4, 285 - 0x554, 0), 285 + 0x554, 0, 0), 286 286 DEF_MOD("sdhi0_imclk2", R9A07G044_SDHI0_IMCLK2, CLK_SD0_DIV4, 287 - 0x554, 1), 287 + 0x554, 1, 0), 288 288 DEF_MOD("sdhi0_clk_hs", R9A07G044_SDHI0_CLK_HS, R9A07G044_CLK_SD0, 289 - 0x554, 2), 289 + 0x554, 2, 0), 290 290 DEF_MOD("sdhi0_aclk", R9A07G044_SDHI0_ACLK, R9A07G044_CLK_P1, 291 - 0x554, 3), 291 + 0x554, 3, 0), 292 292 DEF_MOD("sdhi1_imclk", R9A07G044_SDHI1_IMCLK, CLK_SD1_DIV4, 293 - 0x554, 4), 293 + 0x554, 4, 0), 294 294 DEF_MOD("sdhi1_imclk2", R9A07G044_SDHI1_IMCLK2, CLK_SD1_DIV4, 295 - 0x554, 5), 295 + 0x554, 5, 0), 296 296 DEF_MOD("sdhi1_clk_hs", R9A07G044_SDHI1_CLK_HS, R9A07G044_CLK_SD1, 297 - 0x554, 6), 297 + 0x554, 6, 0), 298 298 DEF_MOD("sdhi1_aclk", R9A07G044_SDHI1_ACLK, R9A07G044_CLK_P1, 299 - 0x554, 7), 299 + 0x554, 7, 0), 300 300 DEF_MOD("gpu_clk", R9A07G044_GPU_CLK, R9A07G044_CLK_G, 301 - 0x558, 0), 301 + 0x558, 0, 0), 302 302 DEF_MOD("gpu_axi_clk", R9A07G044_GPU_AXI_CLK, R9A07G044_CLK_P1, 303 - 0x558, 1), 303 + 0x558, 1, 0), 304 304 DEF_MOD("gpu_ace_clk", R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1, 305 - 0x558, 2), 305 + 0x558, 2, 0), 306 306 DEF_MOD("cru_sysclk", R9A07G044_CRU_SYSCLK, CLK_M2_DIV2, 307 - 0x564, 0), 307 + 0x564, 0, 0), 308 308 DEF_MOD("cru_vclk", R9A07G044_CRU_VCLK, R9A07G044_CLK_M2, 309 - 0x564, 1), 309 + 0x564, 1, 0), 310 310 DEF_MOD("cru_pclk", R9A07G044_CRU_PCLK, R9A07G044_CLK_ZT, 311 - 0x564, 2), 311 + 0x564, 2, 0), 312 312 DEF_MOD("cru_aclk", R9A07G044_CRU_ACLK, R9A07G044_CLK_M0, 313 - 0x564, 3), 313 + 0x564, 3, 0), 314 314 DEF_MOD("dsi_pll_clk", R9A07G044_MIPI_DSI_PLLCLK, R9A07G044_CLK_M1, 315 - 0x568, 0), 315 + 0x568, 0, 0), 316 316 DEF_MOD("dsi_sys_clk", R9A07G044_MIPI_DSI_SYSCLK, CLK_M2_DIV2, 317 - 0x568, 1), 317 + 0x568, 1, 0), 318 318 DEF_MOD("dsi_aclk", R9A07G044_MIPI_DSI_ACLK, R9A07G044_CLK_P1, 319 - 0x568, 2), 319 + 0x568, 2, 0), 320 320 DEF_MOD("dsi_pclk", R9A07G044_MIPI_DSI_PCLK, R9A07G044_CLK_P2, 321 - 0x568, 3), 321 + 0x568, 3, 0), 322 322 DEF_MOD("dsi_vclk", R9A07G044_MIPI_DSI_VCLK, R9A07G044_CLK_M3, 323 - 0x568, 4), 323 + 0x568, 4, 0), 324 324 DEF_MOD("dsi_lpclk", R9A07G044_MIPI_DSI_LPCLK, R9A07G044_CLK_M4, 325 - 0x568, 5), 325 + 0x568, 5, 0), 326 326 DEF_COUPLED("lcdc_a", R9A07G044_LCDC_CLK_A, R9A07G044_CLK_M0, 327 - 0x56c, 0), 327 + 0x56c, 0, 0), 328 328 DEF_COUPLED("lcdc_p", R9A07G044_LCDC_CLK_P, R9A07G044_CLK_ZT, 329 - 0x56c, 0), 329 + 0x56c, 0, 0), 330 330 DEF_MOD("lcdc_clk_d", R9A07G044_LCDC_CLK_D, R9A07G044_CLK_M3, 331 - 0x56c, 1), 331 + 0x56c, 1, 0), 332 332 DEF_MOD("ssi0_pclk", R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0, 333 - 0x570, 0), 333 + 0x570, 0, 0), 334 334 DEF_MOD("ssi0_sfr", R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0, 335 - 0x570, 1), 335 + 0x570, 1, 0), 336 336 DEF_MOD("ssi1_pclk", R9A07G044_SSI1_PCLK2, R9A07G044_CLK_P0, 337 - 0x570, 2), 337 + 0x570, 2, 0), 338 338 DEF_MOD("ssi1_sfr", R9A07G044_SSI1_PCLK_SFR, R9A07G044_CLK_P0, 339 - 0x570, 3), 339 + 0x570, 3, 0), 340 340 DEF_MOD("ssi2_pclk", R9A07G044_SSI2_PCLK2, R9A07G044_CLK_P0, 341 - 0x570, 4), 341 + 0x570, 4, 0), 342 342 DEF_MOD("ssi2_sfr", R9A07G044_SSI2_PCLK_SFR, R9A07G044_CLK_P0, 343 - 0x570, 5), 343 + 0x570, 5, 0), 344 344 DEF_MOD("ssi3_pclk", R9A07G044_SSI3_PCLK2, R9A07G044_CLK_P0, 345 - 0x570, 6), 345 + 0x570, 6, 0), 346 346 DEF_MOD("ssi3_sfr", R9A07G044_SSI3_PCLK_SFR, R9A07G044_CLK_P0, 347 - 0x570, 7), 347 + 0x570, 7, 0), 348 348 DEF_MOD("usb0_host", R9A07G044_USB_U2H0_HCLK, R9A07G044_CLK_P1, 349 - 0x578, 0), 349 + 0x578, 0, 0), 350 350 DEF_MOD("usb1_host", R9A07G044_USB_U2H1_HCLK, R9A07G044_CLK_P1, 351 - 0x578, 1), 351 + 0x578, 1, 0), 352 352 DEF_MOD("usb0_func", R9A07G044_USB_U2P_EXR_CPUCLK, R9A07G044_CLK_P1, 353 - 0x578, 2), 353 + 0x578, 2, 0), 354 354 DEF_MOD("usb_pclk", R9A07G044_USB_PCLK, R9A07G044_CLK_P1, 355 - 0x578, 3), 355 + 0x578, 3, 0), 356 356 DEF_COUPLED("eth0_axi", R9A07G044_ETH0_CLK_AXI, R9A07G044_CLK_M0, 357 - 0x57c, 0), 357 + 0x57c, 0, 0), 358 358 DEF_COUPLED("eth0_chi", R9A07G044_ETH0_CLK_CHI, R9A07G044_CLK_ZT, 359 - 0x57c, 0), 359 + 0x57c, 0, 0), 360 360 DEF_COUPLED("eth1_axi", R9A07G044_ETH1_CLK_AXI, R9A07G044_CLK_M0, 361 - 0x57c, 1), 361 + 0x57c, 1, 0), 362 362 DEF_COUPLED("eth1_chi", R9A07G044_ETH1_CLK_CHI, R9A07G044_CLK_ZT, 363 - 0x57c, 1), 363 + 0x57c, 1, 0), 364 364 DEF_MOD("i2c0", R9A07G044_I2C0_PCLK, R9A07G044_CLK_P0, 365 - 0x580, 0), 365 + 0x580, 0, 0), 366 366 DEF_MOD("i2c1", R9A07G044_I2C1_PCLK, R9A07G044_CLK_P0, 367 - 0x580, 1), 367 + 0x580, 1, 0), 368 368 DEF_MOD("i2c2", R9A07G044_I2C2_PCLK, R9A07G044_CLK_P0, 369 - 0x580, 2), 369 + 0x580, 2, 0), 370 370 DEF_MOD("i2c3", R9A07G044_I2C3_PCLK, R9A07G044_CLK_P0, 371 - 0x580, 3), 371 + 0x580, 3, 0), 372 372 DEF_MOD("scif0", R9A07G044_SCIF0_CLK_PCK, R9A07G044_CLK_P0, 373 - 0x584, 0), 373 + 0x584, 0, 0), 374 374 DEF_MOD("scif1", R9A07G044_SCIF1_CLK_PCK, R9A07G044_CLK_P0, 375 - 0x584, 1), 375 + 0x584, 1, 0), 376 376 DEF_MOD("scif2", R9A07G044_SCIF2_CLK_PCK, R9A07G044_CLK_P0, 377 - 0x584, 2), 377 + 0x584, 2, 0), 378 378 DEF_MOD("scif3", R9A07G044_SCIF3_CLK_PCK, R9A07G044_CLK_P0, 379 - 0x584, 3), 379 + 0x584, 3, 0), 380 380 DEF_MOD("scif4", R9A07G044_SCIF4_CLK_PCK, R9A07G044_CLK_P0, 381 - 0x584, 4), 381 + 0x584, 4, 0), 382 382 DEF_MOD("sci0", R9A07G044_SCI0_CLKP, R9A07G044_CLK_P0, 383 - 0x588, 0), 383 + 0x588, 0, 0), 384 384 DEF_MOD("sci1", R9A07G044_SCI1_CLKP, R9A07G044_CLK_P0, 385 - 0x588, 1), 385 + 0x588, 1, 0), 386 386 DEF_MOD("rspi0", R9A07G044_RSPI0_CLKB, R9A07G044_CLK_P0, 387 - 0x590, 0), 387 + 0x590, 0, 0), 388 388 DEF_MOD("rspi1", R9A07G044_RSPI1_CLKB, R9A07G044_CLK_P0, 389 - 0x590, 1), 389 + 0x590, 1, 0), 390 390 DEF_MOD("rspi2", R9A07G044_RSPI2_CLKB, R9A07G044_CLK_P0, 391 - 0x590, 2), 391 + 0x590, 2, 0), 392 392 DEF_MOD("canfd", R9A07G044_CANFD_PCLK, R9A07G044_CLK_P0, 393 - 0x594, 0), 393 + 0x594, 0, 0), 394 394 DEF_MOD("gpio", R9A07G044_GPIO_HCLK, R9A07G044_OSCCLK, 395 - 0x598, 0), 395 + 0x598, 0, 0), 396 396 DEF_MOD("adc_adclk", R9A07G044_ADC_ADCLK, R9A07G044_CLK_TSU, 397 - 0x5a8, 0), 397 + 0x5a8, 0, 0), 398 398 DEF_MOD("adc_pclk", R9A07G044_ADC_PCLK, R9A07G044_CLK_P0, 399 - 0x5a8, 1), 399 + 0x5a8, 1, 0), 400 400 DEF_MOD("tsu_pclk", R9A07G044_TSU_PCLK, R9A07G044_CLK_TSU, 401 - 0x5ac, 0), 401 + 0x5ac, 0, 0), 402 402 }, 403 403 #ifdef CONFIG_CLK_R9A07G054 404 404 .drp = { 405 405 DEF_MOD("stpai_initclk", R9A07G054_STPAI_INITCLK, R9A07G044_OSCCLK, 406 - 0x5e8, 0), 406 + 0x5e8, 0, 0), 407 407 DEF_MOD("stpai_aclk", R9A07G054_STPAI_ACLK, R9A07G044_CLK_P1, 408 - 0x5e8, 1), 408 + 0x5e8, 1, 0), 409 409 DEF_MOD("stpai_mclk", R9A07G054_STPAI_MCLK, R9A07G054_CLK_DRP_M, 410 - 0x5e8, 2), 410 + 0x5e8, 2, 0), 411 411 DEF_MOD("stpai_dclkin", R9A07G054_STPAI_DCLKIN, R9A07G054_CLK_DRP_D, 412 - 0x5e8, 3), 412 + 0x5e8, 3, 0), 413 413 DEF_MOD("stpai_aclk_drp", R9A07G054_STPAI_ACLK_DRP, R9A07G054_CLK_DRP_A, 414 - 0x5e8, 4), 414 + 0x5e8, 4, 0), 415 415 }, 416 416 #endif 417 417 };

+53 -52

drivers/clk/renesas/r9a08g045-cpg.c

··· 192 192 }; 193 193 194 194 static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = { 195 - DEF_MOD("gic_gicclk", R9A08G045_GIC600_GICCLK, R9A08G045_CLK_P1, 0x514, 0), 196 - DEF_MOD("ia55_pclk", R9A08G045_IA55_PCLK, R9A08G045_CLK_P2, 0x518, 0), 197 - DEF_MOD("ia55_clk", R9A08G045_IA55_CLK, R9A08G045_CLK_P1, 0x518, 1), 198 - DEF_MOD("dmac_aclk", R9A08G045_DMAC_ACLK, R9A08G045_CLK_P3, 0x52c, 0), 199 - DEF_MOD("dmac_pclk", R9A08G045_DMAC_PCLK, CLK_P3_DIV2, 0x52c, 1), 200 - DEF_MOD("wdt0_pclk", R9A08G045_WDT0_PCLK, R9A08G045_CLK_P0, 0x548, 0), 201 - DEF_MOD("wdt0_clk", R9A08G045_WDT0_CLK, R9A08G045_OSCCLK, 0x548, 1), 202 - DEF_MOD("sdhi0_imclk", R9A08G045_SDHI0_IMCLK, CLK_SD0_DIV4, 0x554, 0), 203 - DEF_MOD("sdhi0_imclk2", R9A08G045_SDHI0_IMCLK2, CLK_SD0_DIV4, 0x554, 1), 204 - DEF_MOD("sdhi0_clk_hs", R9A08G045_SDHI0_CLK_HS, R9A08G045_CLK_SD0, 0x554, 2), 205 - DEF_MOD("sdhi0_aclk", R9A08G045_SDHI0_ACLK, R9A08G045_CLK_P1, 0x554, 3), 206 - DEF_MOD("sdhi1_imclk", R9A08G045_SDHI1_IMCLK, CLK_SD1_DIV4, 0x554, 4), 207 - DEF_MOD("sdhi1_imclk2", R9A08G045_SDHI1_IMCLK2, CLK_SD1_DIV4, 0x554, 5), 208 - DEF_MOD("sdhi1_clk_hs", R9A08G045_SDHI1_CLK_HS, R9A08G045_CLK_SD1, 0x554, 6), 209 - DEF_MOD("sdhi1_aclk", R9A08G045_SDHI1_ACLK, R9A08G045_CLK_P1, 0x554, 7), 210 - DEF_MOD("sdhi2_imclk", R9A08G045_SDHI2_IMCLK, CLK_SD2_DIV4, 0x554, 8), 211 - DEF_MOD("sdhi2_imclk2", R9A08G045_SDHI2_IMCLK2, CLK_SD2_DIV4, 0x554, 9), 212 - DEF_MOD("sdhi2_clk_hs", R9A08G045_SDHI2_CLK_HS, R9A08G045_CLK_SD2, 0x554, 10), 213 - DEF_MOD("sdhi2_aclk", R9A08G045_SDHI2_ACLK, R9A08G045_CLK_P1, 0x554, 11), 214 - DEF_MOD("ssi0_pclk2", R9A08G045_SSI0_PCLK2, R9A08G045_CLK_P0, 0x570, 0), 215 - DEF_MOD("ssi0_sfr", R9A08G045_SSI0_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 1), 216 - DEF_MOD("ssi1_pclk2", R9A08G045_SSI1_PCLK2, R9A08G045_CLK_P0, 0x570, 2), 217 - DEF_MOD("ssi1_sfr", R9A08G045_SSI1_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 3), 218 - DEF_MOD("ssi2_pclk2", R9A08G045_SSI2_PCLK2, R9A08G045_CLK_P0, 0x570, 4), 219 - DEF_MOD("ssi2_sfr", R9A08G045_SSI2_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 5), 220 - DEF_MOD("ssi3_pclk2", R9A08G045_SSI3_PCLK2, R9A08G045_CLK_P0, 0x570, 6), 221 - DEF_MOD("ssi3_sfr", R9A08G045_SSI3_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 7), 222 - DEF_MOD("usb0_host", R9A08G045_USB_U2H0_HCLK, R9A08G045_CLK_P1, 0x578, 0), 223 - DEF_MOD("usb1_host", R9A08G045_USB_U2H1_HCLK, R9A08G045_CLK_P1, 0x578, 1), 224 - DEF_MOD("usb0_func", R9A08G045_USB_U2P_EXR_CPUCLK, R9A08G045_CLK_P1, 0x578, 2), 225 - DEF_MOD("usb_pclk", R9A08G045_USB_PCLK, R9A08G045_CLK_P1, 0x578, 3), 226 - DEF_COUPLED("eth0_axi", R9A08G045_ETH0_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 0), 227 - DEF_COUPLED("eth0_chi", R9A08G045_ETH0_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 0), 228 - DEF_MOD("eth0_refclk", R9A08G045_ETH0_REFCLK, R9A08G045_CLK_HP, 0x57c, 8), 229 - DEF_COUPLED("eth1_axi", R9A08G045_ETH1_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 1), 230 - DEF_COUPLED("eth1_chi", R9A08G045_ETH1_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 1), 231 - DEF_MOD("eth1_refclk", R9A08G045_ETH1_REFCLK, R9A08G045_CLK_HP, 0x57c, 9), 232 - DEF_MOD("i2c0_pclk", R9A08G045_I2C0_PCLK, R9A08G045_CLK_P0, 0x580, 0), 233 - DEF_MOD("i2c1_pclk", R9A08G045_I2C1_PCLK, R9A08G045_CLK_P0, 0x580, 1), 234 - DEF_MOD("i2c2_pclk", R9A08G045_I2C2_PCLK, R9A08G045_CLK_P0, 0x580, 2), 235 - DEF_MOD("i2c3_pclk", R9A08G045_I2C3_PCLK, R9A08G045_CLK_P0, 0x580, 3), 236 - DEF_MOD("scif0_clk_pck", R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0), 237 - DEF_MOD("scif1_clk_pck", R9A08G045_SCIF1_CLK_PCK, R9A08G045_CLK_P0, 0x584, 1), 238 - DEF_MOD("scif2_clk_pck", R9A08G045_SCIF2_CLK_PCK, R9A08G045_CLK_P0, 0x584, 2), 239 - DEF_MOD("scif3_clk_pck", R9A08G045_SCIF3_CLK_PCK, R9A08G045_CLK_P0, 0x584, 3), 240 - DEF_MOD("scif4_clk_pck", R9A08G045_SCIF4_CLK_PCK, R9A08G045_CLK_P0, 0x584, 4), 241 - DEF_MOD("scif5_clk_pck", R9A08G045_SCIF5_CLK_PCK, R9A08G045_CLK_P0, 0x584, 5), 242 - DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0), 243 - DEF_MOD("adc_adclk", R9A08G045_ADC_ADCLK, R9A08G045_CLK_TSU, 0x5a8, 0), 244 - DEF_MOD("adc_pclk", R9A08G045_ADC_PCLK, R9A08G045_CLK_TSU, 0x5a8, 1), 245 - DEF_MOD("tsu_pclk", R9A08G045_TSU_PCLK, R9A08G045_CLK_TSU, 0x5ac, 0), 246 - DEF_MOD("vbat_bclk", R9A08G045_VBAT_BCLK, R9A08G045_OSCCLK, 0x614, 0), 195 + DEF_MOD("gic_gicclk", R9A08G045_GIC600_GICCLK, R9A08G045_CLK_P1, 0x514, 0, 0), 196 + DEF_MOD("ia55_pclk", R9A08G045_IA55_PCLK, R9A08G045_CLK_P2, 0x518, 0, 0), 197 + DEF_MOD("ia55_clk", R9A08G045_IA55_CLK, R9A08G045_CLK_P1, 0x518, 1, 0), 198 + DEF_MOD("dmac_aclk", R9A08G045_DMAC_ACLK, R9A08G045_CLK_P3, 0x52c, 0, 0), 199 + DEF_MOD("dmac_pclk", R9A08G045_DMAC_PCLK, CLK_P3_DIV2, 0x52c, 1, 0), 200 + DEF_MOD("wdt0_pclk", R9A08G045_WDT0_PCLK, R9A08G045_CLK_P0, 0x548, 0, 0), 201 + DEF_MOD("wdt0_clk", R9A08G045_WDT0_CLK, R9A08G045_OSCCLK, 0x548, 1, 0), 202 + DEF_MOD("sdhi0_imclk", R9A08G045_SDHI0_IMCLK, CLK_SD0_DIV4, 0x554, 0, 0), 203 + DEF_MOD("sdhi0_imclk2", R9A08G045_SDHI0_IMCLK2, CLK_SD0_DIV4, 0x554, 1, 0), 204 + DEF_MOD("sdhi0_clk_hs", R9A08G045_SDHI0_CLK_HS, R9A08G045_CLK_SD0, 0x554, 2, 0), 205 + DEF_MOD("sdhi0_aclk", R9A08G045_SDHI0_ACLK, R9A08G045_CLK_P1, 0x554, 3, 0), 206 + DEF_MOD("sdhi1_imclk", R9A08G045_SDHI1_IMCLK, CLK_SD1_DIV4, 0x554, 4, 0), 207 + DEF_MOD("sdhi1_imclk2", R9A08G045_SDHI1_IMCLK2, CLK_SD1_DIV4, 0x554, 5, 0), 208 + DEF_MOD("sdhi1_clk_hs", R9A08G045_SDHI1_CLK_HS, R9A08G045_CLK_SD1, 0x554, 6, 0), 209 + DEF_MOD("sdhi1_aclk", R9A08G045_SDHI1_ACLK, R9A08G045_CLK_P1, 0x554, 7, 0), 210 + DEF_MOD("sdhi2_imclk", R9A08G045_SDHI2_IMCLK, CLK_SD2_DIV4, 0x554, 8, 0), 211 + DEF_MOD("sdhi2_imclk2", R9A08G045_SDHI2_IMCLK2, CLK_SD2_DIV4, 0x554, 9, 0), 212 + DEF_MOD("sdhi2_clk_hs", R9A08G045_SDHI2_CLK_HS, R9A08G045_CLK_SD2, 0x554, 10, 0), 213 + DEF_MOD("sdhi2_aclk", R9A08G045_SDHI2_ACLK, R9A08G045_CLK_P1, 0x554, 11, 0), 214 + DEF_MOD("ssi0_pclk2", R9A08G045_SSI0_PCLK2, R9A08G045_CLK_P0, 0x570, 0, 0), 215 + DEF_MOD("ssi0_sfr", R9A08G045_SSI0_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 1, 0), 216 + DEF_MOD("ssi1_pclk2", R9A08G045_SSI1_PCLK2, R9A08G045_CLK_P0, 0x570, 2, 0), 217 + DEF_MOD("ssi1_sfr", R9A08G045_SSI1_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 3, 0), 218 + DEF_MOD("ssi2_pclk2", R9A08G045_SSI2_PCLK2, R9A08G045_CLK_P0, 0x570, 4, 0), 219 + DEF_MOD("ssi2_sfr", R9A08G045_SSI2_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 5, 0), 220 + DEF_MOD("ssi3_pclk2", R9A08G045_SSI3_PCLK2, R9A08G045_CLK_P0, 0x570, 6, 0), 221 + DEF_MOD("ssi3_sfr", R9A08G045_SSI3_PCLK_SFR, R9A08G045_CLK_P0, 0x570, 7, 0), 222 + DEF_MOD("usb0_host", R9A08G045_USB_U2H0_HCLK, R9A08G045_CLK_P1, 0x578, 0, 0), 223 + DEF_MOD("usb1_host", R9A08G045_USB_U2H1_HCLK, R9A08G045_CLK_P1, 0x578, 1, 0), 224 + DEF_MOD("usb0_func", R9A08G045_USB_U2P_EXR_CPUCLK, R9A08G045_CLK_P1, 0x578, 2, 225 + 0), 226 + DEF_MOD("usb_pclk", R9A08G045_USB_PCLK, R9A08G045_CLK_P1, 0x578, 3, 0), 227 + DEF_COUPLED("eth0_axi", R9A08G045_ETH0_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 0, 0), 228 + DEF_COUPLED("eth0_chi", R9A08G045_ETH0_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 0, 0), 229 + DEF_MOD("eth0_refclk", R9A08G045_ETH0_REFCLK, R9A08G045_CLK_HP, 0x57c, 8, 0), 230 + DEF_COUPLED("eth1_axi", R9A08G045_ETH1_CLK_AXI, R9A08G045_CLK_M0, 0x57c, 1, 0), 231 + DEF_COUPLED("eth1_chi", R9A08G045_ETH1_CLK_CHI, R9A08G045_CLK_ZT, 0x57c, 1, 0), 232 + DEF_MOD("eth1_refclk", R9A08G045_ETH1_REFCLK, R9A08G045_CLK_HP, 0x57c, 9, 0), 233 + DEF_MOD("i2c0_pclk", R9A08G045_I2C0_PCLK, R9A08G045_CLK_P0, 0x580, 0, 0), 234 + DEF_MOD("i2c1_pclk", R9A08G045_I2C1_PCLK, R9A08G045_CLK_P0, 0x580, 1, 0), 235 + DEF_MOD("i2c2_pclk", R9A08G045_I2C2_PCLK, R9A08G045_CLK_P0, 0x580, 2, 0), 236 + DEF_MOD("i2c3_pclk", R9A08G045_I2C3_PCLK, R9A08G045_CLK_P0, 0x580, 3, 0), 237 + DEF_MOD("scif0_clk_pck", R9A08G045_SCIF0_CLK_PCK, R9A08G045_CLK_P0, 0x584, 0, 0), 238 + DEF_MOD("scif1_clk_pck", R9A08G045_SCIF1_CLK_PCK, R9A08G045_CLK_P0, 0x584, 1, 0), 239 + DEF_MOD("scif2_clk_pck", R9A08G045_SCIF2_CLK_PCK, R9A08G045_CLK_P0, 0x584, 2, 0), 240 + DEF_MOD("scif3_clk_pck", R9A08G045_SCIF3_CLK_PCK, R9A08G045_CLK_P0, 0x584, 3, 0), 241 + DEF_MOD("scif4_clk_pck", R9A08G045_SCIF4_CLK_PCK, R9A08G045_CLK_P0, 0x584, 4, 0), 242 + DEF_MOD("scif5_clk_pck", R9A08G045_SCIF5_CLK_PCK, R9A08G045_CLK_P0, 0x584, 5, 0), 243 + DEF_MOD("gpio_hclk", R9A08G045_GPIO_HCLK, R9A08G045_OSCCLK, 0x598, 0, 0), 244 + DEF_MOD("adc_adclk", R9A08G045_ADC_ADCLK, R9A08G045_CLK_TSU, 0x5a8, 0, 0), 245 + DEF_MOD("adc_pclk", R9A08G045_ADC_PCLK, R9A08G045_CLK_TSU, 0x5a8, 1, 0), 246 + DEF_MOD("tsu_pclk", R9A08G045_TSU_PCLK, R9A08G045_CLK_TSU, 0x5ac, 0, 0), 247 + DEF_MOD("vbat_bclk", R9A08G045_VBAT_BCLK, R9A08G045_OSCCLK, 0x614, 0, 0), 247 248 }; 248 249 249 250 static const struct rzg2l_reset r9a08g045_resets[] = {

+58 -58

drivers/clk/renesas/r9a09g011-cpg.c

··· 151 151 }; 152 152 153 153 static const struct rzg2l_mod_clk r9a09g011_mod_clks[] __initconst = { 154 - DEF_MOD("pfc", R9A09G011_PFC_PCLK, CLK_MAIN, 0x400, 2), 155 - DEF_MOD("gic", R9A09G011_GIC_CLK, CLK_SEL_B_D2, 0x400, 5), 156 - DEF_MOD("sdi0_aclk", R9A09G011_SDI0_ACLK, CLK_SEL_D, 0x408, 0), 157 - DEF_MOD("sdi0_imclk", R9A09G011_SDI0_IMCLK, CLK_SEL_SDI, 0x408, 1), 158 - DEF_MOD("sdi0_imclk2", R9A09G011_SDI0_IMCLK2, CLK_SEL_SDI, 0x408, 2), 159 - DEF_MOD("sdi0_clk_hs", R9A09G011_SDI0_CLK_HS, CLK_PLL2_800, 0x408, 3), 160 - DEF_MOD("sdi1_aclk", R9A09G011_SDI1_ACLK, CLK_SEL_D, 0x408, 4), 161 - DEF_MOD("sdi1_imclk", R9A09G011_SDI1_IMCLK, CLK_SEL_SDI, 0x408, 5), 162 - DEF_MOD("sdi1_imclk2", R9A09G011_SDI1_IMCLK2, CLK_SEL_SDI, 0x408, 6), 163 - DEF_MOD("sdi1_clk_hs", R9A09G011_SDI1_CLK_HS, CLK_PLL2_800, 0x408, 7), 164 - DEF_MOD("emm_aclk", R9A09G011_EMM_ACLK, CLK_SEL_D, 0x408, 8), 165 - DEF_MOD("emm_imclk", R9A09G011_EMM_IMCLK, CLK_SEL_SDI, 0x408, 9), 166 - DEF_MOD("emm_imclk2", R9A09G011_EMM_IMCLK2, CLK_SEL_SDI, 0x408, 10), 167 - DEF_MOD("emm_clk_hs", R9A09G011_EMM_CLK_HS, CLK_PLL2_800, 0x408, 11), 168 - DEF_COUPLED("eth_axi", R9A09G011_ETH0_CLK_AXI, CLK_PLL2_200, 0x40c, 8), 169 - DEF_COUPLED("eth_chi", R9A09G011_ETH0_CLK_CHI, CLK_PLL2_100, 0x40c, 8), 170 - DEF_MOD("eth_clk_gptp", R9A09G011_ETH0_GPTP_EXT, CLK_PLL2_100, 0x40c, 9), 171 - DEF_MOD("usb_aclk_h", R9A09G011_USB_ACLK_H, CLK_SEL_D, 0x40c, 4), 172 - DEF_MOD("usb_aclk_p", R9A09G011_USB_ACLK_P, CLK_SEL_D, 0x40c, 5), 173 - DEF_MOD("usb_pclk", R9A09G011_USB_PCLK, CLK_SEL_E, 0x40c, 6), 174 - DEF_MOD("syc_cnt_clk", R9A09G011_SYC_CNT_CLK, CLK_MAIN_24, 0x41c, 12), 175 - DEF_MOD("iic_pclk0", R9A09G011_IIC_PCLK0, CLK_SEL_E, 0x420, 12), 176 - DEF_MOD("cperi_grpb", R9A09G011_CPERI_GRPB_PCLK, CLK_SEL_E, 0x424, 0), 177 - DEF_MOD("tim_clk_8", R9A09G011_TIM8_CLK, CLK_MAIN_2, 0x424, 4), 178 - DEF_MOD("tim_clk_9", R9A09G011_TIM9_CLK, CLK_MAIN_2, 0x424, 5), 179 - DEF_MOD("tim_clk_10", R9A09G011_TIM10_CLK, CLK_MAIN_2, 0x424, 6), 180 - DEF_MOD("tim_clk_11", R9A09G011_TIM11_CLK, CLK_MAIN_2, 0x424, 7), 181 - DEF_MOD("tim_clk_12", R9A09G011_TIM12_CLK, CLK_MAIN_2, 0x424, 8), 182 - DEF_MOD("tim_clk_13", R9A09G011_TIM13_CLK, CLK_MAIN_2, 0x424, 9), 183 - DEF_MOD("tim_clk_14", R9A09G011_TIM14_CLK, CLK_MAIN_2, 0x424, 10), 184 - DEF_MOD("tim_clk_15", R9A09G011_TIM15_CLK, CLK_MAIN_2, 0x424, 11), 185 - DEF_MOD("iic_pclk1", R9A09G011_IIC_PCLK1, CLK_SEL_E, 0x424, 12), 186 - DEF_MOD("cperi_grpc", R9A09G011_CPERI_GRPC_PCLK, CLK_SEL_E, 0x428, 0), 187 - DEF_MOD("tim_clk_16", R9A09G011_TIM16_CLK, CLK_MAIN_2, 0x428, 4), 188 - DEF_MOD("tim_clk_17", R9A09G011_TIM17_CLK, CLK_MAIN_2, 0x428, 5), 189 - DEF_MOD("tim_clk_18", R9A09G011_TIM18_CLK, CLK_MAIN_2, 0x428, 6), 190 - DEF_MOD("tim_clk_19", R9A09G011_TIM19_CLK, CLK_MAIN_2, 0x428, 7), 191 - DEF_MOD("tim_clk_20", R9A09G011_TIM20_CLK, CLK_MAIN_2, 0x428, 8), 192 - DEF_MOD("tim_clk_21", R9A09G011_TIM21_CLK, CLK_MAIN_2, 0x428, 9), 193 - DEF_MOD("tim_clk_22", R9A09G011_TIM22_CLK, CLK_MAIN_2, 0x428, 10), 194 - DEF_MOD("tim_clk_23", R9A09G011_TIM23_CLK, CLK_MAIN_2, 0x428, 11), 195 - DEF_MOD("wdt0_pclk", R9A09G011_WDT0_PCLK, CLK_SEL_E, 0x428, 12), 196 - DEF_MOD("wdt0_clk", R9A09G011_WDT0_CLK, CLK_MAIN, 0x428, 13), 197 - DEF_MOD("cperi_grpf", R9A09G011_CPERI_GRPF_PCLK, CLK_SEL_E, 0x434, 0), 198 - DEF_MOD("pwm8_clk", R9A09G011_PWM8_CLK, CLK_MAIN, 0x434, 4), 199 - DEF_MOD("pwm9_clk", R9A09G011_PWM9_CLK, CLK_MAIN, 0x434, 5), 200 - DEF_MOD("pwm10_clk", R9A09G011_PWM10_CLK, CLK_MAIN, 0x434, 6), 201 - DEF_MOD("pwm11_clk", R9A09G011_PWM11_CLK, CLK_MAIN, 0x434, 7), 202 - DEF_MOD("pwm12_clk", R9A09G011_PWM12_CLK, CLK_MAIN, 0x434, 8), 203 - DEF_MOD("pwm13_clk", R9A09G011_PWM13_CLK, CLK_MAIN, 0x434, 9), 204 - DEF_MOD("pwm14_clk", R9A09G011_PWM14_CLK, CLK_MAIN, 0x434, 10), 205 - DEF_MOD("cperi_grpg", R9A09G011_CPERI_GRPG_PCLK, CLK_SEL_E, 0x438, 0), 206 - DEF_MOD("cperi_grph", R9A09G011_CPERI_GRPH_PCLK, CLK_SEL_E, 0x438, 1), 207 - DEF_MOD("urt_pclk", R9A09G011_URT_PCLK, CLK_SEL_E, 0x438, 4), 208 - DEF_MOD("urt0_clk", R9A09G011_URT0_CLK, CLK_SEL_W0, 0x438, 5), 209 - DEF_MOD("csi0_clk", R9A09G011_CSI0_CLK, CLK_SEL_CSI0, 0x438, 8), 210 - DEF_MOD("csi4_clk", R9A09G011_CSI4_CLK, CLK_SEL_CSI4, 0x438, 12), 211 - DEF_MOD("ca53", R9A09G011_CA53_CLK, CLK_DIV_A, 0x448, 0), 154 + DEF_MOD("pfc", R9A09G011_PFC_PCLK, CLK_MAIN, 0x400, 2, 0), 155 + DEF_MOD("gic", R9A09G011_GIC_CLK, CLK_SEL_B_D2, 0x400, 5, 0), 156 + DEF_MOD("sdi0_aclk", R9A09G011_SDI0_ACLK, CLK_SEL_D, 0x408, 0, 0), 157 + DEF_MOD("sdi0_imclk", R9A09G011_SDI0_IMCLK, CLK_SEL_SDI, 0x408, 1, 0), 158 + DEF_MOD("sdi0_imclk2", R9A09G011_SDI0_IMCLK2, CLK_SEL_SDI, 0x408, 2, 0), 159 + DEF_MOD("sdi0_clk_hs", R9A09G011_SDI0_CLK_HS, CLK_PLL2_800, 0x408, 3, 0), 160 + DEF_MOD("sdi1_aclk", R9A09G011_SDI1_ACLK, CLK_SEL_D, 0x408, 4, 0), 161 + DEF_MOD("sdi1_imclk", R9A09G011_SDI1_IMCLK, CLK_SEL_SDI, 0x408, 5, 0), 162 + DEF_MOD("sdi1_imclk2", R9A09G011_SDI1_IMCLK2, CLK_SEL_SDI, 0x408, 6, 0), 163 + DEF_MOD("sdi1_clk_hs", R9A09G011_SDI1_CLK_HS, CLK_PLL2_800, 0x408, 7, 0), 164 + DEF_MOD("emm_aclk", R9A09G011_EMM_ACLK, CLK_SEL_D, 0x408, 8, 0), 165 + DEF_MOD("emm_imclk", R9A09G011_EMM_IMCLK, CLK_SEL_SDI, 0x408, 9, 0), 166 + DEF_MOD("emm_imclk2", R9A09G011_EMM_IMCLK2, CLK_SEL_SDI, 0x408, 10, 0), 167 + DEF_MOD("emm_clk_hs", R9A09G011_EMM_CLK_HS, CLK_PLL2_800, 0x408, 11, 0), 168 + DEF_COUPLED("eth_axi", R9A09G011_ETH0_CLK_AXI, CLK_PLL2_200, 0x40c, 8, 0), 169 + DEF_COUPLED("eth_chi", R9A09G011_ETH0_CLK_CHI, CLK_PLL2_100, 0x40c, 8, 0), 170 + DEF_MOD("eth_clk_gptp", R9A09G011_ETH0_GPTP_EXT, CLK_PLL2_100, 0x40c, 9, 0), 171 + DEF_MOD("usb_aclk_h", R9A09G011_USB_ACLK_H, CLK_SEL_D, 0x40c, 4, 0), 172 + DEF_MOD("usb_aclk_p", R9A09G011_USB_ACLK_P, CLK_SEL_D, 0x40c, 5, 0), 173 + DEF_MOD("usb_pclk", R9A09G011_USB_PCLK, CLK_SEL_E, 0x40c, 6, 0), 174 + DEF_MOD("syc_cnt_clk", R9A09G011_SYC_CNT_CLK, CLK_MAIN_24, 0x41c, 12, 0), 175 + DEF_MOD("iic_pclk0", R9A09G011_IIC_PCLK0, CLK_SEL_E, 0x420, 12, 0), 176 + DEF_MOD("cperi_grpb", R9A09G011_CPERI_GRPB_PCLK, CLK_SEL_E, 0x424, 0, 0), 177 + DEF_MOD("tim_clk_8", R9A09G011_TIM8_CLK, CLK_MAIN_2, 0x424, 4, 0), 178 + DEF_MOD("tim_clk_9", R9A09G011_TIM9_CLK, CLK_MAIN_2, 0x424, 5, 0), 179 + DEF_MOD("tim_clk_10", R9A09G011_TIM10_CLK, CLK_MAIN_2, 0x424, 6, 0), 180 + DEF_MOD("tim_clk_11", R9A09G011_TIM11_CLK, CLK_MAIN_2, 0x424, 7, 0), 181 + DEF_MOD("tim_clk_12", R9A09G011_TIM12_CLK, CLK_MAIN_2, 0x424, 8, 0), 182 + DEF_MOD("tim_clk_13", R9A09G011_TIM13_CLK, CLK_MAIN_2, 0x424, 9, 0), 183 + DEF_MOD("tim_clk_14", R9A09G011_TIM14_CLK, CLK_MAIN_2, 0x424, 10, 0), 184 + DEF_MOD("tim_clk_15", R9A09G011_TIM15_CLK, CLK_MAIN_2, 0x424, 11, 0), 185 + DEF_MOD("iic_pclk1", R9A09G011_IIC_PCLK1, CLK_SEL_E, 0x424, 12, 0), 186 + DEF_MOD("cperi_grpc", R9A09G011_CPERI_GRPC_PCLK, CLK_SEL_E, 0x428, 0, 0), 187 + DEF_MOD("tim_clk_16", R9A09G011_TIM16_CLK, CLK_MAIN_2, 0x428, 4, 0), 188 + DEF_MOD("tim_clk_17", R9A09G011_TIM17_CLK, CLK_MAIN_2, 0x428, 5, 0), 189 + DEF_MOD("tim_clk_18", R9A09G011_TIM18_CLK, CLK_MAIN_2, 0x428, 6, 0), 190 + DEF_MOD("tim_clk_19", R9A09G011_TIM19_CLK, CLK_MAIN_2, 0x428, 7, 0), 191 + DEF_MOD("tim_clk_20", R9A09G011_TIM20_CLK, CLK_MAIN_2, 0x428, 8, 0), 192 + DEF_MOD("tim_clk_21", R9A09G011_TIM21_CLK, CLK_MAIN_2, 0x428, 9, 0), 193 + DEF_MOD("tim_clk_22", R9A09G011_TIM22_CLK, CLK_MAIN_2, 0x428, 10, 0), 194 + DEF_MOD("tim_clk_23", R9A09G011_TIM23_CLK, CLK_MAIN_2, 0x428, 11, 0), 195 + DEF_MOD("wdt0_pclk", R9A09G011_WDT0_PCLK, CLK_SEL_E, 0x428, 12, 0), 196 + DEF_MOD("wdt0_clk", R9A09G011_WDT0_CLK, CLK_MAIN, 0x428, 13, 0), 197 + DEF_MOD("cperi_grpf", R9A09G011_CPERI_GRPF_PCLK, CLK_SEL_E, 0x434, 0, 0), 198 + DEF_MOD("pwm8_clk", R9A09G011_PWM8_CLK, CLK_MAIN, 0x434, 4, 0), 199 + DEF_MOD("pwm9_clk", R9A09G011_PWM9_CLK, CLK_MAIN, 0x434, 5, 0), 200 + DEF_MOD("pwm10_clk", R9A09G011_PWM10_CLK, CLK_MAIN, 0x434, 6, 0), 201 + DEF_MOD("pwm11_clk", R9A09G011_PWM11_CLK, CLK_MAIN, 0x434, 7, 0), 202 + DEF_MOD("pwm12_clk", R9A09G011_PWM12_CLK, CLK_MAIN, 0x434, 8, 0), 203 + DEF_MOD("pwm13_clk", R9A09G011_PWM13_CLK, CLK_MAIN, 0x434, 9, 0), 204 + DEF_MOD("pwm14_clk", R9A09G011_PWM14_CLK, CLK_MAIN, 0x434, 10, 0), 205 + DEF_MOD("cperi_grpg", R9A09G011_CPERI_GRPG_PCLK, CLK_SEL_E, 0x438, 0, 0), 206 + DEF_MOD("cperi_grph", R9A09G011_CPERI_GRPH_PCLK, CLK_SEL_E, 0x438, 1, 0), 207 + DEF_MOD("urt_pclk", R9A09G011_URT_PCLK, CLK_SEL_E, 0x438, 4, 0), 208 + DEF_MOD("urt0_clk", R9A09G011_URT0_CLK, CLK_SEL_W0, 0x438, 5, 0), 209 + DEF_MOD("csi0_clk", R9A09G011_CSI0_CLK, CLK_SEL_CSI0, 0x438, 8, 0), 210 + DEF_MOD("csi4_clk", R9A09G011_CSI4_CLK, CLK_SEL_CSI4, 0x438, 12, 0), 211 + DEF_MOD("ca53", R9A09G011_CA53_CLK, CLK_DIV_A, 0x448, 0, 0), 212 212 }; 213 213 214 214 static const struct rzg2l_reset r9a09g011_resets[] = {

+246 -1

drivers/clk/renesas/rzg2l-cpg.c

··· 11 11 * Copyright (C) 2015 Renesas Electronics Corp. 12 12 */ 13 13 14 + #include <linux/atomic.h> 14 15 #include <linux/bitfield.h> 16 + #include <linux/cleanup.h> 15 17 #include <linux/clk.h> 16 18 #include <linux/clk-provider.h> 17 19 #include <linux/clk/renesas.h> 20 + #include <linux/debugfs.h> 18 21 #include <linux/delay.h> 19 22 #include <linux/device.h> 20 23 #include <linux/init.h> ··· 70 67 #define CPG_WEN_BIT BIT(16) 71 68 72 69 #define MAX_VCLK_FREQ (148500000) 70 + 71 + #define MSTOP_OFF(conf) FIELD_GET(GENMASK(31, 16), (conf)) 72 + #define MSTOP_MASK(conf) FIELD_GET(GENMASK(15, 0), (conf)) 73 73 74 74 /** 75 75 * struct clk_hw_data - clock hardware data ··· 1188 1182 } 1189 1183 1190 1184 /** 1185 + * struct mstop - MSTOP specific data structure 1186 + * @usecnt: Usage counter for MSTOP settings (when zero the settings 1187 + * are applied to register) 1188 + * @conf: MSTOP configuration (register offset, setup bits) 1189 + */ 1190 + struct mstop { 1191 + atomic_t usecnt; 1192 + u32 conf; 1193 + }; 1194 + 1195 + /** 1191 1196 * struct mstp_clock - MSTP gating clock 1192 1197 * 1193 1198 * @hw: handle between common and hardware-specific interfaces 1194 1199 * @priv: CPG/MSTP private data 1195 1200 * @sibling: pointer to the other coupled clock 1201 + * @mstop: MSTOP configuration 1202 + * @shared_mstop_clks: clocks sharing the MSTOP with this clock 1196 1203 * @off: register offset 1197 1204 * @bit: ON/MON bit 1205 + * @num_shared_mstop_clks: number of the clocks sharing MSTOP with this clock 1198 1206 * @enabled: soft state of the clock, if it is coupled with another clock 1199 1207 */ 1200 1208 struct mstp_clock { 1201 1209 struct clk_hw hw; 1202 1210 struct rzg2l_cpg_priv *priv; 1203 1211 struct mstp_clock *sibling; 1212 + struct mstop *mstop; 1213 + struct mstp_clock **shared_mstop_clks; 1204 1214 u16 off; 1205 1215 u8 bit; 1216 + u8 num_shared_mstop_clks; 1206 1217 bool enabled; 1207 1218 }; 1208 1219 ··· 1231 1208 continue; \ 1232 1209 else if (((hw) = __clk_get_hw((priv)->clks[(priv)->num_core_clks + i])) && \ 1233 1210 ((mod_clock) = to_mod_clock(hw))) 1211 + 1212 + /* Need to be called with a lock held to avoid concurrent access to mstop->usecnt. */ 1213 + static void rzg2l_mod_clock_module_set_state(struct mstp_clock *clock, 1214 + bool standby) 1215 + { 1216 + struct rzg2l_cpg_priv *priv = clock->priv; 1217 + struct mstop *mstop = clock->mstop; 1218 + bool update = false; 1219 + u32 value; 1220 + 1221 + if (!mstop) 1222 + return; 1223 + 1224 + value = MSTOP_MASK(mstop->conf) << 16; 1225 + 1226 + if (standby) { 1227 + unsigned int criticals = 0; 1228 + 1229 + for (unsigned int i = 0; i < clock->num_shared_mstop_clks; i++) { 1230 + struct mstp_clock *clk = clock->shared_mstop_clks[i]; 1231 + 1232 + if (clk_hw_get_flags(&clk->hw) & CLK_IS_CRITICAL) 1233 + criticals++; 1234 + } 1235 + 1236 + if (!clock->num_shared_mstop_clks && 1237 + clk_hw_get_flags(&clock->hw) & CLK_IS_CRITICAL) 1238 + criticals++; 1239 + 1240 + /* 1241 + * If this is a shared MSTOP and it is shared with critical clocks, 1242 + * and the system boots up with this clock enabled but no driver 1243 + * uses it the CCF will disable it (as it is unused). As we don't 1244 + * increment reference counter for it at registration (to avoid 1245 + * messing with clocks enabled at probe but later used by drivers) 1246 + * do not set the MSTOP here too if it is shared with critical 1247 + * clocks and ref counted only by those critical clocks. 1248 + */ 1249 + if (criticals && criticals == atomic_read(&mstop->usecnt)) 1250 + return; 1251 + 1252 + value |= MSTOP_MASK(mstop->conf); 1253 + 1254 + /* Allow updates on probe when usecnt = 0. */ 1255 + if (!atomic_read(&mstop->usecnt)) 1256 + update = true; 1257 + else 1258 + update = atomic_dec_and_test(&mstop->usecnt); 1259 + } else { 1260 + if (!atomic_read(&mstop->usecnt)) 1261 + update = true; 1262 + atomic_inc(&mstop->usecnt); 1263 + } 1264 + 1265 + if (update) 1266 + writel(value, priv->base + MSTOP_OFF(mstop->conf)); 1267 + } 1268 + 1269 + static int rzg2l_mod_clock_mstop_show(struct seq_file *s, void *what) 1270 + { 1271 + struct rzg2l_cpg_priv *priv = s->private; 1272 + struct mstp_clock *clk; 1273 + struct clk_hw *hw; 1274 + 1275 + seq_printf(s, "%-20s %-5s %-10s\n", "", "", "MSTOP"); 1276 + seq_printf(s, "%-20s %-5s %-10s\n", "", "clk", "-------------------------"); 1277 + seq_printf(s, "%-20s %-5s %-5s %-5s %-6s %-6s\n", 1278 + "clk_name", "cnt", "cnt", "off", "val", "shared"); 1279 + seq_printf(s, "%-20s %-5s %-5s %-5s %-6s %-6s\n", 1280 + "--------", "-----", "-----", "-----", "------", "------"); 1281 + 1282 + for_each_mod_clock(clk, hw, priv) { 1283 + u32 val; 1284 + 1285 + if (!clk->mstop) 1286 + continue; 1287 + 1288 + val = readl(priv->base + MSTOP_OFF(clk->mstop->conf)) & 1289 + MSTOP_MASK(clk->mstop->conf); 1290 + 1291 + seq_printf(s, "%-20s %-5d %-5d 0x%-3lx 0x%-4x", clk_hw_get_name(hw), 1292 + __clk_get_enable_count(hw->clk), atomic_read(&clk->mstop->usecnt), 1293 + MSTOP_OFF(clk->mstop->conf), val); 1294 + 1295 + for (unsigned int i = 0; i < clk->num_shared_mstop_clks; i++) 1296 + seq_printf(s, " %pC", clk->shared_mstop_clks[i]->hw.clk); 1297 + 1298 + seq_puts(s, "\n"); 1299 + } 1300 + 1301 + return 0; 1302 + } 1303 + DEFINE_SHOW_ATTRIBUTE(rzg2l_mod_clock_mstop); 1234 1304 1235 1305 static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable) 1236 1306 { ··· 1347 1231 if (enable) 1348 1232 value |= bitmask; 1349 1233 1350 - writel(value, priv->base + CLK_ON_R(reg)); 1234 + scoped_guard(spinlock_irqsave, &priv->rmw_lock) { 1235 + if (enable) { 1236 + writel(value, priv->base + CLK_ON_R(reg)); 1237 + rzg2l_mod_clock_module_set_state(clock, false); 1238 + } else { 1239 + rzg2l_mod_clock_module_set_state(clock, true); 1240 + writel(value, priv->base + CLK_ON_R(reg)); 1241 + } 1242 + } 1351 1243 1352 1244 if (!enable) 1353 1245 return 0; ··· 1456 1332 return NULL; 1457 1333 } 1458 1334 1335 + static struct mstop *rzg2l_mod_clock_get_mstop(struct rzg2l_cpg_priv *priv, u32 conf) 1336 + { 1337 + struct mstp_clock *clk; 1338 + struct clk_hw *hw; 1339 + 1340 + for_each_mod_clock(clk, hw, priv) { 1341 + if (!clk->mstop) 1342 + continue; 1343 + 1344 + if (clk->mstop->conf == conf) 1345 + return clk->mstop; 1346 + } 1347 + 1348 + return NULL; 1349 + } 1350 + 1351 + static void rzg2l_mod_clock_init_mstop(struct rzg2l_cpg_priv *priv) 1352 + { 1353 + struct mstp_clock *clk; 1354 + struct clk_hw *hw; 1355 + 1356 + for_each_mod_clock(clk, hw, priv) { 1357 + if (!clk->mstop) 1358 + continue; 1359 + 1360 + /* 1361 + * Out of reset all modules are enabled. Set module state 1362 + * in case associated clocks are disabled at probe. Otherwise 1363 + * module is in invalid HW state. 1364 + */ 1365 + scoped_guard(spinlock_irqsave, &priv->rmw_lock) { 1366 + if (!rzg2l_mod_clock_is_enabled(&clk->hw)) 1367 + rzg2l_mod_clock_module_set_state(clk, true); 1368 + } 1369 + } 1370 + } 1371 + 1372 + static int rzg2l_mod_clock_update_shared_mstop_clks(struct rzg2l_cpg_priv *priv, 1373 + struct mstp_clock *clock) 1374 + { 1375 + struct mstp_clock *clk; 1376 + struct clk_hw *hw; 1377 + 1378 + if (!clock->mstop) 1379 + return 0; 1380 + 1381 + for_each_mod_clock(clk, hw, priv) { 1382 + int num_shared_mstop_clks, incr = 1; 1383 + struct mstp_clock **new_clks; 1384 + 1385 + if (clk->mstop != clock->mstop) 1386 + continue; 1387 + 1388 + num_shared_mstop_clks = clk->num_shared_mstop_clks; 1389 + if (!num_shared_mstop_clks) 1390 + incr++; 1391 + 1392 + new_clks = devm_krealloc(priv->dev, clk->shared_mstop_clks, 1393 + (num_shared_mstop_clks + incr) * sizeof(*new_clks), 1394 + GFP_KERNEL); 1395 + if (!new_clks) 1396 + return -ENOMEM; 1397 + 1398 + if (!num_shared_mstop_clks) 1399 + new_clks[num_shared_mstop_clks++] = clk; 1400 + new_clks[num_shared_mstop_clks++] = clock; 1401 + 1402 + for (unsigned int i = 0; i < num_shared_mstop_clks; i++) { 1403 + new_clks[i]->shared_mstop_clks = new_clks; 1404 + new_clks[i]->num_shared_mstop_clks = num_shared_mstop_clks; 1405 + } 1406 + break; 1407 + } 1408 + 1409 + return 0; 1410 + } 1411 + 1459 1412 static void __init 1460 1413 rzg2l_cpg_register_mod_clk(const struct rzg2l_mod_clk *mod, 1461 1414 const struct rzg2l_cpg_info *info, ··· 1584 1383 clock->priv = priv; 1585 1384 clock->hw.init = &init; 1586 1385 1386 + if (mod->mstop_conf) { 1387 + struct mstop *mstop = rzg2l_mod_clock_get_mstop(priv, mod->mstop_conf); 1388 + 1389 + if (!mstop) { 1390 + mstop = devm_kzalloc(dev, sizeof(*mstop), GFP_KERNEL); 1391 + if (!mstop) { 1392 + clk = ERR_PTR(-ENOMEM); 1393 + goto fail; 1394 + } 1395 + mstop->conf = mod->mstop_conf; 1396 + atomic_set(&mstop->usecnt, 0); 1397 + } 1398 + clock->mstop = mstop; 1399 + } 1400 + 1587 1401 ret = devm_clk_hw_register(dev, &clock->hw); 1588 1402 if (ret) { 1589 1403 clk = ERR_PTR(ret); ··· 1614 1398 clock->sibling = sibling; 1615 1399 sibling->sibling = clock; 1616 1400 } 1401 + } 1402 + 1403 + /* Keep this before priv->clks[id] is updated. */ 1404 + ret = rzg2l_mod_clock_update_shared_mstop_clks(priv, clock); 1405 + if (ret) { 1406 + clk = ERR_PTR(ret); 1407 + goto fail; 1617 1408 } 1618 1409 1619 1410 clk = clock->hw.clk; ··· 2098 1875 for (i = 0; i < info->num_mod_clks; i++) 2099 1876 rzg2l_cpg_register_mod_clk(&info->mod_clks[i], info, priv); 2100 1877 1878 + /* 1879 + * Initialize MSTOP after all the clocks were registered to avoid 1880 + * invalid reference counting when multiple clocks (critical, 1881 + * non-critical) share the same MSTOP. 1882 + */ 1883 + rzg2l_mod_clock_init_mstop(priv); 1884 + 2101 1885 error = of_clk_add_provider(np, rzg2l_cpg_clk_src_twocell_get, priv); 2102 1886 if (error) 2103 1887 return error; ··· 2121 1891 if (error) 2122 1892 return error; 2123 1893 1894 + debugfs_create_file("mstop", 0444, NULL, priv, &rzg2l_mod_clock_mstop_fops); 2124 1895 return 0; 2125 1896 } 1897 + 1898 + static int rzg2l_cpg_resume(struct device *dev) 1899 + { 1900 + struct rzg2l_cpg_priv *priv = dev_get_drvdata(dev); 1901 + 1902 + rzg2l_mod_clock_init_mstop(priv); 1903 + 1904 + return 0; 1905 + } 1906 + 1907 + static const struct dev_pm_ops rzg2l_cpg_pm_ops = { 1908 + NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, rzg2l_cpg_resume) 1909 + }; 2126 1910 2127 1911 static const struct of_device_id rzg2l_cpg_match[] = { 2128 1912 #ifdef CONFIG_CLK_R9A07G043 ··· 2176 1932 .driver = { 2177 1933 .name = "rzg2l-cpg", 2178 1934 .of_match_table = rzg2l_cpg_match, 1935 + .pm = pm_sleep_ptr(&rzg2l_cpg_pm_ops), 2179 1936 }, 2180 1937 }; 2181 1938

+10 -5

drivers/clk/renesas/rzg2l-cpg.h

··· 82 82 #define SEL_PLL6_2 SEL_PLL_PACK(CPG_PL6_ETH_SSEL, 0, 1) 83 83 #define SEL_GPU2 SEL_PLL_PACK(CPG_PL6_SSEL, 12, 1) 84 84 85 + #define MSTOP(name, bitmask) ((CPG_##name##_MSTOP) << 16 | (bitmask)) 86 + 85 87 #define EXTAL_FREQ_IN_MEGA_HZ (24) 86 88 87 89 /** ··· 203 201 * @name: handle between common and hardware-specific interfaces 204 202 * @id: clock index in array containing all Core and Module Clocks 205 203 * @parent: id of parent clock 204 + * @mstop_conf: MSTOP configuration 206 205 * @off: register offset 207 206 * @bit: ON/MON bit 208 207 * @is_coupled: flag to indicate coupled clock ··· 212 209 const char *name; 213 210 unsigned int id; 214 211 unsigned int parent; 212 + u32 mstop_conf; 215 213 u16 off; 216 214 u8 bit; 217 215 bool is_coupled; 218 216 }; 219 217 220 - #define DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _is_coupled) \ 218 + #define DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _mstop_conf, _is_coupled) \ 221 219 { \ 222 220 .name = _name, \ 223 221 .id = MOD_CLK_BASE + (_id), \ 224 222 .parent = (_parent), \ 223 + .mstop_conf = (_mstop_conf), \ 225 224 .off = (_off), \ 226 225 .bit = (_bit), \ 227 226 .is_coupled = (_is_coupled), \ 228 227 } 229 228 230 - #define DEF_MOD(_name, _id, _parent, _off, _bit) \ 231 - DEF_MOD_BASE(_name, _id, _parent, _off, _bit, false) 229 + #define DEF_MOD(_name, _id, _parent, _off, _bit, _mstop_conf) \ 230 + DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _mstop_conf, false) 232 231 233 - #define DEF_COUPLED(_name, _id, _parent, _off, _bit) \ 234 - DEF_MOD_BASE(_name, _id, _parent, _off, _bit, true) 232 + #define DEF_COUPLED(_name, _id, _parent, _off, _bit, _mstop_conf) \ 233 + DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _mstop_conf, true) 235 234 236 235 /** 237 236 * struct rzg2l_reset - Reset definitions

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