Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

+6 -5

arch/x86/events/core.c

··· 2319 2319 perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs) 2320 2320 { 2321 2321 struct stack_frame frame; 2322 - const void __user *fp; 2322 + const unsigned long __user *fp; 2323 2323 2324 2324 if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { 2325 2325 /* TODO: We don't support guest os callchain now */ ··· 2332 2332 if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM)) 2333 2333 return; 2334 2334 2335 - fp = (void __user *)regs->bp; 2335 + fp = (unsigned long __user *)regs->bp; 2336 2336 2337 2337 perf_callchain_store(entry, regs->ip); 2338 2338 ··· 2345 2345 pagefault_disable(); 2346 2346 while (entry->nr < entry->max_stack) { 2347 2347 unsigned long bytes; 2348 + 2348 2349 frame.next_frame = NULL; 2349 2350 frame.return_address = 0; 2350 2351 2351 - if (!access_ok(VERIFY_READ, fp, 16)) 2352 + if (!access_ok(VERIFY_READ, fp, sizeof(*fp) * 2)) 2352 2353 break; 2353 2354 2354 - bytes = __copy_from_user_nmi(&frame.next_frame, fp, 8); 2355 + bytes = __copy_from_user_nmi(&frame.next_frame, fp, sizeof(*fp)); 2355 2356 if (bytes != 0) 2356 2357 break; 2357 - bytes = __copy_from_user_nmi(&frame.return_address, fp+8, 8); 2358 + bytes = __copy_from_user_nmi(&frame.return_address, fp + 1, sizeof(*fp)); 2358 2359 if (bytes != 0) 2359 2360 break; 2360 2361

+2 -2

arch/x86/events/intel/Makefile

··· 1 1 obj-$(CONFIG_CPU_SUP_INTEL) += core.o bts.o cqm.o 2 2 obj-$(CONFIG_CPU_SUP_INTEL) += ds.o knc.o 3 3 obj-$(CONFIG_CPU_SUP_INTEL) += lbr.o p4.o p6.o pt.o 4 - obj-$(CONFIG_PERF_EVENTS_INTEL_RAPL) += intel-rapl.o 5 - intel-rapl-objs := rapl.o 4 + obj-$(CONFIG_PERF_EVENTS_INTEL_RAPL) += intel-rapl-perf.o 5 + intel-rapl-perf-objs := rapl.o 6 6 obj-$(CONFIG_PERF_EVENTS_INTEL_UNCORE) += intel-uncore.o 7 7 intel-uncore-objs := uncore.o uncore_nhmex.o uncore_snb.o uncore_snbep.o 8 8 obj-$(CONFIG_PERF_EVENTS_INTEL_CSTATE) += intel-cstate.o

+29

arch/x86/events/intel/core.c

··· 115 115 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */ 116 116 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */ 117 117 118 + /* 119 + * When HT is off these events can only run on the bottom 4 counters 120 + * When HT is on, they are impacted by the HT bug and require EXCL access 121 + */ 118 122 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 119 123 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 120 124 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ ··· 143 139 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */ 144 140 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */ 145 141 142 + /* 143 + * When HT is off these events can only run on the bottom 4 counters 144 + * When HT is on, they are impacted by the HT bug and require EXCL access 145 + */ 146 146 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 147 147 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 148 148 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ ··· 190 182 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */ 191 183 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 192 184 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */ 185 + 186 + /* 187 + * when HT is off, these can only run on the bottom 4 counters 188 + */ 189 + INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 190 + INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 191 + INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 192 + INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 193 + INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */ 194 + 193 195 EVENT_CONSTRAINT_END 194 196 }; 195 197 ··· 268 250 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */ 269 251 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), 270 252 253 + /* 254 + * When HT is off these events can only run on the bottom 4 counters 255 + * When HT is on, they are impacted by the HT bug and require EXCL access 256 + */ 271 257 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */ 272 258 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */ 273 259 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */ ··· 286 264 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */ 287 265 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */ 288 266 INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */ 267 + /* 268 + * when HT is off, these can only run on the bottom 4 counters 269 + */ 270 + INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */ 271 + INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */ 272 + INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */ 273 + INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */ 289 274 EVENT_CONSTRAINT_END 290 275 }; 291 276

+22 -1

kernel/events/core.c

··· 1678 1678 return event->state == PERF_EVENT_STATE_DEAD; 1679 1679 } 1680 1680 1681 - static inline int pmu_filter_match(struct perf_event *event) 1681 + static inline int __pmu_filter_match(struct perf_event *event) 1682 1682 { 1683 1683 struct pmu *pmu = event->pmu; 1684 1684 return pmu->filter_match ? pmu->filter_match(event) : 1; 1685 + } 1686 + 1687 + /* 1688 + * Check whether we should attempt to schedule an event group based on 1689 + * PMU-specific filtering. An event group can consist of HW and SW events, 1690 + * potentially with a SW leader, so we must check all the filters, to 1691 + * determine whether a group is schedulable: 1692 + */ 1693 + static inline int pmu_filter_match(struct perf_event *event) 1694 + { 1695 + struct perf_event *child; 1696 + 1697 + if (!__pmu_filter_match(event)) 1698 + return 0; 1699 + 1700 + list_for_each_entry(child, &event->sibling_list, group_entry) { 1701 + if (!__pmu_filter_match(child)) 1702 + return 0; 1703 + } 1704 + 1705 + return 1; 1685 1706 } 1686 1707 1687 1708 static inline int

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