Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
phy: eswin: Create eswin directory and add EIC7700 SATA PHY driver
Create the eswin phy driver directory and add support for the
SATA PHY driver on the EIC7700 SoC platform.
Signed-off-by: Yulin Lu <luyulin@eswincomputing.com>
Link: https://patch.msgid.link/20260205082219.1521-1-luyulin@eswincomputing.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Yulin Lu
and committed by
Vinod Koul
67ee9cca
820265f7
+291
+1
drivers/phy/Kconfig
+1
drivers/phy/Kconfig
···
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source "drivers/phy/broadcom/Kconfig"
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source "drivers/phy/cadence/Kconfig"
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source "drivers/phy/canaan/Kconfig"
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source "drivers/phy/eswin/Kconfig"
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source "drivers/phy/freescale/Kconfig"
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source "drivers/phy/hisilicon/Kconfig"
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source "drivers/phy/ingenic/Kconfig"
+1
drivers/phy/Makefile
+1
drivers/phy/Makefile
+14
drivers/phy/eswin/Kconfig
+14
drivers/phy/eswin/Kconfig
···
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# SPDX-License-Identifier: GPL-2.0-only
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#
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# Phy drivers for ESWIN platforms
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#
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config PHY_EIC7700_SATA
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tristate "eic7700 Sata SerDes/PHY driver"
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depends on ARCH_ESWIN || COMPILE_TEST
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depends on HAS_IOMEM
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select GENERIC_PHY
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help
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Enable this to support SerDes/Phy found on ESWIN's
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EIC7700 SoC. This Phy supports SATA 1.5 Gb/s,
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SATA 3.0 Gb/s, SATA 6.0 Gb/s speeds.
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It supports one SATA host port to accept one SATA device.
+2
drivers/phy/eswin/Makefile
+2
drivers/phy/eswin/Makefile
+273
drivers/phy/eswin/phy-eic7700-sata.c
+273
drivers/phy/eswin/phy-eic7700-sata.c
···
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// SPDX-License-Identifier: GPL-2.0
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/*
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* ESWIN SATA PHY driver
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*
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* Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd..
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* All rights reserved.
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*
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* Authors: Yulin Lu <luyulin@eswincomputing.com>
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#define SATA_AXI_LP_CTRL 0x08
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#define SATA_MPLL_CTRL 0x20
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#define SATA_P0_PHY_STAT 0x24
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#define SATA_PHY_CTRL0 0x28
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#define SATA_PHY_CTRL1 0x2c
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#define SATA_REF_CTRL 0x34
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#define SATA_REF_CTRL1 0x38
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#define SATA_LOS_IDEN 0x3c
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#define SATA_CLK_RST_SOURCE_PHY BIT(0)
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#define SATA_P0_PHY_TX_AMPLITUDE_GEN1_MASK GENMASK(6, 0)
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#define SATA_P0_PHY_TX_AMPLITUDE_GEN1_DEFAULT 0x42
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#define SATA_P0_PHY_TX_AMPLITUDE_GEN2_MASK GENMASK(14, 8)
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#define SATA_P0_PHY_TX_AMPLITUDE_GEN2_DEFAULT 0x46
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#define SATA_P0_PHY_TX_AMPLITUDE_GEN3_MASK GENMASK(22, 16)
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#define SATA_P0_PHY_TX_AMPLITUDE_GEN3_DEFAULT 0x73
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#define SATA_P0_PHY_TX_PREEMPH_GEN1_MASK GENMASK(5, 0)
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#define SATA_P0_PHY_TX_PREEMPH_GEN1_DEFAULT 0x5
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#define SATA_P0_PHY_TX_PREEMPH_GEN2_MASK GENMASK(13, 8)
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#define SATA_P0_PHY_TX_PREEMPH_GEN2_DEFAULT 0x5
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#define SATA_P0_PHY_TX_PREEMPH_GEN3_MASK GENMASK(21, 16)
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#define SATA_P0_PHY_TX_PREEMPH_GEN3_DEFAULT 0x23
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#define SATA_LOS_LEVEL_MASK GENMASK(4, 0)
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#define SATA_LOS_BIAS_MASK GENMASK(18, 16)
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#define SATA_M_CSYSREQ BIT(0)
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#define SATA_S_CSYSREQ BIT(16)
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#define SATA_REF_REPEATCLK_EN BIT(0)
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#define SATA_REF_USE_PAD BIT(20)
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#define SATA_MPLL_MULTIPLIER_MASK GENMASK(22, 16)
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#define SATA_P0_PHY_READY BIT(0)
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#define PLL_LOCK_SLEEP_US 10
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#define PLL_LOCK_TIMEOUT_US 1000
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+
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struct eic7700_sata_phy {
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u32 tx_amplitude_tuning_val[3];
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u32 tx_preemph_tuning_val[3];
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struct reset_control *rst;
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struct regmap *regmap;
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struct clk *clk;
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struct phy *phy;
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};
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static const struct regmap_config eic7700_sata_phy_regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = SATA_LOS_IDEN,
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};
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static int wait_for_phy_ready(struct regmap *regmap, u32 reg, u32 checkbit,
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u32 status)
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{
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u32 val;
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int ret;
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ret = regmap_read_poll_timeout(regmap, reg, val,
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(val & checkbit) == status,
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PLL_LOCK_SLEEP_US, PLL_LOCK_TIMEOUT_US);
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return ret;
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}
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static int eic7700_sata_phy_init(struct phy *phy)
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{
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struct eic7700_sata_phy *sata_phy = phy_get_drvdata(phy);
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u32 val;
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int ret;
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ret = clk_prepare_enable(sata_phy->clk);
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if (ret)
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return ret;
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regmap_write(sata_phy->regmap, SATA_REF_CTRL1, SATA_CLK_RST_SOURCE_PHY);
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val = FIELD_PREP(SATA_P0_PHY_TX_AMPLITUDE_GEN1_MASK,
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sata_phy->tx_amplitude_tuning_val[0]) |
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FIELD_PREP(SATA_P0_PHY_TX_AMPLITUDE_GEN2_MASK,
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sata_phy->tx_amplitude_tuning_val[1]) |
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FIELD_PREP(SATA_P0_PHY_TX_AMPLITUDE_GEN3_MASK,
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sata_phy->tx_amplitude_tuning_val[2]);
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regmap_write(sata_phy->regmap, SATA_PHY_CTRL0, val);
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val = FIELD_PREP(SATA_P0_PHY_TX_PREEMPH_GEN1_MASK,
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sata_phy->tx_preemph_tuning_val[0]) |
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FIELD_PREP(SATA_P0_PHY_TX_PREEMPH_GEN2_MASK,
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sata_phy->tx_preemph_tuning_val[1]) |
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FIELD_PREP(SATA_P0_PHY_TX_PREEMPH_GEN3_MASK,
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sata_phy->tx_preemph_tuning_val[2]);
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regmap_write(sata_phy->regmap, SATA_PHY_CTRL1, val);
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val = FIELD_PREP(SATA_LOS_LEVEL_MASK, 0x9) |
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FIELD_PREP(SATA_LOS_BIAS_MASK, 0x2);
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regmap_write(sata_phy->regmap, SATA_LOS_IDEN, val);
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val = SATA_M_CSYSREQ | SATA_S_CSYSREQ;
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regmap_write(sata_phy->regmap, SATA_AXI_LP_CTRL, val);
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val = SATA_REF_REPEATCLK_EN | SATA_REF_USE_PAD;
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regmap_write(sata_phy->regmap, SATA_REF_CTRL, val);
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val = FIELD_PREP(SATA_MPLL_MULTIPLIER_MASK, 0x3c);
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regmap_write(sata_phy->regmap, SATA_MPLL_CTRL, val);
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usleep_range(15, 20);
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ret = reset_control_deassert(sata_phy->rst);
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if (ret)
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goto disable_clk;
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ret = wait_for_phy_ready(sata_phy->regmap, SATA_P0_PHY_STAT,
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SATA_P0_PHY_READY, 1);
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if (ret < 0) {
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dev_err(&sata_phy->phy->dev, "PHY READY check failed\n");
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goto disable_clk;
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}
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return 0;
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disable_clk:
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clk_disable_unprepare(sata_phy->clk);
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return ret;
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}
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static int eic7700_sata_phy_exit(struct phy *phy)
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{
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struct eic7700_sata_phy *sata_phy = phy_get_drvdata(phy);
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int ret;
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ret = reset_control_assert(sata_phy->rst);
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if (ret)
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return ret;
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clk_disable_unprepare(sata_phy->clk);
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return 0;
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}
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static const struct phy_ops eic7700_sata_phy_ops = {
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.init = eic7700_sata_phy_init,
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.exit = eic7700_sata_phy_exit,
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.owner = THIS_MODULE,
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};
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static void eic7700_get_tuning_param(struct device_node *np,
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struct eic7700_sata_phy *sata_phy)
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{
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if (of_property_read_u32_array
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(np, "eswin,tx-amplitude-tuning",
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sata_phy->tx_amplitude_tuning_val,
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ARRAY_SIZE(sata_phy->tx_amplitude_tuning_val))) {
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sata_phy->tx_amplitude_tuning_val[0] =
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SATA_P0_PHY_TX_AMPLITUDE_GEN1_DEFAULT;
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sata_phy->tx_amplitude_tuning_val[1] =
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SATA_P0_PHY_TX_AMPLITUDE_GEN2_DEFAULT;
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sata_phy->tx_amplitude_tuning_val[2] =
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SATA_P0_PHY_TX_AMPLITUDE_GEN3_DEFAULT;
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}
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if (of_property_read_u32_array
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(np, "eswin,tx-preemph-tuning",
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sata_phy->tx_preemph_tuning_val,
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ARRAY_SIZE(sata_phy->tx_preemph_tuning_val))) {
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sata_phy->tx_preemph_tuning_val[0] =
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SATA_P0_PHY_TX_PREEMPH_GEN1_DEFAULT;
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sata_phy->tx_preemph_tuning_val[1] =
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SATA_P0_PHY_TX_PREEMPH_GEN2_DEFAULT;
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sata_phy->tx_preemph_tuning_val[2] =
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SATA_P0_PHY_TX_PREEMPH_GEN3_DEFAULT;
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}
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}
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static int eic7700_sata_phy_probe(struct platform_device *pdev)
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{
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struct eic7700_sata_phy *sata_phy;
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struct phy_provider *phy_provider;
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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struct resource *res;
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void __iomem *regs;
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sata_phy = devm_kzalloc(dev, sizeof(*sata_phy), GFP_KERNEL);
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if (!sata_phy)
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return -ENOMEM;
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/*
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* Map the I/O resource with platform_get_resource and devm_ioremap
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* instead of the devm_platform_ioremap_resource API, because the
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* address region of the SATA-PHY falls into the region of the HSP
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* clock & reset that has already been obtained by the HSP
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* clock-and-reset driver.
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*/
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res)
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return -ENOENT;
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regs = devm_ioremap(dev, res->start, resource_size(res));
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if (IS_ERR(regs))
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return PTR_ERR(regs);
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sata_phy->regmap = devm_regmap_init_mmio
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(dev, regs, &eic7700_sata_phy_regmap_config);
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if (IS_ERR(sata_phy->regmap))
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return dev_err_probe(dev, PTR_ERR(sata_phy->regmap),
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"failed to init regmap\n");
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dev_set_drvdata(dev, sata_phy);
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eic7700_get_tuning_param(np, sata_phy);
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sata_phy->clk = devm_clk_get(dev, "phy");
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if (IS_ERR(sata_phy->clk))
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return PTR_ERR(sata_phy->clk);
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sata_phy->rst = devm_reset_control_array_get_exclusive(dev);
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if (IS_ERR(sata_phy->rst))
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return dev_err_probe(dev, PTR_ERR(sata_phy->rst),
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"failed to get reset control\n");
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+
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sata_phy->phy = devm_phy_create(dev, NULL, &eic7700_sata_phy_ops);
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if (IS_ERR(sata_phy->phy))
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return dev_err_probe(dev, PTR_ERR(sata_phy->phy),
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"failed to create PHY\n");
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phy_set_drvdata(sata_phy->phy, sata_phy);
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+
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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if (IS_ERR(phy_provider))
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return dev_err_probe(dev, PTR_ERR(phy_provider),
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"failed to register PHY provider\n");
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return 0;
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}
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+
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static const struct of_device_id eic7700_sata_phy_of_match[] = {
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{ .compatible = "eswin,eic7700-sata-phy" },
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{ },
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};
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MODULE_DEVICE_TABLE(of, eic7700_sata_phy_of_match);
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+
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static struct platform_driver eic7700_sata_phy_driver = {
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.probe = eic7700_sata_phy_probe,
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.driver = {
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.of_match_table = eic7700_sata_phy_of_match,
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.name = "eic7700-sata-phy",
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}
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};
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module_platform_driver(eic7700_sata_phy_driver);
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MODULE_DESCRIPTION("SATA PHY driver for the ESWIN EIC7700 SoC");
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MODULE_AUTHOR("Yulin Lu <luyulin@eswincomputing.com>");
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MODULE_LICENSE("GPL");