Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'dmaengine-fix-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
Pull dmaengine fixes from Vinod Koul:
- SPI PDMA data fix for TI k3-psil drivers
- suspend fix, pointer check, logic for arbitration fix and channel
leak fix in fsl-edma driver
- couple of fixes in idxd driver for GRPCFG descriptions and int_handle
field handling
- single fix for stm32 driver for bitfield overflow
* tag 'dmaengine-fix-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine:
dmaengine: fsl-edma: fix DMA channel leak in eDMAv4
dmaengine: fsl-edma: fix wrong pointer check in fsl_edma3_attach_pd()
dmaengine: idxd: Fix incorrect descriptions for GRPCFG register
dmaengine: idxd: Protect int_handle field in hw descriptor
dmaengine: stm32-dma: avoid bitfield overflow assertion
dmaengine: fsl-edma: Add judgment on enabling round robin arbitration
dmaengine: fsl-edma: Do not suspend and resume the masked dma channel when the system is sleeping
dmaengine: ti: k3-psil-am62a: Fix SPI PDMA data
dmaengine: ti: k3-psil-am62: Fix SPI PDMA data
+41
-30
+1
drivers/dma/fsl-edma-common.c
+1
drivers/dma/fsl-edma-common.c
+8
-4
drivers/dma/fsl-edma-main.c
+8
-4
drivers/dma/fsl-edma-main.c
···
396
396
link = device_link_add(dev, pd_chan, DL_FLAG_STATELESS |
397
397
DL_FLAG_PM_RUNTIME |
398
398
DL_FLAG_RPM_ACTIVE);
399
-
if (IS_ERR(link)) {
400
-
dev_err(dev, "Failed to add device_link to %d: %ld\n", i,
401
-
PTR_ERR(link));
399
+
if (!link) {
400
+
dev_err(dev, "Failed to add device_link to %d\n", i);
402
401
return -EINVAL;
403
402
}
404
403
···
630
631
631
632
for (i = 0; i < fsl_edma->n_chans; i++) {
632
633
fsl_chan = &fsl_edma->chans[i];
634
+
if (fsl_edma->chan_masked & BIT(i))
635
+
continue;
633
636
spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
634
637
/* Make sure chan is idle or will force disable. */
635
638
if (unlikely(!fsl_chan->idle)) {
···
656
655
657
656
for (i = 0; i < fsl_edma->n_chans; i++) {
658
657
fsl_chan = &fsl_edma->chans[i];
658
+
if (fsl_edma->chan_masked & BIT(i))
659
+
continue;
659
660
fsl_chan->pm_state = RUNNING;
660
661
edma_write_tcdreg(fsl_chan, 0, csr);
661
662
if (fsl_chan->slave_id != 0)
662
663
fsl_edma_chan_mux(fsl_chan, fsl_chan->slave_id, true);
663
664
}
664
665
665
-
edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr);
666
+
if (!(fsl_edma->drvdata->flags & FSL_EDMA_DRV_SPLIT_REG))
667
+
edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr);
666
668
667
669
return 0;
668
670
}
+7
-5
drivers/dma/idxd/registers.h
+7
-5
drivers/dma/idxd/registers.h
···
440
440
/*
441
441
* This macro calculates the offset into the GRPCFG register
442
442
* idxd - struct idxd *
443
-
* n - wq id
444
-
* ofs - the index of the 32b dword for the config register
443
+
* n - group id
444
+
* ofs - the index of the 64b qword for the config register
445
445
*
446
-
* The WQCFG register block is divided into groups per each wq. The n index
447
-
* allows us to move to the register group that's for that particular wq.
448
-
* Each register is 32bits. The ofs gives us the number of register to access.
446
+
* The GRPCFG register block is divided into three sub-registers, which
447
+
* are GRPWQCFG, GRPENGCFG and GRPFLGCFG. The n index allows us to move
448
+
* to the register block that contains the three sub-registers.
449
+
* Each register block is 64bits. And the ofs gives us the offset
450
+
* within the GRPWQCFG register to access.
449
451
*/
450
452
#define GRPWQCFG_OFFSET(idxd_dev, n, ofs) ((idxd_dev)->grpcfg_offset +\
451
453
(n) * GRPCFG_SIZE + sizeof(u64) * (ofs))
+7
-7
drivers/dma/idxd/submit.c
+7
-7
drivers/dma/idxd/submit.c
···
183
183
portal = idxd_wq_portal_addr(wq);
184
184
185
185
/*
186
-
* The wmb() flushes writes to coherent DMA data before
187
-
* possibly triggering a DMA read. The wmb() is necessary
188
-
* even on UP because the recipient is a device.
189
-
*/
190
-
wmb();
191
-
192
-
/*
193
186
* Pending the descriptor to the lockless list for the irq_entry
194
187
* that we designated the descriptor to.
195
188
*/
···
191
198
desc->hw->int_handle = ie->int_handle;
192
199
llist_add(&desc->llnode, &ie->pending_llist);
193
200
}
201
+
202
+
/*
203
+
* The wmb() flushes writes to coherent DMA data before
204
+
* possibly triggering a DMA read. The wmb() is necessary
205
+
* even on UP because the recipient is a device.
206
+
*/
207
+
wmb();
194
208
195
209
if (wq_dedicated(wq)) {
196
210
iosubmit_cmds512(portal, desc->hw, 1);
+6
-2
drivers/dma/stm32-dma.c
+6
-2
drivers/dma/stm32-dma.c
···
1246
1246
enum dma_slave_buswidth max_width;
1247
1247
struct stm32_dma_desc *desc;
1248
1248
size_t xfer_count, offset;
1249
-
u32 num_sgs, best_burst, dma_burst, threshold;
1250
-
int i;
1249
+
u32 num_sgs, best_burst, threshold;
1250
+
int dma_burst, i;
1251
1251
1252
1252
num_sgs = DIV_ROUND_UP(len, STM32_DMA_ALIGNED_MAX_DATA_ITEMS);
1253
1253
desc = kzalloc(struct_size(desc, sg_req, num_sgs), GFP_NOWAIT);
···
1266
1266
best_burst = stm32_dma_get_best_burst(len, STM32_DMA_MAX_BURST,
1267
1267
threshold, max_width);
1268
1268
dma_burst = stm32_dma_get_burst(chan, best_burst);
1269
+
if (dma_burst < 0) {
1270
+
kfree(desc);
1271
+
return NULL;
1272
+
}
1269
1273
1270
1274
stm32_dma_clear_reg(&desc->sg_req[i].chan_reg);
1271
1275
desc->sg_req[i].chan_reg.dma_scr =
+6
-6
drivers/dma/ti/k3-psil-am62.c
+6
-6
drivers/dma/ti/k3-psil-am62.c
···
74
74
PSIL_SAUL(0x7505, 21, 35, 8, 36, 0),
75
75
PSIL_SAUL(0x7506, 22, 43, 8, 43, 0),
76
76
PSIL_SAUL(0x7507, 23, 43, 8, 44, 0),
77
-
/* PDMA_MAIN0 - SPI0-3 */
77
+
/* PDMA_MAIN0 - SPI0-2 */
78
+
PSIL_PDMA_XY_PKT(0x4300),
79
+
PSIL_PDMA_XY_PKT(0x4301),
78
80
PSIL_PDMA_XY_PKT(0x4302),
79
81
PSIL_PDMA_XY_PKT(0x4303),
80
82
PSIL_PDMA_XY_PKT(0x4304),
···
87
85
PSIL_PDMA_XY_PKT(0x4309),
88
86
PSIL_PDMA_XY_PKT(0x430a),
89
87
PSIL_PDMA_XY_PKT(0x430b),
90
-
PSIL_PDMA_XY_PKT(0x430c),
91
-
PSIL_PDMA_XY_PKT(0x430d),
92
88
/* PDMA_MAIN1 - UART0-6 */
93
89
PSIL_PDMA_XY_PKT(0x4400),
94
90
PSIL_PDMA_XY_PKT(0x4401),
···
141
141
/* SAUL */
142
142
PSIL_SAUL(0xf500, 27, 83, 8, 83, 1),
143
143
PSIL_SAUL(0xf501, 28, 91, 8, 91, 1),
144
-
/* PDMA_MAIN0 - SPI0-3 */
144
+
/* PDMA_MAIN0 - SPI0-2 */
145
+
PSIL_PDMA_XY_PKT(0xc300),
146
+
PSIL_PDMA_XY_PKT(0xc301),
145
147
PSIL_PDMA_XY_PKT(0xc302),
146
148
PSIL_PDMA_XY_PKT(0xc303),
147
149
PSIL_PDMA_XY_PKT(0xc304),
···
154
152
PSIL_PDMA_XY_PKT(0xc309),
155
153
PSIL_PDMA_XY_PKT(0xc30a),
156
154
PSIL_PDMA_XY_PKT(0xc30b),
157
-
PSIL_PDMA_XY_PKT(0xc30c),
158
-
PSIL_PDMA_XY_PKT(0xc30d),
159
155
/* PDMA_MAIN1 - UART0-6 */
160
156
PSIL_PDMA_XY_PKT(0xc400),
161
157
PSIL_PDMA_XY_PKT(0xc401),
+6
-6
drivers/dma/ti/k3-psil-am62a.c
+6
-6
drivers/dma/ti/k3-psil-am62a.c
···
84
84
PSIL_SAUL(0x7505, 21, 35, 8, 36, 0),
85
85
PSIL_SAUL(0x7506, 22, 43, 8, 43, 0),
86
86
PSIL_SAUL(0x7507, 23, 43, 8, 44, 0),
87
-
/* PDMA_MAIN0 - SPI0-3 */
87
+
/* PDMA_MAIN0 - SPI0-2 */
88
+
PSIL_PDMA_XY_PKT(0x4300),
89
+
PSIL_PDMA_XY_PKT(0x4301),
88
90
PSIL_PDMA_XY_PKT(0x4302),
89
91
PSIL_PDMA_XY_PKT(0x4303),
90
92
PSIL_PDMA_XY_PKT(0x4304),
···
97
95
PSIL_PDMA_XY_PKT(0x4309),
98
96
PSIL_PDMA_XY_PKT(0x430a),
99
97
PSIL_PDMA_XY_PKT(0x430b),
100
-
PSIL_PDMA_XY_PKT(0x430c),
101
-
PSIL_PDMA_XY_PKT(0x430d),
102
98
/* PDMA_MAIN1 - UART0-6 */
103
99
PSIL_PDMA_XY_PKT(0x4400),
104
100
PSIL_PDMA_XY_PKT(0x4401),
···
151
151
/* SAUL */
152
152
PSIL_SAUL(0xf500, 27, 83, 8, 83, 1),
153
153
PSIL_SAUL(0xf501, 28, 91, 8, 91, 1),
154
-
/* PDMA_MAIN0 - SPI0-3 */
154
+
/* PDMA_MAIN0 - SPI0-2 */
155
+
PSIL_PDMA_XY_PKT(0xc300),
156
+
PSIL_PDMA_XY_PKT(0xc301),
155
157
PSIL_PDMA_XY_PKT(0xc302),
156
158
PSIL_PDMA_XY_PKT(0xc303),
157
159
PSIL_PDMA_XY_PKT(0xc304),
···
164
162
PSIL_PDMA_XY_PKT(0xc309),
165
163
PSIL_PDMA_XY_PKT(0xc30a),
166
164
PSIL_PDMA_XY_PKT(0xc30b),
167
-
PSIL_PDMA_XY_PKT(0xc30c),
168
-
PSIL_PDMA_XY_PKT(0xc30d),
169
165
/* PDMA_MAIN1 - UART0-6 */
170
166
PSIL_PDMA_XY_PKT(0xc400),
171
167
PSIL_PDMA_XY_PKT(0xc401),