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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
iio: adc: rzg2l_adc: Add support for channel 8
The ADC on the Renesas RZ/G3S SoC includes an additional channel (channel
8) dedicated to reading temperature values from the Thermal Sensor Unit
(TSU). There is a direct in-SoC connection between the ADC and TSU IPs.
To read the temperature reported by the TSU, a different sampling rate
(compared to channels 0-7) must be configured in the ADM3 register.
The rzg2l_adc driver has been updated to support reading the TSU
temperature.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://patch.msgid.link/20241206111337.726244-11-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
authored by
Claudiu Beznea
and committed by
Jonathan Cameron
6dd8a771
a259a846
+44
-18
+44
-18
drivers/iio/adc/rzg2l_adc.c
+44
-18
drivers/iio/adc/rzg2l_adc.c
···
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#define RZG2L_ADCR(n) (0x30 + ((n) * 0x4))
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#define RZG2L_ADCR_AD_MASK GENMASK(11, 0)
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-
#define RZG2L_ADC_MAX_CHANNELS 8
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#define RZG2L_ADC_MAX_CHANNELS 9
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#define RZG2L_ADC_TIMEOUT usecs_to_jiffies(1 * 4)
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/**
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* struct rzg2l_adc_hw_params - ADC hardware specific parameters
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* @default_adsmp: default ADC sampling period (see ADM3 register)
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* @default_adsmp: default ADC sampling period (see ADM3 register); index 0 is
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* used for voltage channels, index 1 is used for temperature channel
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* @adsmp_mask: ADC sampling period mask (see ADM3 register)
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* @adint_inten_mask: conversion end interrupt mask (see ADINT register)
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* @default_adcmp: default ADC cmp (see ADM3 register)
···
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* @adivc: specifies if ADVIC register is available
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*/
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struct rzg2l_adc_hw_params {
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u16 default_adsmp;
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u16 default_adsmp[2];
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u16 adsmp_mask;
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u16 adint_inten_mask;
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u8 default_adcmp;
···
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u16 last_val[RZG2L_ADC_MAX_CHANNELS];
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};
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static const char * const rzg2l_adc_channel_name[] = {
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"adc0",
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"adc1",
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"adc2",
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"adc3",
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"adc4",
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"adc5",
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"adc6",
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"adc7",
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/**
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* struct rzg2l_adc_channel - ADC channel descriptor
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* @name: ADC channel name
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* @type: ADC channel type
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*/
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struct rzg2l_adc_channel {
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const char * const name;
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enum iio_chan_type type;
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};
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+
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static const struct rzg2l_adc_channel rzg2l_adc_channels[] = {
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{ "adc0", IIO_VOLTAGE },
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{ "adc1", IIO_VOLTAGE },
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{ "adc2", IIO_VOLTAGE },
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{ "adc3", IIO_VOLTAGE },
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{ "adc4", IIO_VOLTAGE },
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{ "adc5", IIO_VOLTAGE },
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{ "adc6", IIO_VOLTAGE },
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{ "adc7", IIO_VOLTAGE },
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{ "adc8", IIO_TEMP },
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};
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static unsigned int rzg2l_adc_readl(struct rzg2l_adc *adc, u32 reg)
···
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rzg2l_adc_writel(adc, RZG2L_ADM(1), reg);
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}
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static u8 rzg2l_adc_ch_to_adsmp_index(u8 ch)
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{
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if (rzg2l_adc_channels[ch].type == IIO_VOLTAGE)
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return 0;
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+
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return 1;
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}
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+
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static int rzg2l_adc_conversion_setup(struct rzg2l_adc *adc, u8 ch)
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{
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const struct rzg2l_adc_hw_params *hw_params = adc->hw_params;
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u8 index = rzg2l_adc_ch_to_adsmp_index(ch);
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u32 reg;
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if (rzg2l_adc_readl(adc, RZG2L_ADM(0)) & RZG2L_ADM0_ADBSY)
···
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reg &= ~GENMASK(hw_params->num_channels - 1, 0);
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reg |= BIT(ch);
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rzg2l_adc_writel(adc, RZG2L_ADM(2), reg);
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reg = rzg2l_adc_readl(adc, RZG2L_ADM(3));
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reg &= ~hw_params->adsmp_mask;
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reg |= hw_params->default_adsmp[index];
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rzg2l_adc_writel(adc, RZG2L_ADM(3), reg);
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/*
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* Setup ADINT
···
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switch (mask) {
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case IIO_CHAN_INFO_RAW: {
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-
if (chan->type != IIO_VOLTAGE)
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if (chan->type != IIO_VOLTAGE && chan->type != IIO_TEMP)
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return -EINVAL;
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guard(mutex)(&adc->lock);
···
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const struct iio_chan_spec *chan,
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char *label)
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{
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return sysfs_emit(label, "%s\n", rzg2l_adc_channel_name[chan->channel]);
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return sysfs_emit(label, "%s\n", rzg2l_adc_channels[chan->channel].name);
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}
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static const struct iio_info rzg2l_adc_iio_info = {
···
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if (channel >= hw_params->num_channels)
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return -EINVAL;
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-
chan_array[i].type = IIO_VOLTAGE;
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chan_array[i].type = rzg2l_adc_channels[channel].type;
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chan_array[i].indexed = 1;
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chan_array[i].channel = channel;
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chan_array[i].info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
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chan_array[i].datasheet_name = rzg2l_adc_channel_name[channel];
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chan_array[i].datasheet_name = rzg2l_adc_channels[channel].name;
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i++;
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}
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···
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reg &= ~RZG2L_ADM3_ADCMP_MASK;
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reg &= ~hw_params->adsmp_mask;
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reg |= FIELD_PREP(RZG2L_ADM3_ADCMP_MASK, hw_params->default_adcmp) |
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hw_params->default_adsmp;
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hw_params->default_adsmp[0];
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rzg2l_adc_writel(adc, RZG2L_ADM(3), reg);
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···
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static const struct rzg2l_adc_hw_params rzg2l_hw_params = {
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.num_channels = 8,
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.default_adcmp = 0xe,
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-
.default_adsmp = 0x578,
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.default_adsmp = { 0x578 },
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.adsmp_mask = GENMASK(15, 0),
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.adint_inten_mask = GENMASK(7, 0),
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.adivc = true