Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branches 'clk-visconti', 'clk-imx', 'clk-microchip', 'clk-rockchip' and 'clk-qcom' into clk-next
* clk-visconti:
clk: visconti: Add VIIF clocks
dt-bindings: clock: tmpv770x: Add VIIF clocks
dt-bindings: clock: tmpv770x: Remove definition of number of clocks
clk: visconti: Do not define number of clocks in bindings
* clk-imx:
clk: imx: add driver for imx8ulp's sim lpav
dt-bindings: clock: document 8ULP's SIM LPAV
clk: imx: imx8mp-audiomix: use devm_auxiliary_device_create() to simple code
clk: imx: Add some delay before deassert the reset
* clk-microchip:
reset: mpfs: add non-auxiliary bus probing
clk: lan966x: remove unused dt-bindings include
clk: microchip: mpfs: use regmap for clocks
dt-bindings: clk: microchip: mpfs: remove first reg region
* clk-rockchip:
clk: rockchip: Add clock and reset driver for RK3506
dt-bindings: clock: rockchip: Add RK3506 clock and reset unit
clk: rockchip: Add clock controller for the RV1126B
dt-bindings: clock, reset: Add support for rv1126b
clk: rockchip: Implement rockchip_clk_register_armclk_multi_pll()
dt-bindings: clock: rk3568: Drop CLK_NR_CLKS define
clk: rockchip: rk3568: Drop CLK_NR_CLKS usage
dt-bindings: clock: rk3568: Add SCMI clock ids
* clk-qcom: (48 commits)
clk: qcom: Mark camcc_sm7150_hws static
clk: qcom: x1e80100-dispcc: Add USB4 router link resets
dt-bindings: clock: qcom: x1e80100-dispcc: Add USB4 router link resets
clk: qcom: videocc-sm8750: Add video clock controller driver for SM8750
dt-bindings: clock: qcom: Add SM8750 video clock controller
clk: qcom: branch: Extend invert logic for branch2 mem clocks
clk: qcom: ecpricc-qdu100: Add mem_enable_mask to the clock memory branch
clk: qcom: clk_mem_branch: add enable mask and invert flags
clk: qcom: mmcc-sdm660: Add missing MDSS reset
dt-bindings: clock: mmcc-sdm660: Add missing MDSS reset
clk: qcom: use different Kconfig prompts for APSS IPQ5424/6018 drivers
clk: qcom: apss-ipq5424: remove unused 'apss_clk' structure
dt-bindings: clock: qcom: Add Kaanapali Global clock controller
dt-bindings: clock: qcom: Document the Kaanapali TCSR Clock Controller
dt-bindings: clock: qcom-rpmhcc: Add RPMHCC for Kaanapali
clk: qcom: tcsrcc-glymur: Update register offsets for clock refs
clk: qcom: gcc-qcs615: Update the SDCC clock to use shared_floor_ops
clk: qcom: camcc-sm7150: Fix PLL config of PLL2
clk: qcom: camcc-sm6350: Fix PLL config of PLL2
clk: qcom: Add NSS clock controller driver for IPQ5424
...
+8298
-245
+72
Documentation/devicetree/bindings/clock/fsl,imx8ulp-sim-lpav.yaml
+72
Documentation/devicetree/bindings/clock/fsl,imx8ulp-sim-lpav.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/clock/fsl,imx8ulp-sim-lpav.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: NXP i.MX8ULP LPAV System Integration Module (SIM)
8
+
9
+
maintainers:
10
+
- Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
11
+
12
+
description:
13
+
The i.MX8ULP LPAV subsystem contains a block control module known as
14
+
SIM LPAV, which offers functionalities such as clock gating or reset
15
+
line assertion/de-assertion.
16
+
17
+
properties:
18
+
compatible:
19
+
const: fsl,imx8ulp-sim-lpav
20
+
21
+
reg:
22
+
maxItems: 1
23
+
24
+
clocks:
25
+
maxItems: 3
26
+
27
+
clock-names:
28
+
items:
29
+
- const: bus
30
+
- const: core
31
+
- const: plat
32
+
33
+
'#clock-cells':
34
+
const: 1
35
+
36
+
'#reset-cells':
37
+
const: 1
38
+
39
+
mux-controller:
40
+
$ref: /schemas/mux/reg-mux.yaml#
41
+
42
+
required:
43
+
- compatible
44
+
- reg
45
+
- clocks
46
+
- clock-names
47
+
- '#clock-cells'
48
+
- '#reset-cells'
49
+
- mux-controller
50
+
51
+
additionalProperties: false
52
+
53
+
examples:
54
+
- |
55
+
#include <dt-bindings/clock/imx8ulp-clock.h>
56
+
57
+
clock-controller@2da50000 {
58
+
compatible = "fsl,imx8ulp-sim-lpav";
59
+
reg = <0x2da50000 0x10000>;
60
+
clocks = <&cgc2 IMX8ULP_CLK_LPAV_BUS_DIV>,
61
+
<&cgc2 IMX8ULP_CLK_HIFI_DIVCORE>,
62
+
<&cgc2 IMX8ULP_CLK_HIFI_DIVPLAT>;
63
+
clock-names = "bus", "core", "plat";
64
+
#clock-cells = <1>;
65
+
#reset-cells = <1>;
66
+
67
+
mux-controller {
68
+
compatible = "reg-mux";
69
+
#mux-control-cells = <1>;
70
+
mux-reg-masks = <0x8 0x00000200>;
71
+
};
72
+
};
+22
-14
Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml
+22
-14
Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml
···
22
22
const: microchip,mpfs-clkcfg
23
23
24
24
reg:
25
-
items:
26
-
- description: |
27
-
clock config registers:
28
-
These registers contain enable, reset & divider tables for the, cpu,
29
-
axi, ahb and rtc/mtimer reference clocks as well as enable and reset
30
-
for the peripheral clocks.
31
-
- description: |
32
-
mss pll dri registers:
33
-
Block of registers responsible for dynamic reconfiguration of the mss
34
-
pll
25
+
oneOf:
26
+
- items:
27
+
- description: |
28
+
clock config registers:
29
+
These registers contain enable, reset & divider tables for the, cpu,
30
+
axi, ahb and rtc/mtimer reference clocks as well as enable and reset
31
+
for the peripheral clocks.
32
+
- description: |
33
+
mss pll dri registers:
34
+
Block of registers responsible for dynamic reconfiguration of the mss
35
+
pll
36
+
deprecated: true
37
+
- items:
38
+
- description: |
39
+
mss pll dri registers:
40
+
Block of registers responsible for dynamic reconfiguration of the mss
41
+
pll
35
42
36
43
clocks:
37
44
maxItems: 1
···
76
69
- |
77
70
#include <dt-bindings/clock/microchip,mpfs-clock.h>
78
71
soc {
79
-
#address-cells = <2>;
80
-
#size-cells = <2>;
81
-
clkcfg: clock-controller@20002000 {
72
+
#address-cells = <1>;
73
+
#size-cells = <1>;
74
+
75
+
clkcfg: clock-controller@3E001000 {
82
76
compatible = "microchip,mpfs-clkcfg";
83
-
reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
77
+
reg = <0x3E001000 0x1000>;
84
78
clocks = <&ref>;
85
79
#clock-cells = <1>;
86
80
};
+55
-8
Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml
+55
-8
Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml
···
4
4
$id: http://devicetree.org/schemas/clock/qcom,ipq9574-nsscc.yaml#
5
5
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
6
7
-
title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574
7
+
title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574 and IPQ5424
8
8
9
9
maintainers:
10
10
- Bjorn Andersson <andersson@kernel.org>
···
12
12
13
13
description: |
14
14
Qualcomm networking sub system clock control module provides the clocks,
15
-
resets on IPQ9574
15
+
resets on IPQ9574 and IPQ5424
16
16
17
-
See also::
17
+
See also:
18
+
include/dt-bindings/clock/qcom,ipq5424-nsscc.h
18
19
include/dt-bindings/clock/qcom,ipq9574-nsscc.h
20
+
include/dt-bindings/reset/qcom,ipq5424-nsscc.h
19
21
include/dt-bindings/reset/qcom,ipq9574-nsscc.h
20
22
21
23
properties:
22
24
compatible:
23
-
const: qcom,ipq9574-nsscc
25
+
enum:
26
+
- qcom,ipq5424-nsscc
27
+
- qcom,ipq9574-nsscc
24
28
25
29
clocks:
26
30
items:
27
31
- description: Board XO source
28
-
- description: CMN_PLL NSS 1200MHz (Bias PLL cc) clock source
29
-
- description: CMN_PLL PPE 353MHz (Bias PLL ubi nc) clock source
32
+
- description: CMN_PLL NSS (Bias PLL cc) clock source. This clock rate
33
+
can vary for different IPQ SoCs. For example, it is 1200 MHz on the
34
+
IPQ9574 and 300 MHz on the IPQ5424.
35
+
- description: CMN_PLL PPE (Bias PLL ubi nc) clock source. The clock
36
+
rate can vary for different IPQ SoCs. For example, it is 353 MHz
37
+
on the IPQ9574 and 375 MHz on the IPQ5424.
30
38
- description: GCC GPLL0 OUT AUX clock source
31
39
- description: Uniphy0 NSS Rx clock source
32
40
- description: Uniphy0 NSS Tx clock source
···
50
42
clock-names:
51
43
items:
52
44
- const: xo
53
-
- const: nss_1200
54
-
- const: ppe_353
45
+
- enum:
46
+
- nss_1200
47
+
- nss
48
+
- enum:
49
+
- ppe_353
50
+
- ppe
55
51
- const: gpll0_out
56
52
- const: uniphy0_rx
57
53
- const: uniphy0_tx
···
72
60
73
61
allOf:
74
62
- $ref: qcom,gcc.yaml#
63
+
- if:
64
+
properties:
65
+
compatible:
66
+
const: qcom,ipq9574-nsscc
67
+
then:
68
+
properties:
69
+
clock-names:
70
+
items:
71
+
- const: xo
72
+
- const: nss_1200
73
+
- const: ppe_353
74
+
- const: gpll0_out
75
+
- const: uniphy0_rx
76
+
- const: uniphy0_tx
77
+
- const: uniphy1_rx
78
+
- const: uniphy1_tx
79
+
- const: uniphy2_rx
80
+
- const: uniphy2_tx
81
+
- const: bus
82
+
else:
83
+
properties:
84
+
clock-names:
85
+
items:
86
+
- const: xo
87
+
- const: nss
88
+
- const: ppe
89
+
- const: gpll0_out
90
+
- const: uniphy0_rx
91
+
- const: uniphy0_tx
92
+
- const: uniphy1_rx
93
+
- const: uniphy1_tx
94
+
- const: uniphy2_rx
95
+
- const: uniphy2_tx
96
+
- const: bus
75
97
76
98
unevaluatedProperties: false
77
99
···
140
94
"bus";
141
95
#clock-cells = <1>;
142
96
#reset-cells = <1>;
97
+
#interconnect-cells = <1>;
143
98
};
144
99
...
+1
Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
+1
Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml
+4
-1
Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
+4
-1
Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
···
7
7
title: Qualcomm Video Clock & Reset Controller on SM8450
8
8
9
9
maintainers:
10
-
- Taniya Das <quic_tdas@quicinc.com>
10
+
- Taniya Das <taniya.das@oss.qualcomm.com>
11
11
- Jagadeesh Kona <quic_jkona@quicinc.com>
12
12
13
13
description: |
···
17
17
See also:
18
18
include/dt-bindings/clock/qcom,sm8450-videocc.h
19
19
include/dt-bindings/clock/qcom,sm8650-videocc.h
20
+
include/dt-bindings/clock/qcom,sm8750-videocc.h
20
21
21
22
properties:
22
23
compatible:
···
26
25
- qcom,sm8475-videocc
27
26
- qcom,sm8550-videocc
28
27
- qcom,sm8650-videocc
28
+
- qcom,sm8750-videocc
29
29
- qcom,x1e80100-videocc
30
30
31
31
clocks:
···
63
61
enum:
64
62
- qcom,sm8450-videocc
65
63
- qcom,sm8550-videocc
64
+
- qcom,sm8750-videocc
66
65
then:
67
66
required:
68
67
- required-opps
+1
Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
+1
Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml
+6
-2
Documentation/devicetree/bindings/clock/qcom,sm8750-gcc.yaml
+6
-2
Documentation/devicetree/bindings/clock/qcom,sm8750-gcc.yaml
···
13
13
Qualcomm global clock control module provides the clocks, resets and power
14
14
domains on SM8750
15
15
16
-
See also: include/dt-bindings/clock/qcom,sm8750-gcc.h
16
+
See also:
17
+
include/dt-bindings/clock/qcom,kaanapali-gcc.h
18
+
include/dt-bindings/clock/qcom,sm8750-gcc.h
17
19
18
20
properties:
19
21
compatible:
20
-
const: qcom,sm8750-gcc
22
+
enum:
23
+
- qcom,kaanapali-gcc
24
+
- qcom,sm8750-gcc
21
25
22
26
clocks:
23
27
items:
+58
-4
Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml
+58
-4
Documentation/devicetree/bindings/clock/qcom,x1e80100-gcc.yaml
···
32
32
- description: PCIe 5 pipe clock
33
33
- description: PCIe 6a pipe clock
34
34
- description: PCIe 6b pipe clock
35
-
- description: USB QMP Phy 0 clock source
36
-
- description: USB QMP Phy 1 clock source
37
-
- description: USB QMP Phy 2 clock source
35
+
- description: USB4_0 QMPPHY clock source
36
+
- description: USB4_1 QMPPHY clock source
37
+
- description: USB4_2 QMPPHY clock source
38
+
- description: USB4_0 PHY DP0 GMUX clock source
39
+
- description: USB4_0 PHY DP1 GMUX clock source
40
+
- description: USB4_0 PHY PCIE PIPEGMUX clock source
41
+
- description: USB4_0 PHY PIPEGMUX clock source
42
+
- description: USB4_0 PHY SYS PCIE PIPEGMUX clock source
43
+
- description: USB4_1 PHY DP0 GMUX 2 clock source
44
+
- description: USB4_1 PHY DP1 GMUX 2 clock source
45
+
- description: USB4_1 PHY PCIE PIPEGMUX clock source
46
+
- description: USB4_1 PHY PIPEGMUX clock source
47
+
- description: USB4_1 PHY SYS PCIE PIPEGMUX clock source
48
+
- description: USB4_2 PHY DP0 GMUX 2 clock source
49
+
- description: USB4_2 PHY DP1 GMUX 2 clock source
50
+
- description: USB4_2 PHY PCIE PIPEGMUX clock source
51
+
- description: USB4_2 PHY PIPEGMUX clock source
52
+
- description: USB4_2 PHY SYS PCIE PIPEGMUX clock source
53
+
- description: USB4_0 PHY RX 0 clock source
54
+
- description: USB4_0 PHY RX 1 clock source
55
+
- description: USB4_1 PHY RX 0 clock source
56
+
- description: USB4_1 PHY RX 1 clock source
57
+
- description: USB4_2 PHY RX 0 clock source
58
+
- description: USB4_2 PHY RX 1 clock source
59
+
- description: USB4_0 PHY PCIE PIPE clock source
60
+
- description: USB4_0 PHY max PIPE clock source
61
+
- description: USB4_1 PHY PCIE PIPE clock source
62
+
- description: USB4_1 PHY max PIPE clock source
63
+
- description: USB4_2 PHY PCIE PIPE clock source
64
+
- description: USB4_2 PHY max PIPE clock source
38
65
39
66
power-domains:
40
67
description:
···
94
67
<&pcie6b_phy>,
95
68
<&usb_1_ss0_qmpphy 0>,
96
69
<&usb_1_ss1_qmpphy 1>,
97
-
<&usb_1_ss2_qmpphy 2>;
70
+
<&usb_1_ss2_qmpphy 2>,
71
+
<&usb4_0_phy_dp0_gmux_clk>,
72
+
<&usb4_0_phy_dp1_gmux_clk>,
73
+
<&usb4_0_phy_pcie_pipegmux_clk>,
74
+
<&usb4_0_phy_pipegmux_clk>,
75
+
<&usb4_0_phy_sys_pcie_pipegmux_clk>,
76
+
<&usb4_1_phy_dp0_gmux_2_clk>,
77
+
<&usb4_1_phy_dp1_gmux_2_clk>,
78
+
<&usb4_1_phy_pcie_pipegmux_clk>,
79
+
<&usb4_1_phy_pipegmux_clk>,
80
+
<&usb4_1_phy_sys_pcie_pipegmux_clk>,
81
+
<&usb4_2_phy_dp0_gmux_2_clk>,
82
+
<&usb4_2_phy_dp1_gmux_2_clk>,
83
+
<&usb4_2_phy_pcie_pipegmux_clk>,
84
+
<&usb4_2_phy_pipegmux_clk>,
85
+
<&usb4_2_phy_sys_pcie_pipegmux_clk>,
86
+
<&usb4_0_phy_rx_0_clk>,
87
+
<&usb4_0_phy_rx_1_clk>,
88
+
<&usb4_1_phy_rx_0_clk>,
89
+
<&usb4_1_phy_rx_1_clk>,
90
+
<&usb4_2_phy_rx_0_clk>,
91
+
<&usb4_2_phy_rx_1_clk>,
92
+
<&usb4_0_phy_pcie_pipe_clk>,
93
+
<&usb4_0_phy_max_pipe_clk>,
94
+
<&usb4_1_phy_pcie_pipe_clk>,
95
+
<&usb4_1_phy_max_pipe_clk>,
96
+
<&usb4_2_phy_pcie_pipe_clk>,
97
+
<&usb4_2_phy_max_pipe_clk>;
98
98
power-domains = <&rpmhpd RPMHPD_CX>;
99
99
#clock-cells = <1>;
100
100
#reset-cells = <1>;
+55
Documentation/devicetree/bindings/clock/rockchip,rk3506-cru.yaml
+55
Documentation/devicetree/bindings/clock/rockchip,rk3506-cru.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/clock/rockchip,rk3506-cru.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Rockchip RK3506 Clock and Reset Unit (CRU)
8
+
9
+
maintainers:
10
+
- Finley Xiao <finley.xiao@rock-chips.com>
11
+
- Heiko Stuebner <heiko@sntech.de>
12
+
13
+
description:
14
+
The RK3506 CRU generates the clock and also implements reset for SoC
15
+
peripherals.
16
+
17
+
properties:
18
+
compatible:
19
+
const: rockchip,rk3506-cru
20
+
21
+
reg:
22
+
maxItems: 1
23
+
24
+
"#clock-cells":
25
+
const: 1
26
+
27
+
"#reset-cells":
28
+
const: 1
29
+
30
+
clocks:
31
+
maxItems: 1
32
+
33
+
clock-names:
34
+
const: xin
35
+
36
+
required:
37
+
- compatible
38
+
- reg
39
+
- "#clock-cells"
40
+
- "#reset-cells"
41
+
- clocks
42
+
- clock-names
43
+
44
+
additionalProperties: false
45
+
46
+
examples:
47
+
- |
48
+
clock-controller@ff9a0000 {
49
+
compatible = "rockchip,rk3506-cru";
50
+
reg = <0xff9a0000 0x20000>;
51
+
#clock-cells = <1>;
52
+
#reset-cells = <1>;
53
+
clocks = <&xin24m>;
54
+
clock-names = "xin";
55
+
};
+52
Documentation/devicetree/bindings/clock/rockchip,rv1126b-cru.yaml
+52
Documentation/devicetree/bindings/clock/rockchip,rv1126b-cru.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/clock/rockchip,rv1126b-cru.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Rockchip RV1126B Clock and Reset Unit
8
+
9
+
maintainers:
10
+
- Elaine Zhang <zhangqing@rock-chips.com>
11
+
- Heiko Stuebner <heiko@sntech.de>
12
+
13
+
description:
14
+
The rv1126b clock controller generates the clock and also implements a
15
+
reset controller for SoC peripherals.
16
+
17
+
properties:
18
+
compatible:
19
+
enum:
20
+
- rockchip,rv1126b-cru
21
+
22
+
reg:
23
+
maxItems: 1
24
+
25
+
"#clock-cells":
26
+
const: 1
27
+
28
+
"#reset-cells":
29
+
const: 1
30
+
31
+
clocks:
32
+
maxItems: 1
33
+
34
+
clock-names:
35
+
const: xin24m
36
+
37
+
required:
38
+
- compatible
39
+
- reg
40
+
- "#clock-cells"
41
+
- "#reset-cells"
42
+
43
+
additionalProperties: false
44
+
45
+
examples:
46
+
- |
47
+
clock-controller@20000000 {
48
+
compatible = "rockchip,rv1126b-cru";
49
+
reg = <0x20000000 0xc0000>;
50
+
#clock-cells = <1>;
51
+
#reset-cells = <1>;
52
+
};
-2
drivers/clk/clk-lan966x.c
-2
drivers/clk/clk-lan966x.c
+1
drivers/clk/imx/Kconfig
+1
drivers/clk/imx/Kconfig
+1
drivers/clk/imx/Makefile
+1
drivers/clk/imx/Makefile
+13
drivers/clk/imx/clk-composite-7ulp.c
+13
drivers/clk/imx/clk-composite-7ulp.c
···
7
7
8
8
#include <linux/bits.h>
9
9
#include <linux/clk-provider.h>
10
+
#include <linux/delay.h>
10
11
#include <linux/err.h>
11
12
#include <linux/io.h>
12
13
#include <linux/slab.h>
···
37
36
if (ret)
38
37
return ret;
39
38
39
+
/* Make sure the IP's clock is ready before release reset */
40
+
udelay(1);
41
+
40
42
spin_lock_irqsave(gate->lock, flags);
41
43
/*
42
44
* release the sw reset for peripherals associated with
···
50
46
writel(val, gate->reg);
51
47
52
48
spin_unlock_irqrestore(gate->lock, flags);
49
+
50
+
/*
51
+
* Read back the register to make sure the previous write has been
52
+
* done in the target HW register. For IP like GPU, after deassert
53
+
* the reset, need to wait for a while to make sure the sync reset
54
+
* is done
55
+
*/
56
+
readl(gate->reg);
57
+
udelay(1);
53
58
54
59
return 0;
55
60
}
+4
-35
drivers/clk/imx/clk-imx8mp-audiomix.c
+4
-35
drivers/clk/imx/clk-imx8mp-audiomix.c
···
230
230
231
231
#if IS_ENABLED(CONFIG_RESET_CONTROLLER)
232
232
233
-
static void clk_imx8mp_audiomix_reset_unregister_adev(void *_adev)
234
-
{
235
-
struct auxiliary_device *adev = _adev;
236
-
237
-
auxiliary_device_delete(adev);
238
-
auxiliary_device_uninit(adev);
239
-
}
240
-
241
-
static void clk_imx8mp_audiomix_reset_adev_release(struct device *dev)
242
-
{
243
-
struct auxiliary_device *adev = to_auxiliary_dev(dev);
244
-
245
-
kfree(adev);
246
-
}
247
-
248
233
static int clk_imx8mp_audiomix_reset_controller_register(struct device *dev,
249
234
struct clk_imx8mp_audiomix_priv *priv)
250
235
{
251
-
struct auxiliary_device *adev __free(kfree) = NULL;
252
-
int ret;
236
+
struct auxiliary_device *adev;
253
237
254
238
if (!of_property_present(dev->of_node, "#reset-cells"))
255
239
return 0;
256
240
257
-
adev = kzalloc(sizeof(*adev), GFP_KERNEL);
241
+
adev = devm_auxiliary_device_create(dev, "reset", NULL);
258
242
if (!adev)
259
-
return -ENOMEM;
243
+
return -ENODEV;
260
244
261
-
adev->name = "reset";
262
-
adev->dev.parent = dev;
263
-
adev->dev.release = clk_imx8mp_audiomix_reset_adev_release;
264
-
265
-
ret = auxiliary_device_init(adev);
266
-
if (ret)
267
-
return ret;
268
-
269
-
ret = auxiliary_device_add(adev);
270
-
if (ret) {
271
-
auxiliary_device_uninit(adev);
272
-
return ret;
273
-
}
274
-
275
-
return devm_add_action_or_reset(dev, clk_imx8mp_audiomix_reset_unregister_adev,
276
-
no_free_ptr(adev));
245
+
return 0;
277
246
}
278
247
279
248
#else /* !CONFIG_RESET_CONTROLLER */
+156
drivers/clk/imx/clk-imx8ulp-sim-lpav.c
+156
drivers/clk/imx/clk-imx8ulp-sim-lpav.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright 2025 NXP
4
+
*/
5
+
6
+
#include <dt-bindings/clock/imx8ulp-clock.h>
7
+
8
+
#include <linux/auxiliary_bus.h>
9
+
#include <linux/clk-provider.h>
10
+
#include <linux/module.h>
11
+
#include <linux/of.h>
12
+
#include <linux/of_platform.h>
13
+
#include <linux/platform_device.h>
14
+
#include <linux/regmap.h>
15
+
#include <linux/slab.h>
16
+
17
+
#define SYSCTRL0 0x8
18
+
19
+
#define IMX8ULP_HIFI_CLK_GATE(gname, cname, pname, bidx) \
20
+
{ \
21
+
.name = gname "_cg", \
22
+
.id = IMX8ULP_CLK_SIM_LPAV_HIFI_##cname, \
23
+
.parent = { .fw_name = pname }, \
24
+
.bit = bidx, \
25
+
}
26
+
27
+
struct clk_imx8ulp_sim_lpav_data {
28
+
spinlock_t lock; /* shared by MUX, clock gate and reset */
29
+
unsigned long flags; /* for spinlock usage */
30
+
struct clk_hw_onecell_data clk_data; /* keep last */
31
+
};
32
+
33
+
struct clk_imx8ulp_sim_lpav_gate {
34
+
const char *name;
35
+
int id;
36
+
const struct clk_parent_data parent;
37
+
u8 bit;
38
+
};
39
+
40
+
static struct clk_imx8ulp_sim_lpav_gate gates[] = {
41
+
IMX8ULP_HIFI_CLK_GATE("hifi_core", CORE, "core", 17),
42
+
IMX8ULP_HIFI_CLK_GATE("hifi_pbclk", PBCLK, "bus", 18),
43
+
IMX8ULP_HIFI_CLK_GATE("hifi_plat", PLAT, "plat", 19)
44
+
};
45
+
46
+
static void clk_imx8ulp_sim_lpav_lock(void *arg) __acquires(&data->lock)
47
+
{
48
+
struct clk_imx8ulp_sim_lpav_data *data = dev_get_drvdata(arg);
49
+
50
+
spin_lock_irqsave(&data->lock, data->flags);
51
+
}
52
+
53
+
static void clk_imx8ulp_sim_lpav_unlock(void *arg) __releases(&data->lock)
54
+
{
55
+
struct clk_imx8ulp_sim_lpav_data *data = dev_get_drvdata(arg);
56
+
57
+
spin_unlock_irqrestore(&data->lock, data->flags);
58
+
}
59
+
60
+
static int clk_imx8ulp_sim_lpav_probe(struct platform_device *pdev)
61
+
{
62
+
const struct regmap_config regmap_config = {
63
+
.reg_bits = 32,
64
+
.val_bits = 32,
65
+
.reg_stride = 4,
66
+
.lock = clk_imx8ulp_sim_lpav_lock,
67
+
.unlock = clk_imx8ulp_sim_lpav_unlock,
68
+
.lock_arg = &pdev->dev,
69
+
};
70
+
struct clk_imx8ulp_sim_lpav_data *data;
71
+
struct auxiliary_device *adev;
72
+
struct regmap *regmap;
73
+
void __iomem *base;
74
+
struct clk_hw *hw;
75
+
int i, ret;
76
+
77
+
data = devm_kzalloc(&pdev->dev,
78
+
struct_size(data, clk_data.hws, ARRAY_SIZE(gates)),
79
+
GFP_KERNEL);
80
+
if (!data)
81
+
return -ENOMEM;
82
+
83
+
dev_set_drvdata(&pdev->dev, data);
84
+
85
+
/*
86
+
* this lock is used directly by the clock gate and indirectly
87
+
* by the reset and mux controller via the regmap API
88
+
*/
89
+
spin_lock_init(&data->lock);
90
+
91
+
base = devm_platform_ioremap_resource(pdev, 0);
92
+
if (IS_ERR(base))
93
+
return dev_err_probe(&pdev->dev, PTR_ERR(base),
94
+
"failed to ioremap base\n");
95
+
/*
96
+
* although the clock gate doesn't use the regmap API to modify the
97
+
* registers, we still need the regmap because of the reset auxiliary
98
+
* driver and the MUX drivers, which use the parent device's regmap
99
+
*/
100
+
regmap = devm_regmap_init_mmio(&pdev->dev, base, ®map_config);
101
+
if (IS_ERR(regmap))
102
+
return dev_err_probe(&pdev->dev, PTR_ERR(regmap),
103
+
"failed to initialize regmap\n");
104
+
105
+
data->clk_data.num = ARRAY_SIZE(gates);
106
+
107
+
for (i = 0; i < ARRAY_SIZE(gates); i++) {
108
+
hw = devm_clk_hw_register_gate_parent_data(&pdev->dev,
109
+
gates[i].name,
110
+
&gates[i].parent,
111
+
CLK_SET_RATE_PARENT,
112
+
base + SYSCTRL0,
113
+
gates[i].bit,
114
+
0x0, &data->lock);
115
+
if (IS_ERR(hw))
116
+
return dev_err_probe(&pdev->dev, PTR_ERR(hw),
117
+
"failed to register %s gate\n",
118
+
gates[i].name);
119
+
120
+
data->clk_data.hws[i] = hw;
121
+
}
122
+
123
+
adev = devm_auxiliary_device_create(&pdev->dev, "reset", NULL);
124
+
if (!adev)
125
+
return dev_err_probe(&pdev->dev, -ENODEV,
126
+
"failed to register aux reset\n");
127
+
128
+
ret = devm_of_clk_add_hw_provider(&pdev->dev,
129
+
of_clk_hw_onecell_get,
130
+
&data->clk_data);
131
+
if (ret)
132
+
return dev_err_probe(&pdev->dev, ret,
133
+
"failed to register clk hw provider\n");
134
+
135
+
/* used to probe MUX child device */
136
+
return devm_of_platform_populate(&pdev->dev);
137
+
}
138
+
139
+
static const struct of_device_id clk_imx8ulp_sim_lpav_of_match[] = {
140
+
{ .compatible = "fsl,imx8ulp-sim-lpav" },
141
+
{ }
142
+
};
143
+
MODULE_DEVICE_TABLE(of, clk_imx8ulp_sim_lpav_of_match);
144
+
145
+
static struct platform_driver clk_imx8ulp_sim_lpav_driver = {
146
+
.probe = clk_imx8ulp_sim_lpav_probe,
147
+
.driver = {
148
+
.name = "clk-imx8ulp-sim-lpav",
149
+
.of_match_table = clk_imx8ulp_sim_lpav_of_match,
150
+
},
151
+
};
152
+
module_platform_driver(clk_imx8ulp_sim_lpav_driver);
153
+
154
+
MODULE_LICENSE("GPL");
155
+
MODULE_DESCRIPTION("i.MX8ULP LPAV System Integration Module (SIM) clock driver");
156
+
MODULE_AUTHOR("Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>");
+2
drivers/clk/microchip/Kconfig
+2
drivers/clk/microchip/Kconfig
+184
-43
drivers/clk/microchip/clk-mpfs.c
+184
-43
drivers/clk/microchip/clk-mpfs.c
···
4
4
*
5
5
* Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved.
6
6
*/
7
+
#include <linux/cleanup.h>
7
8
#include <linux/clk-provider.h>
8
9
#include <linux/io.h>
10
+
#include <linux/mfd/syscon.h>
9
11
#include <linux/module.h>
10
12
#include <linux/platform_device.h>
13
+
#include <linux/regmap.h>
11
14
#include <dt-bindings/clock/microchip,mpfs-clock.h>
12
15
#include <soc/microchip/mpfs.h>
13
16
···
33
30
#define MSSPLL_POSTDIV_WIDTH 0x07u
34
31
#define MSSPLL_FIXED_DIV 4u
35
32
33
+
static const struct regmap_config mpfs_clk_regmap_config = {
34
+
.reg_bits = 32,
35
+
.reg_stride = 4,
36
+
.val_bits = 32,
37
+
.val_format_endian = REGMAP_ENDIAN_LITTLE,
38
+
.max_register = REG_SUBBLK_RESET_CR,
39
+
};
40
+
36
41
/*
37
42
* This clock ID is defined here, rather than the binding headers, as it is an
38
43
* internal clock only, and therefore has no consumers in other peripheral
···
50
39
51
40
struct mpfs_clock_data {
52
41
struct device *dev;
42
+
struct regmap *regmap;
53
43
void __iomem *base;
54
44
void __iomem *msspll_base;
55
45
struct clk_hw_onecell_data hw_data;
···
79
67
80
68
#define to_mpfs_msspll_out_clk(_hw) container_of(_hw, struct mpfs_msspll_out_hw_clock, hw)
81
69
70
+
struct mpfs_cfg_clock {
71
+
struct regmap *map;
72
+
const struct clk_div_table *table;
73
+
u8 map_offset;
74
+
u8 shift;
75
+
u8 width;
76
+
u8 flags;
77
+
};
78
+
82
79
struct mpfs_cfg_hw_clock {
83
-
struct clk_divider cfg;
84
-
struct clk_init_data init;
80
+
struct clk_hw hw;
81
+
struct mpfs_cfg_clock cfg;
85
82
unsigned int id;
86
-
u32 reg_offset;
83
+
};
84
+
85
+
#define to_mpfs_cfg_clk(_hw) container_of(_hw, struct mpfs_cfg_hw_clock, hw)
86
+
87
+
struct mpfs_periph_clock {
88
+
struct regmap *map;
89
+
u8 map_offset;
90
+
u8 shift;
87
91
};
88
92
89
93
struct mpfs_periph_hw_clock {
90
-
struct clk_gate periph;
94
+
struct clk_hw hw;
95
+
struct mpfs_periph_clock periph;
91
96
unsigned int id;
92
97
};
93
98
99
+
#define to_mpfs_periph_clk(_hw) container_of(_hw, struct mpfs_periph_hw_clock, hw)
100
+
94
101
/*
95
-
* mpfs_clk_lock prevents anything else from writing to the
96
-
* mpfs clk block while a software locked register is being written.
102
+
* Protects MSSPLL outputs, since there's two to a register
97
103
*/
98
104
static DEFINE_SPINLOCK(mpfs_clk_lock);
99
105
···
249
219
/*
250
220
* "CFG" clocks
251
221
*/
222
+
static unsigned long mpfs_cfg_clk_recalc_rate(struct clk_hw *hw, unsigned long prate)
223
+
{
224
+
struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw);
225
+
struct mpfs_cfg_clock *cfg = &cfg_hw->cfg;
226
+
u32 val;
252
227
253
-
#define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offset) { \
254
-
.id = _id, \
255
-
.cfg.shift = _shift, \
256
-
.cfg.width = _width, \
257
-
.cfg.table = _table, \
258
-
.reg_offset = _offset, \
259
-
.cfg.flags = _flags, \
260
-
.cfg.hw.init = CLK_HW_INIT(_name, _parent, &clk_divider_ops, 0), \
261
-
.cfg.lock = &mpfs_clk_lock, \
228
+
regmap_read(cfg->map, cfg->map_offset, &val);
229
+
val >>= cfg->shift;
230
+
val &= clk_div_mask(cfg->width);
231
+
232
+
return divider_recalc_rate(hw, prate, val, cfg->table, cfg->flags, cfg->width);
233
+
}
234
+
235
+
static int mpfs_cfg_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
236
+
{
237
+
struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw);
238
+
struct mpfs_cfg_clock *cfg = &cfg_hw->cfg;
239
+
240
+
return divider_determine_rate(hw, req, cfg->table, cfg->width, 0);
241
+
}
242
+
243
+
static int mpfs_cfg_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate)
244
+
{
245
+
struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw);
246
+
struct mpfs_cfg_clock *cfg = &cfg_hw->cfg;
247
+
int divider_setting;
248
+
u32 val;
249
+
u32 mask;
250
+
251
+
divider_setting = divider_get_val(rate, prate, cfg->table, cfg->width, 0);
252
+
253
+
if (divider_setting < 0)
254
+
return divider_setting;
255
+
256
+
mask = clk_div_mask(cfg->width) << cfg->shift;
257
+
val = divider_setting << cfg->shift;
258
+
regmap_update_bits(cfg->map, cfg->map_offset, val, mask);
259
+
260
+
return 0;
261
+
}
262
+
263
+
static const struct clk_ops mpfs_clk_cfg_ops = {
264
+
.recalc_rate = mpfs_cfg_clk_recalc_rate,
265
+
.determine_rate = mpfs_cfg_clk_determine_rate,
266
+
.set_rate = mpfs_cfg_clk_set_rate,
267
+
};
268
+
269
+
#define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offset) { \
270
+
.id = _id, \
271
+
.cfg.shift = _shift, \
272
+
.cfg.width = _width, \
273
+
.cfg.table = _table, \
274
+
.cfg.map_offset = _offset, \
275
+
.cfg.flags = _flags, \
276
+
.hw.init = CLK_HW_INIT(_name, _parent, &mpfs_clk_cfg_ops, 0), \
262
277
}
263
278
264
279
#define CLK_CPU_OFFSET 0u
···
323
248
.cfg.shift = 0,
324
249
.cfg.width = 12,
325
250
.cfg.table = mpfs_div_rtcref_table,
326
-
.reg_offset = REG_RTC_CLOCK_CR,
251
+
.cfg.map_offset = REG_RTC_CLOCK_CR,
327
252
.cfg.flags = CLK_DIVIDER_ONE_BASED,
328
-
.cfg.hw.init =
329
-
CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &clk_divider_ops, 0),
253
+
.hw.init =
254
+
CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &mpfs_clk_cfg_ops, 0),
330
255
}
331
256
};
332
257
···
339
264
for (i = 0; i < num_clks; i++) {
340
265
struct mpfs_cfg_hw_clock *cfg_hw = &cfg_hws[i];
341
266
342
-
cfg_hw->cfg.reg = data->base + cfg_hw->reg_offset;
343
-
ret = devm_clk_hw_register(dev, &cfg_hw->cfg.hw);
267
+
cfg_hw->cfg.map = data->regmap;
268
+
ret = devm_clk_hw_register(dev, &cfg_hw->hw);
344
269
if (ret)
345
270
return dev_err_probe(dev, ret, "failed to register clock id: %d\n",
346
271
cfg_hw->id);
347
272
348
273
id = cfg_hw->id;
349
-
data->hw_data.hws[id] = &cfg_hw->cfg.hw;
274
+
data->hw_data.hws[id] = &cfg_hw->hw;
350
275
}
351
276
352
277
return 0;
···
356
281
* peripheral clocks - devices connected to axi or ahb buses.
357
282
*/
358
283
359
-
#define CLK_PERIPH(_id, _name, _parent, _shift, _flags) { \
360
-
.id = _id, \
361
-
.periph.bit_idx = _shift, \
362
-
.periph.hw.init = CLK_HW_INIT_HW(_name, _parent, &clk_gate_ops, \
363
-
_flags), \
364
-
.periph.lock = &mpfs_clk_lock, \
284
+
static int mpfs_periph_clk_enable(struct clk_hw *hw)
285
+
{
286
+
struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
287
+
struct mpfs_periph_clock *periph = &periph_hw->periph;
288
+
289
+
regmap_update_bits(periph->map, periph->map_offset,
290
+
BIT(periph->shift), BIT(periph->shift));
291
+
292
+
return 0;
365
293
}
366
294
367
-
#define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT##_OFFSET].cfg.hw)
295
+
static void mpfs_periph_clk_disable(struct clk_hw *hw)
296
+
{
297
+
struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
298
+
struct mpfs_periph_clock *periph = &periph_hw->periph;
299
+
300
+
regmap_update_bits(periph->map, periph->map_offset, BIT(periph->shift), 0);
301
+
}
302
+
303
+
static int mpfs_periph_clk_is_enabled(struct clk_hw *hw)
304
+
{
305
+
struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
306
+
struct mpfs_periph_clock *periph = &periph_hw->periph;
307
+
u32 val;
308
+
309
+
regmap_read(periph->map, periph->map_offset, &val);
310
+
311
+
return !!(val & BIT(periph->shift));
312
+
}
313
+
314
+
static const struct clk_ops mpfs_periph_clk_ops = {
315
+
.enable = mpfs_periph_clk_enable,
316
+
.disable = mpfs_periph_clk_disable,
317
+
.is_enabled = mpfs_periph_clk_is_enabled,
318
+
};
319
+
320
+
#define CLK_PERIPH(_id, _name, _parent, _shift, _flags) { \
321
+
.id = _id, \
322
+
.periph.map_offset = REG_SUBBLK_CLOCK_CR, \
323
+
.periph.shift = _shift, \
324
+
.hw.init = CLK_HW_INIT_HW(_name, _parent, &mpfs_periph_clk_ops, _flags), \
325
+
}
326
+
327
+
#define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT##_OFFSET].hw)
368
328
369
329
/*
370
330
* Critical clocks:
···
456
346
for (i = 0; i < num_clks; i++) {
457
347
struct mpfs_periph_hw_clock *periph_hw = &periph_hws[i];
458
348
459
-
periph_hw->periph.reg = data->base + REG_SUBBLK_CLOCK_CR;
460
-
ret = devm_clk_hw_register(dev, &periph_hw->periph.hw);
349
+
periph_hw->periph.map = data->regmap;
350
+
ret = devm_clk_hw_register(dev, &periph_hw->hw);
461
351
if (ret)
462
352
return dev_err_probe(dev, ret, "failed to register clock id: %d\n",
463
353
periph_hw->id);
464
354
465
355
id = periph_hws[i].id;
466
-
data->hw_data.hws[id] = &periph_hw->periph.hw;
356
+
data->hw_data.hws[id] = &periph_hw->hw;
467
357
}
468
358
469
359
return 0;
360
+
}
361
+
362
+
static inline int mpfs_clk_syscon_probe(struct mpfs_clock_data *clk_data,
363
+
struct platform_device *pdev)
364
+
{
365
+
clk_data->regmap = syscon_regmap_lookup_by_compatible("microchip,mpfs-mss-top-sysreg");
366
+
if (IS_ERR(clk_data->regmap))
367
+
return PTR_ERR(clk_data->regmap);
368
+
369
+
clk_data->msspll_base = devm_platform_ioremap_resource(pdev, 0);
370
+
if (IS_ERR(clk_data->msspll_base))
371
+
return PTR_ERR(clk_data->msspll_base);
372
+
373
+
return 0;
374
+
}
375
+
376
+
static inline int mpfs_clk_old_format_probe(struct mpfs_clock_data *clk_data,
377
+
struct platform_device *pdev)
378
+
{
379
+
struct device *dev = &pdev->dev;
380
+
381
+
dev_warn(&pdev->dev, "falling back to old devicetree format");
382
+
383
+
clk_data->base = devm_platform_ioremap_resource(pdev, 0);
384
+
if (IS_ERR(clk_data->base))
385
+
return PTR_ERR(clk_data->base);
386
+
387
+
clk_data->msspll_base = devm_platform_ioremap_resource(pdev, 1);
388
+
if (IS_ERR(clk_data->msspll_base))
389
+
return PTR_ERR(clk_data->msspll_base);
390
+
391
+
clk_data->regmap = devm_regmap_init_mmio(dev, clk_data->base, &mpfs_clk_regmap_config);
392
+
if (IS_ERR(clk_data->regmap))
393
+
return PTR_ERR(clk_data->regmap);
394
+
395
+
return mpfs_reset_controller_register(dev, clk_data->regmap);
470
396
}
471
397
472
398
static int mpfs_clk_probe(struct platform_device *pdev)
···
520
374
if (!clk_data)
521
375
return -ENOMEM;
522
376
523
-
clk_data->base = devm_platform_ioremap_resource(pdev, 0);
524
-
if (IS_ERR(clk_data->base))
525
-
return PTR_ERR(clk_data->base);
526
-
527
-
clk_data->msspll_base = devm_platform_ioremap_resource(pdev, 1);
528
-
if (IS_ERR(clk_data->msspll_base))
529
-
return PTR_ERR(clk_data->msspll_base);
377
+
ret = mpfs_clk_syscon_probe(clk_data, pdev);
378
+
if (ret) {
379
+
ret = mpfs_clk_old_format_probe(clk_data, pdev);
380
+
if (ret)
381
+
return ret;
382
+
}
530
383
531
384
clk_data->hw_data.num = num_clks;
532
385
clk_data->dev = dev;
···
551
406
if (ret)
552
407
return ret;
553
408
554
-
ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clk_data->hw_data);
555
-
if (ret)
556
-
return ret;
557
-
558
-
return mpfs_reset_controller_register(dev, clk_data->base + REG_SUBBLK_RESET_CR);
409
+
return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clk_data->hw_data);
559
410
}
560
411
561
412
static const struct of_device_id mpfs_clk_of_match_table[] = {
+29
-3
drivers/clk/qcom/Kconfig
+29
-3
drivers/clk/qcom/Kconfig
···
215
215
devices.
216
216
217
217
config IPQ_APSS_5424
218
-
tristate "IPQ APSS Clock Controller"
218
+
tristate "IPQ5424 APSS Clock Controller"
219
219
select IPQ_APSS_PLL
220
220
default y if IPQ_GCC_5424
221
221
help
222
-
Support for APSS Clock controller on Qualcom IPQ5424 platform.
222
+
Support for APSS Clock controller on Qualcomm IPQ5424 platform.
223
223
Say Y if you want to support CPU frequency scaling on ipq based
224
224
devices.
225
225
226
226
config IPQ_APSS_6018
227
-
tristate "IPQ APSS Clock Controller"
227
+
tristate "IPQ6018 APSS Clock Controller"
228
228
select IPQ_APSS_PLL
229
229
depends on QCOM_APCS_IPC || COMPILE_TEST
230
230
depends on QCOM_SMEM
···
316
316
Say Y if you want to use peripheral devices such as UART, SPI,
317
317
i2c, USB, SD/eMMC, etc. Select this for the root clock
318
318
of ipq9574.
319
+
320
+
config IPQ_NSSCC_5424
321
+
tristate "IPQ5424 NSS Clock Controller"
322
+
depends on ARM64 || COMPILE_TEST
323
+
depends on IPQ_GCC_5424
324
+
help
325
+
Support for NSS clock controller on ipq5424 devices.
326
+
NSSCC receives the clock sources from GCC, CMN PLL and UNIPHY (PCS).
327
+
It in turn supplies the clocks and resets to the networking hardware.
328
+
Say Y or M if you want to enable networking function on the
329
+
IPQ5424 devices.
319
330
320
331
config IPQ_NSSCC_9574
321
332
tristate "IPQ9574 NSS Clock Controller"
···
542
531
543
532
config QCS_DISPCC_615
544
533
tristate "QCS615 Display Clock Controller"
534
+
depends on ARM64 || COMPILE_TEST
545
535
select QCS_GCC_615
546
536
help
547
537
Support for the display clock controller on Qualcomm Technologies, Inc
···
598
586
599
587
config QCS_GPUCC_615
600
588
tristate "QCS615 Graphics clock controller"
589
+
depends on ARM64 || COMPILE_TEST
601
590
select QCS_GCC_615
602
591
help
603
592
Support for the graphics clock controller on QCS615 devices.
···
607
594
608
595
config QCS_VIDEOCC_615
609
596
tristate "QCS615 Video Clock Controller"
597
+
depends on ARM64 || COMPILE_TEST
610
598
select QCS_GCC_615
611
599
help
612
600
Support for the video clock controller on QCS615 devices.
···
1462
1448
1463
1449
config SM_VIDEOCC_6350
1464
1450
tristate "SM6350 Video Clock Controller"
1451
+
depends on ARM64 || COMPILE_TEST
1465
1452
select SM_GCC_6350
1466
1453
select QCOM_GDSC
1467
1454
help
···
1528
1513
help
1529
1514
Support for the video clock controller on Qualcomm Technologies, Inc.
1530
1515
SM8550 or SM8650 or X1E80100 devices.
1516
+
Say Y if you want to support video devices and functionality such as
1517
+
video encode/decode.
1518
+
1519
+
config SM_VIDEOCC_8750
1520
+
tristate "SM8750 Video Clock Controller"
1521
+
depends on ARM64 || COMPILE_TEST
1522
+
select SM_GCC_8750
1523
+
select QCOM_GDSC
1524
+
help
1525
+
Support for the video clock controller on Qualcomm Technologies, Inc.
1526
+
SM8750 devices.
1531
1527
Say Y if you want to support video devices and functionality such as
1532
1528
video encode/decode.
1533
1529
+2
drivers/clk/qcom/Makefile
+2
drivers/clk/qcom/Makefile
···
43
43
obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
44
44
obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
45
45
obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o
46
+
obj-$(CONFIG_IPQ_NSSCC_5424) += nsscc-ipq5424.o
46
47
obj-$(CONFIG_IPQ_NSSCC_9574) += nsscc-ipq9574.o
47
48
obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
48
49
obj-$(CONFIG_IPQ_NSSCC_QCA8K) += nsscc-qca8k.o
···
185
184
obj-$(CONFIG_SM_VIDEOCC_8350) += videocc-sm8350.o
186
185
obj-$(CONFIG_SM_VIDEOCC_8450) += videocc-sm8450.o
187
186
obj-$(CONFIG_SM_VIDEOCC_8550) += videocc-sm8550.o
187
+
obj-$(CONFIG_SM_VIDEOCC_8750) += videocc-sm8750.o
188
188
obj-$(CONFIG_SM_VIDEOCC_MILOS) += videocc-milos.o
189
189
obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
190
190
obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
-7
drivers/clk/qcom/apss-ipq5424.c
-7
drivers/clk/qcom/apss-ipq5424.c
···
35
35
P_L3_PLL,
36
36
};
37
37
38
-
struct apss_clk {
39
-
struct notifier_block cpu_clk_notifier;
40
-
struct clk_hw *hw;
41
-
struct device *dev;
42
-
struct clk *l3_clk;
43
-
};
44
-
45
38
static const struct alpha_pll_config apss_pll_config = {
46
39
.l = 0x3b,
47
40
.config_ctl_val = 0x08200920,
+3
drivers/clk/qcom/camcc-sdm845.c
+3
drivers/clk/qcom/camcc-sdm845.c
···
1543
1543
.name = "bps_gdsc",
1544
1544
},
1545
1545
.flags = HW_CTRL | POLL_CFG_GDSCR,
1546
+
.parent = &titan_top_gdsc.pd,
1546
1547
.pwrsts = PWRSTS_OFF_ON,
1547
1548
};
1548
1549
···
1553
1552
.name = "ipe_0_gdsc",
1554
1553
},
1555
1554
.flags = HW_CTRL | POLL_CFG_GDSCR,
1555
+
.parent = &titan_top_gdsc.pd,
1556
1556
.pwrsts = PWRSTS_OFF_ON,
1557
1557
};
1558
1558
···
1563
1561
.name = "ipe_1_gdsc",
1564
1562
},
1565
1563
.flags = HW_CTRL | POLL_CFG_GDSCR,
1564
+
.parent = &titan_top_gdsc.pd,
1566
1565
.pwrsts = PWRSTS_OFF_ON,
1567
1566
};
1568
1567
+8
-5
drivers/clk/qcom/camcc-sm6350.c
+8
-5
drivers/clk/qcom/camcc-sm6350.c
···
145
145
static const struct alpha_pll_config camcc_pll2_config = {
146
146
.l = 0x64,
147
147
.alpha = 0x0,
148
-
.post_div_val = 0x3 << 8,
149
-
.post_div_mask = 0x3 << 8,
150
-
.aux_output_mask = BIT(1),
151
-
.main_output_mask = BIT(0),
152
-
.early_output_mask = BIT(3),
153
148
.config_ctl_val = 0x20000800,
154
149
.config_ctl_hi_val = 0x400003d2,
155
150
.test_ctl_val = 0x04000400,
156
151
.test_ctl_hi_val = 0x00004000,
152
+
.user_ctl_val = 0x0000030b,
157
153
};
158
154
159
155
static struct clk_alpha_pll camcc_pll2 = {
···
1689
1693
},
1690
1694
};
1691
1695
1696
+
static struct gdsc titan_top_gdsc;
1697
+
1692
1698
static struct gdsc bps_gdsc = {
1693
1699
.gdscr = 0x6004,
1694
1700
.en_rest_wait_val = 0x2,
···
1700
1702
.name = "bps_gdsc",
1701
1703
},
1702
1704
.pwrsts = PWRSTS_OFF_ON,
1705
+
.parent = &titan_top_gdsc.pd,
1703
1706
.flags = VOTABLE,
1704
1707
};
1705
1708
···
1713
1714
.name = "ipe_0_gdsc",
1714
1715
},
1715
1716
.pwrsts = PWRSTS_OFF_ON,
1717
+
.parent = &titan_top_gdsc.pd,
1716
1718
.flags = VOTABLE,
1717
1719
};
1718
1720
···
1726
1726
.name = "ife_0_gdsc",
1727
1727
},
1728
1728
.pwrsts = PWRSTS_OFF_ON,
1729
+
.parent = &titan_top_gdsc.pd,
1729
1730
};
1730
1731
1731
1732
static struct gdsc ife_1_gdsc = {
···
1738
1737
.name = "ife_1_gdsc",
1739
1738
},
1740
1739
.pwrsts = PWRSTS_OFF_ON,
1740
+
.parent = &titan_top_gdsc.pd,
1741
1741
};
1742
1742
1743
1743
static struct gdsc ife_2_gdsc = {
···
1750
1748
.name = "ife_2_gdsc",
1751
1749
},
1752
1750
.pwrsts = PWRSTS_OFF_ON,
1751
+
.parent = &titan_top_gdsc.pd,
1753
1752
};
1754
1753
1755
1754
static struct gdsc titan_top_gdsc = {
+5
-6
drivers/clk/qcom/camcc-sm7150.c
+5
-6
drivers/clk/qcom/camcc-sm7150.c
···
139
139
/* 1920MHz configuration */
140
140
static const struct alpha_pll_config camcc_pll2_config = {
141
141
.l = 0x64,
142
-
.post_div_val = 0x3 << 8,
143
-
.post_div_mask = 0x3 << 8,
144
-
.early_output_mask = BIT(3),
145
-
.aux_output_mask = BIT(1),
146
-
.main_output_mask = BIT(0),
147
142
.config_ctl_hi_val = 0x400003d6,
148
143
.config_ctl_val = 0x20000954,
144
+
.user_ctl_val = 0x0000030b,
149
145
};
150
146
151
147
static struct clk_alpha_pll camcc_pll2 = {
···
1842
1846
.name = "camcc_bps_gdsc",
1843
1847
},
1844
1848
.flags = HW_CTRL | POLL_CFG_GDSCR,
1849
+
.parent = &camcc_titan_top_gdsc.pd,
1845
1850
.pwrsts = PWRSTS_OFF_ON,
1846
1851
};
1847
1852
···
1872
1875
.name = "camcc_ipe_0_gdsc",
1873
1876
},
1874
1877
.flags = HW_CTRL | POLL_CFG_GDSCR,
1878
+
.parent = &camcc_titan_top_gdsc.pd,
1875
1879
.pwrsts = PWRSTS_OFF_ON,
1876
1880
};
1877
1881
···
1882
1884
.name = "camcc_ipe_1_gdsc",
1883
1885
},
1884
1886
.flags = HW_CTRL | POLL_CFG_GDSCR,
1887
+
.parent = &camcc_titan_top_gdsc.pd,
1885
1888
.pwrsts = PWRSTS_OFF_ON,
1886
1889
};
1887
1890
···
1895
1896
.pwrsts = PWRSTS_OFF_ON,
1896
1897
};
1897
1898
1898
-
struct clk_hw *camcc_sm7150_hws[] = {
1899
+
static struct clk_hw *camcc_sm7150_hws[] = {
1899
1900
[CAMCC_PLL0_OUT_EVEN] = &camcc_pll0_out_even.hw,
1900
1901
[CAMCC_PLL0_OUT_ODD] = &camcc_pll0_out_odd.hw,
1901
1902
[CAMCC_PLL1_OUT_EVEN] = &camcc_pll1_out_even.hw,
+3
drivers/clk/qcom/camcc-sm8250.c
+3
drivers/clk/qcom/camcc-sm8250.c
···
2213
2213
.name = "bps_gdsc",
2214
2214
},
2215
2215
.flags = HW_CTRL | POLL_CFG_GDSCR,
2216
+
.parent = &titan_top_gdsc.pd,
2216
2217
.pwrsts = PWRSTS_OFF_ON,
2217
2218
};
2218
2219
···
2223
2222
.name = "ipe_0_gdsc",
2224
2223
},
2225
2224
.flags = HW_CTRL | POLL_CFG_GDSCR,
2225
+
.parent = &titan_top_gdsc.pd,
2226
2226
.pwrsts = PWRSTS_OFF_ON,
2227
2227
};
2228
2228
···
2233
2231
.name = "sbi_gdsc",
2234
2232
},
2235
2233
.flags = HW_CTRL | POLL_CFG_GDSCR,
2234
+
.parent = &titan_top_gdsc.pd,
2236
2235
.pwrsts = PWRSTS_OFF_ON,
2237
2236
};
2238
2237
+3
drivers/clk/qcom/camcc-sm8450.c
+3
drivers/clk/qcom/camcc-sm8450.c
···
2935
2935
.name = "bps_gdsc",
2936
2936
},
2937
2937
.flags = HW_CTRL | POLL_CFG_GDSCR,
2938
+
.parent = &titan_top_gdsc.pd,
2938
2939
.pwrsts = PWRSTS_OFF_ON,
2939
2940
};
2940
2941
···
2945
2944
.name = "ipe_0_gdsc",
2946
2945
},
2947
2946
.flags = HW_CTRL | POLL_CFG_GDSCR,
2947
+
.parent = &titan_top_gdsc.pd,
2948
2948
.pwrsts = PWRSTS_OFF_ON,
2949
2949
};
2950
2950
···
2955
2953
.name = "sbi_gdsc",
2956
2954
},
2957
2955
.flags = POLL_CFG_GDSCR,
2956
+
.parent = &titan_top_gdsc.pd,
2958
2957
.pwrsts = PWRSTS_OFF_ON,
2959
2958
};
2960
2959
+10
drivers/clk/qcom/camcc-sm8550.c
+10
drivers/clk/qcom/camcc-sm8550.c
···
3204
3204
},
3205
3205
};
3206
3206
3207
+
static struct gdsc cam_cc_titan_top_gdsc;
3208
+
3207
3209
static struct gdsc cam_cc_bps_gdsc = {
3208
3210
.gdscr = 0x10004,
3209
3211
.en_rest_wait_val = 0x2,
···
3215
3213
.name = "cam_cc_bps_gdsc",
3216
3214
},
3217
3215
.pwrsts = PWRSTS_OFF_ON,
3216
+
.parent = &cam_cc_titan_top_gdsc.pd,
3218
3217
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3219
3218
};
3220
3219
···
3228
3225
.name = "cam_cc_ife_0_gdsc",
3229
3226
},
3230
3227
.pwrsts = PWRSTS_OFF_ON,
3228
+
.parent = &cam_cc_titan_top_gdsc.pd,
3231
3229
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3232
3230
};
3233
3231
···
3241
3237
.name = "cam_cc_ife_1_gdsc",
3242
3238
},
3243
3239
.pwrsts = PWRSTS_OFF_ON,
3240
+
.parent = &cam_cc_titan_top_gdsc.pd,
3244
3241
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3245
3242
};
3246
3243
···
3254
3249
.name = "cam_cc_ife_2_gdsc",
3255
3250
},
3256
3251
.pwrsts = PWRSTS_OFF_ON,
3252
+
.parent = &cam_cc_titan_top_gdsc.pd,
3257
3253
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3258
3254
};
3259
3255
···
3267
3261
.name = "cam_cc_ipe_0_gdsc",
3268
3262
},
3269
3263
.pwrsts = PWRSTS_OFF_ON,
3264
+
.parent = &cam_cc_titan_top_gdsc.pd,
3270
3265
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3271
3266
};
3272
3267
···
3280
3273
.name = "cam_cc_sbi_gdsc",
3281
3274
},
3282
3275
.pwrsts = PWRSTS_OFF_ON,
3276
+
.parent = &cam_cc_titan_top_gdsc.pd,
3283
3277
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3284
3278
};
3285
3279
···
3293
3285
.name = "cam_cc_sfe_0_gdsc",
3294
3286
},
3295
3287
.pwrsts = PWRSTS_OFF_ON,
3288
+
.parent = &cam_cc_titan_top_gdsc.pd,
3296
3289
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3297
3290
};
3298
3291
···
3306
3297
.name = "cam_cc_sfe_1_gdsc",
3307
3298
},
3308
3299
.pwrsts = PWRSTS_OFF_ON,
3300
+
.parent = &cam_cc_titan_top_gdsc.pd,
3309
3301
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
3310
3302
};
3311
3303
+4
-4
drivers/clk/qcom/clk-branch.c
+4
-4
drivers/clk/qcom/clk-branch.c
···
142
142
u32 val;
143
143
int ret;
144
144
145
-
regmap_update_bits(branch.clkr.regmap, mem_br->mem_enable_reg,
146
-
mem_br->mem_enable_ack_mask, mem_br->mem_enable_ack_mask);
145
+
regmap_assign_bits(branch.clkr.regmap, mem_br->mem_enable_reg,
146
+
mem_br->mem_enable_mask, !mem_br->mem_enable_invert);
147
147
148
148
ret = regmap_read_poll_timeout(branch.clkr.regmap, mem_br->mem_ack_reg,
149
149
val, val & mem_br->mem_enable_ack_mask, 0, 200);
···
159
159
{
160
160
struct clk_mem_branch *mem_br = to_clk_mem_branch(hw);
161
161
162
-
regmap_update_bits(mem_br->branch.clkr.regmap, mem_br->mem_enable_reg,
163
-
mem_br->mem_enable_ack_mask, 0);
162
+
regmap_assign_bits(mem_br->branch.clkr.regmap, mem_br->mem_enable_reg,
163
+
mem_br->mem_enable_mask, mem_br->mem_enable_invert);
164
164
165
165
return clk_branch2_disable(hw);
166
166
}
+4
drivers/clk/qcom/clk-branch.h
+4
drivers/clk/qcom/clk-branch.h
···
44
44
* @mem_enable_reg: branch clock memory gating register
45
45
* @mem_ack_reg: branch clock memory ack register
46
46
* @mem_enable_ack_mask: branch clock memory enable and ack field in @mem_ack_reg
47
+
* @mem_enable_mask: branch clock memory enable mask
48
+
* @mem_enable_invert: branch clock memory enable and disable has invert logic
47
49
* @branch: branch clock gating handle
48
50
*
49
51
* Clock which can gate its memories.
···
54
52
u32 mem_enable_reg;
55
53
u32 mem_ack_reg;
56
54
u32 mem_enable_ack_mask;
55
+
u32 mem_enable_mask;
56
+
bool mem_enable_invert;
57
57
struct clk_branch branch;
58
58
};
59
59
+1
drivers/clk/qcom/clk-rpmh.c
+1
drivers/clk/qcom/clk-rpmh.c
+7
drivers/clk/qcom/dispcc-sm6350.c
+7
drivers/clk/qcom/dispcc-sm6350.c
···
679
679
},
680
680
};
681
681
682
+
static const struct qcom_reset_map disp_cc_sm6350_resets[] = {
683
+
[DISP_CC_MDSS_CORE_BCR] = { 0x1000 },
684
+
[DISP_CC_MDSS_RSCC_BCR] = { 0x2000 },
685
+
};
686
+
682
687
static struct gdsc mdss_gdsc = {
683
688
.gdscr = 0x1004,
684
689
.en_rest_wait_val = 0x2,
···
751
746
.num_clks = ARRAY_SIZE(disp_cc_sm6350_clocks),
752
747
.gdscs = disp_cc_sm6350_gdscs,
753
748
.num_gdscs = ARRAY_SIZE(disp_cc_sm6350_gdscs),
749
+
.resets = disp_cc_sm6350_resets,
750
+
.num_resets = ARRAY_SIZE(disp_cc_sm6350_resets),
754
751
};
755
752
756
753
static const struct of_device_id disp_cc_sm6350_match_table[] = {
+8
-1
drivers/clk/qcom/dispcc-sm7150.c
+8
-1
drivers/clk/qcom/dispcc-sm7150.c
···
20
20
#include "clk-regmap-divider.h"
21
21
#include "common.h"
22
22
#include "gdsc.h"
23
+
#include "reset.h"
23
24
24
25
enum {
25
26
DT_BI_TCXO,
···
357
356
.name = "dispcc_mdss_pclk0_clk_src",
358
357
.parent_data = dispcc_parent_data_4,
359
358
.num_parents = ARRAY_SIZE(dispcc_parent_data_4),
360
-
.flags = CLK_SET_RATE_PARENT,
359
+
.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
361
360
.ops = &clk_pixel_ops,
362
361
},
363
362
};
···
952
951
[MDSS_GDSC] = &mdss_gdsc,
953
952
};
954
953
954
+
static const struct qcom_reset_map dispcc_sm7150_resets[] = {
955
+
[DISPCC_MDSS_CORE_BCR] = { 0x2000 },
956
+
};
957
+
955
958
static const struct regmap_config dispcc_sm7150_regmap_config = {
956
959
.reg_bits = 32,
957
960
.reg_stride = 4,
···
970
965
.num_clks = ARRAY_SIZE(dispcc_sm7150_clocks),
971
966
.gdscs = dispcc_sm7150_gdscs,
972
967
.num_gdscs = ARRAY_SIZE(dispcc_sm7150_gdscs),
968
+
.resets = dispcc_sm7150_resets,
969
+
.num_resets = ARRAY_SIZE(dispcc_sm7150_resets),
973
970
};
974
971
975
972
static const struct of_device_id dispcc_sm7150_match_table[] = {
+3
drivers/clk/qcom/dispcc-x1e80100.c
+3
drivers/clk/qcom/dispcc-x1e80100.c
···
1618
1618
1619
1619
static const struct qcom_reset_map disp_cc_x1e80100_resets[] = {
1620
1620
[DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
1621
+
[DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK_ARES] = { .reg = 0x8044, .bit = 2 },
1622
+
[DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK_ARES] = { .reg = 0x8068, .bit = 2 },
1623
+
[DISP_CC_MDSS_DPTX2_USB_ROUTER_LINK_INTF_CLK_ARES] = { .reg = 0x8088, .bit = 2 },
1621
1624
[DISP_CC_MDSS_CORE_INT2_BCR] = { 0xa000 },
1622
1625
[DISP_CC_MDSS_RSCC_BCR] = { 0xc000 },
1623
1626
};
+30
drivers/clk/qcom/ecpricc-qdu1000.c
+30
drivers/clk/qcom/ecpricc-qdu1000.c
···
920
920
static struct clk_mem_branch ecpri_cc_eth_100g_c2c_0_hm_ff_0_clk = {
921
921
.mem_enable_reg = 0x8410,
922
922
.mem_ack_reg = 0x8424,
923
+
.mem_enable_mask = BIT(0),
923
924
.mem_enable_ack_mask = BIT(0),
924
925
.branch = {
925
926
.halt_reg = 0x80b4,
···
944
943
static struct clk_mem_branch ecpri_cc_eth_100g_c2c_0_hm_ff_1_clk = {
945
944
.mem_enable_reg = 0x8410,
946
945
.mem_ack_reg = 0x8424,
946
+
.mem_enable_mask = BIT(1),
947
947
.mem_enable_ack_mask = BIT(1),
948
948
.branch = {
949
949
.halt_reg = 0x80bc,
···
968
966
static struct clk_mem_branch ecpri_cc_eth_100g_c2c_hm_macsec_clk = {
969
967
.mem_enable_reg = 0x8410,
970
968
.mem_ack_reg = 0x8424,
969
+
.mem_enable_mask = BIT(4),
971
970
.mem_enable_ack_mask = BIT(4),
972
971
.branch = {
973
972
.halt_reg = 0x80ac,
···
992
989
static struct clk_mem_branch ecpri_cc_eth_100g_dbg_c2c_hm_ff_0_clk = {
993
990
.mem_enable_reg = 0x8414,
994
991
.mem_ack_reg = 0x8428,
992
+
.mem_enable_mask = BIT(0),
995
993
.mem_enable_ack_mask = BIT(0),
996
994
.branch = {
997
995
.halt_reg = 0x80d8,
···
1016
1012
static struct clk_mem_branch ecpri_cc_eth_100g_dbg_c2c_hm_ff_1_clk = {
1017
1013
.mem_enable_reg = 0x8414,
1018
1014
.mem_ack_reg = 0x8428,
1015
+
.mem_enable_mask = BIT(1),
1019
1016
.mem_enable_ack_mask = BIT(1),
1020
1017
.branch = {
1021
1018
.halt_reg = 0x80e0,
···
1058
1053
static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_0_clk = {
1059
1054
.mem_enable_reg = 0x8404,
1060
1055
.mem_ack_reg = 0x8418,
1056
+
.mem_enable_mask = BIT(0),
1061
1057
.mem_enable_ack_mask = BIT(0),
1062
1058
.branch = {
1063
1059
.halt_reg = 0x800c,
···
1082
1076
static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_1_clk = {
1083
1077
.mem_enable_reg = 0x8404,
1084
1078
.mem_ack_reg = 0x8418,
1079
+
.mem_enable_mask = BIT(1),
1085
1080
.mem_enable_ack_mask = BIT(1),
1086
1081
.branch = {
1087
1082
.halt_reg = 0x8014,
···
1106
1099
static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_2_clk = {
1107
1100
.mem_enable_reg = 0x8404,
1108
1101
.mem_ack_reg = 0x8418,
1102
+
.mem_enable_mask = BIT(2),
1109
1103
.mem_enable_ack_mask = BIT(2),
1110
1104
.branch = {
1111
1105
.halt_reg = 0x801c,
···
1130
1122
static struct clk_mem_branch ecpri_cc_eth_100g_fh_0_hm_ff_3_clk = {
1131
1123
.mem_enable_reg = 0x8404,
1132
1124
.mem_ack_reg = 0x8418,
1125
+
.mem_enable_mask = BIT(3),
1133
1126
.mem_enable_ack_mask = BIT(3),
1134
1127
.branch = {
1135
1128
.halt_reg = 0x8024,
···
1172
1163
static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_0_clk = {
1173
1164
.mem_enable_reg = 0x8408,
1174
1165
.mem_ack_reg = 0x841c,
1166
+
.mem_enable_mask = BIT(0),
1175
1167
.mem_enable_ack_mask = BIT(0),
1176
1168
.branch = {
1177
1169
.halt_reg = 0x8044,
···
1196
1186
static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_1_clk = {
1197
1187
.mem_enable_reg = 0x8408,
1198
1188
.mem_ack_reg = 0x841c,
1189
+
.mem_enable_mask = BIT(1),
1199
1190
.mem_enable_ack_mask = BIT(1),
1200
1191
.branch = {
1201
1192
.halt_reg = 0x804c,
···
1220
1209
static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_2_clk = {
1221
1210
.mem_enable_reg = 0x8408,
1222
1211
.mem_ack_reg = 0x841c,
1212
+
.mem_enable_mask = BIT(2),
1223
1213
.mem_enable_ack_mask = BIT(2),
1224
1214
.branch = {
1225
1215
.halt_reg = 0x8054,
···
1244
1232
static struct clk_mem_branch ecpri_cc_eth_100g_fh_1_hm_ff_3_clk = {
1245
1233
.mem_enable_reg = 0x8408,
1246
1234
.mem_ack_reg = 0x841c,
1235
+
.mem_enable_mask = BIT(3),
1247
1236
.mem_enable_ack_mask = BIT(3),
1248
1237
.branch = {
1249
1238
.halt_reg = 0x805c,
···
1286
1273
static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_0_clk = {
1287
1274
.mem_enable_reg = 0x840c,
1288
1275
.mem_ack_reg = 0x8420,
1276
+
.mem_enable_mask = BIT(0),
1289
1277
.mem_enable_ack_mask = BIT(0),
1290
1278
.branch = {
1291
1279
.halt_reg = 0x807c,
···
1310
1296
static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_1_clk = {
1311
1297
.mem_enable_reg = 0x840c,
1312
1298
.mem_ack_reg = 0x8420,
1299
+
.mem_enable_mask = BIT(1),
1313
1300
.mem_enable_ack_mask = BIT(1),
1314
1301
.branch = {
1315
1302
.halt_reg = 0x8084,
···
1334
1319
static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_2_clk = {
1335
1320
.mem_enable_reg = 0x840c,
1336
1321
.mem_ack_reg = 0x8420,
1322
+
.mem_enable_mask = BIT(2),
1337
1323
.mem_enable_ack_mask = BIT(2),
1338
1324
.branch = {
1339
1325
.halt_reg = 0x808c,
···
1358
1342
static struct clk_mem_branch ecpri_cc_eth_100g_fh_2_hm_ff_3_clk = {
1359
1343
.mem_enable_reg = 0x840c,
1360
1344
.mem_ack_reg = 0x8420,
1345
+
.mem_enable_mask = BIT(3),
1361
1346
.mem_enable_ack_mask = BIT(3),
1362
1347
.branch = {
1363
1348
.halt_reg = 0x8094,
···
1400
1383
static struct clk_mem_branch ecpri_cc_eth_100g_fh_macsec_0_clk = {
1401
1384
.mem_enable_reg = 0x8404,
1402
1385
.mem_ack_reg = 0x8418,
1386
+
.mem_enable_mask = BIT(4),
1403
1387
.mem_enable_ack_mask = BIT(4),
1404
1388
.branch = {
1405
1389
.halt_reg = 0x8004,
···
1424
1406
static struct clk_mem_branch ecpri_cc_eth_100g_fh_macsec_1_clk = {
1425
1407
.mem_enable_reg = 0x8408,
1426
1408
.mem_ack_reg = 0x841c,
1409
+
.mem_enable_mask = BIT(4),
1427
1410
.mem_enable_ack_mask = BIT(4),
1428
1411
.branch = {
1429
1412
.halt_reg = 0x803c,
···
1448
1429
static struct clk_mem_branch ecpri_cc_eth_100g_fh_macsec_2_clk = {
1449
1430
.mem_enable_reg = 0x840c,
1450
1431
.mem_ack_reg = 0x8420,
1432
+
.mem_enable_mask = BIT(4),
1451
1433
.mem_enable_ack_mask = BIT(4),
1452
1434
.branch = {
1453
1435
.halt_reg = 0x8074,
···
1472
1452
static struct clk_mem_branch ecpri_cc_eth_100g_mac_c2c_hm_ref_clk = {
1473
1453
.mem_enable_reg = 0x8410,
1474
1454
.mem_ack_reg = 0x8424,
1455
+
.mem_enable_mask = BIT(5),
1475
1456
.mem_enable_ack_mask = BIT(5),
1476
1457
.branch = {
1477
1458
.halt_reg = 0x80c4,
···
1496
1475
static struct clk_mem_branch ecpri_cc_eth_100g_mac_dbg_c2c_hm_ref_clk = {
1497
1476
.mem_enable_reg = 0x8414,
1498
1477
.mem_ack_reg = 0x8428,
1478
+
.mem_enable_mask = BIT(5),
1499
1479
.mem_enable_ack_mask = BIT(5),
1500
1480
.branch = {
1501
1481
.halt_reg = 0x80e8,
···
1520
1498
static struct clk_mem_branch ecpri_cc_eth_100g_mac_fh0_hm_ref_clk = {
1521
1499
.mem_enable_reg = 0x8404,
1522
1500
.mem_ack_reg = 0x8418,
1501
+
.mem_enable_mask = BIT(5),
1523
1502
.mem_enable_ack_mask = BIT(5),
1524
1503
.branch = {
1525
1504
.halt_reg = 0x802c,
···
1544
1521
static struct clk_mem_branch ecpri_cc_eth_100g_mac_fh1_hm_ref_clk = {
1545
1522
.mem_enable_reg = 0x8408,
1546
1523
.mem_ack_reg = 0x841c,
1524
+
.mem_enable_mask = BIT(5),
1547
1525
.mem_enable_ack_mask = BIT(5),
1548
1526
.branch = {
1549
1527
.halt_reg = 0x8064,
···
1568
1544
static struct clk_mem_branch ecpri_cc_eth_100g_mac_fh2_hm_ref_clk = {
1569
1545
.mem_enable_reg = 0x840c,
1570
1546
.mem_ack_reg = 0x8420,
1547
+
.mem_enable_mask = BIT(5),
1571
1548
.mem_enable_ack_mask = BIT(5),
1572
1549
.branch = {
1573
1550
.halt_reg = 0x809c,
···
1628
1603
static struct clk_mem_branch ecpri_cc_eth_phy_0_ock_sram_clk = {
1629
1604
.mem_enable_reg = 0x8404,
1630
1605
.mem_ack_reg = 0x8418,
1606
+
.mem_enable_mask = BIT(6),
1631
1607
.mem_enable_ack_mask = BIT(6),
1632
1608
.branch = {
1633
1609
.halt_reg = 0xd140,
···
1647
1621
static struct clk_mem_branch ecpri_cc_eth_phy_1_ock_sram_clk = {
1648
1622
.mem_enable_reg = 0x8408,
1649
1623
.mem_ack_reg = 0x841C,
1624
+
.mem_enable_mask = BIT(6),
1650
1625
.mem_enable_ack_mask = BIT(6),
1651
1626
.branch = {
1652
1627
.halt_reg = 0xd148,
···
1666
1639
static struct clk_mem_branch ecpri_cc_eth_phy_2_ock_sram_clk = {
1667
1640
.mem_enable_reg = 0x840c,
1668
1641
.mem_ack_reg = 0x8420,
1642
+
.mem_enable_mask = BIT(6),
1669
1643
.mem_enable_ack_mask = BIT(6),
1670
1644
.branch = {
1671
1645
.halt_reg = 0xd150,
···
1685
1657
static struct clk_mem_branch ecpri_cc_eth_phy_3_ock_sram_clk = {
1686
1658
.mem_enable_reg = 0x8410,
1687
1659
.mem_ack_reg = 0x8424,
1660
+
.mem_enable_mask = BIT(6),
1688
1661
.mem_enable_ack_mask = BIT(6),
1689
1662
.branch = {
1690
1663
.halt_reg = 0xd158,
···
1704
1675
static struct clk_mem_branch ecpri_cc_eth_phy_4_ock_sram_clk = {
1705
1676
.mem_enable_reg = 0x8414,
1706
1677
.mem_ack_reg = 0x8428,
1678
+
.mem_enable_mask = BIT(6),
1707
1679
.mem_enable_ack_mask = BIT(6),
1708
1680
.branch = {
1709
1681
.halt_reg = 0xd160,
+12
-13
drivers/clk/qcom/gcc-glymur.c
+12
-13
drivers/clk/qcom/gcc-glymur.c
···
2643
2643
};
2644
2644
2645
2645
static const struct freq_tbl ftbl_gcc_usb4_0_master_clk_src[] = {
2646
-
F(85714286, P_GCC_GPLL0_OUT_EVEN, 3.5, 0, 0),
2647
2646
F(177666750, P_GCC_GPLL8_OUT_MAIN, 4, 0, 0),
2648
2647
F(355333500, P_GCC_GPLL8_OUT_MAIN, 2, 0, 0),
2649
2648
{ }
···
6759
6760
6760
6761
static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
6761
6762
.halt_reg = 0x3f088,
6762
-
.halt_check = BRANCH_HALT_DELAY,
6763
+
.halt_check = BRANCH_HALT_SKIP,
6763
6764
.hwcg_reg = 0x3f088,
6764
6765
.hwcg_bit = 1,
6765
6766
.clkr = {
···
6815
6816
6816
6817
static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
6817
6818
.halt_reg = 0xe2078,
6818
-
.halt_check = BRANCH_HALT_VOTED,
6819
+
.halt_check = BRANCH_HALT_SKIP,
6819
6820
.hwcg_reg = 0xe2078,
6820
6821
.hwcg_bit = 1,
6821
6822
.clkr = {
···
6871
6872
6872
6873
static struct clk_branch gcc_usb3_tert_phy_pipe_clk = {
6873
6874
.halt_reg = 0xe1078,
6874
-
.halt_check = BRANCH_HALT_VOTED,
6875
+
.halt_check = BRANCH_HALT_SKIP,
6875
6876
.hwcg_reg = 0xe1078,
6876
6877
.hwcg_bit = 1,
6877
6878
.clkr = {
···
6960
6961
6961
6962
static struct clk_branch gcc_usb4_0_phy_p2rr2p_pipe_clk = {
6962
6963
.halt_reg = 0x2b0f4,
6963
-
.halt_check = BRANCH_HALT,
6964
+
.halt_check = BRANCH_HALT_SKIP,
6964
6965
.clkr = {
6965
6966
.enable_reg = 0x2b0f4,
6966
6967
.enable_mask = BIT(0),
···
6978
6979
6979
6980
static struct clk_branch gcc_usb4_0_phy_pcie_pipe_clk = {
6980
6981
.halt_reg = 0x2b04c,
6981
-
.halt_check = BRANCH_HALT_VOTED,
6982
+
.halt_check = BRANCH_HALT_SKIP,
6982
6983
.clkr = {
6983
6984
.enable_reg = 0x62010,
6984
6985
.enable_mask = BIT(11),
···
7032
7033
7033
7034
static struct clk_branch gcc_usb4_0_phy_usb_pipe_clk = {
7034
7035
.halt_reg = 0x2b0bc,
7035
-
.halt_check = BRANCH_HALT_VOTED,
7036
+
.halt_check = BRANCH_HALT_SKIP,
7036
7037
.hwcg_reg = 0x2b0bc,
7037
7038
.hwcg_bit = 1,
7038
7039
.clkr = {
···
7195
7196
7196
7197
static struct clk_branch gcc_usb4_1_phy_p2rr2p_pipe_clk = {
7197
7198
.halt_reg = 0x2d118,
7198
-
.halt_check = BRANCH_HALT,
7199
+
.halt_check = BRANCH_HALT_SKIP,
7199
7200
.clkr = {
7200
7201
.enable_reg = 0x2d118,
7201
7202
.enable_mask = BIT(0),
···
7213
7214
7214
7215
static struct clk_branch gcc_usb4_1_phy_pcie_pipe_clk = {
7215
7216
.halt_reg = 0x2d04c,
7216
-
.halt_check = BRANCH_HALT_VOTED,
7217
+
.halt_check = BRANCH_HALT_SKIP,
7217
7218
.clkr = {
7218
7219
.enable_reg = 0x62010,
7219
7220
.enable_mask = BIT(12),
···
7267
7268
7268
7269
static struct clk_branch gcc_usb4_1_phy_usb_pipe_clk = {
7269
7270
.halt_reg = 0x2d0e0,
7270
-
.halt_check = BRANCH_HALT_VOTED,
7271
+
.halt_check = BRANCH_HALT_SKIP,
7271
7272
.hwcg_reg = 0x2d0e0,
7272
7273
.hwcg_bit = 1,
7273
7274
.clkr = {
···
7430
7431
7431
7432
static struct clk_branch gcc_usb4_2_phy_p2rr2p_pipe_clk = {
7432
7433
.halt_reg = 0xe00f8,
7433
-
.halt_check = BRANCH_HALT,
7434
+
.halt_check = BRANCH_HALT_SKIP,
7434
7435
.clkr = {
7435
7436
.enable_reg = 0xe00f8,
7436
7437
.enable_mask = BIT(0),
···
7448
7449
7449
7450
static struct clk_branch gcc_usb4_2_phy_pcie_pipe_clk = {
7450
7451
.halt_reg = 0xe004c,
7451
-
.halt_check = BRANCH_HALT_VOTED,
7452
+
.halt_check = BRANCH_HALT_SKIP,
7452
7453
.clkr = {
7453
7454
.enable_reg = 0x62010,
7454
7455
.enable_mask = BIT(13),
···
7502
7503
7503
7504
static struct clk_branch gcc_usb4_2_phy_usb_pipe_clk = {
7504
7505
.halt_reg = 0xe00c0,
7505
-
.halt_check = BRANCH_HALT_VOTED,
7506
+
.halt_check = BRANCH_HALT_SKIP,
7506
7507
.hwcg_reg = 0xe00c0,
7507
7508
.hwcg_bit = 1,
7508
7509
.clkr = {
+27
-1
drivers/clk/qcom/gcc-ipq5424.c
+27
-1
drivers/clk/qcom/gcc-ipq5424.c
···
1
1
// SPDX-License-Identifier: GPL-2.0
2
2
/*
3
3
* Copyright (c) 2018,2020 The Linux Foundation. All rights reserved.
4
-
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
4
+
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
5
5
*/
6
6
7
7
#include <linux/clk-provider.h>
···
76
76
},
77
77
.num_parents = 1,
78
78
.ops = &clk_fixed_factor_ops,
79
+
},
80
+
};
81
+
82
+
static struct clk_alpha_pll_postdiv gpll0_out_aux = {
83
+
.offset = 0x20000,
84
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
85
+
.width = 4,
86
+
.clkr.hw.init = &(const struct clk_init_data) {
87
+
.name = "gpll0_out_aux",
88
+
.parent_hws = (const struct clk_hw *[]) {
89
+
&gpll0.clkr.hw
90
+
},
91
+
.num_parents = 1,
92
+
.ops = &clk_alpha_pll_postdiv_ro_ops,
79
93
},
80
94
};
81
95
···
2948
2934
[GPLL2] = &gpll2.clkr,
2949
2935
[GPLL2_OUT_MAIN] = &gpll2_out_main.clkr,
2950
2936
[GPLL4] = &gpll4.clkr,
2937
+
[GPLL0_OUT_AUX] = &gpll0_out_aux.clkr,
2951
2938
};
2952
2939
2953
2940
static const struct qcom_reset_map gcc_ipq5424_resets[] = {
···
3265
3250
{ MASTER_ANOC_PCIE3, SLAVE_ANOC_PCIE3, GCC_ANOC_PCIE3_2LANE_M_CLK },
3266
3251
{ MASTER_CNOC_PCIE3, SLAVE_CNOC_PCIE3, GCC_CNOC_PCIE3_2LANE_S_CLK },
3267
3252
{ MASTER_CNOC_USB, SLAVE_CNOC_USB, GCC_CNOC_USB_CLK },
3253
+
{ MASTER_NSSNOC_NSSCC, SLAVE_NSSNOC_NSSCC, GCC_NSSNOC_NSSCC_CLK },
3254
+
{ MASTER_NSSNOC_SNOC_0, SLAVE_NSSNOC_SNOC_0, GCC_NSSNOC_SNOC_CLK },
3255
+
{ MASTER_NSSNOC_SNOC_1, SLAVE_NSSNOC_SNOC_1, GCC_NSSNOC_SNOC_1_CLK },
3256
+
{ MASTER_NSSNOC_PCNOC_1, SLAVE_NSSNOC_PCNOC_1, GCC_NSSNOC_PCNOC_1_CLK },
3257
+
{ MASTER_NSSNOC_QOSGEN_REF, SLAVE_NSSNOC_QOSGEN_REF, GCC_NSSNOC_QOSGEN_REF_CLK },
3258
+
{ MASTER_NSSNOC_TIMEOUT_REF, SLAVE_NSSNOC_TIMEOUT_REF, GCC_NSSNOC_TIMEOUT_REF_CLK },
3259
+
{ MASTER_NSSNOC_XO_DCD, SLAVE_NSSNOC_XO_DCD, GCC_NSSNOC_XO_DCD_CLK },
3260
+
{ MASTER_NSSNOC_ATB, SLAVE_NSSNOC_ATB, GCC_NSSNOC_ATB_CLK },
3261
+
{ MASTER_CNOC_LPASS_CFG, SLAVE_CNOC_LPASS_CFG, GCC_CNOC_LPASS_CFG_CLK },
3262
+
{ MASTER_SNOC_LPASS, SLAVE_SNOC_LPASS, GCC_SNOC_LPASS_CLK },
3268
3263
};
3269
3264
3270
3265
static const struct of_device_id gcc_ipq5424_match_table[] = {
···
3309
3284
.num_clk_hws = ARRAY_SIZE(gcc_ipq5424_hws),
3310
3285
.icc_hws = icc_ipq5424_hws,
3311
3286
.num_icc_hws = ARRAY_SIZE(icc_ipq5424_hws),
3287
+
.icc_first_node_id = IPQ_APPS_ID,
3312
3288
};
3313
3289
3314
3290
static int gcc_ipq5424_probe(struct platform_device *pdev)
+3
-3
drivers/clk/qcom/gcc-qcs615.c
+3
-3
drivers/clk/qcom/gcc-qcs615.c
···
784
784
.name = "gcc_sdcc1_apps_clk_src",
785
785
.parent_data = gcc_parent_data_1,
786
786
.num_parents = ARRAY_SIZE(gcc_parent_data_1),
787
-
.ops = &clk_rcg2_floor_ops,
787
+
.ops = &clk_rcg2_shared_floor_ops,
788
788
},
789
789
};
790
790
···
806
806
.name = "gcc_sdcc1_ice_core_clk_src",
807
807
.parent_data = gcc_parent_data_0,
808
808
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
809
-
.ops = &clk_rcg2_floor_ops,
809
+
.ops = &clk_rcg2_shared_floor_ops,
810
810
},
811
811
};
812
812
···
830
830
.name = "gcc_sdcc2_apps_clk_src",
831
831
.parent_data = gcc_parent_data_8,
832
832
.num_parents = ARRAY_SIZE(gcc_parent_data_8),
833
-
.ops = &clk_rcg2_floor_ops,
833
+
.ops = &clk_rcg2_shared_floor_ops,
834
834
},
835
835
};
836
836
-1
drivers/clk/qcom/gcc-sc8280xp.c
-1
drivers/clk/qcom/gcc-sc8280xp.c
+1
drivers/clk/qcom/gcc-sm8750.c
+1
drivers/clk/qcom/gcc-sm8750.c
···
1012
1012
static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
1013
1013
F(400000, P_BI_TCXO, 12, 1, 4),
1014
1014
F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
1015
+
F(37500000, P_GCC_GPLL0_OUT_EVEN, 8, 0, 0),
1015
1016
F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
1016
1017
F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
1017
1018
F(202000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
+681
-18
drivers/clk/qcom/gcc-x1e80100.c
+681
-18
drivers/clk/qcom/gcc-x1e80100.c
···
32
32
DT_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE,
33
33
DT_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE,
34
34
DT_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE,
35
+
DT_GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC,
36
+
DT_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC,
37
+
DT_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC,
38
+
DT_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC,
39
+
DT_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC,
40
+
DT_GCC_USB4_1_PHY_DP0_GMUX_CLK_SRC,
41
+
DT_GCC_USB4_1_PHY_DP1_GMUX_CLK_SRC,
42
+
DT_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC,
43
+
DT_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC,
44
+
DT_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC,
45
+
DT_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC,
46
+
DT_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC,
47
+
DT_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC,
48
+
DT_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC,
49
+
DT_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC,
50
+
DT_QUSB4PHY_0_GCC_USB4_RX0_CLK,
51
+
DT_QUSB4PHY_0_GCC_USB4_RX1_CLK,
52
+
DT_QUSB4PHY_1_GCC_USB4_RX0_CLK,
53
+
DT_QUSB4PHY_1_GCC_USB4_RX1_CLK,
54
+
DT_QUSB4PHY_2_GCC_USB4_RX0_CLK,
55
+
DT_QUSB4PHY_2_GCC_USB4_RX1_CLK,
56
+
DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK,
57
+
DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
58
+
DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK,
59
+
DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
60
+
DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK,
61
+
DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
35
62
};
36
63
37
64
enum {
···
69
42
P_GCC_GPLL7_OUT_MAIN,
70
43
P_GCC_GPLL8_OUT_MAIN,
71
44
P_GCC_GPLL9_OUT_MAIN,
45
+
P_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC,
46
+
P_GCC_USB3_SEC_PHY_PIPE_CLK_SRC,
47
+
P_GCC_USB3_TERT_PHY_PIPE_CLK_SRC,
48
+
P_GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC,
49
+
P_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC,
50
+
P_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC,
51
+
P_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC,
52
+
P_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC,
53
+
P_GCC_USB4_1_PHY_DP0_GMUX_CLK_SRC,
54
+
P_GCC_USB4_1_PHY_DP1_GMUX_CLK_SRC,
55
+
P_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC,
56
+
P_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC,
57
+
P_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC,
58
+
P_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC,
59
+
P_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC,
60
+
P_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC,
61
+
P_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC,
62
+
P_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC,
63
+
P_QUSB4PHY_0_GCC_USB4_RX0_CLK,
64
+
P_QUSB4PHY_0_GCC_USB4_RX1_CLK,
65
+
P_QUSB4PHY_1_GCC_USB4_RX0_CLK,
66
+
P_QUSB4PHY_1_GCC_USB4_RX1_CLK,
67
+
P_QUSB4PHY_2_GCC_USB4_RX0_CLK,
68
+
P_QUSB4PHY_2_GCC_USB4_RX1_CLK,
72
69
P_SLEEP_CLK,
73
70
P_USB3_PHY_0_WRAPPER_GCC_USB30_PIPE_CLK,
74
71
P_USB3_PHY_1_WRAPPER_GCC_USB30_PIPE_CLK,
75
72
P_USB3_PHY_2_WRAPPER_GCC_USB30_PIPE_CLK,
73
+
P_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK,
74
+
P_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
75
+
P_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK,
76
+
P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
77
+
P_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK,
78
+
P_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK,
76
79
};
77
80
78
81
static struct clk_alpha_pll gcc_gpll0 = {
···
375
318
F(100000000, P_GCC_GPLL0_OUT_MAIN, 6, 0, 0),
376
319
F(200000000, P_GCC_GPLL0_OUT_MAIN, 3, 0, 0),
377
320
{ }
321
+
};
322
+
323
+
static const struct clk_parent_data gcc_parent_data_13[] = {
324
+
{ .index = DT_GCC_USB4_0_PHY_DP0_GMUX_CLK_SRC },
325
+
{ .index = DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
326
+
};
327
+
328
+
static const struct clk_parent_data gcc_parent_data_14[] = {
329
+
{ .index = DT_GCC_USB4_0_PHY_DP1_GMUX_CLK_SRC },
330
+
{ .index = DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
331
+
};
332
+
333
+
static const struct clk_parent_data gcc_parent_data_15[] = {
334
+
{ .index = DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK },
335
+
{ .index = DT_BI_TCXO },
336
+
};
337
+
338
+
static const struct clk_parent_data gcc_parent_data_16[] = {
339
+
{ .index = DT_GCC_USB4_0_PHY_PCIE_PIPEGMUX_CLK_SRC },
340
+
{ .index = DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK },
341
+
};
342
+
343
+
static const struct clk_parent_data gcc_parent_data_17[] = {
344
+
{ .index = DT_QUSB4PHY_0_GCC_USB4_RX0_CLK },
345
+
{ .index = DT_BI_TCXO },
346
+
};
347
+
348
+
static const struct clk_parent_data gcc_parent_data_18[] = {
349
+
{ .index = DT_QUSB4PHY_0_GCC_USB4_RX1_CLK },
350
+
{ .index = DT_BI_TCXO },
351
+
};
352
+
353
+
static const struct clk_parent_data gcc_parent_data_19[] = {
354
+
{ .index = DT_GCC_USB4_0_PHY_SYS_PIPEGMUX_CLK_SRC },
355
+
{ .index = DT_USB4_0_PHY_GCC_USB4_PCIE_PIPE_CLK },
356
+
};
357
+
358
+
static const struct clk_parent_data gcc_parent_data_20[] = {
359
+
{ .index = DT_GCC_USB4_1_PHY_DP0_GMUX_CLK_SRC },
360
+
{ .index = DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
361
+
};
362
+
363
+
static const struct clk_parent_data gcc_parent_data_21[] = {
364
+
{ .index = DT_GCC_USB4_1_PHY_DP1_GMUX_CLK_SRC },
365
+
{ .index = DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
366
+
};
367
+
368
+
static const struct clk_parent_data gcc_parent_data_22[] = {
369
+
{ .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK },
370
+
{ .index = DT_BI_TCXO },
371
+
};
372
+
373
+
static const struct clk_parent_data gcc_parent_data_23[] = {
374
+
{ .index = DT_GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC },
375
+
{ .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK },
376
+
};
377
+
378
+
static const struct clk_parent_data gcc_parent_data_24[] = {
379
+
{ .index = DT_QUSB4PHY_1_GCC_USB4_RX0_CLK },
380
+
{ .index = DT_BI_TCXO },
381
+
};
382
+
383
+
static const struct clk_parent_data gcc_parent_data_25[] = {
384
+
{ .index = DT_QUSB4PHY_1_GCC_USB4_RX1_CLK },
385
+
{ .index = DT_BI_TCXO },
386
+
};
387
+
388
+
static const struct clk_parent_data gcc_parent_data_26[] = {
389
+
{ .index = DT_GCC_USB4_1_PHY_SYS_PIPEGMUX_CLK_SRC },
390
+
{ .index = DT_USB4_1_PHY_GCC_USB4_PCIE_PIPE_CLK },
391
+
};
392
+
393
+
static const struct clk_parent_data gcc_parent_data_27[] = {
394
+
{ .index = DT_GCC_USB4_2_PHY_DP0_GMUX_CLK_SRC },
395
+
{ .index = DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
396
+
};
397
+
398
+
static const struct clk_parent_data gcc_parent_data_28[] = {
399
+
{ .index = DT_GCC_USB4_2_PHY_DP1_GMUX_CLK_SRC },
400
+
{ .index = DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
401
+
};
402
+
403
+
static const struct clk_parent_data gcc_parent_data_29[] = {
404
+
{ .index = DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK },
405
+
{ .index = DT_BI_TCXO },
406
+
};
407
+
408
+
static const struct clk_parent_data gcc_parent_data_30[] = {
409
+
{ .index = DT_GCC_USB4_2_PHY_PCIE_PIPEGMUX_CLK_SRC },
410
+
{ .index = DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK },
411
+
};
412
+
413
+
static const struct clk_parent_data gcc_parent_data_31[] = {
414
+
{ .index = DT_QUSB4PHY_2_GCC_USB4_RX0_CLK },
415
+
{ .index = DT_BI_TCXO },
416
+
};
417
+
418
+
static const struct clk_parent_data gcc_parent_data_32[] = {
419
+
{ .index = DT_QUSB4PHY_2_GCC_USB4_RX1_CLK },
420
+
{ .index = DT_BI_TCXO },
421
+
};
422
+
423
+
static const struct clk_parent_data gcc_parent_data_33[] = {
424
+
{ .index = DT_GCC_USB4_2_PHY_SYS_PIPEGMUX_CLK_SRC },
425
+
{ .index = DT_USB4_2_PHY_GCC_USB4_PCIE_PIPE_CLK },
426
+
};
427
+
428
+
static struct clk_regmap_phy_mux gcc_usb4_0_phy_dp0_clk_src = {
429
+
.reg = 0x9f06c,
430
+
.clkr = {
431
+
.hw.init = &(const struct clk_init_data) {
432
+
.name = "gcc_usb4_0_phy_dp0_clk_src",
433
+
.parent_data = gcc_parent_data_13,
434
+
.ops = &clk_regmap_phy_mux_ops,
435
+
},
436
+
},
437
+
};
438
+
439
+
static struct clk_regmap_phy_mux gcc_usb4_0_phy_dp1_clk_src = {
440
+
.reg = 0x9f114,
441
+
.clkr = {
442
+
.hw.init = &(const struct clk_init_data) {
443
+
.name = "gcc_usb4_0_phy_dp1_clk_src",
444
+
.parent_data = gcc_parent_data_14,
445
+
.ops = &clk_regmap_phy_mux_ops,
446
+
},
447
+
},
448
+
};
449
+
450
+
static struct clk_regmap_phy_mux gcc_usb4_0_phy_p2rr2p_pipe_clk_src = {
451
+
.reg = 0x9f0d4,
452
+
.clkr = {
453
+
.hw.init = &(const struct clk_init_data) {
454
+
.name = "gcc_usb4_0_phy_p2rr2p_pipe_clk_src",
455
+
.parent_data = gcc_parent_data_15,
456
+
.ops = &clk_regmap_phy_mux_ops,
457
+
},
458
+
},
459
+
};
460
+
461
+
static struct clk_regmap_phy_mux gcc_usb4_0_phy_pcie_pipe_mux_clk_src = {
462
+
.reg = 0x9f104,
463
+
.clkr = {
464
+
.hw.init = &(const struct clk_init_data) {
465
+
.name = "gcc_usb4_0_phy_pcie_pipe_mux_clk_src",
466
+
.parent_data = gcc_parent_data_16,
467
+
.ops = &clk_regmap_phy_mux_ops,
468
+
},
469
+
},
470
+
};
471
+
472
+
static struct clk_regmap_phy_mux gcc_usb4_0_phy_rx0_clk_src = {
473
+
.reg = 0x9f0ac,
474
+
.clkr = {
475
+
.hw.init = &(const struct clk_init_data) {
476
+
.name = "gcc_usb4_0_phy_rx0_clk_src",
477
+
.parent_data = gcc_parent_data_17,
478
+
.ops = &clk_regmap_phy_mux_ops,
479
+
},
480
+
},
481
+
};
482
+
483
+
static struct clk_regmap_phy_mux gcc_usb4_0_phy_rx1_clk_src = {
484
+
.reg = 0x9f0bc,
485
+
.clkr = {
486
+
.hw.init = &(const struct clk_init_data) {
487
+
.name = "gcc_usb4_0_phy_rx1_clk_src",
488
+
.parent_data = gcc_parent_data_18,
489
+
.ops = &clk_regmap_phy_mux_ops,
490
+
},
491
+
},
492
+
};
493
+
494
+
static struct clk_regmap_phy_mux gcc_usb4_0_phy_sys_clk_src = {
495
+
.reg = 0x9f0e4,
496
+
.clkr = {
497
+
.hw.init = &(const struct clk_init_data) {
498
+
.name = "gcc_usb4_0_phy_sys_clk_src",
499
+
.parent_data = gcc_parent_data_19,
500
+
.ops = &clk_regmap_phy_mux_ops,
501
+
},
502
+
},
503
+
};
504
+
505
+
static struct clk_regmap_phy_mux gcc_usb4_1_phy_dp0_clk_src = {
506
+
.reg = 0x2b06c,
507
+
.clkr = {
508
+
.hw.init = &(const struct clk_init_data) {
509
+
.name = "gcc_usb4_1_phy_dp0_clk_src",
510
+
.parent_data = gcc_parent_data_20,
511
+
.ops = &clk_regmap_phy_mux_ops,
512
+
},
513
+
},
514
+
};
515
+
516
+
static struct clk_regmap_phy_mux gcc_usb4_1_phy_dp1_clk_src = {
517
+
.reg = 0x2b114,
518
+
.clkr = {
519
+
.hw.init = &(const struct clk_init_data) {
520
+
.name = "gcc_usb4_1_phy_dp1_clk_src",
521
+
.parent_data = gcc_parent_data_21,
522
+
.ops = &clk_regmap_phy_mux_ops,
523
+
},
524
+
},
525
+
};
526
+
527
+
static struct clk_regmap_phy_mux gcc_usb4_1_phy_p2rr2p_pipe_clk_src = {
528
+
.reg = 0x2b0d4,
529
+
.clkr = {
530
+
.hw.init = &(const struct clk_init_data) {
531
+
.name = "gcc_usb4_1_phy_p2rr2p_pipe_clk_src",
532
+
.parent_data = gcc_parent_data_22,
533
+
.ops = &clk_regmap_phy_mux_ops,
534
+
},
535
+
},
536
+
};
537
+
538
+
static struct clk_regmap_phy_mux gcc_usb4_1_phy_pcie_pipe_mux_clk_src = {
539
+
.reg = 0x2b104,
540
+
.clkr = {
541
+
.hw.init = &(const struct clk_init_data) {
542
+
.name = "gcc_usb4_1_phy_pcie_pipe_mux_clk_src",
543
+
.parent_data = gcc_parent_data_23,
544
+
.ops = &clk_regmap_phy_mux_ops,
545
+
},
546
+
},
547
+
};
548
+
549
+
static struct clk_regmap_phy_mux gcc_usb4_1_phy_rx0_clk_src = {
550
+
.reg = 0x2b0ac,
551
+
.clkr = {
552
+
.hw.init = &(const struct clk_init_data) {
553
+
.name = "gcc_usb4_1_phy_rx0_clk_src",
554
+
.parent_data = gcc_parent_data_24,
555
+
.ops = &clk_regmap_phy_mux_ops,
556
+
},
557
+
},
558
+
};
559
+
560
+
static struct clk_regmap_phy_mux gcc_usb4_1_phy_rx1_clk_src = {
561
+
.reg = 0x2b0bc,
562
+
.clkr = {
563
+
.hw.init = &(const struct clk_init_data) {
564
+
.name = "gcc_usb4_1_phy_rx1_clk_src",
565
+
.parent_data = gcc_parent_data_25,
566
+
.ops = &clk_regmap_phy_mux_ops,
567
+
},
568
+
},
569
+
};
570
+
571
+
static struct clk_regmap_phy_mux gcc_usb4_1_phy_sys_clk_src = {
572
+
.reg = 0x2b0e4,
573
+
.clkr = {
574
+
.hw.init = &(const struct clk_init_data) {
575
+
.name = "gcc_usb4_1_phy_sys_clk_src",
576
+
.parent_data = gcc_parent_data_26,
577
+
.ops = &clk_regmap_phy_mux_ops,
578
+
},
579
+
},
580
+
};
581
+
582
+
static struct clk_regmap_phy_mux gcc_usb4_2_phy_dp0_clk_src = {
583
+
.reg = 0x1106c,
584
+
.clkr = {
585
+
.hw.init = &(const struct clk_init_data) {
586
+
.name = "gcc_usb4_2_phy_dp0_clk_src",
587
+
.parent_data = gcc_parent_data_27,
588
+
.ops = &clk_regmap_phy_mux_ops,
589
+
},
590
+
},
591
+
};
592
+
593
+
static struct clk_regmap_phy_mux gcc_usb4_2_phy_dp1_clk_src = {
594
+
.reg = 0x11114,
595
+
.clkr = {
596
+
.hw.init = &(const struct clk_init_data) {
597
+
.name = "gcc_usb4_2_phy_dp1_clk_src",
598
+
.parent_data = gcc_parent_data_28,
599
+
.ops = &clk_regmap_phy_mux_ops,
600
+
},
601
+
},
602
+
};
603
+
604
+
static struct clk_regmap_phy_mux gcc_usb4_2_phy_p2rr2p_pipe_clk_src = {
605
+
.reg = 0x110d4,
606
+
.clkr = {
607
+
.hw.init = &(const struct clk_init_data) {
608
+
.name = "gcc_usb4_2_phy_p2rr2p_pipe_clk_src",
609
+
.parent_data = gcc_parent_data_29,
610
+
.ops = &clk_regmap_phy_mux_ops,
611
+
},
612
+
},
613
+
};
614
+
615
+
static struct clk_regmap_phy_mux gcc_usb4_2_phy_pcie_pipe_mux_clk_src = {
616
+
.reg = 0x11104,
617
+
.clkr = {
618
+
.hw.init = &(const struct clk_init_data) {
619
+
.name = "gcc_usb4_2_phy_pcie_pipe_mux_clk_src",
620
+
.parent_data = gcc_parent_data_30,
621
+
.ops = &clk_regmap_phy_mux_ops,
622
+
},
623
+
},
624
+
};
625
+
626
+
static struct clk_regmap_phy_mux gcc_usb4_2_phy_rx0_clk_src = {
627
+
.reg = 0x110ac,
628
+
.clkr = {
629
+
.hw.init = &(const struct clk_init_data) {
630
+
.name = "gcc_usb4_2_phy_rx0_clk_src",
631
+
.parent_data = gcc_parent_data_31,
632
+
.ops = &clk_regmap_phy_mux_ops,
633
+
},
634
+
},
635
+
};
636
+
637
+
static struct clk_regmap_phy_mux gcc_usb4_2_phy_rx1_clk_src = {
638
+
.reg = 0x110bc,
639
+
.clkr = {
640
+
.hw.init = &(const struct clk_init_data) {
641
+
.name = "gcc_usb4_2_phy_rx1_clk_src",
642
+
.parent_data = gcc_parent_data_32,
643
+
.ops = &clk_regmap_phy_mux_ops,
644
+
},
645
+
},
646
+
};
647
+
648
+
static struct clk_regmap_phy_mux gcc_usb4_2_phy_sys_clk_src = {
649
+
.reg = 0x110e4,
650
+
.clkr = {
651
+
.hw.init = &(const struct clk_init_data) {
652
+
.name = "gcc_usb4_2_phy_sys_clk_src",
653
+
.parent_data = gcc_parent_data_33,
654
+
.ops = &clk_regmap_phy_mux_ops,
655
+
},
656
+
},
378
657
};
379
658
380
659
static struct clk_rcg2 gcc_gp1_clk_src = {
···
1849
1456
};
1850
1457
1851
1458
static const struct freq_tbl ftbl_gcc_usb4_0_master_clk_src[] = {
1852
-
F(85714286, P_GCC_GPLL0_OUT_EVEN, 3.5, 0, 0),
1853
1459
F(175000000, P_GCC_GPLL8_OUT_MAIN, 4, 0, 0),
1854
1460
F(350000000, P_GCC_GPLL8_OUT_MAIN, 2, 0, 0),
1855
1461
{ }
···
3182
2790
.enable_mask = BIT(25),
3183
2791
.hw.init = &(const struct clk_init_data) {
3184
2792
.name = "gcc_pcie_0_pipe_clk",
2793
+
.parent_hws = (const struct clk_hw*[]) {
2794
+
&gcc_usb4_0_phy_pcie_pipe_mux_clk_src.clkr.hw,
2795
+
},
2796
+
.num_parents = 1,
2797
+
.flags = CLK_SET_RATE_PARENT,
3185
2798
.ops = &clk_branch2_ops,
3186
2799
},
3187
2800
},
···
3276
2879
.enable_mask = BIT(30),
3277
2880
.hw.init = &(const struct clk_init_data) {
3278
2881
.name = "gcc_pcie_1_pipe_clk",
2882
+
.parent_hws = (const struct clk_hw*[]) {
2883
+
&gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr.hw,
2884
+
},
2885
+
.num_parents = 1,
2886
+
.flags = CLK_SET_RATE_PARENT,
3279
2887
.ops = &clk_branch2_ops,
3280
2888
},
3281
2889
},
···
3370
2968
.enable_mask = BIT(23),
3371
2969
.hw.init = &(const struct clk_init_data) {
3372
2970
.name = "gcc_pcie_2_pipe_clk",
2971
+
.parent_hws = (const struct clk_hw*[]) {
2972
+
&gcc_usb4_2_phy_pcie_pipe_mux_clk_src.clkr.hw,
2973
+
},
2974
+
.num_parents = 1,
2975
+
.flags = CLK_SET_RATE_PARENT,
3373
2976
.ops = &clk_branch2_ops,
3374
2977
},
3375
2978
},
···
5563
5156
},
5564
5157
};
5565
5158
5159
+
static const struct parent_map gcc_parent_map_34[] = {
5160
+
{ P_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC, 0 },
5161
+
{ P_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 },
5162
+
{ P_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC, 3 },
5163
+
};
5164
+
5165
+
static const struct clk_parent_data gcc_parent_data_34[] = {
5166
+
{ .hw = &gcc_usb3_prim_phy_pipe_clk_src.clkr.hw },
5167
+
{ .index = DT_USB4_0_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
5168
+
{ .index = DT_GCC_USB4_0_PHY_PIPEGMUX_CLK_SRC },
5169
+
};
5170
+
5171
+
static struct clk_regmap_mux gcc_usb34_prim_phy_pipe_clk_src = {
5172
+
.reg = 0x39070,
5173
+
.shift = 0,
5174
+
.width = 2,
5175
+
.parent_map = gcc_parent_map_34,
5176
+
.clkr = {
5177
+
.hw.init = &(const struct clk_init_data) {
5178
+
.name = "gcc_usb34_prim_phy_pipe_clk_src",
5179
+
.parent_data = gcc_parent_data_34,
5180
+
.num_parents = ARRAY_SIZE(gcc_parent_data_34),
5181
+
.ops = &clk_regmap_mux_closest_ops,
5182
+
},
5183
+
},
5184
+
};
5185
+
5566
5186
static struct clk_branch gcc_usb3_prim_phy_pipe_clk = {
5567
5187
.halt_reg = 0x39068,
5568
5188
.halt_check = BRANCH_HALT_SKIP,
···
5601
5167
.hw.init = &(const struct clk_init_data) {
5602
5168
.name = "gcc_usb3_prim_phy_pipe_clk",
5603
5169
.parent_hws = (const struct clk_hw*[]) {
5604
-
&gcc_usb3_prim_phy_pipe_clk_src.clkr.hw,
5170
+
&gcc_usb34_prim_phy_pipe_clk_src.clkr.hw,
5605
5171
},
5606
5172
.num_parents = 1,
5607
5173
.flags = CLK_SET_RATE_PARENT,
···
5661
5227
},
5662
5228
};
5663
5229
5230
+
static const struct parent_map gcc_parent_map_35[] = {
5231
+
{ P_GCC_USB3_SEC_PHY_PIPE_CLK_SRC, 0 },
5232
+
{ P_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 },
5233
+
{ P_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC, 3 },
5234
+
};
5235
+
5236
+
static const struct clk_parent_data gcc_parent_data_35[] = {
5237
+
{ .hw = &gcc_usb3_sec_phy_pipe_clk_src.clkr.hw },
5238
+
{ .index = DT_USB4_1_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
5239
+
{ .index = DT_GCC_USB4_1_PHY_PIPEGMUX_CLK_SRC },
5240
+
};
5241
+
5242
+
static struct clk_regmap_mux gcc_usb34_sec_phy_pipe_clk_src = {
5243
+
.reg = 0xa1070,
5244
+
.shift = 0,
5245
+
.width = 2,
5246
+
.parent_map = gcc_parent_map_35,
5247
+
.clkr = {
5248
+
.hw.init = &(const struct clk_init_data) {
5249
+
.name = "gcc_usb34_sec_phy_pipe_clk_src",
5250
+
.parent_data = gcc_parent_data_35,
5251
+
.num_parents = ARRAY_SIZE(gcc_parent_data_35),
5252
+
.ops = &clk_regmap_mux_closest_ops,
5253
+
},
5254
+
},
5255
+
};
5256
+
5664
5257
static struct clk_branch gcc_usb3_sec_phy_pipe_clk = {
5665
5258
.halt_reg = 0xa1068,
5666
5259
.halt_check = BRANCH_HALT_SKIP,
···
5699
5238
.hw.init = &(const struct clk_init_data) {
5700
5239
.name = "gcc_usb3_sec_phy_pipe_clk",
5701
5240
.parent_hws = (const struct clk_hw*[]) {
5702
-
&gcc_usb3_sec_phy_pipe_clk_src.clkr.hw,
5241
+
&gcc_usb34_sec_phy_pipe_clk_src.clkr.hw,
5703
5242
},
5704
5243
.num_parents = 1,
5705
5244
.flags = CLK_SET_RATE_PARENT,
···
5759
5298
},
5760
5299
};
5761
5300
5301
+
static const struct parent_map gcc_parent_map_36[] = {
5302
+
{ P_GCC_USB3_TERT_PHY_PIPE_CLK_SRC, 0 },
5303
+
{ P_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK, 1 },
5304
+
{ P_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC, 3 },
5305
+
};
5306
+
5307
+
static const struct clk_parent_data gcc_parent_data_36[] = {
5308
+
{ .hw = &gcc_usb3_tert_phy_pipe_clk_src.clkr.hw },
5309
+
{ .index = DT_USB4_2_PHY_GCC_USB4RTR_MAX_PIPE_CLK },
5310
+
{ .index = DT_GCC_USB4_2_PHY_PIPEGMUX_CLK_SRC },
5311
+
};
5312
+
5313
+
static struct clk_regmap_mux gcc_usb34_tert_phy_pipe_clk_src = {
5314
+
.reg = 0xa2070,
5315
+
.shift = 0,
5316
+
.width = 2,
5317
+
.parent_map = gcc_parent_map_36,
5318
+
.clkr = {
5319
+
.hw.init = &(const struct clk_init_data) {
5320
+
.name = "gcc_usb34_tert_phy_pipe_clk_src",
5321
+
.parent_data = gcc_parent_data_36,
5322
+
.num_parents = ARRAY_SIZE(gcc_parent_data_36),
5323
+
.ops = &clk_regmap_mux_closest_ops,
5324
+
},
5325
+
},
5326
+
};
5327
+
5762
5328
static struct clk_branch gcc_usb3_tert_phy_pipe_clk = {
5763
5329
.halt_reg = 0xa2068,
5764
5330
.halt_check = BRANCH_HALT_SKIP,
···
5797
5309
.hw.init = &(const struct clk_init_data) {
5798
5310
.name = "gcc_usb3_tert_phy_pipe_clk",
5799
5311
.parent_hws = (const struct clk_hw*[]) {
5800
-
&gcc_usb3_tert_phy_pipe_clk_src.clkr.hw,
5312
+
&gcc_usb34_tert_phy_pipe_clk_src.clkr.hw,
5801
5313
},
5802
5314
.num_parents = 1,
5803
5315
.flags = CLK_SET_RATE_PARENT,
···
5823
5335
5824
5336
static struct clk_branch gcc_usb4_0_dp0_clk = {
5825
5337
.halt_reg = 0x9f060,
5826
-
.halt_check = BRANCH_HALT,
5338
+
.halt_check = BRANCH_HALT_SKIP,
5827
5339
.clkr = {
5828
5340
.enable_reg = 0x9f060,
5829
5341
.enable_mask = BIT(0),
5830
5342
.hw.init = &(const struct clk_init_data) {
5831
5343
.name = "gcc_usb4_0_dp0_clk",
5344
+
.parent_hws = (const struct clk_hw*[]) {
5345
+
&gcc_usb4_0_phy_dp0_clk_src.clkr.hw,
5346
+
},
5347
+
.num_parents = 1,
5348
+
.flags = CLK_SET_RATE_PARENT,
5832
5349
.ops = &clk_branch2_ops,
5833
5350
},
5834
5351
},
···
5841
5348
5842
5349
static struct clk_branch gcc_usb4_0_dp1_clk = {
5843
5350
.halt_reg = 0x9f108,
5844
-
.halt_check = BRANCH_HALT,
5351
+
.halt_check = BRANCH_HALT_SKIP,
5845
5352
.clkr = {
5846
5353
.enable_reg = 0x9f108,
5847
5354
.enable_mask = BIT(0),
5848
5355
.hw.init = &(const struct clk_init_data) {
5849
5356
.name = "gcc_usb4_0_dp1_clk",
5357
+
.parent_hws = (const struct clk_hw*[]) {
5358
+
&gcc_usb4_0_phy_dp1_clk_src.clkr.hw,
5359
+
},
5360
+
.num_parents = 1,
5361
+
.flags = CLK_SET_RATE_PARENT,
5850
5362
.ops = &clk_branch2_ops,
5851
5363
},
5852
5364
},
···
5883
5385
.enable_mask = BIT(0),
5884
5386
.hw.init = &(const struct clk_init_data) {
5885
5387
.name = "gcc_usb4_0_phy_p2rr2p_pipe_clk",
5388
+
.parent_hws = (const struct clk_hw*[]) {
5389
+
&gcc_usb4_0_phy_p2rr2p_pipe_clk_src.clkr.hw,
5390
+
},
5391
+
.num_parents = 1,
5392
+
.flags = CLK_SET_RATE_PARENT,
5886
5393
.ops = &clk_branch2_ops,
5887
5394
},
5888
5395
},
···
5901
5398
.enable_mask = BIT(19),
5902
5399
.hw.init = &(const struct clk_init_data) {
5903
5400
.name = "gcc_usb4_0_phy_pcie_pipe_clk",
5401
+
.parent_hws = (const struct clk_hw*[]) {
5402
+
&gcc_usb4_0_phy_pcie_pipe_mux_clk_src.clkr.hw,
5403
+
},
5404
+
.num_parents = 1,
5405
+
.flags = CLK_SET_RATE_PARENT,
5904
5406
.ops = &clk_branch2_ops,
5905
5407
},
5906
5408
},
···
5913
5405
5914
5406
static struct clk_branch gcc_usb4_0_phy_rx0_clk = {
5915
5407
.halt_reg = 0x9f0b0,
5916
-
.halt_check = BRANCH_HALT,
5408
+
.halt_check = BRANCH_HALT_SKIP,
5917
5409
.clkr = {
5918
5410
.enable_reg = 0x9f0b0,
5919
5411
.enable_mask = BIT(0),
5920
5412
.hw.init = &(const struct clk_init_data) {
5921
5413
.name = "gcc_usb4_0_phy_rx0_clk",
5414
+
.parent_hws = (const struct clk_hw*[]) {
5415
+
&gcc_usb4_0_phy_rx0_clk_src.clkr.hw,
5416
+
},
5417
+
.num_parents = 1,
5418
+
.flags = CLK_SET_RATE_PARENT,
5922
5419
.ops = &clk_branch2_ops,
5923
5420
},
5924
5421
},
···
5931
5418
5932
5419
static struct clk_branch gcc_usb4_0_phy_rx1_clk = {
5933
5420
.halt_reg = 0x9f0c0,
5934
-
.halt_check = BRANCH_HALT,
5421
+
.halt_check = BRANCH_HALT_SKIP,
5935
5422
.clkr = {
5936
5423
.enable_reg = 0x9f0c0,
5937
5424
.enable_mask = BIT(0),
5938
5425
.hw.init = &(const struct clk_init_data) {
5939
5426
.name = "gcc_usb4_0_phy_rx1_clk",
5427
+
.parent_hws = (const struct clk_hw*[]) {
5428
+
&gcc_usb4_0_phy_rx1_clk_src.clkr.hw,
5429
+
},
5430
+
.num_parents = 1,
5431
+
.flags = CLK_SET_RATE_PARENT,
5940
5432
.ops = &clk_branch2_ops,
5941
5433
},
5942
5434
},
···
5957
5439
.enable_mask = BIT(0),
5958
5440
.hw.init = &(const struct clk_init_data) {
5959
5441
.name = "gcc_usb4_0_phy_usb_pipe_clk",
5442
+
.parent_hws = (const struct clk_hw*[]) {
5443
+
&gcc_usb34_prim_phy_pipe_clk_src.clkr.hw,
5444
+
},
5445
+
.num_parents = 1,
5446
+
.flags = CLK_SET_RATE_PARENT,
5960
5447
.ops = &clk_branch2_ops,
5961
5448
},
5962
5449
},
···
5993
5470
.enable_mask = BIT(0),
5994
5471
.hw.init = &(const struct clk_init_data) {
5995
5472
.name = "gcc_usb4_0_sys_clk",
5473
+
.parent_hws = (const struct clk_hw*[]) {
5474
+
&gcc_usb4_0_phy_sys_clk_src.clkr.hw,
5475
+
},
5476
+
.num_parents = 1,
5477
+
.flags = CLK_SET_RATE_PARENT,
5996
5478
.ops = &clk_branch2_ops,
5997
5479
},
5998
5480
},
···
6040
5512
6041
5513
static struct clk_branch gcc_usb4_1_dp0_clk = {
6042
5514
.halt_reg = 0x2b060,
6043
-
.halt_check = BRANCH_HALT,
5515
+
.halt_check = BRANCH_HALT_SKIP,
6044
5516
.clkr = {
6045
5517
.enable_reg = 0x2b060,
6046
5518
.enable_mask = BIT(0),
6047
5519
.hw.init = &(const struct clk_init_data) {
6048
5520
.name = "gcc_usb4_1_dp0_clk",
5521
+
.parent_hws = (const struct clk_hw*[]) {
5522
+
&gcc_usb4_1_phy_dp0_clk_src.clkr.hw,
5523
+
},
5524
+
.num_parents = 1,
5525
+
.flags = CLK_SET_RATE_PARENT,
6049
5526
.ops = &clk_branch2_ops,
6050
5527
},
6051
5528
},
···
6058
5525
6059
5526
static struct clk_branch gcc_usb4_1_dp1_clk = {
6060
5527
.halt_reg = 0x2b108,
6061
-
.halt_check = BRANCH_HALT,
5528
+
.halt_check = BRANCH_HALT_SKIP,
6062
5529
.clkr = {
6063
5530
.enable_reg = 0x2b108,
6064
5531
.enable_mask = BIT(0),
6065
5532
.hw.init = &(const struct clk_init_data) {
6066
5533
.name = "gcc_usb4_1_dp1_clk",
5534
+
.parent_hws = (const struct clk_hw*[]) {
5535
+
&gcc_usb4_1_phy_dp1_clk_src.clkr.hw,
5536
+
},
5537
+
.num_parents = 1,
5538
+
.flags = CLK_SET_RATE_PARENT,
6067
5539
.ops = &clk_branch2_ops,
6068
5540
},
6069
5541
},
···
6100
5562
.enable_mask = BIT(0),
6101
5563
.hw.init = &(const struct clk_init_data) {
6102
5564
.name = "gcc_usb4_1_phy_p2rr2p_pipe_clk",
5565
+
.parent_hws = (const struct clk_hw*[]) {
5566
+
&gcc_usb4_1_phy_p2rr2p_pipe_clk_src.clkr.hw,
5567
+
},
5568
+
.num_parents = 1,
5569
+
.flags = CLK_SET_RATE_PARENT,
6103
5570
.ops = &clk_branch2_ops,
6104
5571
},
6105
5572
},
···
6118
5575
.enable_mask = BIT(0),
6119
5576
.hw.init = &(const struct clk_init_data) {
6120
5577
.name = "gcc_usb4_1_phy_pcie_pipe_clk",
5578
+
.parent_hws = (const struct clk_hw*[]) {
5579
+
&gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr.hw,
5580
+
},
5581
+
.num_parents = 1,
5582
+
.flags = CLK_SET_RATE_PARENT,
6121
5583
.ops = &clk_branch2_ops,
6122
5584
},
6123
5585
},
···
6130
5582
6131
5583
static struct clk_branch gcc_usb4_1_phy_rx0_clk = {
6132
5584
.halt_reg = 0x2b0b0,
6133
-
.halt_check = BRANCH_HALT,
5585
+
.halt_check = BRANCH_HALT_SKIP,
6134
5586
.clkr = {
6135
5587
.enable_reg = 0x2b0b0,
6136
5588
.enable_mask = BIT(0),
6137
5589
.hw.init = &(const struct clk_init_data) {
6138
5590
.name = "gcc_usb4_1_phy_rx0_clk",
5591
+
.parent_hws = (const struct clk_hw*[]) {
5592
+
&gcc_usb4_1_phy_rx0_clk_src.clkr.hw,
5593
+
},
5594
+
.num_parents = 1,
5595
+
.flags = CLK_SET_RATE_PARENT,
6139
5596
.ops = &clk_branch2_ops,
6140
5597
},
6141
5598
},
···
6148
5595
6149
5596
static struct clk_branch gcc_usb4_1_phy_rx1_clk = {
6150
5597
.halt_reg = 0x2b0c0,
6151
-
.halt_check = BRANCH_HALT,
5598
+
.halt_check = BRANCH_HALT_SKIP,
6152
5599
.clkr = {
6153
5600
.enable_reg = 0x2b0c0,
6154
5601
.enable_mask = BIT(0),
6155
5602
.hw.init = &(const struct clk_init_data) {
6156
5603
.name = "gcc_usb4_1_phy_rx1_clk",
5604
+
.parent_hws = (const struct clk_hw*[]) {
5605
+
&gcc_usb4_1_phy_rx1_clk_src.clkr.hw,
5606
+
},
5607
+
.num_parents = 1,
5608
+
.flags = CLK_SET_RATE_PARENT,
6157
5609
.ops = &clk_branch2_ops,
6158
5610
},
6159
5611
},
···
6174
5616
.enable_mask = BIT(0),
6175
5617
.hw.init = &(const struct clk_init_data) {
6176
5618
.name = "gcc_usb4_1_phy_usb_pipe_clk",
5619
+
.parent_hws = (const struct clk_hw*[]) {
5620
+
&gcc_usb34_sec_phy_pipe_clk_src.clkr.hw,
5621
+
},
5622
+
.num_parents = 1,
5623
+
.flags = CLK_SET_RATE_PARENT,
6177
5624
.ops = &clk_branch2_ops,
6178
5625
},
6179
5626
},
···
6210
5647
.enable_mask = BIT(0),
6211
5648
.hw.init = &(const struct clk_init_data) {
6212
5649
.name = "gcc_usb4_1_sys_clk",
5650
+
.parent_hws = (const struct clk_hw*[]) {
5651
+
&gcc_usb4_1_phy_sys_clk_src.clkr.hw,
5652
+
},
5653
+
.num_parents = 1,
5654
+
.flags = CLK_SET_RATE_PARENT,
6213
5655
.ops = &clk_branch2_ops,
6214
5656
},
6215
5657
},
···
6257
5689
6258
5690
static struct clk_branch gcc_usb4_2_dp0_clk = {
6259
5691
.halt_reg = 0x11060,
6260
-
.halt_check = BRANCH_HALT,
5692
+
.halt_check = BRANCH_HALT_SKIP,
6261
5693
.clkr = {
6262
5694
.enable_reg = 0x11060,
6263
5695
.enable_mask = BIT(0),
6264
5696
.hw.init = &(const struct clk_init_data) {
6265
5697
.name = "gcc_usb4_2_dp0_clk",
5698
+
.parent_hws = (const struct clk_hw*[]) {
5699
+
&gcc_usb4_2_phy_dp0_clk_src.clkr.hw,
5700
+
},
5701
+
.num_parents = 1,
5702
+
.flags = CLK_SET_RATE_PARENT,
6266
5703
.ops = &clk_branch2_ops,
6267
5704
},
6268
5705
},
···
6275
5702
6276
5703
static struct clk_branch gcc_usb4_2_dp1_clk = {
6277
5704
.halt_reg = 0x11108,
6278
-
.halt_check = BRANCH_HALT,
5705
+
.halt_check = BRANCH_HALT_SKIP,
6279
5706
.clkr = {
6280
5707
.enable_reg = 0x11108,
6281
5708
.enable_mask = BIT(0),
6282
5709
.hw.init = &(const struct clk_init_data) {
6283
5710
.name = "gcc_usb4_2_dp1_clk",
5711
+
.parent_hws = (const struct clk_hw*[]) {
5712
+
&gcc_usb4_2_phy_dp1_clk_src.clkr.hw,
5713
+
},
5714
+
.num_parents = 1,
5715
+
.flags = CLK_SET_RATE_PARENT,
6284
5716
.ops = &clk_branch2_ops,
6285
5717
},
6286
5718
},
···
6317
5739
.enable_mask = BIT(0),
6318
5740
.hw.init = &(const struct clk_init_data) {
6319
5741
.name = "gcc_usb4_2_phy_p2rr2p_pipe_clk",
5742
+
.parent_hws = (const struct clk_hw*[]) {
5743
+
&gcc_usb4_2_phy_p2rr2p_pipe_clk_src.clkr.hw,
5744
+
},
5745
+
.num_parents = 1,
5746
+
.flags = CLK_SET_RATE_PARENT,
6320
5747
.ops = &clk_branch2_ops,
6321
5748
},
6322
5749
},
···
6335
5752
.enable_mask = BIT(1),
6336
5753
.hw.init = &(const struct clk_init_data) {
6337
5754
.name = "gcc_usb4_2_phy_pcie_pipe_clk",
5755
+
.parent_hws = (const struct clk_hw*[]) {
5756
+
&gcc_usb4_2_phy_pcie_pipe_mux_clk_src.clkr.hw,
5757
+
},
5758
+
.num_parents = 1,
5759
+
.flags = CLK_SET_RATE_PARENT,
6338
5760
.ops = &clk_branch2_ops,
6339
5761
},
6340
5762
},
···
6347
5759
6348
5760
static struct clk_branch gcc_usb4_2_phy_rx0_clk = {
6349
5761
.halt_reg = 0x110b0,
6350
-
.halt_check = BRANCH_HALT,
5762
+
.halt_check = BRANCH_HALT_SKIP,
6351
5763
.clkr = {
6352
5764
.enable_reg = 0x110b0,
6353
5765
.enable_mask = BIT(0),
6354
5766
.hw.init = &(const struct clk_init_data) {
6355
5767
.name = "gcc_usb4_2_phy_rx0_clk",
5768
+
.parent_hws = (const struct clk_hw*[]) {
5769
+
&gcc_usb4_2_phy_rx0_clk_src.clkr.hw,
5770
+
},
5771
+
.num_parents = 1,
5772
+
.flags = CLK_SET_RATE_PARENT,
6356
5773
.ops = &clk_branch2_ops,
6357
5774
},
6358
5775
},
···
6365
5772
6366
5773
static struct clk_branch gcc_usb4_2_phy_rx1_clk = {
6367
5774
.halt_reg = 0x110c0,
6368
-
.halt_check = BRANCH_HALT,
5775
+
.halt_check = BRANCH_HALT_SKIP,
6369
5776
.clkr = {
6370
5777
.enable_reg = 0x110c0,
6371
5778
.enable_mask = BIT(0),
6372
5779
.hw.init = &(const struct clk_init_data) {
6373
5780
.name = "gcc_usb4_2_phy_rx1_clk",
5781
+
.parent_hws = (const struct clk_hw*[]) {
5782
+
&gcc_usb4_2_phy_rx1_clk_src.clkr.hw,
5783
+
},
5784
+
.num_parents = 1,
5785
+
.flags = CLK_SET_RATE_PARENT,
6374
5786
.ops = &clk_branch2_ops,
6375
5787
},
6376
5788
},
···
6391
5793
.enable_mask = BIT(0),
6392
5794
.hw.init = &(const struct clk_init_data) {
6393
5795
.name = "gcc_usb4_2_phy_usb_pipe_clk",
5796
+
.parent_hws = (const struct clk_hw*[]) {
5797
+
&gcc_usb34_tert_phy_pipe_clk_src.clkr.hw,
5798
+
},
5799
+
.num_parents = 1,
5800
+
.flags = CLK_SET_RATE_PARENT,
6394
5801
.ops = &clk_branch2_ops,
6395
5802
},
6396
5803
},
···
7086
6483
[GCC_USB30_TERT_MOCK_UTMI_CLK_SRC] = &gcc_usb30_tert_mock_utmi_clk_src.clkr,
7087
6484
[GCC_USB30_TERT_MOCK_UTMI_POSTDIV_CLK_SRC] = &gcc_usb30_tert_mock_utmi_postdiv_clk_src.clkr,
7088
6485
[GCC_USB30_TERT_SLEEP_CLK] = &gcc_usb30_tert_sleep_clk.clkr,
6486
+
[GCC_USB34_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb34_prim_phy_pipe_clk_src.clkr,
6487
+
[GCC_USB34_SEC_PHY_PIPE_CLK_SRC] = &gcc_usb34_sec_phy_pipe_clk_src.clkr,
6488
+
[GCC_USB34_TERT_PHY_PIPE_CLK_SRC] = &gcc_usb34_tert_phy_pipe_clk_src.clkr,
7089
6489
[GCC_USB3_MP_PHY_AUX_CLK] = &gcc_usb3_mp_phy_aux_clk.clkr,
7090
6490
[GCC_USB3_MP_PHY_AUX_CLK_SRC] = &gcc_usb3_mp_phy_aux_clk_src.clkr,
7091
6491
[GCC_USB3_MP_PHY_COM_AUX_CLK] = &gcc_usb3_mp_phy_com_aux_clk.clkr,
···
7114
6508
[GCC_USB4_0_DP1_CLK] = &gcc_usb4_0_dp1_clk.clkr,
7115
6509
[GCC_USB4_0_MASTER_CLK] = &gcc_usb4_0_master_clk.clkr,
7116
6510
[GCC_USB4_0_MASTER_CLK_SRC] = &gcc_usb4_0_master_clk_src.clkr,
6511
+
[GCC_USB4_0_PHY_DP0_CLK_SRC] = &gcc_usb4_0_phy_dp0_clk_src.clkr,
6512
+
[GCC_USB4_0_PHY_DP1_CLK_SRC] = &gcc_usb4_0_phy_dp1_clk_src.clkr,
7117
6513
[GCC_USB4_0_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_0_phy_p2rr2p_pipe_clk.clkr,
6514
+
[GCC_USB4_0_PHY_P2RR2P_PIPE_CLK_SRC] = &gcc_usb4_0_phy_p2rr2p_pipe_clk_src.clkr,
7118
6515
[GCC_USB4_0_PHY_PCIE_PIPE_CLK] = &gcc_usb4_0_phy_pcie_pipe_clk.clkr,
7119
6516
[GCC_USB4_0_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_0_phy_pcie_pipe_clk_src.clkr,
6517
+
[GCC_USB4_0_PHY_PCIE_PIPE_MUX_CLK_SRC] = &gcc_usb4_0_phy_pcie_pipe_mux_clk_src.clkr,
7120
6518
[GCC_USB4_0_PHY_RX0_CLK] = &gcc_usb4_0_phy_rx0_clk.clkr,
6519
+
[GCC_USB4_0_PHY_RX0_CLK_SRC] = &gcc_usb4_0_phy_rx0_clk_src.clkr,
7121
6520
[GCC_USB4_0_PHY_RX1_CLK] = &gcc_usb4_0_phy_rx1_clk.clkr,
6521
+
[GCC_USB4_0_PHY_RX1_CLK_SRC] = &gcc_usb4_0_phy_rx1_clk_src.clkr,
6522
+
[GCC_USB4_0_PHY_SYS_CLK_SRC] = &gcc_usb4_0_phy_sys_clk_src.clkr,
7122
6523
[GCC_USB4_0_PHY_USB_PIPE_CLK] = &gcc_usb4_0_phy_usb_pipe_clk.clkr,
7123
6524
[GCC_USB4_0_SB_IF_CLK] = &gcc_usb4_0_sb_if_clk.clkr,
7124
6525
[GCC_USB4_0_SB_IF_CLK_SRC] = &gcc_usb4_0_sb_if_clk_src.clkr,
···
7137
6524
[GCC_USB4_1_DP1_CLK] = &gcc_usb4_1_dp1_clk.clkr,
7138
6525
[GCC_USB4_1_MASTER_CLK] = &gcc_usb4_1_master_clk.clkr,
7139
6526
[GCC_USB4_1_MASTER_CLK_SRC] = &gcc_usb4_1_master_clk_src.clkr,
6527
+
[GCC_USB4_1_PHY_DP0_CLK_SRC] = &gcc_usb4_1_phy_dp0_clk_src.clkr,
6528
+
[GCC_USB4_1_PHY_DP1_CLK_SRC] = &gcc_usb4_1_phy_dp1_clk_src.clkr,
7140
6529
[GCC_USB4_1_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_1_phy_p2rr2p_pipe_clk.clkr,
6530
+
[GCC_USB4_1_PHY_P2RR2P_PIPE_CLK_SRC] = &gcc_usb4_1_phy_p2rr2p_pipe_clk_src.clkr,
7141
6531
[GCC_USB4_1_PHY_PCIE_PIPE_CLK] = &gcc_usb4_1_phy_pcie_pipe_clk.clkr,
7142
6532
[GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_1_phy_pcie_pipe_clk_src.clkr,
6533
+
[GCC_USB4_1_PHY_PCIE_PIPE_MUX_CLK_SRC] = &gcc_usb4_1_phy_pcie_pipe_mux_clk_src.clkr,
7143
6534
[GCC_USB4_1_PHY_RX0_CLK] = &gcc_usb4_1_phy_rx0_clk.clkr,
6535
+
[GCC_USB4_1_PHY_RX0_CLK_SRC] = &gcc_usb4_1_phy_rx0_clk_src.clkr,
7144
6536
[GCC_USB4_1_PHY_RX1_CLK] = &gcc_usb4_1_phy_rx1_clk.clkr,
6537
+
[GCC_USB4_1_PHY_RX1_CLK_SRC] = &gcc_usb4_1_phy_rx1_clk_src.clkr,
6538
+
[GCC_USB4_1_PHY_SYS_CLK_SRC] = &gcc_usb4_1_phy_sys_clk_src.clkr,
7145
6539
[GCC_USB4_1_PHY_USB_PIPE_CLK] = &gcc_usb4_1_phy_usb_pipe_clk.clkr,
7146
6540
[GCC_USB4_1_SB_IF_CLK] = &gcc_usb4_1_sb_if_clk.clkr,
7147
6541
[GCC_USB4_1_SB_IF_CLK_SRC] = &gcc_usb4_1_sb_if_clk_src.clkr,
···
7160
6540
[GCC_USB4_2_DP1_CLK] = &gcc_usb4_2_dp1_clk.clkr,
7161
6541
[GCC_USB4_2_MASTER_CLK] = &gcc_usb4_2_master_clk.clkr,
7162
6542
[GCC_USB4_2_MASTER_CLK_SRC] = &gcc_usb4_2_master_clk_src.clkr,
6543
+
[GCC_USB4_2_PHY_DP0_CLK_SRC] = &gcc_usb4_2_phy_dp0_clk_src.clkr,
6544
+
[GCC_USB4_2_PHY_DP1_CLK_SRC] = &gcc_usb4_2_phy_dp1_clk_src.clkr,
7163
6545
[GCC_USB4_2_PHY_P2RR2P_PIPE_CLK] = &gcc_usb4_2_phy_p2rr2p_pipe_clk.clkr,
6546
+
[GCC_USB4_2_PHY_P2RR2P_PIPE_CLK_SRC] = &gcc_usb4_2_phy_p2rr2p_pipe_clk_src.clkr,
7164
6547
[GCC_USB4_2_PHY_PCIE_PIPE_CLK] = &gcc_usb4_2_phy_pcie_pipe_clk.clkr,
7165
6548
[GCC_USB4_2_PHY_PCIE_PIPE_CLK_SRC] = &gcc_usb4_2_phy_pcie_pipe_clk_src.clkr,
6549
+
[GCC_USB4_2_PHY_PCIE_PIPE_MUX_CLK_SRC] = &gcc_usb4_2_phy_pcie_pipe_mux_clk_src.clkr,
7166
6550
[GCC_USB4_2_PHY_RX0_CLK] = &gcc_usb4_2_phy_rx0_clk.clkr,
6551
+
[GCC_USB4_2_PHY_RX0_CLK_SRC] = &gcc_usb4_2_phy_rx0_clk_src.clkr,
7167
6552
[GCC_USB4_2_PHY_RX1_CLK] = &gcc_usb4_2_phy_rx1_clk.clkr,
6553
+
[GCC_USB4_2_PHY_RX1_CLK_SRC] = &gcc_usb4_2_phy_rx1_clk_src.clkr,
6554
+
[GCC_USB4_2_PHY_SYS_CLK_SRC] = &gcc_usb4_2_phy_sys_clk_src.clkr,
7168
6555
[GCC_USB4_2_PHY_USB_PIPE_CLK] = &gcc_usb4_2_phy_usb_pipe_clk.clkr,
7169
6556
[GCC_USB4_2_SB_IF_CLK] = &gcc_usb4_2_sb_if_clk.clkr,
7170
6557
[GCC_USB4_2_SB_IF_CLK_SRC] = &gcc_usb4_2_sb_if_clk_src.clkr,
···
7287
6660
[GCC_USB3_UNIPHY_MP0_BCR] = { 0x19000 },
7288
6661
[GCC_USB3_UNIPHY_MP1_BCR] = { 0x54000 },
7289
6662
[GCC_USB3PHY_PHY_PRIM_BCR] = { 0x50004 },
6663
+
[GCC_USB4PHY_PHY_PRIM_BCR] = { 0x5000c },
7290
6664
[GCC_USB3PHY_PHY_SEC_BCR] = { 0x2a004 },
6665
+
[GCC_USB4PHY_PHY_SEC_BCR] = { 0x2a00c },
7291
6666
[GCC_USB3PHY_PHY_TERT_BCR] = { 0xa3004 },
6667
+
[GCC_USB4PHY_PHY_TERT_BCR] = { 0xa300c },
7292
6668
[GCC_USB3UNIPHY_PHY_MP0_BCR] = { 0x19004 },
7293
6669
[GCC_USB3UNIPHY_PHY_MP1_BCR] = { 0x54004 },
7294
6670
[GCC_USB4_0_BCR] = { 0x9f000 },
7295
6671
[GCC_USB4_0_DP0_PHY_PRIM_BCR] = { 0x50010 },
7296
-
[GCC_USB4_1_DP0_PHY_SEC_BCR] = { 0x2a010 },
7297
-
[GCC_USB4_2_DP0_PHY_TERT_BCR] = { 0xa3010 },
6672
+
[GCC_USB4_0_MISC_USB4_SYS_BCR] = { .reg = 0xad0f8, .bit = 0 },
6673
+
[GCC_USB4_0_MISC_RX_CLK_0_BCR] = { .reg = 0xad0f8, .bit = 1 },
6674
+
[GCC_USB4_0_MISC_RX_CLK_1_BCR] = { .reg = 0xad0f8, .bit = 2 },
6675
+
[GCC_USB4_0_MISC_USB_PIPE_BCR] = { .reg = 0xad0f8, .bit = 3 },
6676
+
[GCC_USB4_0_MISC_PCIE_PIPE_BCR] = { .reg = 0xad0f8, .bit = 4 },
6677
+
[GCC_USB4_0_MISC_TMU_BCR] = { .reg = 0xad0f8, .bit = 5 },
6678
+
[GCC_USB4_0_MISC_SB_IF_BCR] = { .reg = 0xad0f8, .bit = 6 },
6679
+
[GCC_USB4_0_MISC_HIA_MSTR_BCR] = { .reg = 0xad0f8, .bit = 7 },
6680
+
[GCC_USB4_0_MISC_AHB_BCR] = { .reg = 0xad0f8, .bit = 8 },
6681
+
[GCC_USB4_0_MISC_DP0_MAX_PCLK_BCR] = { .reg = 0xad0f8, .bit = 9 },
6682
+
[GCC_USB4_0_MISC_DP1_MAX_PCLK_BCR] = { .reg = 0xad0f8, .bit = 10 },
7298
6683
[GCC_USB4_1_BCR] = { 0x2b000 },
6684
+
[GCC_USB4_1_DP0_PHY_SEC_BCR] = { 0x2a010 },
6685
+
[GCC_USB4_1_MISC_USB4_SYS_BCR] = { .reg = 0xae0f8, .bit = 0 },
6686
+
[GCC_USB4_1_MISC_RX_CLK_0_BCR] = { .reg = 0xae0f8, .bit = 1 },
6687
+
[GCC_USB4_1_MISC_RX_CLK_1_BCR] = { .reg = 0xae0f8, .bit = 2 },
6688
+
[GCC_USB4_1_MISC_USB_PIPE_BCR] = { .reg = 0xae0f8, .bit = 3 },
6689
+
[GCC_USB4_1_MISC_PCIE_PIPE_BCR] = { .reg = 0xae0f8, .bit = 4 },
6690
+
[GCC_USB4_1_MISC_TMU_BCR] = { .reg = 0xae0f8, .bit = 5 },
6691
+
[GCC_USB4_1_MISC_SB_IF_BCR] = { .reg = 0xae0f8, .bit = 6 },
6692
+
[GCC_USB4_1_MISC_HIA_MSTR_BCR] = { .reg = 0xae0f8, .bit = 7 },
6693
+
[GCC_USB4_1_MISC_AHB_BCR] = { .reg = 0xae0f8, .bit = 8 },
6694
+
[GCC_USB4_1_MISC_DP0_MAX_PCLK_BCR] = { .reg = 0xae0f8, .bit = 9 },
6695
+
[GCC_USB4_1_MISC_DP1_MAX_PCLK_BCR] = { .reg = 0xae0f8, .bit = 10 },
7299
6696
[GCC_USB4_2_BCR] = { 0x11000 },
6697
+
[GCC_USB4_2_DP0_PHY_TERT_BCR] = { 0xa3010 },
6698
+
[GCC_USB4_2_MISC_USB4_SYS_BCR] = { .reg = 0xaf0f8, .bit = 0 },
6699
+
[GCC_USB4_2_MISC_RX_CLK_0_BCR] = { .reg = 0xaf0f8, .bit = 1 },
6700
+
[GCC_USB4_2_MISC_RX_CLK_1_BCR] = { .reg = 0xaf0f8, .bit = 2 },
6701
+
[GCC_USB4_2_MISC_USB_PIPE_BCR] = { .reg = 0xaf0f8, .bit = 3 },
6702
+
[GCC_USB4_2_MISC_PCIE_PIPE_BCR] = { .reg = 0xaf0f8, .bit = 4 },
6703
+
[GCC_USB4_2_MISC_TMU_BCR] = { .reg = 0xaf0f8, .bit = 5 },
6704
+
[GCC_USB4_2_MISC_SB_IF_BCR] = { .reg = 0xaf0f8, .bit = 6 },
6705
+
[GCC_USB4_2_MISC_HIA_MSTR_BCR] = { .reg = 0xaf0f8, .bit = 7 },
6706
+
[GCC_USB4_2_MISC_AHB_BCR] = { .reg = 0xaf0f8, .bit = 8 },
6707
+
[GCC_USB4_2_MISC_DP0_MAX_PCLK_BCR] = { .reg = 0xaf0f8, .bit = 9 },
6708
+
[GCC_USB4_2_MISC_DP1_MAX_PCLK_BCR] = { .reg = 0xaf0f8, .bit = 10 },
7300
6709
[GCC_USB_0_PHY_BCR] = { 0x50020 },
7301
6710
[GCC_USB_1_PHY_BCR] = { 0x2a020 },
7302
6711
[GCC_USB_2_PHY_BCR] = { 0xa3020 },
+1
drivers/clk/qcom/mmcc-sdm660.c
+1
drivers/clk/qcom/mmcc-sdm660.c
+1340
drivers/clk/qcom/nsscc-ipq5424.c
+1340
drivers/clk/qcom/nsscc-ipq5424.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
4
+
*/
5
+
6
+
#include <linux/clk.h>
7
+
#include <linux/clk-provider.h>
8
+
#include <linux/err.h>
9
+
#include <linux/interconnect-provider.h>
10
+
#include <linux/kernel.h>
11
+
#include <linux/module.h>
12
+
#include <linux/of.h>
13
+
#include <linux/of_device.h>
14
+
#include <linux/platform_device.h>
15
+
#include <linux/pm_clock.h>
16
+
#include <linux/pm_runtime.h>
17
+
#include <linux/regmap.h>
18
+
19
+
#include <dt-bindings/clock/qcom,ipq5424-nsscc.h>
20
+
#include <dt-bindings/interconnect/qcom,ipq5424.h>
21
+
#include <dt-bindings/reset/qcom,ipq5424-nsscc.h>
22
+
23
+
#include "clk-branch.h"
24
+
#include "clk-rcg.h"
25
+
#include "clk-regmap.h"
26
+
#include "clk-regmap-divider.h"
27
+
#include "common.h"
28
+
#include "reset.h"
29
+
30
+
/* Need to match the order of clocks in DT binding */
31
+
enum {
32
+
DT_CMN_PLL_XO_CLK,
33
+
DT_CMN_PLL_NSS_300M_CLK,
34
+
DT_CMN_PLL_NSS_375M_CLK,
35
+
DT_GCC_GPLL0_OUT_AUX,
36
+
DT_UNIPHY0_NSS_RX_CLK,
37
+
DT_UNIPHY0_NSS_TX_CLK,
38
+
DT_UNIPHY1_NSS_RX_CLK,
39
+
DT_UNIPHY1_NSS_TX_CLK,
40
+
DT_UNIPHY2_NSS_RX_CLK,
41
+
DT_UNIPHY2_NSS_TX_CLK,
42
+
};
43
+
44
+
enum {
45
+
P_CMN_PLL_XO_CLK,
46
+
P_CMN_PLL_NSS_300M_CLK,
47
+
P_CMN_PLL_NSS_375M_CLK,
48
+
P_GCC_GPLL0_OUT_AUX,
49
+
P_UNIPHY0_NSS_RX_CLK,
50
+
P_UNIPHY0_NSS_TX_CLK,
51
+
P_UNIPHY1_NSS_RX_CLK,
52
+
P_UNIPHY1_NSS_TX_CLK,
53
+
P_UNIPHY2_NSS_RX_CLK,
54
+
P_UNIPHY2_NSS_TX_CLK,
55
+
};
56
+
57
+
static const struct parent_map nss_cc_parent_map_0[] = {
58
+
{ P_CMN_PLL_XO_CLK, 0 },
59
+
{ P_GCC_GPLL0_OUT_AUX, 2 },
60
+
{ P_CMN_PLL_NSS_300M_CLK, 5 },
61
+
{ P_CMN_PLL_NSS_375M_CLK, 6 },
62
+
};
63
+
64
+
static const struct clk_parent_data nss_cc_parent_data_0[] = {
65
+
{ .index = DT_CMN_PLL_XO_CLK },
66
+
{ .index = DT_GCC_GPLL0_OUT_AUX },
67
+
{ .index = DT_CMN_PLL_NSS_300M_CLK },
68
+
{ .index = DT_CMN_PLL_NSS_375M_CLK },
69
+
};
70
+
71
+
static const struct parent_map nss_cc_parent_map_1[] = {
72
+
{ P_CMN_PLL_XO_CLK, 0 },
73
+
{ P_GCC_GPLL0_OUT_AUX, 2 },
74
+
{ P_UNIPHY0_NSS_RX_CLK, 3 },
75
+
{ P_UNIPHY0_NSS_TX_CLK, 4 },
76
+
{ P_CMN_PLL_NSS_300M_CLK, 5 },
77
+
{ P_CMN_PLL_NSS_375M_CLK, 6 },
78
+
};
79
+
80
+
static const struct clk_parent_data nss_cc_parent_data_1[] = {
81
+
{ .index = DT_CMN_PLL_XO_CLK },
82
+
{ .index = DT_GCC_GPLL0_OUT_AUX },
83
+
{ .index = DT_UNIPHY0_NSS_RX_CLK },
84
+
{ .index = DT_UNIPHY0_NSS_TX_CLK },
85
+
{ .index = DT_CMN_PLL_NSS_300M_CLK },
86
+
{ .index = DT_CMN_PLL_NSS_375M_CLK },
87
+
};
88
+
89
+
static const struct parent_map nss_cc_parent_map_2[] = {
90
+
{ P_CMN_PLL_XO_CLK, 0 },
91
+
{ P_GCC_GPLL0_OUT_AUX, 2 },
92
+
{ P_UNIPHY1_NSS_RX_CLK, 3 },
93
+
{ P_UNIPHY1_NSS_TX_CLK, 4 },
94
+
{ P_CMN_PLL_NSS_300M_CLK, 5 },
95
+
{ P_CMN_PLL_NSS_375M_CLK, 6 },
96
+
};
97
+
98
+
static const struct clk_parent_data nss_cc_parent_data_2[] = {
99
+
{ .index = DT_CMN_PLL_XO_CLK },
100
+
{ .index = DT_GCC_GPLL0_OUT_AUX },
101
+
{ .index = DT_UNIPHY1_NSS_RX_CLK },
102
+
{ .index = DT_UNIPHY1_NSS_TX_CLK },
103
+
{ .index = DT_CMN_PLL_NSS_300M_CLK },
104
+
{ .index = DT_CMN_PLL_NSS_375M_CLK },
105
+
};
106
+
107
+
static const struct parent_map nss_cc_parent_map_3[] = {
108
+
{ P_CMN_PLL_XO_CLK, 0 },
109
+
{ P_GCC_GPLL0_OUT_AUX, 2 },
110
+
{ P_UNIPHY2_NSS_RX_CLK, 3 },
111
+
{ P_UNIPHY2_NSS_TX_CLK, 4 },
112
+
{ P_CMN_PLL_NSS_300M_CLK, 5 },
113
+
{ P_CMN_PLL_NSS_375M_CLK, 6 },
114
+
};
115
+
116
+
static const struct clk_parent_data nss_cc_parent_data_3[] = {
117
+
{ .index = DT_CMN_PLL_XO_CLK },
118
+
{ .index = DT_GCC_GPLL0_OUT_AUX },
119
+
{ .index = DT_UNIPHY2_NSS_RX_CLK },
120
+
{ .index = DT_UNIPHY2_NSS_TX_CLK },
121
+
{ .index = DT_CMN_PLL_NSS_300M_CLK },
122
+
{ .index = DT_CMN_PLL_NSS_375M_CLK },
123
+
};
124
+
125
+
static const struct freq_tbl ftbl_nss_cc_ce_clk_src[] = {
126
+
F(24000000, P_CMN_PLL_XO_CLK, 1, 0, 0),
127
+
F(375000000, P_CMN_PLL_NSS_375M_CLK, 1, 0, 0),
128
+
{ }
129
+
};
130
+
131
+
static struct clk_rcg2 nss_cc_ce_clk_src = {
132
+
.cmd_rcgr = 0x5e0,
133
+
.mnd_width = 0,
134
+
.hid_width = 5,
135
+
.parent_map = nss_cc_parent_map_0,
136
+
.freq_tbl = ftbl_nss_cc_ce_clk_src,
137
+
.clkr.hw.init = &(const struct clk_init_data){
138
+
.name = "nss_cc_ce_clk_src",
139
+
.parent_data = nss_cc_parent_data_0,
140
+
.num_parents = ARRAY_SIZE(nss_cc_parent_data_0),
141
+
.flags = CLK_SET_RATE_PARENT,
142
+
.ops = &clk_rcg2_ops,
143
+
},
144
+
};
145
+
146
+
static const struct freq_tbl ftbl_nss_cc_cfg_clk_src[] = {
147
+
F(100000000, P_GCC_GPLL0_OUT_AUX, 8, 0, 0),
148
+
{ }
149
+
};
150
+
151
+
static struct clk_rcg2 nss_cc_cfg_clk_src = {
152
+
.cmd_rcgr = 0x6a8,
153
+
.mnd_width = 0,
154
+
.hid_width = 5,
155
+
.parent_map = nss_cc_parent_map_0,
156
+
.freq_tbl = ftbl_nss_cc_cfg_clk_src,
157
+
.clkr.hw.init = &(const struct clk_init_data){
158
+
.name = "nss_cc_cfg_clk_src",
159
+
.parent_data = nss_cc_parent_data_0,
160
+
.num_parents = ARRAY_SIZE(nss_cc_parent_data_0),
161
+
.flags = CLK_SET_RATE_PARENT,
162
+
.ops = &clk_rcg2_ops,
163
+
},
164
+
};
165
+
166
+
static const struct freq_tbl ftbl_nss_cc_eip_bfdcd_clk_src[] = {
167
+
F(300000000, P_CMN_PLL_NSS_300M_CLK, 1, 0, 0),
168
+
F(375000000, P_CMN_PLL_NSS_375M_CLK, 1, 0, 0),
169
+
{ }
170
+
};
171
+
172
+
static struct clk_rcg2 nss_cc_eip_bfdcd_clk_src = {
173
+
.cmd_rcgr = 0x644,
174
+
.mnd_width = 0,
175
+
.hid_width = 5,
176
+
.parent_map = nss_cc_parent_map_0,
177
+
.freq_tbl = ftbl_nss_cc_eip_bfdcd_clk_src,
178
+
.clkr.hw.init = &(const struct clk_init_data){
179
+
.name = "nss_cc_eip_bfdcd_clk_src",
180
+
.parent_data = nss_cc_parent_data_0,
181
+
.num_parents = ARRAY_SIZE(nss_cc_parent_data_0),
182
+
.flags = CLK_SET_RATE_PARENT,
183
+
.ops = &clk_rcg2_ops,
184
+
},
185
+
};
186
+
187
+
static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_25[] = {
188
+
C(P_UNIPHY0_NSS_RX_CLK, 12.5, 0, 0),
189
+
C(P_UNIPHY0_NSS_RX_CLK, 5, 0, 0),
190
+
};
191
+
192
+
static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_125[] = {
193
+
C(P_UNIPHY0_NSS_RX_CLK, 2.5, 0, 0),
194
+
C(P_UNIPHY0_NSS_RX_CLK, 1, 0, 0),
195
+
};
196
+
197
+
static const struct freq_multi_tbl ftbl_nss_cc_port1_rx_clk_src[] = {
198
+
FMS(24000000, P_CMN_PLL_XO_CLK, 1, 0, 0),
199
+
FM(25000000, ftbl_nss_cc_port1_rx_clk_src_25),
200
+
FMS(78125000, P_UNIPHY0_NSS_RX_CLK, 4, 0, 0),
201
+
FM(125000000, ftbl_nss_cc_port1_rx_clk_src_125),
202
+
FMS(156250000, P_UNIPHY0_NSS_RX_CLK, 2, 0, 0),
203
+
FMS(312500000, P_UNIPHY0_NSS_RX_CLK, 1, 0, 0),
204
+
{ }
205
+
};
206
+
207
+
static struct clk_rcg2 nss_cc_port1_rx_clk_src = {
208
+
.cmd_rcgr = 0x4b4,
209
+
.mnd_width = 0,
210
+
.hid_width = 5,
211
+
.parent_map = nss_cc_parent_map_1,
212
+
.freq_multi_tbl = ftbl_nss_cc_port1_rx_clk_src,
213
+
.clkr.hw.init = &(const struct clk_init_data){
214
+
.name = "nss_cc_port1_rx_clk_src",
215
+
.parent_data = nss_cc_parent_data_1,
216
+
.num_parents = ARRAY_SIZE(nss_cc_parent_data_1),
217
+
.ops = &clk_rcg2_fm_ops,
218
+
},
219
+
};
220
+
221
+
static const struct freq_conf ftbl_nss_cc_port1_tx_clk_src_25[] = {
222
+
C(P_UNIPHY0_NSS_TX_CLK, 12.5, 0, 0),
223
+
C(P_UNIPHY0_NSS_TX_CLK, 5, 0, 0),
224
+
};
225
+
226
+
static const struct freq_conf ftbl_nss_cc_port1_tx_clk_src_125[] = {
227
+
C(P_UNIPHY0_NSS_TX_CLK, 2.5, 0, 0),
228
+
C(P_UNIPHY0_NSS_TX_CLK, 1, 0, 0),
229
+
};
230
+
231
+
static const struct freq_multi_tbl ftbl_nss_cc_port1_tx_clk_src[] = {
232
+
FMS(24000000, P_CMN_PLL_XO_CLK, 1, 0, 0),
233
+
FM(25000000, ftbl_nss_cc_port1_tx_clk_src_25),
234
+
FMS(78125000, P_UNIPHY0_NSS_TX_CLK, 4, 0, 0),
235
+
FM(125000000, ftbl_nss_cc_port1_tx_clk_src_125),
236
+
FMS(156250000, P_UNIPHY0_NSS_TX_CLK, 2, 0, 0),
237
+
FMS(312500000, P_UNIPHY0_NSS_TX_CLK, 1, 0, 0),
238
+
{ }
239
+
};
240
+
241
+
static struct clk_rcg2 nss_cc_port1_tx_clk_src = {
242
+
.cmd_rcgr = 0x4c0,
243
+
.mnd_width = 0,
244
+
.hid_width = 5,
245
+
.parent_map = nss_cc_parent_map_1,
246
+
.freq_multi_tbl = ftbl_nss_cc_port1_tx_clk_src,
247
+
.clkr.hw.init = &(const struct clk_init_data){
248
+
.name = "nss_cc_port1_tx_clk_src",
249
+
.parent_data = nss_cc_parent_data_1,
250
+
.num_parents = ARRAY_SIZE(nss_cc_parent_data_1),
251
+
.ops = &clk_rcg2_fm_ops,
252
+
},
253
+
};
254
+
255
+
static const struct freq_conf ftbl_nss_cc_port2_rx_clk_src_25[] = {
256
+
C(P_UNIPHY1_NSS_RX_CLK, 12.5, 0, 0),
257
+
C(P_UNIPHY1_NSS_RX_CLK, 5, 0, 0),
258
+
};
259
+
260
+
static const struct freq_conf ftbl_nss_cc_port2_rx_clk_src_125[] = {
261
+
C(P_UNIPHY1_NSS_RX_CLK, 2.5, 0, 0),
262
+
C(P_UNIPHY1_NSS_RX_CLK, 1, 0, 0),
263
+
};
264
+
265
+
static const struct freq_multi_tbl ftbl_nss_cc_port2_rx_clk_src[] = {
266
+
FMS(24000000, P_CMN_PLL_XO_CLK, 1, 0, 0),
267
+
FM(25000000, ftbl_nss_cc_port2_rx_clk_src_25),
268
+
FMS(78125000, P_UNIPHY1_NSS_RX_CLK, 4, 0, 0),
269
+
FM(125000000, ftbl_nss_cc_port2_rx_clk_src_125),
270
+
FMS(156250000, P_UNIPHY1_NSS_RX_CLK, 2, 0, 0),
271
+
FMS(312500000, P_UNIPHY1_NSS_RX_CLK, 1, 0, 0),
272
+
{ }
273
+
};
274
+
275
+
static struct clk_rcg2 nss_cc_port2_rx_clk_src = {
276
+
.cmd_rcgr = 0x4cc,
277
+
.mnd_width = 0,
278
+
.hid_width = 5,
279
+
.parent_map = nss_cc_parent_map_2,
280
+
.freq_multi_tbl = ftbl_nss_cc_port2_rx_clk_src,
281
+
.clkr.hw.init = &(const struct clk_init_data){
282
+
.name = "nss_cc_port2_rx_clk_src",
283
+
.parent_data = nss_cc_parent_data_2,
284
+
.num_parents = ARRAY_SIZE(nss_cc_parent_data_2),
285
+
.ops = &clk_rcg2_fm_ops,
286
+
},
287
+
};
288
+
289
+
static const struct freq_conf ftbl_nss_cc_port2_tx_clk_src_25[] = {
290
+
C(P_UNIPHY1_NSS_TX_CLK, 12.5, 0, 0),
291
+
C(P_UNIPHY1_NSS_TX_CLK, 5, 0, 0),
292
+
};
293
+
294
+
static const struct freq_conf ftbl_nss_cc_port2_tx_clk_src_125[] = {
295
+
C(P_UNIPHY1_NSS_TX_CLK, 2.5, 0, 0),
296
+
C(P_UNIPHY1_NSS_TX_CLK, 1, 0, 0),
297
+
};
298
+
299
+
static const struct freq_multi_tbl ftbl_nss_cc_port2_tx_clk_src[] = {
300
+
FMS(24000000, P_CMN_PLL_XO_CLK, 1, 0, 0),
301
+
FM(25000000, ftbl_nss_cc_port2_tx_clk_src_25),
302
+
FMS(78125000, P_UNIPHY1_NSS_TX_CLK, 4, 0, 0),
303
+
FM(125000000, ftbl_nss_cc_port2_tx_clk_src_125),
304
+
FMS(156250000, P_UNIPHY1_NSS_TX_CLK, 2, 0, 0),
305
+
FMS(312500000, P_UNIPHY1_NSS_TX_CLK, 1, 0, 0),
306
+
{ }
307
+
};
308
+
309
+
static struct clk_rcg2 nss_cc_port2_tx_clk_src = {
310
+
.cmd_rcgr = 0x4d8,
311
+
.mnd_width = 0,
312
+
.hid_width = 5,
313
+
.parent_map = nss_cc_parent_map_2,
314
+
.freq_multi_tbl = ftbl_nss_cc_port2_tx_clk_src,
315
+
.clkr.hw.init = &(const struct clk_init_data){
316
+
.name = "nss_cc_port2_tx_clk_src",
317
+
.parent_data = nss_cc_parent_data_2,
318
+
.num_parents = ARRAY_SIZE(nss_cc_parent_data_2),
319
+
.ops = &clk_rcg2_fm_ops,
320
+
},
321
+
};
322
+
323
+
static const struct freq_conf ftbl_nss_cc_port3_rx_clk_src_25[] = {
324
+
C(P_UNIPHY2_NSS_RX_CLK, 12.5, 0, 0),
325
+
C(P_UNIPHY2_NSS_RX_CLK, 5, 0, 0),
326
+
};
327
+
328
+
static const struct freq_conf ftbl_nss_cc_port3_rx_clk_src_125[] = {
329
+
C(P_UNIPHY2_NSS_RX_CLK, 2.5, 0, 0),
330
+
C(P_UNIPHY2_NSS_RX_CLK, 1, 0, 0),
331
+
};
332
+
333
+
static const struct freq_multi_tbl ftbl_nss_cc_port3_rx_clk_src[] = {
334
+
FMS(24000000, P_CMN_PLL_XO_CLK, 1, 0, 0),
335
+
FM(25000000, ftbl_nss_cc_port3_rx_clk_src_25),
336
+
FMS(78125000, P_UNIPHY2_NSS_RX_CLK, 4, 0, 0),
337
+
FM(125000000, ftbl_nss_cc_port3_rx_clk_src_125),
338
+
FMS(156250000, P_UNIPHY2_NSS_RX_CLK, 2, 0, 0),
339
+
FMS(312500000, P_UNIPHY2_NSS_RX_CLK, 1, 0, 0),
340
+
{ }
341
+
};
342
+
343
+
static struct clk_rcg2 nss_cc_port3_rx_clk_src = {
344
+
.cmd_rcgr = 0x4e4,
345
+
.mnd_width = 0,
346
+
.hid_width = 5,
347
+
.parent_map = nss_cc_parent_map_3,
348
+
.freq_multi_tbl = ftbl_nss_cc_port3_rx_clk_src,
349
+
.clkr.hw.init = &(const struct clk_init_data){
350
+
.name = "nss_cc_port3_rx_clk_src",
351
+
.parent_data = nss_cc_parent_data_3,
352
+
.num_parents = ARRAY_SIZE(nss_cc_parent_data_3),
353
+
.ops = &clk_rcg2_fm_ops,
354
+
},
355
+
};
356
+
357
+
static const struct freq_conf ftbl_nss_cc_port3_tx_clk_src_25[] = {
358
+
C(P_UNIPHY2_NSS_TX_CLK, 12.5, 0, 0),
359
+
C(P_UNIPHY2_NSS_TX_CLK, 5, 0, 0),
360
+
};
361
+
362
+
static const struct freq_conf ftbl_nss_cc_port3_tx_clk_src_125[] = {
363
+
C(P_UNIPHY2_NSS_TX_CLK, 2.5, 0, 0),
364
+
C(P_UNIPHY2_NSS_TX_CLK, 1, 0, 0),
365
+
};
366
+
367
+
static const struct freq_multi_tbl ftbl_nss_cc_port3_tx_clk_src[] = {
368
+
FMS(24000000, P_CMN_PLL_XO_CLK, 1, 0, 0),
369
+
FM(25000000, ftbl_nss_cc_port3_tx_clk_src_25),
370
+
FMS(78125000, P_UNIPHY2_NSS_TX_CLK, 4, 0, 0),
371
+
FM(125000000, ftbl_nss_cc_port3_tx_clk_src_125),
372
+
FMS(156250000, P_UNIPHY2_NSS_TX_CLK, 2, 0, 0),
373
+
FMS(312500000, P_UNIPHY2_NSS_TX_CLK, 1, 0, 0),
374
+
{ }
375
+
};
376
+
377
+
static struct clk_rcg2 nss_cc_port3_tx_clk_src = {
378
+
.cmd_rcgr = 0x4f0,
379
+
.mnd_width = 0,
380
+
.hid_width = 5,
381
+
.parent_map = nss_cc_parent_map_3,
382
+
.freq_multi_tbl = ftbl_nss_cc_port3_tx_clk_src,
383
+
.clkr.hw.init = &(const struct clk_init_data){
384
+
.name = "nss_cc_port3_tx_clk_src",
385
+
.parent_data = nss_cc_parent_data_3,
386
+
.num_parents = ARRAY_SIZE(nss_cc_parent_data_3),
387
+
.ops = &clk_rcg2_fm_ops,
388
+
},
389
+
};
390
+
391
+
static struct clk_rcg2 nss_cc_ppe_clk_src = {
392
+
.cmd_rcgr = 0x3ec,
393
+
.mnd_width = 0,
394
+
.hid_width = 5,
395
+
.parent_map = nss_cc_parent_map_0,
396
+
.freq_tbl = ftbl_nss_cc_ce_clk_src,
397
+
.clkr.hw.init = &(const struct clk_init_data){
398
+
.name = "nss_cc_ppe_clk_src",
399
+
.parent_data = nss_cc_parent_data_0,
400
+
.num_parents = ARRAY_SIZE(nss_cc_parent_data_0),
401
+
.flags = CLK_SET_RATE_PARENT,
402
+
.ops = &clk_rcg2_ops,
403
+
},
404
+
};
405
+
406
+
static struct clk_regmap_div nss_cc_port1_rx_div_clk_src = {
407
+
.reg = 0x4bc,
408
+
.shift = 0,
409
+
.width = 9,
410
+
.clkr.hw.init = &(const struct clk_init_data) {
411
+
.name = "nss_cc_port1_rx_div_clk_src",
412
+
.parent_hws = (const struct clk_hw*[]){
413
+
&nss_cc_port1_rx_clk_src.clkr.hw,
414
+
},
415
+
.num_parents = 1,
416
+
.flags = CLK_SET_RATE_PARENT,
417
+
.ops = &clk_regmap_div_ops,
418
+
},
419
+
};
420
+
421
+
static struct clk_regmap_div nss_cc_port1_tx_div_clk_src = {
422
+
.reg = 0x4c8,
423
+
.shift = 0,
424
+
.width = 9,
425
+
.clkr.hw.init = &(const struct clk_init_data) {
426
+
.name = "nss_cc_port1_tx_div_clk_src",
427
+
.parent_hws = (const struct clk_hw*[]){
428
+
&nss_cc_port1_tx_clk_src.clkr.hw,
429
+
},
430
+
.num_parents = 1,
431
+
.flags = CLK_SET_RATE_PARENT,
432
+
.ops = &clk_regmap_div_ops,
433
+
},
434
+
};
435
+
436
+
static struct clk_regmap_div nss_cc_port2_rx_div_clk_src = {
437
+
.reg = 0x4d4,
438
+
.shift = 0,
439
+
.width = 9,
440
+
.clkr.hw.init = &(const struct clk_init_data) {
441
+
.name = "nss_cc_port2_rx_div_clk_src",
442
+
.parent_hws = (const struct clk_hw*[]){
443
+
&nss_cc_port2_rx_clk_src.clkr.hw,
444
+
},
445
+
.num_parents = 1,
446
+
.flags = CLK_SET_RATE_PARENT,
447
+
.ops = &clk_regmap_div_ops,
448
+
},
449
+
};
450
+
451
+
static struct clk_regmap_div nss_cc_port2_tx_div_clk_src = {
452
+
.reg = 0x4e0,
453
+
.shift = 0,
454
+
.width = 9,
455
+
.clkr.hw.init = &(const struct clk_init_data) {
456
+
.name = "nss_cc_port2_tx_div_clk_src",
457
+
.parent_hws = (const struct clk_hw*[]){
458
+
&nss_cc_port2_tx_clk_src.clkr.hw,
459
+
},
460
+
.num_parents = 1,
461
+
.flags = CLK_SET_RATE_PARENT,
462
+
.ops = &clk_regmap_div_ops,
463
+
},
464
+
};
465
+
466
+
static struct clk_regmap_div nss_cc_port3_rx_div_clk_src = {
467
+
.reg = 0x4ec,
468
+
.shift = 0,
469
+
.width = 9,
470
+
.clkr.hw.init = &(const struct clk_init_data) {
471
+
.name = "nss_cc_port3_rx_div_clk_src",
472
+
.parent_hws = (const struct clk_hw*[]){
473
+
&nss_cc_port3_rx_clk_src.clkr.hw,
474
+
},
475
+
.num_parents = 1,
476
+
.flags = CLK_SET_RATE_PARENT,
477
+
.ops = &clk_regmap_div_ops,
478
+
},
479
+
};
480
+
481
+
static struct clk_regmap_div nss_cc_port3_tx_div_clk_src = {
482
+
.reg = 0x4f8,
483
+
.shift = 0,
484
+
.width = 9,
485
+
.clkr.hw.init = &(const struct clk_init_data) {
486
+
.name = "nss_cc_port3_tx_div_clk_src",
487
+
.parent_hws = (const struct clk_hw*[]){
488
+
&nss_cc_port3_tx_clk_src.clkr.hw,
489
+
},
490
+
.num_parents = 1,
491
+
.flags = CLK_SET_RATE_PARENT,
492
+
.ops = &clk_regmap_div_ops,
493
+
},
494
+
};
495
+
496
+
static struct clk_regmap_div nss_cc_xgmac0_ptp_ref_div_clk_src = {
497
+
.reg = 0x3f4,
498
+
.shift = 0,
499
+
.width = 4,
500
+
.clkr.hw.init = &(const struct clk_init_data) {
501
+
.name = "nss_cc_xgmac0_ptp_ref_div_clk_src",
502
+
.parent_hws = (const struct clk_hw*[]){
503
+
&nss_cc_ppe_clk_src.clkr.hw,
504
+
},
505
+
.num_parents = 1,
506
+
.flags = CLK_SET_RATE_PARENT,
507
+
.ops = &clk_regmap_div_ro_ops,
508
+
},
509
+
};
510
+
511
+
static struct clk_regmap_div nss_cc_xgmac1_ptp_ref_div_clk_src = {
512
+
.reg = 0x3f8,
513
+
.shift = 0,
514
+
.width = 4,
515
+
.clkr.hw.init = &(const struct clk_init_data) {
516
+
.name = "nss_cc_xgmac1_ptp_ref_div_clk_src",
517
+
.parent_hws = (const struct clk_hw*[]){
518
+
&nss_cc_ppe_clk_src.clkr.hw,
519
+
},
520
+
.num_parents = 1,
521
+
.flags = CLK_SET_RATE_PARENT,
522
+
.ops = &clk_regmap_div_ro_ops,
523
+
},
524
+
};
525
+
526
+
static struct clk_regmap_div nss_cc_xgmac2_ptp_ref_div_clk_src = {
527
+
.reg = 0x3fc,
528
+
.shift = 0,
529
+
.width = 4,
530
+
.clkr.hw.init = &(const struct clk_init_data) {
531
+
.name = "nss_cc_xgmac2_ptp_ref_div_clk_src",
532
+
.parent_hws = (const struct clk_hw*[]){
533
+
&nss_cc_ppe_clk_src.clkr.hw,
534
+
},
535
+
.num_parents = 1,
536
+
.flags = CLK_SET_RATE_PARENT,
537
+
.ops = &clk_regmap_div_ro_ops,
538
+
},
539
+
};
540
+
541
+
static struct clk_branch nss_cc_ce_apb_clk = {
542
+
.halt_reg = 0x5e8,
543
+
.halt_check = BRANCH_HALT,
544
+
.clkr = {
545
+
.enable_reg = 0x5e8,
546
+
.enable_mask = BIT(0),
547
+
.hw.init = &(const struct clk_init_data){
548
+
.name = "nss_cc_ce_apb_clk",
549
+
.parent_hws = (const struct clk_hw*[]){
550
+
&nss_cc_ce_clk_src.clkr.hw,
551
+
},
552
+
.num_parents = 1,
553
+
.flags = CLK_SET_RATE_PARENT,
554
+
.ops = &clk_branch2_ops,
555
+
},
556
+
},
557
+
};
558
+
559
+
static struct clk_branch nss_cc_ce_axi_clk = {
560
+
.halt_reg = 0x5ec,
561
+
.halt_check = BRANCH_HALT,
562
+
.clkr = {
563
+
.enable_reg = 0x5ec,
564
+
.enable_mask = BIT(0),
565
+
.hw.init = &(const struct clk_init_data){
566
+
.name = "nss_cc_ce_axi_clk",
567
+
.parent_hws = (const struct clk_hw*[]){
568
+
&nss_cc_ce_clk_src.clkr.hw,
569
+
},
570
+
.num_parents = 1,
571
+
.flags = CLK_SET_RATE_PARENT,
572
+
.ops = &clk_branch2_ops,
573
+
},
574
+
},
575
+
};
576
+
577
+
static struct clk_branch nss_cc_debug_clk = {
578
+
.halt_reg = 0x70c,
579
+
.halt_check = BRANCH_HALT,
580
+
.clkr = {
581
+
.enable_reg = 0x70c,
582
+
.enable_mask = BIT(0),
583
+
.hw.init = &(const struct clk_init_data){
584
+
.name = "nss_cc_debug_clk",
585
+
.ops = &clk_branch2_ops,
586
+
},
587
+
},
588
+
};
589
+
590
+
static struct clk_branch nss_cc_eip_clk = {
591
+
.halt_reg = 0x658,
592
+
.halt_check = BRANCH_HALT,
593
+
.clkr = {
594
+
.enable_reg = 0x658,
595
+
.enable_mask = BIT(0),
596
+
.hw.init = &(const struct clk_init_data){
597
+
.name = "nss_cc_eip_clk",
598
+
.parent_hws = (const struct clk_hw*[]){
599
+
&nss_cc_eip_bfdcd_clk_src.clkr.hw,
600
+
},
601
+
.num_parents = 1,
602
+
.flags = CLK_SET_RATE_PARENT,
603
+
.ops = &clk_branch2_ops,
604
+
},
605
+
},
606
+
};
607
+
608
+
static struct clk_branch nss_cc_nss_csr_clk = {
609
+
.halt_reg = 0x6b0,
610
+
.halt_check = BRANCH_HALT,
611
+
.clkr = {
612
+
.enable_reg = 0x6b0,
613
+
.enable_mask = BIT(0),
614
+
.hw.init = &(const struct clk_init_data){
615
+
.name = "nss_cc_nss_csr_clk",
616
+
.parent_hws = (const struct clk_hw*[]){
617
+
&nss_cc_cfg_clk_src.clkr.hw,
618
+
},
619
+
.num_parents = 1,
620
+
.flags = CLK_SET_RATE_PARENT,
621
+
.ops = &clk_branch2_ops,
622
+
},
623
+
},
624
+
};
625
+
626
+
static struct clk_branch nss_cc_nssnoc_ce_apb_clk = {
627
+
.halt_reg = 0x5f4,
628
+
.halt_check = BRANCH_HALT,
629
+
.clkr = {
630
+
.enable_reg = 0x5f4,
631
+
.enable_mask = BIT(0),
632
+
.hw.init = &(const struct clk_init_data){
633
+
.name = "nss_cc_nssnoc_ce_apb_clk",
634
+
.parent_hws = (const struct clk_hw*[]){
635
+
&nss_cc_ce_clk_src.clkr.hw,
636
+
},
637
+
.num_parents = 1,
638
+
.flags = CLK_SET_RATE_PARENT,
639
+
.ops = &clk_branch2_ops,
640
+
},
641
+
},
642
+
};
643
+
644
+
static struct clk_branch nss_cc_nssnoc_ce_axi_clk = {
645
+
.halt_reg = 0x5f8,
646
+
.halt_check = BRANCH_HALT,
647
+
.clkr = {
648
+
.enable_reg = 0x5f8,
649
+
.enable_mask = BIT(0),
650
+
.hw.init = &(const struct clk_init_data){
651
+
.name = "nss_cc_nssnoc_ce_axi_clk",
652
+
.parent_hws = (const struct clk_hw*[]){
653
+
&nss_cc_ce_clk_src.clkr.hw,
654
+
},
655
+
.num_parents = 1,
656
+
.flags = CLK_SET_RATE_PARENT,
657
+
.ops = &clk_branch2_ops,
658
+
},
659
+
},
660
+
};
661
+
662
+
static struct clk_branch nss_cc_nssnoc_eip_clk = {
663
+
.halt_reg = 0x660,
664
+
.halt_check = BRANCH_HALT,
665
+
.clkr = {
666
+
.enable_reg = 0x660,
667
+
.enable_mask = BIT(0),
668
+
.hw.init = &(const struct clk_init_data){
669
+
.name = "nss_cc_nssnoc_eip_clk",
670
+
.parent_hws = (const struct clk_hw*[]){
671
+
&nss_cc_eip_bfdcd_clk_src.clkr.hw,
672
+
},
673
+
.num_parents = 1,
674
+
.flags = CLK_SET_RATE_PARENT,
675
+
.ops = &clk_branch2_ops,
676
+
},
677
+
},
678
+
};
679
+
680
+
static struct clk_branch nss_cc_nssnoc_nss_csr_clk = {
681
+
.halt_reg = 0x6b4,
682
+
.halt_check = BRANCH_HALT,
683
+
.clkr = {
684
+
.enable_reg = 0x6b4,
685
+
.enable_mask = BIT(0),
686
+
.hw.init = &(const struct clk_init_data){
687
+
.name = "nss_cc_nssnoc_nss_csr_clk",
688
+
.parent_hws = (const struct clk_hw*[]){
689
+
&nss_cc_cfg_clk_src.clkr.hw,
690
+
},
691
+
.num_parents = 1,
692
+
.flags = CLK_SET_RATE_PARENT,
693
+
.ops = &clk_branch2_ops,
694
+
},
695
+
},
696
+
};
697
+
698
+
static struct clk_branch nss_cc_nssnoc_ppe_cfg_clk = {
699
+
.halt_reg = 0x444,
700
+
.halt_check = BRANCH_HALT,
701
+
.clkr = {
702
+
.enable_reg = 0x444,
703
+
.enable_mask = BIT(0),
704
+
.hw.init = &(const struct clk_init_data){
705
+
.name = "nss_cc_nssnoc_ppe_cfg_clk",
706
+
.parent_hws = (const struct clk_hw*[]){
707
+
&nss_cc_ppe_clk_src.clkr.hw,
708
+
},
709
+
.num_parents = 1,
710
+
.flags = CLK_SET_RATE_PARENT,
711
+
.ops = &clk_branch2_ops,
712
+
},
713
+
},
714
+
};
715
+
716
+
static struct clk_branch nss_cc_nssnoc_ppe_clk = {
717
+
.halt_reg = 0x440,
718
+
.halt_check = BRANCH_HALT,
719
+
.clkr = {
720
+
.enable_reg = 0x440,
721
+
.enable_mask = BIT(0),
722
+
.hw.init = &(const struct clk_init_data){
723
+
.name = "nss_cc_nssnoc_ppe_clk",
724
+
.parent_hws = (const struct clk_hw*[]){
725
+
&nss_cc_ppe_clk_src.clkr.hw,
726
+
},
727
+
.num_parents = 1,
728
+
.flags = CLK_SET_RATE_PARENT,
729
+
.ops = &clk_branch2_ops,
730
+
},
731
+
},
732
+
};
733
+
734
+
static struct clk_branch nss_cc_port1_mac_clk = {
735
+
.halt_reg = 0x428,
736
+
.halt_check = BRANCH_HALT,
737
+
.clkr = {
738
+
.enable_reg = 0x428,
739
+
.enable_mask = BIT(0),
740
+
.hw.init = &(const struct clk_init_data){
741
+
.name = "nss_cc_port1_mac_clk",
742
+
.parent_hws = (const struct clk_hw*[]){
743
+
&nss_cc_ppe_clk_src.clkr.hw,
744
+
},
745
+
.num_parents = 1,
746
+
.flags = CLK_SET_RATE_PARENT,
747
+
.ops = &clk_branch2_ops,
748
+
},
749
+
},
750
+
};
751
+
752
+
static struct clk_branch nss_cc_port1_rx_clk = {
753
+
.halt_reg = 0x4fc,
754
+
.halt_check = BRANCH_HALT,
755
+
.clkr = {
756
+
.enable_reg = 0x4fc,
757
+
.enable_mask = BIT(0),
758
+
.hw.init = &(const struct clk_init_data){
759
+
.name = "nss_cc_port1_rx_clk",
760
+
.parent_hws = (const struct clk_hw*[]){
761
+
&nss_cc_port1_rx_div_clk_src.clkr.hw,
762
+
},
763
+
.num_parents = 1,
764
+
.flags = CLK_SET_RATE_PARENT,
765
+
.ops = &clk_branch2_ops,
766
+
},
767
+
},
768
+
};
769
+
770
+
static struct clk_branch nss_cc_port1_tx_clk = {
771
+
.halt_reg = 0x504,
772
+
.halt_check = BRANCH_HALT,
773
+
.clkr = {
774
+
.enable_reg = 0x504,
775
+
.enable_mask = BIT(0),
776
+
.hw.init = &(const struct clk_init_data){
777
+
.name = "nss_cc_port1_tx_clk",
778
+
.parent_hws = (const struct clk_hw*[]){
779
+
&nss_cc_port1_tx_div_clk_src.clkr.hw,
780
+
},
781
+
.num_parents = 1,
782
+
.flags = CLK_SET_RATE_PARENT,
783
+
.ops = &clk_branch2_ops,
784
+
},
785
+
},
786
+
};
787
+
788
+
static struct clk_branch nss_cc_port2_mac_clk = {
789
+
.halt_reg = 0x430,
790
+
.halt_check = BRANCH_HALT,
791
+
.clkr = {
792
+
.enable_reg = 0x430,
793
+
.enable_mask = BIT(0),
794
+
.hw.init = &(const struct clk_init_data){
795
+
.name = "nss_cc_port2_mac_clk",
796
+
.parent_hws = (const struct clk_hw*[]){
797
+
&nss_cc_ppe_clk_src.clkr.hw,
798
+
},
799
+
.num_parents = 1,
800
+
.flags = CLK_SET_RATE_PARENT,
801
+
.ops = &clk_branch2_ops,
802
+
},
803
+
},
804
+
};
805
+
806
+
static struct clk_branch nss_cc_port2_rx_clk = {
807
+
.halt_reg = 0x50c,
808
+
.halt_check = BRANCH_HALT,
809
+
.clkr = {
810
+
.enable_reg = 0x50c,
811
+
.enable_mask = BIT(0),
812
+
.hw.init = &(const struct clk_init_data){
813
+
.name = "nss_cc_port2_rx_clk",
814
+
.parent_hws = (const struct clk_hw*[]){
815
+
&nss_cc_port2_rx_div_clk_src.clkr.hw,
816
+
},
817
+
.num_parents = 1,
818
+
.flags = CLK_SET_RATE_PARENT,
819
+
.ops = &clk_branch2_ops,
820
+
},
821
+
},
822
+
};
823
+
824
+
static struct clk_branch nss_cc_port2_tx_clk = {
825
+
.halt_reg = 0x514,
826
+
.halt_check = BRANCH_HALT,
827
+
.clkr = {
828
+
.enable_reg = 0x514,
829
+
.enable_mask = BIT(0),
830
+
.hw.init = &(const struct clk_init_data){
831
+
.name = "nss_cc_port2_tx_clk",
832
+
.parent_hws = (const struct clk_hw*[]){
833
+
&nss_cc_port2_tx_div_clk_src.clkr.hw,
834
+
},
835
+
.num_parents = 1,
836
+
.flags = CLK_SET_RATE_PARENT,
837
+
.ops = &clk_branch2_ops,
838
+
},
839
+
},
840
+
};
841
+
842
+
static struct clk_branch nss_cc_port3_mac_clk = {
843
+
.halt_reg = 0x438,
844
+
.halt_check = BRANCH_HALT,
845
+
.clkr = {
846
+
.enable_reg = 0x438,
847
+
.enable_mask = BIT(0),
848
+
.hw.init = &(const struct clk_init_data){
849
+
.name = "nss_cc_port3_mac_clk",
850
+
.parent_hws = (const struct clk_hw*[]){
851
+
&nss_cc_ppe_clk_src.clkr.hw,
852
+
},
853
+
.num_parents = 1,
854
+
.flags = CLK_SET_RATE_PARENT,
855
+
.ops = &clk_branch2_ops,
856
+
},
857
+
},
858
+
};
859
+
860
+
static struct clk_branch nss_cc_port3_rx_clk = {
861
+
.halt_reg = 0x51c,
862
+
.halt_check = BRANCH_HALT,
863
+
.clkr = {
864
+
.enable_reg = 0x51c,
865
+
.enable_mask = BIT(0),
866
+
.hw.init = &(const struct clk_init_data){
867
+
.name = "nss_cc_port3_rx_clk",
868
+
.parent_hws = (const struct clk_hw*[]){
869
+
&nss_cc_port3_rx_div_clk_src.clkr.hw,
870
+
},
871
+
.num_parents = 1,
872
+
.flags = CLK_SET_RATE_PARENT,
873
+
.ops = &clk_branch2_ops,
874
+
},
875
+
},
876
+
};
877
+
878
+
static struct clk_branch nss_cc_port3_tx_clk = {
879
+
.halt_reg = 0x524,
880
+
.halt_check = BRANCH_HALT,
881
+
.clkr = {
882
+
.enable_reg = 0x524,
883
+
.enable_mask = BIT(0),
884
+
.hw.init = &(const struct clk_init_data){
885
+
.name = "nss_cc_port3_tx_clk",
886
+
.parent_hws = (const struct clk_hw*[]){
887
+
&nss_cc_port3_tx_div_clk_src.clkr.hw,
888
+
},
889
+
.num_parents = 1,
890
+
.flags = CLK_SET_RATE_PARENT,
891
+
.ops = &clk_branch2_ops,
892
+
},
893
+
},
894
+
};
895
+
896
+
static struct clk_branch nss_cc_ppe_edma_cfg_clk = {
897
+
.halt_reg = 0x424,
898
+
.halt_check = BRANCH_HALT,
899
+
.clkr = {
900
+
.enable_reg = 0x424,
901
+
.enable_mask = BIT(0),
902
+
.hw.init = &(const struct clk_init_data){
903
+
.name = "nss_cc_ppe_edma_cfg_clk",
904
+
.parent_hws = (const struct clk_hw*[]){
905
+
&nss_cc_ppe_clk_src.clkr.hw,
906
+
},
907
+
.num_parents = 1,
908
+
.flags = CLK_SET_RATE_PARENT,
909
+
.ops = &clk_branch2_ops,
910
+
},
911
+
},
912
+
};
913
+
914
+
static struct clk_branch nss_cc_ppe_edma_clk = {
915
+
.halt_reg = 0x41c,
916
+
.halt_check = BRANCH_HALT,
917
+
.clkr = {
918
+
.enable_reg = 0x41c,
919
+
.enable_mask = BIT(0),
920
+
.hw.init = &(const struct clk_init_data){
921
+
.name = "nss_cc_ppe_edma_clk",
922
+
.parent_hws = (const struct clk_hw*[]){
923
+
&nss_cc_ppe_clk_src.clkr.hw,
924
+
},
925
+
.num_parents = 1,
926
+
.flags = CLK_SET_RATE_PARENT,
927
+
.ops = &clk_branch2_ops,
928
+
},
929
+
},
930
+
};
931
+
932
+
static struct clk_branch nss_cc_ppe_switch_btq_clk = {
933
+
.halt_reg = 0x408,
934
+
.halt_check = BRANCH_HALT,
935
+
.clkr = {
936
+
.enable_reg = 0x408,
937
+
.enable_mask = BIT(0),
938
+
.hw.init = &(const struct clk_init_data){
939
+
.name = "nss_cc_ppe_switch_btq_clk",
940
+
.parent_hws = (const struct clk_hw*[]){
941
+
&nss_cc_ppe_clk_src.clkr.hw,
942
+
},
943
+
.num_parents = 1,
944
+
.flags = CLK_SET_RATE_PARENT,
945
+
.ops = &clk_branch2_ops,
946
+
},
947
+
},
948
+
};
949
+
950
+
static struct clk_branch nss_cc_ppe_switch_cfg_clk = {
951
+
.halt_reg = 0x418,
952
+
.halt_check = BRANCH_HALT,
953
+
.clkr = {
954
+
.enable_reg = 0x418,
955
+
.enable_mask = BIT(0),
956
+
.hw.init = &(const struct clk_init_data){
957
+
.name = "nss_cc_ppe_switch_cfg_clk",
958
+
.parent_hws = (const struct clk_hw*[]){
959
+
&nss_cc_ppe_clk_src.clkr.hw,
960
+
},
961
+
.num_parents = 1,
962
+
.flags = CLK_SET_RATE_PARENT,
963
+
.ops = &clk_branch2_ops,
964
+
},
965
+
},
966
+
};
967
+
968
+
static struct clk_branch nss_cc_ppe_switch_clk = {
969
+
.halt_reg = 0x410,
970
+
.halt_check = BRANCH_HALT,
971
+
.clkr = {
972
+
.enable_reg = 0x410,
973
+
.enable_mask = BIT(0),
974
+
.hw.init = &(const struct clk_init_data){
975
+
.name = "nss_cc_ppe_switch_clk",
976
+
.parent_hws = (const struct clk_hw*[]){
977
+
&nss_cc_ppe_clk_src.clkr.hw,
978
+
},
979
+
.num_parents = 1,
980
+
.flags = CLK_SET_RATE_PARENT,
981
+
.ops = &clk_branch2_ops,
982
+
},
983
+
},
984
+
};
985
+
986
+
static struct clk_branch nss_cc_ppe_switch_ipe_clk = {
987
+
.halt_reg = 0x400,
988
+
.halt_check = BRANCH_HALT,
989
+
.clkr = {
990
+
.enable_reg = 0x400,
991
+
.enable_mask = BIT(0),
992
+
.hw.init = &(const struct clk_init_data){
993
+
.name = "nss_cc_ppe_switch_ipe_clk",
994
+
.parent_hws = (const struct clk_hw*[]){
995
+
&nss_cc_ppe_clk_src.clkr.hw,
996
+
},
997
+
.num_parents = 1,
998
+
.flags = CLK_SET_RATE_PARENT,
999
+
.ops = &clk_branch2_ops,
1000
+
},
1001
+
},
1002
+
};
1003
+
1004
+
static struct clk_branch nss_cc_uniphy_port1_rx_clk = {
1005
+
.halt_reg = 0x57c,
1006
+
.halt_check = BRANCH_HALT,
1007
+
.clkr = {
1008
+
.enable_reg = 0x57c,
1009
+
.enable_mask = BIT(0),
1010
+
.hw.init = &(const struct clk_init_data){
1011
+
.name = "nss_cc_uniphy_port1_rx_clk",
1012
+
.parent_hws = (const struct clk_hw*[]){
1013
+
&nss_cc_port1_rx_div_clk_src.clkr.hw,
1014
+
},
1015
+
.num_parents = 1,
1016
+
.flags = CLK_SET_RATE_PARENT,
1017
+
.ops = &clk_branch2_ops,
1018
+
},
1019
+
},
1020
+
};
1021
+
1022
+
static struct clk_branch nss_cc_uniphy_port1_tx_clk = {
1023
+
.halt_reg = 0x580,
1024
+
.halt_check = BRANCH_HALT,
1025
+
.clkr = {
1026
+
.enable_reg = 0x580,
1027
+
.enable_mask = BIT(0),
1028
+
.hw.init = &(const struct clk_init_data){
1029
+
.name = "nss_cc_uniphy_port1_tx_clk",
1030
+
.parent_hws = (const struct clk_hw*[]){
1031
+
&nss_cc_port1_tx_div_clk_src.clkr.hw,
1032
+
},
1033
+
.num_parents = 1,
1034
+
.flags = CLK_SET_RATE_PARENT,
1035
+
.ops = &clk_branch2_ops,
1036
+
},
1037
+
},
1038
+
};
1039
+
1040
+
static struct clk_branch nss_cc_uniphy_port2_rx_clk = {
1041
+
.halt_reg = 0x584,
1042
+
.halt_check = BRANCH_HALT,
1043
+
.clkr = {
1044
+
.enable_reg = 0x584,
1045
+
.enable_mask = BIT(0),
1046
+
.hw.init = &(const struct clk_init_data){
1047
+
.name = "nss_cc_uniphy_port2_rx_clk",
1048
+
.parent_hws = (const struct clk_hw*[]){
1049
+
&nss_cc_port2_rx_div_clk_src.clkr.hw,
1050
+
},
1051
+
.num_parents = 1,
1052
+
.flags = CLK_SET_RATE_PARENT,
1053
+
.ops = &clk_branch2_ops,
1054
+
},
1055
+
},
1056
+
};
1057
+
1058
+
static struct clk_branch nss_cc_uniphy_port2_tx_clk = {
1059
+
.halt_reg = 0x588,
1060
+
.halt_check = BRANCH_HALT,
1061
+
.clkr = {
1062
+
.enable_reg = 0x588,
1063
+
.enable_mask = BIT(0),
1064
+
.hw.init = &(const struct clk_init_data){
1065
+
.name = "nss_cc_uniphy_port2_tx_clk",
1066
+
.parent_hws = (const struct clk_hw*[]){
1067
+
&nss_cc_port2_tx_div_clk_src.clkr.hw,
1068
+
},
1069
+
.num_parents = 1,
1070
+
.flags = CLK_SET_RATE_PARENT,
1071
+
.ops = &clk_branch2_ops,
1072
+
},
1073
+
},
1074
+
};
1075
+
1076
+
static struct clk_branch nss_cc_uniphy_port3_rx_clk = {
1077
+
.halt_reg = 0x58c,
1078
+
.halt_check = BRANCH_HALT,
1079
+
.clkr = {
1080
+
.enable_reg = 0x58c,
1081
+
.enable_mask = BIT(0),
1082
+
.hw.init = &(const struct clk_init_data){
1083
+
.name = "nss_cc_uniphy_port3_rx_clk",
1084
+
.parent_hws = (const struct clk_hw*[]){
1085
+
&nss_cc_port3_rx_div_clk_src.clkr.hw,
1086
+
},
1087
+
.num_parents = 1,
1088
+
.flags = CLK_SET_RATE_PARENT,
1089
+
.ops = &clk_branch2_ops,
1090
+
},
1091
+
},
1092
+
};
1093
+
1094
+
static struct clk_branch nss_cc_uniphy_port3_tx_clk = {
1095
+
.halt_reg = 0x590,
1096
+
.halt_check = BRANCH_HALT,
1097
+
.clkr = {
1098
+
.enable_reg = 0x590,
1099
+
.enable_mask = BIT(0),
1100
+
.hw.init = &(const struct clk_init_data){
1101
+
.name = "nss_cc_uniphy_port3_tx_clk",
1102
+
.parent_hws = (const struct clk_hw*[]){
1103
+
&nss_cc_port3_tx_div_clk_src.clkr.hw,
1104
+
},
1105
+
.num_parents = 1,
1106
+
.flags = CLK_SET_RATE_PARENT,
1107
+
.ops = &clk_branch2_ops,
1108
+
},
1109
+
},
1110
+
};
1111
+
1112
+
static struct clk_branch nss_cc_xgmac0_ptp_ref_clk = {
1113
+
.halt_reg = 0x448,
1114
+
.halt_check = BRANCH_HALT,
1115
+
.clkr = {
1116
+
.enable_reg = 0x448,
1117
+
.enable_mask = BIT(0),
1118
+
.hw.init = &(const struct clk_init_data){
1119
+
.name = "nss_cc_xgmac0_ptp_ref_clk",
1120
+
.parent_hws = (const struct clk_hw*[]){
1121
+
&nss_cc_xgmac0_ptp_ref_div_clk_src.clkr.hw,
1122
+
},
1123
+
.num_parents = 1,
1124
+
.flags = CLK_SET_RATE_PARENT,
1125
+
.ops = &clk_branch2_ops,
1126
+
},
1127
+
},
1128
+
};
1129
+
1130
+
static struct clk_branch nss_cc_xgmac1_ptp_ref_clk = {
1131
+
.halt_reg = 0x44c,
1132
+
.halt_check = BRANCH_HALT,
1133
+
.clkr = {
1134
+
.enable_reg = 0x44c,
1135
+
.enable_mask = BIT(0),
1136
+
.hw.init = &(const struct clk_init_data){
1137
+
.name = "nss_cc_xgmac1_ptp_ref_clk",
1138
+
.parent_hws = (const struct clk_hw*[]){
1139
+
&nss_cc_xgmac1_ptp_ref_div_clk_src.clkr.hw,
1140
+
},
1141
+
.num_parents = 1,
1142
+
.flags = CLK_SET_RATE_PARENT,
1143
+
.ops = &clk_branch2_ops,
1144
+
},
1145
+
},
1146
+
};
1147
+
1148
+
static struct clk_branch nss_cc_xgmac2_ptp_ref_clk = {
1149
+
.halt_reg = 0x450,
1150
+
.halt_check = BRANCH_HALT,
1151
+
.clkr = {
1152
+
.enable_reg = 0x450,
1153
+
.enable_mask = BIT(0),
1154
+
.hw.init = &(const struct clk_init_data){
1155
+
.name = "nss_cc_xgmac2_ptp_ref_clk",
1156
+
.parent_hws = (const struct clk_hw*[]){
1157
+
&nss_cc_xgmac2_ptp_ref_div_clk_src.clkr.hw,
1158
+
},
1159
+
.num_parents = 1,
1160
+
.flags = CLK_SET_RATE_PARENT,
1161
+
.ops = &clk_branch2_ops,
1162
+
},
1163
+
},
1164
+
};
1165
+
1166
+
static struct clk_regmap *nss_cc_ipq5424_clocks[] = {
1167
+
[NSS_CC_CE_APB_CLK] = &nss_cc_ce_apb_clk.clkr,
1168
+
[NSS_CC_CE_AXI_CLK] = &nss_cc_ce_axi_clk.clkr,
1169
+
[NSS_CC_CE_CLK_SRC] = &nss_cc_ce_clk_src.clkr,
1170
+
[NSS_CC_CFG_CLK_SRC] = &nss_cc_cfg_clk_src.clkr,
1171
+
[NSS_CC_DEBUG_CLK] = &nss_cc_debug_clk.clkr,
1172
+
[NSS_CC_EIP_BFDCD_CLK_SRC] = &nss_cc_eip_bfdcd_clk_src.clkr,
1173
+
[NSS_CC_EIP_CLK] = &nss_cc_eip_clk.clkr,
1174
+
[NSS_CC_NSS_CSR_CLK] = &nss_cc_nss_csr_clk.clkr,
1175
+
[NSS_CC_NSSNOC_CE_APB_CLK] = &nss_cc_nssnoc_ce_apb_clk.clkr,
1176
+
[NSS_CC_NSSNOC_CE_AXI_CLK] = &nss_cc_nssnoc_ce_axi_clk.clkr,
1177
+
[NSS_CC_NSSNOC_EIP_CLK] = &nss_cc_nssnoc_eip_clk.clkr,
1178
+
[NSS_CC_NSSNOC_NSS_CSR_CLK] = &nss_cc_nssnoc_nss_csr_clk.clkr,
1179
+
[NSS_CC_NSSNOC_PPE_CFG_CLK] = &nss_cc_nssnoc_ppe_cfg_clk.clkr,
1180
+
[NSS_CC_NSSNOC_PPE_CLK] = &nss_cc_nssnoc_ppe_clk.clkr,
1181
+
[NSS_CC_PORT1_MAC_CLK] = &nss_cc_port1_mac_clk.clkr,
1182
+
[NSS_CC_PORT1_RX_CLK] = &nss_cc_port1_rx_clk.clkr,
1183
+
[NSS_CC_PORT1_RX_CLK_SRC] = &nss_cc_port1_rx_clk_src.clkr,
1184
+
[NSS_CC_PORT1_RX_DIV_CLK_SRC] = &nss_cc_port1_rx_div_clk_src.clkr,
1185
+
[NSS_CC_PORT1_TX_CLK] = &nss_cc_port1_tx_clk.clkr,
1186
+
[NSS_CC_PORT1_TX_CLK_SRC] = &nss_cc_port1_tx_clk_src.clkr,
1187
+
[NSS_CC_PORT1_TX_DIV_CLK_SRC] = &nss_cc_port1_tx_div_clk_src.clkr,
1188
+
[NSS_CC_PORT2_MAC_CLK] = &nss_cc_port2_mac_clk.clkr,
1189
+
[NSS_CC_PORT2_RX_CLK] = &nss_cc_port2_rx_clk.clkr,
1190
+
[NSS_CC_PORT2_RX_CLK_SRC] = &nss_cc_port2_rx_clk_src.clkr,
1191
+
[NSS_CC_PORT2_RX_DIV_CLK_SRC] = &nss_cc_port2_rx_div_clk_src.clkr,
1192
+
[NSS_CC_PORT2_TX_CLK] = &nss_cc_port2_tx_clk.clkr,
1193
+
[NSS_CC_PORT2_TX_CLK_SRC] = &nss_cc_port2_tx_clk_src.clkr,
1194
+
[NSS_CC_PORT2_TX_DIV_CLK_SRC] = &nss_cc_port2_tx_div_clk_src.clkr,
1195
+
[NSS_CC_PORT3_MAC_CLK] = &nss_cc_port3_mac_clk.clkr,
1196
+
[NSS_CC_PORT3_RX_CLK] = &nss_cc_port3_rx_clk.clkr,
1197
+
[NSS_CC_PORT3_RX_CLK_SRC] = &nss_cc_port3_rx_clk_src.clkr,
1198
+
[NSS_CC_PORT3_RX_DIV_CLK_SRC] = &nss_cc_port3_rx_div_clk_src.clkr,
1199
+
[NSS_CC_PORT3_TX_CLK] = &nss_cc_port3_tx_clk.clkr,
1200
+
[NSS_CC_PORT3_TX_CLK_SRC] = &nss_cc_port3_tx_clk_src.clkr,
1201
+
[NSS_CC_PORT3_TX_DIV_CLK_SRC] = &nss_cc_port3_tx_div_clk_src.clkr,
1202
+
[NSS_CC_PPE_CLK_SRC] = &nss_cc_ppe_clk_src.clkr,
1203
+
[NSS_CC_PPE_EDMA_CFG_CLK] = &nss_cc_ppe_edma_cfg_clk.clkr,
1204
+
[NSS_CC_PPE_EDMA_CLK] = &nss_cc_ppe_edma_clk.clkr,
1205
+
[NSS_CC_PPE_SWITCH_BTQ_CLK] = &nss_cc_ppe_switch_btq_clk.clkr,
1206
+
[NSS_CC_PPE_SWITCH_CFG_CLK] = &nss_cc_ppe_switch_cfg_clk.clkr,
1207
+
[NSS_CC_PPE_SWITCH_CLK] = &nss_cc_ppe_switch_clk.clkr,
1208
+
[NSS_CC_PPE_SWITCH_IPE_CLK] = &nss_cc_ppe_switch_ipe_clk.clkr,
1209
+
[NSS_CC_UNIPHY_PORT1_RX_CLK] = &nss_cc_uniphy_port1_rx_clk.clkr,
1210
+
[NSS_CC_UNIPHY_PORT1_TX_CLK] = &nss_cc_uniphy_port1_tx_clk.clkr,
1211
+
[NSS_CC_UNIPHY_PORT2_RX_CLK] = &nss_cc_uniphy_port2_rx_clk.clkr,
1212
+
[NSS_CC_UNIPHY_PORT2_TX_CLK] = &nss_cc_uniphy_port2_tx_clk.clkr,
1213
+
[NSS_CC_UNIPHY_PORT3_RX_CLK] = &nss_cc_uniphy_port3_rx_clk.clkr,
1214
+
[NSS_CC_UNIPHY_PORT3_TX_CLK] = &nss_cc_uniphy_port3_tx_clk.clkr,
1215
+
[NSS_CC_XGMAC0_PTP_REF_CLK] = &nss_cc_xgmac0_ptp_ref_clk.clkr,
1216
+
[NSS_CC_XGMAC0_PTP_REF_DIV_CLK_SRC] = &nss_cc_xgmac0_ptp_ref_div_clk_src.clkr,
1217
+
[NSS_CC_XGMAC1_PTP_REF_CLK] = &nss_cc_xgmac1_ptp_ref_clk.clkr,
1218
+
[NSS_CC_XGMAC1_PTP_REF_DIV_CLK_SRC] = &nss_cc_xgmac1_ptp_ref_div_clk_src.clkr,
1219
+
[NSS_CC_XGMAC2_PTP_REF_CLK] = &nss_cc_xgmac2_ptp_ref_clk.clkr,
1220
+
[NSS_CC_XGMAC2_PTP_REF_DIV_CLK_SRC] = &nss_cc_xgmac2_ptp_ref_div_clk_src.clkr,
1221
+
};
1222
+
1223
+
static const struct qcom_reset_map nss_cc_ipq5424_resets[] = {
1224
+
[NSS_CC_CE_APB_CLK_ARES] = { 0x5e8, 2 },
1225
+
[NSS_CC_CE_AXI_CLK_ARES] = { 0x5ec, 2 },
1226
+
[NSS_CC_DEBUG_CLK_ARES] = { 0x70c, 2 },
1227
+
[NSS_CC_EIP_CLK_ARES] = { 0x658, 2 },
1228
+
[NSS_CC_NSS_CSR_CLK_ARES] = { 0x6b0, 2 },
1229
+
[NSS_CC_NSSNOC_CE_APB_CLK_ARES] = { 0x5f4, 2 },
1230
+
[NSS_CC_NSSNOC_CE_AXI_CLK_ARES] = { 0x5f8, 2 },
1231
+
[NSS_CC_NSSNOC_EIP_CLK_ARES] = { 0x660, 2 },
1232
+
[NSS_CC_NSSNOC_NSS_CSR_CLK_ARES] = { 0x6b4, 2 },
1233
+
[NSS_CC_NSSNOC_PPE_CLK_ARES] = { 0x440, 2 },
1234
+
[NSS_CC_NSSNOC_PPE_CFG_CLK_ARES] = { 0x444, 2 },
1235
+
[NSS_CC_PORT1_MAC_CLK_ARES] = { 0x428, 2 },
1236
+
[NSS_CC_PORT1_RX_CLK_ARES] = { 0x4fc, 2 },
1237
+
[NSS_CC_PORT1_TX_CLK_ARES] = { 0x504, 2 },
1238
+
[NSS_CC_PORT2_MAC_CLK_ARES] = { 0x430, 2 },
1239
+
[NSS_CC_PORT2_RX_CLK_ARES] = { 0x50c, 2 },
1240
+
[NSS_CC_PORT2_TX_CLK_ARES] = { 0x514, 2 },
1241
+
[NSS_CC_PORT3_MAC_CLK_ARES] = { 0x438, 2 },
1242
+
[NSS_CC_PORT3_RX_CLK_ARES] = { 0x51c, 2 },
1243
+
[NSS_CC_PORT3_TX_CLK_ARES] = { 0x524, 2 },
1244
+
[NSS_CC_PPE_BCR] = { 0x3e8 },
1245
+
[NSS_CC_PPE_EDMA_CLK_ARES] = { 0x41c, 2 },
1246
+
[NSS_CC_PPE_EDMA_CFG_CLK_ARES] = { 0x424, 2 },
1247
+
[NSS_CC_PPE_SWITCH_BTQ_CLK_ARES] = { 0x408, 2 },
1248
+
[NSS_CC_PPE_SWITCH_CLK_ARES] = { 0x410, 2 },
1249
+
[NSS_CC_PPE_SWITCH_CFG_CLK_ARES] = { 0x418, 2 },
1250
+
[NSS_CC_PPE_SWITCH_IPE_CLK_ARES] = { 0x400, 2 },
1251
+
[NSS_CC_UNIPHY_PORT1_RX_CLK_ARES] = { 0x57c, 2 },
1252
+
[NSS_CC_UNIPHY_PORT1_TX_CLK_ARES] = { 0x580, 2 },
1253
+
[NSS_CC_UNIPHY_PORT2_RX_CLK_ARES] = { 0x584, 2 },
1254
+
[NSS_CC_UNIPHY_PORT2_TX_CLK_ARES] = { 0x588, 2 },
1255
+
[NSS_CC_UNIPHY_PORT3_RX_CLK_ARES] = { 0x58c, 2 },
1256
+
[NSS_CC_UNIPHY_PORT3_TX_CLK_ARES] = { 0x590, 2 },
1257
+
[NSS_CC_XGMAC0_PTP_REF_CLK_ARES] = { 0x448, 2 },
1258
+
[NSS_CC_XGMAC1_PTP_REF_CLK_ARES] = { 0x44c, 2 },
1259
+
[NSS_CC_XGMAC2_PTP_REF_CLK_ARES] = { 0x450, 2 },
1260
+
};
1261
+
1262
+
static const struct regmap_config nss_cc_ipq5424_regmap_config = {
1263
+
.reg_bits = 32,
1264
+
.reg_stride = 4,
1265
+
.val_bits = 32,
1266
+
.max_register = 0x800,
1267
+
.fast_io = true,
1268
+
};
1269
+
1270
+
static const struct qcom_icc_hws_data icc_ipq5424_nss_hws[] = {
1271
+
{ MASTER_NSSNOC_PPE, SLAVE_NSSNOC_PPE, NSS_CC_NSSNOC_PPE_CLK },
1272
+
{ MASTER_NSSNOC_PPE_CFG, SLAVE_NSSNOC_PPE_CFG, NSS_CC_NSSNOC_PPE_CFG_CLK },
1273
+
{ MASTER_NSSNOC_NSS_CSR, SLAVE_NSSNOC_NSS_CSR, NSS_CC_NSSNOC_NSS_CSR_CLK },
1274
+
{ MASTER_NSSNOC_CE_AXI, SLAVE_NSSNOC_CE_AXI, NSS_CC_NSSNOC_CE_AXI_CLK},
1275
+
{ MASTER_NSSNOC_CE_APB, SLAVE_NSSNOC_CE_APB, NSS_CC_NSSNOC_CE_APB_CLK},
1276
+
{ MASTER_NSSNOC_EIP, SLAVE_NSSNOC_EIP, NSS_CC_NSSNOC_EIP_CLK},
1277
+
};
1278
+
1279
+
#define IPQ_NSSCC_ID (5424 * 2) /* some unique value */
1280
+
1281
+
static const struct qcom_cc_desc nss_cc_ipq5424_desc = {
1282
+
.config = &nss_cc_ipq5424_regmap_config,
1283
+
.clks = nss_cc_ipq5424_clocks,
1284
+
.num_clks = ARRAY_SIZE(nss_cc_ipq5424_clocks),
1285
+
.resets = nss_cc_ipq5424_resets,
1286
+
.num_resets = ARRAY_SIZE(nss_cc_ipq5424_resets),
1287
+
.icc_hws = icc_ipq5424_nss_hws,
1288
+
.num_icc_hws = ARRAY_SIZE(icc_ipq5424_nss_hws),
1289
+
.icc_first_node_id = IPQ_NSSCC_ID,
1290
+
};
1291
+
1292
+
static const struct dev_pm_ops nss_cc_ipq5424_pm_ops = {
1293
+
SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
1294
+
};
1295
+
1296
+
static const struct of_device_id nss_cc_ipq5424_match_table[] = {
1297
+
{ .compatible = "qcom,ipq5424-nsscc" },
1298
+
{ }
1299
+
};
1300
+
MODULE_DEVICE_TABLE(of, nss_cc_ipq5424_match_table);
1301
+
1302
+
static int nss_cc_ipq5424_probe(struct platform_device *pdev)
1303
+
{
1304
+
int ret;
1305
+
1306
+
ret = devm_pm_runtime_enable(&pdev->dev);
1307
+
if (ret)
1308
+
return dev_err_probe(&pdev->dev, ret, "Fail to enable runtime PM\n");
1309
+
1310
+
ret = devm_pm_clk_create(&pdev->dev);
1311
+
if (ret)
1312
+
return dev_err_probe(&pdev->dev, ret, "Fail to create PM clock\n");
1313
+
1314
+
ret = pm_clk_add(&pdev->dev, "bus");
1315
+
if (ret)
1316
+
return dev_err_probe(&pdev->dev, ret, "Fail to add bus clock\n");
1317
+
1318
+
ret = pm_runtime_resume_and_get(&pdev->dev);
1319
+
if (ret)
1320
+
return dev_err_probe(&pdev->dev, ret, "Fail to resume\n");
1321
+
1322
+
ret = qcom_cc_probe(pdev, &nss_cc_ipq5424_desc);
1323
+
pm_runtime_put(&pdev->dev);
1324
+
1325
+
return ret;
1326
+
}
1327
+
1328
+
static struct platform_driver nss_cc_ipq5424_driver = {
1329
+
.probe = nss_cc_ipq5424_probe,
1330
+
.driver = {
1331
+
.name = "qcom,ipq5424-nsscc",
1332
+
.of_match_table = nss_cc_ipq5424_match_table,
1333
+
.pm = &nss_cc_ipq5424_pm_ops,
1334
+
.sync_state = icc_sync_state,
1335
+
},
1336
+
};
1337
+
module_platform_driver(nss_cc_ipq5424_driver);
1338
+
1339
+
MODULE_DESCRIPTION("Qualcomm Technologies, Inc. NSSCC IPQ5424 Driver");
1340
+
MODULE_LICENSE("GPL");
+27
-27
drivers/clk/qcom/tcsrcc-glymur.c
+27
-27
drivers/clk/qcom/tcsrcc-glymur.c
···
28
28
};
29
29
30
30
static struct clk_branch tcsr_edp_clkref_en = {
31
-
.halt_reg = 0x1c,
31
+
.halt_reg = 0x60,
32
32
.halt_check = BRANCH_HALT_DELAY,
33
33
.clkr = {
34
-
.enable_reg = 0x1c,
34
+
.enable_reg = 0x60,
35
35
.enable_mask = BIT(0),
36
36
.hw.init = &(const struct clk_init_data) {
37
37
.name = "tcsr_edp_clkref_en",
···
45
45
};
46
46
47
47
static struct clk_branch tcsr_pcie_1_clkref_en = {
48
-
.halt_reg = 0x4,
48
+
.halt_reg = 0x48,
49
49
.halt_check = BRANCH_HALT_DELAY,
50
50
.clkr = {
51
-
.enable_reg = 0x4,
51
+
.enable_reg = 0x48,
52
52
.enable_mask = BIT(0),
53
53
.hw.init = &(const struct clk_init_data) {
54
54
.name = "tcsr_pcie_1_clkref_en",
···
62
62
};
63
63
64
64
static struct clk_branch tcsr_pcie_2_clkref_en = {
65
-
.halt_reg = 0x8,
65
+
.halt_reg = 0x4c,
66
66
.halt_check = BRANCH_HALT_DELAY,
67
67
.clkr = {
68
-
.enable_reg = 0x8,
68
+
.enable_reg = 0x4c,
69
69
.enable_mask = BIT(0),
70
70
.hw.init = &(const struct clk_init_data) {
71
71
.name = "tcsr_pcie_2_clkref_en",
···
79
79
};
80
80
81
81
static struct clk_branch tcsr_pcie_3_clkref_en = {
82
-
.halt_reg = 0x10,
82
+
.halt_reg = 0x54,
83
83
.halt_check = BRANCH_HALT_DELAY,
84
84
.clkr = {
85
-
.enable_reg = 0x10,
85
+
.enable_reg = 0x54,
86
86
.enable_mask = BIT(0),
87
87
.hw.init = &(const struct clk_init_data) {
88
88
.name = "tcsr_pcie_3_clkref_en",
···
96
96
};
97
97
98
98
static struct clk_branch tcsr_pcie_4_clkref_en = {
99
-
.halt_reg = 0x14,
99
+
.halt_reg = 0x58,
100
100
.halt_check = BRANCH_HALT_DELAY,
101
101
.clkr = {
102
-
.enable_reg = 0x14,
102
+
.enable_reg = 0x58,
103
103
.enable_mask = BIT(0),
104
104
.hw.init = &(const struct clk_init_data) {
105
105
.name = "tcsr_pcie_4_clkref_en",
···
113
113
};
114
114
115
115
static struct clk_branch tcsr_usb2_1_clkref_en = {
116
-
.halt_reg = 0x28,
116
+
.halt_reg = 0x6c,
117
117
.halt_check = BRANCH_HALT_DELAY,
118
118
.clkr = {
119
-
.enable_reg = 0x28,
119
+
.enable_reg = 0x6c,
120
120
.enable_mask = BIT(0),
121
121
.hw.init = &(const struct clk_init_data) {
122
122
.name = "tcsr_usb2_1_clkref_en",
···
130
130
};
131
131
132
132
static struct clk_branch tcsr_usb2_2_clkref_en = {
133
-
.halt_reg = 0x2c,
133
+
.halt_reg = 0x70,
134
134
.halt_check = BRANCH_HALT_DELAY,
135
135
.clkr = {
136
-
.enable_reg = 0x2c,
136
+
.enable_reg = 0x70,
137
137
.enable_mask = BIT(0),
138
138
.hw.init = &(const struct clk_init_data) {
139
139
.name = "tcsr_usb2_2_clkref_en",
···
147
147
};
148
148
149
149
static struct clk_branch tcsr_usb2_3_clkref_en = {
150
-
.halt_reg = 0x30,
150
+
.halt_reg = 0x74,
151
151
.halt_check = BRANCH_HALT_DELAY,
152
152
.clkr = {
153
-
.enable_reg = 0x30,
153
+
.enable_reg = 0x74,
154
154
.enable_mask = BIT(0),
155
155
.hw.init = &(const struct clk_init_data) {
156
156
.name = "tcsr_usb2_3_clkref_en",
···
164
164
};
165
165
166
166
static struct clk_branch tcsr_usb2_4_clkref_en = {
167
-
.halt_reg = 0x44,
167
+
.halt_reg = 0x88,
168
168
.halt_check = BRANCH_HALT_DELAY,
169
169
.clkr = {
170
-
.enable_reg = 0x44,
170
+
.enable_reg = 0x88,
171
171
.enable_mask = BIT(0),
172
172
.hw.init = &(const struct clk_init_data) {
173
173
.name = "tcsr_usb2_4_clkref_en",
···
181
181
};
182
182
183
183
static struct clk_branch tcsr_usb3_0_clkref_en = {
184
-
.halt_reg = 0x20,
184
+
.halt_reg = 0x64,
185
185
.halt_check = BRANCH_HALT_DELAY,
186
186
.clkr = {
187
-
.enable_reg = 0x20,
187
+
.enable_reg = 0x64,
188
188
.enable_mask = BIT(0),
189
189
.hw.init = &(const struct clk_init_data) {
190
190
.name = "tcsr_usb3_0_clkref_en",
···
198
198
};
199
199
200
200
static struct clk_branch tcsr_usb3_1_clkref_en = {
201
-
.halt_reg = 0x24,
201
+
.halt_reg = 0x68,
202
202
.halt_check = BRANCH_HALT_DELAY,
203
203
.clkr = {
204
-
.enable_reg = 0x24,
204
+
.enable_reg = 0x68,
205
205
.enable_mask = BIT(0),
206
206
.hw.init = &(const struct clk_init_data) {
207
207
.name = "tcsr_usb3_1_clkref_en",
···
215
215
};
216
216
217
217
static struct clk_branch tcsr_usb4_1_clkref_en = {
218
-
.halt_reg = 0x0,
218
+
.halt_reg = 0x44,
219
219
.halt_check = BRANCH_HALT_DELAY,
220
220
.clkr = {
221
-
.enable_reg = 0x0,
221
+
.enable_reg = 0x44,
222
222
.enable_mask = BIT(0),
223
223
.hw.init = &(const struct clk_init_data) {
224
224
.name = "tcsr_usb4_1_clkref_en",
···
232
232
};
233
233
234
234
static struct clk_branch tcsr_usb4_2_clkref_en = {
235
-
.halt_reg = 0x18,
235
+
.halt_reg = 0x5c,
236
236
.halt_check = BRANCH_HALT_DELAY,
237
237
.clkr = {
238
-
.enable_reg = 0x18,
238
+
.enable_reg = 0x5c,
239
239
.enable_mask = BIT(0),
240
240
.hw.init = &(const struct clk_init_data) {
241
241
.name = "tcsr_usb4_2_clkref_en",
···
268
268
.reg_bits = 32,
269
269
.reg_stride = 4,
270
270
.val_bits = 32,
271
-
.max_register = 0x44,
271
+
.max_register = 0x94,
272
272
.fast_io = true,
273
273
};
274
274
+463
drivers/clk/qcom/videocc-sm8750.c
+463
drivers/clk/qcom/videocc-sm8750.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
4
+
*/
5
+
6
+
#include <linux/clk-provider.h>
7
+
#include <linux/mod_devicetable.h>
8
+
#include <linux/module.h>
9
+
#include <linux/platform_device.h>
10
+
#include <linux/pm_runtime.h>
11
+
#include <linux/regmap.h>
12
+
13
+
#include <dt-bindings/clock/qcom,sm8750-videocc.h>
14
+
15
+
#include "clk-alpha-pll.h"
16
+
#include "clk-branch.h"
17
+
#include "clk-pll.h"
18
+
#include "clk-rcg.h"
19
+
#include "clk-regmap.h"
20
+
#include "clk-regmap-divider.h"
21
+
#include "clk-regmap-mux.h"
22
+
#include "common.h"
23
+
#include "gdsc.h"
24
+
#include "reset.h"
25
+
26
+
enum {
27
+
DT_BI_TCXO,
28
+
DT_BI_TCXO_AO,
29
+
DT_SLEEP_CLK,
30
+
};
31
+
32
+
enum {
33
+
P_BI_TCXO,
34
+
P_SLEEP_CLK,
35
+
P_VIDEO_CC_PLL0_OUT_MAIN,
36
+
};
37
+
38
+
static const struct pll_vco taycan_elu_vco[] = {
39
+
{ 249600000, 2500000000, 0 },
40
+
};
41
+
42
+
static const struct alpha_pll_config video_cc_pll0_config = {
43
+
.l = 0x25,
44
+
.alpha = 0x8000,
45
+
.config_ctl_val = 0x19660387,
46
+
.config_ctl_hi_val = 0x098060a0,
47
+
.config_ctl_hi1_val = 0xb416cb20,
48
+
.user_ctl_val = 0x00000000,
49
+
.user_ctl_hi_val = 0x00000002,
50
+
};
51
+
52
+
static struct clk_alpha_pll video_cc_pll0 = {
53
+
.offset = 0x0,
54
+
.config = &video_cc_pll0_config,
55
+
.vco_table = taycan_elu_vco,
56
+
.num_vco = ARRAY_SIZE(taycan_elu_vco),
57
+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_ELU],
58
+
.clkr = {
59
+
.hw.init = &(const struct clk_init_data) {
60
+
.name = "video_cc_pll0",
61
+
.parent_data = &(const struct clk_parent_data) {
62
+
.index = DT_BI_TCXO,
63
+
},
64
+
.num_parents = 1,
65
+
.ops = &clk_alpha_pll_taycan_elu_ops,
66
+
},
67
+
},
68
+
};
69
+
70
+
static const struct parent_map video_cc_parent_map_0[] = {
71
+
{ P_BI_TCXO, 0 },
72
+
};
73
+
74
+
static const struct clk_parent_data video_cc_parent_data_0_ao[] = {
75
+
{ .index = DT_BI_TCXO_AO },
76
+
};
77
+
78
+
static const struct parent_map video_cc_parent_map_1[] = {
79
+
{ P_BI_TCXO, 0 },
80
+
{ P_VIDEO_CC_PLL0_OUT_MAIN, 1 },
81
+
};
82
+
83
+
static const struct clk_parent_data video_cc_parent_data_1[] = {
84
+
{ .index = DT_BI_TCXO },
85
+
{ .hw = &video_cc_pll0.clkr.hw },
86
+
};
87
+
88
+
static const struct parent_map video_cc_parent_map_2[] = {
89
+
{ P_SLEEP_CLK, 0 },
90
+
};
91
+
92
+
static const struct clk_parent_data video_cc_parent_data_2_ao[] = {
93
+
{ .index = DT_SLEEP_CLK },
94
+
};
95
+
96
+
static const struct freq_tbl ftbl_video_cc_ahb_clk_src[] = {
97
+
F(19200000, P_BI_TCXO, 1, 0, 0),
98
+
{ }
99
+
};
100
+
101
+
static struct clk_rcg2 video_cc_ahb_clk_src = {
102
+
.cmd_rcgr = 0x8018,
103
+
.mnd_width = 0,
104
+
.hid_width = 5,
105
+
.parent_map = video_cc_parent_map_0,
106
+
.freq_tbl = ftbl_video_cc_ahb_clk_src,
107
+
.clkr.hw.init = &(const struct clk_init_data) {
108
+
.name = "video_cc_ahb_clk_src",
109
+
.parent_data = video_cc_parent_data_0_ao,
110
+
.num_parents = ARRAY_SIZE(video_cc_parent_data_0_ao),
111
+
.flags = CLK_SET_RATE_PARENT,
112
+
.ops = &clk_rcg2_ops,
113
+
},
114
+
};
115
+
116
+
static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = {
117
+
F(720000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
118
+
F(1014000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
119
+
F(1260000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
120
+
F(1332000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
121
+
F(1600000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
122
+
F(1710000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
123
+
F(1890000000, P_VIDEO_CC_PLL0_OUT_MAIN, 1, 0, 0),
124
+
{ }
125
+
};
126
+
127
+
static struct clk_rcg2 video_cc_mvs0_clk_src = {
128
+
.cmd_rcgr = 0x8000,
129
+
.mnd_width = 0,
130
+
.hid_width = 5,
131
+
.parent_map = video_cc_parent_map_1,
132
+
.freq_tbl = ftbl_video_cc_mvs0_clk_src,
133
+
.clkr.hw.init = &(const struct clk_init_data) {
134
+
.name = "video_cc_mvs0_clk_src",
135
+
.parent_data = video_cc_parent_data_1,
136
+
.num_parents = ARRAY_SIZE(video_cc_parent_data_1),
137
+
.flags = CLK_SET_RATE_PARENT,
138
+
.ops = &clk_rcg2_shared_ops,
139
+
},
140
+
};
141
+
142
+
static const struct freq_tbl ftbl_video_cc_sleep_clk_src[] = {
143
+
F(32000, P_SLEEP_CLK, 1, 0, 0),
144
+
{ }
145
+
};
146
+
147
+
static struct clk_rcg2 video_cc_sleep_clk_src = {
148
+
.cmd_rcgr = 0x80e0,
149
+
.mnd_width = 0,
150
+
.hid_width = 5,
151
+
.parent_map = video_cc_parent_map_2,
152
+
.freq_tbl = ftbl_video_cc_sleep_clk_src,
153
+
.clkr.hw.init = &(const struct clk_init_data) {
154
+
.name = "video_cc_sleep_clk_src",
155
+
.parent_data = video_cc_parent_data_2_ao,
156
+
.num_parents = ARRAY_SIZE(video_cc_parent_data_2_ao),
157
+
.flags = CLK_SET_RATE_PARENT,
158
+
.ops = &clk_rcg2_ops,
159
+
},
160
+
};
161
+
162
+
static struct clk_rcg2 video_cc_xo_clk_src = {
163
+
.cmd_rcgr = 0x80bc,
164
+
.mnd_width = 0,
165
+
.hid_width = 5,
166
+
.parent_map = video_cc_parent_map_0,
167
+
.freq_tbl = ftbl_video_cc_ahb_clk_src,
168
+
.clkr.hw.init = &(const struct clk_init_data) {
169
+
.name = "video_cc_xo_clk_src",
170
+
.parent_data = video_cc_parent_data_0_ao,
171
+
.num_parents = ARRAY_SIZE(video_cc_parent_data_0_ao),
172
+
.flags = CLK_SET_RATE_PARENT,
173
+
.ops = &clk_rcg2_ops,
174
+
},
175
+
};
176
+
177
+
static struct clk_regmap_div video_cc_mvs0_div_clk_src = {
178
+
.reg = 0x809c,
179
+
.shift = 0,
180
+
.width = 4,
181
+
.clkr.hw.init = &(const struct clk_init_data) {
182
+
.name = "video_cc_mvs0_div_clk_src",
183
+
.parent_hws = (const struct clk_hw*[]) {
184
+
&video_cc_mvs0_clk_src.clkr.hw,
185
+
},
186
+
.num_parents = 1,
187
+
.flags = CLK_SET_RATE_PARENT,
188
+
.ops = &clk_regmap_div_ro_ops,
189
+
},
190
+
};
191
+
192
+
static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src = {
193
+
.reg = 0x8060,
194
+
.shift = 0,
195
+
.width = 4,
196
+
.clkr.hw.init = &(const struct clk_init_data) {
197
+
.name = "video_cc_mvs0c_div2_div_clk_src",
198
+
.parent_hws = (const struct clk_hw*[]) {
199
+
&video_cc_mvs0_clk_src.clkr.hw,
200
+
},
201
+
.num_parents = 1,
202
+
.flags = CLK_SET_RATE_PARENT,
203
+
.ops = &clk_regmap_div_ro_ops,
204
+
},
205
+
};
206
+
207
+
static struct clk_branch video_cc_mvs0_clk = {
208
+
.halt_reg = 0x807c,
209
+
.halt_check = BRANCH_HALT_VOTED,
210
+
.hwcg_reg = 0x807c,
211
+
.hwcg_bit = 1,
212
+
.clkr = {
213
+
.enable_reg = 0x807c,
214
+
.enable_mask = BIT(0),
215
+
.hw.init = &(const struct clk_init_data) {
216
+
.name = "video_cc_mvs0_clk",
217
+
.parent_hws = (const struct clk_hw*[]) {
218
+
&video_cc_mvs0_div_clk_src.clkr.hw,
219
+
},
220
+
.num_parents = 1,
221
+
.flags = CLK_SET_RATE_PARENT,
222
+
.ops = &clk_branch2_ops,
223
+
},
224
+
},
225
+
};
226
+
227
+
static struct clk_mem_branch video_cc_mvs0_freerun_clk = {
228
+
.mem_enable_reg = 0x8090,
229
+
.mem_ack_reg = 0x8090,
230
+
.mem_enable_mask = BIT(3),
231
+
.mem_enable_ack_mask = GENMASK(11, 10),
232
+
.mem_enable_invert = true,
233
+
.branch = {
234
+
.halt_reg = 0x808c,
235
+
.halt_check = BRANCH_HALT,
236
+
.clkr = {
237
+
.enable_reg = 0x808c,
238
+
.enable_mask = BIT(0),
239
+
.hw.init = &(const struct clk_init_data) {
240
+
.name = "video_cc_mvs0_freerun_clk",
241
+
.parent_hws = (const struct clk_hw*[]) {
242
+
&video_cc_mvs0_div_clk_src.clkr.hw,
243
+
},
244
+
.num_parents = 1,
245
+
.flags = CLK_SET_RATE_PARENT,
246
+
.ops = &clk_branch2_mem_ops,
247
+
},
248
+
},
249
+
},
250
+
};
251
+
252
+
static struct clk_branch video_cc_mvs0_shift_clk = {
253
+
.halt_reg = 0x80d8,
254
+
.halt_check = BRANCH_HALT_VOTED,
255
+
.hwcg_reg = 0x80d8,
256
+
.hwcg_bit = 1,
257
+
.clkr = {
258
+
.enable_reg = 0x80d8,
259
+
.enable_mask = BIT(0),
260
+
.hw.init = &(const struct clk_init_data) {
261
+
.name = "video_cc_mvs0_shift_clk",
262
+
.parent_hws = (const struct clk_hw*[]) {
263
+
&video_cc_xo_clk_src.clkr.hw,
264
+
},
265
+
.num_parents = 1,
266
+
.flags = CLK_SET_RATE_PARENT,
267
+
.ops = &clk_branch2_ops,
268
+
},
269
+
},
270
+
};
271
+
272
+
static struct clk_branch video_cc_mvs0c_clk = {
273
+
.halt_reg = 0x804c,
274
+
.halt_check = BRANCH_HALT,
275
+
.clkr = {
276
+
.enable_reg = 0x804c,
277
+
.enable_mask = BIT(0),
278
+
.hw.init = &(const struct clk_init_data) {
279
+
.name = "video_cc_mvs0c_clk",
280
+
.parent_hws = (const struct clk_hw*[]) {
281
+
&video_cc_mvs0c_div2_div_clk_src.clkr.hw,
282
+
},
283
+
.num_parents = 1,
284
+
.flags = CLK_SET_RATE_PARENT,
285
+
.ops = &clk_branch2_ops,
286
+
},
287
+
},
288
+
};
289
+
290
+
static struct clk_branch video_cc_mvs0c_freerun_clk = {
291
+
.halt_reg = 0x805c,
292
+
.halt_check = BRANCH_HALT,
293
+
.clkr = {
294
+
.enable_reg = 0x805c,
295
+
.enable_mask = BIT(0),
296
+
.hw.init = &(const struct clk_init_data) {
297
+
.name = "video_cc_mvs0c_freerun_clk",
298
+
.parent_hws = (const struct clk_hw*[]) {
299
+
&video_cc_mvs0c_div2_div_clk_src.clkr.hw,
300
+
},
301
+
.num_parents = 1,
302
+
.flags = CLK_SET_RATE_PARENT,
303
+
.ops = &clk_branch2_ops,
304
+
},
305
+
},
306
+
};
307
+
308
+
static struct clk_branch video_cc_mvs0c_shift_clk = {
309
+
.halt_reg = 0x80dc,
310
+
.halt_check = BRANCH_HALT_VOTED,
311
+
.hwcg_reg = 0x80dc,
312
+
.hwcg_bit = 1,
313
+
.clkr = {
314
+
.enable_reg = 0x80dc,
315
+
.enable_mask = BIT(0),
316
+
.hw.init = &(const struct clk_init_data) {
317
+
.name = "video_cc_mvs0c_shift_clk",
318
+
.parent_hws = (const struct clk_hw*[]) {
319
+
&video_cc_xo_clk_src.clkr.hw,
320
+
},
321
+
.num_parents = 1,
322
+
.flags = CLK_SET_RATE_PARENT,
323
+
.ops = &clk_branch2_ops,
324
+
},
325
+
},
326
+
};
327
+
328
+
static struct gdsc video_cc_mvs0c_gdsc = {
329
+
.gdscr = 0x8034,
330
+
.en_rest_wait_val = 0x2,
331
+
.en_few_wait_val = 0x2,
332
+
.clk_dis_wait_val = 0x6,
333
+
.pd = {
334
+
.name = "video_cc_mvs0c_gdsc",
335
+
},
336
+
.pwrsts = PWRSTS_OFF_ON,
337
+
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
338
+
};
339
+
340
+
static struct gdsc video_cc_mvs0_gdsc = {
341
+
.gdscr = 0x8068,
342
+
.en_rest_wait_val = 0x2,
343
+
.en_few_wait_val = 0x2,
344
+
.clk_dis_wait_val = 0x6,
345
+
.pd = {
346
+
.name = "video_cc_mvs0_gdsc",
347
+
},
348
+
.pwrsts = PWRSTS_OFF_ON,
349
+
.parent = &video_cc_mvs0c_gdsc.pd,
350
+
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE | HW_CTRL_TRIGGER,
351
+
};
352
+
353
+
static struct clk_regmap *video_cc_sm8750_clocks[] = {
354
+
[VIDEO_CC_AHB_CLK_SRC] = &video_cc_ahb_clk_src.clkr,
355
+
[VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr,
356
+
[VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr,
357
+
[VIDEO_CC_MVS0_DIV_CLK_SRC] = &video_cc_mvs0_div_clk_src.clkr,
358
+
[VIDEO_CC_MVS0_FREERUN_CLK] = &video_cc_mvs0_freerun_clk.branch.clkr,
359
+
[VIDEO_CC_MVS0_SHIFT_CLK] = &video_cc_mvs0_shift_clk.clkr,
360
+
[VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr,
361
+
[VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] = &video_cc_mvs0c_div2_div_clk_src.clkr,
362
+
[VIDEO_CC_MVS0C_FREERUN_CLK] = &video_cc_mvs0c_freerun_clk.clkr,
363
+
[VIDEO_CC_MVS0C_SHIFT_CLK] = &video_cc_mvs0c_shift_clk.clkr,
364
+
[VIDEO_CC_PLL0] = &video_cc_pll0.clkr,
365
+
[VIDEO_CC_SLEEP_CLK_SRC] = &video_cc_sleep_clk_src.clkr,
366
+
[VIDEO_CC_XO_CLK_SRC] = &video_cc_xo_clk_src.clkr,
367
+
};
368
+
369
+
static struct gdsc *video_cc_sm8750_gdscs[] = {
370
+
[VIDEO_CC_MVS0_GDSC] = &video_cc_mvs0_gdsc,
371
+
[VIDEO_CC_MVS0C_GDSC] = &video_cc_mvs0c_gdsc,
372
+
};
373
+
374
+
static const struct qcom_reset_map video_cc_sm8750_resets[] = {
375
+
[VIDEO_CC_INTERFACE_BCR] = { 0x80a0 },
376
+
[VIDEO_CC_MVS0_BCR] = { 0x8064 },
377
+
[VIDEO_CC_MVS0C_CLK_ARES] = { 0x804c, 2 },
378
+
[VIDEO_CC_MVS0C_BCR] = { 0x8030 },
379
+
[VIDEO_CC_MVS0_FREERUN_CLK_ARES] = { 0x808c, 2 },
380
+
[VIDEO_CC_MVS0C_FREERUN_CLK_ARES] = { 0x805c, 2 },
381
+
[VIDEO_CC_XO_CLK_ARES] = { 0x80d4, 2 },
382
+
};
383
+
384
+
static const struct regmap_config video_cc_sm8750_regmap_config = {
385
+
.reg_bits = 32,
386
+
.reg_stride = 4,
387
+
.val_bits = 32,
388
+
.max_register = 0x9f4c,
389
+
.fast_io = true,
390
+
};
391
+
392
+
static struct clk_alpha_pll *video_cc_sm8750_plls[] = {
393
+
&video_cc_pll0,
394
+
};
395
+
396
+
static u32 video_cc_sm8750_critical_cbcrs[] = {
397
+
0x80a4, /* VIDEO_CC_AHB_CLK */
398
+
0x80f8, /* VIDEO_CC_SLEEP_CLK */
399
+
0x80d4, /* VIDEO_CC_XO_CLK */
400
+
};
401
+
402
+
static void clk_sm8750_regs_configure(struct device *dev, struct regmap *regmap)
403
+
{
404
+
/* Update DLY_ACCU_RED_SHIFTER_DONE to 0xF for mvs0, mvs0c */
405
+
regmap_update_bits(regmap, 0x8074, GENMASK(25, 21), GENMASK(25, 21));
406
+
regmap_update_bits(regmap, 0x8040, GENMASK(25, 21), GENMASK(25, 21));
407
+
408
+
regmap_update_bits(regmap, 0x9f24, BIT(0), BIT(0));
409
+
}
410
+
411
+
static struct qcom_cc_driver_data video_cc_sm8750_driver_data = {
412
+
.alpha_plls = video_cc_sm8750_plls,
413
+
.num_alpha_plls = ARRAY_SIZE(video_cc_sm8750_plls),
414
+
.clk_cbcrs = video_cc_sm8750_critical_cbcrs,
415
+
.num_clk_cbcrs = ARRAY_SIZE(video_cc_sm8750_critical_cbcrs),
416
+
.clk_regs_configure = clk_sm8750_regs_configure,
417
+
};
418
+
419
+
static struct qcom_cc_desc video_cc_sm8750_desc = {
420
+
.config = &video_cc_sm8750_regmap_config,
421
+
.clks = video_cc_sm8750_clocks,
422
+
.num_clks = ARRAY_SIZE(video_cc_sm8750_clocks),
423
+
.resets = video_cc_sm8750_resets,
424
+
.num_resets = ARRAY_SIZE(video_cc_sm8750_resets),
425
+
.gdscs = video_cc_sm8750_gdscs,
426
+
.num_gdscs = ARRAY_SIZE(video_cc_sm8750_gdscs),
427
+
.use_rpm = true,
428
+
.driver_data = &video_cc_sm8750_driver_data,
429
+
};
430
+
431
+
static const struct of_device_id video_cc_sm8750_match_table[] = {
432
+
{ .compatible = "qcom,sm8750-videocc" },
433
+
{ }
434
+
};
435
+
MODULE_DEVICE_TABLE(of, video_cc_sm8750_match_table);
436
+
437
+
static int video_cc_sm8750_probe(struct platform_device *pdev)
438
+
{
439
+
return qcom_cc_probe(pdev, &video_cc_sm8750_desc);
440
+
}
441
+
442
+
static struct platform_driver video_cc_sm8750_driver = {
443
+
.probe = video_cc_sm8750_probe,
444
+
.driver = {
445
+
.name = "video_cc-sm8750",
446
+
.of_match_table = video_cc_sm8750_match_table,
447
+
},
448
+
};
449
+
450
+
static int __init video_cc_sm8750_init(void)
451
+
{
452
+
return platform_driver_register(&video_cc_sm8750_driver);
453
+
}
454
+
subsys_initcall(video_cc_sm8750_init);
455
+
456
+
static void __exit video_cc_sm8750_exit(void)
457
+
{
458
+
platform_driver_unregister(&video_cc_sm8750_driver);
459
+
}
460
+
module_exit(video_cc_sm8750_exit);
461
+
462
+
MODULE_DESCRIPTION("QTI VIDEO_CC SM8750 Driver");
463
+
MODULE_LICENSE("GPL");
+14
drivers/clk/rockchip/Kconfig
+14
drivers/clk/rockchip/Kconfig
···
30
30
help
31
31
Build the driver for RV1126 Clock Driver.
32
32
33
+
config CLK_RV1126B
34
+
bool "Rockchip RV1126B clock controller support"
35
+
depends on ARM64 || COMPILE_TEST
36
+
default y
37
+
help
38
+
Build the driver for RV1126B Clock Driver.
39
+
33
40
config CLK_RK3036
34
41
bool "Rockchip RK3036 clock controller support"
35
42
depends on ARM || COMPILE_TEST
···
99
92
default y
100
93
help
101
94
Build the driver for RK3399 Clock Driver.
95
+
96
+
config CLK_RK3506
97
+
bool "Rockchip RK3506 clock controller support"
98
+
depends on ARM || COMPILE_TEST
99
+
default y
100
+
help
101
+
Build the driver for RK3506 Clock Driver.
102
102
103
103
config CLK_RK3528
104
104
bool "Rockchip RK3528 clock controller support"
+2
drivers/clk/rockchip/Makefile
+2
drivers/clk/rockchip/Makefile
···
20
20
obj-$(CONFIG_CLK_PX30) += clk-px30.o
21
21
obj-$(CONFIG_CLK_RV110X) += clk-rv1108.o
22
22
obj-$(CONFIG_CLK_RV1126) += clk-rv1126.o
23
+
obj-$(CONFIG_CLK_RV1126B) += clk-rv1126b.o rst-rv1126b.o
23
24
obj-$(CONFIG_CLK_RK3036) += clk-rk3036.o
24
25
obj-$(CONFIG_CLK_RK312X) += clk-rk3128.o
25
26
obj-$(CONFIG_CLK_RK3188) += clk-rk3188.o
···
30
29
obj-$(CONFIG_CLK_RK3328) += clk-rk3328.o
31
30
obj-$(CONFIG_CLK_RK3368) += clk-rk3368.o
32
31
obj-$(CONFIG_CLK_RK3399) += clk-rk3399.o
32
+
obj-$(CONFIG_CLK_RK3506) += clk-rk3506.o rst-rk3506.o
33
33
obj-$(CONFIG_CLK_RK3528) += clk-rk3528.o rst-rk3528.o
34
34
obj-$(CONFIG_CLK_RK3562) += clk-rk3562.o rst-rk3562.o
35
35
obj-$(CONFIG_CLK_RK3568) += clk-rk3568.o
+165
drivers/clk/rockchip/clk-cpu.c
+165
drivers/clk/rockchip/clk-cpu.c
···
396
396
kfree(cpuclk);
397
397
return ERR_PTR(ret);
398
398
}
399
+
400
+
static int rockchip_cpuclk_multi_pll_pre_rate_change(struct rockchip_cpuclk *cpuclk,
401
+
struct clk_notifier_data *ndata)
402
+
{
403
+
unsigned long new_rate = roundup(ndata->new_rate, 1000);
404
+
const struct rockchip_cpuclk_rate_table *rate;
405
+
unsigned long flags;
406
+
407
+
rate = rockchip_get_cpuclk_settings(cpuclk, new_rate);
408
+
if (!rate) {
409
+
pr_err("%s: Invalid rate : %lu for cpuclk\n",
410
+
__func__, new_rate);
411
+
return -EINVAL;
412
+
}
413
+
414
+
if (new_rate > ndata->old_rate) {
415
+
spin_lock_irqsave(cpuclk->lock, flags);
416
+
rockchip_cpuclk_set_dividers(cpuclk, rate);
417
+
spin_unlock_irqrestore(cpuclk->lock, flags);
418
+
}
419
+
420
+
return 0;
421
+
}
422
+
423
+
static int rockchip_cpuclk_multi_pll_post_rate_change(struct rockchip_cpuclk *cpuclk,
424
+
struct clk_notifier_data *ndata)
425
+
{
426
+
unsigned long new_rate = roundup(ndata->new_rate, 1000);
427
+
const struct rockchip_cpuclk_rate_table *rate;
428
+
unsigned long flags;
429
+
430
+
rate = rockchip_get_cpuclk_settings(cpuclk, new_rate);
431
+
if (!rate) {
432
+
pr_err("%s: Invalid rate : %lu for cpuclk\n",
433
+
__func__, new_rate);
434
+
return -EINVAL;
435
+
}
436
+
437
+
if (new_rate < ndata->old_rate) {
438
+
spin_lock_irqsave(cpuclk->lock, flags);
439
+
rockchip_cpuclk_set_dividers(cpuclk, rate);
440
+
spin_unlock_irqrestore(cpuclk->lock, flags);
441
+
}
442
+
443
+
return 0;
444
+
}
445
+
446
+
static int rockchip_cpuclk_multi_pll_notifier_cb(struct notifier_block *nb,
447
+
unsigned long event, void *data)
448
+
{
449
+
struct clk_notifier_data *ndata = data;
450
+
struct rockchip_cpuclk *cpuclk = to_rockchip_cpuclk_nb(nb);
451
+
int ret = 0;
452
+
453
+
pr_debug("%s: event %lu, old_rate %lu, new_rate: %lu\n",
454
+
__func__, event, ndata->old_rate, ndata->new_rate);
455
+
if (event == PRE_RATE_CHANGE)
456
+
ret = rockchip_cpuclk_multi_pll_pre_rate_change(cpuclk, ndata);
457
+
else if (event == POST_RATE_CHANGE)
458
+
ret = rockchip_cpuclk_multi_pll_post_rate_change(cpuclk, ndata);
459
+
460
+
return notifier_from_errno(ret);
461
+
}
462
+
463
+
struct clk *rockchip_clk_register_cpuclk_multi_pll(const char *name,
464
+
const char *const *parent_names,
465
+
u8 num_parents, void __iomem *base,
466
+
int muxdiv_offset, u8 mux_shift,
467
+
u8 mux_width, u8 mux_flags,
468
+
int div_offset, u8 div_shift,
469
+
u8 div_width, u8 div_flags,
470
+
unsigned long flags, spinlock_t *lock,
471
+
const struct rockchip_cpuclk_rate_table *rates,
472
+
int nrates)
473
+
{
474
+
struct rockchip_cpuclk *cpuclk;
475
+
struct clk_hw *hw;
476
+
struct clk_mux *mux = NULL;
477
+
struct clk_divider *div = NULL;
478
+
const struct clk_ops *mux_ops = NULL, *div_ops = NULL;
479
+
int ret;
480
+
481
+
if (num_parents > 1) {
482
+
mux = kzalloc(sizeof(*mux), GFP_KERNEL);
483
+
if (!mux)
484
+
return ERR_PTR(-ENOMEM);
485
+
486
+
mux->reg = base + muxdiv_offset;
487
+
mux->shift = mux_shift;
488
+
mux->mask = BIT(mux_width) - 1;
489
+
mux->flags = mux_flags;
490
+
mux->lock = lock;
491
+
mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops
492
+
: &clk_mux_ops;
493
+
}
494
+
495
+
if (div_width > 0) {
496
+
div = kzalloc(sizeof(*div), GFP_KERNEL);
497
+
if (!div) {
498
+
ret = -ENOMEM;
499
+
goto free_mux;
500
+
}
501
+
502
+
div->flags = div_flags;
503
+
if (div_offset)
504
+
div->reg = base + div_offset;
505
+
else
506
+
div->reg = base + muxdiv_offset;
507
+
div->shift = div_shift;
508
+
div->width = div_width;
509
+
div->lock = lock;
510
+
div_ops = (div_flags & CLK_DIVIDER_READ_ONLY)
511
+
? &clk_divider_ro_ops
512
+
: &clk_divider_ops;
513
+
}
514
+
515
+
hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
516
+
mux ? &mux->hw : NULL, mux_ops,
517
+
div ? &div->hw : NULL, div_ops,
518
+
NULL, NULL, flags);
519
+
if (IS_ERR(hw)) {
520
+
ret = PTR_ERR(hw);
521
+
goto free_div;
522
+
}
523
+
524
+
cpuclk = kzalloc(sizeof(*cpuclk), GFP_KERNEL);
525
+
if (!cpuclk) {
526
+
ret = -ENOMEM;
527
+
goto unregister_clk;
528
+
}
529
+
530
+
cpuclk->reg_base = base;
531
+
cpuclk->lock = lock;
532
+
cpuclk->clk_nb.notifier_call = rockchip_cpuclk_multi_pll_notifier_cb;
533
+
ret = clk_notifier_register(hw->clk, &cpuclk->clk_nb);
534
+
if (ret) {
535
+
pr_err("%s: failed to register clock notifier for %s\n",
536
+
__func__, name);
537
+
goto free_cpuclk;
538
+
}
539
+
540
+
if (nrates > 0) {
541
+
cpuclk->rate_count = nrates;
542
+
cpuclk->rate_table = kmemdup(rates,
543
+
sizeof(*rates) * nrates,
544
+
GFP_KERNEL);
545
+
if (!cpuclk->rate_table) {
546
+
ret = -ENOMEM;
547
+
goto free_cpuclk;
548
+
}
549
+
}
550
+
551
+
return hw->clk;
552
+
553
+
free_cpuclk:
554
+
kfree(cpuclk);
555
+
unregister_clk:
556
+
clk_hw_unregister_composite(hw);
557
+
free_div:
558
+
kfree(div);
559
+
free_mux:
560
+
kfree(mux);
561
+
562
+
return ERR_PTR(ret);
563
+
}
+869
drivers/clk/rockchip/clk-rk3506.c
+869
drivers/clk/rockchip/clk-rk3506.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright (c) 2023-2025 Rockchip Electronics Co., Ltd.
4
+
* Author: Finley Xiao <finley.xiao@rock-chips.com>
5
+
*/
6
+
7
+
#include <linux/clk-provider.h>
8
+
#include <linux/module.h>
9
+
#include <linux/of.h>
10
+
#include <linux/of_device.h>
11
+
#include <linux/of_address.h>
12
+
#include <linux/platform_device.h>
13
+
#include <linux/syscore_ops.h>
14
+
#include <dt-bindings/clock/rockchip,rk3506-cru.h>
15
+
#include "clk.h"
16
+
17
+
#define PVTPLL_SRC_SEL_PVTPLL (BIT(7) | BIT(23))
18
+
19
+
enum rk3506_plls {
20
+
gpll, v0pll, v1pll,
21
+
};
22
+
23
+
/*
24
+
* [FRAC PLL]: GPLL, V0PLL, V1PLL
25
+
* - VCO Frequency: 950MHz to 3800MHZ
26
+
* - Output Frequency: 19MHz to 3800MHZ
27
+
* - refdiv: 1 to 63 (Int Mode), 1 to 2 (Frac Mode)
28
+
* - fbdiv: 16 to 3800 (Int Mode), 20 to 380 (Frac Mode)
29
+
* - post1div: 1 to 7
30
+
* - post2div: 1 to 7
31
+
*/
32
+
static struct rockchip_pll_rate_table rk3506_pll_rates[] = {
33
+
/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
34
+
RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0),
35
+
RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0),
36
+
RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0),
37
+
RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
38
+
RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
39
+
RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
40
+
RK3036_PLL_RATE(1350000000, 4, 225, 1, 1, 1, 0),
41
+
RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
42
+
RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
43
+
RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
44
+
RK3036_PLL_RATE(1179648000, 1, 49, 1, 1, 0, 2550137),
45
+
RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
46
+
RK3036_PLL_RATE(1000000000, 3, 125, 1, 1, 1, 0),
47
+
RK3036_PLL_RATE(993484800, 1, 41, 1, 1, 0, 6630355),
48
+
RK3036_PLL_RATE(983040000, 1, 40, 1, 1, 0, 16106127),
49
+
RK3036_PLL_RATE(960000000, 1, 80, 2, 1, 1, 0),
50
+
RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
51
+
RK3036_PLL_RATE(903168000, 1, 75, 2, 1, 0, 4429185),
52
+
RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
53
+
RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0),
54
+
RK3036_PLL_RATE(600000000, 1, 50, 2, 1, 1, 0),
55
+
RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0),
56
+
RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
57
+
RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
58
+
RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
59
+
RK3036_PLL_RATE(96000000, 1, 48, 6, 2, 1, 0),
60
+
{ /* sentinel */ },
61
+
};
62
+
63
+
#define RK3506_DIV_ACLK_CORE_MASK 0xf
64
+
#define RK3506_DIV_ACLK_CORE_SHIFT 9
65
+
#define RK3506_DIV_PCLK_CORE_MASK 0xf
66
+
#define RK3506_DIV_PCLK_CORE_SHIFT 0
67
+
68
+
#define RK3506_CLKSEL15(_aclk_core_div) \
69
+
{ \
70
+
.reg = RK3506_CLKSEL_CON(15), \
71
+
.val = HIWORD_UPDATE(_aclk_core_div, RK3506_DIV_ACLK_CORE_MASK, \
72
+
RK3506_DIV_ACLK_CORE_SHIFT), \
73
+
}
74
+
75
+
#define RK3506_CLKSEL16(_pclk_core_div) \
76
+
{ \
77
+
.reg = RK3506_CLKSEL_CON(16), \
78
+
.val = HIWORD_UPDATE(_pclk_core_div, RK3506_DIV_PCLK_CORE_MASK, \
79
+
RK3506_DIV_PCLK_CORE_SHIFT), \
80
+
}
81
+
82
+
/* SIGN-OFF: aclk_core: 500M, pclk_core: 125M, */
83
+
#define RK3506_CPUCLK_RATE(_prate, _aclk_core_div, _pclk_core_div) \
84
+
{ \
85
+
.prate = _prate, \
86
+
.divs = { \
87
+
RK3506_CLKSEL15(_aclk_core_div), \
88
+
RK3506_CLKSEL16(_pclk_core_div), \
89
+
}, \
90
+
}
91
+
92
+
static struct rockchip_cpuclk_rate_table rk3506_cpuclk_rates[] __initdata = {
93
+
RK3506_CPUCLK_RATE(1608000000, 3, 12),
94
+
RK3506_CPUCLK_RATE(1512000000, 3, 12),
95
+
RK3506_CPUCLK_RATE(1416000000, 2, 11),
96
+
RK3506_CPUCLK_RATE(1296000000, 2, 10),
97
+
RK3506_CPUCLK_RATE(1200000000, 2, 9),
98
+
RK3506_CPUCLK_RATE(1179648000, 2, 9),
99
+
RK3506_CPUCLK_RATE(1008000000, 1, 7),
100
+
RK3506_CPUCLK_RATE(903168000, 1, 7),
101
+
RK3506_CPUCLK_RATE(800000000, 1, 6),
102
+
RK3506_CPUCLK_RATE(750000000, 1, 5),
103
+
RK3506_CPUCLK_RATE(589824000, 1, 4),
104
+
RK3506_CPUCLK_RATE(400000000, 1, 3),
105
+
RK3506_CPUCLK_RATE(200000000, 1, 1),
106
+
};
107
+
108
+
PNAME(mux_pll_p) = { "xin24m" };
109
+
PNAME(gpll_v0pll_v1pll_parents_p) = { "gpll", "v0pll", "v1pll" };
110
+
PNAME(gpll_v0pll_v1pll_g_parents_p) = { "clk_gpll_gate", "clk_v0pll_gate", "clk_v1pll_gate" };
111
+
PNAME(gpll_v0pll_v1pll_div_parents_p) = { "clk_gpll_div", "clk_v0pll_div", "clk_v1pll_div" };
112
+
PNAME(xin24m_gpll_v0pll_v1pll_g_parents_p) = { "xin24m", "clk_gpll_gate", "clk_v0pll_gate", "clk_v1pll_gate" };
113
+
PNAME(xin24m_g_gpll_v0pll_v1pll_g_parents_p) = { "xin24m_gate", "clk_gpll_gate", "clk_v0pll_gate", "clk_v1pll_gate" };
114
+
PNAME(xin24m_g_gpll_v0pll_v1pll_div_parents_p) = { "xin24m_gate", "clk_gpll_div", "clk_v0pll_div", "clk_v1pll_div" };
115
+
PNAME(xin24m_400k_32k_parents_p) = { "xin24m", "clk_rc", "clk_32k" };
116
+
PNAME(clk_frac_uart_matrix0_mux_parents_p) = { "xin24m", "gpll", "clk_v0pll_gate", "clk_v1pll_gate" };
117
+
PNAME(clk_timer0_parents_p) = { "xin24m", "clk_gpll_div_100m", "clk_32k", "clk_core_pvtpll", "sai0_mclk_in", "sai0_sclk_in" };
118
+
PNAME(clk_timer1_parents_p) = { "xin24m", "clk_gpll_div_100m", "clk_32k", "clk_core_pvtpll", "sai1_mclk_in", "sai1_sclk_in" };
119
+
PNAME(clk_timer2_parents_p) = { "xin24m", "clk_gpll_div_100m", "clk_32k", "clk_core_pvtpll", "sai2_mclk_in", "sai2_sclk_in" };
120
+
PNAME(clk_timer3_parents_p) = { "xin24m", "clk_gpll_div_100m", "clk_32k", "clk_core_pvtpll", "sai3_mclk_in", "sai3_sclk_in" };
121
+
PNAME(clk_timer4_parents_p) = { "xin24m", "clk_gpll_div_100m", "clk_32k", "clk_core_pvtpll", "mclk_asrc0" };
122
+
PNAME(clk_timer5_parents_p) = { "xin24m", "clk_gpll_div_100m", "clk_32k", "clk_core_pvtpll", "mclk_asrc1" };
123
+
PNAME(sclk_uart_parents_p) = { "xin24m", "clk_gpll_gate", "clk_v0pll_gate", "clk_frac_uart_matrix0", "clk_frac_uart_matrix1",
124
+
"clk_frac_common_matrix0", "clk_frac_common_matrix1", "clk_frac_common_matrix2" };
125
+
PNAME(clk_mac_ptp_root_parents_p) = { "gpll", "v0pll", "v1pll" };
126
+
PNAME(clk_pwm_parents_p) = { "clk_rc", "sai0_mclk_in", "sai1_mclk_in", "sai2_mclk_in", "sai3_mclk_in", "sai0_sclk_in", "sai1_sclk_in",
127
+
"sai2_sclk_in", "sai3_sclk_in", "mclk_asrc0", "mclk_asrc1" };
128
+
PNAME(clk_can_parents_p) = { "xin24m", "gpll", "clk_v0pll_gate", "clk_v1pll_gate", "clk_frac_voice_matrix1",
129
+
"clk_frac_common_matrix0", "clk_frac_common_matrix1", "clk_frac_common_matrix2" };
130
+
PNAME(clk_pdm_parents_p) = { "xin24m_gate", "clk_int_voice_matrix0", "clk_int_voice_matrix1", "clk_int_voice_matrix2",
131
+
"clk_frac_voice_matrix0", "clk_frac_voice_matrix1", "clk_frac_common_matrix0", "clk_frac_common_matrix1",
132
+
"clk_frac_common_matrix2", "sai0_mclk_in", "sai1_mclk_in", "sai2_mclk_in", "sai3_mclk_in", "clk_gpll_div" };
133
+
PNAME(mclk_sai_asrc_parents_p) = { "xin24m_gate", "clk_int_voice_matrix0", "clk_int_voice_matrix1", "clk_int_voice_matrix2",
134
+
"clk_frac_voice_matrix0", "clk_frac_voice_matrix1", "clk_frac_common_matrix0", "clk_frac_common_matrix1",
135
+
"clk_frac_common_matrix2", "sai0_mclk_in", "sai1_mclk_in", "sai2_mclk_in", "sai3_mclk_in" };
136
+
PNAME(lrck_asrc_parents_p) = { "mclk_asrc0", "mclk_asrc1", "mclk_asrc2", "mclk_asrc3", "mclk_spdiftx", "clk_spdifrx_to_asrc", "clkout_pdm",
137
+
"sai0_fs", "sai1_fs", "sai2_fs", "sai3_fs", "sai4_fs" };
138
+
PNAME(cclk_src_sdmmc_parents_p) = { "xin24m_gate", "gpll", "clk_v0pll_gate", "clk_v1pll_gate" };
139
+
PNAME(dclk_vop_parents_p) = { "xin24m_gate", "clk_gpll_gate", "clk_v0pll_gate", "clk_v1pll_gate", "dummy_vop_dclk",
140
+
"dummy_vop_dclk", "dummy_vop_dclk", "dummy_vop_dclk" };
141
+
PNAME(dbclk_gpio0_parents_p) = { "xin24m", "clk_rc", "clk_32k_pmu" };
142
+
PNAME(clk_pmu_hp_timer_parents_p) = { "xin24m", "gpll_div_100m", "clk_core_pvtpll" };
143
+
PNAME(clk_ref_out_parents_p) = { "xin24m", "gpll", "v0pll", "v1pll" };
144
+
PNAME(clk_32k_frac_parents_p) = { "xin24m", "v0pll", "v1pll", "clk_rc" };
145
+
PNAME(clk_32k_parents_p) = { "xin32k", "clk_32k_rc", "clk_32k_frac" };
146
+
PNAME(clk_ref_phy_pmu_mux_parents_p) = { "xin24m", "clk_ref_phy_pll" };
147
+
PNAME(clk_vpll_ref_parents_p) = { "xin24m", "clk_pll_ref_io" };
148
+
PNAME(mux_armclk_p) = { "armclk_pll", "clk_core_pvtpll" };
149
+
150
+
#define MFLAGS CLK_MUX_HIWORD_MASK
151
+
#define DFLAGS CLK_DIVIDER_HIWORD_MASK
152
+
#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
153
+
154
+
static struct rockchip_pll_clock rk3506_pll_clks[] __initdata = {
155
+
[gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
156
+
CLK_IS_CRITICAL, RK3506_PLL_CON(0),
157
+
RK3506_MODE_CON, 0, 2, 0, rk3506_pll_rates),
158
+
[v0pll] = PLL(pll_rk3328, PLL_V0PLL, "v0pll", mux_pll_p,
159
+
CLK_IS_CRITICAL, RK3506_PLL_CON(8),
160
+
RK3506_MODE_CON, 2, 0, 0, rk3506_pll_rates),
161
+
[v1pll] = PLL(pll_rk3328, PLL_V1PLL, "v1pll", mux_pll_p,
162
+
CLK_IS_CRITICAL, RK3506_PLL_CON(16),
163
+
RK3506_MODE_CON, 4, 1, 0, rk3506_pll_rates),
164
+
};
165
+
166
+
static struct rockchip_clk_branch rk3506_armclk __initdata =
167
+
MUX(ARMCLK, "armclk", mux_armclk_p, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
168
+
RK3506_CLKSEL_CON(15), 8, 1, MFLAGS);
169
+
170
+
static struct rockchip_clk_branch rk3506_clk_branches[] __initdata = {
171
+
/*
172
+
* CRU Clock-Architecture
173
+
*/
174
+
/* top */
175
+
GATE(XIN24M_GATE, "xin24m_gate", "xin24m", CLK_IS_CRITICAL,
176
+
RK3506_CLKGATE_CON(0), 1, GFLAGS),
177
+
GATE(CLK_GPLL_GATE, "clk_gpll_gate", "gpll", CLK_IS_CRITICAL,
178
+
RK3506_CLKGATE_CON(0), 2, GFLAGS),
179
+
GATE(CLK_V0PLL_GATE, "clk_v0pll_gate", "v0pll", CLK_IS_CRITICAL,
180
+
RK3506_CLKGATE_CON(0), 3, GFLAGS),
181
+
GATE(CLK_V1PLL_GATE, "clk_v1pll_gate", "v1pll", 0,
182
+
RK3506_CLKGATE_CON(0), 4, GFLAGS),
183
+
COMPOSITE_NOMUX(CLK_GPLL_DIV, "clk_gpll_div", "clk_gpll_gate", CLK_IS_CRITICAL,
184
+
RK3506_CLKSEL_CON(0), 6, 4, DFLAGS,
185
+
RK3506_CLKGATE_CON(0), 5, GFLAGS),
186
+
COMPOSITE_NOMUX(CLK_GPLL_DIV_100M, "clk_gpll_div_100m", "clk_gpll_div", 0,
187
+
RK3506_CLKSEL_CON(0), 10, 4, DFLAGS,
188
+
RK3506_CLKGATE_CON(0), 6, GFLAGS),
189
+
COMPOSITE_NOMUX(CLK_V0PLL_DIV, "clk_v0pll_div", "clk_v0pll_gate", CLK_IS_CRITICAL,
190
+
RK3506_CLKSEL_CON(1), 0, 4, DFLAGS,
191
+
RK3506_CLKGATE_CON(0), 7, GFLAGS),
192
+
COMPOSITE_NOMUX(CLK_V1PLL_DIV, "clk_v1pll_div", "clk_v1pll_gate", 0,
193
+
RK3506_CLKSEL_CON(1), 4, 4, DFLAGS,
194
+
RK3506_CLKGATE_CON(0), 8, GFLAGS),
195
+
COMPOSITE_NOMUX(CLK_INT_VOICE_MATRIX0, "clk_int_voice_matrix0", "clk_v0pll_gate", 0,
196
+
RK3506_CLKSEL_CON(1), 8, 5, DFLAGS,
197
+
RK3506_CLKGATE_CON(0), 9, GFLAGS),
198
+
COMPOSITE_NOMUX(CLK_INT_VOICE_MATRIX1, "clk_int_voice_matrix1", "clk_v1pll_gate", 0,
199
+
RK3506_CLKSEL_CON(2), 0, 5, DFLAGS,
200
+
RK3506_CLKGATE_CON(0), 10, GFLAGS),
201
+
COMPOSITE_NOMUX(CLK_INT_VOICE_MATRIX2, "clk_int_voice_matrix2", "clk_v0pll_gate", 0,
202
+
RK3506_CLKSEL_CON(2), 5, 5, DFLAGS,
203
+
RK3506_CLKGATE_CON(0), 11, GFLAGS),
204
+
MUX(CLK_FRAC_UART_MATRIX0_MUX, "clk_frac_uart_matrix0_mux", clk_frac_uart_matrix0_mux_parents_p, 0,
205
+
RK3506_CLKSEL_CON(3), 9, 2, MFLAGS),
206
+
MUX(CLK_FRAC_UART_MATRIX1_MUX, "clk_frac_uart_matrix1_mux", xin24m_gpll_v0pll_v1pll_g_parents_p, 0,
207
+
RK3506_CLKSEL_CON(3), 11, 2, MFLAGS),
208
+
MUX(CLK_FRAC_VOICE_MATRIX0_MUX, "clk_frac_voice_matrix0_mux", xin24m_g_gpll_v0pll_v1pll_g_parents_p, 0,
209
+
RK3506_CLKSEL_CON(3), 13, 2, MFLAGS),
210
+
MUX(CLK_FRAC_VOICE_MATRIX1_MUX, "clk_frac_voice_matrix1_mux", xin24m_g_gpll_v0pll_v1pll_g_parents_p, 0,
211
+
RK3506_CLKSEL_CON(4), 0, 2, MFLAGS),
212
+
MUX(CLK_FRAC_COMMON_MATRIX0_MUX, "clk_frac_common_matrix0_mux", xin24m_gpll_v0pll_v1pll_g_parents_p, 0,
213
+
RK3506_CLKSEL_CON(4), 2, 2, MFLAGS),
214
+
MUX(CLK_FRAC_COMMON_MATRIX1_MUX, "clk_frac_common_matrix1_mux", xin24m_g_gpll_v0pll_v1pll_g_parents_p, 0,
215
+
RK3506_CLKSEL_CON(4), 4, 2, MFLAGS),
216
+
MUX(CLK_FRAC_COMMON_MATRIX2_MUX, "clk_frac_common_matrix2_mux", xin24m_g_gpll_v0pll_v1pll_g_parents_p, 0,
217
+
RK3506_CLKSEL_CON(4), 6, 2, MFLAGS),
218
+
COMPOSITE_FRAC(CLK_FRAC_UART_MATRIX0, "clk_frac_uart_matrix0", "clk_frac_uart_matrix0_mux", 0,
219
+
RK3506_CLKSEL_CON(5), 0,
220
+
RK3506_CLKGATE_CON(0), 13, GFLAGS),
221
+
COMPOSITE_FRAC(CLK_FRAC_UART_MATRIX1, "clk_frac_uart_matrix1", "clk_frac_uart_matrix1_mux", 0,
222
+
RK3506_CLKSEL_CON(6), 0,
223
+
RK3506_CLKGATE_CON(0), 14, GFLAGS),
224
+
COMPOSITE_FRAC(CLK_FRAC_VOICE_MATRIX0, "clk_frac_voice_matrix0", "clk_frac_voice_matrix0_mux", 0,
225
+
RK3506_CLKSEL_CON(7), 0,
226
+
RK3506_CLKGATE_CON(0), 15, GFLAGS),
227
+
COMPOSITE_FRAC(CLK_FRAC_VOICE_MATRIX1, "clk_frac_voice_matrix1", "clk_frac_voice_matrix1_mux", 0,
228
+
RK3506_CLKSEL_CON(9), 0,
229
+
RK3506_CLKGATE_CON(1), 0, GFLAGS),
230
+
COMPOSITE_FRAC(CLK_FRAC_COMMON_MATRIX0, "clk_frac_common_matrix0", "clk_frac_common_matrix0_mux", 0,
231
+
RK3506_CLKSEL_CON(11), 0,
232
+
RK3506_CLKGATE_CON(1), 1, GFLAGS),
233
+
COMPOSITE_FRAC(CLK_FRAC_COMMON_MATRIX1, "clk_frac_common_matrix1", "clk_frac_common_matrix1_mux", 0,
234
+
RK3506_CLKSEL_CON(12), 0,
235
+
RK3506_CLKGATE_CON(1), 2, GFLAGS),
236
+
COMPOSITE_FRAC(CLK_FRAC_COMMON_MATRIX2, "clk_frac_common_matrix2", "clk_frac_common_matrix2_mux", 0,
237
+
RK3506_CLKSEL_CON(13), 0,
238
+
RK3506_CLKGATE_CON(1), 3, GFLAGS),
239
+
GATE(CLK_REF_USBPHY_TOP, "clk_ref_usbphy_top", "xin24m", 0,
240
+
RK3506_CLKGATE_CON(1), 4, GFLAGS),
241
+
GATE(CLK_REF_DPHY_TOP, "clk_ref_dphy_top", "xin24m", 0,
242
+
RK3506_CLKGATE_CON(1), 5, GFLAGS),
243
+
244
+
/* core */
245
+
COMPOSITE_NOGATE(0, "armclk_pll", gpll_v0pll_v1pll_parents_p, CLK_IS_CRITICAL,
246
+
RK3506_CLKSEL_CON(15), 5, 2, MFLAGS, 0, 5, DFLAGS),
247
+
COMPOSITE_NOMUX(ACLK_CORE_ROOT, "aclk_core_root", "armclk", CLK_IGNORE_UNUSED,
248
+
RK3506_CLKSEL_CON(15), 9, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
249
+
RK3506_CLKGATE_CON(2), 11, GFLAGS),
250
+
COMPOSITE_NOMUX(PCLK_CORE_ROOT, "pclk_core_root", "armclk", CLK_IGNORE_UNUSED,
251
+
RK3506_CLKSEL_CON(16), 0, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
252
+
RK3506_CLKGATE_CON(2), 12, GFLAGS),
253
+
GATE(PCLK_DBG, "pclk_dbg", "pclk_core_root", CLK_IGNORE_UNUSED,
254
+
RK3506_CLKGATE_CON(3), 1, GFLAGS),
255
+
GATE(PCLK_CORE_GRF, "pclk_core_grf", "pclk_core_root", CLK_IGNORE_UNUSED,
256
+
RK3506_CLKGATE_CON(3), 4, GFLAGS),
257
+
GATE(PCLK_CORE_CRU, "pclk_core_cru", "pclk_core_root", CLK_IGNORE_UNUSED,
258
+
RK3506_CLKGATE_CON(3), 5, GFLAGS),
259
+
GATE(CLK_CORE_EMA_DETECT, "clk_core_ema_detect", "xin24m_gate", CLK_IGNORE_UNUSED,
260
+
RK3506_CLKGATE_CON(3), 6, GFLAGS),
261
+
GATE(PCLK_GPIO1, "pclk_gpio1", "aclk_core_root", 0,
262
+
RK3506_CLKGATE_CON(3), 8, GFLAGS),
263
+
GATE(DBCLK_GPIO1, "dbclk_gpio1", "xin24m_gate", 0,
264
+
RK3506_CLKGATE_CON(3), 9, GFLAGS),
265
+
266
+
/* core peri */
267
+
COMPOSITE(ACLK_CORE_PERI_ROOT, "aclk_core_peri_root", gpll_v0pll_v1pll_g_parents_p, 0,
268
+
RK3506_CLKSEL_CON(18), 5, 2, MFLAGS, 0, 5, DFLAGS,
269
+
RK3506_CLKGATE_CON(4), 0, GFLAGS),
270
+
GATE(HCLK_CORE_PERI_ROOT, "hclk_core_peri_root", "aclk_core_peri_root", 0,
271
+
RK3506_CLKGATE_CON(4), 1, GFLAGS),
272
+
GATE(PCLK_CORE_PERI_ROOT, "pclk_core_peri_root", "aclk_core_peri_root", 0,
273
+
RK3506_CLKGATE_CON(4), 2, GFLAGS),
274
+
COMPOSITE(CLK_DSMC, "clk_dsmc", xin24m_gpll_v0pll_v1pll_g_parents_p, 0,
275
+
RK3506_CLKSEL_CON(18), 12, 2, MFLAGS, 7, 5, DFLAGS,
276
+
RK3506_CLKGATE_CON(4), 4, GFLAGS),
277
+
GATE(ACLK_DSMC, "aclk_dsmc", "aclk_core_peri_root", 0,
278
+
RK3506_CLKGATE_CON(4), 5, GFLAGS),
279
+
GATE(PCLK_DSMC, "pclk_dsmc", "pclk_core_peri_root", 0,
280
+
RK3506_CLKGATE_CON(4), 6, GFLAGS),
281
+
COMPOSITE(CLK_FLEXBUS_TX, "clk_flexbus_tx", xin24m_gpll_v0pll_v1pll_g_parents_p, 0,
282
+
RK3506_CLKSEL_CON(19), 5, 2, MFLAGS, 0, 5, DFLAGS,
283
+
RK3506_CLKGATE_CON(4), 7, GFLAGS),
284
+
COMPOSITE(CLK_FLEXBUS_RX, "clk_flexbus_rx", xin24m_gpll_v0pll_v1pll_g_parents_p, 0,
285
+
RK3506_CLKSEL_CON(19), 12, 2, MFLAGS, 7, 5, DFLAGS,
286
+
RK3506_CLKGATE_CON(4), 8, GFLAGS),
287
+
GATE(ACLK_FLEXBUS, "aclk_flexbus", "aclk_core_peri_root", 0,
288
+
RK3506_CLKGATE_CON(4), 9, GFLAGS),
289
+
GATE(HCLK_FLEXBUS, "hclk_flexbus", "hclk_core_peri_root", 0,
290
+
RK3506_CLKGATE_CON(4), 10, GFLAGS),
291
+
GATE(ACLK_DSMC_SLV, "aclk_dsmc_slv", "aclk_core_peri_root", 0,
292
+
RK3506_CLKGATE_CON(4), 11, GFLAGS),
293
+
GATE(HCLK_DSMC_SLV, "hclk_dsmc_slv", "hclk_core_peri_root", 0,
294
+
RK3506_CLKGATE_CON(4), 12, GFLAGS),
295
+
296
+
/* bus */
297
+
COMPOSITE(ACLK_BUS_ROOT, "aclk_bus_root", gpll_v0pll_v1pll_div_parents_p, CLK_IS_CRITICAL,
298
+
RK3506_CLKSEL_CON(21), 5, 2, MFLAGS, 0, 5, DFLAGS,
299
+
RK3506_CLKGATE_CON(5), 0, GFLAGS),
300
+
COMPOSITE(HCLK_BUS_ROOT, "hclk_bus_root", gpll_v0pll_v1pll_div_parents_p, CLK_IS_CRITICAL,
301
+
RK3506_CLKSEL_CON(21), 12, 2, MFLAGS, 7, 5, DFLAGS,
302
+
RK3506_CLKGATE_CON(5), 1, GFLAGS),
303
+
COMPOSITE(PCLK_BUS_ROOT, "pclk_bus_root", gpll_v0pll_v1pll_div_parents_p, CLK_IS_CRITICAL,
304
+
RK3506_CLKSEL_CON(22), 5, 2, MFLAGS, 0, 5, DFLAGS,
305
+
RK3506_CLKGATE_CON(5), 2, GFLAGS),
306
+
GATE(ACLK_SYSRAM, "aclk_sysram", "aclk_bus_root", CLK_IGNORE_UNUSED,
307
+
RK3506_CLKGATE_CON(5), 6, GFLAGS),
308
+
GATE(HCLK_SYSRAM, "hclk_sysram", "aclk_bus_root", CLK_IGNORE_UNUSED,
309
+
RK3506_CLKGATE_CON(5), 7, GFLAGS),
310
+
GATE(ACLK_DMAC0, "aclk_dmac0", "aclk_bus_root", 0,
311
+
RK3506_CLKGATE_CON(5), 8, GFLAGS),
312
+
GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_bus_root", 0,
313
+
RK3506_CLKGATE_CON(5), 9, GFLAGS),
314
+
GATE(HCLK_M0, "hclk_m0", "aclk_bus_root", 0,
315
+
RK3506_CLKGATE_CON(5), 10, GFLAGS),
316
+
GATE(ACLK_CRYPTO_NS, "aclk_crypto_ns", "aclk_bus_root", 0,
317
+
RK3506_CLKGATE_CON(5), 14, GFLAGS),
318
+
GATE(HCLK_CRYPTO_NS, "hclk_crypto_ns", "hclk_bus_root", 0,
319
+
RK3506_CLKGATE_CON(5), 15, GFLAGS),
320
+
GATE(HCLK_RNG, "hclk_rng", "hclk_bus_root", 0,
321
+
RK3506_CLKGATE_CON(6), 0, GFLAGS),
322
+
GATE(PCLK_BUS_GRF, "pclk_bus_grf", "pclk_bus_root", CLK_IGNORE_UNUSED,
323
+
RK3506_CLKGATE_CON(6), 1, GFLAGS),
324
+
GATE(PCLK_TIMER, "pclk_timer", "pclk_bus_root", 0,
325
+
RK3506_CLKGATE_CON(6), 2, GFLAGS),
326
+
COMPOSITE_NODIV(CLK_TIMER0_CH0, "clk_timer0_ch0", clk_timer0_parents_p, 0,
327
+
RK3506_CLKSEL_CON(22), 7, 3, MFLAGS,
328
+
RK3506_CLKGATE_CON(6), 3, GFLAGS),
329
+
COMPOSITE_NODIV(CLK_TIMER0_CH1, "clk_timer0_ch1", clk_timer1_parents_p, 0,
330
+
RK3506_CLKSEL_CON(22), 10, 3, MFLAGS,
331
+
RK3506_CLKGATE_CON(6), 4, GFLAGS),
332
+
COMPOSITE_NODIV(CLK_TIMER0_CH2, "clk_timer0_ch2", clk_timer2_parents_p, 0,
333
+
RK3506_CLKSEL_CON(22), 13, 3, MFLAGS,
334
+
RK3506_CLKGATE_CON(6), 5, GFLAGS),
335
+
COMPOSITE_NODIV(CLK_TIMER0_CH3, "clk_timer0_ch3", clk_timer3_parents_p, 0,
336
+
RK3506_CLKSEL_CON(23), 0, 3, MFLAGS,
337
+
RK3506_CLKGATE_CON(6), 6, GFLAGS),
338
+
COMPOSITE_NODIV(CLK_TIMER0_CH4, "clk_timer0_ch4", clk_timer4_parents_p, 0,
339
+
RK3506_CLKSEL_CON(23), 3, 3, MFLAGS,
340
+
RK3506_CLKGATE_CON(6), 7, GFLAGS),
341
+
COMPOSITE_NODIV(CLK_TIMER0_CH5, "clk_timer0_ch5", clk_timer5_parents_p, 0,
342
+
RK3506_CLKSEL_CON(23), 6, 3, MFLAGS,
343
+
RK3506_CLKGATE_CON(6), 8, GFLAGS),
344
+
GATE(PCLK_WDT0, "pclk_wdt0", "pclk_bus_root", 0,
345
+
RK3506_CLKGATE_CON(6), 9, GFLAGS),
346
+
GATE(TCLK_WDT0, "tclk_wdt0", "xin24m_gate", 0,
347
+
RK3506_CLKGATE_CON(6), 10, GFLAGS),
348
+
GATE(PCLK_WDT1, "pclk_wdt1", "pclk_bus_root", 0,
349
+
RK3506_CLKGATE_CON(6), 11, GFLAGS),
350
+
GATE(TCLK_WDT1, "tclk_wdt1", "xin24m_gate", 0,
351
+
RK3506_CLKGATE_CON(6), 12, GFLAGS),
352
+
GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus_root", 0,
353
+
RK3506_CLKGATE_CON(6), 13, GFLAGS),
354
+
GATE(PCLK_INTMUX, "pclk_intmux", "pclk_bus_root", 0,
355
+
RK3506_CLKGATE_CON(6), 14, GFLAGS),
356
+
GATE(PCLK_SPINLOCK, "pclk_spinlock", "pclk_bus_root", 0,
357
+
RK3506_CLKGATE_CON(6), 15, GFLAGS),
358
+
GATE(PCLK_DDRC, "pclk_ddrc", "pclk_bus_root", CLK_IGNORE_UNUSED,
359
+
RK3506_CLKGATE_CON(7), 0, GFLAGS),
360
+
GATE(HCLK_DDRPHY, "hclk_ddrphy", "hclk_bus_root", CLK_IGNORE_UNUSED,
361
+
RK3506_CLKGATE_CON(7), 1, GFLAGS),
362
+
GATE(PCLK_DDRMON, "pclk_ddrmon", "pclk_bus_root", CLK_IGNORE_UNUSED,
363
+
RK3506_CLKGATE_CON(7), 2, GFLAGS),
364
+
GATE(CLK_DDRMON_OSC, "clk_ddrmon_osc", "xin24m_gate", CLK_IGNORE_UNUSED,
365
+
RK3506_CLKGATE_CON(7), 3, GFLAGS),
366
+
GATE(PCLK_STDBY, "pclk_stdby", "pclk_bus_root", CLK_IGNORE_UNUSED,
367
+
RK3506_CLKGATE_CON(7), 4, GFLAGS),
368
+
GATE(HCLK_USBOTG0, "hclk_usbotg0", "hclk_bus_root", 0,
369
+
RK3506_CLKGATE_CON(7), 5, GFLAGS),
370
+
GATE(HCLK_USBOTG0_PMU, "hclk_usbotg0_pmu", "hclk_bus_root", 0,
371
+
RK3506_CLKGATE_CON(7), 6, GFLAGS),
372
+
GATE(CLK_USBOTG0_ADP, "clk_usbotg0_adp", "clk_32k", 0,
373
+
RK3506_CLKGATE_CON(7), 7, GFLAGS),
374
+
GATE(HCLK_USBOTG1, "hclk_usbotg1", "hclk_bus_root", 0,
375
+
RK3506_CLKGATE_CON(7), 8, GFLAGS),
376
+
GATE(HCLK_USBOTG1_PMU, "hclk_usbotg1_pmu", "hclk_bus_root", 0,
377
+
RK3506_CLKGATE_CON(7), 9, GFLAGS),
378
+
GATE(CLK_USBOTG1_ADP, "clk_usbotg1_adp", "clk_32k", 0,
379
+
RK3506_CLKGATE_CON(7), 10, GFLAGS),
380
+
GATE(PCLK_USBPHY, "pclk_usbphy", "pclk_bus_root", 0,
381
+
RK3506_CLKGATE_CON(7), 11, GFLAGS),
382
+
GATE(ACLK_DMA2DDR, "aclk_dma2ddr", "aclk_bus_root", CLK_IGNORE_UNUSED,
383
+
RK3506_CLKGATE_CON(8), 0, GFLAGS),
384
+
GATE(PCLK_DMA2DDR, "pclk_dma2ddr", "pclk_bus_root", CLK_IGNORE_UNUSED,
385
+
RK3506_CLKGATE_CON(8), 1, GFLAGS),
386
+
COMPOSITE_NOMUX(STCLK_M0, "stclk_m0", "xin24m_gate", 0,
387
+
RK3506_CLKSEL_CON(23), 9, 6, DFLAGS,
388
+
RK3506_CLKGATE_CON(8), 2, GFLAGS),
389
+
COMPOSITE(CLK_DDRPHY, "clk_ddrphy", gpll_v0pll_v1pll_parents_p, CLK_IGNORE_UNUSED,
390
+
RK3506_PMU_CLKSEL_CON(4), 4, 2, MFLAGS, 0, 4, DFLAGS,
391
+
RK3506_PMU_CLKGATE_CON(1), 10, GFLAGS),
392
+
FACTOR(CLK_DDRC_SRC, "clk_ddrc_src", "clk_ddrphy", 0, 1, 4),
393
+
GATE(ACLK_DDRC_0, "aclk_ddrc_0", "clk_ddrc_src", CLK_IGNORE_UNUSED,
394
+
RK3506_CLKGATE_CON(10), 0, GFLAGS),
395
+
GATE(ACLK_DDRC_1, "aclk_ddrc_1", "clk_ddrc_src", CLK_IGNORE_UNUSED,
396
+
RK3506_CLKGATE_CON(10), 1, GFLAGS),
397
+
GATE(CLK_DDRC, "clk_ddrc", "clk_ddrc_src", CLK_IS_CRITICAL,
398
+
RK3506_CLKGATE_CON(10), 3, GFLAGS),
399
+
GATE(CLK_DDRMON, "clk_ddrmon", "clk_ddrc_src", CLK_IGNORE_UNUSED,
400
+
RK3506_CLKGATE_CON(10), 4, GFLAGS),
401
+
402
+
/* ls peri */
403
+
COMPOSITE(HCLK_LSPERI_ROOT, "hclk_lsperi_root", gpll_v0pll_v1pll_div_parents_p, 0,
404
+
RK3506_CLKSEL_CON(29), 5, 2, MFLAGS, 0, 5, DFLAGS,
405
+
RK3506_CLKGATE_CON(11), 0, GFLAGS),
406
+
GATE(PCLK_LSPERI_ROOT, "pclk_lsperi_root", "hclk_lsperi_root", 0,
407
+
RK3506_CLKGATE_CON(11), 1, GFLAGS),
408
+
GATE(PCLK_UART0, "pclk_uart0", "pclk_lsperi_root", 0,
409
+
RK3506_CLKGATE_CON(11), 4, GFLAGS),
410
+
GATE(PCLK_UART1, "pclk_uart1", "pclk_lsperi_root", 0,
411
+
RK3506_CLKGATE_CON(11), 5, GFLAGS),
412
+
GATE(PCLK_UART2, "pclk_uart2", "pclk_lsperi_root", 0,
413
+
RK3506_CLKGATE_CON(11), 6, GFLAGS),
414
+
GATE(PCLK_UART3, "pclk_uart3", "pclk_lsperi_root", 0,
415
+
RK3506_CLKGATE_CON(11), 7, GFLAGS),
416
+
GATE(PCLK_UART4, "pclk_uart4", "pclk_lsperi_root", 0,
417
+
RK3506_CLKGATE_CON(11), 8, GFLAGS),
418
+
COMPOSITE(SCLK_UART0, "sclk_uart0", sclk_uart_parents_p, 0,
419
+
RK3506_CLKSEL_CON(29), 12, 3, MFLAGS, 7, 5, DFLAGS,
420
+
RK3506_CLKGATE_CON(11), 9, GFLAGS),
421
+
COMPOSITE(SCLK_UART1, "sclk_uart1", sclk_uart_parents_p, 0,
422
+
RK3506_CLKSEL_CON(30), 5, 3, MFLAGS, 0, 5, DFLAGS,
423
+
RK3506_CLKGATE_CON(11), 10, GFLAGS),
424
+
COMPOSITE(SCLK_UART2, "sclk_uart2", sclk_uart_parents_p, 0,
425
+
RK3506_CLKSEL_CON(30), 13, 3, MFLAGS, 8, 5, DFLAGS,
426
+
RK3506_CLKGATE_CON(11), 11, GFLAGS),
427
+
COMPOSITE(SCLK_UART3, "sclk_uart3", sclk_uart_parents_p, 0,
428
+
RK3506_CLKSEL_CON(31), 5, 3, MFLAGS, 0, 5, DFLAGS,
429
+
RK3506_CLKGATE_CON(11), 12, GFLAGS),
430
+
COMPOSITE(SCLK_UART4, "sclk_uart4", sclk_uart_parents_p, 0,
431
+
RK3506_CLKSEL_CON(31), 13, 3, MFLAGS, 8, 5, DFLAGS,
432
+
RK3506_CLKGATE_CON(11), 13, GFLAGS),
433
+
GATE(PCLK_I2C0, "pclk_i2c0", "pclk_lsperi_root", 0,
434
+
RK3506_CLKGATE_CON(11), 14, GFLAGS),
435
+
COMPOSITE(CLK_I2C0, "clk_i2c0", xin24m_g_gpll_v0pll_v1pll_div_parents_p, 0,
436
+
RK3506_CLKSEL_CON(32), 4, 2, MFLAGS, 0, 4, DFLAGS,
437
+
RK3506_CLKGATE_CON(11), 15, GFLAGS),
438
+
GATE(PCLK_I2C1, "pclk_i2c1", "pclk_lsperi_root", 0,
439
+
RK3506_CLKGATE_CON(12), 0, GFLAGS),
440
+
COMPOSITE(CLK_I2C1, "clk_i2c1", xin24m_g_gpll_v0pll_v1pll_div_parents_p, 0,
441
+
RK3506_CLKSEL_CON(32), 10, 2, MFLAGS, 6, 4, DFLAGS,
442
+
RK3506_CLKGATE_CON(12), 1, GFLAGS),
443
+
GATE(PCLK_I2C2, "pclk_i2c2", "pclk_lsperi_root", 0,
444
+
RK3506_CLKGATE_CON(12), 2, GFLAGS),
445
+
COMPOSITE(CLK_I2C2, "clk_i2c2", xin24m_g_gpll_v0pll_v1pll_div_parents_p, 0,
446
+
RK3506_CLKSEL_CON(33), 4, 2, MFLAGS, 0, 4, DFLAGS,
447
+
RK3506_CLKGATE_CON(12), 3, GFLAGS),
448
+
GATE(PCLK_PWM1, "pclk_pwm1", "pclk_lsperi_root", 0,
449
+
RK3506_CLKGATE_CON(12), 4, GFLAGS),
450
+
COMPOSITE(CLK_PWM1, "clk_pwm1", gpll_v0pll_v1pll_div_parents_p, 0,
451
+
RK3506_CLKSEL_CON(33), 10, 2, MFLAGS, 6, 4, DFLAGS,
452
+
RK3506_CLKGATE_CON(12), 5, GFLAGS),
453
+
GATE(CLK_OSC_PWM1, "clk_osc_pwm1", "xin24m", 0,
454
+
RK3506_CLKGATE_CON(12), 6, GFLAGS),
455
+
GATE(CLK_RC_PWM1, "clk_rc_pwm1", "clk_rc", 0,
456
+
RK3506_CLKGATE_CON(12), 7, GFLAGS),
457
+
COMPOSITE_NODIV(CLK_FREQ_PWM1, "clk_freq_pwm1", clk_pwm_parents_p, 0,
458
+
RK3506_CLKSEL_CON(33), 12, 4, MFLAGS,
459
+
RK3506_CLKGATE_CON(12), 8, GFLAGS),
460
+
COMPOSITE_NODIV(CLK_COUNTER_PWM1, "clk_counter_pwm1", clk_pwm_parents_p, 0,
461
+
RK3506_CLKSEL_CON(34), 0, 4, MFLAGS,
462
+
RK3506_CLKGATE_CON(12), 9, GFLAGS),
463
+
GATE(PCLK_SPI0, "pclk_spi0", "pclk_lsperi_root", 0,
464
+
RK3506_CLKGATE_CON(12), 10, GFLAGS),
465
+
COMPOSITE(CLK_SPI0, "clk_spi0", xin24m_g_gpll_v0pll_v1pll_div_parents_p, 0,
466
+
RK3506_CLKSEL_CON(34), 8, 2, MFLAGS, 4, 4, DFLAGS,
467
+
RK3506_CLKGATE_CON(12), 11, GFLAGS),
468
+
GATE(PCLK_SPI1, "pclk_spi1", "pclk_lsperi_root", 0,
469
+
RK3506_CLKGATE_CON(12), 12, GFLAGS),
470
+
COMPOSITE(CLK_SPI1, "clk_spi1", xin24m_g_gpll_v0pll_v1pll_div_parents_p, 0,
471
+
RK3506_CLKSEL_CON(34), 14, 2, MFLAGS, 10, 4, DFLAGS,
472
+
RK3506_CLKGATE_CON(12), 13, GFLAGS),
473
+
GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_lsperi_root", 0,
474
+
RK3506_CLKGATE_CON(12), 14, GFLAGS),
475
+
COMPOSITE_NODIV(DBCLK_GPIO2, "dbclk_gpio2", xin24m_400k_32k_parents_p, 0,
476
+
RK3506_CLKSEL_CON(35), 0, 2, MFLAGS,
477
+
RK3506_CLKGATE_CON(12), 15, GFLAGS),
478
+
GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_lsperi_root", 0,
479
+
RK3506_CLKGATE_CON(13), 0, GFLAGS),
480
+
COMPOSITE_NODIV(DBCLK_GPIO3, "dbclk_gpio3", xin24m_400k_32k_parents_p, 0,
481
+
RK3506_CLKSEL_CON(35), 2, 2, MFLAGS,
482
+
RK3506_CLKGATE_CON(13), 1, GFLAGS),
483
+
GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_lsperi_root", 0,
484
+
RK3506_CLKGATE_CON(13), 2, GFLAGS),
485
+
COMPOSITE_NODIV(DBCLK_GPIO4, "dbclk_gpio4", xin24m_400k_32k_parents_p, 0,
486
+
RK3506_CLKSEL_CON(35), 4, 2, MFLAGS,
487
+
RK3506_CLKGATE_CON(13), 3, GFLAGS),
488
+
GATE(HCLK_CAN0, "hclk_can0", "hclk_lsperi_root", 0,
489
+
RK3506_CLKGATE_CON(13), 4, GFLAGS),
490
+
COMPOSITE(CLK_CAN0, "clk_can0", clk_can_parents_p, 0,
491
+
RK3506_CLKSEL_CON(35), 11, 3, MFLAGS, 6, 5, DFLAGS,
492
+
RK3506_CLKGATE_CON(13), 5, GFLAGS),
493
+
GATE(HCLK_CAN1, "hclk_can1", "hclk_lsperi_root", 0,
494
+
RK3506_CLKGATE_CON(13), 6, GFLAGS),
495
+
COMPOSITE(CLK_CAN1, "clk_can1", clk_can_parents_p, 0,
496
+
RK3506_CLKSEL_CON(36), 5, 3, MFLAGS, 0, 5, DFLAGS,
497
+
RK3506_CLKGATE_CON(13), 7, GFLAGS),
498
+
GATE(HCLK_PDM, "hclk_pdm", "hclk_lsperi_root", 0,
499
+
RK3506_CLKGATE_CON(13), 8, GFLAGS),
500
+
COMPOSITE(MCLK_PDM, "mclk_pdm", clk_pdm_parents_p, 0,
501
+
RK3506_CLKSEL_CON(37), 5, 4, MFLAGS, 0, 5, DFLAGS,
502
+
RK3506_CLKGATE_CON(13), 9, GFLAGS),
503
+
COMPOSITE(CLKOUT_PDM, "clkout_pdm", clk_pdm_parents_p, 0,
504
+
RK3506_CLKSEL_CON(38), 10, 4, MFLAGS, 0, 10, DFLAGS,
505
+
RK3506_CLKGATE_CON(13), 10, GFLAGS),
506
+
COMPOSITE(MCLK_SPDIFTX, "mclk_spdiftx", mclk_sai_asrc_parents_p, 0,
507
+
RK3506_CLKSEL_CON(39), 5, 4, MFLAGS, 0, 5, DFLAGS,
508
+
RK3506_CLKGATE_CON(13), 11, GFLAGS),
509
+
GATE(HCLK_SPDIFTX, "hclk_spdiftx", "hclk_lsperi_root", 0,
510
+
RK3506_CLKGATE_CON(13), 12, GFLAGS),
511
+
GATE(HCLK_SPDIFRX, "hclk_spdifrx", "hclk_lsperi_root", 0,
512
+
RK3506_CLKGATE_CON(13), 13, GFLAGS),
513
+
COMPOSITE(MCLK_SPDIFRX, "mclk_spdifrx", gpll_v0pll_v1pll_g_parents_p, 0,
514
+
RK3506_CLKSEL_CON(39), 14, 2, MFLAGS, 9, 5, DFLAGS,
515
+
RK3506_CLKGATE_CON(13), 14, GFLAGS),
516
+
COMPOSITE(MCLK_SAI0, "mclk_sai0", mclk_sai_asrc_parents_p, 0,
517
+
RK3506_CLKSEL_CON(40), 8, 4, MFLAGS, 0, 8, DFLAGS,
518
+
RK3506_CLKGATE_CON(13), 15, GFLAGS),
519
+
GATE(HCLK_SAI0, "hclk_sai0", "hclk_lsperi_root", 0,
520
+
RK3506_CLKGATE_CON(14), 0, GFLAGS),
521
+
GATE(MCLK_OUT_SAI0, "mclk_out_sai0", "mclk_sai0", 0,
522
+
RK3506_CLKGATE_CON(14), 1, GFLAGS),
523
+
COMPOSITE(MCLK_SAI1, "mclk_sai1", mclk_sai_asrc_parents_p, 0,
524
+
RK3506_CLKSEL_CON(41), 8, 4, MFLAGS, 0, 8, DFLAGS,
525
+
RK3506_CLKGATE_CON(14), 2, GFLAGS),
526
+
GATE(HCLK_SAI1, "hclk_sai1", "hclk_lsperi_root", 0,
527
+
RK3506_CLKGATE_CON(14), 3, GFLAGS),
528
+
GATE(MCLK_OUT_SAI1, "mclk_out_sai1", "mclk_sai1", 0,
529
+
RK3506_CLKGATE_CON(14), 4, GFLAGS),
530
+
GATE(HCLK_ASRC0, "hclk_asrc0", "hclk_lsperi_root", 0,
531
+
RK3506_CLKGATE_CON(14), 5, GFLAGS),
532
+
COMPOSITE(CLK_ASRC0, "clk_asrc0", gpll_v0pll_v1pll_g_parents_p, 0,
533
+
RK3506_CLKSEL_CON(42), 5, 2, MFLAGS, 0, 5, DFLAGS,
534
+
RK3506_CLKGATE_CON(14), 6, GFLAGS),
535
+
GATE(HCLK_ASRC1, "hclk_asrc1", "hclk_lsperi_root", 0,
536
+
RK3506_CLKGATE_CON(14), 7, GFLAGS),
537
+
COMPOSITE(CLK_ASRC1, "clk_asrc1", gpll_v0pll_v1pll_g_parents_p, 0,
538
+
RK3506_CLKSEL_CON(42), 12, 2, MFLAGS, 7, 5, DFLAGS,
539
+
RK3506_CLKGATE_CON(14), 8, GFLAGS),
540
+
GATE(PCLK_CRU, "pclk_cru", "pclk_lsperi_root", CLK_IS_CRITICAL,
541
+
RK3506_CLKGATE_CON(14), 9, GFLAGS),
542
+
GATE(PCLK_PMU_ROOT, "pclk_pmu_root", "pclk_lsperi_root", CLK_IS_CRITICAL,
543
+
RK3506_CLKGATE_CON(14), 10, GFLAGS),
544
+
COMPOSITE_NODIV(MCLK_ASRC0, "mclk_asrc0", mclk_sai_asrc_parents_p, 0,
545
+
RK3506_CLKSEL_CON(46), 0, 4, MFLAGS,
546
+
RK3506_CLKGATE_CON(16), 0, GFLAGS),
547
+
COMPOSITE_NODIV(MCLK_ASRC1, "mclk_asrc1", mclk_sai_asrc_parents_p, 0,
548
+
RK3506_CLKSEL_CON(46), 4, 4, MFLAGS,
549
+
RK3506_CLKGATE_CON(16), 1, GFLAGS),
550
+
COMPOSITE_NODIV(MCLK_ASRC2, "mclk_asrc2", mclk_sai_asrc_parents_p, 0,
551
+
RK3506_CLKSEL_CON(46), 8, 4, MFLAGS,
552
+
RK3506_CLKGATE_CON(16), 2, GFLAGS),
553
+
COMPOSITE_NODIV(MCLK_ASRC3, "mclk_asrc3", mclk_sai_asrc_parents_p, 0,
554
+
RK3506_CLKSEL_CON(46), 12, 4, MFLAGS,
555
+
RK3506_CLKGATE_CON(16), 3, GFLAGS),
556
+
COMPOSITE_NODIV(LRCK_ASRC0_SRC, "lrck_asrc0_src", lrck_asrc_parents_p, 0,
557
+
RK3506_CLKSEL_CON(47), 0, 4, MFLAGS,
558
+
RK3506_CLKGATE_CON(16), 4, GFLAGS),
559
+
COMPOSITE_NODIV(LRCK_ASRC0_DST, "lrck_asrc0_dst", lrck_asrc_parents_p, 0,
560
+
RK3506_CLKSEL_CON(47), 4, 4, MFLAGS,
561
+
RK3506_CLKGATE_CON(16), 5, GFLAGS),
562
+
COMPOSITE_NODIV(LRCK_ASRC1_SRC, "lrck_asrc1_src", lrck_asrc_parents_p, 0,
563
+
RK3506_CLKSEL_CON(47), 8, 4, MFLAGS,
564
+
RK3506_CLKGATE_CON(16), 6, GFLAGS),
565
+
COMPOSITE_NODIV(LRCK_ASRC1_DST, "lrck_asrc1_dst", lrck_asrc_parents_p, 0,
566
+
RK3506_CLKSEL_CON(47), 12, 4, MFLAGS,
567
+
RK3506_CLKGATE_CON(16), 7, GFLAGS),
568
+
569
+
/* hs peri */
570
+
COMPOSITE(ACLK_HSPERI_ROOT, "aclk_hsperi_root", gpll_v0pll_v1pll_div_parents_p, CLK_IS_CRITICAL,
571
+
RK3506_CLKSEL_CON(49), 5, 2, MFLAGS, 0, 5, DFLAGS,
572
+
RK3506_CLKGATE_CON(17), 0, GFLAGS),
573
+
GATE(HCLK_HSPERI_ROOT, "hclk_hsperi_root", "aclk_hsperi_root", CLK_IS_CRITICAL,
574
+
RK3506_CLKGATE_CON(17), 1, GFLAGS),
575
+
GATE(PCLK_HSPERI_ROOT, "pclk_hsperi_root", "hclk_hsperi_root", CLK_IS_CRITICAL,
576
+
RK3506_CLKGATE_CON(17), 2, GFLAGS),
577
+
COMPOSITE(CCLK_SRC_SDMMC, "cclk_src_sdmmc", cclk_src_sdmmc_parents_p, 0,
578
+
RK3506_CLKSEL_CON(49), 13, 2, MFLAGS, 7, 6, DFLAGS,
579
+
RK3506_CLKGATE_CON(17), 6, GFLAGS),
580
+
GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_hsperi_root", 0,
581
+
RK3506_CLKGATE_CON(17), 7, GFLAGS),
582
+
GATE(HCLK_FSPI, "hclk_fspi", "hclk_hsperi_root", 0,
583
+
RK3506_CLKGATE_CON(17), 8, GFLAGS),
584
+
COMPOSITE(SCLK_FSPI, "sclk_fspi", xin24m_g_gpll_v0pll_v1pll_g_parents_p, 0,
585
+
RK3506_CLKSEL_CON(50), 5, 2, MFLAGS, 0, 5, DFLAGS,
586
+
RK3506_CLKGATE_CON(17), 9, GFLAGS),
587
+
GATE(PCLK_SPI2, "pclk_spi2", "pclk_hsperi_root", 0,
588
+
RK3506_CLKGATE_CON(17), 10, GFLAGS),
589
+
GATE(ACLK_MAC0, "aclk_mac0", "aclk_hsperi_root", 0,
590
+
RK3506_CLKGATE_CON(17), 11, GFLAGS),
591
+
GATE(ACLK_MAC1, "aclk_mac1", "aclk_hsperi_root", 0,
592
+
RK3506_CLKGATE_CON(17), 12, GFLAGS),
593
+
GATE(PCLK_MAC0, "pclk_mac0", "pclk_hsperi_root", 0,
594
+
RK3506_CLKGATE_CON(17), 13, GFLAGS),
595
+
GATE(PCLK_MAC1, "pclk_mac1", "pclk_hsperi_root", 0,
596
+
RK3506_CLKGATE_CON(17), 14, GFLAGS),
597
+
COMPOSITE_NOMUX(CLK_MAC_ROOT, "clk_mac_root", "gpll", 0,
598
+
RK3506_CLKSEL_CON(50), 7, 5, DFLAGS,
599
+
RK3506_CLKGATE_CON(17), 15, GFLAGS),
600
+
GATE(CLK_MAC0, "clk_mac0", "clk_mac_root", 0,
601
+
RK3506_CLKGATE_CON(18), 0, GFLAGS),
602
+
GATE(CLK_MAC1, "clk_mac1", "clk_mac_root", 0,
603
+
RK3506_CLKGATE_CON(18), 1, GFLAGS),
604
+
COMPOSITE(MCLK_SAI2, "mclk_sai2", mclk_sai_asrc_parents_p, 0,
605
+
RK3506_CLKSEL_CON(51), 8, 4, MFLAGS, 0, 8, DFLAGS,
606
+
RK3506_CLKGATE_CON(18), 2, GFLAGS),
607
+
GATE(HCLK_SAI2, "hclk_sai2", "hclk_hsperi_root", 0,
608
+
RK3506_CLKGATE_CON(18), 3, GFLAGS),
609
+
GATE(MCLK_OUT_SAI2, "mclk_out_sai2", "mclk_sai2", 0,
610
+
RK3506_CLKGATE_CON(18), 4, GFLAGS),
611
+
COMPOSITE(MCLK_SAI3_SRC, "mclk_sai3_src", mclk_sai_asrc_parents_p, 0,
612
+
RK3506_CLKSEL_CON(52), 8, 4, MFLAGS, 0, 8, DFLAGS,
613
+
RK3506_CLKGATE_CON(18), 5, GFLAGS),
614
+
GATE(HCLK_SAI3, "hclk_sai3", "hclk_hsperi_root", 0,
615
+
RK3506_CLKGATE_CON(18), 6, GFLAGS),
616
+
GATE(MCLK_SAI3, "mclk_sai3", "mclk_sai3_src", 0,
617
+
RK3506_CLKGATE_CON(18), 7, GFLAGS),
618
+
GATE(MCLK_OUT_SAI3, "mclk_out_sai3", "mclk_sai3_src", 0,
619
+
RK3506_CLKGATE_CON(18), 8, GFLAGS),
620
+
COMPOSITE(MCLK_SAI4_SRC, "mclk_sai4_src", mclk_sai_asrc_parents_p, 0,
621
+
RK3506_CLKSEL_CON(53), 8, 4, MFLAGS, 0, 8, DFLAGS,
622
+
RK3506_CLKGATE_CON(18), 9, GFLAGS),
623
+
GATE(HCLK_SAI4, "hclk_sai4", "hclk_hsperi_root", 0,
624
+
RK3506_CLKGATE_CON(18), 10, GFLAGS),
625
+
GATE(MCLK_SAI4, "mclk_sai4", "mclk_sai4_src", 0,
626
+
RK3506_CLKGATE_CON(18), 11, GFLAGS),
627
+
GATE(HCLK_DSM, "hclk_dsm", "hclk_hsperi_root", 0,
628
+
RK3506_CLKGATE_CON(18), 12, GFLAGS),
629
+
GATE(MCLK_DSM, "mclk_dsm", "mclk_sai3_src", 0,
630
+
RK3506_CLKGATE_CON(18), 13, GFLAGS),
631
+
GATE(PCLK_AUDIO_ADC, "pclk_audio_adc", "pclk_hsperi_root", 0,
632
+
RK3506_CLKGATE_CON(18), 14, GFLAGS),
633
+
GATE(MCLK_AUDIO_ADC, "mclk_audio_adc", "mclk_sai4_src", 0,
634
+
RK3506_CLKGATE_CON(18), 15, GFLAGS),
635
+
FACTOR(MCLK_AUDIO_ADC_DIV4, "mclk_audio_adc_div4", "mclk_audio_adc", 0, 1, 4),
636
+
GATE(PCLK_SARADC, "pclk_saradc", "pclk_hsperi_root", 0,
637
+
RK3506_CLKGATE_CON(19), 0, GFLAGS),
638
+
COMPOSITE(CLK_SARADC, "clk_saradc", xin24m_400k_32k_parents_p, 0,
639
+
RK3506_CLKSEL_CON(54), 4, 2, MFLAGS, 0, 4, DFLAGS,
640
+
RK3506_CLKGATE_CON(19), 1, GFLAGS),
641
+
GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_hsperi_root", 0,
642
+
RK3506_CLKGATE_CON(19), 3, GFLAGS),
643
+
GATE(CLK_SBPI_OTPC_NS, "clk_sbpi_otpc_ns", "xin24m_gate", 0,
644
+
RK3506_CLKGATE_CON(19), 4, GFLAGS),
645
+
FACTOR(CLK_USER_OTPC_NS, "clk_user_otpc_ns", "clk_sbpi_otpc_ns", 0, 1, 2),
646
+
GATE(PCLK_UART5, "pclk_uart5", "pclk_hsperi_root", 0,
647
+
RK3506_CLKGATE_CON(19), 6, GFLAGS),
648
+
COMPOSITE(SCLK_UART5, "sclk_uart5", sclk_uart_parents_p, 0,
649
+
RK3506_CLKSEL_CON(54), 11, 3, MFLAGS, 6, 5, DFLAGS,
650
+
RK3506_CLKGATE_CON(19), 7, GFLAGS),
651
+
GATE(PCLK_GPIO234_IOC, "pclk_gpio234_ioc", "pclk_hsperi_root", CLK_IS_CRITICAL,
652
+
RK3506_CLKGATE_CON(19), 8, GFLAGS),
653
+
COMPOSITE(CLK_MAC_PTP_ROOT, "clk_mac_ptp_root", clk_mac_ptp_root_parents_p, 0,
654
+
RK3506_CLKSEL_CON(55), 5, 2, MFLAGS, 0, 5, DFLAGS,
655
+
RK3506_CLKGATE_CON(19), 9, GFLAGS),
656
+
GATE(CLK_MAC0_PTP, "clk_mac0_ptp", "clk_mac_ptp_root", 0,
657
+
RK3506_CLKGATE_CON(19), 10, GFLAGS),
658
+
GATE(CLK_MAC1_PTP, "clk_mac1_ptp", "clk_mac_ptp_root", 0,
659
+
RK3506_CLKGATE_CON(19), 11, GFLAGS),
660
+
COMPOSITE(ACLK_VIO_ROOT, "aclk_vio_root", gpll_v0pll_v1pll_g_parents_p, 0,
661
+
RK3506_CLKSEL_CON(58), 5, 2, MFLAGS, 0, 5, DFLAGS,
662
+
RK3506_CLKGATE_CON(21), 0, GFLAGS),
663
+
COMPOSITE(HCLK_VIO_ROOT, "hclk_vio_root", gpll_v0pll_v1pll_div_parents_p, 0,
664
+
RK3506_CLKSEL_CON(58), 12, 2, MFLAGS, 7, 5, DFLAGS,
665
+
RK3506_CLKGATE_CON(21), 1, GFLAGS),
666
+
GATE(PCLK_VIO_ROOT, "pclk_vio_root", "hclk_vio_root", 0,
667
+
RK3506_CLKGATE_CON(21), 2, GFLAGS),
668
+
GATE(HCLK_RGA, "hclk_rga", "hclk_vio_root", 0,
669
+
RK3506_CLKGATE_CON(21), 6, GFLAGS),
670
+
GATE(ACLK_RGA, "aclk_rga", "aclk_vio_root", 0,
671
+
RK3506_CLKGATE_CON(21), 7, GFLAGS),
672
+
COMPOSITE(CLK_CORE_RGA, "clk_core_rga", gpll_v0pll_v1pll_g_parents_p, 0,
673
+
RK3506_CLKSEL_CON(59), 5, 2, MFLAGS, 0, 5, DFLAGS,
674
+
RK3506_CLKGATE_CON(21), 8, GFLAGS),
675
+
GATE(ACLK_VOP, "aclk_vop", "aclk_vio_root", 0,
676
+
RK3506_CLKGATE_CON(21), 9, GFLAGS),
677
+
GATE(HCLK_VOP, "hclk_vop", "hclk_vio_root", 0,
678
+
RK3506_CLKGATE_CON(21), 10, GFLAGS),
679
+
COMPOSITE(DCLK_VOP, "dclk_vop", dclk_vop_parents_p, 0,
680
+
RK3506_CLKSEL_CON(60), 8, 3, MFLAGS, 0, 8, DFLAGS,
681
+
RK3506_CLKGATE_CON(21), 11, GFLAGS),
682
+
GATE(PCLK_DPHY, "pclk_dphy", "pclk_vio_root", 0,
683
+
RK3506_CLKGATE_CON(21), 12, GFLAGS),
684
+
GATE(PCLK_DSI_HOST, "pclk_dsi_host", "pclk_vio_root", 0,
685
+
RK3506_CLKGATE_CON(21), 13, GFLAGS),
686
+
GATE(PCLK_TSADC, "pclk_tsadc", "pclk_vio_root", 0,
687
+
RK3506_CLKGATE_CON(21), 14, GFLAGS),
688
+
COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "xin24m_gate", 0,
689
+
RK3506_CLKSEL_CON(61), 0, 8, DFLAGS,
690
+
RK3506_CLKGATE_CON(21), 15, GFLAGS),
691
+
COMPOSITE_NOMUX(CLK_TSADC_TSEN, "clk_tsadc_tsen", "xin24m_gate", 0,
692
+
RK3506_CLKSEL_CON(61), 8, 3, DFLAGS,
693
+
RK3506_CLKGATE_CON(22), 0, GFLAGS),
694
+
GATE(PCLK_GPIO1_IOC, "pclk_gpio1_ioc", "pclk_vio_root", CLK_IS_CRITICAL,
695
+
RK3506_CLKGATE_CON(22), 1, GFLAGS),
696
+
697
+
/* pmu */
698
+
GATE(CLK_PMU, "clk_pmu", "xin24m", CLK_IGNORE_UNUSED,
699
+
RK3506_PMU_CLKGATE_CON(0), 1, GFLAGS),
700
+
GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_root", CLK_IGNORE_UNUSED,
701
+
RK3506_PMU_CLKGATE_CON(0), 2, GFLAGS),
702
+
GATE(PCLK_PMU_CRU, "pclk_pmu_cru", "pclk_pmu_root", CLK_IGNORE_UNUSED,
703
+
RK3506_PMU_CLKGATE_CON(0), 4, GFLAGS),
704
+
GATE(PCLK_PMU_GRF, "pclk_pmu_grf", "pclk_pmu_root", CLK_IGNORE_UNUSED,
705
+
RK3506_PMU_CLKGATE_CON(0), 5, GFLAGS),
706
+
GATE(PCLK_GPIO0_IOC, "pclk_gpio0_ioc", "pclk_pmu_root", CLK_IS_CRITICAL,
707
+
RK3506_PMU_CLKGATE_CON(0), 7, GFLAGS),
708
+
GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pmu_root", 0,
709
+
RK3506_PMU_CLKGATE_CON(0), 8, GFLAGS),
710
+
COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", dbclk_gpio0_parents_p, 0,
711
+
RK3506_PMU_CLKSEL_CON(0), 0, 2, MFLAGS,
712
+
RK3506_PMU_CLKGATE_CON(0), 9, GFLAGS),
713
+
GATE(PCLK_GPIO1_SHADOW, "pclk_gpio1_shadow", "pclk_pmu_root", 0,
714
+
RK3506_PMU_CLKGATE_CON(0), 10, GFLAGS),
715
+
COMPOSITE_NODIV(DBCLK_GPIO1_SHADOW, "dbclk_gpio1_shadow", dbclk_gpio0_parents_p, 0,
716
+
RK3506_PMU_CLKSEL_CON(0), 2, 2, MFLAGS,
717
+
RK3506_PMU_CLKGATE_CON(0), 11, GFLAGS),
718
+
GATE(PCLK_PMU_HP_TIMER, "pclk_pmu_hp_timer", "pclk_pmu_root", CLK_IGNORE_UNUSED,
719
+
RK3506_PMU_CLKGATE_CON(0), 12, GFLAGS),
720
+
MUX(CLK_PMU_HP_TIMER, "clk_pmu_hp_timer", clk_pmu_hp_timer_parents_p, CLK_IGNORE_UNUSED,
721
+
RK3506_PMU_CLKSEL_CON(0), 4, 2, MFLAGS),
722
+
GATE(PCLK_PWM0, "pclk_pwm0", "pclk_pmu_root", 0,
723
+
RK3506_PMU_CLKGATE_CON(0), 15, GFLAGS),
724
+
COMPOSITE_NOMUX(CLK_PWM0, "clk_pwm0", "clk_gpll_div_100m", 0,
725
+
RK3506_PMU_CLKSEL_CON(0), 6, 4, DFLAGS,
726
+
RK3506_PMU_CLKGATE_CON(1), 0, GFLAGS),
727
+
GATE(CLK_OSC_PWM0, "clk_osc_pwm0", "xin24m", 0,
728
+
RK3506_PMU_CLKGATE_CON(1), 1, GFLAGS),
729
+
GATE(CLK_RC_PWM0, "clk_rc_pwm0", "clk_rc", 0,
730
+
RK3506_PMU_CLKGATE_CON(1), 2, GFLAGS),
731
+
COMPOSITE_NOMUX(CLK_MAC_OUT, "clk_mac_out", "gpll", 0,
732
+
RK3506_PMU_CLKSEL_CON(0), 10, 6, DFLAGS,
733
+
RK3506_PMU_CLKGATE_CON(1), 3, GFLAGS),
734
+
COMPOSITE(CLK_REF_OUT0, "clk_ref_out0", clk_ref_out_parents_p, 0,
735
+
RK3506_PMU_CLKSEL_CON(1), 6, 2, MFLAGS, 0, 6, DFLAGS,
736
+
RK3506_PMU_CLKGATE_CON(1), 4, GFLAGS),
737
+
COMPOSITE(CLK_REF_OUT1, "clk_ref_out1", clk_ref_out_parents_p, 0,
738
+
RK3506_PMU_CLKSEL_CON(1), 14, 2, MFLAGS, 8, 6, DFLAGS,
739
+
RK3506_PMU_CLKGATE_CON(1), 5, GFLAGS),
740
+
MUX(CLK_32K_FRAC_MUX, "clk_32k_frac_mux", clk_32k_frac_parents_p, 0,
741
+
RK3506_PMU_CLKSEL_CON(3), 0, 2, MFLAGS),
742
+
COMPOSITE_FRAC(CLK_32K_FRAC, "clk_32k_frac", "clk_32k_frac_mux", 0,
743
+
RK3506_PMU_CLKSEL_CON(2), 0,
744
+
RK3506_PMU_CLKGATE_CON(1), 6, GFLAGS),
745
+
COMPOSITE_NOMUX(CLK_32K_RC, "clk_32k_rc", "clk_rc", CLK_IS_CRITICAL,
746
+
RK3506_PMU_CLKSEL_CON(3), 2, 5, DFLAGS,
747
+
RK3506_PMU_CLKGATE_CON(1), 7, GFLAGS),
748
+
COMPOSITE_NODIV(CLK_32K, "clk_32k", clk_32k_parents_p, CLK_IS_CRITICAL,
749
+
RK3506_PMU_CLKSEL_CON(3), 7, 2, MFLAGS,
750
+
RK3506_PMU_CLKGATE_CON(1), 8, GFLAGS),
751
+
COMPOSITE_NODIV(CLK_32K_PMU, "clk_32k_pmu", clk_32k_parents_p, CLK_IS_CRITICAL,
752
+
RK3506_PMU_CLKSEL_CON(3), 9, 2, MFLAGS,
753
+
RK3506_PMU_CLKGATE_CON(1), 9, GFLAGS),
754
+
GATE(CLK_PMU_32K, "clk_pmu_32k", "clk_32k_pmu", CLK_IGNORE_UNUSED,
755
+
RK3506_PMU_CLKGATE_CON(0), 3, GFLAGS),
756
+
GATE(CLK_PMU_HP_TIMER_32K, "clk_pmu_hp_timer_32k", "clk_32k_pmu", CLK_IGNORE_UNUSED,
757
+
RK3506_PMU_CLKGATE_CON(0), 14, GFLAGS),
758
+
GATE(PCLK_TOUCH_KEY, "pclk_touch_key", "pclk_pmu_root", CLK_IGNORE_UNUSED,
759
+
RK3506_PMU_CLKGATE_CON(1), 12, GFLAGS),
760
+
GATE(CLK_TOUCH_KEY, "clk_touch_key", "xin24m", CLK_IGNORE_UNUSED,
761
+
RK3506_PMU_CLKGATE_CON(1), 13, GFLAGS),
762
+
COMPOSITE(CLK_REF_PHY_PLL, "clk_ref_phy_pll", gpll_v0pll_v1pll_parents_p, 0,
763
+
RK3506_PMU_CLKSEL_CON(4), 13, 2, MFLAGS, 6, 7, DFLAGS,
764
+
RK3506_PMU_CLKGATE_CON(1), 14, GFLAGS),
765
+
MUX(CLK_REF_PHY_PMU_MUX, "clk_ref_phy_pmu_mux", clk_ref_phy_pmu_mux_parents_p, 0,
766
+
RK3506_PMU_CLKSEL_CON(4), 15, 1, MFLAGS),
767
+
GATE(CLK_WIFI_OUT, "clk_wifi_out", "xin24m", 0,
768
+
RK3506_PMU_CLKGATE_CON(2), 0, GFLAGS),
769
+
MUX(CLK_V0PLL_REF, "clk_v0pll_ref", clk_vpll_ref_parents_p, CLK_IGNORE_UNUSED,
770
+
RK3506_PMU_CLKSEL_CON(6), 0, 1, MFLAGS),
771
+
MUX(CLK_V1PLL_REF, "clk_v1pll_ref", clk_vpll_ref_parents_p, CLK_IGNORE_UNUSED,
772
+
RK3506_PMU_CLKSEL_CON(6), 1, 1, MFLAGS),
773
+
774
+
/* secure ns */
775
+
GATE(CLK_CORE_CRYPTO_NS, "clk_core_crypto_ns", "clk_core_crypto", 0,
776
+
RK3506_CLKGATE_CON(5), 12, GFLAGS),
777
+
GATE(CLK_PKA_CRYPTO_NS, "clk_pka_crypto_ns", "clk_pka_crypto", 0,
778
+
RK3506_CLKGATE_CON(5), 13, GFLAGS),
779
+
780
+
/* io */
781
+
GATE(CLK_SPI2, "clk_spi2", "clk_spi2_io", 0,
782
+
RK3506_CLKGATE_CON(20), 0, GFLAGS),
783
+
};
784
+
785
+
static void __init rk3506_clk_init(struct device_node *np)
786
+
{
787
+
struct rockchip_clk_provider *ctx;
788
+
unsigned long clk_nr_clks;
789
+
void __iomem *reg_base;
790
+
791
+
clk_nr_clks = rockchip_clk_find_max_clk_id(rk3506_clk_branches,
792
+
ARRAY_SIZE(rk3506_clk_branches)) + 1;
793
+
794
+
reg_base = of_iomap(np, 0);
795
+
if (!reg_base) {
796
+
pr_err("%s: could not map cru region\n", __func__);
797
+
return;
798
+
}
799
+
800
+
ctx = rockchip_clk_init(np, reg_base, clk_nr_clks);
801
+
if (IS_ERR(ctx)) {
802
+
pr_err("%s: rockchip clk init failed\n", __func__);
803
+
iounmap(reg_base);
804
+
return;
805
+
}
806
+
807
+
rockchip_clk_register_plls(ctx, rk3506_pll_clks,
808
+
ARRAY_SIZE(rk3506_pll_clks),
809
+
0);
810
+
811
+
rockchip_clk_register_armclk_multi_pll(ctx, &rk3506_armclk,
812
+
rk3506_cpuclk_rates,
813
+
ARRAY_SIZE(rk3506_cpuclk_rates));
814
+
815
+
rockchip_clk_register_branches(ctx, rk3506_clk_branches,
816
+
ARRAY_SIZE(rk3506_clk_branches));
817
+
818
+
rk3506_rst_init(np, reg_base);
819
+
820
+
rockchip_register_restart_notifier(ctx, RK3506_GLB_SRST_FST, NULL);
821
+
822
+
rockchip_clk_of_add_provider(np, ctx);
823
+
824
+
/* pvtpll src init */
825
+
writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RK3506_CLKSEL_CON(15));
826
+
}
827
+
828
+
CLK_OF_DECLARE(rk3506_cru, "rockchip,rk3506-cru", rk3506_clk_init);
829
+
830
+
struct clk_rk3506_inits {
831
+
void (*inits)(struct device_node *np);
832
+
};
833
+
834
+
static const struct clk_rk3506_inits clk_rk3506_cru_init = {
835
+
.inits = rk3506_clk_init,
836
+
};
837
+
838
+
static const struct of_device_id clk_rk3506_match_table[] = {
839
+
{
840
+
.compatible = "rockchip,rk3506-cru",
841
+
.data = &clk_rk3506_cru_init,
842
+
},
843
+
{ }
844
+
};
845
+
846
+
static int clk_rk3506_probe(struct platform_device *pdev)
847
+
{
848
+
const struct clk_rk3506_inits *init_data;
849
+
struct device *dev = &pdev->dev;
850
+
851
+
init_data = device_get_match_data(dev);
852
+
if (!init_data)
853
+
return -EINVAL;
854
+
855
+
if (init_data->inits)
856
+
init_data->inits(dev->of_node);
857
+
858
+
return 0;
859
+
}
860
+
861
+
static struct platform_driver clk_rk3506_driver = {
862
+
.probe = clk_rk3506_probe,
863
+
.driver = {
864
+
.name = "clk-rk3506",
865
+
.of_match_table = clk_rk3506_match_table,
866
+
.suppress_bind_attrs = true,
867
+
},
868
+
};
869
+
builtin_platform_driver_probe(clk_rk3506_driver, clk_rk3506_probe);
+4
-1
drivers/clk/rockchip/clk-rk3568.c
+4
-1
drivers/clk/rockchip/clk-rk3568.c
···
1652
1652
static void __init rk3568_clk_init(struct device_node *np)
1653
1653
{
1654
1654
struct rockchip_clk_provider *ctx;
1655
+
unsigned long clk_nr_clks;
1655
1656
void __iomem *reg_base;
1656
1657
1657
1658
reg_base = of_iomap(np, 0);
···
1661
1660
return;
1662
1661
}
1663
1662
1664
-
ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
1663
+
clk_nr_clks = rockchip_clk_find_max_clk_id(rk3568_clk_branches,
1664
+
ARRAY_SIZE(rk3568_clk_branches)) + 1;
1665
+
ctx = rockchip_clk_init(np, reg_base, clk_nr_clks);
1665
1666
if (IS_ERR(ctx)) {
1666
1667
pr_err("%s: rockchip clk init failed\n", __func__);
1667
1668
iounmap(reg_base);
+1117
drivers/clk/rockchip/clk-rv1126b.c
+1117
drivers/clk/rockchip/clk-rv1126b.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
4
+
* Author: Elaine Zhang <zhangqing@rock-chips.com>
5
+
*/
6
+
7
+
#include <linux/clk.h>
8
+
#include <linux/clk-provider.h>
9
+
#include <linux/module.h>
10
+
#include <linux/of.h>
11
+
#include <linux/of_address.h>
12
+
#include <linux/of_device.h>
13
+
#include <linux/platform_device.h>
14
+
#include <linux/regmap.h>
15
+
#include <linux/syscore_ops.h>
16
+
#include <dt-bindings/clock/rockchip,rv1126b-cru.h>
17
+
#include "clk.h"
18
+
19
+
#define RV1126B_FRAC_MAX_PRATE 1200000000
20
+
21
+
#define PVTPLL_SRC_SEL_PVTPLL (BIT(0) | BIT(16))
22
+
23
+
enum rv1126b_plls {
24
+
gpll, cpll, aupll, dpll
25
+
};
26
+
27
+
static struct rockchip_pll_rate_table rv1126b_pll_rates[] = {
28
+
/* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
29
+
RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0),
30
+
RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
31
+
RK3036_PLL_RATE(1179648000, 1, 49, 1, 1, 0, 2550137),
32
+
RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0),
33
+
RK3036_PLL_RATE(993484800, 1, 41, 1, 1, 0, 6630355),
34
+
RK3036_PLL_RATE(983040000, 1, 40, 1, 1, 0, 16106127),
35
+
RK3036_PLL_RATE(903168000, 1, 75, 2, 1, 0, 4429185),
36
+
{ /* sentinel */ },
37
+
};
38
+
39
+
#define RV1126B_DIV_ACLK_CORE_MASK 0x1f
40
+
#define RV1126B_DIV_ACLK_CORE_SHIFT 0
41
+
#define RV1126B_DIV_PCLK_CORE_MASK 0x1f
42
+
#define RV1126B_DIV_PCLK_CORE_SHIFT 8
43
+
#define RV1126B_CORE_SEL_MASK 0x1
44
+
#define RV1126B_CORE_SEL_SHIFT 1
45
+
46
+
#define RV1126B_CLKSEL0(_aclk_core) \
47
+
{ \
48
+
.reg = RV1126B_CORECLKSEL_CON(2), \
49
+
.val = HIWORD_UPDATE(_aclk_core - 1, RV1126B_DIV_ACLK_CORE_MASK, \
50
+
RV1126B_DIV_ACLK_CORE_SHIFT), \
51
+
}
52
+
53
+
#define RV1126B_CLKSEL1(_pclk_dbg) \
54
+
{ \
55
+
.reg = RV1126B_CORECLKSEL_CON(2), \
56
+
.val = HIWORD_UPDATE(_pclk_dbg - 1, RV1126B_DIV_PCLK_CORE_MASK, \
57
+
RV1126B_DIV_PCLK_CORE_SHIFT), \
58
+
}
59
+
60
+
#define RV1126B_CPUCLK_RATE(_prate, _aclk_core, _pclk_dbg) \
61
+
{ \
62
+
.prate = _prate, \
63
+
.divs = { \
64
+
RV1126B_CLKSEL0(_aclk_core), \
65
+
RV1126B_CLKSEL1(_pclk_dbg), \
66
+
}, \
67
+
}
68
+
69
+
static struct rockchip_cpuclk_rate_table rv1126b_cpuclk_rates[] __initdata = {
70
+
RV1126B_CPUCLK_RATE(1608000000, 4, 10),
71
+
RV1126B_CPUCLK_RATE(1512000000, 4, 10),
72
+
RV1126B_CPUCLK_RATE(1416000000, 4, 10),
73
+
RV1126B_CPUCLK_RATE(1296000000, 3, 10),
74
+
RV1126B_CPUCLK_RATE(1200000000, 3, 10),
75
+
RV1126B_CPUCLK_RATE(1188000000, 3, 8),
76
+
RV1126B_CPUCLK_RATE(1104000000, 2, 8),
77
+
RV1126B_CPUCLK_RATE(1008000000, 2, 8),
78
+
RV1126B_CPUCLK_RATE(816000000, 2, 6),
79
+
RV1126B_CPUCLK_RATE(600000000, 2, 4),
80
+
RV1126B_CPUCLK_RATE(594000000, 2, 4),
81
+
RV1126B_CPUCLK_RATE(408000000, 1, 3),
82
+
RV1126B_CPUCLK_RATE(396000000, 1, 3),
83
+
};
84
+
85
+
PNAME(mux_pll_p) = { "xin24m" };
86
+
PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" };
87
+
PNAME(mux_gpll_aupll_p) = { "gpll", "aupll" };
88
+
PNAME(mux_gpll_aupll_cpll_p) = { "gpll", "aupll", "cpll" };
89
+
PNAME(mux_gpll_cpll_24m_p) = { "gpll", "cpll", "xin24m" };
90
+
PNAME(mux_cpll_24m_p) = { "cpll", "xin24m" };
91
+
PNAME(mux_24m_gpll_aupll_cpll_p) = { "xin24m", "gpll", "aupll", "cpll" };
92
+
PNAME(mux_24m_gpll_cpll_p) = { "xin24m", "gpll", "cpll" };
93
+
PNAME(mux_24m_gpll_aupll_p) = { "xin24m", "gpll", "aupll" };
94
+
PNAME(mux_sclk_uart_src_p) = { "xin24m", "clk_cm_frac0", "clk_cm_frac1",
95
+
"clk_cm_frac2", "clk_uart_frac0", "clk_uart_frac1" };
96
+
PNAME(mclk_sai0_src_p) = { "xin24m", "clk_cm_frac0", "clk_cm_frac1",
97
+
"clk_cm_frac2", "clk_audio_frac0", "clk_audio_frac1",
98
+
"clk_audio_int0", "clk_audio_int1",
99
+
"mclk_sai0_from_io" };
100
+
PNAME(mclk_sai1_src_p) = { "xin24m", "clk_cm_frac0", "clk_cm_frac1",
101
+
"clk_cm_frac2", "clk_audio_frac0", "clk_audio_frac1",
102
+
"clk_audio_int0", "clk_audio_int1",
103
+
"mclk_sai1_from_io" };
104
+
PNAME(mclk_sai2_src_p) = { "xin24m", "clk_cm_frac0", "clk_cm_frac1",
105
+
"clk_cm_frac2", "clk_audio_frac0", "clk_audio_frac1",
106
+
"clk_audio_int0", "clk_audio_int1",
107
+
"mclk_sai2_from_io" };
108
+
PNAME(mux_sai_src_p) = { "xin24m", "clk_cm_frac0", "clk_cm_frac1",
109
+
"clk_cm_frac2", "clk_audio_frac0", "clk_audio_frac1",
110
+
"clk_audio_int0", "clk_audio_int1", "mclk_sai0_from_io",
111
+
"mclk_sai1_from_io", "mclk_sai2_from_io"};
112
+
PNAME(mux_100m_24m_p) = { "clk_cpll_div10", "xin24m" };
113
+
PNAME(mux_200m_24m_p) = { "clk_gpll_div6", "xin24m" };
114
+
PNAME(mux_500m_400m_200m_p) = { "clk_cpll_div2", "clk_gpll_div3", "clk_gpll_div6" };
115
+
PNAME(mux_300m_200m_p) = { "clk_gpll_div4", "clk_gpll_div6" };
116
+
PNAME(mux_500m_400m_300m_p) = { "clk_cpll_div2", "clk_gpll_div3", "clk_gpll_div4" };
117
+
PNAME(mux_333m_200m_p) = { "clk_cpll_div3", "clk_gpll_div6" };
118
+
PNAME(mux_600m_400m_200m_p) = { "clk_gpll_div2", "clk_gpll_div3", "clk_gpll_div6" };
119
+
PNAME(mux_400m_300m_200m_p) = { "clk_gpll_div3", "clk_gpll_div4", "clk_gpll_div6" };
120
+
PNAME(mux_200m_100m_p) = { "clk_gpll_div6", "clk_cpll_div10" };
121
+
PNAME(mux_200m_100m_50m_24m_p) = { "clk_gpll_div6", "clk_cpll_div10", "clk_cpll_div20",
122
+
"xin24m" };
123
+
PNAME(mux_600m_24m_p) = { "clk_gpll_div2", "xin24m" };
124
+
PNAME(mux_armclk_p) = { "clk_core_pll", "clk_core_pvtpll" };
125
+
PNAME(aclk_npu_root_p) = { "clk_npu_pll", "clk_npu_pvtpll" };
126
+
PNAME(clk_saradc0_p) = { "clk_saradc0_src", "clk_saradc0_rcosc_io" };
127
+
PNAME(clk_core_vepu_p) = { "clk_vepu_pll", "clk_vepu_pvtpll" };
128
+
PNAME(clk_core_fec_p) = { "clk_core_fec_src", "clk_vcp_pvtpll" };
129
+
PNAME(clk_core_aisp_p) = { "clk_aisp_pll", "clk_vcp_pvtpll" };
130
+
PNAME(clk_core_isp_root_p) = { "clk_isp_pll", "clk_isp_pvtpll" };
131
+
PNAME(clk_gmac_ptp_ref_p) = { "clk_gmac_ptp_ref_src", "clk_gmac_ptp_from_io" };
132
+
PNAME(clk_saradc1_p) = { "clk_saradc1_src", "clk_saradc1_rcosc_io" };
133
+
PNAME(clk_saradc2_p) = { "clk_saradc2_src", "clk_saradc2_rcosc_io" };
134
+
PNAME(clk_rcosc_src_p) = { "xin24m", "clk_rcosc", "clk_rcosc_div2",
135
+
"clk_rcosc_div3", "clk_rcosc_div4" };
136
+
PNAME(busclk_pmu_mux_p) = { "clk_cpll_div10", "clk_rcosc_src" };
137
+
PNAME(clk_xin_rc_div_p) = { "xin24m", "clk_rcosc_src" };
138
+
PNAME(clk_32k_p) = { "clk_xin_rc_div", "clk_32k_rtc", "clk_32k_io" };
139
+
PNAME(mux_24m_32k_p) = { "xin24m", "clk_32k" };
140
+
PNAME(mux_24m_rcosc_buspmu_p) = { "xin24m", "clk_rcosc_src", "busclk_pmu_src" };
141
+
PNAME(mux_24m_rcosc_buspmu_32k_p) = { "xin24m", "clk_rcosc_src", "busclk_pmu_src",
142
+
"clk_32k" };
143
+
PNAME(sclk_uart0_p) = { "sclk_uart0_src", "xin24m", "clk_rcosc_src" };
144
+
PNAME(clk_osc_rcosc_ctrl_p) = { "clk_rcosc_src", "clk_testout_out" };
145
+
PNAME(lrck_src_asrc_p) = { "mclk_asrc0", "mclk_asrc1", "mclk_asrc2", "mclk_asrc3",
146
+
"fs_inter_from_sai0", "fs_inter_from_sai1",
147
+
"fs_inter_from_sai2", "clkout_pdm"};
148
+
PNAME(clk_ref_pipephy_p) = { "clk_ref_pipephy_cpll_src", "xin24m" };
149
+
PNAME(clk_timer0_parents_p) = { "clk_timer_root", "mclk_sai0_from_io",
150
+
"sclk_sai0_from_io" };
151
+
PNAME(clk_timer1_parents_p) = { "clk_timer_root", "mclk_sai1_from_io",
152
+
"sclk_sai1_from_io" };
153
+
PNAME(clk_timer2_parents_p) = { "clk_timer_root", "mclk_sai2_from_io",
154
+
"sclk_sai2_from_io" };
155
+
PNAME(clk_timer3_parents_p) = { "clk_timer_root", "mclk_asrc0", "mclk_asrc1" };
156
+
PNAME(clk_timer4_parents_p) = { "clk_timer_root", "mclk_asrc2", "mclk_asrc3" };
157
+
PNAME(clk_macphy_p) = { "xin24m", "clk_cpll_div20" };
158
+
PNAME(clk_cpll_div10_p) = { "gpll", "clk_aisp_pll_src" };
159
+
160
+
static struct rockchip_pll_clock rv1126b_pll_clks[] __initdata = {
161
+
[gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
162
+
CLK_IS_CRITICAL, RV1126B_PLL_CON(8),
163
+
RV1126B_MODE_CON, 2, 10, 0, rv1126b_pll_rates),
164
+
[aupll] = PLL(pll_rk3328, PLL_AUPLL, "aupll", mux_pll_p,
165
+
CLK_IS_CRITICAL, RV1126B_PLL_CON(0),
166
+
RV1126B_MODE_CON, 0, 10, 0, rv1126b_pll_rates),
167
+
[cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
168
+
CLK_IS_CRITICAL, RV1126B_PERIPLL_CON(0),
169
+
RV1126B_MODE_CON, 4, 10, 0, rv1126b_pll_rates),
170
+
[dpll] = PLL(pll_rk3328, 0, "dpll", mux_pll_p,
171
+
CLK_IS_CRITICAL, RV1126B_SUBDDRPLL_CON(0),
172
+
RV1126B_MODE_CON, 2, 10, 0, rv1126b_pll_rates),
173
+
};
174
+
175
+
#define MFLAGS CLK_MUX_HIWORD_MASK
176
+
#define DFLAGS CLK_DIVIDER_HIWORD_MASK
177
+
#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
178
+
179
+
static struct rockchip_clk_branch rv1126b_rcdiv_pmu_fracmux __initdata =
180
+
MUX(CLK_32K, "clk_32k", clk_32k_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
181
+
RV1126B_PMUCLKSEL_CON(2), 1, 2, MFLAGS);
182
+
183
+
static struct rockchip_clk_branch rv1126b_clk_branches[] __initdata = {
184
+
185
+
FACTOR(0, "clk_rcosc_div2", "clk_rcosc", 0, 1, 2),
186
+
FACTOR(0, "clk_rcosc_div3", "clk_rcosc", 0, 1, 3),
187
+
FACTOR(0, "clk_rcosc_div4", "clk_rcosc", 0, 1, 4),
188
+
189
+
/* Clock Definition */
190
+
COMPOSITE_NODIV(CLK_AISP_PLL_SRC, "clk_aisp_pll_src", mux_gpll_aupll_cpll_p, 0,
191
+
RV1126B_CLKSEL_CON(62), 4, 2, MFLAGS,
192
+
RV1126B_CLKGATE_CON(5), 4, GFLAGS),
193
+
DIV(CLK_AISP_PLL, "clk_aisp_pll", "clk_aisp_pll_src", 0,
194
+
RV1126B_CLKSEL_CON(62), 0, 3, DFLAGS),
195
+
196
+
COMPOSITE(CLK_CPLL_DIV10, "clk_cpll_div10", clk_cpll_div10_p, 0,
197
+
RV1126B_CLKSEL_CON(1), 15, 1, MFLAGS, 5, 5, DFLAGS,
198
+
RV1126B_CLKGATE_CON(0), 1, GFLAGS),
199
+
COMPOSITE_NOMUX(CLK_CPLL_DIV20, "clk_cpll_div20", "cpll", 0,
200
+
RV1126B_CLKSEL_CON(1), 0, 5, DFLAGS,
201
+
RV1126B_CLKGATE_CON(0), 0, GFLAGS),
202
+
COMPOSITE_NOMUX(CLK_CPLL_DIV8, "clk_cpll_div8", "cpll", 0,
203
+
RV1126B_CLKSEL_CON(1), 10, 5, DFLAGS,
204
+
RV1126B_CLKGATE_CON(0), 2, GFLAGS),
205
+
COMPOSITE_NOMUX(CLK_GPLL_DIV8, "clk_gpll_div8", "gpll", 0,
206
+
RV1126B_CLKSEL_CON(2), 0, 5, DFLAGS,
207
+
RV1126B_CLKGATE_CON(0), 3, GFLAGS),
208
+
COMPOSITE_NOMUX(CLK_GPLL_DIV6, "clk_gpll_div6", "gpll", 0,
209
+
RV1126B_CLKSEL_CON(2), 5, 5, DFLAGS,
210
+
RV1126B_CLKGATE_CON(0), 4, GFLAGS),
211
+
COMPOSITE_NOMUX(CLK_GPLL_DIV4, "clk_gpll_div4", "gpll", 0,
212
+
RV1126B_CLKSEL_CON(2), 10, 5, DFLAGS,
213
+
RV1126B_CLKGATE_CON(0), 5, GFLAGS),
214
+
COMPOSITE_NOMUX(CLK_CPLL_DIV3, "clk_cpll_div3", "cpll", 0,
215
+
RV1126B_CLKSEL_CON(3), 0, 5, DFLAGS,
216
+
RV1126B_CLKGATE_CON(0), 6, GFLAGS),
217
+
COMPOSITE_NOMUX(CLK_GPLL_DIV3, "clk_gpll_div3", "gpll", 0,
218
+
RV1126B_CLKSEL_CON(3), 5, 5, DFLAGS,
219
+
RV1126B_CLKGATE_CON(0), 7, GFLAGS),
220
+
COMPOSITE_NOMUX(CLK_CPLL_DIV2, "clk_cpll_div2", "cpll", 0,
221
+
RV1126B_CLKSEL_CON(3), 10, 5, DFLAGS,
222
+
RV1126B_CLKGATE_CON(0), 8, GFLAGS),
223
+
COMPOSITE_NOMUX(CLK_GPLL_DIV2, "clk_gpll_div2", "gpll", 0,
224
+
RV1126B_CLKSEL_CON(4), 0, 5, DFLAGS,
225
+
RV1126B_CLKGATE_CON(0), 9, GFLAGS),
226
+
MUX(CLK_CM_FRAC0_SRC, "clk_cm_frac0_src", mux_24m_gpll_aupll_cpll_p, 0,
227
+
RV1126B_CLKSEL_CON(10), 0, 2, MFLAGS),
228
+
COMPOSITE_FRAC(CLK_CM_FRAC0, "clk_cm_frac0", "clk_cm_frac0_src", 0,
229
+
RV1126B_CLKSEL_CON(25), 0,
230
+
RV1126B_CLKGATE_CON(1), 0, GFLAGS),
231
+
MUX(CLK_CM_FRAC1_SRC, "clk_cm_frac1_src", mux_24m_gpll_aupll_cpll_p, 0,
232
+
RV1126B_CLKSEL_CON(10), 2, 2, MFLAGS),
233
+
COMPOSITE_FRAC(CLK_CM_FRAC1, "clk_cm_frac1", "clk_cm_frac1_src", 0,
234
+
RV1126B_CLKSEL_CON(26), 0,
235
+
RV1126B_CLKGATE_CON(1), 1, GFLAGS),
236
+
MUX(CLK_CM_FRAC2_SRC, "clk_cm_frac2_src", mux_24m_gpll_aupll_cpll_p, 0,
237
+
RV1126B_CLKSEL_CON(10), 4, 2, MFLAGS),
238
+
COMPOSITE_FRAC(CLK_CM_FRAC2, "clk_cm_frac2", "clk_cm_frac2_src", 0,
239
+
RV1126B_CLKSEL_CON(27), 0,
240
+
RV1126B_CLKGATE_CON(1), 2, GFLAGS),
241
+
MUX(CLK_UART_FRAC0_SRC, "clk_uart_frac0_src", mux_24m_gpll_cpll_p, 0,
242
+
RV1126B_CLKSEL_CON(10), 6, 2, MFLAGS),
243
+
COMPOSITE_FRAC(CLK_UART_FRAC0, "clk_uart_frac0", "clk_uart_frac0_src", 0,
244
+
RV1126B_CLKSEL_CON(28), 0,
245
+
RV1126B_CLKGATE_CON(1), 3, GFLAGS),
246
+
MUX(CLK_UART_FRAC1_SRC, "clk_uart_frac1_src", mux_24m_gpll_cpll_p, 0,
247
+
RV1126B_CLKSEL_CON(10), 8, 2, MFLAGS),
248
+
COMPOSITE_FRAC(CLK_UART_FRAC1, "clk_uart_frac1", "clk_uart_frac1_src", 0,
249
+
RV1126B_CLKSEL_CON(29), 0,
250
+
RV1126B_CLKGATE_CON(1), 4, GFLAGS),
251
+
MUX(CLK_AUDIO_FRAC0_SRC, "clk_audio_frac0_src", mux_24m_gpll_aupll_p, 0,
252
+
RV1126B_CLKSEL_CON(10), 10, 2, MFLAGS),
253
+
COMPOSITE_FRAC(CLK_AUDIO_FRAC0, "clk_audio_frac0", "clk_audio_frac0_src", 0,
254
+
RV1126B_CLKSEL_CON(30), 0,
255
+
RV1126B_CLKGATE_CON(1), 5, GFLAGS),
256
+
MUX(CLK_AUDIO_FRAC1_SRC, "clk_audio_frac1_src", mux_24m_gpll_aupll_p, 0,
257
+
RV1126B_CLKSEL_CON(10), 12, 2, MFLAGS),
258
+
COMPOSITE_FRAC(CLK_AUDIO_FRAC1, "clk_audio_frac1", "clk_audio_frac1_src", 0,
259
+
RV1126B_CLKSEL_CON(31), 0,
260
+
RV1126B_CLKGATE_CON(1), 6, GFLAGS),
261
+
COMPOSITE(CLK_AUDIO_INT0, "clk_audio_int0", mux_24m_gpll_aupll_p, 0,
262
+
RV1126B_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 5, DFLAGS,
263
+
RV1126B_CLKGATE_CON(1), 7, GFLAGS),
264
+
COMPOSITE(CLK_AUDIO_INT1, "clk_audio_int1", mux_24m_gpll_aupll_p, 0,
265
+
RV1126B_CLKSEL_CON(11), 14, 2, MFLAGS, 8, 5, DFLAGS,
266
+
RV1126B_CLKGATE_CON(1), 8, GFLAGS),
267
+
COMPOSITE(SCLK_UART0_SRC, "sclk_uart0_src", mux_sclk_uart_src_p, 0,
268
+
RV1126B_CLKSEL_CON(12), 5, 3, MFLAGS, 0, 5, DFLAGS,
269
+
RV1126B_CLKGATE_CON(1), 9, GFLAGS),
270
+
COMPOSITE(SCLK_UART1, "sclk_uart1", mux_sclk_uart_src_p, 0,
271
+
RV1126B_CLKSEL_CON(12), 13, 3, MFLAGS, 8, 5, DFLAGS,
272
+
RV1126B_CLKGATE_CON(1), 10, GFLAGS),
273
+
COMPOSITE(SCLK_UART2, "sclk_uart2", mux_sclk_uart_src_p, 0,
274
+
RV1126B_CLKSEL_CON(13), 5, 3, MFLAGS, 0, 5, DFLAGS,
275
+
RV1126B_CLKGATE_CON(1), 11, GFLAGS),
276
+
COMPOSITE(SCLK_UART3, "sclk_uart3", mux_sclk_uart_src_p, 0,
277
+
RV1126B_CLKSEL_CON(13), 13, 3, MFLAGS, 8, 5, DFLAGS,
278
+
RV1126B_CLKGATE_CON(1), 12, GFLAGS),
279
+
COMPOSITE(SCLK_UART4, "sclk_uart4", mux_sclk_uart_src_p, 0,
280
+
RV1126B_CLKSEL_CON(14), 5, 3, MFLAGS, 0, 5, DFLAGS,
281
+
RV1126B_CLKGATE_CON(1), 13, GFLAGS),
282
+
COMPOSITE(SCLK_UART5, "sclk_uart5", mux_sclk_uart_src_p, 0,
283
+
RV1126B_CLKSEL_CON(14), 13, 3, MFLAGS, 8, 5, DFLAGS,
284
+
RV1126B_CLKGATE_CON(1), 14, GFLAGS),
285
+
COMPOSITE(SCLK_UART6, "sclk_uart6", mux_sclk_uart_src_p, 0,
286
+
RV1126B_CLKSEL_CON(15), 5, 3, MFLAGS, 0, 5, DFLAGS,
287
+
RV1126B_CLKGATE_CON(2), 0, GFLAGS),
288
+
COMPOSITE(SCLK_UART7, "sclk_uart7", mux_sclk_uart_src_p, 0,
289
+
RV1126B_CLKSEL_CON(15), 13, 3, MFLAGS, 8, 5, DFLAGS,
290
+
RV1126B_CLKGATE_CON(2), 1, GFLAGS),
291
+
COMPOSITE(MCLK_SAI0, "mclk_sai0", mclk_sai0_src_p, 0,
292
+
RV1126B_CLKSEL_CON(16), 8, 4, MFLAGS, 0, 8, DFLAGS,
293
+
RV1126B_CLKGATE_CON(2), 2, GFLAGS),
294
+
COMPOSITE(MCLK_SAI1, "mclk_sai1", mclk_sai1_src_p, 0,
295
+
RV1126B_CLKSEL_CON(17), 8, 4, MFLAGS, 0, 8, DFLAGS,
296
+
RV1126B_CLKGATE_CON(2), 3, GFLAGS),
297
+
COMPOSITE(MCLK_SAI2, "mclk_sai2", mclk_sai2_src_p, 0,
298
+
RV1126B_CLKSEL_CON(18), 8, 4, MFLAGS, 0, 8, DFLAGS,
299
+
RV1126B_CLKGATE_CON(2), 4, GFLAGS),
300
+
COMPOSITE(MCLK_PDM, "mclk_pdm", mux_sai_src_p, 0,
301
+
RV1126B_CLKSEL_CON(19), 6, 4, MFLAGS, 0, 5, DFLAGS,
302
+
RV1126B_CLKGATE_CON(2), 5, GFLAGS),
303
+
COMPOSITE_NOGATE(0, "clkout_pdm_src", mux_sai_src_p, 0,
304
+
RV1126B_CLKSEL_CON(20), 8, 4, MFLAGS, 0, 8, DFLAGS),
305
+
GATE(CLKOUT_PDM, "clkout_pdm", "clkout_pdm_src", 0,
306
+
RV1126B_CLKGATE_CON(2), 6, GFLAGS),
307
+
COMPOSITE_NODIV(MCLK_ASRC0, "mclk_asrc0", mux_sai_src_p, 0,
308
+
RV1126B_CLKSEL_CON(16), 12, 4, MFLAGS,
309
+
RV1126B_CLKGATE_CON(2), 7, GFLAGS),
310
+
COMPOSITE_NODIV(MCLK_ASRC1, "mclk_asrc1", mux_sai_src_p, 0,
311
+
RV1126B_CLKSEL_CON(17), 12, 4, MFLAGS,
312
+
RV1126B_CLKGATE_CON(2), 8, GFLAGS),
313
+
COMPOSITE_NODIV(MCLK_ASRC2, "mclk_asrc2", mux_sai_src_p, 0,
314
+
RV1126B_CLKSEL_CON(18), 12, 4, MFLAGS,
315
+
RV1126B_CLKGATE_CON(2), 9, GFLAGS),
316
+
COMPOSITE_NODIV(MCLK_ASRC3, "mclk_asrc3", mux_sai_src_p, 0,
317
+
RV1126B_CLKSEL_CON(19), 12, 4, MFLAGS,
318
+
RV1126B_CLKGATE_CON(2), 10, GFLAGS),
319
+
COMPOSITE(CLK_ASRC0, "clk_asrc0", mux_gpll_aupll_p, 0,
320
+
RV1126B_CLKSEL_CON(21), 6, 1, MFLAGS, 0, 5, DFLAGS,
321
+
RV1126B_CLKGATE_CON(2), 11, GFLAGS),
322
+
COMPOSITE(CLK_ASRC1, "clk_asrc1", mux_gpll_aupll_p, 0,
323
+
RV1126B_CLKSEL_CON(21), 14, 1, MFLAGS, 8, 5, DFLAGS,
324
+
RV1126B_CLKGATE_CON(2), 12, GFLAGS),
325
+
COMPOSITE_NOMUX(CLK_CORE_PLL, "clk_core_pll", "gpll", CLK_IS_CRITICAL,
326
+
RV1126B_CLKSEL_CON(60), 0, 3, DFLAGS,
327
+
RV1126B_CLKGATE_CON(5), 0, GFLAGS),
328
+
COMPOSITE_NOMUX(CLK_NPU_PLL, "clk_npu_pll", "gpll", CLK_IS_CRITICAL,
329
+
RV1126B_CLKSEL_CON(60), 6, 3, DFLAGS,
330
+
RV1126B_CLKGATE_CON(5), 1, GFLAGS),
331
+
COMPOSITE(CLK_VEPU_PLL, "clk_vepu_pll", mux_gpll_aupll_cpll_p, 0,
332
+
RV1126B_CLKSEL_CON(61), 4, 2, MFLAGS, 0, 3, DFLAGS,
333
+
RV1126B_CLKGATE_CON(5), 2, GFLAGS),
334
+
COMPOSITE(CLK_ISP_PLL, "clk_isp_pll", mux_gpll_aupll_cpll_p, 0,
335
+
RV1126B_CLKSEL_CON(61), 10, 2, MFLAGS, 6, 4, DFLAGS,
336
+
RV1126B_CLKGATE_CON(5), 3, GFLAGS),
337
+
COMPOSITE(CLK_SARADC0_SRC, "clk_saradc0_src", mux_200m_24m_p, 0,
338
+
RV1126B_CLKSEL_CON(63), 12, 1, MFLAGS, 0, 3, DFLAGS,
339
+
RV1126B_CLKGATE_CON(5), 6, GFLAGS),
340
+
COMPOSITE(CLK_SARADC1_SRC, "clk_saradc1_src", mux_200m_24m_p, 0,
341
+
RV1126B_CLKSEL_CON(63), 13, 1, MFLAGS, 4, 3, DFLAGS,
342
+
RV1126B_CLKGATE_CON(5), 7, GFLAGS),
343
+
COMPOSITE(CLK_SARADC2_SRC, "clk_saradc2_src", mux_200m_24m_p, 0,
344
+
RV1126B_CLKSEL_CON(63), 14, 1, MFLAGS, 8, 3, DFLAGS,
345
+
RV1126B_CLKGATE_CON(5), 8, GFLAGS),
346
+
GATE(HCLK_RKNN, "hclk_rknn", "clk_gpll_div8", CLK_IS_CRITICAL,
347
+
RV1126B_CLKGATE_CON(5), 10, GFLAGS),
348
+
GATE(PCLK_NPU_ROOT, "pclk_npu_root", "clk_cpll_div10", CLK_IS_CRITICAL,
349
+
RV1126B_CLKGATE_CON(5), 11, GFLAGS),
350
+
COMPOSITE_NODIV(ACLK_VEPU_ROOT, "aclk_vepu_root", mux_500m_400m_200m_p, CLK_IS_CRITICAL,
351
+
RV1126B_CLKSEL_CON(40), 0, 2, MFLAGS,
352
+
RV1126B_CLKGATE_CON(5), 12, GFLAGS),
353
+
GATE(HCLK_VEPU_ROOT, "hclk_vepu_root", "clk_gpll_div8", CLK_IS_CRITICAL,
354
+
RV1126B_CLKGATE_CON(5), 13, GFLAGS),
355
+
GATE(PCLK_VEPU_ROOT, "pclk_vepu_root", "clk_cpll_div10", 0,
356
+
RV1126B_CLKGATE_CON(5), 14, GFLAGS),
357
+
COMPOSITE(CLK_CORE_RGA_SRC, "clk_core_rga_src", mux_gpll_cpll_p, 0,
358
+
RV1126B_CLKSEL_CON(40), 5, 1, MFLAGS, 2, 3, DFLAGS,
359
+
RV1126B_CLKGATE_CON(6), 0, GFLAGS),
360
+
COMPOSITE_NODIV(ACLK_GMAC_ROOT, "aclk_gmac_root", mux_300m_200m_p, 0,
361
+
RV1126B_CLKSEL_CON(40), 6, 1, MFLAGS,
362
+
RV1126B_CLKGATE_CON(6), 1, GFLAGS),
363
+
COMPOSITE_NODIV(ACLK_VI_ROOT, "aclk_vi_root", mux_500m_400m_300m_p, CLK_IS_CRITICAL,
364
+
RV1126B_CLKSEL_CON(40), 7, 2, MFLAGS,
365
+
RV1126B_CLKGATE_CON(6), 2, GFLAGS),
366
+
GATE(HCLK_VI_ROOT, "hclk_vi_root", "clk_gpll_div8", CLK_IS_CRITICAL,
367
+
RV1126B_CLKGATE_CON(6), 3, GFLAGS),
368
+
GATE(PCLK_VI_ROOT, "pclk_vi_root", "clk_cpll_div10", CLK_IS_CRITICAL,
369
+
RV1126B_CLKGATE_CON(6), 4, GFLAGS),
370
+
COMPOSITE_NODIV(DCLK_VICAP_ROOT, "dclk_vicap_root", mux_333m_200m_p, 0,
371
+
RV1126B_CLKSEL_CON(42), 5, 1, MFLAGS,
372
+
RV1126B_CLKGATE_CON(6), 5, GFLAGS),
373
+
COMPOSITE(CLK_SYS_DSMC_ROOT, "clk_sys_dsmc_root", mux_24m_gpll_cpll_p, 0,
374
+
RV1126B_CLKSEL_CON(40), 14, 2, MFLAGS, 9, 5, DFLAGS,
375
+
RV1126B_CLKGATE_CON(6), 6, GFLAGS),
376
+
COMPOSITE(ACLK_VDO_ROOT, "aclk_vdo_root", mux_gpll_cpll_p, CLK_IS_CRITICAL,
377
+
RV1126B_CLKSEL_CON(42), 4, 1, MFLAGS, 0, 4, DFLAGS,
378
+
RV1126B_CLKGATE_CON(6), 7, GFLAGS),
379
+
COMPOSITE(ACLK_RKVDEC_ROOT, "aclk_rkvdec_root", mux_gpll_cpll_p, 0,
380
+
RV1126B_CLKSEL_CON(42), 10, 1, MFLAGS, 6, 4, DFLAGS,
381
+
RV1126B_CLKGATE_CON(6), 8, GFLAGS),
382
+
GATE(HCLK_VDO_ROOT, "hclk_vdo_root", "clk_gpll_div8", CLK_IS_CRITICAL,
383
+
RV1126B_CLKGATE_CON(6), 9, GFLAGS),
384
+
GATE(PCLK_VDO_ROOT, "pclk_vdo_root", "clk_cpll_div10", CLK_IS_CRITICAL,
385
+
RV1126B_CLKGATE_CON(6), 10, GFLAGS),
386
+
COMPOSITE(DCLK_VOP, "dclk_vop", mux_gpll_cpll_p, 0,
387
+
RV1126B_CLKSEL_CON(43), 8, 1, MFLAGS, 0, 8, DFLAGS,
388
+
RV1126B_CLKGATE_CON(6), 12, GFLAGS),
389
+
COMPOSITE(DCLK_OOC_SRC, "dclk_ooc_src", mux_gpll_cpll_p, 0,
390
+
RV1126B_CLKSEL_CON(62), 7, 1, MFLAGS, 8, 8, DFLAGS,
391
+
RV1126B_CLKGATE_CON(6), 13, GFLAGS),
392
+
GATE(DCLK_DECOM_SRC, "dclk_decom_src", "clk_gpll_div3", 0,
393
+
RV1126B_CLKGATE_CON(6), 14, GFLAGS),
394
+
GATE(PCLK_DDR_ROOT, "pclk_ddr_root", "clk_cpll_div10", 0,
395
+
RV1126B_CLKGATE_CON(7), 0, GFLAGS),
396
+
COMPOSITE(ACLK_SYSMEM, "aclk_sysmem", mux_gpll_cpll_p, CLK_IS_CRITICAL,
397
+
RV1126B_CLKSEL_CON(44), 3, 1, MFLAGS, 0, 3, DFLAGS,
398
+
RV1126B_CLKGATE_CON(7), 1, GFLAGS),
399
+
COMPOSITE_NODIV(ACLK_TOP_ROOT, "aclk_top_root", mux_600m_400m_200m_p, CLK_IS_CRITICAL,
400
+
RV1126B_CLKSEL_CON(44), 6, 2, MFLAGS,
401
+
RV1126B_CLKGATE_CON(7), 3, GFLAGS),
402
+
COMPOSITE_NODIV(ACLK_BUS_ROOT, "aclk_bus_root", mux_400m_300m_200m_p, CLK_IS_CRITICAL,
403
+
RV1126B_CLKSEL_CON(44), 8, 2, MFLAGS,
404
+
RV1126B_CLKGATE_CON(7), 4, GFLAGS),
405
+
COMPOSITE_NODIV(HCLK_BUS_ROOT, "hclk_bus_root", mux_200m_100m_p, CLK_IS_CRITICAL,
406
+
RV1126B_CLKSEL_CON(44), 10, 1, MFLAGS,
407
+
RV1126B_CLKGATE_CON(7), 5, GFLAGS),
408
+
GATE(PCLK_BUS_ROOT, "pclk_bus_root", "clk_cpll_div10", CLK_IS_CRITICAL,
409
+
RV1126B_CLKGATE_CON(7), 6, GFLAGS),
410
+
COMPOSITE(CCLK_SDMMC0, "cclk_sdmmc0", mux_gpll_cpll_24m_p, 0,
411
+
RV1126B_CLKSEL_CON(45), 8, 2, MFLAGS, 0, 8, DFLAGS,
412
+
RV1126B_CLKGATE_CON(7), 7, GFLAGS),
413
+
COMPOSITE(CCLK_SDMMC1, "cclk_sdmmc1", mux_gpll_cpll_24m_p, 0,
414
+
RV1126B_CLKSEL_CON(46), 8, 2, MFLAGS, 0, 8, DFLAGS,
415
+
RV1126B_CLKGATE_CON(7), 8, GFLAGS),
416
+
COMPOSITE(CCLK_EMMC, "cclk_emmc", mux_gpll_cpll_24m_p, 0,
417
+
RV1126B_CLKSEL_CON(47), 8, 2, MFLAGS, 0, 8, DFLAGS,
418
+
RV1126B_CLKGATE_CON(7), 9, GFLAGS),
419
+
COMPOSITE(SCLK_2X_FSPI0, "sclk_2x_fspi0", mux_gpll_cpll_24m_p, 0,
420
+
RV1126B_CLKSEL_CON(48), 8, 2, MFLAGS, 0, 8, DFLAGS,
421
+
RV1126B_CLKGATE_CON(7), 10, GFLAGS),
422
+
COMPOSITE(CLK_GMAC_PTP_REF_SRC, "clk_gmac_ptp_ref_src", mux_cpll_24m_p, 0,
423
+
RV1126B_CLKSEL_CON(45), 10, 1, MFLAGS, 11, 5, DFLAGS,
424
+
RV1126B_CLKGATE_CON(7), 11, GFLAGS),
425
+
GATE(CLK_GMAC_125M, "clk_gmac_125m", "clk_cpll_div8", 0,
426
+
RV1126B_CLKGATE_CON(7), 12, GFLAGS),
427
+
COMPOSITE_NODIV(CLK_TIMER_ROOT, "clk_timer_root", mux_100m_24m_p, 0,
428
+
RV1126B_CLKSEL_CON(46), 11, 1, MFLAGS,
429
+
RV1126B_CLKGATE_CON(7), 13, GFLAGS),
430
+
COMPOSITE_NODIV(TCLK_WDT_NS_SRC, "tclk_wdt_ns_src", mux_100m_24m_p, 0,
431
+
RV1126B_CLKSEL_CON(46), 12, 1, MFLAGS,
432
+
RV1126B_CLKGATE_CON(8), 0, GFLAGS),
433
+
COMPOSITE_NODIV(TCLK_WDT_S_SRC, "tclk_wdt_s_src", mux_100m_24m_p, 0,
434
+
RV1126B_CLKSEL_CON(46), 13, 1, MFLAGS,
435
+
RV1126B_CLKGATE_CON(8), 1, GFLAGS),
436
+
COMPOSITE_NODIV(TCLK_WDT_HPMCU, "tclk_wdt_hpmcu", mux_100m_24m_p, 0,
437
+
RV1126B_CLKSEL_CON(46), 14, 1, MFLAGS,
438
+
RV1126B_CLKGATE_CON(8), 2, GFLAGS),
439
+
COMPOSITE(CLK_CAN0, "clk_can0", mux_gpll_cpll_24m_p, 0,
440
+
RV1126B_CLKSEL_CON(49), 6, 2, MFLAGS, 0, 5, DFLAGS,
441
+
RV1126B_CLKGATE_CON(8), 4, GFLAGS),
442
+
COMPOSITE(CLK_CAN1, "clk_can1", mux_gpll_cpll_24m_p, 0,
443
+
RV1126B_CLKSEL_CON(49), 14, 2, MFLAGS, 8, 5, DFLAGS,
444
+
RV1126B_CLKGATE_CON(8), 5, GFLAGS),
445
+
COMPOSITE_NODIV(PCLK_PERI_ROOT, "pclk_peri_root", mux_100m_24m_p, CLK_IS_CRITICAL,
446
+
RV1126B_CLKSEL_CON(47), 12, 1, MFLAGS,
447
+
RV1126B_CLKGATE_CON(8), 6, GFLAGS),
448
+
COMPOSITE_NODIV(ACLK_PERI_ROOT, "aclk_peri_root", mux_200m_24m_p, CLK_IS_CRITICAL,
449
+
RV1126B_CLKSEL_CON(47), 13, 1, MFLAGS,
450
+
RV1126B_CLKGATE_CON(8), 7, GFLAGS),
451
+
COMPOSITE_NODIV(CLK_I2C_BUS_SRC, "clk_i2c_bus_src", mux_200m_24m_p, 0,
452
+
RV1126B_CLKSEL_CON(50), 1, 1, MFLAGS,
453
+
RV1126B_CLKGATE_CON(8), 9, GFLAGS),
454
+
COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_100m_50m_24m_p, 0,
455
+
RV1126B_CLKSEL_CON(50), 2, 2, MFLAGS,
456
+
RV1126B_CLKGATE_CON(8), 10, GFLAGS),
457
+
COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_100m_50m_24m_p, 0,
458
+
RV1126B_CLKSEL_CON(50), 4, 2, MFLAGS,
459
+
RV1126B_CLKGATE_CON(8), 11, GFLAGS),
460
+
GATE(BUSCLK_PMU_SRC, "busclk_pmu_src", "clk_cpll_div10", CLK_IS_CRITICAL,
461
+
RV1126B_CLKGATE_CON(8), 12, GFLAGS),
462
+
COMPOSITE_NODIV(CLK_PWM0, "clk_pwm0", mux_100m_24m_p, 0,
463
+
RV1126B_CLKSEL_CON(50), 8, 1, MFLAGS,
464
+
RV1126B_CLKGATE_CON(9), 0, GFLAGS),
465
+
COMPOSITE_NODIV(CLK_PWM2, "clk_pwm2", mux_100m_24m_p, 0,
466
+
RV1126B_CLKSEL_CON(50), 10, 1, MFLAGS,
467
+
RV1126B_CLKGATE_CON(9), 2, GFLAGS),
468
+
COMPOSITE_NODIV(CLK_PWM3, "clk_pwm3", mux_100m_24m_p, 0,
469
+
RV1126B_CLKSEL_CON(50), 11, 1, MFLAGS,
470
+
RV1126B_CLKGATE_CON(9), 3, GFLAGS),
471
+
COMPOSITE_NODIV(CLK_PKA_RKCE_SRC, "clk_pka_rkce_src", mux_300m_200m_p, CLK_IS_CRITICAL,
472
+
RV1126B_CLKSEL_CON(50), 12, 1, MFLAGS,
473
+
RV1126B_CLKGATE_CON(9), 4, GFLAGS),
474
+
COMPOSITE_NODIV(ACLK_RKCE_SRC, "aclk_rkce_src", mux_200m_24m_p, CLK_IS_CRITICAL,
475
+
RV1126B_CLKSEL_CON(50), 13, 1, MFLAGS,
476
+
RV1126B_CLKGATE_CON(9), 5, GFLAGS),
477
+
COMPOSITE_NODIV(ACLK_VCP_ROOT, "aclk_vcp_root", mux_500m_400m_200m_p, CLK_IS_CRITICAL,
478
+
RV1126B_CLKSEL_CON(48), 12, 2, MFLAGS,
479
+
RV1126B_CLKGATE_CON(9), 6, GFLAGS),
480
+
GATE(HCLK_VCP_ROOT, "hclk_vcp_root", "clk_gpll_div8", CLK_IS_CRITICAL,
481
+
RV1126B_CLKGATE_CON(9), 7, GFLAGS),
482
+
GATE(PCLK_VCP_ROOT, "pclk_vcp_root", "clk_cpll_div10", CLK_IS_CRITICAL,
483
+
RV1126B_CLKGATE_CON(9), 8, GFLAGS),
484
+
COMPOSITE(CLK_CORE_FEC_SRC, "clk_core_fec_src", mux_gpll_cpll_p, 0,
485
+
RV1126B_CLKSEL_CON(51), 3, 1, MFLAGS, 0, 3, DFLAGS,
486
+
RV1126B_CLKGATE_CON(9), 9, GFLAGS),
487
+
GATE(CLK_50M_GMAC_IOBUF_VI, "clk_50m_gmac_iobuf_vi", "clk_cpll_div20", 0,
488
+
RV1126B_CLKGATE_CON(9), 11, GFLAGS),
489
+
GATE(PCLK_TOP_ROOT, "pclk_top_root", "clk_cpll_div10", CLK_IS_CRITICAL,
490
+
RV1126B_CLKGATE_CON(15), 0, GFLAGS),
491
+
COMPOSITE(CLK_MIPI0_OUT2IO, "clk_mipi0_out2io", mux_600m_24m_p, 0,
492
+
RV1126B_CLKSEL_CON(67), 11, 1, MFLAGS, 0, 5, DFLAGS,
493
+
RV1126B_CLKGATE_CON(15), 3, GFLAGS),
494
+
COMPOSITE(CLK_MIPI1_OUT2IO, "clk_mipi1_out2io", mux_600m_24m_p, 0,
495
+
RV1126B_CLKSEL_CON(67), 12, 1, MFLAGS, 6, 5, DFLAGS,
496
+
RV1126B_CLKGATE_CON(15), 4, GFLAGS),
497
+
COMPOSITE(CLK_MIPI2_OUT2IO, "clk_mipi2_out2io", mux_600m_24m_p, 0,
498
+
RV1126B_CLKSEL_CON(68), 11, 1, MFLAGS, 0, 5, DFLAGS,
499
+
RV1126B_CLKGATE_CON(15), 5, GFLAGS),
500
+
COMPOSITE(CLK_MIPI3_OUT2IO, "clk_mipi3_out2io", mux_600m_24m_p, 0,
501
+
RV1126B_CLKSEL_CON(68), 12, 1, MFLAGS, 6, 5, DFLAGS,
502
+
RV1126B_CLKGATE_CON(15), 6, GFLAGS),
503
+
COMPOSITE(CLK_CIF_OUT2IO, "clk_cif_out2io", mux_600m_24m_p, 0,
504
+
RV1126B_CLKSEL_CON(69), 5, 1, MFLAGS, 0, 5, DFLAGS,
505
+
RV1126B_CLKGATE_CON(15), 7, GFLAGS),
506
+
COMPOSITE(CLK_MAC_OUT2IO, "clk_mac_out2io", mux_gpll_cpll_24m_p, 0,
507
+
RV1126B_CLKSEL_CON(69), 6, 2, MFLAGS, 8, 7, DFLAGS,
508
+
RV1126B_CLKGATE_CON(15), 8, GFLAGS),
509
+
COMPOSITE_NOMUX(MCLK_SAI0_OUT2IO, "mclk_sai0_out2io", "mclk_sai0", CLK_SET_RATE_PARENT,
510
+
RV1126B_CLKSEL_CON(70), 0, 4, DFLAGS,
511
+
RV1126B_CLKGATE_CON(15), 9, GFLAGS),
512
+
COMPOSITE_NOMUX(MCLK_SAI1_OUT2IO, "mclk_sai1_out2io", "mclk_sai1", CLK_SET_RATE_PARENT,
513
+
RV1126B_CLKSEL_CON(70), 5, 4, DFLAGS,
514
+
RV1126B_CLKGATE_CON(15), 10, GFLAGS),
515
+
COMPOSITE_NOMUX(MCLK_SAI2_OUT2IO, "mclk_sai2_out2io", "mclk_sai2", CLK_SET_RATE_PARENT,
516
+
RV1126B_CLKSEL_CON(70), 10, 4, DFLAGS,
517
+
RV1126B_CLKGATE_CON(15), 11, GFLAGS),
518
+
519
+
/* pd _npu */
520
+
MUX(ACLK_RKNN, "aclk_rknn", aclk_npu_root_p, CLK_SET_RATE_PARENT,
521
+
RV1126B_NPUCLKSEL_CON(0), 1, 1, MFLAGS),
522
+
523
+
/* pd_vepu */
524
+
GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_vepu_root", 0,
525
+
RV1126B_VEPUCLKGATE_CON(0), 7, GFLAGS),
526
+
GATE(DBCLK_GPIO3, "dbclk_gpio3", "xin24m", 0,
527
+
RV1126B_VEPUCLKGATE_CON(0), 8, GFLAGS),
528
+
GATE(PCLK_IOC_VCCIO3, "pclk_ioc_vccio3", "pclk_vepu_root", CLK_IS_CRITICAL,
529
+
RV1126B_VEPUCLKGATE_CON(0), 9, GFLAGS),
530
+
GATE(PCLK_SARADC0, "pclk_saradc0", "pclk_vepu_root", 0,
531
+
RV1126B_VEPUCLKGATE_CON(0), 10, GFLAGS),
532
+
MUX(CLK_SARADC0, "clk_saradc0", clk_saradc0_p, CLK_SET_RATE_PARENT,
533
+
RV1126B_VEPUCLKSEL_CON(0), 2, 1, MFLAGS),
534
+
GATE(HCLK_SDMMC1, "hclk_sdmmc1", "hclk_vepu_root", 0,
535
+
RV1126B_VEPUCLKGATE_CON(0), 12, GFLAGS),
536
+
GATE(HCLK_VEPU, "hclk_vepu", "hclk_vepu_root", 0,
537
+
RV1126B_VEPUCLKGATE_CON(1), 1, GFLAGS),
538
+
GATE(ACLK_VEPU, "aclk_vepu", "aclk_vepu_root", 0,
539
+
RV1126B_VEPUCLKGATE_CON(1), 2, GFLAGS),
540
+
COMPOSITE_NODIV(CLK_CORE_VEPU, "clk_core_vepu", clk_core_vepu_p, CLK_SET_RATE_PARENT,
541
+
RV1126B_VEPUCLKSEL_CON(0), 1, 1, MFLAGS,
542
+
RV1126B_VEPUCLKGATE_CON(1), 3, GFLAGS),
543
+
544
+
/* pd_vcp */
545
+
GATE(HCLK_FEC, "hclk_fec", "hclk_vcp_root", 0,
546
+
RV1126B_VCPCLKGATE_CON(1), 0, GFLAGS),
547
+
GATE(ACLK_FEC, "aclk_fec", "aclk_vcp_root", 0,
548
+
RV1126B_VCPCLKGATE_CON(1), 1, GFLAGS),
549
+
COMPOSITE_NODIV(CLK_CORE_FEC, "clk_core_fec", clk_core_fec_p, CLK_SET_RATE_PARENT,
550
+
RV1126B_VCPCLKSEL_CON(0), 13, 1, MFLAGS,
551
+
RV1126B_VCPCLKGATE_CON(1), 2, GFLAGS),
552
+
GATE(HCLK_AVSP, "hclk_avsp", "hclk_vcp_root", 0,
553
+
RV1126B_VCPCLKGATE_CON(1), 3, GFLAGS),
554
+
GATE(ACLK_AVSP, "aclk_avsp", "aclk_vcp_root", 0,
555
+
RV1126B_VCPCLKGATE_CON(1), 4, GFLAGS),
556
+
GATE(HCLK_AISP, "hclk_aisp", "hclk_vcp_root", 0,
557
+
RV1126B_VCPCLKGATE_CON(0), 11, GFLAGS),
558
+
GATE(ACLK_AISP, "aclk_aisp", "aclk_vcp_root", 0,
559
+
RV1126B_VCPCLKGATE_CON(0), 12, GFLAGS),
560
+
COMPOSITE_NODIV(CLK_CORE_AISP, "clk_core_aisp", clk_core_aisp_p, CLK_SET_RATE_PARENT,
561
+
RV1126B_VCPCLKSEL_CON(0), 15, 1, MFLAGS,
562
+
RV1126B_VCPCLKGATE_CON(0), 13, GFLAGS),
563
+
564
+
/* pd_vi */
565
+
MUX(CLK_CORE_ISP_ROOT, "clk_core_isp_root", clk_core_isp_root_p, CLK_SET_RATE_PARENT,
566
+
RV1126B_VICLKSEL_CON(0), 1, 1, MFLAGS),
567
+
GATE(PCLK_DSMC, "pclk_dsmc", "pclk_vi_root", 0,
568
+
RV1126B_VICLKGATE_CON(0), 8, GFLAGS),
569
+
GATE(ACLK_DSMC, "aclk_dsmc", "hclk_vi_root", 0,
570
+
RV1126B_VICLKGATE_CON(0), 9, GFLAGS),
571
+
GATE(HCLK_CAN0, "hclk_can0", "hclk_vi_root", 0,
572
+
RV1126B_VICLKGATE_CON(0), 10, GFLAGS),
573
+
GATE(HCLK_CAN1, "hclk_can1", "hclk_vi_root", 0,
574
+
RV1126B_VICLKGATE_CON(0), 11, GFLAGS),
575
+
GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_vi_root", 0,
576
+
RV1126B_VICLKGATE_CON(1), 0, GFLAGS),
577
+
GATE(DBCLK_GPIO2, "dbclk_gpio2", "xin24m", 0,
578
+
RV1126B_VICLKGATE_CON(1), 1, GFLAGS),
579
+
GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_vi_root", 0,
580
+
RV1126B_VICLKGATE_CON(1), 2, GFLAGS),
581
+
GATE(DBCLK_GPIO4, "dbclk_gpio4", "xin24m", 0,
582
+
RV1126B_VICLKGATE_CON(1), 3, GFLAGS),
583
+
GATE(PCLK_GPIO5, "pclk_gpio5", "pclk_vi_root", 0,
584
+
RV1126B_VICLKGATE_CON(1), 4, GFLAGS),
585
+
GATE(DBCLK_GPIO5, "dbclk_gpio5", "xin24m", 0,
586
+
RV1126B_VICLKGATE_CON(1), 5, GFLAGS),
587
+
GATE(PCLK_GPIO6, "pclk_gpio6", "pclk_vi_root", 0,
588
+
RV1126B_VICLKGATE_CON(1), 6, GFLAGS),
589
+
GATE(DBCLK_GPIO6, "dbclk_gpio6", "xin24m", 0,
590
+
RV1126B_VICLKGATE_CON(1), 7, GFLAGS),
591
+
GATE(PCLK_GPIO7, "pclk_gpio7", "pclk_vi_root", 0,
592
+
RV1126B_VICLKGATE_CON(1), 8, GFLAGS),
593
+
GATE(DBCLK_GPIO7, "dbclk_gpio7", "xin24m", 0,
594
+
RV1126B_VICLKGATE_CON(1), 9, GFLAGS),
595
+
GATE(PCLK_IOC_VCCIO2, "pclk_ioc_vccio2", "pclk_vi_root", CLK_IS_CRITICAL,
596
+
RV1126B_VICLKGATE_CON(1), 10, GFLAGS),
597
+
GATE(PCLK_IOC_VCCIO4, "pclk_ioc_vccio4", "pclk_vi_root", CLK_IS_CRITICAL,
598
+
RV1126B_VICLKGATE_CON(1), 11, GFLAGS),
599
+
GATE(PCLK_IOC_VCCIO5, "pclk_ioc_vccio5", "pclk_vi_root", CLK_IS_CRITICAL,
600
+
RV1126B_VICLKGATE_CON(1), 12, GFLAGS),
601
+
GATE(PCLK_IOC_VCCIO6, "pclk_ioc_vccio6", "pclk_vi_root", CLK_IS_CRITICAL,
602
+
RV1126B_VICLKGATE_CON(1), 13, GFLAGS),
603
+
GATE(PCLK_IOC_VCCIO7, "pclk_ioc_vccio7", "pclk_vi_root", CLK_IS_CRITICAL,
604
+
RV1126B_VICLKGATE_CON(1), 14, GFLAGS),
605
+
GATE(HCLK_ISP, "hclk_isp", "hclk_vi_root", 0,
606
+
RV1126B_VICLKGATE_CON(2), 0, GFLAGS),
607
+
GATE(ACLK_ISP, "aclk_isp", "aclk_vi_root", 0,
608
+
RV1126B_VICLKGATE_CON(2), 1, GFLAGS),
609
+
GATE(CLK_CORE_ISP, "clk_core_isp", "clk_core_isp_root", 0,
610
+
RV1126B_VICLKGATE_CON(2), 2, GFLAGS),
611
+
GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi_root", 0,
612
+
RV1126B_VICLKGATE_CON(2), 3, GFLAGS),
613
+
GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi_root", 0,
614
+
RV1126B_VICLKGATE_CON(2), 4, GFLAGS),
615
+
GATE(DCLK_VICAP, "dclk_vicap", "dclk_vicap_root", 0,
616
+
RV1126B_VICLKGATE_CON(2), 5, GFLAGS),
617
+
GATE(ISP0CLK_VICAP, "isp0clk_vicap", "clk_core_isp_root", 0,
618
+
RV1126B_VICLKGATE_CON(2), 6, GFLAGS),
619
+
GATE(HCLK_VPSS, "hclk_vpss", "hclk_vi_root", 0,
620
+
RV1126B_VICLKGATE_CON(2), 7, GFLAGS),
621
+
GATE(ACLK_VPSS, "aclk_vpss", "aclk_vi_root", 0,
622
+
RV1126B_VICLKGATE_CON(2), 8, GFLAGS),
623
+
GATE(CLK_CORE_VPSS, "clk_core_vpss", "clk_core_isp_root", 0,
624
+
RV1126B_VICLKGATE_CON(2), 9, GFLAGS),
625
+
GATE(HCLK_VPSL, "hclk_vpsl", "hclk_vi_root", 0,
626
+
RV1126B_VICLKGATE_CON(2), 10, GFLAGS),
627
+
GATE(ACLK_VPSL, "aclk_vpsl", "aclk_vi_root", 0,
628
+
RV1126B_VICLKGATE_CON(2), 11, GFLAGS),
629
+
GATE(CLK_CORE_VPSL, "clk_core_vpsl", "clk_core_isp_root", 0,
630
+
RV1126B_VICLKGATE_CON(2), 12, GFLAGS),
631
+
GATE(PCLK_CSI2HOST0, "pclk_csi2host0", "pclk_vi_root", 0,
632
+
RV1126B_VICLKGATE_CON(3), 0, GFLAGS),
633
+
GATE(DCLK_CSI2HOST0, "dclk_csi2host0", "dclk_vicap_root", 0,
634
+
RV1126B_VICLKGATE_CON(3), 1, GFLAGS),
635
+
GATE(PCLK_CSI2HOST1, "pclk_csi2host1", "pclk_vi_root", 0,
636
+
RV1126B_VICLKGATE_CON(3), 2, GFLAGS),
637
+
GATE(DCLK_CSI2HOST1, "dclk_csi2host1", "dclk_vicap_root", 0,
638
+
RV1126B_VICLKGATE_CON(3), 3, GFLAGS),
639
+
GATE(PCLK_CSI2HOST2, "pclk_csi2host2", "pclk_vi_root", 0,
640
+
RV1126B_VICLKGATE_CON(3), 4, GFLAGS),
641
+
GATE(DCLK_CSI2HOST2, "dclk_csi2host2", "dclk_vicap_root", 0,
642
+
RV1126B_VICLKGATE_CON(3), 5, GFLAGS),
643
+
GATE(PCLK_CSI2HOST3, "pclk_csi2host3", "pclk_vi_root", 0,
644
+
RV1126B_VICLKGATE_CON(3), 6, GFLAGS),
645
+
GATE(DCLK_CSI2HOST3, "dclk_csi2host3", "dclk_vicap_root", 0,
646
+
RV1126B_VICLKGATE_CON(3), 7, GFLAGS),
647
+
GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_vi_root", 0,
648
+
RV1126B_VICLKGATE_CON(3), 8, GFLAGS),
649
+
GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_root", 0,
650
+
RV1126B_VICLKGATE_CON(3), 9, GFLAGS),
651
+
GATE(PCLK_GMAC, "pclk_gmac", "pclk_vi_root", 0,
652
+
RV1126B_VICLKGATE_CON(3), 10, GFLAGS),
653
+
MUX(CLK_GMAC_PTP_REF, "clk_gmac_ptp_ref", clk_gmac_ptp_ref_p, CLK_SET_RATE_PARENT,
654
+
RV1126B_VICLKSEL_CON(0), 14, 1, MFLAGS),
655
+
GATE(PCLK_CSIPHY0, "pclk_csiphy0", "pclk_vi_root", 0,
656
+
RV1126B_VICLKGATE_CON(3), 11, GFLAGS),
657
+
GATE(PCLK_CSIPHY1, "pclk_csiphy1", "pclk_vi_root", 0,
658
+
RV1126B_VICLKGATE_CON(3), 12, GFLAGS),
659
+
GATE(PCLK_MACPHY, "pclk_macphy", "pclk_vi_root", 0,
660
+
RV1126B_VICLKGATE_CON(3), 13, GFLAGS),
661
+
GATE(PCLK_SARADC1, "pclk_saradc1", "pclk_vi_root", 0,
662
+
RV1126B_VICLKGATE_CON(4), 0, GFLAGS),
663
+
MUX(CLK_SARADC1, "clk_saradc1", clk_saradc1_p, CLK_SET_RATE_PARENT,
664
+
RV1126B_VICLKSEL_CON(0), 2, 1, MFLAGS),
665
+
GATE(PCLK_SARADC2, "pclk_saradc2", "pclk_vi_root", 0,
666
+
RV1126B_VICLKGATE_CON(4), 2, GFLAGS),
667
+
MUX(CLK_SARADC2, "clk_saradc2", clk_saradc2_p, CLK_SET_RATE_PARENT,
668
+
RV1126B_VICLKSEL_CON(0), 3, 1, MFLAGS),
669
+
COMPOSITE_NODIV(CLK_MACPHY, "clk_macphy", clk_macphy_p, 0,
670
+
RV1126B_VICLKSEL_CON(1), 1, 1, MFLAGS,
671
+
RV1126B_VICLKGATE_CON(0), 12, GFLAGS),
672
+
673
+
/* pd_vdo */
674
+
GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_root", 0,
675
+
RV1126B_VDOCLKGATE_CON(0), 7, GFLAGS),
676
+
GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_vdo_root", 0,
677
+
RV1126B_VDOCLKGATE_CON(0), 8, GFLAGS),
678
+
GATE(CLK_HEVC_CA_RKVDEC, "clk_hevc_ca_rkvdec", "aclk_rkvdec_root", 0,
679
+
RV1126B_VDOCLKGATE_CON(0), 9, GFLAGS),
680
+
GATE(ACLK_VOP, "aclk_vop", "aclk_vdo_root", 0,
681
+
RV1126B_VDOCLKGATE_CON(0), 10, GFLAGS),
682
+
GATE(HCLK_VOP, "hclk_vop", "hclk_vdo_root", 0,
683
+
RV1126B_VDOCLKGATE_CON(0), 11, GFLAGS),
684
+
GATE(ACLK_OOC, "aclk_ooc", "aclk_vdo_root", 0,
685
+
RV1126B_VDOCLKGATE_CON(0), 13, GFLAGS),
686
+
GATE(HCLK_OOC, "hclk_ooc", "hclk_vdo_root", 0,
687
+
RV1126B_VDOCLKGATE_CON(0), 14, GFLAGS),
688
+
GATE(HCLK_RKJPEG, "hclk_rkjpeg", "hclk_vdo_root", 0,
689
+
RV1126B_VDOCLKGATE_CON(1), 3, GFLAGS),
690
+
GATE(ACLK_RKJPEG, "aclk_rkjpeg", "aclk_vdo_root", 0,
691
+
RV1126B_VDOCLKGATE_CON(1), 4, GFLAGS),
692
+
GATE(ACLK_RKMMU_DECOM, "aclk_rkmmu_decom", "aclk_vdo_root", 0,
693
+
RV1126B_VDOCLKGATE_CON(1), 5, GFLAGS),
694
+
GATE(HCLK_RKMMU_DECOM, "hclk_rkmmu_decom", "hclk_vdo_root", 0,
695
+
RV1126B_VDOCLKGATE_CON(1), 6, GFLAGS),
696
+
GATE(DCLK_DECOM, "dclk_decom", "dclk_decom_src", 0,
697
+
RV1126B_VDOCLKGATE_CON(1), 8, GFLAGS),
698
+
GATE(ACLK_DECOM, "aclk_decom", "aclk_vdo_root", 0,
699
+
RV1126B_VDOCLKGATE_CON(1), 9, GFLAGS),
700
+
GATE(PCLK_DECOM, "pclk_decom", "pclk_vdo_root", 0,
701
+
RV1126B_VDOCLKGATE_CON(1), 10, GFLAGS),
702
+
GATE(PCLK_MIPI_DSI, "pclk_mipi_dsi", "pclk_vdo_root", 0,
703
+
RV1126B_VDOCLKGATE_CON(1), 12, GFLAGS),
704
+
GATE(PCLK_DSIPHY, "pclk_dsiphy", "pclk_vdo_root", 0,
705
+
RV1126B_VDOCLKGATE_CON(1), 13, GFLAGS),
706
+
707
+
/* pd_ddr */
708
+
GATE(PCLK_DDRC, "pclk_ddrc", "pclk_ddr_root", CLK_IS_CRITICAL,
709
+
RV1126B_DDRCLKGATE_CON(0), 2, GFLAGS),
710
+
GATE(PCLK_DDRMON, "pclk_ddrmon", "pclk_ddr_root", CLK_IS_CRITICAL,
711
+
RV1126B_DDRCLKGATE_CON(0), 3, GFLAGS),
712
+
GATE(CLK_TIMER_DDRMON, "clk_timer_ddrmon", "xin24m", 0,
713
+
RV1126B_DDRCLKGATE_CON(0), 4, GFLAGS),
714
+
GATE(PCLK_DFICTRL, "pclk_dfictrl", "pclk_ddr_root", CLK_IS_CRITICAL,
715
+
RV1126B_DDRCLKGATE_CON(0), 5, GFLAGS),
716
+
GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_ddr_root", CLK_IS_CRITICAL,
717
+
RV1126B_DDRCLKGATE_CON(0), 8, GFLAGS),
718
+
GATE(PCLK_DMA2DDR, "pclk_dma2ddr", "pclk_ddr_root", CLK_IS_CRITICAL,
719
+
RV1126B_DDRCLKGATE_CON(0), 9, GFLAGS),
720
+
721
+
/* pd_pmu*/
722
+
COMPOSITE_NODIV(CLK_RCOSC_SRC, "clk_rcosc_src", clk_rcosc_src_p, 0,
723
+
RV1126B_PMUCLKSEL_CON(1), 0, 3, MFLAGS,
724
+
RV1126B_PMUCLKGATE_CON(0), 0, GFLAGS),
725
+
COMPOSITE_NOGATE(BUSCLK_PMU_MUX, "busclk_pmu_mux", busclk_pmu_mux_p, 0,
726
+
RV1126B_PMUCLKSEL_CON(1), 3, 1, MFLAGS, 4, 2, DFLAGS),
727
+
GATE(BUSCLK_PMU_ROOT, "busclk_pmu_root", "busclk_pmu_mux", 0,
728
+
RV1126B_PMUCLKGATE_CON(0), 1, GFLAGS),
729
+
GATE(BUSCLK_PMU1_ROOT, "busclk_pmu1_root", "busclk_pmu_mux", CLK_IS_CRITICAL,
730
+
RV1126B_PMUCLKGATE_CON(3), 11, GFLAGS),
731
+
GATE(PCLK_PMU, "pclk_pmu", "busclk_pmu_root", CLK_IS_CRITICAL,
732
+
RV1126B_PMUCLKGATE_CON(0), 6, GFLAGS),
733
+
MUX(0, "xin_rc_src", clk_xin_rc_div_p, 0,
734
+
RV1126B_PMUCLKSEL_CON(2), 0, 1, MFLAGS),
735
+
COMPOSITE_FRACMUX_NOGATE(CLK_XIN_RC_DIV, "clk_xin_rc_div", "xin_rc_src", CLK_SET_RATE_PARENT,
736
+
RV1126B_PMUCLKSEL_CON(8), 0,
737
+
&rv1126b_rcdiv_pmu_fracmux),
738
+
GATE(PCLK_PMU_GPIO0, "pclk_pmu_gpio0", "busclk_pmu_root", 0,
739
+
RV1126B_PMUCLKGATE_CON(0), 7, GFLAGS),
740
+
COMPOSITE_NODIV(DBCLK_PMU_GPIO0, "dbclk_pmu_gpio0", mux_24m_32k_p, 0,
741
+
RV1126B_PMUCLKSEL_CON(2), 4, 1, MFLAGS,
742
+
RV1126B_PMUCLKGATE_CON(0), 8, GFLAGS),
743
+
GATE(PCLK_PMU_HP_TIMER, "pclk_pmu_hp_timer", "busclk_pmu_root", CLK_IS_CRITICAL,
744
+
RV1126B_PMUCLKGATE_CON(0), 10, GFLAGS),
745
+
COMPOSITE(CLK_PMU_HP_TIMER, "clk_pmu_hp_timer", mux_cpll_24m_p, CLK_IS_CRITICAL,
746
+
RV1126B_PMUCLKSEL_CON(1), 13, 1, MFLAGS, 8, 5, DFLAGS,
747
+
RV1126B_PMUCLKGATE_CON(0), 11, GFLAGS),
748
+
GATE(CLK_PMU_32K_HP_TIMER, "clk_pmu_32k_hp_timer", "clk_32k", CLK_IS_CRITICAL,
749
+
RV1126B_PMUCLKGATE_CON(0), 13, GFLAGS),
750
+
GATE(PCLK_PWM1, "pclk_pwm1", "busclk_pmu_root", 0,
751
+
RV1126B_PMUCLKGATE_CON(1), 0, GFLAGS),
752
+
COMPOSITE(CLK_PWM1, "clk_pwm1", mux_24m_rcosc_buspmu_p, 0,
753
+
RV1126B_PMUCLKSEL_CON(2), 8, 2, MFLAGS, 6, 2, DFLAGS,
754
+
RV1126B_PMUCLKGATE_CON(1), 1, GFLAGS),
755
+
GATE(CLK_OSC_PWM1, "clk_osc_pwm1", "xin24m", 0,
756
+
RV1126B_PMUCLKGATE_CON(1), 2, GFLAGS),
757
+
GATE(CLK_RC_PWM1, "clk_rc_pwm1", "clk_32k", 0,
758
+
RV1126B_PMUCLKGATE_CON(1), 3, GFLAGS),
759
+
GATE(PCLK_I2C2, "pclk_i2c2", "busclk_pmu_root", 0,
760
+
RV1126B_PMUCLKGATE_CON(1), 6, GFLAGS),
761
+
COMPOSITE(CLK_I2C2, "clk_i2c2", mux_24m_rcosc_buspmu_p, 0,
762
+
RV1126B_PMUCLKSEL_CON(2), 14, 2, MFLAGS, 12, 2, DFLAGS,
763
+
RV1126B_PMUCLKGATE_CON(1), 7, GFLAGS),
764
+
GATE(PCLK_UART0, "pclk_uart0", "busclk_pmu_root", 0,
765
+
RV1126B_PMUCLKGATE_CON(1), 8, GFLAGS),
766
+
COMPOSITE_NODIV(SCLK_UART0, "sclk_uart0", sclk_uart0_p, CLK_SET_RATE_PARENT,
767
+
RV1126B_PMUCLKSEL_CON(3), 0, 2, MFLAGS,
768
+
RV1126B_PMUCLKGATE_CON(1), 11, GFLAGS),
769
+
GATE(PCLK_RCOSC_CTRL, "pclk_rcosc_ctrl", "busclk_pmu_root", CLK_IS_CRITICAL,
770
+
RV1126B_PMUCLKGATE_CON(2), 0, GFLAGS),
771
+
COMPOSITE_NODIV(CLK_OSC_RCOSC_CTRL, "clk_osc_rcosc_ctrl", clk_osc_rcosc_ctrl_p, CLK_IS_CRITICAL,
772
+
RV1126B_PMUCLKSEL_CON(3), 2, 1, MFLAGS,
773
+
RV1126B_PMUCLKGATE_CON(2), 1, GFLAGS),
774
+
GATE(CLK_REF_RCOSC_CTRL, "clk_ref_rcosc_ctrl", "xin24m", CLK_IS_CRITICAL,
775
+
RV1126B_PMUCLKGATE_CON(2), 2, GFLAGS),
776
+
GATE(PCLK_IOC_PMUIO0, "pclk_ioc_pmuio0", "busclk_pmu_root", CLK_IS_CRITICAL,
777
+
RV1126B_PMUCLKGATE_CON(2), 3, GFLAGS),
778
+
GATE(CLK_REFOUT, "clk_refout", "xin24m", 0,
779
+
RV1126B_PMUCLKGATE_CON(2), 6, GFLAGS),
780
+
GATE(CLK_PREROLL, "clk_preroll", "busclk_pmu_root", 0,
781
+
RV1126B_PMUCLKGATE_CON(2), 7, GFLAGS),
782
+
GATE(CLK_PREROLL_32K, "clk_preroll_32k", "clk_32k", 0,
783
+
RV1126B_PMUCLKGATE_CON(2), 8, GFLAGS),
784
+
GATE(HCLK_PMU_SRAM, "hclk_pmu_sram", "busclk_pmu_root", CLK_IS_CRITICAL,
785
+
RV1126B_PMUCLKGATE_CON(2), 9, GFLAGS),
786
+
GATE(PCLK_WDT_LPMCU, "pclk_wdt_lpmcu", "busclk_pmu_root", 0,
787
+
RV1126B_PMUCLKGATE_CON(3), 0, GFLAGS),
788
+
COMPOSITE_NODIV(TCLK_WDT_LPMCU, "tclk_wdt_lpmcu", mux_24m_rcosc_buspmu_32k_p, 0,
789
+
RV1126B_PMUCLKSEL_CON(3), 6, 2, MFLAGS,
790
+
RV1126B_PMUCLKGATE_CON(3), 1, GFLAGS),
791
+
GATE(CLK_LPMCU, "clk_lpmcu", "busclk_pmu_root", 0,
792
+
RV1126B_PMUCLKGATE_CON(3), 2, GFLAGS),
793
+
GATE(CLK_LPMCU_RTC, "clk_lpmcu_rtc", "xin24m", 0,
794
+
RV1126B_PMUCLKGATE_CON(3), 3, GFLAGS),
795
+
GATE(PCLK_LPMCU_MAILBOX, "pclk_lpmcu_mailbox", "busclk_pmu_root", 0,
796
+
RV1126B_PMUCLKGATE_CON(3), 4, GFLAGS),
797
+
798
+
/* pd_pmu1 */
799
+
GATE(PCLK_SPI2AHB, "pclk_spi2ahb", "busclk_pmu_root", 0,
800
+
RV1126B_PMU1CLKGATE_CON(0), 0, GFLAGS),
801
+
GATE(HCLK_SPI2AHB, "hclk_spi2ahb", "busclk_pmu_root", 0,
802
+
RV1126B_PMU1CLKGATE_CON(0), 1, GFLAGS),
803
+
GATE(HCLK_FSPI1, "hclk_fspi1", "busclk_pmu_root", 0,
804
+
RV1126B_PMU1CLKGATE_CON(0), 2, GFLAGS),
805
+
GATE(HCLK_XIP_FSPI1, "hclk_xip_fspi1", "busclk_pmu_root", 0,
806
+
RV1126B_PMU1CLKGATE_CON(0), 3, GFLAGS),
807
+
COMPOSITE(SCLK_1X_FSPI1, "sclk_1x_fspi1", mux_24m_rcosc_buspmu_p, 0,
808
+
RV1126B_PMU1CLKSEL_CON(0), 0, 2, MFLAGS, 2, 3, DFLAGS,
809
+
RV1126B_PMU1CLKGATE_CON(0), 4, GFLAGS),
810
+
GATE(PCLK_IOC_PMUIO1, "pclk_ioc_pmuio1", "busclk_pmu_root", CLK_IS_CRITICAL,
811
+
RV1126B_PMU1CLKGATE_CON(0), 5, GFLAGS),
812
+
GATE(PCLK_AUDIO_ADC_PMU, "pclk_audio_adc_pmu", "busclk_pmu_root", 0,
813
+
RV1126B_PMU1CLKGATE_CON(0), 8, GFLAGS),
814
+
815
+
COMPOSITE(MCLK_LPSAI, "mclk_lpsai", mux_24m_rcosc_buspmu_p, 0,
816
+
RV1126B_PMU1CLKSEL_CON(0), 6, 2, MFLAGS, 8, 5, DFLAGS,
817
+
RV1126B_PMU1CLKGATE_CON(1), 3, GFLAGS),
818
+
GATE(MCLK_AUDIO_ADC_PMU, "mclk_audio_adc_pmu", "mclk_lpsai", CLK_IS_CRITICAL,
819
+
RV1126B_PMU1CLKGATE_CON(0), 9, GFLAGS),
820
+
FACTOR(MCLK_AUDIO_ADC_DIV4_PMU, "mclk_audio_adc_div4_pmu", "mclk_audio_adc_pmu", 0, 1, 4),
821
+
822
+
/* pd_bus */
823
+
GATE(ACLK_GIC400, "aclk_gic400", "hclk_bus_root", CLK_IS_CRITICAL,
824
+
RV1126B_BUSCLKGATE_CON(0), 8, GFLAGS),
825
+
GATE(PCLK_WDT_NS, "pclk_wdt_ns", "pclk_bus_root", 0,
826
+
RV1126B_BUSCLKGATE_CON(0), 10, GFLAGS),
827
+
GATE(TCLK_WDT_NS, "tclk_wdt_ns", "tclk_wdt_ns_src", 0,
828
+
RV1126B_BUSCLKGATE_CON(0), 11, GFLAGS),
829
+
GATE(PCLK_WDT_HPMCU, "pclk_wdt_hpmcu", "pclk_bus_root", 0,
830
+
RV1126B_BUSCLKGATE_CON(1), 0, GFLAGS),
831
+
GATE(HCLK_CACHE, "hclk_cache", "aclk_bus_root", 0,
832
+
RV1126B_BUSCLKGATE_CON(1), 2, GFLAGS),
833
+
GATE(PCLK_HPMCU_MAILBOX, "pclk_hpmcu_mailbox", "pclk_bus_root", 0,
834
+
RV1126B_BUSCLKGATE_CON(1), 3, GFLAGS),
835
+
GATE(PCLK_HPMCU_INTMUX, "pclk_hpmcu_intmux", "pclk_bus_root", 0,
836
+
RV1126B_BUSCLKGATE_CON(1), 4, GFLAGS),
837
+
GATE(CLK_HPMCU, "clk_hpmcu", "aclk_bus_root", 0,
838
+
RV1126B_BUSCLKGATE_CON(1), 5, GFLAGS),
839
+
GATE(CLK_HPMCU_RTC, "clk_hpmcu_rtc", "xin24m", 0,
840
+
RV1126B_BUSCLKGATE_CON(1), 10, GFLAGS),
841
+
GATE(PCLK_RKDMA, "pclk_rkdma", "pclk_bus_root", 0,
842
+
RV1126B_BUSCLKGATE_CON(1), 11, GFLAGS),
843
+
GATE(ACLK_RKDMA, "aclk_rkdma", "aclk_bus_root", 0,
844
+
RV1126B_BUSCLKGATE_CON(1), 12, GFLAGS),
845
+
GATE(PCLK_DCF, "pclk_dcf", "pclk_bus_root", 0,
846
+
RV1126B_BUSCLKGATE_CON(2), 0, GFLAGS),
847
+
GATE(ACLK_DCF, "aclk_dcf", "aclk_bus_root", 0,
848
+
RV1126B_BUSCLKGATE_CON(2), 1, GFLAGS),
849
+
GATE(HCLK_RGA, "hclk_rga", "hclk_bus_root", 0,
850
+
RV1126B_BUSCLKGATE_CON(2), 2, GFLAGS),
851
+
GATE(ACLK_RGA, "aclk_rga", "aclk_bus_root", 0,
852
+
RV1126B_BUSCLKGATE_CON(2), 3, GFLAGS),
853
+
GATE(CLK_CORE_RGA, "clk_core_rga", "clk_core_rga_src", 0,
854
+
RV1126B_BUSCLKGATE_CON(2), 4, GFLAGS),
855
+
GATE(PCLK_TIMER, "pclk_timer", "pclk_bus_root", 0,
856
+
RV1126B_BUSCLKGATE_CON(2), 5, GFLAGS),
857
+
COMPOSITE_NODIV(CLK_TIMER0, "clk_timer0", clk_timer0_parents_p, 0,
858
+
RV1126B_BUSCLKSEL_CON(2), 0, 2, MFLAGS,
859
+
RV1126B_BUSCLKGATE_CON(2), 6, GFLAGS),
860
+
COMPOSITE_NODIV(CLK_TIMER1, "clk_timer1", clk_timer1_parents_p, 0,
861
+
RV1126B_BUSCLKSEL_CON(2), 2, 2, MFLAGS,
862
+
RV1126B_BUSCLKGATE_CON(2), 7, GFLAGS),
863
+
COMPOSITE_NODIV(CLK_TIMER2, "clk_timer2", clk_timer2_parents_p, 0,
864
+
RV1126B_BUSCLKSEL_CON(2), 4, 2, MFLAGS,
865
+
RV1126B_BUSCLKGATE_CON(2), 8, GFLAGS),
866
+
COMPOSITE_NODIV(CLK_TIMER3, "clk_timer3", clk_timer3_parents_p, 0,
867
+
RV1126B_BUSCLKSEL_CON(2), 6, 2, MFLAGS,
868
+
RV1126B_BUSCLKGATE_CON(2), 9, GFLAGS),
869
+
COMPOSITE_NODIV(CLK_TIMER4, "clk_timer4", clk_timer4_parents_p, 0,
870
+
RV1126B_BUSCLKSEL_CON(2), 8, 2, MFLAGS,
871
+
RV1126B_BUSCLKGATE_CON(2), 10, GFLAGS),
872
+
GATE(HCLK_RKRNG_S_NS, "hclk_rkrng_s_ns", "hclk_bus_root", 0,
873
+
RV1126B_BUSCLKGATE_CON(2), 14, GFLAGS),
874
+
GATE(HCLK_RKRNG_NS, "hclk_rkrng_ns", "hclk_rkrng_s_ns", 0,
875
+
RV1126B_BUSCLKGATE_CON(2), 15, GFLAGS),
876
+
GATE(CLK_TIMER5, "clk_timer5", "clk_timer_root", CLK_IS_CRITICAL,
877
+
RV1126B_BUSCLKGATE_CON(2), 11, GFLAGS),
878
+
GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus_root", 0,
879
+
RV1126B_BUSCLKGATE_CON(3), 0, GFLAGS),
880
+
GATE(CLK_I2C0, "clk_i2c0", "clk_i2c_bus_src", 0,
881
+
RV1126B_BUSCLKGATE_CON(3), 1, GFLAGS),
882
+
GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus_root", 0,
883
+
RV1126B_BUSCLKGATE_CON(3), 2, GFLAGS),
884
+
GATE(CLK_I2C1, "clk_i2c1", "clk_i2c_bus_src", 0,
885
+
RV1126B_BUSCLKGATE_CON(3), 3, GFLAGS),
886
+
GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus_root", 0,
887
+
RV1126B_BUSCLKGATE_CON(3), 4, GFLAGS),
888
+
GATE(CLK_I2C3, "clk_i2c3", "clk_i2c_bus_src", 0,
889
+
RV1126B_BUSCLKGATE_CON(3), 5, GFLAGS),
890
+
GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus_root", 0,
891
+
RV1126B_BUSCLKGATE_CON(3), 6, GFLAGS),
892
+
GATE(CLK_I2C4, "clk_i2c4", "clk_i2c_bus_src", 0,
893
+
RV1126B_BUSCLKGATE_CON(3), 7, GFLAGS),
894
+
GATE(PCLK_I2C5, "pclk_i2c5", "pclk_bus_root", 0,
895
+
RV1126B_BUSCLKGATE_CON(3), 8, GFLAGS),
896
+
GATE(CLK_I2C5, "clk_i2c5", "clk_i2c_bus_src", 0,
897
+
RV1126B_BUSCLKGATE_CON(3), 9, GFLAGS),
898
+
GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus_root", 0,
899
+
RV1126B_BUSCLKGATE_CON(3), 10, GFLAGS),
900
+
GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus_root", 0,
901
+
RV1126B_BUSCLKGATE_CON(3), 12, GFLAGS),
902
+
GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus_root", 0,
903
+
RV1126B_BUSCLKGATE_CON(4), 0, GFLAGS),
904
+
GATE(CLK_OSC_PWM0, "clk_osc_pwm0", "xin24m", 0,
905
+
RV1126B_BUSCLKGATE_CON(4), 1, GFLAGS),
906
+
GATE(CLK_RC_PWM0, "clk_rc_pwm0", "xin24m", 0,
907
+
RV1126B_BUSCLKGATE_CON(4), 2, GFLAGS),
908
+
GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus_root", 0,
909
+
RV1126B_BUSCLKGATE_CON(4), 3, GFLAGS),
910
+
GATE(CLK_OSC_PWM2, "clk_osc_pwm2", "xin24m", 0,
911
+
RV1126B_BUSCLKGATE_CON(4), 4, GFLAGS),
912
+
GATE(CLK_RC_PWM2, "clk_rc_pwm2", "xin24m", 0,
913
+
RV1126B_BUSCLKGATE_CON(4), 5, GFLAGS),
914
+
GATE(PCLK_PWM3, "pclk_pwm3", "pclk_bus_root", 0,
915
+
RV1126B_BUSCLKGATE_CON(4), 6, GFLAGS),
916
+
GATE(CLK_OSC_PWM3, "clk_osc_pwm3", "xin24m", 0,
917
+
RV1126B_BUSCLKGATE_CON(4), 7, GFLAGS),
918
+
GATE(CLK_RC_PWM3, "clk_rc_pwm3", "xin24m", 0,
919
+
RV1126B_BUSCLKGATE_CON(4), 8, GFLAGS),
920
+
GATE(PCLK_UART1, "pclk_uart1", "pclk_bus_root", 0,
921
+
RV1126B_BUSCLKGATE_CON(4), 9, GFLAGS),
922
+
GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_root", 0,
923
+
RV1126B_BUSCLKGATE_CON(4), 10, GFLAGS),
924
+
GATE(PCLK_UART3, "pclk_uart3", "pclk_bus_root", 0,
925
+
RV1126B_BUSCLKGATE_CON(4), 11, GFLAGS),
926
+
GATE(PCLK_UART4, "pclk_uart4", "pclk_bus_root", 0,
927
+
RV1126B_BUSCLKGATE_CON(4), 12, GFLAGS),
928
+
GATE(PCLK_UART5, "pclk_uart5", "pclk_bus_root", 0,
929
+
RV1126B_BUSCLKGATE_CON(4), 13, GFLAGS),
930
+
GATE(PCLK_UART6, "pclk_uart6", "pclk_bus_root", 0,
931
+
RV1126B_BUSCLKGATE_CON(4), 14, GFLAGS),
932
+
GATE(PCLK_UART7, "pclk_uart7", "pclk_bus_root", 0,
933
+
RV1126B_BUSCLKGATE_CON(4), 15, GFLAGS),
934
+
GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus_root", CLK_IS_CRITICAL,
935
+
RV1126B_BUSCLKGATE_CON(5), 0, GFLAGS),
936
+
GATE(CLK_TSADC, "clk_tsadc", "xin24m", CLK_IS_CRITICAL,
937
+
RV1126B_BUSCLKGATE_CON(5), 1, GFLAGS),
938
+
GATE(HCLK_SAI0, "hclk_sai0", "hclk_bus_root", 0,
939
+
RV1126B_BUSCLKGATE_CON(5), 2, GFLAGS),
940
+
GATE(HCLK_SAI1, "hclk_sai1", "hclk_bus_root", 0,
941
+
RV1126B_BUSCLKGATE_CON(5), 4, GFLAGS),
942
+
GATE(HCLK_SAI2, "hclk_sai2", "hclk_bus_root", 0,
943
+
RV1126B_BUSCLKGATE_CON(5), 6, GFLAGS),
944
+
GATE(HCLK_RKDSM, "hclk_rkdsm", "hclk_bus_root", 0,
945
+
RV1126B_BUSCLKGATE_CON(5), 8, GFLAGS),
946
+
GATE(MCLK_RKDSM, "mclk_rkdsm", "mclk_sai2", 0,
947
+
RV1126B_BUSCLKGATE_CON(5), 9, GFLAGS),
948
+
GATE(HCLK_PDM, "hclk_pdm", "hclk_bus_root", 0,
949
+
RV1126B_BUSCLKGATE_CON(5), 10, GFLAGS),
950
+
GATE(HCLK_ASRC0, "hclk_asrc0", "hclk_bus_root", 0,
951
+
RV1126B_BUSCLKGATE_CON(5), 11, GFLAGS),
952
+
GATE(HCLK_ASRC1, "hclk_asrc1", "hclk_bus_root", 0,
953
+
RV1126B_BUSCLKGATE_CON(5), 12, GFLAGS),
954
+
GATE(PCLK_AUDIO_ADC_BUS, "pclk_audio_adc_bus", "pclk_bus_root", 0,
955
+
RV1126B_BUSCLKGATE_CON(5), 13, GFLAGS),
956
+
GATE(MCLK_AUDIO_ADC_BUS, "mclk_audio_adc_bus", "mclk_sai2", 0,
957
+
RV1126B_BUSCLKGATE_CON(5), 14, GFLAGS),
958
+
FACTOR(MCLK_AUDIO_ADC_DIV4_BUS, "mclk_audio_adc_div4_bus", "mclk_audio_adc_bus", 0, 1, 4),
959
+
GATE(PCLK_RKCE, "pclk_rkce", "pclk_bus_root", CLK_IS_CRITICAL,
960
+
RV1126B_BUSCLKGATE_CON(6), 0, GFLAGS),
961
+
GATE(HCLK_NS_RKCE, "hclk_ns_rkce", "hclk_bus_root", 0,
962
+
RV1126B_BUSCLKGATE_CON(6), 1, GFLAGS),
963
+
GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_bus_root", 0,
964
+
RV1126B_BUSCLKGATE_CON(6), 2, GFLAGS),
965
+
GATE(CLK_SBPI_OTPC_NS, "clk_sbpi_otpc_ns", "xin24m", 0,
966
+
RV1126B_BUSCLKGATE_CON(6), 3, GFLAGS),
967
+
COMPOSITE_NOMUX(CLK_USER_OTPC_NS, "clk_user_otpc_ns", "xin24m", 0,
968
+
RV1126B_BUSCLKSEL_CON(2), 12, 3, DFLAGS,
969
+
RV1126B_BUSCLKGATE_CON(6), 4, GFLAGS),
970
+
GATE(PCLK_OTP_MASK, "pclk_otp_mask", "pclk_bus_root", 0,
971
+
RV1126B_BUSCLKGATE_CON(6), 6, GFLAGS),
972
+
GATE(CLK_TSADC_PHYCTRL, "clk_tsadc_phyctrl", "xin24m", CLK_IS_CRITICAL,
973
+
RV1126B_BUSCLKGATE_CON(6), 8, GFLAGS),
974
+
MUX(LRCK_SRC_ASRC0, "lrck_src_asrc0", lrck_src_asrc_p, 0,
975
+
RV1126B_BUSCLKSEL_CON(3), 0, 3, MFLAGS),
976
+
MUX(LRCK_DST_ASRC0, "lrck_dst_asrc0", lrck_src_asrc_p, 0,
977
+
RV1126B_BUSCLKSEL_CON(3), 4, 3, MFLAGS),
978
+
MUX(LRCK_SRC_ASRC1, "lrck_src_asrc1", lrck_src_asrc_p, 0,
979
+
RV1126B_BUSCLKSEL_CON(3), 8, 3, MFLAGS),
980
+
MUX(LRCK_DST_ASRC1, "lrck_dst_asrc1", lrck_src_asrc_p, 0,
981
+
RV1126B_BUSCLKSEL_CON(3), 12, 3, MFLAGS),
982
+
GATE(ACLK_NSRKCE, "aclk_nsrkce", "aclk_rkce_src", 0,
983
+
RV1126B_BUSCLKGATE_CON(2), 12, GFLAGS),
984
+
GATE(CLK_PKA_NSRKCE, "clk_pka_nsrkce", "clk_pka_rkce_src", 0,
985
+
RV1126B_BUSCLKGATE_CON(2), 13, GFLAGS),
986
+
987
+
/* pd_peri */
988
+
DIV(PCLK_RTC_ROOT, "pclk_rtc_root", "pclk_peri_root", 0,
989
+
RV1126B_PERICLKSEL_CON(0), 0, 2, DFLAGS),
990
+
GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_peri_root", 0,
991
+
RV1126B_PERICLKGATE_CON(0), 5, GFLAGS),
992
+
GATE(DBCLK_GPIO1, "dbclk_gpio1", "xin24m", 0,
993
+
RV1126B_PERICLKGATE_CON(0), 6, GFLAGS),
994
+
GATE(PCLK_IOC_VCCIO1, "pclk_ioc_vccio1", "pclk_peri_root", CLK_IS_CRITICAL,
995
+
RV1126B_PERICLKGATE_CON(0), 7, GFLAGS),
996
+
GATE(ACLK_USB3OTG, "aclk_usb3otg", "aclk_peri_root", 0,
997
+
RV1126B_PERICLKGATE_CON(0), 8, GFLAGS),
998
+
GATE(CLK_REF_USB3OTG, "clk_ref_usb3otg", "xin24m", 0,
999
+
RV1126B_PERICLKGATE_CON(0), 9, GFLAGS),
1000
+
GATE(CLK_SUSPEND_USB3OTG, "clk_suspend_usb3otg", "xin24m", 0,
1001
+
RV1126B_PERICLKGATE_CON(0), 10, GFLAGS),
1002
+
GATE(HCLK_USB2HOST, "hclk_usb2host", "aclk_peri_root", 0,
1003
+
RV1126B_PERICLKGATE_CON(0), 11, GFLAGS),
1004
+
GATE(HCLK_ARB_USB2HOST, "hclk_arb_usb2host", "aclk_peri_root", 0,
1005
+
RV1126B_PERICLKGATE_CON(0), 12, GFLAGS),
1006
+
GATE(PCLK_RTC_TEST, "pclk_rtc_test", "pclk_rtc_root", 0,
1007
+
RV1126B_PERICLKGATE_CON(0), 13, GFLAGS),
1008
+
GATE(HCLK_EMMC, "hclk_emmc", "aclk_peri_root", 0,
1009
+
RV1126B_PERICLKGATE_CON(1), 0, GFLAGS),
1010
+
GATE(HCLK_FSPI0, "hclk_fspi0", "aclk_peri_root", 0,
1011
+
RV1126B_PERICLKGATE_CON(1), 1, GFLAGS),
1012
+
GATE(HCLK_XIP_FSPI0, "hclk_xip_fspi0", "aclk_peri_root", 0,
1013
+
RV1126B_PERICLKGATE_CON(1), 2, GFLAGS),
1014
+
GATE(PCLK_PIPEPHY, "pclk_pipephy", "pclk_peri_root", 0,
1015
+
RV1126B_PERICLKGATE_CON(1), 8, GFLAGS),
1016
+
GATE(PCLK_USB2PHY, "pclk_usb2phy", "pclk_peri_root", 0,
1017
+
RV1126B_PERICLKGATE_CON(1), 10, GFLAGS),
1018
+
COMPOSITE_NOMUX(CLK_REF_PIPEPHY_CPLL_SRC, "clk_ref_pipephy_cpll_src", "cpll", 0,
1019
+
RV1126B_PERICLKSEL_CON(1), 0, 6, DFLAGS,
1020
+
RV1126B_PERICLKGATE_CON(1), 14, GFLAGS),
1021
+
MUX(CLK_REF_PIPEPHY, "clk_ref_pipephy", clk_ref_pipephy_p, 0,
1022
+
RV1126B_PERICLKSEL_CON(1), 12, 1, MFLAGS),
1023
+
};
1024
+
1025
+
static struct rockchip_clk_branch rv1126b_armclk __initdata =
1026
+
MUX(ARMCLK, "armclk", mux_armclk_p, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
1027
+
RV1126B_CORECLKSEL_CON(0), 1, 1, MFLAGS);
1028
+
1029
+
static void __init rv1126b_clk_init(struct device_node *np)
1030
+
{
1031
+
struct rockchip_clk_provider *ctx;
1032
+
void __iomem *reg_base;
1033
+
unsigned long clk_nr_clks;
1034
+
1035
+
clk_nr_clks = rockchip_clk_find_max_clk_id(rv1126b_clk_branches,
1036
+
ARRAY_SIZE(rv1126b_clk_branches)) + 1;
1037
+
1038
+
reg_base = of_iomap(np, 0);
1039
+
if (!reg_base) {
1040
+
pr_err("%s: could not map cru region\n", __func__);
1041
+
return;
1042
+
}
1043
+
1044
+
ctx = rockchip_clk_init(np, reg_base, clk_nr_clks);
1045
+
if (IS_ERR(ctx)) {
1046
+
pr_err("%s: rockchip clk init failed\n", __func__);
1047
+
iounmap(reg_base);
1048
+
return;
1049
+
}
1050
+
1051
+
rockchip_clk_register_plls(ctx, rv1126b_pll_clks,
1052
+
ARRAY_SIZE(rv1126b_pll_clks),
1053
+
0);
1054
+
1055
+
rockchip_clk_register_branches(ctx, rv1126b_clk_branches,
1056
+
ARRAY_SIZE(rv1126b_clk_branches));
1057
+
1058
+
rockchip_clk_register_armclk_multi_pll(ctx, &rv1126b_armclk,
1059
+
rv1126b_cpuclk_rates,
1060
+
ARRAY_SIZE(rv1126b_cpuclk_rates));
1061
+
1062
+
rv1126b_rst_init(np, reg_base);
1063
+
1064
+
rockchip_register_restart_notifier(ctx, RV1126B_GLB_SRST_FST, NULL);
1065
+
1066
+
rockchip_clk_of_add_provider(np, ctx);
1067
+
1068
+
/* pvtpll src init */
1069
+
writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1126B_CORECLKSEL_CON(0));
1070
+
writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1126B_NPUCLKSEL_CON(0));
1071
+
writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1126B_VICLKSEL_CON(0));
1072
+
writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1126B_VEPUCLKSEL_CON(0));
1073
+
writel_relaxed(PVTPLL_SRC_SEL_PVTPLL, reg_base + RV1126B_VCPCLKSEL_CON(0));
1074
+
}
1075
+
1076
+
CLK_OF_DECLARE(rv1126b_cru, "rockchip,rv1126b-cru", rv1126b_clk_init);
1077
+
1078
+
struct clk_rv1126b_inits {
1079
+
void (*inits)(struct device_node *np);
1080
+
};
1081
+
1082
+
static const struct clk_rv1126b_inits clk_rv1126b_init = {
1083
+
.inits = rv1126b_clk_init,
1084
+
};
1085
+
1086
+
static const struct of_device_id clk_rv1126b_match_table[] = {
1087
+
{
1088
+
.compatible = "rockchip,rv1126b-cru",
1089
+
.data = &clk_rv1126b_init,
1090
+
},
1091
+
{ }
1092
+
};
1093
+
1094
+
static int clk_rv1126b_probe(struct platform_device *pdev)
1095
+
{
1096
+
const struct clk_rv1126b_inits *init_data;
1097
+
struct device *dev = &pdev->dev;
1098
+
1099
+
init_data = device_get_match_data(dev);
1100
+
if (!init_data)
1101
+
return -EINVAL;
1102
+
1103
+
if (init_data->inits)
1104
+
init_data->inits(dev->of_node);
1105
+
1106
+
return 0;
1107
+
}
1108
+
1109
+
static struct platform_driver clk_rv1126b_driver = {
1110
+
.probe = clk_rv1126b_probe,
1111
+
.driver = {
1112
+
.name = "clk-rv1126b",
1113
+
.of_match_table = clk_rv1126b_match_table,
1114
+
.suppress_bind_attrs = true,
1115
+
},
1116
+
};
1117
+
builtin_platform_driver_probe(clk_rv1126b_driver, clk_rv1126b_probe);
+24
drivers/clk/rockchip/clk.c
+24
drivers/clk/rockchip/clk.c
···
722
722
}
723
723
EXPORT_SYMBOL_GPL(rockchip_clk_register_armclk);
724
724
725
+
void rockchip_clk_register_armclk_multi_pll(struct rockchip_clk_provider *ctx,
726
+
struct rockchip_clk_branch *list,
727
+
const struct rockchip_cpuclk_rate_table *rates,
728
+
int nrates)
729
+
{
730
+
struct clk *clk;
731
+
732
+
clk = rockchip_clk_register_cpuclk_multi_pll(list->name, list->parent_names,
733
+
list->num_parents, ctx->reg_base,
734
+
list->muxdiv_offset, list->mux_shift,
735
+
list->mux_width, list->mux_flags,
736
+
list->div_offset, list->div_shift,
737
+
list->div_width, list->div_flags,
738
+
list->flags, &ctx->lock, rates, nrates);
739
+
if (IS_ERR(clk)) {
740
+
pr_err("%s: failed to register clock %s: %ld\n",
741
+
__func__, list->name, PTR_ERR(clk));
742
+
return;
743
+
}
744
+
745
+
rockchip_clk_set_lookup(ctx, clk, list->id);
746
+
}
747
+
EXPORT_SYMBOL_GPL(rockchip_clk_register_armclk_multi_pll);
748
+
725
749
void rockchip_clk_protect_critical(const char *const clocks[],
726
750
int nclocks)
727
751
{
+96
drivers/clk/rockchip/clk.h
+96
drivers/clk/rockchip/clk.h
···
99
99
#define RV1126_EMMC_CON0 0x450
100
100
#define RV1126_EMMC_CON1 0x454
101
101
102
+
#define RV1126B_TOPCRU_BASE 0x0
103
+
#define RV1126B_BUSCRU_BASE 0x10000
104
+
#define RV1126B_PERICRU_BASE 0x20000
105
+
#define RV1126B_CORECRU_BASE 0x30000
106
+
#define RV1126B_PMUCRU_BASE 0x40000
107
+
#define RV1126B_PMU1CRU_BASE 0x50000
108
+
#define RV1126B_DDRCRU_BASE 0x60000
109
+
#define RV1126B_SUBDDRCRU_BASE 0x68000
110
+
#define RV1126B_VICRU_BASE 0x70000
111
+
#define RV1126B_VEPUCRU_BASE 0x80000
112
+
#define RV1126B_NPUCRU_BASE 0x90000
113
+
#define RV1126B_VDOCRU_BASE 0xA0000
114
+
#define RV1126B_VCPCRU_BASE 0xB0000
115
+
116
+
#define RV1126B_PLL_CON(x) ((x) * 0x4 + RV1126B_TOPCRU_BASE)
117
+
#define RV1126B_MODE_CON (0x280 + RV1126B_TOPCRU_BASE)
118
+
#define RV1126B_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_TOPCRU_BASE)
119
+
#define RV1126B_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_TOPCRU_BASE)
120
+
#define RV1126B_SOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_TOPCRU_BASE)
121
+
#define RV1126B_GLB_SRST_FST (0xc08 + RV1126B_TOPCRU_BASE)
122
+
#define RV1126B_GLB_SRST_SND (0xc0c + RV1126B_TOPCRU_BASE)
123
+
#define RV1126B_CLK_CM_FRAC0_DIV_H (0xcc0 + RV1126B_TOPCRU_BASE)
124
+
#define RV1126B_CLK_CM_FRAC1_DIV_H (0xcc4 + RV1126B_TOPCRU_BASE)
125
+
#define RV1126B_CLK_CM_FRAC2_DIV_H (0xcc8 + RV1126B_TOPCRU_BASE)
126
+
#define RV1126B_CLK_UART_FRAC0_DIV_H (0xccc + RV1126B_TOPCRU_BASE)
127
+
#define RV1126B_CLK_UART_FRAC1_DIV_H (0xcd0 + RV1126B_TOPCRU_BASE)
128
+
#define RV1126B_CLK_AUDIO_FRAC0_DIV_H (0xcd4 + RV1126B_TOPCRU_BASE)
129
+
#define RV1126B_CLK_AUDIO_FRAC1_DIV_H (0xcd8 + RV1126B_TOPCRU_BASE)
130
+
#define RV1126B_BUSCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_BUSCRU_BASE)
131
+
#define RV1126B_BUSCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_BUSCRU_BASE)
132
+
#define RV1126B_BUSSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_BUSCRU_BASE)
133
+
#define RV1126B_PERIPLL_CON(x) ((x) * 0x4 + RV1126B_PERICRU_BASE)
134
+
#define RV1126B_PERICLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_PERICRU_BASE)
135
+
#define RV1126B_PERICLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_PERICRU_BASE)
136
+
#define RV1126B_PERISOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_PERICRU_BASE)
137
+
#define RV1126B_CORECLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_CORECRU_BASE)
138
+
#define RV1126B_CORECLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_CORECRU_BASE)
139
+
#define RV1126B_CORESOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_CORECRU_BASE)
140
+
#define RV1126B_PMUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_PMUCRU_BASE)
141
+
#define RV1126B_PMUCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_PMUCRU_BASE)
142
+
#define RV1126B_PMUSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_PMUCRU_BASE)
143
+
#define RV1126B_PMU1CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_PMU1CRU_BASE)
144
+
#define RV1126B_PMU1CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_PMU1CRU_BASE)
145
+
#define RV1126B_PMU1SOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_PMU1CRU_BASE)
146
+
#define RV1126B_DDRCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_DDRCRU_BASE)
147
+
#define RV1126B_DDRCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_DDRCRU_BASE)
148
+
#define RV1126B_DDRSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_DDRCRU_BASE)
149
+
#define RV1126B_SUBDDRPLL_CON(x) ((x) * 0x4 + RV1126B_SUBDDRCRU_BASE)
150
+
#define RV1126B_SUBDDRCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_SUBDDRCRU_BASE)
151
+
#define RV1126B_SUBDDRCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_SUBDDRCRU_BASE)
152
+
#define RV1126B_SUBDDRSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_SUBDDRCRU_BASE)
153
+
#define RV1126B_VICLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_VICRU_BASE)
154
+
#define RV1126B_VICLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_VICRU_BASE)
155
+
#define RV1126B_VISOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_VICRU_BASE)
156
+
#define RV1126B_VEPUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_VEPUCRU_BASE)
157
+
#define RV1126B_VEPUCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_VEPUCRU_BASE)
158
+
#define RV1126B_VEPUSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_VEPUCRU_BASE)
159
+
#define RV1126B_NPUCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_NPUCRU_BASE)
160
+
#define RV1126B_NPUCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_NPUCRU_BASE)
161
+
#define RV1126B_NPUSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_NPUCRU_BASE)
162
+
#define RV1126B_VDOCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_VDOCRU_BASE)
163
+
#define RV1126B_VDOCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_VDOCRU_BASE)
164
+
#define RV1126B_VDOSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_VDOCRU_BASE)
165
+
#define RV1126B_VCPCLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1126B_VCPCRU_BASE)
166
+
#define RV1126B_VCPCLKGATE_CON(x) ((x) * 0x4 + 0x800 + RV1126B_VCPCRU_BASE)
167
+
#define RV1126B_VCPSOFTRST_CON(x) ((x) * 0x4 + 0xa00 + RV1126B_VCPCRU_BASE)
168
+
102
169
#define RK2928_PLL_CON(x) ((x) * 0x4)
103
170
#define RK2928_MODE_CON 0x40
104
171
#define RK2928_CLKSEL_CON(x) ((x) * 0x4 + 0x44)
···
274
207
#define RK3399_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x80)
275
208
#define RK3399_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x100)
276
209
#define RK3399_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x110)
210
+
211
+
#define RK3506_PMU_CRU_BASE 0x10000
212
+
#define RK3506_PLL_CON(x) ((x) * 0x4 + RK3506_PMU_CRU_BASE)
213
+
#define RK3506_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
214
+
#define RK3506_CLKGATE_CON(x) ((x) * 0x4 + 0x800)
215
+
#define RK3506_SOFTRST_CON(x) ((x) * 0x4 + 0xa00)
216
+
#define RK3506_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3506_PMU_CRU_BASE)
217
+
#define RK3506_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3506_PMU_CRU_BASE)
218
+
#define RK3506_MODE_CON 0x280
219
+
#define RK3506_GLB_CNT_TH 0xc00
220
+
#define RK3506_GLB_SRST_FST 0xc08
221
+
#define RK3506_GLB_SRST_SND 0xc0c
277
222
278
223
#define RK3528_PMU_CRU_BASE 0x10000
279
224
#define RK3528_PCIE_CRU_BASE 0x20000
···
700
621
const struct rockchip_cpuclk_reg_data *reg_data,
701
622
const struct rockchip_cpuclk_rate_table *rates,
702
623
int nrates, void __iomem *reg_base, spinlock_t *lock);
624
+
625
+
struct clk *rockchip_clk_register_cpuclk_multi_pll(const char *name,
626
+
const char *const *parent_names,
627
+
u8 num_parents, void __iomem *base,
628
+
int muxdiv_offset, u8 mux_shift,
629
+
u8 mux_width, u8 mux_flags,
630
+
int div_offset, u8 div_shift,
631
+
u8 div_width, u8 div_flags,
632
+
unsigned long flags, spinlock_t *lock,
633
+
const struct rockchip_cpuclk_rate_table *rates,
634
+
int nrates);
703
635
704
636
struct clk *rockchip_clk_register_mmc(const char *name,
705
637
const char *const *parent_names, u8 num_parents,
···
1298
1208
const struct rockchip_cpuclk_reg_data *reg_data,
1299
1209
const struct rockchip_cpuclk_rate_table *rates,
1300
1210
int nrates);
1211
+
void rockchip_clk_register_armclk_multi_pll(struct rockchip_clk_provider *ctx,
1212
+
struct rockchip_clk_branch *list,
1213
+
const struct rockchip_cpuclk_rate_table *rates,
1214
+
int nrates);
1301
1215
void rockchip_clk_protect_critical(const char *const clocks[], int nclocks);
1302
1216
void rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx,
1303
1217
unsigned int reg, void (*cb)(void));
···
1340
1246
return rockchip_register_softrst_lut(np, NULL, num_regs, base, flags);
1341
1247
}
1342
1248
1249
+
void rv1126b_rst_init(struct device_node *np, void __iomem *reg_base);
1250
+
void rk3506_rst_init(struct device_node *np, void __iomem *reg_base);
1343
1251
void rk3528_rst_init(struct device_node *np, void __iomem *reg_base);
1344
1252
void rk3562_rst_init(struct device_node *np, void __iomem *reg_base);
1345
1253
void rk3576_rst_init(struct device_node *np, void __iomem *reg_base);
+226
drivers/clk/rockchip/rst-rk3506.c
+226
drivers/clk/rockchip/rst-rk3506.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-or-later
2
+
/*
3
+
* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
4
+
* Author: Finley Xiao <finley.xiao@rock-chips.com>
5
+
*/
6
+
7
+
#include <linux/module.h>
8
+
#include <linux/of.h>
9
+
#include <dt-bindings/reset/rockchip,rk3506-cru.h>
10
+
#include "clk.h"
11
+
12
+
/* 0xFF9A0000 + 0x0A00 */
13
+
#define RK3506_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit)
14
+
15
+
/* mapping table for reset ID to register offset */
16
+
static const int rk3506_register_offset[] = {
17
+
/* CRU-->SOFTRST_CON00 */
18
+
RK3506_CRU_RESET_OFFSET(SRST_NCOREPORESET0_AC, 0, 0),
19
+
RK3506_CRU_RESET_OFFSET(SRST_NCOREPORESET1_AC, 0, 1),
20
+
RK3506_CRU_RESET_OFFSET(SRST_NCOREPORESET2_AC, 0, 2),
21
+
RK3506_CRU_RESET_OFFSET(SRST_NCORESET0_AC, 0, 4),
22
+
RK3506_CRU_RESET_OFFSET(SRST_NCORESET1_AC, 0, 5),
23
+
RK3506_CRU_RESET_OFFSET(SRST_NCORESET2_AC, 0, 6),
24
+
RK3506_CRU_RESET_OFFSET(SRST_NL2RESET_AC, 0, 8),
25
+
RK3506_CRU_RESET_OFFSET(SRST_A_CORE_BIU_AC, 0, 9),
26
+
RK3506_CRU_RESET_OFFSET(SRST_H_M0_AC, 0, 10),
27
+
28
+
/* CRU-->SOFTRST_CON02 */
29
+
RK3506_CRU_RESET_OFFSET(SRST_NDBGRESET, 2, 10),
30
+
RK3506_CRU_RESET_OFFSET(SRST_P_CORE_BIU, 2, 14),
31
+
RK3506_CRU_RESET_OFFSET(SRST_PMU, 2, 15),
32
+
33
+
/* CRU-->SOFTRST_CON03 */
34
+
RK3506_CRU_RESET_OFFSET(SRST_P_DBG, 3, 1),
35
+
RK3506_CRU_RESET_OFFSET(SRST_POT_DBG, 3, 2),
36
+
RK3506_CRU_RESET_OFFSET(SRST_P_CORE_GRF, 3, 4),
37
+
RK3506_CRU_RESET_OFFSET(SRST_CORE_EMA_DETECT, 3, 6),
38
+
RK3506_CRU_RESET_OFFSET(SRST_REF_PVTPLL_CORE, 3, 7),
39
+
RK3506_CRU_RESET_OFFSET(SRST_P_GPIO1, 3, 8),
40
+
RK3506_CRU_RESET_OFFSET(SRST_DB_GPIO1, 3, 9),
41
+
42
+
/* CRU-->SOFTRST_CON04 */
43
+
RK3506_CRU_RESET_OFFSET(SRST_A_CORE_PERI_BIU, 4, 3),
44
+
RK3506_CRU_RESET_OFFSET(SRST_A_DSMC, 4, 5),
45
+
RK3506_CRU_RESET_OFFSET(SRST_P_DSMC, 4, 6),
46
+
RK3506_CRU_RESET_OFFSET(SRST_FLEXBUS, 4, 7),
47
+
RK3506_CRU_RESET_OFFSET(SRST_A_FLEXBUS, 4, 9),
48
+
RK3506_CRU_RESET_OFFSET(SRST_H_FLEXBUS, 4, 10),
49
+
RK3506_CRU_RESET_OFFSET(SRST_A_DSMC_SLV, 4, 11),
50
+
RK3506_CRU_RESET_OFFSET(SRST_H_DSMC_SLV, 4, 12),
51
+
RK3506_CRU_RESET_OFFSET(SRST_DSMC_SLV, 4, 13),
52
+
53
+
/* CRU-->SOFTRST_CON05 */
54
+
RK3506_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 5, 3),
55
+
RK3506_CRU_RESET_OFFSET(SRST_H_BUS_BIU, 5, 4),
56
+
RK3506_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 5, 5),
57
+
RK3506_CRU_RESET_OFFSET(SRST_A_SYSRAM, 5, 6),
58
+
RK3506_CRU_RESET_OFFSET(SRST_H_SYSRAM, 5, 7),
59
+
RK3506_CRU_RESET_OFFSET(SRST_A_DMAC0, 5, 8),
60
+
RK3506_CRU_RESET_OFFSET(SRST_A_DMAC1, 5, 9),
61
+
RK3506_CRU_RESET_OFFSET(SRST_H_M0, 5, 10),
62
+
RK3506_CRU_RESET_OFFSET(SRST_M0_JTAG, 5, 11),
63
+
RK3506_CRU_RESET_OFFSET(SRST_H_CRYPTO, 5, 15),
64
+
65
+
/* CRU-->SOFTRST_CON06 */
66
+
RK3506_CRU_RESET_OFFSET(SRST_H_RNG, 6, 0),
67
+
RK3506_CRU_RESET_OFFSET(SRST_P_BUS_GRF, 6, 1),
68
+
RK3506_CRU_RESET_OFFSET(SRST_P_TIMER0, 6, 2),
69
+
RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH0, 6, 3),
70
+
RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH1, 6, 4),
71
+
RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH2, 6, 5),
72
+
RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH3, 6, 6),
73
+
RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH4, 6, 7),
74
+
RK3506_CRU_RESET_OFFSET(SRST_TIMER0_CH5, 6, 8),
75
+
RK3506_CRU_RESET_OFFSET(SRST_P_WDT0, 6, 9),
76
+
RK3506_CRU_RESET_OFFSET(SRST_T_WDT0, 6, 10),
77
+
RK3506_CRU_RESET_OFFSET(SRST_P_WDT1, 6, 11),
78
+
RK3506_CRU_RESET_OFFSET(SRST_T_WDT1, 6, 12),
79
+
RK3506_CRU_RESET_OFFSET(SRST_P_MAILBOX, 6, 13),
80
+
RK3506_CRU_RESET_OFFSET(SRST_P_INTMUX, 6, 14),
81
+
RK3506_CRU_RESET_OFFSET(SRST_P_SPINLOCK, 6, 15),
82
+
83
+
/* CRU-->SOFTRST_CON07 */
84
+
RK3506_CRU_RESET_OFFSET(SRST_P_DDRC, 7, 0),
85
+
RK3506_CRU_RESET_OFFSET(SRST_H_DDRPHY, 7, 1),
86
+
RK3506_CRU_RESET_OFFSET(SRST_P_DDRMON, 7, 2),
87
+
RK3506_CRU_RESET_OFFSET(SRST_DDRMON_OSC, 7, 3),
88
+
RK3506_CRU_RESET_OFFSET(SRST_P_DDR_LPC, 7, 4),
89
+
RK3506_CRU_RESET_OFFSET(SRST_H_USBOTG0, 7, 5),
90
+
RK3506_CRU_RESET_OFFSET(SRST_USBOTG0_ADP, 7, 7),
91
+
RK3506_CRU_RESET_OFFSET(SRST_H_USBOTG1, 7, 8),
92
+
RK3506_CRU_RESET_OFFSET(SRST_USBOTG1_ADP, 7, 10),
93
+
RK3506_CRU_RESET_OFFSET(SRST_P_USBPHY, 7, 11),
94
+
RK3506_CRU_RESET_OFFSET(SRST_USBPHY_POR, 7, 12),
95
+
RK3506_CRU_RESET_OFFSET(SRST_USBPHY_OTG0, 7, 13),
96
+
RK3506_CRU_RESET_OFFSET(SRST_USBPHY_OTG1, 7, 14),
97
+
98
+
/* CRU-->SOFTRST_CON08 */
99
+
RK3506_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 8, 0),
100
+
RK3506_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 8, 1),
101
+
102
+
/* CRU-->SOFTRST_CON09 */
103
+
RK3506_CRU_RESET_OFFSET(SRST_USBOTG0_UTMI, 9, 0),
104
+
RK3506_CRU_RESET_OFFSET(SRST_USBOTG1_UTMI, 9, 1),
105
+
106
+
/* CRU-->SOFTRST_CON10 */
107
+
RK3506_CRU_RESET_OFFSET(SRST_A_DDRC_0, 10, 0),
108
+
RK3506_CRU_RESET_OFFSET(SRST_A_DDRC_1, 10, 1),
109
+
RK3506_CRU_RESET_OFFSET(SRST_A_DDR_BIU, 10, 2),
110
+
RK3506_CRU_RESET_OFFSET(SRST_DDRC, 10, 3),
111
+
RK3506_CRU_RESET_OFFSET(SRST_DDRMON, 10, 4),
112
+
113
+
/* CRU-->SOFTRST_CON11 */
114
+
RK3506_CRU_RESET_OFFSET(SRST_H_LSPERI_BIU, 11, 2),
115
+
RK3506_CRU_RESET_OFFSET(SRST_P_UART0, 11, 4),
116
+
RK3506_CRU_RESET_OFFSET(SRST_P_UART1, 11, 5),
117
+
RK3506_CRU_RESET_OFFSET(SRST_P_UART2, 11, 6),
118
+
RK3506_CRU_RESET_OFFSET(SRST_P_UART3, 11, 7),
119
+
RK3506_CRU_RESET_OFFSET(SRST_P_UART4, 11, 8),
120
+
RK3506_CRU_RESET_OFFSET(SRST_UART0, 11, 9),
121
+
RK3506_CRU_RESET_OFFSET(SRST_UART1, 11, 10),
122
+
RK3506_CRU_RESET_OFFSET(SRST_UART2, 11, 11),
123
+
RK3506_CRU_RESET_OFFSET(SRST_UART3, 11, 12),
124
+
RK3506_CRU_RESET_OFFSET(SRST_UART4, 11, 13),
125
+
RK3506_CRU_RESET_OFFSET(SRST_P_I2C0, 11, 14),
126
+
RK3506_CRU_RESET_OFFSET(SRST_I2C0, 11, 15),
127
+
128
+
/* CRU-->SOFTRST_CON12 */
129
+
RK3506_CRU_RESET_OFFSET(SRST_P_I2C1, 12, 0),
130
+
RK3506_CRU_RESET_OFFSET(SRST_I2C1, 12, 1),
131
+
RK3506_CRU_RESET_OFFSET(SRST_P_I2C2, 12, 2),
132
+
RK3506_CRU_RESET_OFFSET(SRST_I2C2, 12, 3),
133
+
RK3506_CRU_RESET_OFFSET(SRST_P_PWM1, 12, 4),
134
+
RK3506_CRU_RESET_OFFSET(SRST_PWM1, 12, 5),
135
+
RK3506_CRU_RESET_OFFSET(SRST_P_SPI0, 12, 10),
136
+
RK3506_CRU_RESET_OFFSET(SRST_SPI0, 12, 11),
137
+
RK3506_CRU_RESET_OFFSET(SRST_P_SPI1, 12, 12),
138
+
RK3506_CRU_RESET_OFFSET(SRST_SPI1, 12, 13),
139
+
RK3506_CRU_RESET_OFFSET(SRST_P_GPIO2, 12, 14),
140
+
RK3506_CRU_RESET_OFFSET(SRST_DB_GPIO2, 12, 15),
141
+
142
+
/* CRU-->SOFTRST_CON13 */
143
+
RK3506_CRU_RESET_OFFSET(SRST_P_GPIO3, 13, 0),
144
+
RK3506_CRU_RESET_OFFSET(SRST_DB_GPIO3, 13, 1),
145
+
RK3506_CRU_RESET_OFFSET(SRST_P_GPIO4, 13, 2),
146
+
RK3506_CRU_RESET_OFFSET(SRST_DB_GPIO4, 13, 3),
147
+
RK3506_CRU_RESET_OFFSET(SRST_H_CAN0, 13, 4),
148
+
RK3506_CRU_RESET_OFFSET(SRST_CAN0, 13, 5),
149
+
RK3506_CRU_RESET_OFFSET(SRST_H_CAN1, 13, 6),
150
+
RK3506_CRU_RESET_OFFSET(SRST_CAN1, 13, 7),
151
+
RK3506_CRU_RESET_OFFSET(SRST_H_PDM, 13, 8),
152
+
RK3506_CRU_RESET_OFFSET(SRST_M_PDM, 13, 9),
153
+
RK3506_CRU_RESET_OFFSET(SRST_PDM, 13, 10),
154
+
RK3506_CRU_RESET_OFFSET(SRST_SPDIFTX, 13, 11),
155
+
RK3506_CRU_RESET_OFFSET(SRST_H_SPDIFTX, 13, 12),
156
+
RK3506_CRU_RESET_OFFSET(SRST_H_SPDIFRX, 13, 13),
157
+
RK3506_CRU_RESET_OFFSET(SRST_SPDIFRX, 13, 14),
158
+
RK3506_CRU_RESET_OFFSET(SRST_M_SAI0, 13, 15),
159
+
160
+
/* CRU-->SOFTRST_CON14 */
161
+
RK3506_CRU_RESET_OFFSET(SRST_H_SAI0, 14, 0),
162
+
RK3506_CRU_RESET_OFFSET(SRST_M_SAI1, 14, 2),
163
+
RK3506_CRU_RESET_OFFSET(SRST_H_SAI1, 14, 3),
164
+
RK3506_CRU_RESET_OFFSET(SRST_H_ASRC0, 14, 5),
165
+
RK3506_CRU_RESET_OFFSET(SRST_ASRC0, 14, 6),
166
+
RK3506_CRU_RESET_OFFSET(SRST_H_ASRC1, 14, 7),
167
+
RK3506_CRU_RESET_OFFSET(SRST_ASRC1, 14, 8),
168
+
169
+
/* CRU-->SOFTRST_CON17 */
170
+
RK3506_CRU_RESET_OFFSET(SRST_H_HSPERI_BIU, 17, 4),
171
+
RK3506_CRU_RESET_OFFSET(SRST_H_SDMMC, 17, 7),
172
+
RK3506_CRU_RESET_OFFSET(SRST_H_FSPI, 17, 8),
173
+
RK3506_CRU_RESET_OFFSET(SRST_S_FSPI, 17, 9),
174
+
RK3506_CRU_RESET_OFFSET(SRST_P_SPI2, 17, 10),
175
+
RK3506_CRU_RESET_OFFSET(SRST_A_MAC0, 17, 11),
176
+
RK3506_CRU_RESET_OFFSET(SRST_A_MAC1, 17, 12),
177
+
178
+
/* CRU-->SOFTRST_CON18 */
179
+
RK3506_CRU_RESET_OFFSET(SRST_M_SAI2, 18, 2),
180
+
RK3506_CRU_RESET_OFFSET(SRST_H_SAI2, 18, 3),
181
+
RK3506_CRU_RESET_OFFSET(SRST_H_SAI3, 18, 6),
182
+
RK3506_CRU_RESET_OFFSET(SRST_M_SAI3, 18, 7),
183
+
RK3506_CRU_RESET_OFFSET(SRST_H_SAI4, 18, 10),
184
+
RK3506_CRU_RESET_OFFSET(SRST_M_SAI4, 18, 11),
185
+
RK3506_CRU_RESET_OFFSET(SRST_H_DSM, 18, 12),
186
+
RK3506_CRU_RESET_OFFSET(SRST_M_DSM, 18, 13),
187
+
RK3506_CRU_RESET_OFFSET(SRST_P_AUDIO_ADC, 18, 14),
188
+
RK3506_CRU_RESET_OFFSET(SRST_M_AUDIO_ADC, 18, 15),
189
+
190
+
/* CRU-->SOFTRST_CON19 */
191
+
RK3506_CRU_RESET_OFFSET(SRST_P_SARADC, 19, 0),
192
+
RK3506_CRU_RESET_OFFSET(SRST_SARADC, 19, 1),
193
+
RK3506_CRU_RESET_OFFSET(SRST_SARADC_PHY, 19, 2),
194
+
RK3506_CRU_RESET_OFFSET(SRST_P_OTPC_NS, 19, 3),
195
+
RK3506_CRU_RESET_OFFSET(SRST_SBPI_OTPC_NS, 19, 4),
196
+
RK3506_CRU_RESET_OFFSET(SRST_USER_OTPC_NS, 19, 5),
197
+
RK3506_CRU_RESET_OFFSET(SRST_P_UART5, 19, 6),
198
+
RK3506_CRU_RESET_OFFSET(SRST_UART5, 19, 7),
199
+
RK3506_CRU_RESET_OFFSET(SRST_P_GPIO234_IOC, 19, 8),
200
+
201
+
/* CRU-->SOFTRST_CON21 */
202
+
RK3506_CRU_RESET_OFFSET(SRST_A_VIO_BIU, 21, 3),
203
+
RK3506_CRU_RESET_OFFSET(SRST_H_VIO_BIU, 21, 4),
204
+
RK3506_CRU_RESET_OFFSET(SRST_H_RGA, 21, 6),
205
+
RK3506_CRU_RESET_OFFSET(SRST_A_RGA, 21, 7),
206
+
RK3506_CRU_RESET_OFFSET(SRST_CORE_RGA, 21, 8),
207
+
RK3506_CRU_RESET_OFFSET(SRST_A_VOP, 21, 9),
208
+
RK3506_CRU_RESET_OFFSET(SRST_H_VOP, 21, 10),
209
+
RK3506_CRU_RESET_OFFSET(SRST_VOP, 21, 11),
210
+
RK3506_CRU_RESET_OFFSET(SRST_P_DPHY, 21, 12),
211
+
RK3506_CRU_RESET_OFFSET(SRST_P_DSI_HOST, 21, 13),
212
+
RK3506_CRU_RESET_OFFSET(SRST_P_TSADC, 21, 14),
213
+
RK3506_CRU_RESET_OFFSET(SRST_TSADC, 21, 15),
214
+
215
+
/* CRU-->SOFTRST_CON22 */
216
+
RK3506_CRU_RESET_OFFSET(SRST_P_GPIO1_IOC, 22, 1),
217
+
};
218
+
219
+
void rk3506_rst_init(struct device_node *np, void __iomem *reg_base)
220
+
{
221
+
rockchip_register_softrst_lut(np,
222
+
rk3506_register_offset,
223
+
ARRAY_SIZE(rk3506_register_offset),
224
+
reg_base + RK3506_SOFTRST_CON(0),
225
+
ROCKCHIP_SOFTRST_HIWORD_MASK);
226
+
}
+443
drivers/clk/rockchip/rst-rv1126b.c
+443
drivers/clk/rockchip/rst-rv1126b.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-or-later
2
+
/*
3
+
* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
4
+
* Author: Elaine Zhang <zhangqing@rock-chips.com>
5
+
*/
6
+
7
+
#include <linux/module.h>
8
+
#include <linux/of.h>
9
+
#include <dt-bindings/reset/rockchip,rv1126b-cru.h>
10
+
#include "clk.h"
11
+
12
+
/* 0x20000000 + 0x0A00 */
13
+
#define TOPCRU_RESET_OFFSET(id, reg, bit) [id] = (0x0 * 4 + reg * 16 + bit)
14
+
/* 0x20010000 + 0x0A00 */
15
+
#define BUSCRU_RESET_OFFSET(id, reg, bit) [id] = (0x10000 * 4 + reg * 16 + bit)
16
+
/* 0x20020000 + 0x0A00 */
17
+
#define PERICRU_RESET_OFFSET(id, reg, bit) [id] = (0x20000 * 4 + reg * 16 + bit)
18
+
/* 0x20030000 + 0x0A00 */
19
+
#define CORECRU_RESET_OFFSET(id, reg, bit) [id] = (0x30000 * 4 + reg * 16 + bit)
20
+
/* 0x20040000 + 0x0A00 */
21
+
#define PMUCRU_RESET_OFFSET(id, reg, bit) [id] = (0x40000 * 4 + reg * 16 + bit)
22
+
/* 0x20050000 + 0x0A00 */
23
+
#define PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x50000 * 4 + reg * 16 + bit)
24
+
/* 0x20060000 + 0x0A00 */
25
+
#define DDRCRU_RESET_OFFSET(id, reg, bit) [id] = (0x60000 * 4 + reg * 16 + bit)
26
+
/* 0x20068000 + 0x0A00 */
27
+
#define SUBDDRCRU_RESET_OFFSET(id, reg, bit) [id] = (0x68000 * 4 + reg * 16 + bit)
28
+
/* 0x20070000 + 0x0A00 */
29
+
#define VICRU_RESET_OFFSET(id, reg, bit) [id] = (0x70000 * 4 + reg * 16 + bit)
30
+
/* 0x20080000 + 0x0A00 */
31
+
#define VEPUCRU_RESET_OFFSET(id, reg, bit) [id] = (0x80000 * 4 + reg * 16 + bit)
32
+
/* 0x20090000 + 0x0A00 */
33
+
#define NPUCRU_RESET_OFFSET(id, reg, bit) [id] = (0x90000 * 4 + reg * 16 + bit)
34
+
/* 0x200A0000 + 0x0A00 */
35
+
#define VDOCRU_RESET_OFFSET(id, reg, bit) [id] = (0xA0000 * 4 + reg * 16 + bit)
36
+
/* 0x200B0000 + 0x0A00 */
37
+
#define VCPCRU_RESET_OFFSET(id, reg, bit) [id] = (0xB0000 * 4 + reg * 16 + bit)
38
+
39
+
/* =================mapping table for reset ID to register offset================== */
40
+
static const int rv1126b_register_offset[] = {
41
+
/* TOPCRU-->SOFTRST_CON00 */
42
+
43
+
/* TOPCRU-->SOFTRST_CON15 */
44
+
TOPCRU_RESET_OFFSET(SRST_P_CRU, 15, 1),
45
+
TOPCRU_RESET_OFFSET(SRST_P_CRU_BIU, 15, 2),
46
+
47
+
/* BUSCRU-->SOFTRST_CON00 */
48
+
BUSCRU_RESET_OFFSET(SRST_A_TOP_BIU, 0, 0),
49
+
BUSCRU_RESET_OFFSET(SRST_A_RKCE_BIU, 0, 1),
50
+
BUSCRU_RESET_OFFSET(SRST_A_BUS_BIU, 0, 2),
51
+
BUSCRU_RESET_OFFSET(SRST_H_BUS_BIU, 0, 3),
52
+
BUSCRU_RESET_OFFSET(SRST_P_BUS_BIU, 0, 4),
53
+
BUSCRU_RESET_OFFSET(SRST_P_CRU_BUS, 0, 5),
54
+
BUSCRU_RESET_OFFSET(SRST_P_SYS_GRF, 0, 6),
55
+
BUSCRU_RESET_OFFSET(SRST_H_BOOTROM, 0, 7),
56
+
BUSCRU_RESET_OFFSET(SRST_A_GIC400, 0, 8),
57
+
BUSCRU_RESET_OFFSET(SRST_A_SPINLOCK, 0, 9),
58
+
BUSCRU_RESET_OFFSET(SRST_P_WDT_NS, 0, 10),
59
+
BUSCRU_RESET_OFFSET(SRST_T_WDT_NS, 0, 11),
60
+
61
+
/* BUSCRU-->SOFTRST_CON01 */
62
+
BUSCRU_RESET_OFFSET(SRST_P_WDT_HPMCU, 1, 0),
63
+
BUSCRU_RESET_OFFSET(SRST_T_WDT_HPMCU, 1, 1),
64
+
BUSCRU_RESET_OFFSET(SRST_H_CACHE, 1, 2),
65
+
BUSCRU_RESET_OFFSET(SRST_P_HPMCU_MAILBOX, 1, 3),
66
+
BUSCRU_RESET_OFFSET(SRST_P_HPMCU_INTMUX, 1, 4),
67
+
BUSCRU_RESET_OFFSET(SRST_HPMCU_FULL_CLUSTER, 1, 5),
68
+
BUSCRU_RESET_OFFSET(SRST_HPMCU_PWUP, 1, 6),
69
+
BUSCRU_RESET_OFFSET(SRST_HPMCU_ONLY_CORE, 1, 7),
70
+
BUSCRU_RESET_OFFSET(SRST_T_HPMCU_JTAG, 1, 8),
71
+
BUSCRU_RESET_OFFSET(SRST_P_RKDMA, 1, 11),
72
+
BUSCRU_RESET_OFFSET(SRST_A_RKDMA, 1, 12),
73
+
74
+
/* BUSCRU-->SOFTRST_CON02 */
75
+
BUSCRU_RESET_OFFSET(SRST_P_DCF, 2, 0),
76
+
BUSCRU_RESET_OFFSET(SRST_A_DCF, 2, 1),
77
+
BUSCRU_RESET_OFFSET(SRST_H_RGA, 2, 2),
78
+
BUSCRU_RESET_OFFSET(SRST_A_RGA, 2, 3),
79
+
BUSCRU_RESET_OFFSET(SRST_CORE_RGA, 2, 4),
80
+
BUSCRU_RESET_OFFSET(SRST_P_TIMER, 2, 5),
81
+
BUSCRU_RESET_OFFSET(SRST_TIMER0, 2, 6),
82
+
BUSCRU_RESET_OFFSET(SRST_TIMER1, 2, 7),
83
+
BUSCRU_RESET_OFFSET(SRST_TIMER2, 2, 8),
84
+
BUSCRU_RESET_OFFSET(SRST_TIMER3, 2, 9),
85
+
BUSCRU_RESET_OFFSET(SRST_TIMER4, 2, 10),
86
+
BUSCRU_RESET_OFFSET(SRST_TIMER5, 2, 11),
87
+
BUSCRU_RESET_OFFSET(SRST_A_RKCE, 2, 12),
88
+
BUSCRU_RESET_OFFSET(SRST_PKA_RKCE, 2, 13),
89
+
BUSCRU_RESET_OFFSET(SRST_H_RKRNG_S, 2, 14),
90
+
BUSCRU_RESET_OFFSET(SRST_H_RKRNG_NS, 2, 15),
91
+
92
+
/* BUSCRU-->SOFTRST_CON03 */
93
+
BUSCRU_RESET_OFFSET(SRST_P_I2C0, 3, 0),
94
+
BUSCRU_RESET_OFFSET(SRST_I2C0, 3, 1),
95
+
BUSCRU_RESET_OFFSET(SRST_P_I2C1, 3, 2),
96
+
BUSCRU_RESET_OFFSET(SRST_I2C1, 3, 3),
97
+
BUSCRU_RESET_OFFSET(SRST_P_I2C3, 3, 4),
98
+
BUSCRU_RESET_OFFSET(SRST_I2C3, 3, 5),
99
+
BUSCRU_RESET_OFFSET(SRST_P_I2C4, 3, 6),
100
+
BUSCRU_RESET_OFFSET(SRST_I2C4, 3, 7),
101
+
BUSCRU_RESET_OFFSET(SRST_P_I2C5, 3, 8),
102
+
BUSCRU_RESET_OFFSET(SRST_I2C5, 3, 9),
103
+
BUSCRU_RESET_OFFSET(SRST_P_SPI0, 3, 10),
104
+
BUSCRU_RESET_OFFSET(SRST_SPI0, 3, 11),
105
+
BUSCRU_RESET_OFFSET(SRST_P_SPI1, 3, 12),
106
+
BUSCRU_RESET_OFFSET(SRST_SPI1, 3, 13),
107
+
108
+
/* BUSCRU-->SOFTRST_CON04 */
109
+
BUSCRU_RESET_OFFSET(SRST_P_PWM0, 4, 0),
110
+
BUSCRU_RESET_OFFSET(SRST_PWM0, 4, 1),
111
+
BUSCRU_RESET_OFFSET(SRST_P_PWM2, 4, 4),
112
+
BUSCRU_RESET_OFFSET(SRST_PWM2, 4, 5),
113
+
BUSCRU_RESET_OFFSET(SRST_P_PWM3, 4, 8),
114
+
BUSCRU_RESET_OFFSET(SRST_PWM3, 4, 9),
115
+
116
+
/* BUSCRU-->SOFTRST_CON05 */
117
+
BUSCRU_RESET_OFFSET(SRST_P_UART1, 5, 0),
118
+
BUSCRU_RESET_OFFSET(SRST_S_UART1, 5, 1),
119
+
BUSCRU_RESET_OFFSET(SRST_P_UART2, 5, 2),
120
+
BUSCRU_RESET_OFFSET(SRST_S_UART2, 5, 3),
121
+
BUSCRU_RESET_OFFSET(SRST_P_UART3, 5, 4),
122
+
BUSCRU_RESET_OFFSET(SRST_S_UART3, 5, 5),
123
+
BUSCRU_RESET_OFFSET(SRST_P_UART4, 5, 6),
124
+
BUSCRU_RESET_OFFSET(SRST_S_UART4, 5, 7),
125
+
BUSCRU_RESET_OFFSET(SRST_P_UART5, 5, 8),
126
+
BUSCRU_RESET_OFFSET(SRST_S_UART5, 5, 9),
127
+
BUSCRU_RESET_OFFSET(SRST_P_UART6, 5, 10),
128
+
BUSCRU_RESET_OFFSET(SRST_S_UART6, 5, 11),
129
+
BUSCRU_RESET_OFFSET(SRST_P_UART7, 5, 12),
130
+
BUSCRU_RESET_OFFSET(SRST_S_UART7, 5, 13),
131
+
132
+
/* BUSCRU-->SOFTRST_CON06 */
133
+
BUSCRU_RESET_OFFSET(SRST_P_TSADC, 6, 0),
134
+
BUSCRU_RESET_OFFSET(SRST_TSADC, 6, 1),
135
+
BUSCRU_RESET_OFFSET(SRST_H_SAI0, 6, 2),
136
+
BUSCRU_RESET_OFFSET(SRST_M_SAI0, 6, 3),
137
+
BUSCRU_RESET_OFFSET(SRST_H_SAI1, 6, 4),
138
+
BUSCRU_RESET_OFFSET(SRST_M_SAI1, 6, 5),
139
+
BUSCRU_RESET_OFFSET(SRST_H_SAI2, 6, 6),
140
+
BUSCRU_RESET_OFFSET(SRST_M_SAI2, 6, 7),
141
+
BUSCRU_RESET_OFFSET(SRST_H_RKDSM, 6, 8),
142
+
BUSCRU_RESET_OFFSET(SRST_M_RKDSM, 6, 9),
143
+
BUSCRU_RESET_OFFSET(SRST_H_PDM, 6, 10),
144
+
BUSCRU_RESET_OFFSET(SRST_M_PDM, 6, 11),
145
+
BUSCRU_RESET_OFFSET(SRST_PDM, 6, 12),
146
+
147
+
/* BUSCRU-->SOFTRST_CON07 */
148
+
BUSCRU_RESET_OFFSET(SRST_H_ASRC0, 7, 0),
149
+
BUSCRU_RESET_OFFSET(SRST_ASRC0, 7, 1),
150
+
BUSCRU_RESET_OFFSET(SRST_H_ASRC1, 7, 2),
151
+
BUSCRU_RESET_OFFSET(SRST_ASRC1, 7, 3),
152
+
BUSCRU_RESET_OFFSET(SRST_P_AUDIO_ADC_BUS, 7, 4),
153
+
BUSCRU_RESET_OFFSET(SRST_M_AUDIO_ADC_BUS, 7, 5),
154
+
BUSCRU_RESET_OFFSET(SRST_P_RKCE, 7, 6),
155
+
BUSCRU_RESET_OFFSET(SRST_H_NS_RKCE, 7, 7),
156
+
BUSCRU_RESET_OFFSET(SRST_P_OTPC_NS, 7, 8),
157
+
BUSCRU_RESET_OFFSET(SRST_SBPI_OTPC_NS, 7, 9),
158
+
BUSCRU_RESET_OFFSET(SRST_USER_OTPC_NS, 7, 10),
159
+
BUSCRU_RESET_OFFSET(SRST_OTPC_ARB, 7, 11),
160
+
BUSCRU_RESET_OFFSET(SRST_P_OTP_MASK, 7, 12),
161
+
162
+
/* PERICRU-->SOFTRST_CON00 */
163
+
PERICRU_RESET_OFFSET(SRST_A_PERI_BIU, 0, 0),
164
+
PERICRU_RESET_OFFSET(SRST_P_PERI_BIU, 0, 1),
165
+
PERICRU_RESET_OFFSET(SRST_P_RTC_BIU, 0, 2),
166
+
PERICRU_RESET_OFFSET(SRST_P_CRU_PERI, 0, 3),
167
+
PERICRU_RESET_OFFSET(SRST_P_PERI_GRF, 0, 4),
168
+
PERICRU_RESET_OFFSET(SRST_P_GPIO1, 0, 5),
169
+
PERICRU_RESET_OFFSET(SRST_DB_GPIO1, 0, 6),
170
+
PERICRU_RESET_OFFSET(SRST_P_IOC_VCCIO1, 0, 7),
171
+
PERICRU_RESET_OFFSET(SRST_A_USB3OTG, 0, 8),
172
+
PERICRU_RESET_OFFSET(SRST_H_USB2HOST, 0, 11),
173
+
PERICRU_RESET_OFFSET(SRST_H_ARB_USB2HOST, 0, 12),
174
+
PERICRU_RESET_OFFSET(SRST_P_RTC_TEST, 0, 13),
175
+
176
+
/* PERICRU-->SOFTRST_CON01 */
177
+
PERICRU_RESET_OFFSET(SRST_H_EMMC, 1, 0),
178
+
PERICRU_RESET_OFFSET(SRST_H_FSPI0, 1, 1),
179
+
PERICRU_RESET_OFFSET(SRST_H_XIP_FSPI0, 1, 2),
180
+
PERICRU_RESET_OFFSET(SRST_S_2X_FSPI0, 1, 3),
181
+
PERICRU_RESET_OFFSET(SRST_UTMI_USB2HOST, 1, 5),
182
+
PERICRU_RESET_OFFSET(SRST_REF_PIPEPHY, 1, 7),
183
+
PERICRU_RESET_OFFSET(SRST_P_PIPEPHY, 1, 8),
184
+
PERICRU_RESET_OFFSET(SRST_P_PIPEPHY_GRF, 1, 9),
185
+
PERICRU_RESET_OFFSET(SRST_P_USB2PHY, 1, 10),
186
+
PERICRU_RESET_OFFSET(SRST_POR_USB2PHY, 1, 11),
187
+
PERICRU_RESET_OFFSET(SRST_OTG_USB2PHY, 1, 12),
188
+
PERICRU_RESET_OFFSET(SRST_HOST_USB2PHY, 1, 13),
189
+
190
+
/* CORECRU-->SOFTRST_CON00 */
191
+
CORECRU_RESET_OFFSET(SRST_REF_PVTPLL_CORE, 0, 0),
192
+
CORECRU_RESET_OFFSET(SRST_NCOREPORESET0, 0, 1),
193
+
CORECRU_RESET_OFFSET(SRST_NCORESET0, 0, 2),
194
+
CORECRU_RESET_OFFSET(SRST_NCOREPORESET1, 0, 3),
195
+
CORECRU_RESET_OFFSET(SRST_NCORESET1, 0, 4),
196
+
CORECRU_RESET_OFFSET(SRST_NCOREPORESET2, 0, 5),
197
+
CORECRU_RESET_OFFSET(SRST_NCORESET2, 0, 6),
198
+
CORECRU_RESET_OFFSET(SRST_NCOREPORESET3, 0, 7),
199
+
CORECRU_RESET_OFFSET(SRST_NCORESET3, 0, 8),
200
+
CORECRU_RESET_OFFSET(SRST_NDBGRESET, 0, 9),
201
+
CORECRU_RESET_OFFSET(SRST_NL2RESET, 0, 10),
202
+
203
+
/* CORECRU-->SOFTRST_CON01 */
204
+
CORECRU_RESET_OFFSET(SRST_A_CORE_BIU, 1, 0),
205
+
CORECRU_RESET_OFFSET(SRST_P_CORE_BIU, 1, 1),
206
+
CORECRU_RESET_OFFSET(SRST_H_CORE_BIU, 1, 2),
207
+
CORECRU_RESET_OFFSET(SRST_P_DBG, 1, 3),
208
+
CORECRU_RESET_OFFSET(SRST_POT_DBG, 1, 4),
209
+
CORECRU_RESET_OFFSET(SRST_NT_DBG, 1, 5),
210
+
CORECRU_RESET_OFFSET(SRST_P_CORE_PVTPLL, 1, 6),
211
+
CORECRU_RESET_OFFSET(SRST_P_CRU_CORE, 1, 7),
212
+
CORECRU_RESET_OFFSET(SRST_P_CORE_GRF, 1, 8),
213
+
CORECRU_RESET_OFFSET(SRST_P_DFT2APB, 1, 10),
214
+
215
+
/* PMUCRU-->SOFTRST_CON00 */
216
+
PMUCRU_RESET_OFFSET(SRST_H_PMU_BIU, 0, 0),
217
+
PMUCRU_RESET_OFFSET(SRST_P_PMU_GPIO0, 0, 7),
218
+
PMUCRU_RESET_OFFSET(SRST_DB_PMU_GPIO0, 0, 8),
219
+
PMUCRU_RESET_OFFSET(SRST_P_PMU_HP_TIMER, 0, 10),
220
+
PMUCRU_RESET_OFFSET(SRST_PMU_HP_TIMER, 0, 11),
221
+
PMUCRU_RESET_OFFSET(SRST_PMU_32K_HP_TIMER, 0, 12),
222
+
223
+
/* PMUCRU-->SOFTRST_CON01 */
224
+
PMUCRU_RESET_OFFSET(SRST_P_PWM1, 1, 0),
225
+
PMUCRU_RESET_OFFSET(SRST_PWM1, 1, 1),
226
+
PMUCRU_RESET_OFFSET(SRST_P_I2C2, 1, 2),
227
+
PMUCRU_RESET_OFFSET(SRST_I2C2, 1, 3),
228
+
PMUCRU_RESET_OFFSET(SRST_P_UART0, 1, 4),
229
+
PMUCRU_RESET_OFFSET(SRST_S_UART0, 1, 5),
230
+
231
+
/* PMUCRU-->SOFTRST_CON02 */
232
+
PMUCRU_RESET_OFFSET(SRST_P_RCOSC_CTRL, 2, 0),
233
+
PMUCRU_RESET_OFFSET(SRST_REF_RCOSC_CTRL, 2, 2),
234
+
PMUCRU_RESET_OFFSET(SRST_P_IOC_PMUIO0, 2, 3),
235
+
PMUCRU_RESET_OFFSET(SRST_P_CRU_PMU, 2, 4),
236
+
PMUCRU_RESET_OFFSET(SRST_P_PMU_GRF, 2, 5),
237
+
PMUCRU_RESET_OFFSET(SRST_PREROLL, 2, 7),
238
+
PMUCRU_RESET_OFFSET(SRST_PREROLL_32K, 2, 8),
239
+
PMUCRU_RESET_OFFSET(SRST_H_PMU_SRAM, 2, 9),
240
+
241
+
/* PMUCRU-->SOFTRST_CON03 */
242
+
PMUCRU_RESET_OFFSET(SRST_P_WDT_LPMCU, 3, 0),
243
+
PMUCRU_RESET_OFFSET(SRST_T_WDT_LPMCU, 3, 1),
244
+
PMUCRU_RESET_OFFSET(SRST_LPMCU_FULL_CLUSTER, 3, 2),
245
+
PMUCRU_RESET_OFFSET(SRST_LPMCU_PWUP, 3, 3),
246
+
PMUCRU_RESET_OFFSET(SRST_LPMCU_ONLY_CORE, 3, 4),
247
+
PMUCRU_RESET_OFFSET(SRST_T_LPMCU_JTAG, 3, 5),
248
+
PMUCRU_RESET_OFFSET(SRST_P_LPMCU_MAILBOX, 3, 6),
249
+
250
+
/* PMU1CRU-->SOFTRST_CON00 */
251
+
PMU1CRU_RESET_OFFSET(SRST_P_SPI2AHB, 0, 0),
252
+
PMU1CRU_RESET_OFFSET(SRST_H_SPI2AHB, 0, 1),
253
+
PMU1CRU_RESET_OFFSET(SRST_H_FSPI1, 0, 2),
254
+
PMU1CRU_RESET_OFFSET(SRST_H_XIP_FSPI1, 0, 3),
255
+
PMU1CRU_RESET_OFFSET(SRST_S_1X_FSPI1, 0, 4),
256
+
PMU1CRU_RESET_OFFSET(SRST_P_IOC_PMUIO1, 0, 5),
257
+
PMU1CRU_RESET_OFFSET(SRST_P_CRU_PMU1, 0, 6),
258
+
PMU1CRU_RESET_OFFSET(SRST_P_AUDIO_ADC_PMU, 0, 7),
259
+
PMU1CRU_RESET_OFFSET(SRST_M_AUDIO_ADC_PMU, 0, 8),
260
+
PMU1CRU_RESET_OFFSET(SRST_H_PMU1_BIU, 0, 9),
261
+
262
+
/* PMU1CRU-->SOFTRST_CON01 */
263
+
PMU1CRU_RESET_OFFSET(SRST_P_LPDMA, 1, 0),
264
+
PMU1CRU_RESET_OFFSET(SRST_A_LPDMA, 1, 1),
265
+
PMU1CRU_RESET_OFFSET(SRST_H_LPSAI, 1, 2),
266
+
PMU1CRU_RESET_OFFSET(SRST_M_LPSAI, 1, 3),
267
+
PMU1CRU_RESET_OFFSET(SRST_P_AOA_TDD, 1, 4),
268
+
PMU1CRU_RESET_OFFSET(SRST_P_AOA_FE, 1, 5),
269
+
PMU1CRU_RESET_OFFSET(SRST_P_AOA_AAD, 1, 6),
270
+
PMU1CRU_RESET_OFFSET(SRST_P_AOA_APB, 1, 7),
271
+
PMU1CRU_RESET_OFFSET(SRST_P_AOA_SRAM, 1, 8),
272
+
273
+
/* DDRCRU-->SOFTRST_CON00 */
274
+
DDRCRU_RESET_OFFSET(SRST_P_DDR_BIU, 0, 1),
275
+
DDRCRU_RESET_OFFSET(SRST_P_DDRC, 0, 2),
276
+
DDRCRU_RESET_OFFSET(SRST_P_DDRMON, 0, 3),
277
+
DDRCRU_RESET_OFFSET(SRST_TIMER_DDRMON, 0, 4),
278
+
DDRCRU_RESET_OFFSET(SRST_P_DFICTRL, 0, 5),
279
+
DDRCRU_RESET_OFFSET(SRST_P_DDR_GRF, 0, 6),
280
+
DDRCRU_RESET_OFFSET(SRST_P_CRU_DDR, 0, 7),
281
+
DDRCRU_RESET_OFFSET(SRST_P_DDRPHY, 0, 8),
282
+
DDRCRU_RESET_OFFSET(SRST_P_DMA2DDR, 0, 9),
283
+
284
+
/* SUBDDRCRU-->SOFTRST_CON00 */
285
+
SUBDDRCRU_RESET_OFFSET(SRST_A_SYSMEM_BIU, 0, 0),
286
+
SUBDDRCRU_RESET_OFFSET(SRST_A_SYSMEM, 0, 1),
287
+
SUBDDRCRU_RESET_OFFSET(SRST_A_DDR_BIU, 0, 2),
288
+
SUBDDRCRU_RESET_OFFSET(SRST_A_DDRSCH0_CPU, 0, 3),
289
+
SUBDDRCRU_RESET_OFFSET(SRST_A_DDRSCH1_NPU, 0, 4),
290
+
SUBDDRCRU_RESET_OFFSET(SRST_A_DDRSCH2_POE, 0, 5),
291
+
SUBDDRCRU_RESET_OFFSET(SRST_A_DDRSCH3_VI, 0, 6),
292
+
SUBDDRCRU_RESET_OFFSET(SRST_CORE_DDRC, 0, 7),
293
+
SUBDDRCRU_RESET_OFFSET(SRST_DDRMON, 0, 8),
294
+
SUBDDRCRU_RESET_OFFSET(SRST_DFICTRL, 0, 9),
295
+
SUBDDRCRU_RESET_OFFSET(SRST_RS, 0, 11),
296
+
SUBDDRCRU_RESET_OFFSET(SRST_A_DMA2DDR, 0, 12),
297
+
SUBDDRCRU_RESET_OFFSET(SRST_DDRPHY, 0, 13),
298
+
299
+
/* VICRU-->SOFTRST_CON00 */
300
+
VICRU_RESET_OFFSET(SRST_REF_PVTPLL_ISP, 0, 0),
301
+
VICRU_RESET_OFFSET(SRST_A_GMAC_BIU, 0, 1),
302
+
VICRU_RESET_OFFSET(SRST_A_VI_BIU, 0, 2),
303
+
VICRU_RESET_OFFSET(SRST_H_VI_BIU, 0, 3),
304
+
VICRU_RESET_OFFSET(SRST_P_VI_BIU, 0, 4),
305
+
VICRU_RESET_OFFSET(SRST_P_CRU_VI, 0, 5),
306
+
VICRU_RESET_OFFSET(SRST_P_VI_GRF, 0, 6),
307
+
VICRU_RESET_OFFSET(SRST_P_VI_PVTPLL, 0, 7),
308
+
VICRU_RESET_OFFSET(SRST_P_DSMC, 0, 8),
309
+
VICRU_RESET_OFFSET(SRST_A_DSMC, 0, 9),
310
+
VICRU_RESET_OFFSET(SRST_H_CAN0, 0, 10),
311
+
VICRU_RESET_OFFSET(SRST_CAN0, 0, 11),
312
+
VICRU_RESET_OFFSET(SRST_H_CAN1, 0, 12),
313
+
VICRU_RESET_OFFSET(SRST_CAN1, 0, 13),
314
+
315
+
/* VICRU-->SOFTRST_CON01 */
316
+
VICRU_RESET_OFFSET(SRST_P_GPIO2, 1, 0),
317
+
VICRU_RESET_OFFSET(SRST_DB_GPIO2, 1, 1),
318
+
VICRU_RESET_OFFSET(SRST_P_GPIO4, 1, 2),
319
+
VICRU_RESET_OFFSET(SRST_DB_GPIO4, 1, 3),
320
+
VICRU_RESET_OFFSET(SRST_P_GPIO5, 1, 4),
321
+
VICRU_RESET_OFFSET(SRST_DB_GPIO5, 1, 5),
322
+
VICRU_RESET_OFFSET(SRST_P_GPIO6, 1, 6),
323
+
VICRU_RESET_OFFSET(SRST_DB_GPIO6, 1, 7),
324
+
VICRU_RESET_OFFSET(SRST_P_GPIO7, 1, 8),
325
+
VICRU_RESET_OFFSET(SRST_DB_GPIO7, 1, 9),
326
+
VICRU_RESET_OFFSET(SRST_P_IOC_VCCIO2, 1, 10),
327
+
VICRU_RESET_OFFSET(SRST_P_IOC_VCCIO4, 1, 11),
328
+
VICRU_RESET_OFFSET(SRST_P_IOC_VCCIO5, 1, 12),
329
+
VICRU_RESET_OFFSET(SRST_P_IOC_VCCIO6, 1, 13),
330
+
VICRU_RESET_OFFSET(SRST_P_IOC_VCCIO7, 1, 14),
331
+
332
+
/* VICRU-->SOFTRST_CON02 */
333
+
VICRU_RESET_OFFSET(SRST_CORE_ISP, 2, 0),
334
+
VICRU_RESET_OFFSET(SRST_H_VICAP, 2, 1),
335
+
VICRU_RESET_OFFSET(SRST_A_VICAP, 2, 2),
336
+
VICRU_RESET_OFFSET(SRST_D_VICAP, 2, 3),
337
+
VICRU_RESET_OFFSET(SRST_ISP0_VICAP, 2, 4),
338
+
VICRU_RESET_OFFSET(SRST_CORE_VPSS, 2, 5),
339
+
VICRU_RESET_OFFSET(SRST_CORE_VPSL, 2, 6),
340
+
VICRU_RESET_OFFSET(SRST_P_CSI2HOST0, 2, 7),
341
+
VICRU_RESET_OFFSET(SRST_P_CSI2HOST1, 2, 8),
342
+
VICRU_RESET_OFFSET(SRST_P_CSI2HOST2, 2, 9),
343
+
VICRU_RESET_OFFSET(SRST_P_CSI2HOST3, 2, 10),
344
+
VICRU_RESET_OFFSET(SRST_H_SDMMC0, 2, 11),
345
+
VICRU_RESET_OFFSET(SRST_A_GMAC, 2, 12),
346
+
VICRU_RESET_OFFSET(SRST_P_CSIPHY0, 2, 13),
347
+
VICRU_RESET_OFFSET(SRST_P_CSIPHY1, 2, 14),
348
+
349
+
/* VICRU-->SOFTRST_CON03 */
350
+
VICRU_RESET_OFFSET(SRST_P_MACPHY, 3, 0),
351
+
VICRU_RESET_OFFSET(SRST_MACPHY, 3, 1),
352
+
VICRU_RESET_OFFSET(SRST_P_SARADC1, 3, 2),
353
+
VICRU_RESET_OFFSET(SRST_SARADC1, 3, 3),
354
+
VICRU_RESET_OFFSET(SRST_P_SARADC2, 3, 5),
355
+
VICRU_RESET_OFFSET(SRST_SARADC2, 3, 6),
356
+
357
+
/* VEPUCRU-->SOFTRST_CON00 */
358
+
VEPUCRU_RESET_OFFSET(SRST_REF_PVTPLL_VEPU, 0, 0),
359
+
VEPUCRU_RESET_OFFSET(SRST_A_VEPU_BIU, 0, 1),
360
+
VEPUCRU_RESET_OFFSET(SRST_H_VEPU_BIU, 0, 2),
361
+
VEPUCRU_RESET_OFFSET(SRST_P_VEPU_BIU, 0, 3),
362
+
VEPUCRU_RESET_OFFSET(SRST_P_CRU_VEPU, 0, 4),
363
+
VEPUCRU_RESET_OFFSET(SRST_P_VEPU_GRF, 0, 5),
364
+
VEPUCRU_RESET_OFFSET(SRST_P_GPIO3, 0, 7),
365
+
VEPUCRU_RESET_OFFSET(SRST_DB_GPIO3, 0, 8),
366
+
VEPUCRU_RESET_OFFSET(SRST_P_IOC_VCCIO3, 0, 9),
367
+
VEPUCRU_RESET_OFFSET(SRST_P_SARADC0, 0, 10),
368
+
VEPUCRU_RESET_OFFSET(SRST_SARADC0, 0, 11),
369
+
VEPUCRU_RESET_OFFSET(SRST_H_SDMMC1, 0, 13),
370
+
371
+
/* VEPUCRU-->SOFTRST_CON01 */
372
+
VEPUCRU_RESET_OFFSET(SRST_P_VEPU_PVTPLL, 1, 0),
373
+
VEPUCRU_RESET_OFFSET(SRST_H_VEPU, 1, 1),
374
+
VEPUCRU_RESET_OFFSET(SRST_A_VEPU, 1, 2),
375
+
VEPUCRU_RESET_OFFSET(SRST_CORE_VEPU, 1, 3),
376
+
377
+
/* NPUCRU-->SOFTRST_CON00 */
378
+
NPUCRU_RESET_OFFSET(SRST_REF_PVTPLL_NPU, 0, 0),
379
+
NPUCRU_RESET_OFFSET(SRST_A_NPU_BIU, 0, 2),
380
+
NPUCRU_RESET_OFFSET(SRST_H_NPU_BIU, 0, 3),
381
+
NPUCRU_RESET_OFFSET(SRST_P_NPU_BIU, 0, 4),
382
+
NPUCRU_RESET_OFFSET(SRST_P_CRU_NPU, 0, 5),
383
+
NPUCRU_RESET_OFFSET(SRST_P_NPU_GRF, 0, 6),
384
+
NPUCRU_RESET_OFFSET(SRST_P_NPU_PVTPLL, 0, 8),
385
+
NPUCRU_RESET_OFFSET(SRST_H_RKNN, 0, 9),
386
+
NPUCRU_RESET_OFFSET(SRST_A_RKNN, 0, 10),
387
+
388
+
/* VDOCRU-->SOFTRST_CON00 */
389
+
VDOCRU_RESET_OFFSET(SRST_A_RKVDEC_BIU, 0, 0),
390
+
VDOCRU_RESET_OFFSET(SRST_A_VDO_BIU, 0, 1),
391
+
VDOCRU_RESET_OFFSET(SRST_H_VDO_BIU, 0, 3),
392
+
VDOCRU_RESET_OFFSET(SRST_P_VDO_BIU, 0, 4),
393
+
VDOCRU_RESET_OFFSET(SRST_P_CRU_VDO, 0, 5),
394
+
VDOCRU_RESET_OFFSET(SRST_P_VDO_GRF, 0, 6),
395
+
VDOCRU_RESET_OFFSET(SRST_A_RKVDEC, 0, 7),
396
+
VDOCRU_RESET_OFFSET(SRST_H_RKVDEC, 0, 8),
397
+
VDOCRU_RESET_OFFSET(SRST_HEVC_CA_RKVDEC, 0, 9),
398
+
VDOCRU_RESET_OFFSET(SRST_A_VOP, 0, 10),
399
+
VDOCRU_RESET_OFFSET(SRST_H_VOP, 0, 11),
400
+
VDOCRU_RESET_OFFSET(SRST_D_VOP, 0, 12),
401
+
VDOCRU_RESET_OFFSET(SRST_A_OOC, 0, 13),
402
+
VDOCRU_RESET_OFFSET(SRST_H_OOC, 0, 14),
403
+
VDOCRU_RESET_OFFSET(SRST_D_OOC, 0, 15),
404
+
405
+
/* VDOCRU-->SOFTRST_CON01 */
406
+
VDOCRU_RESET_OFFSET(SRST_H_RKJPEG, 1, 3),
407
+
VDOCRU_RESET_OFFSET(SRST_A_RKJPEG, 1, 4),
408
+
VDOCRU_RESET_OFFSET(SRST_A_RKMMU_DECOM, 1, 5),
409
+
VDOCRU_RESET_OFFSET(SRST_H_RKMMU_DECOM, 1, 6),
410
+
VDOCRU_RESET_OFFSET(SRST_D_DECOM, 1, 8),
411
+
VDOCRU_RESET_OFFSET(SRST_A_DECOM, 1, 9),
412
+
VDOCRU_RESET_OFFSET(SRST_P_DECOM, 1, 10),
413
+
VDOCRU_RESET_OFFSET(SRST_P_MIPI_DSI, 1, 12),
414
+
VDOCRU_RESET_OFFSET(SRST_P_DSIPHY, 1, 13),
415
+
416
+
/* VCPCRU-->SOFTRST_CON00 */
417
+
VCPCRU_RESET_OFFSET(SRST_REF_PVTPLL_VCP, 0, 0),
418
+
VCPCRU_RESET_OFFSET(SRST_A_VCP_BIU, 0, 1),
419
+
VCPCRU_RESET_OFFSET(SRST_H_VCP_BIU, 0, 2),
420
+
VCPCRU_RESET_OFFSET(SRST_P_VCP_BIU, 0, 3),
421
+
VCPCRU_RESET_OFFSET(SRST_P_CRU_VCP, 0, 4),
422
+
VCPCRU_RESET_OFFSET(SRST_P_VCP_GRF, 0, 5),
423
+
VCPCRU_RESET_OFFSET(SRST_P_VCP_PVTPLL, 0, 7),
424
+
VCPCRU_RESET_OFFSET(SRST_A_AISP_BIU, 0, 8),
425
+
VCPCRU_RESET_OFFSET(SRST_H_AISP_BIU, 0, 9),
426
+
VCPCRU_RESET_OFFSET(SRST_CORE_AISP, 0, 13),
427
+
428
+
/* VCPCRU-->SOFTRST_CON01 */
429
+
VCPCRU_RESET_OFFSET(SRST_H_FEC, 1, 0),
430
+
VCPCRU_RESET_OFFSET(SRST_A_FEC, 1, 1),
431
+
VCPCRU_RESET_OFFSET(SRST_CORE_FEC, 1, 2),
432
+
VCPCRU_RESET_OFFSET(SRST_H_AVSP, 1, 3),
433
+
VCPCRU_RESET_OFFSET(SRST_A_AVSP, 1, 4),
434
+
};
435
+
436
+
void rv1126b_rst_init(struct device_node *np, void __iomem *reg_base)
437
+
{
438
+
rockchip_register_softrst_lut(np,
439
+
rv1126b_register_offset,
440
+
ARRAY_SIZE(rv1126b_register_offset),
441
+
reg_base + RV1126B_SOFTRST_CON(0),
442
+
ROCKCHIP_SOFTRST_HIWORD_MASK);
443
+
}
+77
-2
drivers/clk/visconti/clkc-tmpv770x.c
+77
-2
drivers/clk/visconti/clkc-tmpv770x.c
···
17
17
#include "clkc.h"
18
18
#include "reset.h"
19
19
20
+
/* Must be equal to the last clock/reset ID increased by one */
21
+
#define CLKS_NR (TMPV770X_CLK_VIIFBS1_PROC + 1)
22
+
#define RESETS_NR (TMPV770X_RESET_VIIFBS1_L1ISP + 1)
23
+
20
24
static DEFINE_SPINLOCK(tmpv770x_clk_lock);
21
25
static DEFINE_SPINLOCK(tmpv770x_rst_lock);
22
26
···
30
26
31
27
static const struct clk_parent_data pietherplls_parent_data[] = {
32
28
{ .fw_name = "pietherpll", .name = "pietherpll", },
29
+
};
30
+
31
+
static const struct clk_parent_data pidnnplls_parent_data[] = {
32
+
{ .fw_name = "pidnnpll", .name = "pidnnpll", },
33
33
};
34
34
35
35
static const struct visconti_fixed_clk fixed_clk_tables[] = {
···
70
62
pietherplls_parent_data, ARRAY_SIZE(pietherplls_parent_data),
71
63
CLK_SET_RATE_PARENT, 0x34, 0x134, 7, 4,
72
64
TMPV770X_RESET_PIETHER_125M, },
65
+
};
66
+
67
+
static const struct visconti_clk_gate_table pidnnpll_clk_gate_tables[] = {
68
+
{ TMPV770X_CLK_VIIFBS0, "viifbs0",
69
+
pidnnplls_parent_data, ARRAY_SIZE(pidnnplls_parent_data),
70
+
0, 0x58, 0x158, 1, 1,
71
+
NO_RESET, },
72
+
{ TMPV770X_CLK_VIIFBS0_PROC, "viifbs0_proc",
73
+
pidnnplls_parent_data, ARRAY_SIZE(pidnnplls_parent_data),
74
+
0, 0x58, 0x158, 18, 1,
75
+
NO_RESET, },
76
+
{ TMPV770X_CLK_VIIFBS0_L1ISP, "viifbs0_l1isp",
77
+
pidnnplls_parent_data, ARRAY_SIZE(pidnnplls_parent_data),
78
+
0, 0x58, 0x158, 17, 1,
79
+
NO_RESET, },
80
+
{ TMPV770X_CLK_VIIFBS0_L2ISP, "viifbs0_l2isp",
81
+
pidnnplls_parent_data, ARRAY_SIZE(pidnnplls_parent_data),
82
+
0, 0x58, 0x158, 16, 1,
83
+
NO_RESET, },
84
+
{ TMPV770X_CLK_VIIFBS1, "viifbs1",
85
+
pidnnplls_parent_data, ARRAY_SIZE(pidnnplls_parent_data),
86
+
0, 0x58, 0x158, 5, 1,
87
+
NO_RESET, },
88
+
{ TMPV770X_CLK_VIIFBS1_PROC, "viifbs1_proc",
89
+
pidnnplls_parent_data, ARRAY_SIZE(pidnnplls_parent_data),
90
+
0, 0x58, 0x158, 22, 1,
91
+
NO_RESET, },
92
+
{ TMPV770X_CLK_VIIFBS1_L1ISP, "viifbs1_l1isp",
93
+
pidnnplls_parent_data, ARRAY_SIZE(pidnnplls_parent_data),
94
+
0, 0x58, 0x158, 21, 1,
95
+
NO_RESET, },
96
+
{ TMPV770X_CLK_VIIFBS1_L2ISP, "viifbs1_l2isp",
97
+
pidnnplls_parent_data, ARRAY_SIZE(pidnnplls_parent_data),
98
+
0, 0x58, 0x158, 20, 1,
99
+
NO_RESET, },
73
100
};
74
101
75
102
static const struct visconti_clk_gate_table clk_gate_tables[] = {
···
228
185
clks_parent_data, ARRAY_SIZE(clks_parent_data),
229
186
0, 0x14, 0x114, 0, 4,
230
187
TMPV770X_RESET_SBUSCLK, },
188
+
{ TMPV770X_CLK_VIIF0_CFGCLK, "csi2rx0cfg",
189
+
clks_parent_data, ARRAY_SIZE(clks_parent_data),
190
+
0, 0x58, 0x158, 0, 24,
191
+
NO_RESET, },
192
+
{ TMPV770X_CLK_VIIF0_APBCLK, "csi2rx0apb",
193
+
clks_parent_data, ARRAY_SIZE(clks_parent_data),
194
+
0, 0x58, 0x158, 2, 4,
195
+
NO_RESET, },
196
+
{ TMPV770X_CLK_VIIF1_CFGCLK, "csi2rx1cfg",
197
+
clks_parent_data, ARRAY_SIZE(clks_parent_data),
198
+
0, 0x58, 0x158, 4, 24,
199
+
NO_RESET, },
200
+
{ TMPV770X_CLK_VIIF1_APBCLK, "csi2rx1apb",
201
+
clks_parent_data, ARRAY_SIZE(clks_parent_data),
202
+
0, 0x58, 0x158, 6, 4,
203
+
NO_RESET, },
231
204
};
232
205
233
206
static const struct visconti_reset_data clk_reset_data[] = {
···
279
220
[TMPV770X_RESET_PIPCMIF] = { 0x464, 0x564, 0, },
280
221
[TMPV770X_RESET_PICKMON] = { 0x410, 0x510, 8, },
281
222
[TMPV770X_RESET_SBUSCLK] = { 0x414, 0x514, 0, },
223
+
[TMPV770X_RESET_VIIFBS0] = { 0x458, 0x558, 0, },
224
+
[TMPV770X_RESET_VIIFBS0_APB] = { 0x458, 0x558, 1, },
225
+
[TMPV770X_RESET_VIIFBS0_L2ISP] = { 0x458, 0x558, 16, },
226
+
[TMPV770X_RESET_VIIFBS0_L1ISP] = { 0x458, 0x558, 17, },
227
+
[TMPV770X_RESET_VIIFBS1] = { 0x458, 0x558, 4, },
228
+
[TMPV770X_RESET_VIIFBS1_APB] = { 0x458, 0x558, 5, },
229
+
[TMPV770X_RESET_VIIFBS1_L2ISP] = { 0x458, 0x558, 20, },
230
+
[TMPV770X_RESET_VIIFBS1_L1ISP] = { 0x458, 0x558, 21, },
282
231
};
283
232
284
233
static int visconti_clk_probe(struct platform_device *pdev)
···
301
234
if (IS_ERR(regmap))
302
235
return PTR_ERR(regmap);
303
236
304
-
ctx = visconti_init_clk(dev, regmap, TMPV770X_NR_CLK);
237
+
ctx = visconti_init_clk(dev, regmap, CLKS_NR);
305
238
if (IS_ERR(ctx))
306
239
return PTR_ERR(ctx);
307
240
308
241
ret = visconti_register_reset_controller(dev, regmap, clk_reset_data,
309
-
TMPV770X_NR_RESET,
242
+
RESETS_NR,
310
243
&visconti_reset_ops,
311
244
&tmpv770x_rst_lock);
312
245
if (ret) {
···
336
269
clk_reset_data, &tmpv770x_clk_lock);
337
270
if (ret) {
338
271
dev_err(dev, "Failed to register pietherpll clock gate: %d\n", ret);
272
+
return ret;
273
+
}
274
+
275
+
ret = visconti_clk_register_gates(ctx, pidnnpll_clk_gate_tables,
276
+
ARRAY_SIZE(pidnnpll_clk_gate_tables),
277
+
clk_reset_data, &tmpv770x_clk_lock);
278
+
if (ret) {
279
+
dev_err(dev, "Failed to register pidnnpll clock gate: %d\n", ret);
339
280
return ret;
340
281
}
341
282
+4
-1
drivers/clk/visconti/pll-tmpv770x.c
+4
-1
drivers/clk/visconti/pll-tmpv770x.c
···
16
16
17
17
#include "pll.h"
18
18
19
+
/* Must be equal to the last pll ID increased by one */
20
+
#define PLLS_NR (TMPV770X_PLL_PIIMGERPLL + 1)
21
+
19
22
static DEFINE_SPINLOCK(tmpv770x_pll_lock);
20
23
21
24
static const struct visconti_pll_rate_table pipll0_rates[] __initconst = {
···
69
66
if (!reg_base)
70
67
return;
71
68
72
-
ctx = visconti_init_pll(np, reg_base, TMPV770X_NR_PLL);
69
+
ctx = visconti_init_pll(np, reg_base, PLLS_NR);
73
70
if (IS_ERR(ctx)) {
74
71
iounmap(reg_base);
75
72
return;
+1
drivers/reset/Kconfig
+1
drivers/reset/Kconfig
+55
-36
drivers/reset/reset-mpfs.c
+55
-36
drivers/reset/reset-mpfs.c
···
9
9
#include <linux/auxiliary_bus.h>
10
10
#include <linux/delay.h>
11
11
#include <linux/io.h>
12
+
#include <linux/mfd/syscon.h>
12
13
#include <linux/module.h>
13
14
#include <linux/of.h>
14
15
#include <linux/platform_device.h>
15
-
#include <linux/slab.h>
16
+
#include <linux/regmap.h>
16
17
#include <linux/reset-controller.h>
18
+
#include <linux/slab.h>
17
19
#include <dt-bindings/clock/microchip,mpfs-clock.h>
18
20
#include <soc/microchip/mpfs.h>
19
21
···
29
27
#define MPFS_SLEEP_MIN_US 100
30
28
#define MPFS_SLEEP_MAX_US 200
31
29
32
-
/* block concurrent access to the soft reset register */
33
-
static DEFINE_SPINLOCK(mpfs_reset_lock);
30
+
#define REG_SUBBLK_RESET_CR 0x88u
34
31
35
32
struct mpfs_reset {
36
-
void __iomem *base;
33
+
struct regmap *regmap;
37
34
struct reset_controller_dev rcdev;
38
35
};
39
36
···
47
46
static int mpfs_assert(struct reset_controller_dev *rcdev, unsigned long id)
48
47
{
49
48
struct mpfs_reset *rst = to_mpfs_reset(rcdev);
50
-
unsigned long flags;
51
-
u32 reg;
52
49
53
-
spin_lock_irqsave(&mpfs_reset_lock, flags);
50
+
return regmap_set_bits(rst->regmap, REG_SUBBLK_RESET_CR, BIT(id));
54
51
55
-
reg = readl(rst->base);
56
-
reg |= BIT(id);
57
-
writel(reg, rst->base);
58
-
59
-
spin_unlock_irqrestore(&mpfs_reset_lock, flags);
60
-
61
-
return 0;
62
52
}
63
53
64
54
static int mpfs_deassert(struct reset_controller_dev *rcdev, unsigned long id)
65
55
{
66
56
struct mpfs_reset *rst = to_mpfs_reset(rcdev);
67
-
unsigned long flags;
68
-
u32 reg;
69
57
70
-
spin_lock_irqsave(&mpfs_reset_lock, flags);
58
+
return regmap_clear_bits(rst->regmap, REG_SUBBLK_RESET_CR, BIT(id));
71
59
72
-
reg = readl(rst->base);
73
-
reg &= ~BIT(id);
74
-
writel(reg, rst->base);
75
-
76
-
spin_unlock_irqrestore(&mpfs_reset_lock, flags);
77
-
78
-
return 0;
79
60
}
80
61
81
62
static int mpfs_status(struct reset_controller_dev *rcdev, unsigned long id)
82
63
{
83
64
struct mpfs_reset *rst = to_mpfs_reset(rcdev);
84
-
u32 reg = readl(rst->base);
65
+
u32 reg;
66
+
67
+
regmap_read(rst->regmap, REG_SUBBLK_RESET_CR, ®);
85
68
86
69
/*
87
70
* It is safe to return here as MPFS_NUM_RESETS makes sure the sign bit
···
115
130
return index - MPFS_PERIPH_OFFSET;
116
131
}
117
132
118
-
static int mpfs_reset_probe(struct auxiliary_device *adev,
119
-
const struct auxiliary_device_id *id)
133
+
static int mpfs_reset_mfd_probe(struct platform_device *pdev)
120
134
{
121
-
struct device *dev = &adev->dev;
122
135
struct reset_controller_dev *rcdev;
136
+
struct device *dev = &pdev->dev;
123
137
struct mpfs_reset *rst;
124
138
125
139
rst = devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL);
126
140
if (!rst)
127
141
return -ENOMEM;
128
142
129
-
rst->base = (void __iomem *)adev->dev.platform_data;
143
+
rcdev = &rst->rcdev;
144
+
rcdev->dev = dev;
145
+
rcdev->ops = &mpfs_reset_ops;
146
+
147
+
rcdev->of_node = pdev->dev.parent->of_node;
148
+
rcdev->of_reset_n_cells = 1;
149
+
rcdev->of_xlate = mpfs_reset_xlate;
150
+
rcdev->nr_resets = MPFS_NUM_RESETS;
151
+
152
+
rst->regmap = device_node_to_regmap(pdev->dev.parent->of_node);
153
+
if (IS_ERR(rst->regmap))
154
+
return dev_err_probe(dev, PTR_ERR(rst->regmap),
155
+
"Failed to find syscon regmap\n");
156
+
157
+
return devm_reset_controller_register(dev, rcdev);
158
+
}
159
+
160
+
static struct platform_driver mpfs_reset_mfd_driver = {
161
+
.probe = mpfs_reset_mfd_probe,
162
+
.driver = {
163
+
.name = "mpfs-reset",
164
+
},
165
+
};
166
+
module_platform_driver(mpfs_reset_mfd_driver);
167
+
168
+
static int mpfs_reset_adev_probe(struct auxiliary_device *adev,
169
+
const struct auxiliary_device_id *id)
170
+
{
171
+
struct reset_controller_dev *rcdev;
172
+
struct device *dev = &adev->dev;
173
+
struct mpfs_reset *rst;
174
+
175
+
rst = devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL);
176
+
if (!rst)
177
+
return -ENOMEM;
178
+
179
+
rst->regmap = (struct regmap *)adev->dev.platform_data;
130
180
131
181
rcdev = &rst->rcdev;
132
182
rcdev->dev = dev;
133
-
rcdev->dev->parent = dev->parent;
134
183
rcdev->ops = &mpfs_reset_ops;
184
+
135
185
rcdev->of_node = dev->parent->of_node;
136
186
rcdev->of_reset_n_cells = 1;
137
187
rcdev->of_xlate = mpfs_reset_xlate;
···
175
155
return devm_reset_controller_register(dev, rcdev);
176
156
}
177
157
178
-
int mpfs_reset_controller_register(struct device *clk_dev, void __iomem *base)
158
+
int mpfs_reset_controller_register(struct device *clk_dev, struct regmap *map)
179
159
{
180
160
struct auxiliary_device *adev;
181
161
182
-
adev = devm_auxiliary_device_create(clk_dev, "reset-mpfs",
183
-
(__force void *)base);
162
+
adev = devm_auxiliary_device_create(clk_dev, "reset-mpfs", (void *)map);
184
163
if (!adev)
185
164
return -ENODEV;
186
165
···
195
176
};
196
177
MODULE_DEVICE_TABLE(auxiliary, mpfs_reset_ids);
197
178
198
-
static struct auxiliary_driver mpfs_reset_driver = {
199
-
.probe = mpfs_reset_probe,
179
+
static struct auxiliary_driver mpfs_reset_aux_driver = {
180
+
.probe = mpfs_reset_adev_probe,
200
181
.id_table = mpfs_reset_ids,
201
182
};
202
183
203
-
module_auxiliary_driver(mpfs_reset_driver);
184
+
module_auxiliary_driver(mpfs_reset_aux_driver);
204
185
205
186
MODULE_DESCRIPTION("Microchip PolarFire SoC Reset Driver");
206
187
MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
+5
include/dt-bindings/clock/imx8ulp-clock.h
+5
include/dt-bindings/clock/imx8ulp-clock.h
+4
include/dt-bindings/clock/qcom,dispcc-sm6350.h
+4
include/dt-bindings/clock/qcom,dispcc-sm6350.h
+2
-1
include/dt-bindings/clock/qcom,ipq5424-gcc.h
+2
-1
include/dt-bindings/clock/qcom,ipq5424-gcc.h
···
1
1
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
2
/*
3
3
* Copyright (c) 2018,2020 The Linux Foundation. All rights reserved.
4
-
* Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
4
+
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
5
5
*/
6
6
7
7
#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_IPQ5424_H
···
152
152
#define GCC_PCIE3_RCHNG_CLK 143
153
153
#define GCC_IM_SLEEP_CLK 144
154
154
#define GCC_XO_CLK 145
155
+
#define GPLL0_OUT_AUX 146
155
156
156
157
#endif
+65
include/dt-bindings/clock/qcom,ipq5424-nsscc.h
+65
include/dt-bindings/clock/qcom,ipq5424-nsscc.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
4
+
*/
5
+
6
+
#ifndef _DT_BINDINGS_CLOCK_QCOM_IPQ5424_NSSCC_H
7
+
#define _DT_BINDINGS_CLOCK_QCOM_IPQ5424_NSSCC_H
8
+
9
+
/* NSS_CC clocks */
10
+
#define NSS_CC_CE_APB_CLK 0
11
+
#define NSS_CC_CE_AXI_CLK 1
12
+
#define NSS_CC_CE_CLK_SRC 2
13
+
#define NSS_CC_CFG_CLK_SRC 3
14
+
#define NSS_CC_DEBUG_CLK 4
15
+
#define NSS_CC_EIP_BFDCD_CLK_SRC 5
16
+
#define NSS_CC_EIP_CLK 6
17
+
#define NSS_CC_NSS_CSR_CLK 7
18
+
#define NSS_CC_NSSNOC_CE_APB_CLK 8
19
+
#define NSS_CC_NSSNOC_CE_AXI_CLK 9
20
+
#define NSS_CC_NSSNOC_EIP_CLK 10
21
+
#define NSS_CC_NSSNOC_NSS_CSR_CLK 11
22
+
#define NSS_CC_NSSNOC_PPE_CFG_CLK 12
23
+
#define NSS_CC_NSSNOC_PPE_CLK 13
24
+
#define NSS_CC_PORT1_MAC_CLK 14
25
+
#define NSS_CC_PORT1_RX_CLK 15
26
+
#define NSS_CC_PORT1_RX_CLK_SRC 16
27
+
#define NSS_CC_PORT1_RX_DIV_CLK_SRC 17
28
+
#define NSS_CC_PORT1_TX_CLK 18
29
+
#define NSS_CC_PORT1_TX_CLK_SRC 19
30
+
#define NSS_CC_PORT1_TX_DIV_CLK_SRC 20
31
+
#define NSS_CC_PORT2_MAC_CLK 21
32
+
#define NSS_CC_PORT2_RX_CLK 22
33
+
#define NSS_CC_PORT2_RX_CLK_SRC 23
34
+
#define NSS_CC_PORT2_RX_DIV_CLK_SRC 24
35
+
#define NSS_CC_PORT2_TX_CLK 25
36
+
#define NSS_CC_PORT2_TX_CLK_SRC 26
37
+
#define NSS_CC_PORT2_TX_DIV_CLK_SRC 27
38
+
#define NSS_CC_PORT3_MAC_CLK 28
39
+
#define NSS_CC_PORT3_RX_CLK 29
40
+
#define NSS_CC_PORT3_RX_CLK_SRC 30
41
+
#define NSS_CC_PORT3_RX_DIV_CLK_SRC 31
42
+
#define NSS_CC_PORT3_TX_CLK 32
43
+
#define NSS_CC_PORT3_TX_CLK_SRC 33
44
+
#define NSS_CC_PORT3_TX_DIV_CLK_SRC 34
45
+
#define NSS_CC_PPE_CLK_SRC 35
46
+
#define NSS_CC_PPE_EDMA_CFG_CLK 36
47
+
#define NSS_CC_PPE_EDMA_CLK 37
48
+
#define NSS_CC_PPE_SWITCH_BTQ_CLK 38
49
+
#define NSS_CC_PPE_SWITCH_CFG_CLK 39
50
+
#define NSS_CC_PPE_SWITCH_CLK 40
51
+
#define NSS_CC_PPE_SWITCH_IPE_CLK 41
52
+
#define NSS_CC_UNIPHY_PORT1_RX_CLK 42
53
+
#define NSS_CC_UNIPHY_PORT1_TX_CLK 43
54
+
#define NSS_CC_UNIPHY_PORT2_RX_CLK 44
55
+
#define NSS_CC_UNIPHY_PORT2_TX_CLK 45
56
+
#define NSS_CC_UNIPHY_PORT3_RX_CLK 46
57
+
#define NSS_CC_UNIPHY_PORT3_TX_CLK 47
58
+
#define NSS_CC_XGMAC0_PTP_REF_CLK 48
59
+
#define NSS_CC_XGMAC0_PTP_REF_DIV_CLK_SRC 49
60
+
#define NSS_CC_XGMAC1_PTP_REF_CLK 50
61
+
#define NSS_CC_XGMAC1_PTP_REF_DIV_CLK_SRC 51
62
+
#define NSS_CC_XGMAC2_PTP_REF_CLK 52
63
+
#define NSS_CC_XGMAC2_PTP_REF_DIV_CLK_SRC 53
64
+
65
+
#endif
+241
include/dt-bindings/clock/qcom,kaanapali-gcc.h
+241
include/dt-bindings/clock/qcom,kaanapali-gcc.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
4
+
*/
5
+
6
+
#ifndef _DT_BINDINGS_CLK_QCOM_GCC_KAANAPALI_H
7
+
#define _DT_BINDINGS_CLK_QCOM_GCC_KAANAPALI_H
8
+
9
+
/* GCC clocks */
10
+
#define GCC_AGGRE_NOC_PCIE_AXI_CLK 0
11
+
#define GCC_AGGRE_UFS_PHY_AXI_CLK 1
12
+
#define GCC_AGGRE_USB3_PRIM_AXI_CLK 2
13
+
#define GCC_BOOT_ROM_AHB_CLK 3
14
+
#define GCC_CAM_BIST_MCLK_AHB_CLK 4
15
+
#define GCC_CAMERA_AHB_CLK 5
16
+
#define GCC_CAMERA_HF_AXI_CLK 6
17
+
#define GCC_CAMERA_SF_AXI_CLK 7
18
+
#define GCC_CAMERA_XO_CLK 8
19
+
#define GCC_CFG_NOC_PCIE_ANOC_AHB_CLK 9
20
+
#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 10
21
+
#define GCC_CNOC_PCIE_SF_AXI_CLK 11
22
+
#define GCC_DDRSS_PCIE_SF_QTB_CLK 12
23
+
#define GCC_QMIP_CAMERA_CMD_AHB_CLK 13
24
+
#define GCC_DISP_HF_AXI_CLK 14
25
+
#define GCC_DISP_SF_AXI_CLK 15
26
+
#define GCC_EVA_AHB_CLK 16
27
+
#define GCC_EVA_AXI0_CLK 17
28
+
#define GCC_EVA_AXI0C_CLK 18
29
+
#define GCC_EVA_XO_CLK 19
30
+
#define GCC_GP1_CLK 20
31
+
#define GCC_GP1_CLK_SRC 21
32
+
#define GCC_GP2_CLK 22
33
+
#define GCC_GP2_CLK_SRC 23
34
+
#define GCC_GP3_CLK 24
35
+
#define GCC_GP3_CLK_SRC 25
36
+
#define GCC_GPLL0 26
37
+
#define GCC_GPLL0_OUT_EVEN 27
38
+
#define GCC_GPLL1 28
39
+
#define GCC_GPLL4 29
40
+
#define GCC_GPLL7 30
41
+
#define GCC_GPLL9 31
42
+
#define GCC_GPU_CFG_AHB_CLK 32
43
+
#define GCC_GPU_GEMNOC_GFX_CLK 33
44
+
#define GCC_GPU_GPLL0_CLK_SRC 34
45
+
#define GCC_GPU_GPLL0_DIV_CLK_SRC 35
46
+
#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 36
47
+
#define GCC_QMIP_GPU_AHB_CLK 37
48
+
#define GCC_PCIE_0_AUX_CLK 38
49
+
#define GCC_PCIE_0_AUX_CLK_SRC 39
50
+
#define GCC_PCIE_0_CFG_AHB_CLK 40
51
+
#define GCC_PCIE_0_MSTR_AXI_CLK 41
52
+
#define GCC_PCIE_0_PHY_AUX_CLK 42
53
+
#define GCC_PCIE_0_PHY_AUX_CLK_SRC 43
54
+
#define GCC_PCIE_0_PHY_RCHNG_CLK 44
55
+
#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 45
56
+
#define GCC_PCIE_0_PIPE_CLK 46
57
+
#define GCC_PCIE_0_PIPE_CLK_SRC 47
58
+
#define GCC_PCIE_0_SLV_AXI_CLK 48
59
+
#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 49
60
+
#define GCC_PCIE_RSCC_CFG_AHB_CLK 50
61
+
#define GCC_PCIE_RSCC_XO_CLK 51
62
+
#define GCC_PDM2_CLK 52
63
+
#define GCC_PDM2_CLK_SRC 53
64
+
#define GCC_PDM_AHB_CLK 54
65
+
#define GCC_PDM_XO4_CLK 55
66
+
#define GCC_QUPV3_I2C_CORE_CLK 56
67
+
#define GCC_QUPV3_I2C_S0_CLK 57
68
+
#define GCC_QUPV3_I2C_S0_CLK_SRC 58
69
+
#define GCC_QUPV3_I2C_S1_CLK 59
70
+
#define GCC_QUPV3_I2C_S1_CLK_SRC 60
71
+
#define GCC_QUPV3_I2C_S2_CLK 61
72
+
#define GCC_QUPV3_I2C_S2_CLK_SRC 62
73
+
#define GCC_QUPV3_I2C_S3_CLK 63
74
+
#define GCC_QUPV3_I2C_S3_CLK_SRC 64
75
+
#define GCC_QUPV3_I2C_S4_CLK 65
76
+
#define GCC_QUPV3_I2C_S4_CLK_SRC 66
77
+
#define GCC_QUPV3_I2C_S_AHB_CLK 67
78
+
#define GCC_QUPV3_WRAP1_CORE_2X_CLK 68
79
+
#define GCC_QUPV3_WRAP1_CORE_CLK 69
80
+
#define GCC_QUPV3_WRAP1_QSPI_REF_CLK 70
81
+
#define GCC_QUPV3_WRAP1_QSPI_REF_CLK_SRC 71
82
+
#define GCC_QUPV3_WRAP1_S0_CLK 72
83
+
#define GCC_QUPV3_WRAP1_S0_CLK_SRC 73
84
+
#define GCC_QUPV3_WRAP1_S1_CLK 74
85
+
#define GCC_QUPV3_WRAP1_S1_CLK_SRC 75
86
+
#define GCC_QUPV3_WRAP1_S2_CLK 76
87
+
#define GCC_QUPV3_WRAP1_S2_CLK_SRC 77
88
+
#define GCC_QUPV3_WRAP1_S3_CLK 78
89
+
#define GCC_QUPV3_WRAP1_S3_CLK_SRC 79
90
+
#define GCC_QUPV3_WRAP1_S4_CLK 80
91
+
#define GCC_QUPV3_WRAP1_S4_CLK_SRC 81
92
+
#define GCC_QUPV3_WRAP1_S5_CLK 82
93
+
#define GCC_QUPV3_WRAP1_S5_CLK_SRC 83
94
+
#define GCC_QUPV3_WRAP1_S6_CLK 84
95
+
#define GCC_QUPV3_WRAP1_S6_CLK_SRC 85
96
+
#define GCC_QUPV3_WRAP1_S7_CLK 86
97
+
#define GCC_QUPV3_WRAP1_S7_CLK_SRC 87
98
+
#define GCC_QUPV3_WRAP2_CORE_2X_CLK 88
99
+
#define GCC_QUPV3_WRAP2_CORE_CLK 89
100
+
#define GCC_QUPV3_WRAP2_S0_CLK 90
101
+
#define GCC_QUPV3_WRAP2_S0_CLK_SRC 91
102
+
#define GCC_QUPV3_WRAP2_S1_CLK 92
103
+
#define GCC_QUPV3_WRAP2_S1_CLK_SRC 93
104
+
#define GCC_QUPV3_WRAP2_S2_CLK 94
105
+
#define GCC_QUPV3_WRAP2_S2_CLK_SRC 95
106
+
#define GCC_QUPV3_WRAP2_S3_CLK 96
107
+
#define GCC_QUPV3_WRAP2_S3_CLK_SRC 97
108
+
#define GCC_QUPV3_WRAP2_S4_CLK 98
109
+
#define GCC_QUPV3_WRAP2_S4_CLK_SRC 99
110
+
#define GCC_QUPV3_WRAP3_CORE_2X_CLK 100
111
+
#define GCC_QUPV3_WRAP3_CORE_CLK 101
112
+
#define GCC_QUPV3_WRAP3_IBI_CTRL_0_CLK_SRC 102
113
+
#define GCC_QUPV3_WRAP3_IBI_CTRL_1_CLK 103
114
+
#define GCC_QUPV3_WRAP3_IBI_CTRL_2_CLK 104
115
+
#define GCC_QUPV3_WRAP3_S0_CLK 105
116
+
#define GCC_QUPV3_WRAP3_S0_CLK_SRC 106
117
+
#define GCC_QUPV3_WRAP3_S1_CLK 107
118
+
#define GCC_QUPV3_WRAP3_S1_CLK_SRC 108
119
+
#define GCC_QUPV3_WRAP3_S2_CLK 109
120
+
#define GCC_QUPV3_WRAP3_S2_CLK_SRC 110
121
+
#define GCC_QUPV3_WRAP3_S3_CLK 111
122
+
#define GCC_QUPV3_WRAP3_S3_CLK_SRC 112
123
+
#define GCC_QUPV3_WRAP3_S4_CLK 113
124
+
#define GCC_QUPV3_WRAP3_S4_CLK_SRC 114
125
+
#define GCC_QUPV3_WRAP3_S5_CLK 115
126
+
#define GCC_QUPV3_WRAP3_S5_CLK_SRC 116
127
+
#define GCC_QUPV3_WRAP4_CORE_2X_CLK 117
128
+
#define GCC_QUPV3_WRAP4_CORE_CLK 118
129
+
#define GCC_QUPV3_WRAP4_S0_CLK 119
130
+
#define GCC_QUPV3_WRAP4_S0_CLK_SRC 120
131
+
#define GCC_QUPV3_WRAP4_S1_CLK 121
132
+
#define GCC_QUPV3_WRAP4_S1_CLK_SRC 122
133
+
#define GCC_QUPV3_WRAP4_S2_CLK 123
134
+
#define GCC_QUPV3_WRAP4_S2_CLK_SRC 124
135
+
#define GCC_QUPV3_WRAP4_S3_CLK 125
136
+
#define GCC_QUPV3_WRAP4_S3_CLK_SRC 126
137
+
#define GCC_QUPV3_WRAP4_S4_CLK 127
138
+
#define GCC_QUPV3_WRAP4_S4_CLK_SRC 128
139
+
#define GCC_QUPV3_WRAP_1_M_AXI_CLK 129
140
+
#define GCC_QUPV3_WRAP_1_S_AHB_CLK 130
141
+
#define GCC_QUPV3_WRAP_2_M_AHB_CLK 131
142
+
#define GCC_QUPV3_WRAP_2_S_AHB_CLK 132
143
+
#define GCC_QUPV3_WRAP_3_IBI_1_AHB_CLK 133
144
+
#define GCC_QUPV3_WRAP_3_IBI_2_AHB_CLK 134
145
+
#define GCC_QUPV3_WRAP_3_M_AHB_CLK 135
146
+
#define GCC_QUPV3_WRAP_3_S_AHB_CLK 136
147
+
#define GCC_QUPV3_WRAP_4_M_AHB_CLK 137
148
+
#define GCC_QUPV3_WRAP_4_S_AHB_CLK 138
149
+
#define GCC_SDCC2_AHB_CLK 139
150
+
#define GCC_SDCC2_APPS_CLK 140
151
+
#define GCC_SDCC2_APPS_CLK_SRC 141
152
+
#define GCC_SDCC4_AHB_CLK 142
153
+
#define GCC_SDCC4_APPS_CLK 143
154
+
#define GCC_SDCC4_APPS_CLK_SRC 144
155
+
#define GCC_UFS_PHY_AHB_CLK 145
156
+
#define GCC_UFS_PHY_AXI_CLK 146
157
+
#define GCC_UFS_PHY_AXI_CLK_SRC 147
158
+
#define GCC_UFS_PHY_ICE_CORE_CLK 148
159
+
#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 149
160
+
#define GCC_UFS_PHY_PHY_AUX_CLK 150
161
+
#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 151
162
+
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 152
163
+
#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 153
164
+
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 154
165
+
#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 155
166
+
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 156
167
+
#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 157
168
+
#define GCC_UFS_PHY_UNIPRO_CORE_CLK 158
169
+
#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 159
170
+
#define GCC_USB30_PRIM_MASTER_CLK 160
171
+
#define GCC_USB30_PRIM_MASTER_CLK_SRC 161
172
+
#define GCC_USB30_PRIM_MOCK_UTMI_CLK 162
173
+
#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 163
174
+
#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 164
175
+
#define GCC_USB30_PRIM_SLEEP_CLK 165
176
+
#define GCC_USB3_PRIM_PHY_AUX_CLK 166
177
+
#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 167
178
+
#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 168
179
+
#define GCC_USB3_PRIM_PHY_PIPE_CLK 169
180
+
#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 170
181
+
#define GCC_VIDEO_AHB_CLK 171
182
+
#define GCC_VIDEO_AXI0_CLK 172
183
+
#define GCC_VIDEO_AXI1_CLK 173
184
+
#define GCC_VIDEO_XO_CLK 174
185
+
#define GCC_QMIP_CAMERA_NRT_AHB_CLK 175
186
+
#define GCC_QMIP_CAMERA_RT_AHB_CLK 176
187
+
#define GCC_QMIP_DISP_DCP_SF_AHB_CLK 177
188
+
#define GCC_QMIP_PCIE_AHB_CLK 178
189
+
#define GCC_QMIP_VIDEO_CV_CPU_AHB_CLK 179
190
+
#define GCC_QMIP_VIDEO_CVP_AHB_CLK 180
191
+
#define GCC_QMIP_VIDEO_V_CPU_AHB_CLK 181
192
+
#define GCC_DISP_AHB_CLK 182
193
+
194
+
/* GCC power domains */
195
+
#define GCC_PCIE_0_GDSC 0
196
+
#define GCC_PCIE_0_PHY_GDSC 1
197
+
#define GCC_UFS_MEM_PHY_GDSC 2
198
+
#define GCC_UFS_PHY_GDSC 3
199
+
#define GCC_USB30_PRIM_GDSC 4
200
+
#define GCC_USB3_PHY_GDSC 5
201
+
202
+
/* GCC resets */
203
+
#define GCC_CAMERA_BCR 0
204
+
#define GCC_DISPLAY_BCR 1
205
+
#define GCC_EVA_AXI0_CLK_ARES 2
206
+
#define GCC_EVA_AXI0C_CLK_ARES 3
207
+
#define GCC_EVA_BCR 4
208
+
#define GCC_GPU_BCR 5
209
+
#define GCC_PCIE_0_BCR 6
210
+
#define GCC_PCIE_0_LINK_DOWN_BCR 7
211
+
#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 8
212
+
#define GCC_PCIE_0_PHY_BCR 9
213
+
#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 10
214
+
#define GCC_PCIE_PHY_BCR 11
215
+
#define GCC_PCIE_PHY_CFG_AHB_BCR 12
216
+
#define GCC_PCIE_PHY_COM_BCR 13
217
+
#define GCC_PCIE_RSCC_BCR 14
218
+
#define GCC_PDM_BCR 15
219
+
#define GCC_QUPV3_WRAPPER_1_BCR 16
220
+
#define GCC_QUPV3_WRAPPER_2_BCR 17
221
+
#define GCC_QUPV3_WRAPPER_3_BCR 18
222
+
#define GCC_QUPV3_WRAPPER_4_BCR 19
223
+
#define GCC_QUPV3_WRAPPER_I2C_BCR 20
224
+
#define GCC_QUSB2PHY_PRIM_BCR 21
225
+
#define GCC_QUSB2PHY_SEC_BCR 22
226
+
#define GCC_SDCC2_BCR 23
227
+
#define GCC_SDCC4_BCR 24
228
+
#define GCC_UFS_PHY_BCR 25
229
+
#define GCC_USB30_PRIM_BCR 26
230
+
#define GCC_USB3_DP_PHY_PRIM_BCR 27
231
+
#define GCC_USB3_DP_PHY_SEC_BCR 28
232
+
#define GCC_USB3_PHY_PRIM_BCR 29
233
+
#define GCC_USB3_PHY_SEC_BCR 30
234
+
#define GCC_USB3PHY_PHY_PRIM_BCR 31
235
+
#define GCC_USB3PHY_PHY_SEC_BCR 32
236
+
#define GCC_VIDEO_AXI0_CLK_ARES 33
237
+
#define GCC_VIDEO_AXI1_CLK_ARES 34
238
+
#define GCC_VIDEO_BCR 35
239
+
#define GCC_VIDEO_XO_CLK_ARES 36
240
+
241
+
#endif
+1
include/dt-bindings/clock/qcom,mmcc-sdm660.h
+1
include/dt-bindings/clock/qcom,mmcc-sdm660.h
+3
include/dt-bindings/clock/qcom,sm7150-dispcc.h
+3
include/dt-bindings/clock/qcom,sm7150-dispcc.h
+40
include/dt-bindings/clock/qcom,sm8750-videocc.h
+40
include/dt-bindings/clock/qcom,sm8750-videocc.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
4
+
*/
5
+
6
+
#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8750_H
7
+
#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8750_H
8
+
9
+
/* VIDEO_CC clocks */
10
+
#define VIDEO_CC_AHB_CLK 0
11
+
#define VIDEO_CC_AHB_CLK_SRC 1
12
+
#define VIDEO_CC_MVS0_CLK 2
13
+
#define VIDEO_CC_MVS0_CLK_SRC 3
14
+
#define VIDEO_CC_MVS0_DIV_CLK_SRC 4
15
+
#define VIDEO_CC_MVS0_FREERUN_CLK 5
16
+
#define VIDEO_CC_MVS0_SHIFT_CLK 6
17
+
#define VIDEO_CC_MVS0C_CLK 7
18
+
#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 8
19
+
#define VIDEO_CC_MVS0C_FREERUN_CLK 9
20
+
#define VIDEO_CC_MVS0C_SHIFT_CLK 10
21
+
#define VIDEO_CC_PLL0 11
22
+
#define VIDEO_CC_SLEEP_CLK 12
23
+
#define VIDEO_CC_SLEEP_CLK_SRC 13
24
+
#define VIDEO_CC_XO_CLK 14
25
+
#define VIDEO_CC_XO_CLK_SRC 15
26
+
27
+
/* VIDEO_CC power domains */
28
+
#define VIDEO_CC_MVS0_GDSC 0
29
+
#define VIDEO_CC_MVS0C_GDSC 1
30
+
31
+
/* VIDEO_CC resets */
32
+
#define VIDEO_CC_INTERFACE_BCR 0
33
+
#define VIDEO_CC_MVS0_BCR 1
34
+
#define VIDEO_CC_MVS0C_CLK_ARES 2
35
+
#define VIDEO_CC_MVS0C_BCR 3
36
+
#define VIDEO_CC_MVS0_FREERUN_CLK_ARES 4
37
+
#define VIDEO_CC_MVS0C_FREERUN_CLK_ARES 5
38
+
#define VIDEO_CC_XO_CLK_ARES 6
39
+
40
+
#endif
+3
include/dt-bindings/clock/qcom,x1e80100-dispcc.h
+3
include/dt-bindings/clock/qcom,x1e80100-dispcc.h
···
90
90
#define DISP_CC_MDSS_CORE_BCR 0
91
91
#define DISP_CC_MDSS_CORE_INT2_BCR 1
92
92
#define DISP_CC_MDSS_RSCC_BCR 2
93
+
#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK_ARES 3
94
+
#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK_ARES 4
95
+
#define DISP_CC_MDSS_DPTX2_USB_ROUTER_LINK_INTF_CLK_ARES 5
93
96
94
97
/* DISP_CC GDSCR */
95
98
#define MDSS_GDSC 0
+61
include/dt-bindings/clock/qcom,x1e80100-gcc.h
+61
include/dt-bindings/clock/qcom,x1e80100-gcc.h
···
363
363
#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 353
364
364
#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 354
365
365
#define GCC_USB3_TERT_PHY_PIPE_CLK_SRC 355
366
+
#define GCC_USB34_PRIM_PHY_PIPE_CLK_SRC 356
367
+
#define GCC_USB34_SEC_PHY_PIPE_CLK_SRC 357
368
+
#define GCC_USB34_TERT_PHY_PIPE_CLK_SRC 358
369
+
#define GCC_USB4_0_PHY_DP0_CLK_SRC 359
370
+
#define GCC_USB4_0_PHY_DP1_CLK_SRC 360
371
+
#define GCC_USB4_0_PHY_P2RR2P_PIPE_CLK_SRC 361
372
+
#define GCC_USB4_0_PHY_PCIE_PIPE_MUX_CLK_SRC 362
373
+
#define GCC_USB4_0_PHY_RX0_CLK_SRC 363
374
+
#define GCC_USB4_0_PHY_RX1_CLK_SRC 364
375
+
#define GCC_USB4_0_PHY_SYS_CLK_SRC 365
376
+
#define GCC_USB4_1_PHY_DP0_CLK_SRC 366
377
+
#define GCC_USB4_1_PHY_DP1_CLK_SRC 367
378
+
#define GCC_USB4_1_PHY_P2RR2P_PIPE_CLK_SRC 368
379
+
#define GCC_USB4_1_PHY_PCIE_PIPE_MUX_CLK_SRC 369
380
+
#define GCC_USB4_1_PHY_RX0_CLK_SRC 370
381
+
#define GCC_USB4_1_PHY_RX1_CLK_SRC 371
382
+
#define GCC_USB4_1_PHY_SYS_CLK_SRC 372
383
+
#define GCC_USB4_2_PHY_DP0_CLK_SRC 373
384
+
#define GCC_USB4_2_PHY_DP1_CLK_SRC 374
385
+
#define GCC_USB4_2_PHY_P2RR2P_PIPE_CLK_SRC 375
386
+
#define GCC_USB4_2_PHY_PCIE_PIPE_MUX_CLK_SRC 376
387
+
#define GCC_USB4_2_PHY_RX0_CLK_SRC 377
388
+
#define GCC_USB4_2_PHY_RX1_CLK_SRC 378
389
+
#define GCC_USB4_2_PHY_SYS_CLK_SRC 379
366
390
367
391
/* GCC power domains */
368
392
#define GCC_PCIE_0_TUNNEL_GDSC 0
···
508
484
#define GCC_VIDEO_BCR 87
509
485
#define GCC_VIDEO_AXI0_CLK_ARES 88
510
486
#define GCC_VIDEO_AXI1_CLK_ARES 89
487
+
#define GCC_USB4_0_MISC_USB4_SYS_BCR 90
488
+
#define GCC_USB4_0_MISC_RX_CLK_0_BCR 91
489
+
#define GCC_USB4_0_MISC_RX_CLK_1_BCR 92
490
+
#define GCC_USB4_0_MISC_USB_PIPE_BCR 93
491
+
#define GCC_USB4_0_MISC_PCIE_PIPE_BCR 94
492
+
#define GCC_USB4_0_MISC_TMU_BCR 95
493
+
#define GCC_USB4_0_MISC_SB_IF_BCR 96
494
+
#define GCC_USB4_0_MISC_HIA_MSTR_BCR 97
495
+
#define GCC_USB4_0_MISC_AHB_BCR 98
496
+
#define GCC_USB4_0_MISC_DP0_MAX_PCLK_BCR 99
497
+
#define GCC_USB4_0_MISC_DP1_MAX_PCLK_BCR 100
498
+
#define GCC_USB4_1_MISC_USB4_SYS_BCR 101
499
+
#define GCC_USB4_1_MISC_RX_CLK_0_BCR 102
500
+
#define GCC_USB4_1_MISC_RX_CLK_1_BCR 103
501
+
#define GCC_USB4_1_MISC_USB_PIPE_BCR 104
502
+
#define GCC_USB4_1_MISC_PCIE_PIPE_BCR 105
503
+
#define GCC_USB4_1_MISC_TMU_BCR 106
504
+
#define GCC_USB4_1_MISC_SB_IF_BCR 107
505
+
#define GCC_USB4_1_MISC_HIA_MSTR_BCR 108
506
+
#define GCC_USB4_1_MISC_AHB_BCR 109
507
+
#define GCC_USB4_1_MISC_DP0_MAX_PCLK_BCR 110
508
+
#define GCC_USB4_1_MISC_DP1_MAX_PCLK_BCR 111
509
+
#define GCC_USB4_2_MISC_USB4_SYS_BCR 112
510
+
#define GCC_USB4_2_MISC_RX_CLK_0_BCR 113
511
+
#define GCC_USB4_2_MISC_RX_CLK_1_BCR 114
512
+
#define GCC_USB4_2_MISC_USB_PIPE_BCR 115
513
+
#define GCC_USB4_2_MISC_PCIE_PIPE_BCR 116
514
+
#define GCC_USB4_2_MISC_TMU_BCR 117
515
+
#define GCC_USB4_2_MISC_SB_IF_BCR 118
516
+
#define GCC_USB4_2_MISC_HIA_MSTR_BCR 119
517
+
#define GCC_USB4_2_MISC_AHB_BCR 120
518
+
#define GCC_USB4_2_MISC_DP0_MAX_PCLK_BCR 121
519
+
#define GCC_USB4_2_MISC_DP1_MAX_PCLK_BCR 122
520
+
#define GCC_USB4PHY_PHY_PRIM_BCR 123
521
+
#define GCC_USB4PHY_PHY_SEC_BCR 124
522
+
#define GCC_USB4PHY_PHY_TERT_BCR 125
523
+
511
524
#endif
+5
-1
include/dt-bindings/clock/rk3568-cru.h
+5
-1
include/dt-bindings/clock/rk3568-cru.h
···
483
483
484
484
#define PCLK_CORE_PVTM 450
485
485
486
-
#define CLK_NR_CLKS (PCLK_CORE_PVTM + 1)
486
+
/* scmi-clocks indices */
487
+
488
+
#define SCMI_CLK_CPU 0
489
+
#define SCMI_CLK_GPU 1
490
+
#define SCMI_CLK_NPU 2
487
491
488
492
/* pmu soft-reset indices */
489
493
/* pmucru_softrst_con0 */
+285
include/dt-bindings/clock/rockchip,rk3506-cru.h
+285
include/dt-bindings/clock/rockchip,rk3506-cru.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) 2023-2025 Rockchip Electronics Co., Ltd.
4
+
* Author: Finley Xiao <finley.xiao@rock-chips.com>
5
+
*/
6
+
7
+
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3506_H
8
+
#define _DT_BINDINGS_CLK_ROCKCHIP_RK3506_H
9
+
10
+
/* cru plls */
11
+
#define PLL_GPLL 0
12
+
#define PLL_V0PLL 1
13
+
#define PLL_V1PLL 2
14
+
15
+
/* cru-clocks indices */
16
+
#define ARMCLK 3
17
+
#define CLK_DDR 4
18
+
#define XIN24M_GATE 5
19
+
#define CLK_GPLL_GATE 6
20
+
#define CLK_V0PLL_GATE 7
21
+
#define CLK_V1PLL_GATE 8
22
+
#define CLK_GPLL_DIV 9
23
+
#define CLK_GPLL_DIV_100M 10
24
+
#define CLK_V0PLL_DIV 11
25
+
#define CLK_V1PLL_DIV 12
26
+
#define CLK_INT_VOICE_MATRIX0 13
27
+
#define CLK_INT_VOICE_MATRIX1 14
28
+
#define CLK_INT_VOICE_MATRIX2 15
29
+
#define CLK_FRAC_UART_MATRIX0_MUX 16
30
+
#define CLK_FRAC_UART_MATRIX1_MUX 17
31
+
#define CLK_FRAC_VOICE_MATRIX0_MUX 18
32
+
#define CLK_FRAC_VOICE_MATRIX1_MUX 19
33
+
#define CLK_FRAC_COMMON_MATRIX0_MUX 20
34
+
#define CLK_FRAC_COMMON_MATRIX1_MUX 21
35
+
#define CLK_FRAC_COMMON_MATRIX2_MUX 22
36
+
#define CLK_FRAC_UART_MATRIX0 23
37
+
#define CLK_FRAC_UART_MATRIX1 24
38
+
#define CLK_FRAC_VOICE_MATRIX0 25
39
+
#define CLK_FRAC_VOICE_MATRIX1 26
40
+
#define CLK_FRAC_COMMON_MATRIX0 27
41
+
#define CLK_FRAC_COMMON_MATRIX1 28
42
+
#define CLK_FRAC_COMMON_MATRIX2 29
43
+
#define CLK_REF_USBPHY_TOP 30
44
+
#define CLK_REF_DPHY_TOP 31
45
+
#define ACLK_CORE_ROOT 32
46
+
#define PCLK_CORE_ROOT 33
47
+
#define PCLK_DBG 34
48
+
#define PCLK_CORE_GRF 35
49
+
#define PCLK_CORE_CRU 36
50
+
#define CLK_CORE_EMA_DETECT 37
51
+
#define CLK_REF_PVTPLL_CORE 38
52
+
#define PCLK_GPIO1 39
53
+
#define DBCLK_GPIO1 40
54
+
#define ACLK_CORE_PERI_ROOT 41
55
+
#define HCLK_CORE_PERI_ROOT 42
56
+
#define PCLK_CORE_PERI_ROOT 43
57
+
#define CLK_DSMC 44
58
+
#define ACLK_DSMC 45
59
+
#define PCLK_DSMC 46
60
+
#define CLK_FLEXBUS_TX 47
61
+
#define CLK_FLEXBUS_RX 48
62
+
#define ACLK_FLEXBUS 49
63
+
#define HCLK_FLEXBUS 50
64
+
#define ACLK_DSMC_SLV 51
65
+
#define HCLK_DSMC_SLV 52
66
+
#define ACLK_BUS_ROOT 53
67
+
#define HCLK_BUS_ROOT 54
68
+
#define PCLK_BUS_ROOT 55
69
+
#define ACLK_SYSRAM 56
70
+
#define HCLK_SYSRAM 57
71
+
#define ACLK_DMAC0 58
72
+
#define ACLK_DMAC1 59
73
+
#define HCLK_M0 60
74
+
#define PCLK_BUS_GRF 61
75
+
#define PCLK_TIMER 62
76
+
#define CLK_TIMER0_CH0 63
77
+
#define CLK_TIMER0_CH1 64
78
+
#define CLK_TIMER0_CH2 65
79
+
#define CLK_TIMER0_CH3 66
80
+
#define CLK_TIMER0_CH4 67
81
+
#define CLK_TIMER0_CH5 68
82
+
#define PCLK_WDT0 69
83
+
#define TCLK_WDT0 70
84
+
#define PCLK_WDT1 71
85
+
#define TCLK_WDT1 72
86
+
#define PCLK_MAILBOX 73
87
+
#define PCLK_INTMUX 74
88
+
#define PCLK_SPINLOCK 75
89
+
#define PCLK_DDRC 76
90
+
#define HCLK_DDRPHY 77
91
+
#define PCLK_DDRMON 78
92
+
#define CLK_DDRMON_OSC 79
93
+
#define PCLK_STDBY 80
94
+
#define HCLK_USBOTG0 81
95
+
#define HCLK_USBOTG0_PMU 82
96
+
#define CLK_USBOTG0_ADP 83
97
+
#define HCLK_USBOTG1 84
98
+
#define HCLK_USBOTG1_PMU 85
99
+
#define CLK_USBOTG1_ADP 86
100
+
#define PCLK_USBPHY 87
101
+
#define ACLK_DMA2DDR 88
102
+
#define PCLK_DMA2DDR 89
103
+
#define STCLK_M0 90
104
+
#define CLK_DDRPHY 91
105
+
#define CLK_DDRC_SRC 92
106
+
#define ACLK_DDRC_0 93
107
+
#define ACLK_DDRC_1 94
108
+
#define CLK_DDRC 95
109
+
#define CLK_DDRMON 96
110
+
#define HCLK_LSPERI_ROOT 97
111
+
#define PCLK_LSPERI_ROOT 98
112
+
#define PCLK_UART0 99
113
+
#define PCLK_UART1 100
114
+
#define PCLK_UART2 101
115
+
#define PCLK_UART3 102
116
+
#define PCLK_UART4 103
117
+
#define SCLK_UART0 104
118
+
#define SCLK_UART1 105
119
+
#define SCLK_UART2 106
120
+
#define SCLK_UART3 107
121
+
#define SCLK_UART4 108
122
+
#define PCLK_I2C0 109
123
+
#define CLK_I2C0 110
124
+
#define PCLK_I2C1 111
125
+
#define CLK_I2C1 112
126
+
#define PCLK_I2C2 113
127
+
#define CLK_I2C2 114
128
+
#define PCLK_PWM1 115
129
+
#define CLK_PWM1 116
130
+
#define CLK_OSC_PWM1 117
131
+
#define CLK_RC_PWM1 118
132
+
#define CLK_FREQ_PWM1 119
133
+
#define CLK_COUNTER_PWM1 120
134
+
#define PCLK_SPI0 121
135
+
#define CLK_SPI0 122
136
+
#define PCLK_SPI1 123
137
+
#define CLK_SPI1 124
138
+
#define PCLK_GPIO2 125
139
+
#define DBCLK_GPIO2 126
140
+
#define PCLK_GPIO3 127
141
+
#define DBCLK_GPIO3 128
142
+
#define PCLK_GPIO4 129
143
+
#define DBCLK_GPIO4 130
144
+
#define HCLK_CAN0 131
145
+
#define CLK_CAN0 132
146
+
#define HCLK_CAN1 133
147
+
#define CLK_CAN1 134
148
+
#define HCLK_PDM 135
149
+
#define MCLK_PDM 136
150
+
#define CLKOUT_PDM 137
151
+
#define MCLK_SPDIFTX 138
152
+
#define HCLK_SPDIFTX 139
153
+
#define HCLK_SPDIFRX 140
154
+
#define MCLK_SPDIFRX 141
155
+
#define MCLK_SAI0 142
156
+
#define HCLK_SAI0 143
157
+
#define MCLK_OUT_SAI0 144
158
+
#define MCLK_SAI1 145
159
+
#define HCLK_SAI1 146
160
+
#define MCLK_OUT_SAI1 147
161
+
#define HCLK_ASRC0 148
162
+
#define CLK_ASRC0 149
163
+
#define HCLK_ASRC1 150
164
+
#define CLK_ASRC1 151
165
+
#define PCLK_CRU 152
166
+
#define PCLK_PMU_ROOT 153
167
+
#define MCLK_ASRC0 154
168
+
#define MCLK_ASRC1 155
169
+
#define MCLK_ASRC2 156
170
+
#define MCLK_ASRC3 157
171
+
#define LRCK_ASRC0_SRC 158
172
+
#define LRCK_ASRC0_DST 159
173
+
#define LRCK_ASRC1_SRC 160
174
+
#define LRCK_ASRC1_DST 161
175
+
#define ACLK_HSPERI_ROOT 162
176
+
#define HCLK_HSPERI_ROOT 163
177
+
#define PCLK_HSPERI_ROOT 164
178
+
#define CCLK_SRC_SDMMC 165
179
+
#define HCLK_SDMMC 166
180
+
#define HCLK_FSPI 167
181
+
#define SCLK_FSPI 168
182
+
#define PCLK_SPI2 169
183
+
#define ACLK_MAC0 170
184
+
#define ACLK_MAC1 171
185
+
#define PCLK_MAC0 172
186
+
#define PCLK_MAC1 173
187
+
#define CLK_MAC_ROOT 174
188
+
#define CLK_MAC0 175
189
+
#define CLK_MAC1 176
190
+
#define MCLK_SAI2 177
191
+
#define HCLK_SAI2 178
192
+
#define MCLK_OUT_SAI2 179
193
+
#define MCLK_SAI3_SRC 180
194
+
#define HCLK_SAI3 181
195
+
#define MCLK_SAI3 182
196
+
#define MCLK_OUT_SAI3 183
197
+
#define MCLK_SAI4_SRC 184
198
+
#define HCLK_SAI4 185
199
+
#define MCLK_SAI4 186
200
+
#define HCLK_DSM 187
201
+
#define MCLK_DSM 188
202
+
#define PCLK_AUDIO_ADC 189
203
+
#define MCLK_AUDIO_ADC 190
204
+
#define MCLK_AUDIO_ADC_DIV4 191
205
+
#define PCLK_SARADC 192
206
+
#define CLK_SARADC 193
207
+
#define PCLK_OTPC_NS 194
208
+
#define CLK_SBPI_OTPC_NS 195
209
+
#define CLK_USER_OTPC_NS 196
210
+
#define PCLK_UART5 197
211
+
#define SCLK_UART5 198
212
+
#define PCLK_GPIO234_IOC 199
213
+
#define CLK_MAC_PTP_ROOT 200
214
+
#define CLK_MAC0_PTP 201
215
+
#define CLK_MAC1_PTP 202
216
+
#define CLK_SPI2 203
217
+
#define ACLK_VIO_ROOT 204
218
+
#define HCLK_VIO_ROOT 205
219
+
#define PCLK_VIO_ROOT 206
220
+
#define HCLK_RGA 207
221
+
#define ACLK_RGA 208
222
+
#define CLK_CORE_RGA 209
223
+
#define ACLK_VOP 210
224
+
#define HCLK_VOP 211
225
+
#define DCLK_VOP 212
226
+
#define PCLK_DPHY 213
227
+
#define PCLK_DSI_HOST 214
228
+
#define PCLK_TSADC 215
229
+
#define CLK_TSADC 216
230
+
#define CLK_TSADC_TSEN 217
231
+
#define PCLK_GPIO1_IOC 218
232
+
#define PCLK_OTPC_S 219
233
+
#define CLK_SBPI_OTPC_S 220
234
+
#define CLK_USER_OTPC_S 221
235
+
#define PCLK_OTP_MASK 222
236
+
#define PCLK_KEYREADER 223
237
+
#define HCLK_BOOTROM 224
238
+
#define PCLK_DDR_SERVICE 225
239
+
#define HCLK_CRYPTO_S 226
240
+
#define HCLK_KEYLAD 227
241
+
#define CLK_CORE_CRYPTO 228
242
+
#define CLK_PKA_CRYPTO 229
243
+
#define CLK_CORE_CRYPTO_S 230
244
+
#define CLK_PKA_CRYPTO_S 231
245
+
#define ACLK_CRYPTO_S 232
246
+
#define HCLK_RNG_S 233
247
+
#define CLK_CORE_CRYPTO_NS 234
248
+
#define CLK_PKA_CRYPTO_NS 235
249
+
#define ACLK_CRYPTO_NS 236
250
+
#define HCLK_CRYPTO_NS 237
251
+
#define HCLK_RNG 238
252
+
#define CLK_PMU 239
253
+
#define PCLK_PMU 240
254
+
#define CLK_PMU_32K 241
255
+
#define PCLK_PMU_CRU 242
256
+
#define PCLK_PMU_GRF 243
257
+
#define PCLK_GPIO0_IOC 244
258
+
#define PCLK_GPIO0 245
259
+
#define DBCLK_GPIO0 246
260
+
#define PCLK_GPIO1_SHADOW 247
261
+
#define DBCLK_GPIO1_SHADOW 248
262
+
#define PCLK_PMU_HP_TIMER 249
263
+
#define CLK_PMU_HP_TIMER 250
264
+
#define CLK_PMU_HP_TIMER_32K 251
265
+
#define PCLK_PWM0 252
266
+
#define CLK_PWM0 253
267
+
#define CLK_OSC_PWM0 254
268
+
#define CLK_RC_PWM0 255
269
+
#define CLK_MAC_OUT 256
270
+
#define CLK_REF_OUT0 257
271
+
#define CLK_REF_OUT1 258
272
+
#define CLK_32K_FRAC 259
273
+
#define CLK_32K_RC 260
274
+
#define CLK_32K 261
275
+
#define CLK_32K_PMU 262
276
+
#define PCLK_TOUCH_KEY 263
277
+
#define CLK_TOUCH_KEY 264
278
+
#define CLK_REF_PHY_PLL 265
279
+
#define CLK_REF_PHY_PMU_MUX 266
280
+
#define CLK_WIFI_OUT 267
281
+
#define CLK_V0PLL_REF 268
282
+
#define CLK_V1PLL_REF 269
283
+
#define CLK_32K_FRAC_MUX 270
284
+
285
+
#endif
+392
include/dt-bindings/clock/rockchip,rv1126b-cru.h
+392
include/dt-bindings/clock/rockchip,rv1126b-cru.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
2
+
/*
3
+
* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
4
+
* Author: Elaine Zhang <zhangqing@rock-chips.com>
5
+
*/
6
+
7
+
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1126B_H
8
+
#define _DT_BINDINGS_CLK_ROCKCHIP_RV1126B_H
9
+
10
+
/* pll clocks */
11
+
#define PLL_GPLL 0
12
+
#define PLL_CPLL 1
13
+
#define PLL_AUPLL 2
14
+
#define ARMCLK 3
15
+
#define SCLK_DDR 4
16
+
17
+
/* clk (clocks) */
18
+
#define CLK_CPLL_DIV20 5
19
+
#define CLK_CPLL_DIV10 6
20
+
#define CLK_CPLL_DIV8 7
21
+
#define CLK_GPLL_DIV8 8
22
+
#define CLK_GPLL_DIV6 9
23
+
#define CLK_GPLL_DIV4 10
24
+
#define CLK_CPLL_DIV3 11
25
+
#define CLK_GPLL_DIV3 12
26
+
#define CLK_CPLL_DIV2 13
27
+
#define CLK_GPLL_DIV2 14
28
+
#define CLK_CM_FRAC0 15
29
+
#define CLK_CM_FRAC1 16
30
+
#define CLK_CM_FRAC2 17
31
+
#define CLK_UART_FRAC0 18
32
+
#define CLK_UART_FRAC1 19
33
+
#define CLK_AUDIO_FRAC0 20
34
+
#define CLK_AUDIO_FRAC1 21
35
+
#define CLK_AUDIO_INT0 22
36
+
#define CLK_AUDIO_INT1 23
37
+
#define SCLK_UART0_SRC 24
38
+
#define SCLK_UART1 25
39
+
#define SCLK_UART2 26
40
+
#define SCLK_UART3 27
41
+
#define SCLK_UART4 28
42
+
#define SCLK_UART5 29
43
+
#define SCLK_UART6 30
44
+
#define SCLK_UART7 31
45
+
#define MCLK_SAI0 32
46
+
#define MCLK_SAI1 33
47
+
#define MCLK_SAI2 34
48
+
#define MCLK_PDM 35
49
+
#define CLKOUT_PDM 36
50
+
#define MCLK_ASRC0 37
51
+
#define MCLK_ASRC1 38
52
+
#define MCLK_ASRC2 39
53
+
#define MCLK_ASRC3 40
54
+
#define CLK_ASRC0 41
55
+
#define CLK_ASRC1 42
56
+
#define CLK_CORE_PLL 43
57
+
#define CLK_NPU_PLL 44
58
+
#define CLK_VEPU_PLL 45
59
+
#define CLK_ISP_PLL 46
60
+
#define CLK_AISP_PLL 47
61
+
#define CLK_SARADC0_SRC 48
62
+
#define CLK_SARADC1_SRC 49
63
+
#define CLK_SARADC2_SRC 50
64
+
#define HCLK_NPU_ROOT 51
65
+
#define PCLK_NPU_ROOT 52
66
+
#define ACLK_VEPU_ROOT 53
67
+
#define HCLK_VEPU_ROOT 54
68
+
#define PCLK_VEPU_ROOT 55
69
+
#define CLK_CORE_RGA_SRC 56
70
+
#define ACLK_GMAC_ROOT 57
71
+
#define ACLK_VI_ROOT 58
72
+
#define HCLK_VI_ROOT 59
73
+
#define PCLK_VI_ROOT 60
74
+
#define DCLK_VICAP_ROOT 61
75
+
#define CLK_SYS_DSMC_ROOT 62
76
+
#define ACLK_VDO_ROOT 63
77
+
#define ACLK_RKVDEC_ROOT 64
78
+
#define HCLK_VDO_ROOT 65
79
+
#define PCLK_VDO_ROOT 66
80
+
#define DCLK_OOC_SRC 67
81
+
#define DCLK_VOP 68
82
+
#define DCLK_DECOM_SRC 69
83
+
#define PCLK_DDR_ROOT 70
84
+
#define ACLK_SYSMEM_SRC 71
85
+
#define ACLK_TOP_ROOT 72
86
+
#define ACLK_BUS_ROOT 73
87
+
#define HCLK_BUS_ROOT 74
88
+
#define PCLK_BUS_ROOT 75
89
+
#define CCLK_SDMMC0 76
90
+
#define CCLK_SDMMC1 77
91
+
#define CCLK_EMMC 78
92
+
#define SCLK_2X_FSPI0 79
93
+
#define CLK_GMAC_PTP_REF_SRC 80
94
+
#define CLK_GMAC_125M 81
95
+
#define CLK_TIMER_ROOT 82
96
+
#define TCLK_WDT_NS_SRC 83
97
+
#define TCLK_WDT_S_SRC 84
98
+
#define TCLK_WDT_HPMCU 85
99
+
#define CLK_CAN0 86
100
+
#define CLK_CAN1 87
101
+
#define PCLK_PERI_ROOT 88
102
+
#define ACLK_PERI_ROOT 89
103
+
#define CLK_I2C_BUS_SRC 90
104
+
#define CLK_SPI0 91
105
+
#define CLK_SPI1 92
106
+
#define BUSCLK_PMU_SRC 93
107
+
#define CLK_PWM0 94
108
+
#define CLK_PWM2 95
109
+
#define CLK_PWM3 96
110
+
#define CLK_PKA_RKCE_SRC 97
111
+
#define ACLK_RKCE_SRC 98
112
+
#define ACLK_VCP_ROOT 99
113
+
#define HCLK_VCP_ROOT 100
114
+
#define PCLK_VCP_ROOT 101
115
+
#define CLK_CORE_FEC_SRC 102
116
+
#define CLK_CORE_AVSP_SRC 103
117
+
#define CLK_50M_GMAC_IOBUF_VI 104
118
+
#define PCLK_TOP_ROOT 105
119
+
#define CLK_MIPI0_OUT2IO 106
120
+
#define CLK_MIPI1_OUT2IO 107
121
+
#define CLK_MIPI2_OUT2IO 108
122
+
#define CLK_MIPI3_OUT2IO 109
123
+
#define CLK_CIF_OUT2IO 110
124
+
#define CLK_MAC_OUT2IO 111
125
+
#define MCLK_SAI0_OUT2IO 112
126
+
#define MCLK_SAI1_OUT2IO 113
127
+
#define MCLK_SAI2_OUT2IO 114
128
+
#define CLK_CM_FRAC0_SRC 115
129
+
#define CLK_CM_FRAC1_SRC 116
130
+
#define CLK_CM_FRAC2_SRC 117
131
+
#define CLK_UART_FRAC0_SRC 118
132
+
#define CLK_UART_FRAC1_SRC 119
133
+
#define CLK_AUDIO_FRAC0_SRC 120
134
+
#define CLK_AUDIO_FRAC1_SRC 121
135
+
#define ACLK_NPU_ROOT 122
136
+
#define HCLK_RKNN 123
137
+
#define ACLK_RKNN 124
138
+
#define PCLK_GPIO3 125
139
+
#define DBCLK_GPIO3 126
140
+
#define PCLK_IOC_VCCIO3 127
141
+
#define PCLK_SARADC0 128
142
+
#define CLK_SARADC0 129
143
+
#define HCLK_SDMMC1 130
144
+
#define HCLK_VEPU 131
145
+
#define ACLK_VEPU 132
146
+
#define CLK_CORE_VEPU 133
147
+
#define HCLK_FEC 134
148
+
#define ACLK_FEC 135
149
+
#define CLK_CORE_FEC 136
150
+
#define HCLK_AVSP 137
151
+
#define ACLK_AVSP 138
152
+
#define BUSCLK_PMU1_ROOT 139
153
+
#define HCLK_AISP 140
154
+
#define ACLK_AISP 141
155
+
#define CLK_CORE_AISP 142
156
+
#define CLK_CORE_ISP_ROOT 143
157
+
#define PCLK_DSMC 144
158
+
#define ACLK_DSMC 145
159
+
#define HCLK_CAN0 146
160
+
#define HCLK_CAN1 147
161
+
#define PCLK_GPIO2 148
162
+
#define DBCLK_GPIO2 149
163
+
#define PCLK_GPIO4 150
164
+
#define DBCLK_GPIO4 151
165
+
#define PCLK_GPIO5 152
166
+
#define DBCLK_GPIO5 153
167
+
#define PCLK_GPIO6 154
168
+
#define DBCLK_GPIO6 155
169
+
#define PCLK_GPIO7 156
170
+
#define DBCLK_GPIO7 157
171
+
#define PCLK_IOC_VCCIO2 158
172
+
#define PCLK_IOC_VCCIO4 159
173
+
#define PCLK_IOC_VCCIO5 160
174
+
#define PCLK_IOC_VCCIO6 161
175
+
#define PCLK_IOC_VCCIO7 162
176
+
#define HCLK_ISP 163
177
+
#define ACLK_ISP 164
178
+
#define CLK_CORE_ISP 165
179
+
#define HCLK_VICAP 166
180
+
#define ACLK_VICAP 167
181
+
#define DCLK_VICAP 168
182
+
#define ISP0CLK_VICAP 169
183
+
#define HCLK_VPSS 170
184
+
#define ACLK_VPSS 171
185
+
#define CLK_CORE_VPSS 172
186
+
#define PCLK_CSI2HOST0 173
187
+
#define DCLK_CSI2HOST0 174
188
+
#define PCLK_CSI2HOST1 175
189
+
#define DCLK_CSI2HOST1 176
190
+
#define PCLK_CSI2HOST2 177
191
+
#define DCLK_CSI2HOST2 178
192
+
#define PCLK_CSI2HOST3 179
193
+
#define DCLK_CSI2HOST3 180
194
+
#define HCLK_SDMMC0 181
195
+
#define ACLK_GMAC 182
196
+
#define PCLK_GMAC 183
197
+
#define CLK_GMAC_PTP_REF 184
198
+
#define PCLK_CSIPHY0 185
199
+
#define PCLK_CSIPHY1 186
200
+
#define PCLK_MACPHY 187
201
+
#define PCLK_SARADC1 188
202
+
#define CLK_SARADC1 189
203
+
#define PCLK_SARADC2 190
204
+
#define CLK_SARADC2 191
205
+
#define ACLK_RKVDEC 192
206
+
#define HCLK_RKVDEC 193
207
+
#define CLK_HEVC_CA_RKVDEC 194
208
+
#define ACLK_VOP 195
209
+
#define HCLK_VOP 196
210
+
#define HCLK_RKJPEG 197
211
+
#define ACLK_RKJPEG 198
212
+
#define ACLK_RKMMU_DECOM 199
213
+
#define HCLK_RKMMU_DECOM 200
214
+
#define DCLK_DECOM 201
215
+
#define ACLK_DECOM 202
216
+
#define PCLK_DECOM 203
217
+
#define PCLK_MIPI_DSI 204
218
+
#define PCLK_DSIPHY 205
219
+
#define ACLK_OOC 206
220
+
#define ACLK_SYSMEM 207
221
+
#define PCLK_DDRC 208
222
+
#define PCLK_DDRMON 209
223
+
#define CLK_TIMER_DDRMON 210
224
+
#define PCLK_DFICTRL 211
225
+
#define PCLK_DDRPHY 212
226
+
#define PCLK_DMA2DDR 213
227
+
#define CLK_RCOSC_SRC 214
228
+
#define BUSCLK_PMU_MUX 215
229
+
#define BUSCLK_PMU_ROOT 216
230
+
#define PCLK_PMU 217
231
+
#define CLK_XIN_RC_DIV 218
232
+
#define CLK_32K 219
233
+
#define PCLK_PMU_GPIO0 220
234
+
#define DBCLK_PMU_GPIO0 221
235
+
#define PCLK_PMU_HP_TIMER 222
236
+
#define CLK_PMU_HP_TIMER 223
237
+
#define CLK_PMU_32K_HP_TIMER 224
238
+
#define PCLK_PWM1 225
239
+
#define CLK_PWM1 226
240
+
#define CLK_OSC_PWM1 227
241
+
#define CLK_RC_PWM1 228
242
+
#define CLK_FREQ_PWM1 229
243
+
#define CLK_COUNTER_PWM1 230
244
+
#define PCLK_I2C2 231
245
+
#define CLK_I2C2 232
246
+
#define PCLK_UART0 233
247
+
#define SCLK_UART0 234
248
+
#define PCLK_RCOSC_CTRL 235
249
+
#define CLK_OSC_RCOSC_CTRL 236
250
+
#define CLK_REF_RCOSC_CTRL 237
251
+
#define PCLK_IOC_PMUIO0 238
252
+
#define CLK_REFOUT 239
253
+
#define CLK_PREROLL 240
254
+
#define CLK_PREROLL_32K 241
255
+
#define HCLK_PMU_SRAM 242
256
+
#define PCLK_WDT_LPMCU 243
257
+
#define TCLK_WDT_LPMCU 244
258
+
#define CLK_LPMCU 245
259
+
#define CLK_LPMCU_RTC 246
260
+
#define PCLK_LPMCU_MAILBOX 247
261
+
#define HCLK_OOC 248
262
+
#define PCLK_SPI2AHB 249
263
+
#define HCLK_SPI2AHB 250
264
+
#define HCLK_FSPI1 251
265
+
#define HCLK_XIP_FSPI1 252
266
+
#define SCLK_1X_FSPI1 253
267
+
#define PCLK_IOC_PMUIO1 254
268
+
#define PCLK_AUDIO_ADC_PMU 255
269
+
#define MCLK_AUDIO_ADC_PMU 256
270
+
#define MCLK_AUDIO_ADC_DIV4_PMU 257
271
+
#define MCLK_LPSAI 258
272
+
#define ACLK_GIC400 259
273
+
#define PCLK_WDT_NS 260
274
+
#define TCLK_WDT_NS 261
275
+
#define PCLK_WDT_HPMCU 262
276
+
#define HCLK_CACHE 263
277
+
#define PCLK_HPMCU_MAILBOX 264
278
+
#define PCLK_HPMCU_INTMUX 265
279
+
#define CLK_HPMCU 266
280
+
#define CLK_HPMCU_RTC 267
281
+
#define PCLK_RKDMA 268
282
+
#define ACLK_RKDMA 269
283
+
#define PCLK_DCF 270
284
+
#define ACLK_DCF 271
285
+
#define HCLK_RGA 272
286
+
#define ACLK_RGA 273
287
+
#define CLK_CORE_RGA 274
288
+
#define PCLK_TIMER 275
289
+
#define CLK_TIMER0 276
290
+
#define CLK_TIMER1 277
291
+
#define CLK_TIMER2 278
292
+
#define CLK_TIMER3 279
293
+
#define CLK_TIMER4 280
294
+
#define CLK_TIMER5 281
295
+
#define PCLK_I2C0 282
296
+
#define CLK_I2C0 283
297
+
#define PCLK_I2C1 284
298
+
#define CLK_I2C1 285
299
+
#define PCLK_I2C3 286
300
+
#define CLK_I2C3 287
301
+
#define PCLK_I2C4 288
302
+
#define CLK_I2C4 289
303
+
#define PCLK_I2C5 290
304
+
#define CLK_I2C5 291
305
+
#define PCLK_SPI0 292
306
+
#define PCLK_SPI1 293
307
+
#define PCLK_PWM0 294
308
+
#define CLK_OSC_PWM0 295
309
+
#define CLK_RC_PWM0 296
310
+
#define PCLK_PWM2 297
311
+
#define CLK_OSC_PWM2 298
312
+
#define CLK_RC_PWM2 299
313
+
#define PCLK_PWM3 300
314
+
#define CLK_OSC_PWM3 301
315
+
#define CLK_RC_PWM3 302
316
+
#define PCLK_UART1 303
317
+
#define PCLK_UART2 304
318
+
#define PCLK_UART3 305
319
+
#define PCLK_UART4 306
320
+
#define PCLK_UART5 307
321
+
#define PCLK_UART6 308
322
+
#define PCLK_UART7 309
323
+
#define PCLK_TSADC 310
324
+
#define CLK_TSADC 311
325
+
#define HCLK_SAI0 312
326
+
#define HCLK_SAI1 313
327
+
#define HCLK_SAI2 314
328
+
#define HCLK_RKDSM 315
329
+
#define MCLK_RKDSM 316
330
+
#define HCLK_PDM 317
331
+
#define HCLK_ASRC0 318
332
+
#define HCLK_ASRC1 319
333
+
#define PCLK_AUDIO_ADC_BUS 320
334
+
#define MCLK_AUDIO_ADC_BUS 321
335
+
#define MCLK_AUDIO_ADC_DIV4_BUS 322
336
+
#define PCLK_RKCE 323
337
+
#define HCLK_NS_RKCE 324
338
+
#define PCLK_OTPC_NS 325
339
+
#define CLK_SBPI_OTPC_NS 326
340
+
#define CLK_USER_OTPC_NS 327
341
+
#define CLK_OTPC_ARB 328
342
+
#define PCLK_OTP_MASK 329
343
+
#define CLK_TSADC_PHYCTRL 330
344
+
#define LRCK_SRC_ASRC0 331
345
+
#define LRCK_DST_ASRC0 332
346
+
#define LRCK_SRC_ASRC1 333
347
+
#define LRCK_DST_ASRC1 334
348
+
#define PCLK_KEY_READER 335
349
+
#define ACLK_NSRKCE 336
350
+
#define CLK_PKA_NSRKCE 337
351
+
#define PCLK_RTC_ROOT 338
352
+
#define PCLK_GPIO1 339
353
+
#define DBCLK_GPIO1 340
354
+
#define PCLK_IOC_VCCIO1 341
355
+
#define ACLK_USB3OTG 342
356
+
#define CLK_REF_USB3OTG 343
357
+
#define CLK_SUSPEND_USB3OTG 344
358
+
#define HCLK_USB2HOST 345
359
+
#define HCLK_ARB_USB2HOST 346
360
+
#define PCLK_RTC_TEST 347
361
+
#define HCLK_EMMC 348
362
+
#define HCLK_FSPI0 349
363
+
#define HCLK_XIP_FSPI0 350
364
+
#define PCLK_PIPEPHY 351
365
+
#define PCLK_USB2PHY 352
366
+
#define CLK_REF_PIPEPHY_CPLL_SRC 353
367
+
#define CLK_REF_PIPEPHY 354
368
+
#define HCLK_VPSL 355
369
+
#define ACLK_VPSL 356
370
+
#define CLK_CORE_VPSL 357
371
+
#define CLK_MACPHY 358
372
+
#define HCLK_RKRNG_NS 359
373
+
#define HCLK_RKRNG_S_NS 360
374
+
#define CLK_AISP_PLL_SRC 361
375
+
376
+
/* secure clks */
377
+
#define CLK_USER_OTPC_S 362
378
+
#define CLK_SBPI_OTPC_S 363
379
+
#define PCLK_OTPC_S 364
380
+
#define PCLK_KEY_READER_S 365
381
+
#define HCLK_KL_RKCE_S 366
382
+
#define HCLK_RKCE_S 367
383
+
#define PCLK_WDT_S 368
384
+
#define TCLK_WDT_S 369
385
+
#define CLK_STIMER0 370
386
+
#define CLK_STIMER1 371
387
+
#define PLK_STIMER 372
388
+
#define HCLK_RKRNG_S 373
389
+
#define CLK_PKA_RKCE_S 374
390
+
#define ACLK_RKCE_S 375
391
+
392
+
#endif
+11
-3
include/dt-bindings/clock/toshiba,tmpv770x.h
+11
-3
include/dt-bindings/clock/toshiba,tmpv770x.h
···
11
11
#define TMPV770X_PLL_PIDDRCPLL 4
12
12
#define TMPV770X_PLL_PIVOIFPLL 5
13
13
#define TMPV770X_PLL_PIIMGERPLL 6
14
-
#define TMPV770X_NR_PLL 7
15
14
16
15
/* Clocks */
17
16
#define TMPV770X_CLK_PIPLL1_DIV1 0
···
140
141
#define TMPV770X_CLK_PIREFCLK 124
141
142
#define TMPV770X_CLK_SBUS 125
142
143
#define TMPV770X_CLK_BUSLCK 126
143
-
#define TMPV770X_NR_CLK 127
144
+
#define TMPV770X_CLK_VIIFBS1_L2ISP 127
145
+
#define TMPV770X_CLK_VIIFBS1_L1ISP 128
146
+
#define TMPV770X_CLK_VIIFBS1_PROC 129
144
147
145
148
/* Reset */
146
149
#define TMPV770X_RESET_PIETHER_2P5M 0
···
177
176
#define TMPV770X_RESET_PIPCMIF 29
178
177
#define TMPV770X_RESET_PICKMON 30
179
178
#define TMPV770X_RESET_SBUSCLK 31
180
-
#define TMPV770X_NR_RESET 32
179
+
#define TMPV770X_RESET_VIIFBS0 32
180
+
#define TMPV770X_RESET_VIIFBS0_APB 33
181
+
#define TMPV770X_RESET_VIIFBS0_L2ISP 34
182
+
#define TMPV770X_RESET_VIIFBS0_L1ISP 35
183
+
#define TMPV770X_RESET_VIIFBS1 36
184
+
#define TMPV770X_RESET_VIIFBS1_APB 37
185
+
#define TMPV770X_RESET_VIIFBS1_L2ISP 38
186
+
#define TMPV770X_RESET_VIIFBS1_L1ISP 39
181
187
182
188
#endif /*_DT_BINDINGS_CLOCK_TOSHIBA_TMPV770X_H_ */
+33
include/dt-bindings/interconnect/qcom,ipq5424.h
+33
include/dt-bindings/interconnect/qcom,ipq5424.h
···
20
20
#define SLAVE_CNOC_PCIE3 15
21
21
#define MASTER_CNOC_USB 16
22
22
#define SLAVE_CNOC_USB 17
23
+
#define MASTER_NSSNOC_NSSCC 18
24
+
#define SLAVE_NSSNOC_NSSCC 19
25
+
#define MASTER_NSSNOC_SNOC_0 20
26
+
#define SLAVE_NSSNOC_SNOC_0 21
27
+
#define MASTER_NSSNOC_SNOC_1 22
28
+
#define SLAVE_NSSNOC_SNOC_1 23
29
+
#define MASTER_NSSNOC_PCNOC_1 24
30
+
#define SLAVE_NSSNOC_PCNOC_1 25
31
+
#define MASTER_NSSNOC_QOSGEN_REF 26
32
+
#define SLAVE_NSSNOC_QOSGEN_REF 27
33
+
#define MASTER_NSSNOC_TIMEOUT_REF 28
34
+
#define SLAVE_NSSNOC_TIMEOUT_REF 29
35
+
#define MASTER_NSSNOC_XO_DCD 30
36
+
#define SLAVE_NSSNOC_XO_DCD 31
37
+
#define MASTER_NSSNOC_ATB 32
38
+
#define SLAVE_NSSNOC_ATB 33
39
+
#define MASTER_CNOC_LPASS_CFG 34
40
+
#define SLAVE_CNOC_LPASS_CFG 35
41
+
#define MASTER_SNOC_LPASS 36
42
+
#define SLAVE_SNOC_LPASS 37
23
43
24
44
#define MASTER_CPU 0
25
45
#define SLAVE_L3 1
46
+
47
+
#define MASTER_NSSNOC_PPE 0
48
+
#define SLAVE_NSSNOC_PPE 1
49
+
#define MASTER_NSSNOC_PPE_CFG 2
50
+
#define SLAVE_NSSNOC_PPE_CFG 3
51
+
#define MASTER_NSSNOC_NSS_CSR 4
52
+
#define SLAVE_NSSNOC_NSS_CSR 5
53
+
#define MASTER_NSSNOC_CE_AXI 6
54
+
#define SLAVE_NSSNOC_CE_AXI 7
55
+
#define MASTER_NSSNOC_CE_APB 8
56
+
#define SLAVE_NSSNOC_CE_APB 9
57
+
#define MASTER_NSSNOC_EIP 10
58
+
#define SLAVE_NSSNOC_EIP 11
26
59
27
60
#endif /* INTERCONNECT_QCOM_IPQ5424_H */
+16
include/dt-bindings/reset/fsl,imx8ulp-sim-lpav.h
+16
include/dt-bindings/reset/fsl,imx8ulp-sim-lpav.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright 2025 NXP
4
+
*/
5
+
6
+
#ifndef DT_BINDING_RESET_IMX8ULP_SIM_LPAV_H
7
+
#define DT_BINDING_RESET_IMX8ULP_SIM_LPAV_H
8
+
9
+
#define IMX8ULP_SIM_LPAV_HIFI4_DSP_DBG_RST 0
10
+
#define IMX8ULP_SIM_LPAV_HIFI4_DSP_RST 1
11
+
#define IMX8ULP_SIM_LPAV_HIFI4_DSP_STALL 2
12
+
#define IMX8ULP_SIM_LPAV_DSI_RST_BYTE_N 3
13
+
#define IMX8ULP_SIM_LPAV_DSI_RST_ESC_N 4
14
+
#define IMX8ULP_SIM_LPAV_DSI_RST_DPI_N 5
15
+
16
+
#endif /* DT_BINDING_RESET_IMX8ULP_SIM_LPAV_H */
+46
include/dt-bindings/reset/qcom,ipq5424-nsscc.h
+46
include/dt-bindings/reset/qcom,ipq5424-nsscc.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
4
+
*/
5
+
6
+
#ifndef _DT_BINDINGS_RESET_QCOM_IPQ5424_NSSCC_H
7
+
#define _DT_BINDINGS_RESET_QCOM_IPQ5424_NSSCC_H
8
+
9
+
#define NSS_CC_CE_APB_CLK_ARES 0
10
+
#define NSS_CC_CE_AXI_CLK_ARES 1
11
+
#define NSS_CC_DEBUG_CLK_ARES 2
12
+
#define NSS_CC_EIP_CLK_ARES 3
13
+
#define NSS_CC_NSS_CSR_CLK_ARES 4
14
+
#define NSS_CC_NSSNOC_CE_APB_CLK_ARES 5
15
+
#define NSS_CC_NSSNOC_CE_AXI_CLK_ARES 6
16
+
#define NSS_CC_NSSNOC_EIP_CLK_ARES 7
17
+
#define NSS_CC_NSSNOC_NSS_CSR_CLK_ARES 8
18
+
#define NSS_CC_NSSNOC_PPE_CLK_ARES 9
19
+
#define NSS_CC_NSSNOC_PPE_CFG_CLK_ARES 10
20
+
#define NSS_CC_PORT1_MAC_CLK_ARES 11
21
+
#define NSS_CC_PORT1_RX_CLK_ARES 12
22
+
#define NSS_CC_PORT1_TX_CLK_ARES 13
23
+
#define NSS_CC_PORT2_MAC_CLK_ARES 14
24
+
#define NSS_CC_PORT2_RX_CLK_ARES 15
25
+
#define NSS_CC_PORT2_TX_CLK_ARES 16
26
+
#define NSS_CC_PORT3_MAC_CLK_ARES 17
27
+
#define NSS_CC_PORT3_RX_CLK_ARES 18
28
+
#define NSS_CC_PORT3_TX_CLK_ARES 19
29
+
#define NSS_CC_PPE_BCR 20
30
+
#define NSS_CC_PPE_EDMA_CLK_ARES 21
31
+
#define NSS_CC_PPE_EDMA_CFG_CLK_ARES 22
32
+
#define NSS_CC_PPE_SWITCH_BTQ_CLK_ARES 23
33
+
#define NSS_CC_PPE_SWITCH_CLK_ARES 24
34
+
#define NSS_CC_PPE_SWITCH_CFG_CLK_ARES 25
35
+
#define NSS_CC_PPE_SWITCH_IPE_CLK_ARES 26
36
+
#define NSS_CC_UNIPHY_PORT1_RX_CLK_ARES 27
37
+
#define NSS_CC_UNIPHY_PORT1_TX_CLK_ARES 28
38
+
#define NSS_CC_UNIPHY_PORT2_RX_CLK_ARES 29
39
+
#define NSS_CC_UNIPHY_PORT2_TX_CLK_ARES 30
40
+
#define NSS_CC_UNIPHY_PORT3_RX_CLK_ARES 31
41
+
#define NSS_CC_UNIPHY_PORT3_TX_CLK_ARES 32
42
+
#define NSS_CC_XGMAC0_PTP_REF_CLK_ARES 33
43
+
#define NSS_CC_XGMAC1_PTP_REF_CLK_ARES 34
44
+
#define NSS_CC_XGMAC2_PTP_REF_CLK_ARES 35
45
+
46
+
#endif
+211
include/dt-bindings/reset/rockchip,rk3506-cru.h
+211
include/dt-bindings/reset/rockchip,rk3506-cru.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (c) 2023-2025 Rockchip Electronics Co., Ltd.
4
+
* Author: Finley Xiao <finley.xiao@rock-chips.com>
5
+
*/
6
+
7
+
#ifndef _DT_BINDINGS_REST_ROCKCHIP_RK3506_H
8
+
#define _DT_BINDINGS_REST_ROCKCHIP_RK3506_H
9
+
10
+
/* CRU-->SOFTRST_CON00 */
11
+
#define SRST_NCOREPORESET0_AC 0
12
+
#define SRST_NCOREPORESET1_AC 1
13
+
#define SRST_NCOREPORESET2_AC 2
14
+
#define SRST_NCORESET0_AC 3
15
+
#define SRST_NCORESET1_AC 4
16
+
#define SRST_NCORESET2_AC 5
17
+
#define SRST_NL2RESET_AC 6
18
+
#define SRST_A_CORE_BIU_AC 7
19
+
#define SRST_H_M0_AC 8
20
+
21
+
/* CRU-->SOFTRST_CON02 */
22
+
#define SRST_NDBGRESET 9
23
+
#define SRST_P_CORE_BIU 10
24
+
#define SRST_PMU 11
25
+
26
+
/* CRU-->SOFTRST_CON03 */
27
+
#define SRST_P_DBG 12
28
+
#define SRST_POT_DBG 13
29
+
#define SRST_P_CORE_GRF 14
30
+
#define SRST_CORE_EMA_DETECT 15
31
+
#define SRST_REF_PVTPLL_CORE 16
32
+
#define SRST_P_GPIO1 17
33
+
#define SRST_DB_GPIO1 18
34
+
35
+
/* CRU-->SOFTRST_CON04 */
36
+
#define SRST_A_CORE_PERI_BIU 19
37
+
#define SRST_A_DSMC 20
38
+
#define SRST_P_DSMC 21
39
+
#define SRST_FLEXBUS 22
40
+
#define SRST_A_FLEXBUS 23
41
+
#define SRST_H_FLEXBUS 24
42
+
#define SRST_A_DSMC_SLV 25
43
+
#define SRST_H_DSMC_SLV 26
44
+
#define SRST_DSMC_SLV 27
45
+
46
+
/* CRU-->SOFTRST_CON05 */
47
+
#define SRST_A_BUS_BIU 28
48
+
#define SRST_H_BUS_BIU 29
49
+
#define SRST_P_BUS_BIU 30
50
+
#define SRST_A_SYSRAM 31
51
+
#define SRST_H_SYSRAM 32
52
+
#define SRST_A_DMAC0 33
53
+
#define SRST_A_DMAC1 34
54
+
#define SRST_H_M0 35
55
+
#define SRST_M0_JTAG 36
56
+
#define SRST_H_CRYPTO 37
57
+
58
+
/* CRU-->SOFTRST_CON06 */
59
+
#define SRST_H_RNG 38
60
+
#define SRST_P_BUS_GRF 39
61
+
#define SRST_P_TIMER0 40
62
+
#define SRST_TIMER0_CH0 41
63
+
#define SRST_TIMER0_CH1 42
64
+
#define SRST_TIMER0_CH2 43
65
+
#define SRST_TIMER0_CH3 44
66
+
#define SRST_TIMER0_CH4 45
67
+
#define SRST_TIMER0_CH5 46
68
+
#define SRST_P_WDT0 47
69
+
#define SRST_T_WDT0 48
70
+
#define SRST_P_WDT1 49
71
+
#define SRST_T_WDT1 50
72
+
#define SRST_P_MAILBOX 51
73
+
#define SRST_P_INTMUX 52
74
+
#define SRST_P_SPINLOCK 53
75
+
76
+
/* CRU-->SOFTRST_CON07 */
77
+
#define SRST_P_DDRC 54
78
+
#define SRST_H_DDRPHY 55
79
+
#define SRST_P_DDRMON 56
80
+
#define SRST_DDRMON_OSC 57
81
+
#define SRST_P_DDR_LPC 58
82
+
#define SRST_H_USBOTG0 59
83
+
#define SRST_USBOTG0_ADP 60
84
+
#define SRST_H_USBOTG1 61
85
+
#define SRST_USBOTG1_ADP 62
86
+
#define SRST_P_USBPHY 63
87
+
#define SRST_USBPHY_POR 64
88
+
#define SRST_USBPHY_OTG0 65
89
+
#define SRST_USBPHY_OTG1 66
90
+
91
+
/* CRU-->SOFTRST_CON08 */
92
+
#define SRST_A_DMA2DDR 67
93
+
#define SRST_P_DMA2DDR 68
94
+
95
+
/* CRU-->SOFTRST_CON09 */
96
+
#define SRST_USBOTG0_UTMI 69
97
+
#define SRST_USBOTG1_UTMI 70
98
+
99
+
/* CRU-->SOFTRST_CON10 */
100
+
#define SRST_A_DDRC_0 71
101
+
#define SRST_A_DDRC_1 72
102
+
#define SRST_A_DDR_BIU 73
103
+
#define SRST_DDRC 74
104
+
#define SRST_DDRMON 75
105
+
106
+
/* CRU-->SOFTRST_CON11 */
107
+
#define SRST_H_LSPERI_BIU 76
108
+
#define SRST_P_UART0 77
109
+
#define SRST_P_UART1 78
110
+
#define SRST_P_UART2 79
111
+
#define SRST_P_UART3 80
112
+
#define SRST_P_UART4 81
113
+
#define SRST_UART0 82
114
+
#define SRST_UART1 83
115
+
#define SRST_UART2 84
116
+
#define SRST_UART3 85
117
+
#define SRST_UART4 86
118
+
#define SRST_P_I2C0 87
119
+
#define SRST_I2C0 88
120
+
121
+
/* CRU-->SOFTRST_CON12 */
122
+
#define SRST_P_I2C1 89
123
+
#define SRST_I2C1 90
124
+
#define SRST_P_I2C2 91
125
+
#define SRST_I2C2 92
126
+
#define SRST_P_PWM1 93
127
+
#define SRST_PWM1 94
128
+
#define SRST_P_SPI0 95
129
+
#define SRST_SPI0 96
130
+
#define SRST_P_SPI1 97
131
+
#define SRST_SPI1 98
132
+
#define SRST_P_GPIO2 99
133
+
#define SRST_DB_GPIO2 100
134
+
135
+
/* CRU-->SOFTRST_CON13 */
136
+
#define SRST_P_GPIO3 101
137
+
#define SRST_DB_GPIO3 102
138
+
#define SRST_P_GPIO4 103
139
+
#define SRST_DB_GPIO4 104
140
+
#define SRST_H_CAN0 105
141
+
#define SRST_CAN0 106
142
+
#define SRST_H_CAN1 107
143
+
#define SRST_CAN1 108
144
+
#define SRST_H_PDM 109
145
+
#define SRST_M_PDM 110
146
+
#define SRST_PDM 111
147
+
#define SRST_SPDIFTX 112
148
+
#define SRST_H_SPDIFTX 113
149
+
#define SRST_H_SPDIFRX 114
150
+
#define SRST_SPDIFRX 115
151
+
#define SRST_M_SAI0 116
152
+
153
+
/* CRU-->SOFTRST_CON14 */
154
+
#define SRST_H_SAI0 117
155
+
#define SRST_M_SAI1 118
156
+
#define SRST_H_SAI1 119
157
+
#define SRST_H_ASRC0 120
158
+
#define SRST_ASRC0 121
159
+
#define SRST_H_ASRC1 122
160
+
#define SRST_ASRC1 123
161
+
162
+
/* CRU-->SOFTRST_CON17 */
163
+
#define SRST_H_HSPERI_BIU 124
164
+
#define SRST_H_SDMMC 125
165
+
#define SRST_H_FSPI 126
166
+
#define SRST_S_FSPI 127
167
+
#define SRST_P_SPI2 128
168
+
#define SRST_A_MAC0 129
169
+
#define SRST_A_MAC1 130
170
+
171
+
/* CRU-->SOFTRST_CON18 */
172
+
#define SRST_M_SAI2 131
173
+
#define SRST_H_SAI2 132
174
+
#define SRST_H_SAI3 133
175
+
#define SRST_M_SAI3 134
176
+
#define SRST_H_SAI4 135
177
+
#define SRST_M_SAI4 136
178
+
#define SRST_H_DSM 137
179
+
#define SRST_M_DSM 138
180
+
#define SRST_P_AUDIO_ADC 139
181
+
#define SRST_M_AUDIO_ADC 140
182
+
183
+
/* CRU-->SOFTRST_CON19 */
184
+
#define SRST_P_SARADC 141
185
+
#define SRST_SARADC 142
186
+
#define SRST_SARADC_PHY 143
187
+
#define SRST_P_OTPC_NS 144
188
+
#define SRST_SBPI_OTPC_NS 145
189
+
#define SRST_USER_OTPC_NS 146
190
+
#define SRST_P_UART5 147
191
+
#define SRST_UART5 148
192
+
#define SRST_P_GPIO234_IOC 149
193
+
194
+
/* CRU-->SOFTRST_CON21 */
195
+
#define SRST_A_VIO_BIU 150
196
+
#define SRST_H_VIO_BIU 151
197
+
#define SRST_H_RGA 152
198
+
#define SRST_A_RGA 153
199
+
#define SRST_CORE_RGA 154
200
+
#define SRST_A_VOP 155
201
+
#define SRST_H_VOP 156
202
+
#define SRST_VOP 157
203
+
#define SRST_P_DPHY 158
204
+
#define SRST_P_DSI_HOST 159
205
+
#define SRST_P_TSADC 160
206
+
#define SRST_TSADC 161
207
+
208
+
/* CRU-->SOFTRST_CON22 */
209
+
#define SRST_P_GPIO1_IOC 162
210
+
211
+
#endif
+405
include/dt-bindings/reset/rockchip,rv1126b-cru.h
+405
include/dt-bindings/reset/rockchip,rv1126b-cru.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
2
+
/*
3
+
* Copyright (c) 2025 Rockchip Electronics Co., Ltd.
4
+
* Author: Elaine Zhang <zhangqing@rock-chips.com>
5
+
*/
6
+
7
+
#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RV1126B_H
8
+
#define _DT_BINDINGS_RESET_ROCKCHIP_RV1126B_H
9
+
10
+
/* ==========================list all of reset fields id=========================== */
11
+
/* TOPCRU-->SOFTRST_CON00 */
12
+
13
+
/* TOPCRU-->SOFTRST_CON15 */
14
+
#define SRST_P_CRU 0
15
+
#define SRST_P_CRU_BIU 1
16
+
17
+
/* BUSCRU-->SOFTRST_CON00 */
18
+
#define SRST_A_TOP_BIU 2
19
+
#define SRST_A_RKCE_BIU 3
20
+
#define SRST_A_BUS_BIU 4
21
+
#define SRST_H_BUS_BIU 5
22
+
#define SRST_P_BUS_BIU 6
23
+
#define SRST_P_CRU_BUS 7
24
+
#define SRST_P_SYS_GRF 8
25
+
#define SRST_H_BOOTROM 9
26
+
#define SRST_A_GIC400 10
27
+
#define SRST_A_SPINLOCK 11
28
+
#define SRST_P_WDT_NS 12
29
+
#define SRST_T_WDT_NS 13
30
+
31
+
/* BUSCRU-->SOFTRST_CON01 */
32
+
#define SRST_P_WDT_HPMCU 14
33
+
#define SRST_T_WDT_HPMCU 15
34
+
#define SRST_H_CACHE 16
35
+
#define SRST_P_HPMCU_MAILBOX 17
36
+
#define SRST_P_HPMCU_INTMUX 18
37
+
#define SRST_HPMCU_FULL_CLUSTER 19
38
+
#define SRST_HPMCU_PWUP 20
39
+
#define SRST_HPMCU_ONLY_CORE 21
40
+
#define SRST_T_HPMCU_JTAG 22
41
+
#define SRST_P_RKDMA 23
42
+
#define SRST_A_RKDMA 24
43
+
44
+
/* BUSCRU-->SOFTRST_CON02 */
45
+
#define SRST_P_DCF 25
46
+
#define SRST_A_DCF 26
47
+
#define SRST_H_RGA 27
48
+
#define SRST_A_RGA 28
49
+
#define SRST_CORE_RGA 29
50
+
#define SRST_P_TIMER 30
51
+
#define SRST_TIMER0 31
52
+
#define SRST_TIMER1 32
53
+
#define SRST_TIMER2 33
54
+
#define SRST_TIMER3 34
55
+
#define SRST_TIMER4 35
56
+
#define SRST_TIMER5 36
57
+
#define SRST_A_RKCE 37
58
+
#define SRST_PKA_RKCE 38
59
+
#define SRST_H_RKRNG_S 39
60
+
#define SRST_H_RKRNG_NS 40
61
+
62
+
/* BUSCRU-->SOFTRST_CON03 */
63
+
#define SRST_P_I2C0 41
64
+
#define SRST_I2C0 42
65
+
#define SRST_P_I2C1 43
66
+
#define SRST_I2C1 44
67
+
#define SRST_P_I2C3 45
68
+
#define SRST_I2C3 46
69
+
#define SRST_P_I2C4 47
70
+
#define SRST_I2C4 48
71
+
#define SRST_P_I2C5 49
72
+
#define SRST_I2C5 50
73
+
#define SRST_P_SPI0 51
74
+
#define SRST_SPI0 52
75
+
#define SRST_P_SPI1 53
76
+
#define SRST_SPI1 54
77
+
78
+
/* BUSCRU-->SOFTRST_CON04 */
79
+
#define SRST_P_PWM0 55
80
+
#define SRST_PWM0 56
81
+
#define SRST_P_PWM2 57
82
+
#define SRST_PWM2 58
83
+
#define SRST_P_PWM3 59
84
+
#define SRST_PWM3 60
85
+
86
+
/* BUSCRU-->SOFTRST_CON05 */
87
+
#define SRST_P_UART1 61
88
+
#define SRST_S_UART1 62
89
+
#define SRST_P_UART2 63
90
+
#define SRST_S_UART2 64
91
+
#define SRST_P_UART3 65
92
+
#define SRST_S_UART3 66
93
+
#define SRST_P_UART4 67
94
+
#define SRST_S_UART4 68
95
+
#define SRST_P_UART5 69
96
+
#define SRST_S_UART5 70
97
+
#define SRST_P_UART6 71
98
+
#define SRST_S_UART6 72
99
+
#define SRST_P_UART7 73
100
+
#define SRST_S_UART7 74
101
+
102
+
/* BUSCRU-->SOFTRST_CON06 */
103
+
#define SRST_P_TSADC 75
104
+
#define SRST_TSADC 76
105
+
#define SRST_H_SAI0 77
106
+
#define SRST_M_SAI0 78
107
+
#define SRST_H_SAI1 79
108
+
#define SRST_M_SAI1 80
109
+
#define SRST_H_SAI2 81
110
+
#define SRST_M_SAI2 82
111
+
#define SRST_H_RKDSM 83
112
+
#define SRST_M_RKDSM 84
113
+
#define SRST_H_PDM 85
114
+
#define SRST_M_PDM 86
115
+
#define SRST_PDM 87
116
+
117
+
/* BUSCRU-->SOFTRST_CON07 */
118
+
#define SRST_H_ASRC0 88
119
+
#define SRST_ASRC0 89
120
+
#define SRST_H_ASRC1 90
121
+
#define SRST_ASRC1 91
122
+
#define SRST_P_AUDIO_ADC_BUS 92
123
+
#define SRST_M_AUDIO_ADC_BUS 93
124
+
#define SRST_P_RKCE 94
125
+
#define SRST_H_NS_RKCE 95
126
+
#define SRST_P_OTPC_NS 96
127
+
#define SRST_SBPI_OTPC_NS 97
128
+
#define SRST_USER_OTPC_NS 98
129
+
#define SRST_OTPC_ARB 99
130
+
#define SRST_P_OTP_MASK 100
131
+
132
+
/* PERICRU-->SOFTRST_CON00 */
133
+
#define SRST_A_PERI_BIU 101
134
+
#define SRST_P_PERI_BIU 102
135
+
#define SRST_P_RTC_BIU 103
136
+
#define SRST_P_CRU_PERI 104
137
+
#define SRST_P_PERI_GRF 105
138
+
#define SRST_P_GPIO1 106
139
+
#define SRST_DB_GPIO1 107
140
+
#define SRST_P_IOC_VCCIO1 108
141
+
#define SRST_A_USB3OTG 109
142
+
#define SRST_H_USB2HOST 110
143
+
#define SRST_H_ARB_USB2HOST 111
144
+
#define SRST_P_RTC_TEST 112
145
+
146
+
/* PERICRU-->SOFTRST_CON01 */
147
+
#define SRST_H_EMMC 113
148
+
#define SRST_H_FSPI0 114
149
+
#define SRST_H_XIP_FSPI0 115
150
+
#define SRST_S_2X_FSPI0 116
151
+
#define SRST_UTMI_USB2HOST 117
152
+
#define SRST_REF_PIPEPHY 118
153
+
#define SRST_P_PIPEPHY 119
154
+
#define SRST_P_PIPEPHY_GRF 120
155
+
#define SRST_P_USB2PHY 121
156
+
#define SRST_POR_USB2PHY 122
157
+
#define SRST_OTG_USB2PHY 123
158
+
#define SRST_HOST_USB2PHY 124
159
+
160
+
/* CORECRU-->SOFTRST_CON00 */
161
+
#define SRST_REF_PVTPLL_CORE 125
162
+
#define SRST_NCOREPORESET0 126
163
+
#define SRST_NCORESET0 127
164
+
#define SRST_NCOREPORESET1 128
165
+
#define SRST_NCORESET1 129
166
+
#define SRST_NCOREPORESET2 130
167
+
#define SRST_NCORESET2 131
168
+
#define SRST_NCOREPORESET3 132
169
+
#define SRST_NCORESET3 133
170
+
#define SRST_NDBGRESET 134
171
+
#define SRST_NL2RESET 135
172
+
173
+
/* CORECRU-->SOFTRST_CON01 */
174
+
#define SRST_A_CORE_BIU 136
175
+
#define SRST_P_CORE_BIU 137
176
+
#define SRST_H_CORE_BIU 138
177
+
#define SRST_P_DBG 139
178
+
#define SRST_POT_DBG 140
179
+
#define SRST_NT_DBG 141
180
+
#define SRST_P_CORE_PVTPLL 142
181
+
#define SRST_P_CRU_CORE 143
182
+
#define SRST_P_CORE_GRF 144
183
+
#define SRST_P_DFT2APB 145
184
+
185
+
/* PMUCRU-->SOFTRST_CON00 */
186
+
#define SRST_H_PMU_BIU 146
187
+
#define SRST_P_PMU_GPIO0 147
188
+
#define SRST_DB_PMU_GPIO0 148
189
+
#define SRST_P_PMU_HP_TIMER 149
190
+
#define SRST_PMU_HP_TIMER 150
191
+
#define SRST_PMU_32K_HP_TIMER 151
192
+
193
+
/* PMUCRU-->SOFTRST_CON01 */
194
+
#define SRST_P_PWM1 152
195
+
#define SRST_PWM1 153
196
+
#define SRST_P_I2C2 154
197
+
#define SRST_I2C2 155
198
+
#define SRST_P_UART0 156
199
+
#define SRST_S_UART0 157
200
+
201
+
/* PMUCRU-->SOFTRST_CON02 */
202
+
#define SRST_P_RCOSC_CTRL 158
203
+
#define SRST_REF_RCOSC_CTRL 159
204
+
#define SRST_P_IOC_PMUIO0 160
205
+
#define SRST_P_CRU_PMU 161
206
+
#define SRST_P_PMU_GRF 162
207
+
#define SRST_PREROLL 163
208
+
#define SRST_PREROLL_32K 164
209
+
#define SRST_H_PMU_SRAM 165
210
+
211
+
/* PMUCRU-->SOFTRST_CON03 */
212
+
#define SRST_P_WDT_LPMCU 166
213
+
#define SRST_T_WDT_LPMCU 167
214
+
#define SRST_LPMCU_FULL_CLUSTER 168
215
+
#define SRST_LPMCU_PWUP 169
216
+
#define SRST_LPMCU_ONLY_CORE 170
217
+
#define SRST_T_LPMCU_JTAG 171
218
+
#define SRST_P_LPMCU_MAILBOX 172
219
+
220
+
/* PMU1CRU-->SOFTRST_CON00 */
221
+
#define SRST_P_SPI2AHB 173
222
+
#define SRST_H_SPI2AHB 174
223
+
#define SRST_H_FSPI1 175
224
+
#define SRST_H_XIP_FSPI1 176
225
+
#define SRST_S_1X_FSPI1 177
226
+
#define SRST_P_IOC_PMUIO1 178
227
+
#define SRST_P_CRU_PMU1 179
228
+
#define SRST_P_AUDIO_ADC_PMU 180
229
+
#define SRST_M_AUDIO_ADC_PMU 181
230
+
#define SRST_H_PMU1_BIU 182
231
+
232
+
/* PMU1CRU-->SOFTRST_CON01 */
233
+
#define SRST_P_LPDMA 183
234
+
#define SRST_A_LPDMA 184
235
+
#define SRST_H_LPSAI 185
236
+
#define SRST_M_LPSAI 186
237
+
#define SRST_P_AOA_TDD 187
238
+
#define SRST_P_AOA_FE 188
239
+
#define SRST_P_AOA_AAD 189
240
+
#define SRST_P_AOA_APB 190
241
+
#define SRST_P_AOA_SRAM 191
242
+
243
+
/* DDRCRU-->SOFTRST_CON00 */
244
+
#define SRST_P_DDR_BIU 192
245
+
#define SRST_P_DDRC 193
246
+
#define SRST_P_DDRMON 194
247
+
#define SRST_TIMER_DDRMON 195
248
+
#define SRST_P_DFICTRL 196
249
+
#define SRST_P_DDR_GRF 197
250
+
#define SRST_P_CRU_DDR 198
251
+
#define SRST_P_DDRPHY 199
252
+
#define SRST_P_DMA2DDR 200
253
+
254
+
/* SUBDDRCRU-->SOFTRST_CON00 */
255
+
#define SRST_A_SYSMEM_BIU 201
256
+
#define SRST_A_SYSMEM 202
257
+
#define SRST_A_DDR_BIU 203
258
+
#define SRST_A_DDRSCH0_CPU 204
259
+
#define SRST_A_DDRSCH1_NPU 205
260
+
#define SRST_A_DDRSCH2_POE 206
261
+
#define SRST_A_DDRSCH3_VI 207
262
+
#define SRST_CORE_DDRC 208
263
+
#define SRST_DDRMON 209
264
+
#define SRST_DFICTRL 210
265
+
#define SRST_RS 211
266
+
#define SRST_A_DMA2DDR 212
267
+
#define SRST_DDRPHY 213
268
+
269
+
/* VICRU-->SOFTRST_CON00 */
270
+
#define SRST_REF_PVTPLL_ISP 214
271
+
#define SRST_A_GMAC_BIU 215
272
+
#define SRST_A_VI_BIU 216
273
+
#define SRST_H_VI_BIU 217
274
+
#define SRST_P_VI_BIU 218
275
+
#define SRST_P_CRU_VI 219
276
+
#define SRST_P_VI_GRF 220
277
+
#define SRST_P_VI_PVTPLL 221
278
+
#define SRST_P_DSMC 222
279
+
#define SRST_A_DSMC 223
280
+
#define SRST_H_CAN0 224
281
+
#define SRST_CAN0 225
282
+
#define SRST_H_CAN1 226
283
+
#define SRST_CAN1 227
284
+
285
+
/* VICRU-->SOFTRST_CON01 */
286
+
#define SRST_P_GPIO2 228
287
+
#define SRST_DB_GPIO2 229
288
+
#define SRST_P_GPIO4 230
289
+
#define SRST_DB_GPIO4 231
290
+
#define SRST_P_GPIO5 232
291
+
#define SRST_DB_GPIO5 233
292
+
#define SRST_P_GPIO6 234
293
+
#define SRST_DB_GPIO6 235
294
+
#define SRST_P_GPIO7 236
295
+
#define SRST_DB_GPIO7 237
296
+
#define SRST_P_IOC_VCCIO2 238
297
+
#define SRST_P_IOC_VCCIO4 239
298
+
#define SRST_P_IOC_VCCIO5 240
299
+
#define SRST_P_IOC_VCCIO6 241
300
+
#define SRST_P_IOC_VCCIO7 242
301
+
302
+
/* VICRU-->SOFTRST_CON02 */
303
+
#define SRST_CORE_ISP 243
304
+
#define SRST_H_VICAP 244
305
+
#define SRST_A_VICAP 245
306
+
#define SRST_D_VICAP 246
307
+
#define SRST_ISP0_VICAP 247
308
+
#define SRST_CORE_VPSS 248
309
+
#define SRST_CORE_VPSL 249
310
+
#define SRST_P_CSI2HOST0 250
311
+
#define SRST_P_CSI2HOST1 251
312
+
#define SRST_P_CSI2HOST2 252
313
+
#define SRST_P_CSI2HOST3 253
314
+
#define SRST_H_SDMMC0 254
315
+
#define SRST_A_GMAC 255
316
+
#define SRST_P_CSIPHY0 256
317
+
#define SRST_P_CSIPHY1 257
318
+
319
+
/* VICRU-->SOFTRST_CON03 */
320
+
#define SRST_P_MACPHY 258
321
+
#define SRST_MACPHY 259
322
+
#define SRST_P_SARADC1 260
323
+
#define SRST_SARADC1 261
324
+
#define SRST_P_SARADC2 262
325
+
#define SRST_SARADC2 263
326
+
327
+
/* VEPUCRU-->SOFTRST_CON00 */
328
+
#define SRST_REF_PVTPLL_VEPU 264
329
+
#define SRST_A_VEPU_BIU 265
330
+
#define SRST_H_VEPU_BIU 266
331
+
#define SRST_P_VEPU_BIU 267
332
+
#define SRST_P_CRU_VEPU 268
333
+
#define SRST_P_VEPU_GRF 269
334
+
#define SRST_P_GPIO3 270
335
+
#define SRST_DB_GPIO3 271
336
+
#define SRST_P_IOC_VCCIO3 272
337
+
#define SRST_P_SARADC0 273
338
+
#define SRST_SARADC0 274
339
+
#define SRST_H_SDMMC1 275
340
+
341
+
/* VEPUCRU-->SOFTRST_CON01 */
342
+
#define SRST_P_VEPU_PVTPLL 276
343
+
#define SRST_H_VEPU 277
344
+
#define SRST_A_VEPU 278
345
+
#define SRST_CORE_VEPU 279
346
+
347
+
/* NPUCRU-->SOFTRST_CON00 */
348
+
#define SRST_REF_PVTPLL_NPU 280
349
+
#define SRST_A_NPU_BIU 281
350
+
#define SRST_H_NPU_BIU 282
351
+
#define SRST_P_NPU_BIU 283
352
+
#define SRST_P_CRU_NPU 284
353
+
#define SRST_P_NPU_GRF 285
354
+
#define SRST_P_NPU_PVTPLL 286
355
+
#define SRST_H_RKNN 287
356
+
#define SRST_A_RKNN 288
357
+
358
+
/* VDOCRU-->SOFTRST_CON00 */
359
+
#define SRST_A_RKVDEC_BIU 289
360
+
#define SRST_A_VDO_BIU 290
361
+
#define SRST_H_VDO_BIU 291
362
+
#define SRST_P_VDO_BIU 292
363
+
#define SRST_P_CRU_VDO 293
364
+
#define SRST_P_VDO_GRF 294
365
+
#define SRST_A_RKVDEC 295
366
+
#define SRST_H_RKVDEC 296
367
+
#define SRST_HEVC_CA_RKVDEC 297
368
+
#define SRST_A_VOP 298
369
+
#define SRST_H_VOP 299
370
+
#define SRST_D_VOP 300
371
+
#define SRST_A_OOC 301
372
+
#define SRST_H_OOC 302
373
+
#define SRST_D_OOC 303
374
+
375
+
/* VDOCRU-->SOFTRST_CON01 */
376
+
#define SRST_H_RKJPEG 304
377
+
#define SRST_A_RKJPEG 305
378
+
#define SRST_A_RKMMU_DECOM 306
379
+
#define SRST_H_RKMMU_DECOM 307
380
+
#define SRST_D_DECOM 308
381
+
#define SRST_A_DECOM 309
382
+
#define SRST_P_DECOM 310
383
+
#define SRST_P_MIPI_DSI 311
384
+
#define SRST_P_DSIPHY 312
385
+
386
+
/* VCPCRU-->SOFTRST_CON00 */
387
+
#define SRST_REF_PVTPLL_VCP 313
388
+
#define SRST_A_VCP_BIU 314
389
+
#define SRST_H_VCP_BIU 315
390
+
#define SRST_P_VCP_BIU 316
391
+
#define SRST_P_CRU_VCP 317
392
+
#define SRST_P_VCP_GRF 318
393
+
#define SRST_P_VCP_PVTPLL 319
394
+
#define SRST_A_AISP_BIU 320
395
+
#define SRST_H_AISP_BIU 321
396
+
#define SRST_CORE_AISP 322
397
+
398
+
/* VCPCRU-->SOFTRST_CON01 */
399
+
#define SRST_H_FEC 323
400
+
#define SRST_A_FEC 324
401
+
#define SRST_CORE_FEC 325
402
+
#define SRST_H_AVSP 326
403
+
#define SRST_A_AVSP 327
404
+
405
+
#endif
+8
-1
include/dt-bindings/reset/toshiba,tmpv770x.h
+8
-1
include/dt-bindings/reset/toshiba,tmpv770x.h
···
36
36
#define TMPV770X_RESET_PIPCMIF 29
37
37
#define TMPV770X_RESET_PICKMON 30
38
38
#define TMPV770X_RESET_SBUSCLK 31
39
-
#define TMPV770X_NR_RESET 32
39
+
#define TMPV770X_RESET_VIIFBS0 32
40
+
#define TMPV770X_RESET_VIIFBS0_APB 33
41
+
#define TMPV770X_RESET_VIIFBS0_L2ISP 34
42
+
#define TMPV770X_RESET_VIIFBS0_L1ISP 35
43
+
#define TMPV770X_RESET_VIIFBS1 36
44
+
#define TMPV770X_RESET_VIIFBS1_APB 37
45
+
#define TMPV770X_RESET_VIIFBS1_L2ISP 38
46
+
#define TMPV770X_RESET_VIIFBS1_L1ISP 39
40
47
41
48
#endif /*_DT_BINDINGS_RESET_TOSHIBA_TMPV770X_H_ */
+2
-1
include/soc/microchip/mpfs.h
+2
-1
include/soc/microchip/mpfs.h
···
14
14
15
15
#include <linux/types.h>
16
16
#include <linux/of_device.h>
17
+
#include <linux/regmap.h>
17
18
18
19
struct mpfs_sys_controller;
19
20
···
45
44
46
45
#if IS_ENABLED(CONFIG_MCHP_CLK_MPFS)
47
46
#if IS_ENABLED(CONFIG_RESET_POLARFIRE_SOC)
48
-
int mpfs_reset_controller_register(struct device *clk_dev, void __iomem *base);
47
+
int mpfs_reset_controller_register(struct device *clk_dev, struct regmap *map);
49
48
#else
50
49
static inline int mpfs_reset_controller_register(struct device *clk_dev, void __iomem *base) { return 0; }
51
50
#endif /* if IS_ENABLED(CONFIG_RESET_POLARFIRE_SOC) */