tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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x86,fs/resctrl: Detect io_alloc feature

AMD's SDCIAE (SDCI Allocation Enforcement) PQE feature enables system software
to control the portions of L3 cache used for direct insertion of data from I/O
devices into the L3 cache.

Introduce a generic resctrl cache resource property "io_alloc_capable" as the
first part of the new "io_alloc" resctrl feature that will support AMD's
SDCIAE. Any architecture can set a cache resource as "io_alloc_capable" if
a portion of the cache can be allocated for I/O traffic.

Set the "io_alloc_capable" property for the L3 cache resource on x86 (AMD)
systems that support SDCIAE.

Signed-off-by: Babu Moger <babu.moger@amd.com>
Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Link: https://patch.msgid.link/df85a9a6081674fd3ef6b4170920485512ce2ded.1762995456.git.babu.moger@amd.com

authored by

Babu Moger and committed by
Borislav Petkov (AMD) 7923ae76 4d4840b1

+10
+7
arch/x86/kernel/cpu/resctrl/core.c
··· 274 274 rdt_resources_all[level].r_resctrl.cdp_capable = true; 275 275 } 276 276 277 + static void rdt_set_io_alloc_capable(struct rdt_resource *r) 278 + { 279 + r->cache.io_alloc_capable = true; 280 + } 281 + 277 282 static void rdt_get_cdp_l3_config(void) 278 283 { 279 284 rdt_get_cdp_config(RDT_RESOURCE_L3); ··· 860 855 rdt_get_cache_alloc_cfg(1, r); 861 856 if (rdt_cpu_has(X86_FEATURE_CDP_L3)) 862 857 rdt_get_cdp_l3_config(); 858 + if (rdt_cpu_has(X86_FEATURE_SDCIAE)) 859 + rdt_set_io_alloc_capable(r); 863 860 ret = true; 864 861 } 865 862 if (rdt_cpu_has(X86_FEATURE_CAT_L2)) {
+3
include/linux/resctrl.h
··· 206 206 * @arch_has_sparse_bitmasks: True if a bitmask like f00f is valid. 207 207 * @arch_has_per_cpu_cfg: True if QOS_CFG register for this cache 208 208 * level has CPU scope. 209 + * @io_alloc_capable: True if portion of the cache can be configured 210 + * for I/O traffic. 209 211 */ 210 212 struct resctrl_cache { 211 213 unsigned int cbm_len; ··· 215 213 unsigned int shareable_bits; 216 214 bool arch_has_sparse_bitmasks; 217 215 bool arch_has_per_cpu_cfg; 216 + bool io_alloc_capable; 218 217 }; 219 218 220 219 /**