Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
gpu: nova-core: convert PFB registers to kernel register macro
Convert all PFB registers to use the kernel's register macro and update
the code accordingly.
NV_PGSP_QUEUE_HEAD was somehow caught in the PFB section, so move it to
its own section and convert it as well.
Reviewed-by: Eliot Courtney <ecourtney@nvidia.com>
Reviewed-by: Gary Guo <gary@garyguo.net>
Acked-by: Danilo Krummrich <dakr@kernel.org>
Link: https://patch.msgid.link/20260325-b4-nova-register-v4-4-bdf172f0f6ca@nvidia.com
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
+70
-50
+21
-13
drivers/gpu/nova-core/fb/hal/ga100.rs
+21
-13
drivers/gpu/nova-core/fb/hal/ga100.rs
···
1
1
// SPDX-License-Identifier: GPL-2.0
2
2
3
-
use kernel::prelude::*;
3
+
use kernel::{
4
+
io::Io,
5
+
num::Bounded,
6
+
prelude::*, //
7
+
};
4
8
5
9
use crate::{
6
10
driver::Bar0,
···
17
13
struct Ga100;
18
14
19
15
pub(super) fn read_sysmem_flush_page_ga100(bar: &Bar0) -> u64 {
20
-
u64::from(regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR::read(bar).adr_39_08()) << FLUSH_SYSMEM_ADDR_SHIFT
21
-
| u64::from(regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI::read(bar).adr_63_40())
16
+
u64::from(bar.read(regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR).adr_39_08()) << FLUSH_SYSMEM_ADDR_SHIFT
17
+
| u64::from(bar.read(regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI).adr_63_40())
22
18
<< FLUSH_SYSMEM_ADDR_SHIFT_HI
23
19
}
24
20
25
21
pub(super) fn write_sysmem_flush_page_ga100(bar: &Bar0, addr: u64) {
26
-
regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI::default()
27
-
// CAST: `as u32` is used on purpose since the remaining bits are guaranteed to fit within
28
-
// a `u32`.
29
-
.set_adr_63_40((addr >> FLUSH_SYSMEM_ADDR_SHIFT_HI) as u32)
30
-
.write(bar);
31
-
regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR::default()
32
-
// CAST: `as u32` is used on purpose since we want to strip the upper bits that have been
33
-
// written to `NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI`.
34
-
.set_adr_39_08((addr >> FLUSH_SYSMEM_ADDR_SHIFT) as u32)
35
-
.write(bar);
22
+
bar.write_reg(
23
+
regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI::zeroed().with_adr_63_40(
24
+
Bounded::<u64, _>::from(addr)
25
+
.shr::<FLUSH_SYSMEM_ADDR_SHIFT_HI, _>()
26
+
.cast(),
27
+
),
28
+
);
29
+
30
+
bar.write_reg(
31
+
regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR::zeroed()
32
+
// CAST: `as u32` is used on purpose since we want to strip the upper bits that have
33
+
// been written to `NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI`.
34
+
.with_adr_39_08((addr >> FLUSH_SYSMEM_ADDR_SHIFT) as u32),
35
+
);
36
36
}
37
37
38
38
pub(super) fn display_enabled_ga100(bar: &Bar0) -> bool {
+8
-6
drivers/gpu/nova-core/fb/hal/tu102.rs
+8
-6
drivers/gpu/nova-core/fb/hal/tu102.rs
···
1
1
// SPDX-License-Identifier: GPL-2.0
2
2
3
-
use kernel::prelude::*;
3
+
use kernel::{
4
+
io::Io,
5
+
prelude::*, //
6
+
};
4
7
5
8
use crate::{
6
9
driver::Bar0,
···
16
13
pub(super) const FLUSH_SYSMEM_ADDR_SHIFT: u32 = 8;
17
14
18
15
pub(super) fn read_sysmem_flush_page_gm107(bar: &Bar0) -> u64 {
19
-
u64::from(regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR::read(bar).adr_39_08()) << FLUSH_SYSMEM_ADDR_SHIFT
16
+
u64::from(bar.read(regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR).adr_39_08()) << FLUSH_SYSMEM_ADDR_SHIFT
20
17
}
21
18
22
19
pub(super) fn write_sysmem_flush_page_gm107(bar: &Bar0, addr: u64) -> Result {
···
24
21
u32::try_from(addr >> FLUSH_SYSMEM_ADDR_SHIFT)
25
22
.map_err(|_| EINVAL)
26
23
.map(|addr| {
27
-
regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR::default()
28
-
.set_adr_39_08(addr)
29
-
.write(bar)
24
+
bar.write_reg(regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR::zeroed().with_adr_39_08(addr))
30
25
})
31
26
}
32
27
···
33
32
}
34
33
35
34
pub(super) fn vidmem_size_gp102(bar: &Bar0) -> u64 {
36
-
regs::NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE::read(bar).usable_fb_size()
35
+
bar.read(regs::NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE)
36
+
.usable_fb_size()
37
37
}
38
38
39
39
struct Tu102;
+3
-3
drivers/gpu/nova-core/gsp/boot.rs
+3
-3
drivers/gpu/nova-core/gsp/boot.rs
···
57
57
) -> Result<()> {
58
58
// Check that the WPR2 region does not already exists - if it does, we cannot run
59
59
// FWSEC-FRTS until the GPU is reset.
60
-
if regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI::read(bar).higher_bound() != 0 {
60
+
if bar.read(regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI).higher_bound() != 0 {
61
61
dev_err!(
62
62
dev,
63
63
"WPR2 region already exists - GPU needs to be reset to proceed\n"
···
102
102
103
103
// Check that the WPR2 region has been created as we requested.
104
104
let (wpr2_lo, wpr2_hi) = (
105
-
regs::NV_PFB_PRI_MMU_WPR2_ADDR_LO::read(bar).lower_bound(),
106
-
regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI::read(bar).higher_bound(),
105
+
bar.read(regs::NV_PFB_PRI_MMU_WPR2_ADDR_LO).lower_bound(),
106
+
bar.read(regs::NV_PFB_PRI_MMU_WPR2_ADDR_HI).higher_bound(),
107
107
);
108
108
109
109
match (wpr2_lo, wpr2_hi) {
+5
-4
drivers/gpu/nova-core/gsp/cmdq.rs
+5
-4
drivers/gpu/nova-core/gsp/cmdq.rs
···
11
11
DmaAddress, //
12
12
},
13
13
dma_write,
14
-
io::poll::read_poll_timeout,
14
+
io::{
15
+
poll::read_poll_timeout,
16
+
Io, //
17
+
},
15
18
new_mutex,
16
19
prelude::*,
17
20
sync::{
···
512
509
513
510
/// Notifies the GSP that we have updated the command queue pointers.
514
511
fn notify_gsp(bar: &Bar0) {
515
-
regs::NV_PGSP_QUEUE_HEAD::default()
516
-
.set_address(0)
517
-
.write(bar);
512
+
bar.write_reg(regs::NV_PGSP_QUEUE_HEAD::zeroed().with_address(0u32));
518
513
}
519
514
520
515
/// Sends `command` to the GSP and waits for the reply.
+33
-24
drivers/gpu/nova-core/regs.rs
+33
-24
drivers/gpu/nova-core/regs.rs
···
120
120
121
121
// PFB
122
122
123
-
// The following two registers together hold the physical system memory address that is used by the
124
-
// GPU to perform sysmembar operations (see `fb::SysmemFlush`).
123
+
io::register! {
124
+
/// Low bits of the physical system memory address used by the GPU to perform sysmembar
125
+
/// operations (see [`crate::fb::SysmemFlush`]).
126
+
pub(crate) NV_PFB_NISO_FLUSH_SYSMEM_ADDR(u32) @ 0x00100c10 {
127
+
31:0 adr_39_08;
128
+
}
125
129
126
-
register!(NV_PFB_NISO_FLUSH_SYSMEM_ADDR @ 0x00100c10 {
127
-
31:0 adr_39_08 as u32;
128
-
});
130
+
/// High bits of the physical system memory address used by the GPU to perform sysmembar
131
+
/// operations (see [`crate::fb::SysmemFlush`]).
132
+
pub(crate) NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI(u32) @ 0x00100c40 {
133
+
23:0 adr_63_40;
134
+
}
129
135
130
-
register!(NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI @ 0x00100c40 {
131
-
23:0 adr_63_40 as u32;
132
-
});
136
+
pub(crate) NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE(u32) @ 0x00100ce0 {
137
+
30:30 ecc_mode_enabled => bool;
138
+
9:4 lower_mag;
139
+
3:0 lower_scale;
140
+
}
133
141
134
-
register!(NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE @ 0x00100ce0 {
135
-
3:0 lower_scale as u8;
136
-
9:4 lower_mag as u8;
137
-
30:30 ecc_mode_enabled as bool;
138
-
});
142
+
pub(crate) NV_PFB_PRI_MMU_WPR2_ADDR_LO(u32) @ 0x001fa824 {
143
+
/// Bits 12..40 of the lower (inclusive) bound of the WPR2 region.
144
+
31:4 lo_val;
145
+
}
139
146
140
-
register!(NV_PGSP_QUEUE_HEAD @ 0x00110c00 {
141
-
31:0 address as u32;
142
-
});
147
+
pub(crate) NV_PFB_PRI_MMU_WPR2_ADDR_HI(u32) @ 0x001fa828 {
148
+
/// Bits 12..40 of the higher (exclusive) bound of the WPR2 region.
149
+
31:4 hi_val;
150
+
}
151
+
}
143
152
144
153
impl NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE {
145
154
/// Returns the usable framebuffer size, in bytes.
···
165
156
}
166
157
}
167
158
168
-
register!(NV_PFB_PRI_MMU_WPR2_ADDR_LO@0x001fa824 {
169
-
31:4 lo_val as u32, "Bits 12..40 of the lower (inclusive) bound of the WPR2 region";
170
-
});
171
-
172
159
impl NV_PFB_PRI_MMU_WPR2_ADDR_LO {
173
160
/// Returns the lower (inclusive) bound of the WPR2 region.
174
161
pub(crate) fn lower_bound(self) -> u64 {
···
172
167
}
173
168
}
174
169
175
-
register!(NV_PFB_PRI_MMU_WPR2_ADDR_HI@0x001fa828 {
176
-
31:4 hi_val as u32, "Bits 12..40 of the higher (exclusive) bound of the WPR2 region";
177
-
});
178
-
179
170
impl NV_PFB_PRI_MMU_WPR2_ADDR_HI {
180
171
/// Returns the higher (exclusive) bound of the WPR2 region.
181
172
///
182
173
/// A value of zero means the WPR2 region is not set.
183
174
pub(crate) fn higher_bound(self) -> u64 {
184
175
u64::from(self.hi_val()) << 12
176
+
}
177
+
}
178
+
179
+
// PGSP
180
+
181
+
io::register! {
182
+
pub(crate) NV_PGSP_QUEUE_HEAD(u32) @ 0x00110c00 {
183
+
31:0 address;
185
184
}
186
185
}
187
186