Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
mmc: dw_mmc: add exynos7870 DW MMC support
Add support for Exynos7870 DW MMC controllers, for both SMU and non-SMU
variants. These controllers require a quirk to access 64-bit FIFO in 32-bit
accesses (DW_MMC_QUIRK_FIFO64_32).
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org>
Link: https://lore.kernel.org/r/20250219-exynos7870-mmc-v2-3-b4255a3e39ed@disroot.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
authored by
Kaustabh Chakraborty
and committed by
Ulf Hansson
7cbe799a
57c0902f
+40
-1
+40
-1
drivers/mmc/host/dw_mmc-exynos.c
+40
-1
drivers/mmc/host/dw_mmc-exynos.c
···
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DW_MCI_TYPE_EXYNOS5420_SMU,
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DW_MCI_TYPE_EXYNOS7,
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DW_MCI_TYPE_EXYNOS7_SMU,
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+
DW_MCI_TYPE_EXYNOS7870,
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+
DW_MCI_TYPE_EXYNOS7870_SMU,
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DW_MCI_TYPE_ARTPEC8,
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};
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···
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.compatible = "samsung,exynos7-dw-mshc-smu",
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.ctrl_type = DW_MCI_TYPE_EXYNOS7_SMU,
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}, {
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.compatible = "samsung,exynos7870-dw-mshc",
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+
.ctrl_type = DW_MCI_TYPE_EXYNOS7870,
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+
}, {
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+
.compatible = "samsung,exynos7870-dw-mshc-smu",
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+
.ctrl_type = DW_MCI_TYPE_EXYNOS7870_SMU,
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+
}, {
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.compatible = "axis,artpec8-dw-mshc",
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.ctrl_type = DW_MCI_TYPE_ARTPEC8,
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},
···
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return EXYNOS4210_FIXED_CIU_CLK_DIV;
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else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
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+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870 ||
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+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU ||
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priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
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return SDMMC_CLKSEL_GET_DIV(mci_readl(host, CLKSEL64)) + 1;
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else
···
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* set for non-ecryption mode at this time.
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*/
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS5420_SMU ||
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-
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) {
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+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
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+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU) {
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mci_writel(host, MPSBEGIN0, 0);
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mci_writel(host, MPSEND0, SDMMC_ENDING_SEC_NR_MAX);
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mci_writel(host, MPSCTRL0, SDMMC_MPSCTRL_SECURE_WRITE_BIT |
···
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DQS_CTRL_GET_RD_DELAY(priv->saved_strobe_ctrl);
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}
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+
if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870 ||
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+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU) {
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/* Quirk needed for certain Exynos SoCs */
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host->quirks |= DW_MMC_QUIRK_FIFO64_32;
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+
}
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+
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if (priv->ctrl_type == DW_MCI_TYPE_ARTPEC8) {
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/* Quirk needed for the ARTPEC-8 SoC */
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host->quirks |= DW_MMC_QUIRK_EXTENDED_TMOUT;
···
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
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+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870 ||
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+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU ||
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priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
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clksel = mci_readl(host, CLKSEL64);
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else
···
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
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+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870 ||
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+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU ||
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priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
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mci_writel(host, CLKSEL64, clksel);
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else
···
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
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+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870 ||
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+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU ||
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priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
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clksel = mci_readl(host, CLKSEL64);
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else
···
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if (clksel & SDMMC_CLKSEL_WAKEUP_INT) {
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
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+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870 ||
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+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU ||
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priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
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mci_writel(host, CLKSEL64, clksel);
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else
···
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
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+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870 ||
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+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU ||
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priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
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return SDMMC_CLKSEL_CCLK_SAMPLE(mci_readl(host, CLKSEL64));
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else
···
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
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+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870 ||
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+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU ||
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priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
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clksel = mci_readl(host, CLKSEL64);
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else
···
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clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample);
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
460
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
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+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870 ||
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+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU ||
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priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
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mci_writel(host, CLKSEL64, clksel);
463
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else
···
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
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+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870 ||
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+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU ||
477
448
priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
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clksel = mci_readl(host, CLKSEL64);
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else
···
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453
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if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
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priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
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+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870 ||
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+
priv->ctrl_type == DW_MCI_TYPE_EXYNOS7870_SMU ||
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priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
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mci_writel(host, CLKSEL64, clksel);
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else
···
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{ .compatible = "samsung,exynos7-dw-mshc",
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.data = &exynos_drv_data, },
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{ .compatible = "samsung,exynos7-dw-mshc-smu",
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+
.data = &exynos_drv_data, },
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+
{ .compatible = "samsung,exynos7870-dw-mshc",
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+
.data = &exynos_drv_data, },
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+
{ .compatible = "samsung,exynos7870-dw-mshc-smu",
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.data = &exynos_drv_data, },
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{ .compatible = "axis,artpec8-dw-mshc",
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.data = &artpec_drv_data, },