Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'rmobile-fixes-for-linus' of git://github.com/pmundt/linux-sh
* 'rmobile-fixes-for-linus' of git://github.com/pmundt/linux-sh:
ARM: mach-shmobile: cpuidle single/global and last_state fixes
ARM: mach-shmobile: move helper macro PORTCR to sh_pfc.h
ARM: mach-shmobile: move helper macro PORT_xx to sh_pfc.h
ARM: mach-shmobile: move helper macro PORT_DATA_xx to sh_pfc.h
ARM: mach-shmobile: ap4evb: remove white space from end of line
ARM: mach-shmobile: clock-sh7372: remove un-necessary index
ARM: mach-shmobile: kota2: add comment out separator
ARM: mach-shmobile: sh73a0: add MMC data pin pull-up
+381
-504
+8
-8
arch/arm/mach-shmobile/board-ag5evm.c
+8
-8
arch/arm/mach-shmobile/board-ag5evm.c
···
515
515
/* enable MMCIF */
516
516
gpio_request(GPIO_FN_MMCCLK0, NULL);
517
517
gpio_request(GPIO_FN_MMCCMD0_PU, NULL);
518
-
gpio_request(GPIO_FN_MMCD0_0, NULL);
519
-
gpio_request(GPIO_FN_MMCD0_1, NULL);
520
-
gpio_request(GPIO_FN_MMCD0_2, NULL);
521
-
gpio_request(GPIO_FN_MMCD0_3, NULL);
522
-
gpio_request(GPIO_FN_MMCD0_4, NULL);
523
-
gpio_request(GPIO_FN_MMCD0_5, NULL);
524
-
gpio_request(GPIO_FN_MMCD0_6, NULL);
525
-
gpio_request(GPIO_FN_MMCD0_7, NULL);
518
+
gpio_request(GPIO_FN_MMCD0_0_PU, NULL);
519
+
gpio_request(GPIO_FN_MMCD0_1_PU, NULL);
520
+
gpio_request(GPIO_FN_MMCD0_2_PU, NULL);
521
+
gpio_request(GPIO_FN_MMCD0_3_PU, NULL);
522
+
gpio_request(GPIO_FN_MMCD0_4_PU, NULL);
523
+
gpio_request(GPIO_FN_MMCD0_5_PU, NULL);
524
+
gpio_request(GPIO_FN_MMCD0_6_PU, NULL);
525
+
gpio_request(GPIO_FN_MMCD0_7_PU, NULL);
526
526
gpio_request(GPIO_PORT208, NULL); /* Reset */
527
527
gpio_direction_output(GPIO_PORT208, 1);
528
528
+1
-1
arch/arm/mach-shmobile/board-ap4evb.c
+1
-1
arch/arm/mach-shmobile/board-ap4evb.c
···
201
201
static struct resource nor_flash_resources[] = {
202
202
[0] = {
203
203
.start = 0x20000000, /* CS0 shadow instead of regular CS0 */
204
-
.end = 0x28000000 - 1, /* needed by USB MASK ROM boot */
204
+
.end = 0x28000000 - 1, /* needed by USB MASK ROM boot */
205
205
.flags = IORESOURCE_MEM,
206
206
}
207
207
};
+7
arch/arm/mach-shmobile/board-kota2.c
+7
arch/arm/mach-shmobile/board-kota2.c
···
48
48
#include <asm/hardware/cache-l2x0.h>
49
49
#include <asm/traps.h>
50
50
51
+
/* SMSC 9220 */
51
52
static struct resource smsc9220_resources[] = {
52
53
[0] = {
53
54
.start = 0x14000000, /* CS5A */
···
78
77
.num_resources = ARRAY_SIZE(smsc9220_resources),
79
78
};
80
79
80
+
/* KEYSC */
81
81
static struct sh_keysc_info keysc_platdata = {
82
82
.mode = SH_KEYSC_MODE_6,
83
83
.scan_timing = 3,
···
122
120
},
123
121
};
124
122
123
+
/* GPIO KEY */
125
124
#define GPIO_KEY(c, g, d) { .code = c, .gpio = g, .desc = d, .active_low = 1 }
126
125
127
126
static struct gpio_keys_button gpio_buttons[] = {
···
153
150
},
154
151
};
155
152
153
+
/* GPIO LED */
156
154
#define GPIO_LED(n, g) { .name = n, .gpio = g }
157
155
158
156
static struct gpio_led gpio_leds[] = {
···
179
175
},
180
176
};
181
177
178
+
/* MMCIF */
182
179
static struct resource mmcif_resources[] = {
183
180
[0] = {
184
181
.name = "MMCIF",
···
212
207
.resource = mmcif_resources,
213
208
};
214
209
210
+
/* SDHI0 */
215
211
static struct sh_mobile_sdhi_info sdhi0_info = {
216
212
.tmio_caps = MMC_CAP_SD_HIGHSPEED,
217
213
.tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_HAS_IDLE_WAIT,
···
249
243
},
250
244
};
251
245
246
+
/* SDHI1 */
252
247
static struct sh_mobile_sdhi_info sdhi1_info = {
253
248
.tmio_caps = MMC_CAP_NONREMOVABLE | MMC_CAP_SDIO_IRQ,
254
249
.tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_HAS_IDLE_WAIT,
+4
-4
arch/arm/mach-shmobile/clock-sh7372.c
+4
-4
arch/arm/mach-shmobile/clock-sh7372.c
···
476
476
.disable = fsidiv_disable,
477
477
};
478
478
479
-
static struct clk_mapping sh7372_fsidiva_clk_mapping = {
479
+
static struct clk_mapping fsidiva_clk_mapping = {
480
480
.phys = FSIDIVA,
481
481
.len = 8,
482
482
};
···
484
484
struct clk sh7372_fsidiva_clk = {
485
485
.ops = &fsidiv_clk_ops,
486
486
.parent = &div6_reparent_clks[DIV6_FSIA], /* late install */
487
-
.mapping = &sh7372_fsidiva_clk_mapping,
487
+
.mapping = &fsidiva_clk_mapping,
488
488
};
489
489
490
-
static struct clk_mapping sh7372_fsidivb_clk_mapping = {
490
+
static struct clk_mapping fsidivb_clk_mapping = {
491
491
.phys = FSIDIVB,
492
492
.len = 8,
493
493
};
···
495
495
struct clk sh7372_fsidivb_clk = {
496
496
.ops = &fsidiv_clk_ops,
497
497
.parent = &div6_reparent_clks[DIV6_FSIB], /* late install */
498
-
.mapping = &sh7372_fsidivb_clk_mapping,
498
+
.mapping = &fsidivb_clk_mapping,
499
499
};
500
500
501
501
static struct clk *late_main_clks[] = {
+23
-29
arch/arm/mach-shmobile/cpuidle.c
+23
-29
arch/arm/mach-shmobile/cpuidle.c
···
26
26
};
27
27
28
28
static int shmobile_cpuidle_enter(struct cpuidle_device *dev,
29
-
struct cpuidle_state *state)
29
+
struct cpuidle_driver *drv,
30
+
int index)
30
31
{
31
32
ktime_t before, after;
32
-
int requested_state = state - &dev->states[0];
33
33
34
-
dev->last_state = &dev->states[requested_state];
35
34
before = ktime_get();
36
35
37
36
local_irq_disable();
38
37
local_fiq_disable();
39
38
40
-
shmobile_cpuidle_modes[requested_state]();
39
+
shmobile_cpuidle_modes[index]();
41
40
42
41
local_irq_enable();
43
42
local_fiq_enable();
44
43
45
44
after = ktime_get();
46
-
return ktime_to_ns(ktime_sub(after, before)) >> 10;
45
+
dev->last_residency = ktime_to_ns(ktime_sub(after, before)) >> 10;
46
+
47
+
return index;
47
48
}
48
49
49
50
static struct cpuidle_device shmobile_cpuidle_dev;
50
51
static struct cpuidle_driver shmobile_cpuidle_driver = {
51
52
.name = "shmobile_cpuidle",
52
53
.owner = THIS_MODULE,
54
+
.states[0] = {
55
+
.name = "C1",
56
+
.desc = "WFI",
57
+
.exit_latency = 1,
58
+
.target_residency = 1 * 2,
59
+
.flags = CPUIDLE_FLAG_TIME_VALID,
60
+
},
61
+
.safe_state_index = 0, /* C1 */
62
+
.state_count = 1,
53
63
};
54
64
55
-
void (*shmobile_cpuidle_setup)(struct cpuidle_device *dev);
65
+
void (*shmobile_cpuidle_setup)(struct cpuidle_driver *drv);
56
66
57
67
static int shmobile_cpuidle_init(void)
58
68
{
59
69
struct cpuidle_device *dev = &shmobile_cpuidle_dev;
60
-
struct cpuidle_state *state;
70
+
struct cpuidle_driver *drv = &shmobile_cpuidle_driver;
61
71
int i;
62
72
63
-
cpuidle_register_driver(&shmobile_cpuidle_driver);
64
-
65
-
for (i = 0; i < CPUIDLE_STATE_MAX; i++) {
66
-
dev->states[i].name[0] = '\0';
67
-
dev->states[i].desc[0] = '\0';
68
-
dev->states[i].enter = shmobile_cpuidle_enter;
69
-
}
70
-
71
-
i = CPUIDLE_DRIVER_STATE_START;
72
-
73
-
state = &dev->states[i++];
74
-
snprintf(state->name, CPUIDLE_NAME_LEN, "C1");
75
-
strncpy(state->desc, "WFI", CPUIDLE_DESC_LEN);
76
-
state->exit_latency = 1;
77
-
state->target_residency = 1 * 2;
78
-
state->power_usage = 3;
79
-
state->flags = 0;
80
-
state->flags |= CPUIDLE_FLAG_TIME_VALID;
81
-
82
-
dev->safe_state = state;
83
-
dev->state_count = i;
73
+
for (i = 0; i < CPUIDLE_STATE_MAX; i++)
74
+
drv->states[i].enter = shmobile_cpuidle_enter;
84
75
85
76
if (shmobile_cpuidle_setup)
86
-
shmobile_cpuidle_setup(dev);
77
+
shmobile_cpuidle_setup(drv);
87
78
79
+
cpuidle_register_driver(drv);
80
+
81
+
dev->state_count = drv->state_count;
88
82
cpuidle_register_device(dev);
89
83
90
84
return 0;
+2
-2
arch/arm/mach-shmobile/include/mach/common.h
+2
-2
arch/arm/mach-shmobile/include/mach/common.h
···
9
9
extern void shmobile_handle_irq_intc(struct pt_regs *);
10
10
extern void shmobile_handle_irq_gic(struct pt_regs *);
11
11
extern struct platform_suspend_ops shmobile_suspend_ops;
12
-
struct cpuidle_device;
12
+
struct cpuidle_driver;
13
13
extern void (*shmobile_cpuidle_modes[])(void);
14
-
extern void (*shmobile_cpuidle_setup)(struct cpuidle_device *dev);
14
+
extern void (*shmobile_cpuidle_setup)(struct cpuidle_driver *drv);
15
15
16
16
extern void sh7367_init_irq(void);
17
17
extern void sh7367_add_early_devices(void);
+8
arch/arm/mach-shmobile/include/mach/sh73a0.h
+8
arch/arm/mach-shmobile/include/mach/sh73a0.h
···
470
470
GPIO_FN_SDHICMD2_PU,
471
471
GPIO_FN_MMCCMD0_PU,
472
472
GPIO_FN_MMCCMD1_PU,
473
+
GPIO_FN_MMCD0_0_PU,
474
+
GPIO_FN_MMCD0_1_PU,
475
+
GPIO_FN_MMCD0_2_PU,
476
+
GPIO_FN_MMCD0_3_PU,
477
+
GPIO_FN_MMCD0_4_PU,
478
+
GPIO_FN_MMCD0_5_PU,
479
+
GPIO_FN_MMCD0_6_PU,
480
+
GPIO_FN_MMCD0_7_PU,
473
481
GPIO_FN_FSIACK_PU,
474
482
GPIO_FN_FSIAILR_PU,
475
483
GPIO_FN_FSIAIBT_PU,
+24
-98
arch/arm/mach-shmobile/pfc-sh7367.c
+24
-98
arch/arm/mach-shmobile/pfc-sh7367.c
···
21
21
#include <linux/gpio.h>
22
22
#include <mach/sh7367.h>
23
23
24
-
#define _1(fn, pfx, sfx) fn(pfx, sfx)
25
-
26
-
#define _10(fn, pfx, sfx) \
27
-
_1(fn, pfx##0, sfx), _1(fn, pfx##1, sfx), \
28
-
_1(fn, pfx##2, sfx), _1(fn, pfx##3, sfx), \
29
-
_1(fn, pfx##4, sfx), _1(fn, pfx##5, sfx), \
30
-
_1(fn, pfx##6, sfx), _1(fn, pfx##7, sfx), \
31
-
_1(fn, pfx##8, sfx), _1(fn, pfx##9, sfx)
32
-
33
-
#define _90(fn, pfx, sfx) \
34
-
_10(fn, pfx##1, sfx), _10(fn, pfx##2, sfx), \
35
-
_10(fn, pfx##3, sfx), _10(fn, pfx##4, sfx), \
36
-
_10(fn, pfx##5, sfx), _10(fn, pfx##6, sfx), \
37
-
_10(fn, pfx##7, sfx), _10(fn, pfx##8, sfx), \
38
-
_10(fn, pfx##9, sfx)
39
-
40
-
#define _273(fn, pfx, sfx) \
41
-
_10(fn, pfx, sfx), _90(fn, pfx, sfx), \
42
-
_10(fn, pfx##10, sfx), _90(fn, pfx##1, sfx), \
43
-
_10(fn, pfx##20, sfx), _10(fn, pfx##21, sfx), \
44
-
_10(fn, pfx##22, sfx), _10(fn, pfx##23, sfx), \
45
-
_10(fn, pfx##24, sfx), _10(fn, pfx##25, sfx), \
46
-
_10(fn, pfx##26, sfx), _1(fn, pfx##270, sfx), \
47
-
_1(fn, pfx##271, sfx), _1(fn, pfx##272, sfx)
48
-
49
-
#define _PORT(pfx, sfx) pfx##_##sfx
50
-
#define PORT_273(str) _273(_PORT, PORT, str)
24
+
#define CPU_ALL_PORT(fn, pfx, sfx) \
25
+
PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \
26
+
PORT_10(fn, pfx##10, sfx), PORT_90(fn, pfx##1, sfx), \
27
+
PORT_10(fn, pfx##20, sfx), PORT_10(fn, pfx##21, sfx), \
28
+
PORT_10(fn, pfx##22, sfx), PORT_10(fn, pfx##23, sfx), \
29
+
PORT_10(fn, pfx##24, sfx), PORT_10(fn, pfx##25, sfx), \
30
+
PORT_10(fn, pfx##26, sfx), PORT_1(fn, pfx##270, sfx), \
31
+
PORT_1(fn, pfx##271, sfx), PORT_1(fn, pfx##272, sfx)
51
32
52
33
enum {
53
34
PINMUX_RESERVED = 0,
54
35
55
36
PINMUX_DATA_BEGIN,
56
-
PORT_273(DATA), /* PORT0_DATA -> PORT272_DATA */
37
+
PORT_ALL(DATA), /* PORT0_DATA -> PORT272_DATA */
57
38
PINMUX_DATA_END,
58
39
59
40
PINMUX_INPUT_BEGIN,
60
-
PORT_273(IN), /* PORT0_IN -> PORT272_IN */
41
+
PORT_ALL(IN), /* PORT0_IN -> PORT272_IN */
61
42
PINMUX_INPUT_END,
62
43
63
44
PINMUX_INPUT_PULLUP_BEGIN,
64
-
PORT_273(IN_PU), /* PORT0_IN_PU -> PORT272_IN_PU */
45
+
PORT_ALL(IN_PU), /* PORT0_IN_PU -> PORT272_IN_PU */
65
46
PINMUX_INPUT_PULLUP_END,
66
47
67
48
PINMUX_INPUT_PULLDOWN_BEGIN,
68
-
PORT_273(IN_PD), /* PORT0_IN_PD -> PORT272_IN_PD */
49
+
PORT_ALL(IN_PD), /* PORT0_IN_PD -> PORT272_IN_PD */
69
50
PINMUX_INPUT_PULLDOWN_END,
70
51
71
52
PINMUX_OUTPUT_BEGIN,
72
-
PORT_273(OUT), /* PORT0_OUT -> PORT272_OUT */
53
+
PORT_ALL(OUT), /* PORT0_OUT -> PORT272_OUT */
73
54
PINMUX_OUTPUT_END,
74
55
75
56
PINMUX_FUNCTION_BEGIN,
76
-
PORT_273(FN_IN), /* PORT0_FN_IN -> PORT272_FN_IN */
77
-
PORT_273(FN_OUT), /* PORT0_FN_OUT -> PORT272_FN_OUT */
78
-
PORT_273(FN0), /* PORT0_FN0 -> PORT272_FN0 */
79
-
PORT_273(FN1), /* PORT0_FN1 -> PORT272_FN1 */
80
-
PORT_273(FN2), /* PORT0_FN2 -> PORT272_FN2 */
81
-
PORT_273(FN3), /* PORT0_FN3 -> PORT272_FN3 */
82
-
PORT_273(FN4), /* PORT0_FN4 -> PORT272_FN4 */
83
-
PORT_273(FN5), /* PORT0_FN5 -> PORT272_FN5 */
84
-
PORT_273(FN6), /* PORT0_FN6 -> PORT272_FN6 */
85
-
PORT_273(FN7), /* PORT0_FN7 -> PORT272_FN7 */
57
+
PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT272_FN_IN */
58
+
PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT272_FN_OUT */
59
+
PORT_ALL(FN0), /* PORT0_FN0 -> PORT272_FN0 */
60
+
PORT_ALL(FN1), /* PORT0_FN1 -> PORT272_FN1 */
61
+
PORT_ALL(FN2), /* PORT0_FN2 -> PORT272_FN2 */
62
+
PORT_ALL(FN3), /* PORT0_FN3 -> PORT272_FN3 */
63
+
PORT_ALL(FN4), /* PORT0_FN4 -> PORT272_FN4 */
64
+
PORT_ALL(FN5), /* PORT0_FN5 -> PORT272_FN5 */
65
+
PORT_ALL(FN6), /* PORT0_FN6 -> PORT272_FN6 */
66
+
PORT_ALL(FN7), /* PORT0_FN7 -> PORT272_FN7 */
86
67
87
68
MSELBCR_MSEL2_1, MSELBCR_MSEL2_0,
88
69
PINMUX_FUNCTION_END,
···
307
326
DIVLOCK_MARK,
308
327
PINMUX_MARK_END,
309
328
};
310
-
311
-
#define PORT_DATA_I(nr) \
312
-
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN)
313
-
314
-
#define PORT_DATA_I_PD(nr) \
315
-
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
316
-
PORT##nr##_IN, PORT##nr##_IN_PD)
317
-
318
-
#define PORT_DATA_I_PU(nr) \
319
-
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
320
-
PORT##nr##_IN, PORT##nr##_IN_PU)
321
-
322
-
#define PORT_DATA_I_PU_PD(nr) \
323
-
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
324
-
PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)
325
-
326
-
#define PORT_DATA_O(nr) \
327
-
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT)
328
-
329
-
#define PORT_DATA_IO(nr) \
330
-
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
331
-
PORT##nr##_IN)
332
-
333
-
#define PORT_DATA_IO_PD(nr) \
334
-
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
335
-
PORT##nr##_IN, PORT##nr##_IN_PD)
336
-
337
-
#define PORT_DATA_IO_PU(nr) \
338
-
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
339
-
PORT##nr##_IN, PORT##nr##_IN_PU)
340
-
341
-
#define PORT_DATA_IO_PU_PD(nr) \
342
-
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
343
-
PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)
344
-
345
329
346
330
static pinmux_enum_t pinmux_data[] = {
347
331
···
1044
1098
PINMUX_DATA(DIVLOCK_MARK, PORT272_FN1),
1045
1099
};
1046
1100
1047
-
#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA)
1048
-
#define GPIO_PORT_273() _273(_GPIO_PORT, , unused)
1049
-
#define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK)
1050
-
1051
1101
static struct pinmux_gpio pinmux_gpios[] = {
1052
1102
/* 49-1 -> 49-6 (GPIO) */
1053
-
GPIO_PORT_273(),
1103
+
GPIO_PORT_ALL(),
1054
1104
1055
1105
/* Special Pull-up / Pull-down Functions */
1056
1106
GPIO_FN(PORT48_KEYIN0_PU), GPIO_FN(PORT49_KEYIN1_PU),
···
1286
1344
GPIO_FN(RESETOUTS),
1287
1345
GPIO_FN(DIVLOCK),
1288
1346
};
1289
-
1290
-
/* helper for top 4 bits in PORTnCR */
1291
-
#define PCRH(in, in_pd, in_pu, out) \
1292
-
0, (out), (in), 0, \
1293
-
0, 0, 0, 0, \
1294
-
0, 0, (in_pd), 0, \
1295
-
0, 0, (in_pu), 0
1296
-
1297
-
#define PORTCR(nr, reg) \
1298
-
{ PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
1299
-
PCRH(PORT##nr##_IN, PORT##nr##_IN_PD, \
1300
-
PORT##nr##_IN_PU, PORT##nr##_OUT), \
1301
-
PORT##nr##_FN0, PORT##nr##_FN1, PORT##nr##_FN2, \
1302
-
PORT##nr##_FN3, PORT##nr##_FN4, PORT##nr##_FN5, \
1303
-
PORT##nr##_FN6, PORT##nr##_FN7 } \
1304
-
}
1305
1347
1306
1348
static struct pinmux_cfg_reg pinmux_config_regs[] = {
1307
1349
PORTCR(0, 0xe6050000), /* PORT0CR */
+103
-121
arch/arm/mach-shmobile/pfc-sh7372.c
+103
-121
arch/arm/mach-shmobile/pfc-sh7372.c
···
25
25
#include <linux/gpio.h>
26
26
#include <mach/sh7372.h>
27
27
28
-
#define _1(fn, pfx, sfx) fn(pfx, sfx)
29
-
30
-
#define _10(fn, pfx, sfx) \
31
-
_1(fn, pfx##0, sfx), _1(fn, pfx##1, sfx), \
32
-
_1(fn, pfx##2, sfx), _1(fn, pfx##3, sfx), \
33
-
_1(fn, pfx##4, sfx), _1(fn, pfx##5, sfx), \
34
-
_1(fn, pfx##6, sfx), _1(fn, pfx##7, sfx), \
35
-
_1(fn, pfx##8, sfx), _1(fn, pfx##9, sfx)
36
-
37
-
#define _80(fn, pfx, sfx) \
38
-
_10(fn, pfx##1, sfx), _10(fn, pfx##2, sfx), \
39
-
_10(fn, pfx##3, sfx), _10(fn, pfx##4, sfx), \
40
-
_10(fn, pfx##5, sfx), _10(fn, pfx##6, sfx), \
41
-
_10(fn, pfx##7, sfx), _10(fn, pfx##8, sfx)
42
-
43
-
#define _190(fn, pfx, sfx) \
44
-
_10(fn, pfx, sfx), _80(fn, pfx, sfx), _10(fn, pfx##9, sfx), \
45
-
_10(fn, pfx##10, sfx), _80(fn, pfx##1, sfx), _1(fn, pfx##190, sfx)
46
-
47
-
#define _PORT(pfx, sfx) pfx##_##sfx
48
-
#define PORT_ALL(str) _190(_PORT, PORT, str)
28
+
#define CPU_ALL_PORT(fn, pfx, sfx) \
29
+
PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \
30
+
PORT_10(fn, pfx##10, sfx), PORT_10(fn, pfx##11, sfx), \
31
+
PORT_10(fn, pfx##12, sfx), PORT_10(fn, pfx##13, sfx), \
32
+
PORT_10(fn, pfx##14, sfx), PORT_10(fn, pfx##15, sfx), \
33
+
PORT_10(fn, pfx##16, sfx), PORT_10(fn, pfx##17, sfx), \
34
+
PORT_10(fn, pfx##18, sfx), PORT_1(fn, pfx##190, sfx)
49
35
50
36
enum {
51
37
PINMUX_RESERVED = 0,
···
367
381
PINMUX_MARK_END,
368
382
};
369
383
370
-
/* PORT_DATA_I_PD(nr) */
371
-
#define _I___D(nr) \
372
-
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
373
-
PORT##nr##_IN, PORT##nr##_IN_PD)
374
-
375
-
/* PORT_DATA_I_PU(nr) */
376
-
#define _I__U_(nr) \
377
-
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
378
-
PORT##nr##_IN, PORT##nr##_IN_PU)
379
-
380
-
/* PORT_DATA_I_PU_PD(nr) */
381
-
#define _I__UD(nr) \
382
-
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
383
-
PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)
384
-
385
-
/* PORT_DATA_O(nr) */
386
-
#define __O___(nr) \
387
-
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT)
388
-
389
-
/* PORT_DATA_IO(nr) */
390
-
#define _IO___(nr) \
391
-
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
392
-
PORT##nr##_IN)
393
-
394
-
/* PORT_DATA_IO_PD(nr) */
395
-
#define _IO__D(nr) \
396
-
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
397
-
PORT##nr##_IN, PORT##nr##_IN_PD)
398
-
399
-
/* PORT_DATA_IO_PU(nr) */
400
-
#define _IO_U_(nr) \
401
-
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
402
-
PORT##nr##_IN, PORT##nr##_IN_PU)
403
-
404
-
/* PORT_DATA_IO_PU_PD(nr) */
405
-
#define _IO_UD(nr) \
406
-
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
407
-
PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)
408
-
409
-
410
384
static pinmux_enum_t pinmux_data[] = {
411
385
412
386
/* specify valid pin states for each pin in GPIO mode */
387
+
PORT_DATA_IO_PD(0), PORT_DATA_IO_PD(1),
388
+
PORT_DATA_O(2), PORT_DATA_I_PD(3),
389
+
PORT_DATA_I_PD(4), PORT_DATA_I_PD(5),
390
+
PORT_DATA_IO_PU_PD(6), PORT_DATA_I_PD(7),
391
+
PORT_DATA_IO_PD(8), PORT_DATA_O(9),
413
392
414
-
_IO__D(0), _IO__D(1), __O___(2), _I___D(3), _I___D(4),
415
-
_I___D(5), _IO_UD(6), _I___D(7), _IO__D(8), __O___(9),
393
+
PORT_DATA_O(10), PORT_DATA_O(11),
394
+
PORT_DATA_IO_PU_PD(12), PORT_DATA_IO_PD(13),
395
+
PORT_DATA_IO_PD(14), PORT_DATA_O(15),
396
+
PORT_DATA_IO_PD(16), PORT_DATA_IO_PD(17),
397
+
PORT_DATA_I_PD(18), PORT_DATA_IO(19),
416
398
417
-
__O___(10), __O___(11), _IO_UD(12), _IO__D(13), _IO__D(14),
418
-
__O___(15), _IO__D(16), _IO__D(17), _I___D(18), _IO___(19),
399
+
PORT_DATA_IO(20), PORT_DATA_IO(21),
400
+
PORT_DATA_IO(22), PORT_DATA_IO(23),
401
+
PORT_DATA_IO(24), PORT_DATA_IO(25),
402
+
PORT_DATA_IO(26), PORT_DATA_IO(27),
403
+
PORT_DATA_IO(28), PORT_DATA_IO(29),
419
404
420
-
_IO___(20), _IO___(21), _IO___(22), _IO___(23), _IO___(24),
421
-
_IO___(25), _IO___(26), _IO___(27), _IO___(28), _IO___(29),
405
+
PORT_DATA_IO(30), PORT_DATA_IO(31),
406
+
PORT_DATA_IO(32), PORT_DATA_IO(33),
407
+
PORT_DATA_IO(34), PORT_DATA_IO(35),
408
+
PORT_DATA_IO(36), PORT_DATA_IO(37),
409
+
PORT_DATA_IO(38), PORT_DATA_IO(39),
422
410
423
-
_IO___(30), _IO___(31), _IO___(32), _IO___(33), _IO___(34),
424
-
_IO___(35), _IO___(36), _IO___(37), _IO___(38), _IO___(39),
411
+
PORT_DATA_IO(40), PORT_DATA_IO(41),
412
+
PORT_DATA_IO(42), PORT_DATA_IO(43),
413
+
PORT_DATA_IO(44), PORT_DATA_IO(45),
414
+
PORT_DATA_IO_PU(46), PORT_DATA_IO_PU(47),
415
+
PORT_DATA_IO_PU(48), PORT_DATA_IO_PU(49),
425
416
426
-
_IO___(40), _IO___(41), _IO___(42), _IO___(43), _IO___(44),
427
-
_IO___(45), _IO_U_(46), _IO_U_(47), _IO_U_(48), _IO_U_(49),
417
+
PORT_DATA_IO_PU(50), PORT_DATA_IO_PU(51),
418
+
PORT_DATA_IO_PU(52), PORT_DATA_IO_PU(53),
419
+
PORT_DATA_IO_PU(54), PORT_DATA_IO_PU(55),
420
+
PORT_DATA_IO_PU(56), PORT_DATA_IO_PU(57),
421
+
PORT_DATA_IO_PU(58), PORT_DATA_IO_PU(59),
428
422
429
-
_IO_U_(50), _IO_U_(51), _IO_U_(52), _IO_U_(53), _IO_U_(54),
430
-
_IO_U_(55), _IO_U_(56), _IO_U_(57), _IO_U_(58), _IO_U_(59),
423
+
PORT_DATA_IO_PU(60), PORT_DATA_IO_PU(61),
424
+
PORT_DATA_IO(62), PORT_DATA_O(63),
425
+
PORT_DATA_O(64), PORT_DATA_IO_PU(65),
426
+
PORT_DATA_O(66), PORT_DATA_IO_PU(67), /*66?*/
427
+
PORT_DATA_O(68), PORT_DATA_IO(69),
431
428
432
-
_IO_U_(60), _IO_U_(61), _IO___(62), __O___(63), __O___(64),
433
-
_IO_U_(65), __O___(66), _IO_U_(67), __O___(68), _IO___(69), /*66?*/
429
+
PORT_DATA_IO(70), PORT_DATA_IO(71),
430
+
PORT_DATA_O(72), PORT_DATA_I_PU(73),
431
+
PORT_DATA_I_PU_PD(74), PORT_DATA_IO_PU_PD(75),
432
+
PORT_DATA_IO_PU_PD(76), PORT_DATA_IO_PU_PD(77),
433
+
PORT_DATA_IO_PU_PD(78), PORT_DATA_IO_PU_PD(79),
434
434
435
-
_IO___(70), _IO___(71), __O___(72), _I__U_(73), _I__UD(74),
436
-
_IO_UD(75), _IO_UD(76), _IO_UD(77), _IO_UD(78), _IO_UD(79),
435
+
PORT_DATA_IO_PU_PD(80), PORT_DATA_IO_PU_PD(81),
436
+
PORT_DATA_IO_PU_PD(82), PORT_DATA_IO_PU_PD(83),
437
+
PORT_DATA_IO_PU_PD(84), PORT_DATA_IO_PU_PD(85),
438
+
PORT_DATA_IO_PU_PD(86), PORT_DATA_IO_PU_PD(87),
439
+
PORT_DATA_IO_PU_PD(88), PORT_DATA_IO_PU_PD(89),
437
440
438
-
_IO_UD(80), _IO_UD(81), _IO_UD(82), _IO_UD(83), _IO_UD(84),
439
-
_IO_UD(85), _IO_UD(86), _IO_UD(87), _IO_UD(88), _IO_UD(89),
441
+
PORT_DATA_IO_PU_PD(90), PORT_DATA_IO_PU_PD(91),
442
+
PORT_DATA_IO_PU_PD(92), PORT_DATA_IO_PU_PD(93),
443
+
PORT_DATA_IO_PU_PD(94), PORT_DATA_IO_PU_PD(95),
444
+
PORT_DATA_IO_PU(96), PORT_DATA_IO_PU_PD(97),
445
+
PORT_DATA_IO_PU_PD(98), PORT_DATA_O(99), /*99?*/
440
446
441
-
_IO_UD(90), _IO_UD(91), _IO_UD(92), _IO_UD(93), _IO_UD(94),
442
-
_IO_UD(95), _IO_U_(96), _IO_UD(97), _IO_UD(98), __O___(99), /*99?*/
447
+
PORT_DATA_IO_PD(100), PORT_DATA_IO_PD(101),
448
+
PORT_DATA_IO_PD(102), PORT_DATA_IO_PD(103),
449
+
PORT_DATA_IO_PD(104), PORT_DATA_IO_PD(105),
450
+
PORT_DATA_IO_PU(106), PORT_DATA_IO_PU(107),
451
+
PORT_DATA_IO_PU(108), PORT_DATA_IO_PU(109),
443
452
444
-
_IO__D(100), _IO__D(101), _IO__D(102), _IO__D(103), _IO__D(104),
445
-
_IO__D(105), _IO_U_(106), _IO_U_(107), _IO_U_(108), _IO_U_(109),
453
+
PORT_DATA_IO_PU(110), PORT_DATA_IO_PU(111),
454
+
PORT_DATA_IO_PD(112), PORT_DATA_IO_PD(113),
455
+
PORT_DATA_IO_PU(114), PORT_DATA_IO_PU(115),
456
+
PORT_DATA_IO_PU(116), PORT_DATA_IO_PU(117),
457
+
PORT_DATA_IO_PU(118), PORT_DATA_IO_PU(119),
446
458
447
-
_IO_U_(110), _IO_U_(111), _IO__D(112), _IO__D(113), _IO_U_(114),
448
-
_IO_U_(115), _IO_U_(116), _IO_U_(117), _IO_U_(118), _IO_U_(119),
459
+
PORT_DATA_IO_PU(120), PORT_DATA_IO_PD(121),
460
+
PORT_DATA_IO_PD(122), PORT_DATA_IO_PD(123),
461
+
PORT_DATA_IO_PD(124), PORT_DATA_IO_PD(125),
462
+
PORT_DATA_IO_PD(126), PORT_DATA_IO_PD(127),
463
+
PORT_DATA_IO_PD(128), PORT_DATA_IO_PU_PD(129),
449
464
450
-
_IO_U_(120), _IO__D(121), _IO__D(122), _IO__D(123), _IO__D(124),
451
-
_IO__D(125), _IO__D(126), _IO__D(127), _IO__D(128), _IO_UD(129),
465
+
PORT_DATA_IO_PU_PD(130), PORT_DATA_IO_PU_PD(131),
466
+
PORT_DATA_IO_PU_PD(132), PORT_DATA_IO_PU_PD(133),
467
+
PORT_DATA_IO_PU_PD(134), PORT_DATA_IO_PU_PD(135),
468
+
PORT_DATA_IO_PD(136), PORT_DATA_IO_PD(137),
469
+
PORT_DATA_IO_PD(138), PORT_DATA_IO_PD(139),
452
470
453
-
_IO_UD(130), _IO_UD(131), _IO_UD(132), _IO_UD(133), _IO_UD(134),
454
-
_IO_UD(135), _IO__D(136), _IO__D(137), _IO__D(138), _IO__D(139),
471
+
PORT_DATA_IO_PD(140), PORT_DATA_IO_PD(141),
472
+
PORT_DATA_IO_PD(142), PORT_DATA_IO_PU_PD(143),
473
+
PORT_DATA_IO_PD(144), PORT_DATA_IO_PD(145),
474
+
PORT_DATA_IO_PD(146), PORT_DATA_IO_PD(147),
475
+
PORT_DATA_IO_PD(148), PORT_DATA_IO_PD(149),
455
476
456
-
_IO__D(140), _IO__D(141), _IO__D(142), _IO_UD(143), _IO__D(144),
457
-
_IO__D(145), _IO__D(146), _IO__D(147), _IO__D(148), _IO__D(149),
477
+
PORT_DATA_IO_PD(150), PORT_DATA_IO_PD(151),
478
+
PORT_DATA_IO_PU_PD(152), PORT_DATA_I_PD(153),
479
+
PORT_DATA_IO_PU_PD(154), PORT_DATA_I_PD(155),
480
+
PORT_DATA_IO_PD(156), PORT_DATA_IO_PD(157),
481
+
PORT_DATA_I_PD(158), PORT_DATA_IO_PD(159),
458
482
459
-
_IO__D(150), _IO__D(151), _IO_UD(152), _I___D(153), _IO_UD(154),
460
-
_I___D(155), _IO__D(156), _IO__D(157), _I___D(158), _IO__D(159),
483
+
PORT_DATA_O(160), PORT_DATA_IO_PD(161),
484
+
PORT_DATA_IO_PD(162), PORT_DATA_IO_PD(163),
485
+
PORT_DATA_I_PD(164), PORT_DATA_IO_PD(165),
486
+
PORT_DATA_I_PD(166), PORT_DATA_I_PD(167),
487
+
PORT_DATA_I_PD(168), PORT_DATA_I_PD(169),
461
488
462
-
__O___(160), _IO__D(161), _IO__D(162), _IO__D(163), _I___D(164),
463
-
_IO__D(165), _I___D(166), _I___D(167), _I___D(168), _I___D(169),
489
+
PORT_DATA_I_PD(170), PORT_DATA_O(171),
490
+
PORT_DATA_IO_PU_PD(172), PORT_DATA_IO_PU_PD(173),
491
+
PORT_DATA_IO_PU_PD(174), PORT_DATA_IO_PU_PD(175),
492
+
PORT_DATA_IO_PU_PD(176), PORT_DATA_IO_PU_PD(177),
493
+
PORT_DATA_IO_PU_PD(178), PORT_DATA_O(179),
464
494
465
-
_I___D(170), __O___(171), _IO_UD(172), _IO_UD(173), _IO_UD(174),
466
-
_IO_UD(175), _IO_UD(176), _IO_UD(177), _IO_UD(178), __O___(179),
495
+
PORT_DATA_IO_PU_PD(180), PORT_DATA_IO_PU_PD(181),
496
+
PORT_DATA_IO_PU_PD(182), PORT_DATA_IO_PU_PD(183),
497
+
PORT_DATA_IO_PU_PD(184), PORT_DATA_O(185),
498
+
PORT_DATA_IO_PU_PD(186), PORT_DATA_IO_PU_PD(187),
499
+
PORT_DATA_IO_PU_PD(188), PORT_DATA_IO_PU_PD(189),
467
500
468
-
_IO_UD(180), _IO_UD(181), _IO_UD(182), _IO_UD(183), _IO_UD(184),
469
-
__O___(185), _IO_UD(186), _IO_UD(187), _IO_UD(188), _IO_UD(189),
470
-
471
-
_IO_UD(190),
501
+
PORT_DATA_IO_PU_PD(190),
472
502
473
503
/* IRQ */
474
504
PINMUX_DATA(IRQ0_6_MARK, PORT6_FN0, MSEL1CR_0_0),
···
928
926
PINMUX_DATA(MFIv4_MARK, MSEL4CR_6_1),
929
927
};
930
928
931
-
#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA)
932
-
#define GPIO_PORT_ALL() _190(_GPIO_PORT, , unused)
933
-
#define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK)
934
-
935
929
static struct pinmux_gpio pinmux_gpios[] = {
936
930
937
931
/* PORT */
···
1198
1200
GPIO_FN(SDENC_CPG),
1199
1201
GPIO_FN(SDENC_DV_CLKI),
1200
1202
};
1201
-
1202
-
/* helper for top 4 bits in PORTnCR */
1203
-
#define PCRH(in, in_pd, in_pu, out) \
1204
-
0, (out), (in), 0, \
1205
-
0, 0, 0, 0, \
1206
-
0, 0, (in_pd), 0, \
1207
-
0, 0, (in_pu), 0
1208
-
1209
-
#define PORTCR(nr, reg) \
1210
-
{ PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
1211
-
PCRH(PORT##nr##_IN, PORT##nr##_IN_PD, \
1212
-
PORT##nr##_IN_PU, PORT##nr##_OUT), \
1213
-
PORT##nr##_FN0, PORT##nr##_FN1, PORT##nr##_FN2, \
1214
-
PORT##nr##_FN3, PORT##nr##_FN4, PORT##nr##_FN5, \
1215
-
PORT##nr##_FN6, PORT##nr##_FN7 } \
1216
-
}
1217
1203
1218
1204
static struct pinmux_cfg_reg pinmux_config_regs[] = {
1219
1205
PORTCR(0, 0xE6051000), /* PORT0CR */
+40
-119
arch/arm/mach-shmobile/pfc-sh7377.c
+40
-119
arch/arm/mach-shmobile/pfc-sh7377.c
···
22
22
#include <linux/gpio.h>
23
23
#include <mach/sh7377.h>
24
24
25
-
#define _1(fn, pfx, sfx) fn(pfx, sfx)
26
-
27
-
#define _10(fn, pfx, sfx) \
28
-
_1(fn, pfx##0, sfx), _1(fn, pfx##1, sfx), \
29
-
_1(fn, pfx##2, sfx), _1(fn, pfx##3, sfx), \
30
-
_1(fn, pfx##4, sfx), _1(fn, pfx##5, sfx), \
31
-
_1(fn, pfx##6, sfx), _1(fn, pfx##7, sfx), \
32
-
_1(fn, pfx##8, sfx), _1(fn, pfx##9, sfx)
33
-
34
-
#define _90(fn, pfx, sfx) \
35
-
_10(fn, pfx##1, sfx), _10(fn, pfx##2, sfx), \
36
-
_10(fn, pfx##3, sfx), _10(fn, pfx##4, sfx), \
37
-
_10(fn, pfx##5, sfx), _10(fn, pfx##6, sfx), \
38
-
_10(fn, pfx##7, sfx), _10(fn, pfx##8, sfx), \
39
-
_10(fn, pfx##9, sfx)
40
-
41
-
#define _265(fn, pfx, sfx) \
42
-
_10(fn, pfx, sfx), _90(fn, pfx, sfx), \
43
-
_10(fn, pfx##10, sfx), \
44
-
_1(fn, pfx##110, sfx), _1(fn, pfx##111, sfx), \
45
-
_1(fn, pfx##112, sfx), _1(fn, pfx##113, sfx), \
46
-
_1(fn, pfx##114, sfx), _1(fn, pfx##115, sfx), \
47
-
_1(fn, pfx##116, sfx), _1(fn, pfx##117, sfx), \
48
-
_1(fn, pfx##118, sfx), \
49
-
_1(fn, pfx##128, sfx), _1(fn, pfx##129, sfx), \
50
-
_10(fn, pfx##13, sfx), _10(fn, pfx##14, sfx), \
51
-
_10(fn, pfx##15, sfx), \
52
-
_1(fn, pfx##160, sfx), _1(fn, pfx##161, sfx), \
53
-
_1(fn, pfx##162, sfx), _1(fn, pfx##163, sfx), \
54
-
_1(fn, pfx##164, sfx), \
55
-
_1(fn, pfx##192, sfx), _1(fn, pfx##193, sfx), \
56
-
_1(fn, pfx##194, sfx), _1(fn, pfx##195, sfx), \
57
-
_1(fn, pfx##196, sfx), _1(fn, pfx##197, sfx), \
58
-
_1(fn, pfx##198, sfx), _1(fn, pfx##199, sfx), \
59
-
_10(fn, pfx##20, sfx), _10(fn, pfx##21, sfx), \
60
-
_10(fn, pfx##22, sfx), _10(fn, pfx##23, sfx), \
61
-
_10(fn, pfx##24, sfx), _10(fn, pfx##25, sfx), \
62
-
_1(fn, pfx##260, sfx), _1(fn, pfx##261, sfx), \
63
-
_1(fn, pfx##262, sfx), _1(fn, pfx##263, sfx), \
64
-
_1(fn, pfx##264, sfx)
65
-
66
-
#define _PORT(pfx, sfx) pfx##_##sfx
67
-
#define PORT_265(str) _265(_PORT, PORT, str)
25
+
#define CPU_ALL_PORT(fn, pfx, sfx) \
26
+
PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \
27
+
PORT_10(fn, pfx##10, sfx), \
28
+
PORT_1(fn, pfx##110, sfx), PORT_1(fn, pfx##111, sfx), \
29
+
PORT_1(fn, pfx##112, sfx), PORT_1(fn, pfx##113, sfx), \
30
+
PORT_1(fn, pfx##114, sfx), PORT_1(fn, pfx##115, sfx), \
31
+
PORT_1(fn, pfx##116, sfx), PORT_1(fn, pfx##117, sfx), \
32
+
PORT_1(fn, pfx##118, sfx), \
33
+
PORT_1(fn, pfx##128, sfx), PORT_1(fn, pfx##129, sfx), \
34
+
PORT_10(fn, pfx##13, sfx), PORT_10(fn, pfx##14, sfx), \
35
+
PORT_10(fn, pfx##15, sfx), \
36
+
PORT_1(fn, pfx##160, sfx), PORT_1(fn, pfx##161, sfx), \
37
+
PORT_1(fn, pfx##162, sfx), PORT_1(fn, pfx##163, sfx), \
38
+
PORT_1(fn, pfx##164, sfx), \
39
+
PORT_1(fn, pfx##192, sfx), PORT_1(fn, pfx##193, sfx), \
40
+
PORT_1(fn, pfx##194, sfx), PORT_1(fn, pfx##195, sfx), \
41
+
PORT_1(fn, pfx##196, sfx), PORT_1(fn, pfx##197, sfx), \
42
+
PORT_1(fn, pfx##198, sfx), PORT_1(fn, pfx##199, sfx), \
43
+
PORT_10(fn, pfx##20, sfx), PORT_10(fn, pfx##21, sfx), \
44
+
PORT_10(fn, pfx##22, sfx), PORT_10(fn, pfx##23, sfx), \
45
+
PORT_10(fn, pfx##24, sfx), PORT_10(fn, pfx##25, sfx), \
46
+
PORT_1(fn, pfx##260, sfx), PORT_1(fn, pfx##261, sfx), \
47
+
PORT_1(fn, pfx##262, sfx), PORT_1(fn, pfx##263, sfx), \
48
+
PORT_1(fn, pfx##264, sfx)
68
49
69
50
enum {
70
51
PINMUX_RESERVED = 0,
71
52
72
53
PINMUX_DATA_BEGIN,
73
-
PORT_265(DATA), /* PORT0_DATA -> PORT264_DATA */
54
+
PORT_ALL(DATA), /* PORT0_DATA -> PORT264_DATA */
74
55
PINMUX_DATA_END,
75
56
76
57
PINMUX_INPUT_BEGIN,
77
-
PORT_265(IN), /* PORT0_IN -> PORT264_IN */
58
+
PORT_ALL(IN), /* PORT0_IN -> PORT264_IN */
78
59
PINMUX_INPUT_END,
79
60
80
61
PINMUX_INPUT_PULLUP_BEGIN,
81
-
PORT_265(IN_PU), /* PORT0_IN_PU -> PORT264_IN_PU */
62
+
PORT_ALL(IN_PU), /* PORT0_IN_PU -> PORT264_IN_PU */
82
63
PINMUX_INPUT_PULLUP_END,
83
64
84
65
PINMUX_INPUT_PULLDOWN_BEGIN,
85
-
PORT_265(IN_PD), /* PORT0_IN_PD -> PORT264_IN_PD */
66
+
PORT_ALL(IN_PD), /* PORT0_IN_PD -> PORT264_IN_PD */
86
67
PINMUX_INPUT_PULLDOWN_END,
87
68
88
69
PINMUX_OUTPUT_BEGIN,
89
-
PORT_265(OUT), /* PORT0_OUT -> PORT264_OUT */
70
+
PORT_ALL(OUT), /* PORT0_OUT -> PORT264_OUT */
90
71
PINMUX_OUTPUT_END,
91
72
92
73
PINMUX_FUNCTION_BEGIN,
93
-
PORT_265(FN_IN), /* PORT0_FN_IN -> PORT264_FN_IN */
94
-
PORT_265(FN_OUT), /* PORT0_FN_OUT -> PORT264_FN_OUT */
95
-
PORT_265(FN0), /* PORT0_FN0 -> PORT264_FN0 */
96
-
PORT_265(FN1), /* PORT0_FN1 -> PORT264_FN1 */
97
-
PORT_265(FN2), /* PORT0_FN2 -> PORT264_FN2 */
98
-
PORT_265(FN3), /* PORT0_FN3 -> PORT264_FN3 */
99
-
PORT_265(FN4), /* PORT0_FN4 -> PORT264_FN4 */
100
-
PORT_265(FN5), /* PORT0_FN5 -> PORT264_FN5 */
101
-
PORT_265(FN6), /* PORT0_FN6 -> PORT264_FN6 */
102
-
PORT_265(FN7), /* PORT0_FN7 -> PORT264_FN7 */
74
+
PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT264_FN_IN */
75
+
PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT264_FN_OUT */
76
+
PORT_ALL(FN0), /* PORT0_FN0 -> PORT264_FN0 */
77
+
PORT_ALL(FN1), /* PORT0_FN1 -> PORT264_FN1 */
78
+
PORT_ALL(FN2), /* PORT0_FN2 -> PORT264_FN2 */
79
+
PORT_ALL(FN3), /* PORT0_FN3 -> PORT264_FN3 */
80
+
PORT_ALL(FN4), /* PORT0_FN4 -> PORT264_FN4 */
81
+
PORT_ALL(FN5), /* PORT0_FN5 -> PORT264_FN5 */
82
+
PORT_ALL(FN6), /* PORT0_FN6 -> PORT264_FN6 */
83
+
PORT_ALL(FN7), /* PORT0_FN7 -> PORT264_FN7 */
103
84
104
85
MSELBCR_MSEL17_1, MSELBCR_MSEL17_0,
105
86
MSELBCR_MSEL16_1, MSELBCR_MSEL16_0,
···
340
359
RESETOUTS_MARK,
341
360
PINMUX_MARK_END,
342
361
};
343
-
344
-
#define PORT_DATA_I(nr) \
345
-
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN)
346
-
347
-
#define PORT_DATA_I_PD(nr) \
348
-
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
349
-
PORT##nr##_IN, PORT##nr##_IN_PD)
350
-
351
-
#define PORT_DATA_I_PU(nr) \
352
-
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
353
-
PORT##nr##_IN, PORT##nr##_IN_PU)
354
-
355
-
#define PORT_DATA_I_PU_PD(nr) \
356
-
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
357
-
PORT##nr##_IN, PORT##nr##_IN_PD, \
358
-
PORT##nr##_IN_PU)
359
-
360
-
#define PORT_DATA_O(nr) \
361
-
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
362
-
PORT##nr##_OUT)
363
-
364
-
#define PORT_DATA_IO(nr) \
365
-
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
366
-
PORT##nr##_OUT, PORT##nr##_IN)
367
-
368
-
#define PORT_DATA_IO_PD(nr) \
369
-
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
370
-
PORT##nr##_OUT, PORT##nr##_IN, \
371
-
PORT##nr##_IN_PD)
372
-
373
-
#define PORT_DATA_IO_PU(nr) \
374
-
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
375
-
PORT##nr##_OUT, PORT##nr##_IN, \
376
-
PORT##nr##_IN_PU)
377
-
378
-
#define PORT_DATA_IO_PU_PD(nr) \
379
-
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
380
-
PORT##nr##_OUT, PORT##nr##_IN, \
381
-
PORT##nr##_IN_PD, PORT##nr##_IN_PU)
382
362
383
363
static pinmux_enum_t pinmux_data[] = {
384
364
/* specify valid pin states for each pin in GPIO mode */
···
1020
1078
PINMUX_DATA(RESETOUTS_MARK, PORT264_FN1),
1021
1079
};
1022
1080
1023
-
#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA)
1024
-
#define GPIO_PORT_265() _265(_GPIO_PORT, , unused)
1025
-
#define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK)
1026
-
1027
1081
static struct pinmux_gpio pinmux_gpios[] = {
1028
1082
/* 55-1 -> 55-5 (GPIO) */
1029
-
GPIO_PORT_265(),
1083
+
GPIO_PORT_ALL(),
1030
1084
1031
1085
/* Special Pull-up / Pull-down Functions */
1032
1086
GPIO_FN(PORT66_KEYIN0_PU), GPIO_FN(PORT67_KEYIN1_PU),
···
1299
1361
GPIO_FN(SDHICMD1), GPIO_FN(TRST3),
1300
1362
GPIO_FN(RESETOUTS),
1301
1363
};
1302
-
1303
-
/* helper for top 4 bits in PORTnCR */
1304
-
#define PCRH(in, in_pd, in_pu, out) \
1305
-
0, (out), (in), 0, \
1306
-
0, 0, 0, 0, \
1307
-
0, 0, (in_pd), 0, \
1308
-
0, 0, (in_pu), 0
1309
-
1310
-
#define PORTCR(nr, reg) \
1311
-
{ PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
1312
-
PCRH(PORT##nr##_IN, PORT##nr##_IN_PD, \
1313
-
PORT##nr##_IN_PU, PORT##nr##_OUT), \
1314
-
PORT##nr##_FN0, PORT##nr##_FN1, \
1315
-
PORT##nr##_FN2, PORT##nr##_FN3, \
1316
-
PORT##nr##_FN4, PORT##nr##_FN5, \
1317
-
PORT##nr##_FN6, PORT##nr##_FN7 } \
1318
-
}
1319
1364
1320
1365
static struct pinmux_cfg_reg pinmux_config_regs[] = {
1321
1366
PORTCR(0, 0xe6050000), /* PORT0CR */
+80
-113
arch/arm/mach-shmobile/pfc-sh73a0.c
+80
-113
arch/arm/mach-shmobile/pfc-sh73a0.c
···
24
24
#include <mach/sh73a0.h>
25
25
#include <mach/irqs.h>
26
26
27
-
#define _1(fn, pfx, sfx) fn(pfx, sfx)
28
-
29
-
#define _10(fn, pfx, sfx) \
30
-
_1(fn, pfx##0, sfx), _1(fn, pfx##1, sfx), \
31
-
_1(fn, pfx##2, sfx), _1(fn, pfx##3, sfx), \
32
-
_1(fn, pfx##4, sfx), _1(fn, pfx##5, sfx), \
33
-
_1(fn, pfx##6, sfx), _1(fn, pfx##7, sfx), \
34
-
_1(fn, pfx##8, sfx), _1(fn, pfx##9, sfx)
35
-
36
-
#define _310(fn, pfx, sfx) \
37
-
_10(fn, pfx, sfx), _10(fn, pfx##1, sfx), \
38
-
_10(fn, pfx##2, sfx), _10(fn, pfx##3, sfx), \
39
-
_10(fn, pfx##4, sfx), _10(fn, pfx##5, sfx), \
40
-
_10(fn, pfx##6, sfx), _10(fn, pfx##7, sfx), \
41
-
_10(fn, pfx##8, sfx), _10(fn, pfx##9, sfx), \
42
-
_10(fn, pfx##10, sfx), \
43
-
_1(fn, pfx##110, sfx), _1(fn, pfx##111, sfx), \
44
-
_1(fn, pfx##112, sfx), _1(fn, pfx##113, sfx), \
45
-
_1(fn, pfx##114, sfx), _1(fn, pfx##115, sfx), \
46
-
_1(fn, pfx##116, sfx), _1(fn, pfx##117, sfx), \
47
-
_1(fn, pfx##118, sfx), \
48
-
_1(fn, pfx##128, sfx), _1(fn, pfx##129, sfx), \
49
-
_10(fn, pfx##13, sfx), _10(fn, pfx##14, sfx), \
50
-
_10(fn, pfx##15, sfx), \
51
-
_1(fn, pfx##160, sfx), _1(fn, pfx##161, sfx), \
52
-
_1(fn, pfx##162, sfx), _1(fn, pfx##163, sfx), \
53
-
_1(fn, pfx##164, sfx), \
54
-
_1(fn, pfx##192, sfx), _1(fn, pfx##193, sfx), \
55
-
_1(fn, pfx##194, sfx), _1(fn, pfx##195, sfx), \
56
-
_1(fn, pfx##196, sfx), _1(fn, pfx##197, sfx), \
57
-
_1(fn, pfx##198, sfx), _1(fn, pfx##199, sfx), \
58
-
_10(fn, pfx##20, sfx), _10(fn, pfx##21, sfx), \
59
-
_10(fn, pfx##22, sfx), _10(fn, pfx##23, sfx), \
60
-
_10(fn, pfx##24, sfx), _10(fn, pfx##25, sfx), \
61
-
_10(fn, pfx##26, sfx), _10(fn, pfx##27, sfx), \
62
-
_1(fn, pfx##280, sfx), _1(fn, pfx##281, sfx), \
63
-
_1(fn, pfx##282, sfx), \
64
-
_1(fn, pfx##288, sfx), _1(fn, pfx##289, sfx), \
65
-
_10(fn, pfx##29, sfx), _10(fn, pfx##30, sfx)
66
-
67
-
#define _PORT(pfx, sfx) pfx##_##sfx
68
-
#define PORT_310(str) _310(_PORT, PORT, str)
27
+
#define CPU_ALL_PORT(fn, pfx, sfx) \
28
+
PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
29
+
PORT_10(fn, pfx##2, sfx), PORT_10(fn, pfx##3, sfx), \
30
+
PORT_10(fn, pfx##4, sfx), PORT_10(fn, pfx##5, sfx), \
31
+
PORT_10(fn, pfx##6, sfx), PORT_10(fn, pfx##7, sfx), \
32
+
PORT_10(fn, pfx##8, sfx), PORT_10(fn, pfx##9, sfx), \
33
+
PORT_10(fn, pfx##10, sfx), \
34
+
PORT_1(fn, pfx##110, sfx), PORT_1(fn, pfx##111, sfx), \
35
+
PORT_1(fn, pfx##112, sfx), PORT_1(fn, pfx##113, sfx), \
36
+
PORT_1(fn, pfx##114, sfx), PORT_1(fn, pfx##115, sfx), \
37
+
PORT_1(fn, pfx##116, sfx), PORT_1(fn, pfx##117, sfx), \
38
+
PORT_1(fn, pfx##118, sfx), \
39
+
PORT_1(fn, pfx##128, sfx), PORT_1(fn, pfx##129, sfx), \
40
+
PORT_10(fn, pfx##13, sfx), PORT_10(fn, pfx##14, sfx), \
41
+
PORT_10(fn, pfx##15, sfx), \
42
+
PORT_1(fn, pfx##160, sfx), PORT_1(fn, pfx##161, sfx), \
43
+
PORT_1(fn, pfx##162, sfx), PORT_1(fn, pfx##163, sfx), \
44
+
PORT_1(fn, pfx##164, sfx), \
45
+
PORT_1(fn, pfx##192, sfx), PORT_1(fn, pfx##193, sfx), \
46
+
PORT_1(fn, pfx##194, sfx), PORT_1(fn, pfx##195, sfx), \
47
+
PORT_1(fn, pfx##196, sfx), PORT_1(fn, pfx##197, sfx), \
48
+
PORT_1(fn, pfx##198, sfx), PORT_1(fn, pfx##199, sfx), \
49
+
PORT_10(fn, pfx##20, sfx), PORT_10(fn, pfx##21, sfx), \
50
+
PORT_10(fn, pfx##22, sfx), PORT_10(fn, pfx##23, sfx), \
51
+
PORT_10(fn, pfx##24, sfx), PORT_10(fn, pfx##25, sfx), \
52
+
PORT_10(fn, pfx##26, sfx), PORT_10(fn, pfx##27, sfx), \
53
+
PORT_1(fn, pfx##280, sfx), PORT_1(fn, pfx##281, sfx), \
54
+
PORT_1(fn, pfx##282, sfx), \
55
+
PORT_1(fn, pfx##288, sfx), PORT_1(fn, pfx##289, sfx), \
56
+
PORT_10(fn, pfx##29, sfx), PORT_10(fn, pfx##30, sfx)
69
57
70
58
enum {
71
59
PINMUX_RESERVED = 0,
72
60
73
61
PINMUX_DATA_BEGIN,
74
-
PORT_310(DATA), /* PORT0_DATA -> PORT309_DATA */
62
+
PORT_ALL(DATA), /* PORT0_DATA -> PORT309_DATA */
75
63
PINMUX_DATA_END,
76
64
77
65
PINMUX_INPUT_BEGIN,
78
-
PORT_310(IN), /* PORT0_IN -> PORT309_IN */
66
+
PORT_ALL(IN), /* PORT0_IN -> PORT309_IN */
79
67
PINMUX_INPUT_END,
80
68
81
69
PINMUX_INPUT_PULLUP_BEGIN,
82
-
PORT_310(IN_PU), /* PORT0_IN_PU -> PORT309_IN_PU */
70
+
PORT_ALL(IN_PU), /* PORT0_IN_PU -> PORT309_IN_PU */
83
71
PINMUX_INPUT_PULLUP_END,
84
72
85
73
PINMUX_INPUT_PULLDOWN_BEGIN,
86
-
PORT_310(IN_PD), /* PORT0_IN_PD -> PORT309_IN_PD */
74
+
PORT_ALL(IN_PD), /* PORT0_IN_PD -> PORT309_IN_PD */
87
75
PINMUX_INPUT_PULLDOWN_END,
88
76
89
77
PINMUX_OUTPUT_BEGIN,
90
-
PORT_310(OUT), /* PORT0_OUT -> PORT309_OUT */
78
+
PORT_ALL(OUT), /* PORT0_OUT -> PORT309_OUT */
91
79
PINMUX_OUTPUT_END,
92
80
93
81
PINMUX_FUNCTION_BEGIN,
94
-
PORT_310(FN_IN), /* PORT0_FN_IN -> PORT309_FN_IN */
95
-
PORT_310(FN_OUT), /* PORT0_FN_OUT -> PORT309_FN_OUT */
96
-
PORT_310(FN0), /* PORT0_FN0 -> PORT309_FN0 */
97
-
PORT_310(FN1), /* PORT0_FN1 -> PORT309_FN1 */
98
-
PORT_310(FN2), /* PORT0_FN2 -> PORT309_FN2 */
99
-
PORT_310(FN3), /* PORT0_FN3 -> PORT309_FN3 */
100
-
PORT_310(FN4), /* PORT0_FN4 -> PORT309_FN4 */
101
-
PORT_310(FN5), /* PORT0_FN5 -> PORT309_FN5 */
102
-
PORT_310(FN6), /* PORT0_FN6 -> PORT309_FN6 */
103
-
PORT_310(FN7), /* PORT0_FN7 -> PORT309_FN7 */
82
+
PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT309_FN_IN */
83
+
PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT309_FN_OUT */
84
+
PORT_ALL(FN0), /* PORT0_FN0 -> PORT309_FN0 */
85
+
PORT_ALL(FN1), /* PORT0_FN1 -> PORT309_FN1 */
86
+
PORT_ALL(FN2), /* PORT0_FN2 -> PORT309_FN2 */
87
+
PORT_ALL(FN3), /* PORT0_FN3 -> PORT309_FN3 */
88
+
PORT_ALL(FN4), /* PORT0_FN4 -> PORT309_FN4 */
89
+
PORT_ALL(FN5), /* PORT0_FN5 -> PORT309_FN5 */
90
+
PORT_ALL(FN6), /* PORT0_FN6 -> PORT309_FN6 */
91
+
PORT_ALL(FN7), /* PORT0_FN7 -> PORT309_FN7 */
104
92
105
93
MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
106
94
MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
···
496
508
SDHICMD2_PU_MARK,
497
509
MMCCMD0_PU_MARK,
498
510
MMCCMD1_PU_MARK,
511
+
MMCD0_0_PU_MARK,
512
+
MMCD0_1_PU_MARK,
513
+
MMCD0_2_PU_MARK,
514
+
MMCD0_3_PU_MARK,
515
+
MMCD0_4_PU_MARK,
516
+
MMCD0_5_PU_MARK,
517
+
MMCD0_6_PU_MARK,
518
+
MMCD0_7_PU_MARK,
499
519
FSIBISLD_PU_MARK,
500
520
FSIACK_PU_MARK,
501
521
FSIAILR_PU_MARK,
···
512
516
513
517
PINMUX_MARK_END,
514
518
};
515
-
516
-
#define PORT_DATA_I(nr) \
517
-
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN)
518
-
519
-
#define PORT_DATA_I_PD(nr) \
520
-
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
521
-
PORT##nr##_IN, PORT##nr##_IN_PD)
522
-
523
-
#define PORT_DATA_I_PU(nr) \
524
-
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
525
-
PORT##nr##_IN, PORT##nr##_IN_PU)
526
-
527
-
#define PORT_DATA_I_PU_PD(nr) \
528
-
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
529
-
PORT##nr##_IN, PORT##nr##_IN_PD, \
530
-
PORT##nr##_IN_PU)
531
-
532
-
#define PORT_DATA_O(nr) \
533
-
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
534
-
PORT##nr##_OUT)
535
-
536
-
#define PORT_DATA_IO(nr) \
537
-
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
538
-
PORT##nr##_OUT, PORT##nr##_IN)
539
-
540
-
#define PORT_DATA_IO_PD(nr) \
541
-
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
542
-
PORT##nr##_OUT, PORT##nr##_IN, \
543
-
PORT##nr##_IN_PD)
544
-
545
-
#define PORT_DATA_IO_PU(nr) \
546
-
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
547
-
PORT##nr##_OUT, PORT##nr##_IN, \
548
-
PORT##nr##_IN_PU)
549
-
550
-
#define PORT_DATA_IO_PU_PD(nr) \
551
-
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
552
-
PORT##nr##_OUT, PORT##nr##_IN, \
553
-
PORT##nr##_IN_PD, PORT##nr##_IN_PU)
554
519
555
520
static pinmux_enum_t pinmux_data[] = {
556
521
/* specify valid pin states for each pin in GPIO mode */
···
1518
1561
MSEL4CR_MSEL15_0),
1519
1562
PINMUX_DATA(MMCCMD1_PU_MARK, PORT297_FN2, PORT297_IN_PU,
1520
1563
MSEL4CR_MSEL15_1),
1564
+
1565
+
PINMUX_DATA(MMCD0_0_PU_MARK,
1566
+
PORT271_FN1, PORT271_IN_PU, MSEL4CR_MSEL15_0),
1567
+
PINMUX_DATA(MMCD0_1_PU_MARK,
1568
+
PORT272_FN1, PORT272_IN_PU, MSEL4CR_MSEL15_0),
1569
+
PINMUX_DATA(MMCD0_2_PU_MARK,
1570
+
PORT273_FN1, PORT273_IN_PU, MSEL4CR_MSEL15_0),
1571
+
PINMUX_DATA(MMCD0_3_PU_MARK,
1572
+
PORT274_FN1, PORT274_IN_PU, MSEL4CR_MSEL15_0),
1573
+
PINMUX_DATA(MMCD0_4_PU_MARK,
1574
+
PORT275_FN1, PORT275_IN_PU, MSEL4CR_MSEL15_0),
1575
+
PINMUX_DATA(MMCD0_5_PU_MARK,
1576
+
PORT276_FN1, PORT276_IN_PU, MSEL4CR_MSEL15_0),
1577
+
PINMUX_DATA(MMCD0_6_PU_MARK,
1578
+
PORT277_FN1, PORT277_IN_PU, MSEL4CR_MSEL15_0),
1579
+
PINMUX_DATA(MMCD0_7_PU_MARK,
1580
+
PORT278_FN1, PORT278_IN_PU, MSEL4CR_MSEL15_0),
1581
+
1521
1582
PINMUX_DATA(FSIBISLD_PU_MARK, PORT39_FN1, PORT39_IN_PU),
1522
1583
PINMUX_DATA(FSIACK_PU_MARK, PORT49_FN1, PORT49_IN_PU),
1523
1584
PINMUX_DATA(FSIAILR_PU_MARK, PORT50_FN5, PORT50_IN_PU),
···
1543
1568
PINMUX_DATA(FSIAISLD_PU_MARK, PORT55_FN1, PORT55_IN_PU),
1544
1569
};
1545
1570
1546
-
#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA)
1547
-
#define GPIO_PORT_310() _310(_GPIO_PORT, , unused)
1548
-
#define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK)
1549
-
1550
1571
static struct pinmux_gpio pinmux_gpios[] = {
1551
-
GPIO_PORT_310(),
1572
+
GPIO_PORT_ALL(),
1552
1573
1553
1574
/* Table 25-1 (Functions 0-7) */
1554
1575
GPIO_FN(VBUS_0),
···
2207
2236
GPIO_FN(SDHICMD2_PU),
2208
2237
GPIO_FN(MMCCMD0_PU),
2209
2238
GPIO_FN(MMCCMD1_PU),
2239
+
GPIO_FN(MMCD0_0_PU),
2240
+
GPIO_FN(MMCD0_1_PU),
2241
+
GPIO_FN(MMCD0_2_PU),
2242
+
GPIO_FN(MMCD0_3_PU),
2243
+
GPIO_FN(MMCD0_4_PU),
2244
+
GPIO_FN(MMCD0_5_PU),
2245
+
GPIO_FN(MMCD0_6_PU),
2246
+
GPIO_FN(MMCD0_7_PU),
2210
2247
GPIO_FN(FSIACK_PU),
2211
2248
GPIO_FN(FSIAILR_PU),
2212
2249
GPIO_FN(FSIAIBT_PU),
2213
2250
GPIO_FN(FSIAISLD_PU),
2214
2251
};
2215
-
2216
-
#define PORTCR(nr, reg) \
2217
-
{ PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
2218
-
0, \
2219
-
/*0001*/ PORT##nr##_OUT , \
2220
-
/*0010*/ PORT##nr##_IN , 0, 0, 0, 0, 0, 0, 0, \
2221
-
/*1010*/ PORT##nr##_IN_PD, 0, 0, 0, \
2222
-
/*1110*/ PORT##nr##_IN_PU, 0, \
2223
-
PORT##nr##_FN0, PORT##nr##_FN1, PORT##nr##_FN2, \
2224
-
PORT##nr##_FN3, PORT##nr##_FN4, PORT##nr##_FN5, \
2225
-
PORT##nr##_FN6, PORT##nr##_FN7, 0, 0, 0, 0, 0, 0, 0, 0 } \
2226
-
}
2227
2252
2228
2253
static struct pinmux_cfg_reg pinmux_config_regs[] = {
2229
2254
PORTCR(0, 0xe6050000), /* PORT0CR */
+5
-9
arch/arm/mach-shmobile/pm-sh7372.c
+5
-9
arch/arm/mach-shmobile/pm-sh7372.c
···
402
402
403
403
#ifdef CONFIG_CPU_IDLE
404
404
405
-
static void sh7372_cpuidle_setup(struct cpuidle_device *dev)
405
+
static void sh7372_cpuidle_setup(struct cpuidle_driver *drv)
406
406
{
407
-
struct cpuidle_state *state;
408
-
int i = dev->state_count;
407
+
struct cpuidle_state *state = &drv->states[drv->state_count];
409
408
410
-
state = &dev->states[i];
411
409
snprintf(state->name, CPUIDLE_NAME_LEN, "C2");
412
410
strncpy(state->desc, "Core Standby Mode", CPUIDLE_DESC_LEN);
413
411
state->exit_latency = 10;
414
412
state->target_residency = 20 + 10;
415
-
state->power_usage = 1; /* perhaps not */
416
-
state->flags = 0;
417
-
state->flags |= CPUIDLE_FLAG_TIME_VALID;
418
-
shmobile_cpuidle_modes[i] = sh7372_enter_core_standby;
413
+
state->flags = CPUIDLE_FLAG_TIME_VALID;
414
+
shmobile_cpuidle_modes[drv->state_count] = sh7372_enter_core_standby;
419
415
420
-
dev->state_count = i + 1;
416
+
drv->state_count++;
421
417
}
422
418
423
419
static void sh7372_cpuidle_init(void)
+76
include/linux/sh_pfc.h
+76
include/linux/sh_pfc.h
···
104
104
int register_pinmux(struct pinmux_info *pip);
105
105
int unregister_pinmux(struct pinmux_info *pip);
106
106
107
+
/* helper macro for port */
108
+
#define PORT_1(fn, pfx, sfx) fn(pfx, sfx)
109
+
110
+
#define PORT_10(fn, pfx, sfx) \
111
+
PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \
112
+
PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \
113
+
PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx), \
114
+
PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \
115
+
PORT_1(fn, pfx##8, sfx), PORT_1(fn, pfx##9, sfx)
116
+
117
+
#define PORT_90(fn, pfx, sfx) \
118
+
PORT_10(fn, pfx##1, sfx), PORT_10(fn, pfx##2, sfx), \
119
+
PORT_10(fn, pfx##3, sfx), PORT_10(fn, pfx##4, sfx), \
120
+
PORT_10(fn, pfx##5, sfx), PORT_10(fn, pfx##6, sfx), \
121
+
PORT_10(fn, pfx##7, sfx), PORT_10(fn, pfx##8, sfx), \
122
+
PORT_10(fn, pfx##9, sfx)
123
+
124
+
#define _PORT_ALL(pfx, sfx) pfx##_##sfx
125
+
#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA)
126
+
#define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str)
127
+
#define GPIO_PORT_ALL() CPU_ALL_PORT(_GPIO_PORT, , unused)
128
+
#define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK)
129
+
130
+
/* helper macro for pinmux_enum_t */
131
+
#define PORT_DATA_I(nr) \
132
+
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_IN)
133
+
134
+
#define PORT_DATA_I_PD(nr) \
135
+
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
136
+
PORT##nr##_IN, PORT##nr##_IN_PD)
137
+
138
+
#define PORT_DATA_I_PU(nr) \
139
+
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
140
+
PORT##nr##_IN, PORT##nr##_IN_PU)
141
+
142
+
#define PORT_DATA_I_PU_PD(nr) \
143
+
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, \
144
+
PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)
145
+
146
+
#define PORT_DATA_O(nr) \
147
+
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT)
148
+
149
+
#define PORT_DATA_IO(nr) \
150
+
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
151
+
PORT##nr##_IN)
152
+
153
+
#define PORT_DATA_IO_PD(nr) \
154
+
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
155
+
PORT##nr##_IN, PORT##nr##_IN_PD)
156
+
157
+
#define PORT_DATA_IO_PU(nr) \
158
+
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
159
+
PORT##nr##_IN, PORT##nr##_IN_PU)
160
+
161
+
#define PORT_DATA_IO_PU_PD(nr) \
162
+
PINMUX_DATA(PORT##nr##_DATA, PORT##nr##_FN0, PORT##nr##_OUT, \
163
+
PORT##nr##_IN, PORT##nr##_IN_PD, PORT##nr##_IN_PU)
164
+
165
+
/* helper macro for top 4 bits in PORTnCR */
166
+
#define _PCRH(in, in_pd, in_pu, out) \
167
+
0, (out), (in), 0, \
168
+
0, 0, 0, 0, \
169
+
0, 0, (in_pd), 0, \
170
+
0, 0, (in_pu), 0
171
+
172
+
#define PORTCR(nr, reg) \
173
+
{ \
174
+
PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
175
+
_PCRH(PORT##nr##_IN, PORT##nr##_IN_PD, \
176
+
PORT##nr##_IN_PU, PORT##nr##_OUT), \
177
+
PORT##nr##_FN0, PORT##nr##_FN1, \
178
+
PORT##nr##_FN2, PORT##nr##_FN3, \
179
+
PORT##nr##_FN4, PORT##nr##_FN5, \
180
+
PORT##nr##_FN6, PORT##nr##_FN7 } \
181
+
}
182
+
107
183
#endif /* __SH_PFC_H */